Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The MIPS bits for 3.8.  This also includes a bunch fixes that were
  sitting in the linux-mips.org git tree for a long time.  This pull
  request contains updates to several OCTEON drivers and the board
  support code for BCM47XX, BCM63XX, XLP, XLR, XLS, lantiq, Loongson1B,
  updates to the SSB bus support, MIPS kexec code and adds support for
  kdump.

  When pulling this, there are two expected merge conflicts in
  include/linux/bcma/bcma_driver_chipcommon.h which are trivial to
  resolve, just remove the conflict markers and keep both alternatives."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (90 commits)
  MIPS: PMC-Sierra Yosemite: Remove support.
  VIDEO: Newport Fix console crashes
  MIPS: wrppmc: Fix build of PCI code.
  MIPS: IP22/IP28: Fix build of EISA code.
  MIPS: RB532: Fix build of prom code.
  MIPS: PowerTV: Fix build.
  MIPS: IP27: Correct fucked grammar in ops-bridge.c
  MIPS: Highmem: Fix build error if CONFIG_DEBUG_HIGHMEM is disabled
  MIPS: Fix potencial corruption
  MIPS: Fix for warning from FPU emulation code
  MIPS: Handle COP3 Unusable exception as COP1X for FP emulation
  MIPS: Fix poweroff failure when HOTPLUG_CPU configured.
  MIPS: MT: Fix build with CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
  MIPS: Remove unused smvp.h
  MIPS/EDAC: Improve OCTEON EDAC support.
  MIPS: OCTEON: Add definitions for OCTEON memory contoller registers.
  MIPS: OCTEON: Add OCTEON family definitions to octeon-model.h
  ata: pata_octeon_cf: Use correct byte order for DMA in when built little-endian.
  MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.
  MIPS: Remove usage of CEVT_R4K_LIB config option.
  ...

1 files changed, 76 insertions, 5 deletions

diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c
index dc96dd8ebff2..e461ad25fda4 100644
--- a/drivers/bcma/driver_chipcommon.c
+++ b/drivers/bcma/driver_chipcommon.c
@@ -114,6 +114,8 @@ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
         if (cc->early_setup_done)
                 return;
 
+        spin_lock_init(&cc->gpio_lock);
+
         if (cc->core->id.rev >= 11)
                 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
         cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
@@ -202,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
 
 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
 {
-        return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
+        unsigned long flags;
+        u32 res;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
 }
 
 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
 {
-        return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
+        unsigned long flags;
+        u32 res;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
 }
 
+/*
+ * If the bit is set to 0, chipcommon controlls this GPIO,
+ * if the bit is set to 1, it is used by some part of the chip and not our code.
+ */
 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
 {
-        return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
+        unsigned long flags;
+        u32 res;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
 }
 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
 
 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
 {
-        return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
+        unsigned long flags;
+        u32 res;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
 }
 
 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
 {
-        return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
+        unsigned long flags;
+        u32 res;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
+}
+
+u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res;
+
+        if (cc->core->id.rev < 20)
+                return 0;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
+}
+
+u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res;
+
+        if (cc->core->id.rev < 20)
+                return 0;
+
+        spin_lock_irqsave(&cc->gpio_lock, flags);
+        res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
+        spin_unlock_irqrestore(&cc->gpio_lock, flags);
+
+        return res;
 }
 
 #ifdef CONFIG_BCMA_DRIVER_MIPS