aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ata/pata_cs5530.c
diff options
context:
space:
mode:
authorJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
committerJeff Garzik <jeff@garzik.org>2006-08-29 18:12:40 -0400
commit669a5db411d85a14f86cd92bc16bf7ab5b8aa235 (patch)
tree8d4f9d63e18185695a4d97e1a3fa4e18b61c7345 /drivers/ata/pata_cs5530.c
parentb01e86fee6c821e4e003fd4e9f65453ac478a58e (diff)
[libata] Add a bunch of PATA drivers.
The vast majority of drivers and changes are from Alan Cox. Albert Lee contributed and maintains pata_pdc2027x. Adrian Bunk, Andrew Morton, and Tejun Heo contributed various minor fixes and updates. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_cs5530.c')
-rw-r--r--drivers/ata/pata_cs5530.c387
1 files changed, 387 insertions, 0 deletions
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c
new file mode 100644
index 000000000000..f3d8a3bc1e78
--- /dev/null
+++ b/drivers/ata/pata_cs5530.c
@@ -0,0 +1,387 @@
1/*
2 * pata-cs5530.c - CS5530 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon cs5530.c by Mark Lord.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * Loosely based on the piix & svwks drivers.
22 *
23 * Documentation:
24 * Available from AMD web site.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <scsi/scsi_host.h>
34#include <linux/libata.h>
35#include <linux/dmi.h>
36
37#define DRV_NAME "pata_cs5530"
38#define DRV_VERSION "0.6"
39
40/**
41 * cs5530_set_piomode - PIO setup
42 * @ap: ATA interface
43 * @adev: device on the interface
44 *
45 * Set our PIO requirements. This is fairly simple on the CS5530
46 * chips.
47 */
48
49static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
50{
51 static const unsigned int cs5530_pio_timings[2][5] = {
52 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
53 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
54 };
55 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
56 u32 tuning;
57 int format;
58
59 /* Find out which table to use */
60 tuning = inl(base + 0x04);
61 format = (tuning & 0x80000000UL) ? 1 : 0;
62
63 /* Now load the right timing register */
64 if (adev->devno)
65 base += 0x08;
66
67 outl(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
68}
69
70/**
71 * cs5530_set_dmamode - DMA timing setup
72 * @ap: ATA interface
73 * @adev: Device being configured
74 *
75 * We cannot mix MWDMA and UDMA without reloading timings each switch
76 * master to slave. We track the last DMA setup in order to minimise
77 * reloads.
78 */
79
80static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
81{
82 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no;
83 u32 tuning, timing = 0;
84 u8 reg;
85
86 /* Find out which table to use */
87 tuning = inl(base + 0x04);
88
89 switch(adev->dma_mode) {
90 case XFER_UDMA_0:
91 timing = 0x00921250;break;
92 case XFER_UDMA_1:
93 timing = 0x00911140;break;
94 case XFER_UDMA_2:
95 timing = 0x00911030;break;
96 case XFER_MW_DMA_0:
97 timing = 0x00077771;break;
98 case XFER_MW_DMA_1:
99 timing = 0x00012121;break;
100 case XFER_MW_DMA_2:
101 timing = 0x00002020;break;
102 default:
103 BUG();
104 }
105 /* Merge in the PIO format bit */
106 timing |= (tuning & 0x80000000UL);
107 if (adev->devno == 0) /* Master */
108 outl(timing, base + 0x04);
109 else {
110 if (timing & 0x00100000)
111 tuning |= 0x00100000; /* UDMA for both */
112 else
113 tuning &= ~0x00100000; /* MWDMA for both */
114 outl(tuning, base + 0x04);
115 outl(timing, base + 0x0C);
116 }
117
118 /* Set the DMA capable bit in the BMDMA area */
119 reg = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
120 reg |= (1 << (5 + adev->devno));
121 outb(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
122
123 /* Remember the last DMA setup we did */
124
125 ap->private_data = adev;
126}
127
128/**
129 * cs5530_qc_issue_prot - command issue
130 * @qc: command pending
131 *
132 * Called when the libata layer is about to issue a command. We wrap
133 * this interface so that we can load the correct ATA timings if
134 * neccessary. Specifically we have a problem that there is only
135 * one MWDMA/UDMA bit.
136 */
137
138static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
139{
140 struct ata_port *ap = qc->ap;
141 struct ata_device *adev = qc->dev;
142 struct ata_device *prev = ap->private_data;
143
144 /* See if the DMA settings could be wrong */
145 if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
146 /* Maybe, but do the channels match MWDMA/UDMA ? */
147 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
148 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
149 /* Switch the mode bits */
150 cs5530_set_dmamode(ap, adev);
151 }
152
153 return ata_qc_issue_prot(qc);
154}
155
156static int cs5530_pre_reset(struct ata_port *ap)
157{
158 ap->cbl = ATA_CBL_PATA40;
159 return ata_std_prereset(ap);
160}
161
162static void cs5530_error_handler(struct ata_port *ap)
163{
164 return ata_bmdma_drive_eh(ap, cs5530_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
165}
166
167
168static struct scsi_host_template cs5530_sht = {
169 .module = THIS_MODULE,
170 .name = DRV_NAME,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .max_sectors = ATA_MAX_SECTORS,
177 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
178 .emulated = ATA_SHT_EMULATED,
179 .use_clustering = ATA_SHT_USE_CLUSTERING,
180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config,
183 .bios_param = ata_std_bios_param,
184};
185
186static struct ata_port_operations cs5530_port_ops = {
187 .port_disable = ata_port_disable,
188 .set_piomode = cs5530_set_piomode,
189 .set_dmamode = cs5530_set_dmamode,
190 .mode_filter = ata_pci_default_filter,
191
192 .tf_load = ata_tf_load,
193 .tf_read = ata_tf_read,
194 .check_status = ata_check_status,
195 .exec_command = ata_exec_command,
196 .dev_select = ata_std_dev_select,
197
198 .bmdma_setup = ata_bmdma_setup,
199 .bmdma_start = ata_bmdma_start,
200 .bmdma_stop = ata_bmdma_stop,
201 .bmdma_status = ata_bmdma_status,
202
203 .freeze = ata_bmdma_freeze,
204 .thaw = ata_bmdma_thaw,
205 .error_handler = cs5530_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
207
208 .qc_prep = ata_qc_prep,
209 .qc_issue = cs5530_qc_issue_prot,
210 .eng_timeout = ata_eng_timeout,
211 .data_xfer = ata_pio_data_xfer,
212
213 .irq_handler = ata_interrupt,
214 .irq_clear = ata_bmdma_irq_clear,
215
216 .port_start = ata_port_start,
217 .port_stop = ata_port_stop,
218 .host_stop = ata_host_stop
219};
220
221static struct dmi_system_id palmax_dmi_table[] = {
222 {
223 .ident = "Palmax PD1100",
224 .matches = {
225 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
226 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
227 },
228 },
229 { }
230};
231
232static int cs5530_is_palmax(void)
233{
234 if (dmi_check_system(palmax_dmi_table)) {
235 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
236 return 1;
237 }
238 return 0;
239}
240
241/**
242 * cs5530_init_one - Initialise a CS5530
243 * @dev: PCI device
244 * @id: Entry in match table
245 *
246 * Install a driver for the newly found CS5530 companion chip. Most of
247 * this is just housekeeping. We have to set the chip up correctly and
248 * turn off various bits of emulation magic.
249 */
250
251static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
252{
253 int compiler_warning_pointless_fix;
254 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
255 static struct ata_port_info info = {
256 .sht = &cs5530_sht,
257 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
258 .pio_mask = 0x1f,
259 .mwdma_mask = 0x07,
260 .udma_mask = 0x07,
261 .port_ops = &cs5530_port_ops
262 };
263 /* The docking connector doesn't do UDMA, and it seems not MWDMA */
264 static struct ata_port_info info_palmax_secondary = {
265 .sht = &cs5530_sht,
266 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
267 .pio_mask = 0x1f,
268 .port_ops = &cs5530_port_ops
269 };
270 static struct ata_port_info *port_info[2] = { &info, &info };
271
272 dev = NULL;
273 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
274 switch (dev->device) {
275 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
276 master_0 = pci_dev_get(dev);
277 break;
278 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
279 cs5530_0 = pci_dev_get(dev);
280 break;
281 }
282 }
283 if (!master_0) {
284 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
285 goto fail_put;
286 }
287 if (!cs5530_0) {
288 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
289 goto fail_put;
290 }
291
292 pci_set_master(cs5530_0);
293 compiler_warning_pointless_fix = pci_set_mwi(cs5530_0);
294
295 /*
296 * Set PCI CacheLineSize to 16-bytes:
297 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
298 *
299 * Note: This value is constant because the 5530 is only a Geode companion
300 */
301
302 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
303
304 /*
305 * Disable trapping of UDMA register accesses (Win98 hack):
306 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
307 */
308
309 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
310
311 /*
312 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
313 * The other settings are what is necessary to get the register
314 * into a sane state for IDE DMA operation.
315 */
316
317 pci_write_config_byte(master_0, 0x40, 0x1e);
318
319 /*
320 * Set max PCI burst size (16-bytes seems to work best):
321 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
322 * all others: clear bit-1 at 0x41, and do:
323 * 128bytes: OR 0x00 at 0x41
324 * 256bytes: OR 0x04 at 0x41
325 * 512bytes: OR 0x08 at 0x41
326 * 1024bytes: OR 0x0c at 0x41
327 */
328
329 pci_write_config_byte(master_0, 0x41, 0x14);
330
331 /*
332 * These settings are necessary to get the chip
333 * into a sane state for IDE DMA operation.
334 */
335
336 pci_write_config_byte(master_0, 0x42, 0x00);
337 pci_write_config_byte(master_0, 0x43, 0xc1);
338
339 pci_dev_put(master_0);
340 pci_dev_put(cs5530_0);
341
342 if (cs5530_is_palmax())
343 port_info[1] = &info_palmax_secondary;
344
345 /* Now kick off ATA set up */
346 return ata_pci_init_one(dev, port_info, 2);
347
348fail_put:
349 if (master_0)
350 pci_dev_put(master_0);
351 if (cs5530_0)
352 pci_dev_put(cs5530_0);
353 return -ENODEV;
354}
355
356static struct pci_device_id cs5530[] = {
357 { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
358 { 0, },
359};
360
361static struct pci_driver cs5530_pci_driver = {
362 .name = DRV_NAME,
363 .id_table = cs5530,
364 .probe = cs5530_init_one,
365 .remove = ata_pci_remove_one
366};
367
368static int __init cs5530_init(void)
369{
370 return pci_register_driver(&cs5530_pci_driver);
371}
372
373
374static void __exit cs5530_exit(void)
375{
376 pci_unregister_driver(&cs5530_pci_driver);
377}
378
379
380MODULE_AUTHOR("Alan Cox");
381MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
382MODULE_LICENSE("GPL");
383MODULE_DEVICE_TABLE(pci, cs5530);
384MODULE_VERSION(DRV_VERSION);
385
386module_init(cs5530_init);
387module_exit(cs5530_exit);