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authorMika Westerberg <mika.westerberg@linux.intel.com>2015-02-18 06:50:17 -0500
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2015-02-18 12:47:44 -0500
commit3095794ae972bc6fc76af6cb3b864d6686b96094 (patch)
tree5a55e78482f6e4d44492a0a7f1932ac0636a2bc7 /drivers/acpi
parent3293c7b8ec213a640f5ea2e5efeaa2b7559b1e19 (diff)
ACPI / LPSS: Deassert resets for SPI host controllers on Braswell
On some Braswell systems BIOS leaves resets for SPI host controllers active. This prevents the SPI driver from transferring messages on wire. Fix this in similar way that we do for I2C already by deasserting resets for the SPI host controllers. Reported-by: Yang A Fang <yang.a.fang@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: 3.17+ <stable@vger.kernel.org> # 3.17+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/acpi')
-rw-r--r--drivers/acpi/acpi_lpss.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
index cb84efe7fc5d..6bb8d3574ec6 100644
--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -105,9 +105,7 @@ static void lpss_uart_setup(struct lpss_private_data *pdata)
105 } 105 }
106} 106}
107 107
108#define LPSS_I2C_ENABLE 0x6c 108static void lpss_deassert_reset(struct lpss_private_data *pdata)
109
110static void byt_i2c_setup(struct lpss_private_data *pdata)
111{ 109{
112 unsigned int offset; 110 unsigned int offset;
113 u32 val; 111 u32 val;
@@ -116,6 +114,13 @@ static void byt_i2c_setup(struct lpss_private_data *pdata)
116 val = readl(pdata->mmio_base + offset); 114 val = readl(pdata->mmio_base + offset);
117 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 115 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
118 writel(val, pdata->mmio_base + offset); 116 writel(val, pdata->mmio_base + offset);
117}
118
119#define LPSS_I2C_ENABLE 0x6c
120
121static void byt_i2c_setup(struct lpss_private_data *pdata)
122{
123 lpss_deassert_reset(pdata);
119 124
120 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 125 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
121 pdata->fixed_clk_rate = 133000000; 126 pdata->fixed_clk_rate = 133000000;
@@ -170,6 +175,12 @@ static struct lpss_device_desc byt_i2c_dev_desc = {
170 .setup = byt_i2c_setup, 175 .setup = byt_i2c_setup,
171}; 176};
172 177
178static struct lpss_device_desc bsw_spi_dev_desc = {
179 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
180 .prv_offset = 0x400,
181 .setup = lpss_deassert_reset,
182};
183
173#else 184#else
174 185
175#define LPSS_ADDR(desc) (0UL) 186#define LPSS_ADDR(desc) (0UL)
@@ -202,7 +213,7 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = {
202 /* Braswell LPSS devices */ 213 /* Braswell LPSS devices */
203 { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, 214 { "80862288", LPSS_ADDR(byt_pwm_dev_desc) },
204 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, 215 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
205 { "8086228E", LPSS_ADDR(byt_spi_dev_desc) }, 216 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
206 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, 217 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
207 218
208 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 219 { "INT3430", LPSS_ADDR(lpt_dev_desc) },