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authorBalaji T K <balajitk@ti.com>2011-10-03 08:22:50 -0400
committerTony Lindgren <tony@atomide.com>2011-11-04 20:41:07 -0400
commitff2beb1d9f2fecc3f5c1d67bfec1183a5a476586 (patch)
tree2b66069b8f479cd8e1f7015d3574170d93f9f0cb /arch
parentace9021698ef7d298e6d184ae2880b1cb3ebc4c7 (diff)
ARM: OMAP4: hsmmc: Fix Pbias configuration on regulator OFF
MMC1 data line IO's are powered down in before set regulator function. IO's should not be powered ON when regulator is OFF. Keep the IO's in power pown mode after regulator OFF otherwise VMODE_ERROR interrupt is generated due to mismatch in input (regulator) voltage and MMC IO drive voltage. Delete incorrect comments which are not applicable for OMAP4. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Reported-by: Viswanath Puttagunta <vishp@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/hsmmc.c14
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 77085847e4e7..d663649f6923 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -129,15 +129,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the 129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both 130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register. 131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
132 *
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
135 *
136 * FIXME handle VMMC1A as needed ...
137 */ 132 */
138 reg = omap4_ctrl_pad_readl(control_pbias_offset); 133 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | 134 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_MMC1_PWRDNZ_MASK); 135 OMAP4_MMC1_PWRDNZ_MASK |
136 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
141 omap4_ctrl_pad_writel(reg, control_pbias_offset); 137 omap4_ctrl_pad_writel(reg, control_pbias_offset);
142} 138}
143 139
@@ -172,12 +168,6 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
172 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); 168 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
173 omap4_ctrl_pad_writel(reg, control_pbias_offset); 169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
174 } 170 }
175 } else {
176 reg = omap4_ctrl_pad_readl(control_pbias_offset);
177 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
178 OMAP4_MMC1_PWRDNZ_MASK |
179 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
180 omap4_ctrl_pad_writel(reg, control_pbias_offset);
181 } 171 }
182} 172}
183 173