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authorYinghai Lu <yhlu.kernel@gmail.com>2008-09-04 23:09:14 -0400
committerIngo Molnar <mingo@elte.hu>2008-09-05 03:40:57 -0400
commitf5017cfa3591d8eaf5c792e40ff30f18e498b68c (patch)
tree644c59dace6207b489f3412820bfb0caadd42afd /arch
parent143b604a2d07ff69cc2bc02ecd9395b28e0b5292 (diff)
x86: use cpu/common.c on 64 bit
Use cpu/common.c on both 64-bit and 32-bit and remove cpu/common_64.c. We started out with this linecount: 816 arch/x86/kernel/cpu/common_64.c 805 arch/x86/kernel/cpu/common.c and the resulting common.c is 1197 lines long, so there's already 424 lines of code eliminated in this phase of the unification. Signed-off-by: Yinghai <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/cpu/Makefile6
-rw-r--r--arch/x86/kernel/cpu/common_64.c1197
2 files changed, 3 insertions, 1200 deletions
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 403e689df0b8..d031f248dfc0 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -3,10 +3,10 @@
3# 3#
4 4
5obj-y := intel_cacheinfo.o addon_cpuid_features.o 5obj-y := intel_cacheinfo.o addon_cpuid_features.o
6obj-y += proc.o capflags.o powerflags.o 6obj-y += proc.o capflags.o powerflags.o common.o
7 7
8obj-$(CONFIG_X86_32) += common.o bugs.o cmpxchg.o 8obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o
9obj-$(CONFIG_X86_64) += common_64.o bugs_64.o 9obj-$(CONFIG_X86_64) += bugs_64.o
10 10
11obj-$(CONFIG_CPU_SUP_INTEL_32) += intel.o 11obj-$(CONFIG_CPU_SUP_INTEL_32) += intel.o
12obj-$(CONFIG_CPU_SUP_INTEL_64) += intel_64.o 12obj-$(CONFIG_CPU_SUP_INTEL_64) += intel_64.o
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
deleted file mode 100644
index eef868c97b89..000000000000
--- a/arch/x86/kernel/cpu/common_64.c
+++ /dev/null
@@ -1,1197 +0,0 @@
1#include <linux/init.h>
2#include <linux/kernel.h>
3#include <linux/sched.h>
4#include <linux/string.h>
5#include <linux/bootmem.h>
6#include <linux/bitops.h>
7#include <linux/module.h>
8#include <linux/kgdb.h>
9#include <linux/topology.h>
10#include <linux/delay.h>
11#include <linux/smp.h>
12#include <linux/percpu.h>
13#include <asm/i387.h>
14#include <asm/msr.h>
15#include <asm/io.h>
16#include <asm/linkage.h>
17#include <asm/mmu_context.h>
18#include <asm/mtrr.h>
19#include <asm/mce.h>
20#include <asm/pat.h>
21#include <asm/asm.h>
22#include <asm/numa.h>
23#ifdef CONFIG_X86_LOCAL_APIC
24#include <asm/mpspec.h>
25#include <asm/apic.h>
26#include <mach_apic.h>
27#include <asm/genapic.h>
28#endif
29
30#include <asm/pda.h>
31#include <asm/pgtable.h>
32#include <asm/processor.h>
33#include <asm/desc.h>
34#include <asm/atomic.h>
35#include <asm/proto.h>
36#include <asm/sections.h>
37#include <asm/setup.h>
38
39#include "cpu.h"
40
41static struct cpu_dev *this_cpu __cpuinitdata;
42
43#ifdef CONFIG_X86_64
44/* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
47 */
48/* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
51 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
57} };
58#else
59DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
60 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
64 /*
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
68 */
69 /* 32-bit code */
70 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
71 /* 16-bit code */
72 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
73 /* 16-bit data */
74 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
75 /* 16-bit data */
76 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
77 /* 16-bit data */
78 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
79 /*
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
82 */
83 /* 32-bit code */
84 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
85 /* 16-bit code */
86 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
87 /* data */
88 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
89
90 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
92} };
93#endif
94EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
95
96#ifdef CONFIG_X86_32
97static int cachesize_override __cpuinitdata = -1;
98static int disable_x86_serial_nr __cpuinitdata = 1;
99
100static int __init cachesize_setup(char *str)
101{
102 get_option(&str, &cachesize_override);
103 return 1;
104}
105__setup("cachesize=", cachesize_setup);
106
107static int __init x86_fxsr_setup(char *s)
108{
109 setup_clear_cpu_cap(X86_FEATURE_FXSR);
110 setup_clear_cpu_cap(X86_FEATURE_XMM);
111 return 1;
112}
113__setup("nofxsr", x86_fxsr_setup);
114
115static int __init x86_sep_setup(char *s)
116{
117 setup_clear_cpu_cap(X86_FEATURE_SEP);
118 return 1;
119}
120__setup("nosep", x86_sep_setup);
121
122/* Standard macro to see if a specific flag is changeable */
123static inline int flag_is_changeable_p(u32 flag)
124{
125 u32 f1, f2;
126
127 asm("pushfl\n\t"
128 "pushfl\n\t"
129 "popl %0\n\t"
130 "movl %0,%1\n\t"
131 "xorl %2,%0\n\t"
132 "pushl %0\n\t"
133 "popfl\n\t"
134 "pushfl\n\t"
135 "popl %0\n\t"
136 "popfl\n\t"
137 : "=&r" (f1), "=&r" (f2)
138 : "ir" (flag));
139
140 return ((f1^f2) & flag) != 0;
141}
142
143/* Probe for the CPUID instruction */
144static int __cpuinit have_cpuid_p(void)
145{
146 return flag_is_changeable_p(X86_EFLAGS_ID);
147}
148
149static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
150{
151 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
152 /* Disable processor serial number */
153 unsigned long lo, hi;
154 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
155 lo |= 0x200000;
156 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
157 printk(KERN_NOTICE "CPU serial number disabled.\n");
158 clear_cpu_cap(c, X86_FEATURE_PN);
159
160 /* Disabling the serial number may affect the cpuid level */
161 c->cpuid_level = cpuid_eax(0);
162 }
163}
164
165static int __init x86_serial_nr_setup(char *s)
166{
167 disable_x86_serial_nr = 0;
168 return 1;
169}
170__setup("serialnumber", x86_serial_nr_setup);
171#else
172static inline int flag_is_changeable_p(u32 flag)
173{
174 return 1;
175}
176/* Probe for the CPUID instruction */
177static inline int have_cpuid_p(void)
178{
179 return 1;
180}
181static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
182{
183}
184#endif
185
186/*
187 * Naming convention should be: <Name> [(<Codename>)]
188 * This table only is used unless init_<vendor>() below doesn't set it;
189 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
190 *
191 */
192
193/* Look up CPU names by table lookup. */
194static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
195{
196 struct cpu_model_info *info;
197
198 if (c->x86_model >= 16)
199 return NULL; /* Range check */
200
201 if (!this_cpu)
202 return NULL;
203
204 info = this_cpu->c_models;
205
206 while (info && info->family) {
207 if (info->family == c->x86)
208 return info->model_names[c->x86_model];
209 info++;
210 }
211 return NULL; /* Not found */
212}
213
214__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
215
216/* Current gdt points %fs at the "master" per-cpu area: after this,
217 * it's on the real one. */
218void switch_to_new_gdt(void)
219{
220 struct desc_ptr gdt_descr;
221
222 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
223 gdt_descr.size = GDT_SIZE - 1;
224 load_gdt(&gdt_descr);
225#ifdef CONFIG_X86_32
226 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
227#endif
228}
229
230static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
231
232static void __cpuinit default_init(struct cpuinfo_x86 *c)
233{
234#ifdef CONFIG_X86_64
235 display_cacheinfo(c);
236#else
237 /* Not much we can do here... */
238 /* Check if at least it has cpuid */
239 if (c->cpuid_level == -1) {
240 /* No cpuid. It must be an ancient CPU */
241 if (c->x86 == 4)
242 strcpy(c->x86_model_id, "486");
243 else if (c->x86 == 3)
244 strcpy(c->x86_model_id, "386");
245 }
246#endif
247}
248
249static struct cpu_dev __cpuinitdata default_cpu = {
250 .c_init = default_init,
251 .c_vendor = "Unknown",
252 .c_x86_vendor = X86_VENDOR_UNKNOWN,
253};
254
255int __cpuinit get_model_name(struct cpuinfo_x86 *c)
256{
257 unsigned int *v;
258 char *p, *q;
259
260 if (c->extended_cpuid_level < 0x80000004)
261 return 0;
262
263 v = (unsigned int *) c->x86_model_id;
264 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
265 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
266 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
267 c->x86_model_id[48] = 0;
268
269 /* Intel chips right-justify this string for some dumb reason;
270 undo that brain damage */
271 p = q = &c->x86_model_id[0];
272 while (*p == ' ')
273 p++;
274 if (p != q) {
275 while (*p)
276 *q++ = *p++;
277 while (q <= &c->x86_model_id[48])
278 *q++ = '\0'; /* Zero-pad the rest */
279 }
280
281 return 1;
282}
283
284void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
285{
286 unsigned int n, dummy, ebx, ecx, edx, l2size;
287
288 n = c->extended_cpuid_level;
289
290 if (n >= 0x80000005) {
291 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
292 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
293 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
294 c->x86_cache_size = (ecx>>24) + (edx>>24);
295#ifdef CONFIG_X86_64
296 /* On K8 L1 TLB is inclusive, so don't count it */
297 c->x86_tlbsize = 0;
298#endif
299 }
300
301 if (n < 0x80000006) /* Some chips just has a large L1. */
302 return;
303
304 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
305 l2size = ecx >> 16;
306
307#ifdef CONFIG_X86_64
308 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
309#else
310 /* do processor-specific cache resizing */
311 if (this_cpu->c_size_cache)
312 l2size = this_cpu->c_size_cache(c, l2size);
313
314 /* Allow user to override all this if necessary. */
315 if (cachesize_override != -1)
316 l2size = cachesize_override;
317
318 if (l2size == 0)
319 return; /* Again, no L2 cache is possible */
320#endif
321
322 c->x86_cache_size = l2size;
323
324 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
325 l2size, ecx & 0xFF);
326}
327
328void __cpuinit detect_ht(struct cpuinfo_x86 *c)
329{
330#ifdef CONFIG_X86_HT
331 u32 eax, ebx, ecx, edx;
332 int index_msb, core_bits;
333
334 if (!cpu_has(c, X86_FEATURE_HT))
335 return;
336
337 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
338 goto out;
339
340 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
341 return;
342
343 cpuid(1, &eax, &ebx, &ecx, &edx);
344
345 smp_num_siblings = (ebx & 0xff0000) >> 16;
346
347 if (smp_num_siblings == 1) {
348 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
349 } else if (smp_num_siblings > 1) {
350
351 if (smp_num_siblings > NR_CPUS) {
352 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
353 smp_num_siblings);
354 smp_num_siblings = 1;
355 return;
356 }
357
358 index_msb = get_count_order(smp_num_siblings);
359#ifdef CONFIG_X86_64
360 c->phys_proc_id = phys_pkg_id(index_msb);
361#else
362 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
363#endif
364
365 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
366
367 index_msb = get_count_order(smp_num_siblings);
368
369 core_bits = get_count_order(c->x86_max_cores);
370
371#ifdef CONFIG_X86_64
372 c->cpu_core_id = phys_pkg_id(index_msb) &
373 ((1 << core_bits) - 1);
374#else
375 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
376 ((1 << core_bits) - 1);
377#endif
378 }
379
380out:
381 if ((c->x86_max_cores * smp_num_siblings) > 1) {
382 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
383 c->phys_proc_id);
384 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
385 c->cpu_core_id);
386 }
387#endif
388}
389
390static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
391{
392 char *v = c->x86_vendor_id;
393 int i;
394 static int printed;
395
396 for (i = 0; i < X86_VENDOR_NUM; i++) {
397 if (!cpu_devs[i])
398 break;
399
400 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
401 (cpu_devs[i]->c_ident[1] &&
402 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
403 this_cpu = cpu_devs[i];
404 c->x86_vendor = this_cpu->c_x86_vendor;
405 return;
406 }
407 }
408
409 if (!printed) {
410 printed++;
411 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
412 printk(KERN_ERR "CPU: Your system may be unstable.\n");
413 }
414
415 c->x86_vendor = X86_VENDOR_UNKNOWN;
416 this_cpu = &default_cpu;
417}
418
419void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
420{
421 /* Get vendor name */
422 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
423 (unsigned int *)&c->x86_vendor_id[0],
424 (unsigned int *)&c->x86_vendor_id[8],
425 (unsigned int *)&c->x86_vendor_id[4]);
426
427 c->x86 = 4;
428 /* Intel-defined flags: level 0x00000001 */
429 if (c->cpuid_level >= 0x00000001) {
430 u32 junk, tfms, cap0, misc;
431 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
432 c->x86 = (tfms >> 8) & 0xf;
433 c->x86_model = (tfms >> 4) & 0xf;
434 c->x86_mask = tfms & 0xf;
435 if (c->x86 == 0xf)
436 c->x86 += (tfms >> 20) & 0xff;
437 if (c->x86 >= 0x6)
438 c->x86_model += ((tfms >> 16) & 0xf) << 4;
439 if (cap0 & (1<<19)) {
440 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
441 c->x86_cache_alignment = c->x86_clflush_size;
442 }
443 }
444}
445
446static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
447{
448 u32 tfms, xlvl;
449 u32 ebx;
450
451 /* Intel-defined flags: level 0x00000001 */
452 if (c->cpuid_level >= 0x00000001) {
453 u32 capability, excap;
454 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
455 c->x86_capability[0] = capability;
456 c->x86_capability[4] = excap;
457 }
458
459 /* AMD-defined flags: level 0x80000001 */
460 xlvl = cpuid_eax(0x80000000);
461 c->extended_cpuid_level = xlvl;
462 if ((xlvl & 0xffff0000) == 0x80000000) {
463 if (xlvl >= 0x80000001) {
464 c->x86_capability[1] = cpuid_edx(0x80000001);
465 c->x86_capability[6] = cpuid_ecx(0x80000001);
466 }
467 }
468
469#ifdef CONFIG_X86_64
470 /* Transmeta-defined flags: level 0x80860001 */
471 xlvl = cpuid_eax(0x80860000);
472 if ((xlvl & 0xffff0000) == 0x80860000) {
473 /* Don't set x86_cpuid_level here for now to not confuse. */
474 if (xlvl >= 0x80860001)
475 c->x86_capability[2] = cpuid_edx(0x80860001);
476 }
477
478 if (c->extended_cpuid_level >= 0x80000007)
479 c->x86_power = cpuid_edx(0x80000007);
480
481 if (c->extended_cpuid_level >= 0x80000008) {
482 u32 eax = cpuid_eax(0x80000008);
483
484 c->x86_virt_bits = (eax >> 8) & 0xff;
485 c->x86_phys_bits = eax & 0xff;
486 }
487#endif
488}
489/*
490 * Do minimum CPU detection early.
491 * Fields really needed: vendor, cpuid_level, family, model, mask,
492 * cache alignment.
493 * The others are not touched to avoid unwanted side effects.
494 *
495 * WARNING: this function is only called on the BP. Don't add code here
496 * that is supposed to run on all CPUs.
497 */
498static void __init early_identify_cpu(struct cpuinfo_x86 *c)
499{
500#ifdef CONFIG_X86_64
501 c->x86_clflush_size = 64;
502#else
503 c->x86_clflush_size = 32;
504#endif
505 c->x86_cache_alignment = c->x86_clflush_size;
506
507 if (!have_cpuid_p())
508 return;
509
510 memset(&c->x86_capability, 0, sizeof c->x86_capability);
511
512 c->extended_cpuid_level = 0;
513
514 cpu_detect(c);
515
516 get_cpu_vendor(c);
517
518 get_cpu_cap(c);
519
520 if (this_cpu->c_early_init)
521 this_cpu->c_early_init(c);
522
523 validate_pat_support(c);
524}
525
526void __init early_cpu_init(void)
527{
528 struct cpu_dev **cdev;
529 int count = 0;
530
531 printk("KERNEL supported cpus:\n");
532 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
533 struct cpu_dev *cpudev = *cdev;
534 unsigned int j;
535
536 if (count >= X86_VENDOR_NUM)
537 break;
538 cpu_devs[count] = cpudev;
539 count++;
540
541 for (j = 0; j < 2; j++) {
542 if (!cpudev->c_ident[j])
543 continue;
544 printk(" %s %s\n", cpudev->c_vendor,
545 cpudev->c_ident[j]);
546 }
547 }
548
549 early_identify_cpu(&boot_cpu_data);
550}
551
552/*
553 * The NOPL instruction is supposed to exist on all CPUs with
554 * family >= 6, unfortunately, that's not true in practice because
555 * of early VIA chips and (more importantly) broken virtualizers that
556 * are not easy to detect. Hence, probe for it based on first
557 * principles.
558 *
559 * Note: no 64-bit chip is known to lack these, but put the code here
560 * for consistency with 32 bits, and to make it utterly trivial to
561 * diagnose the problem should it ever surface.
562 */
563static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
564{
565 const u32 nopl_signature = 0x888c53b1; /* Random number */
566 u32 has_nopl = nopl_signature;
567
568 clear_cpu_cap(c, X86_FEATURE_NOPL);
569 if (c->x86 >= 6) {
570 asm volatile("\n"
571 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
572 "2:\n"
573 " .section .fixup,\"ax\"\n"
574 "3: xor %0,%0\n"
575 " jmp 2b\n"
576 " .previous\n"
577 _ASM_EXTABLE(1b,3b)
578 : "+a" (has_nopl));
579
580 if (has_nopl == nopl_signature)
581 set_cpu_cap(c, X86_FEATURE_NOPL);
582 }
583}
584
585static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
586{
587 if (!have_cpuid_p())
588 return;
589
590 c->extended_cpuid_level = 0;
591
592 cpu_detect(c);
593
594 get_cpu_vendor(c);
595
596 get_cpu_cap(c);
597
598 if (c->cpuid_level >= 0x00000001) {
599 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
600#ifdef CONFIG_X86_32
601# ifdef CONFIG_X86_HT
602 c->apicid = phys_pkg_id(c->initial_apicid, 0);
603# else
604 c->apicid = c->initial_apicid;
605# endif
606#endif
607
608#ifdef CONFIG_X86_HT
609 c->phys_proc_id = c->initial_apicid;
610#endif
611 }
612
613 if (c->extended_cpuid_level >= 0x80000004)
614 get_model_name(c); /* Default name */
615
616 init_scattered_cpuid_features(c);
617 detect_nopl(c);
618}
619
620/*
621 * This does the hard work of actually picking apart the CPU stuff...
622 */
623static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
624{
625 int i;
626
627 c->loops_per_jiffy = loops_per_jiffy;
628 c->x86_cache_size = -1;
629 c->x86_vendor = X86_VENDOR_UNKNOWN;
630 c->x86_model = c->x86_mask = 0; /* So far unknown... */
631 c->x86_vendor_id[0] = '\0'; /* Unset */
632 c->x86_model_id[0] = '\0'; /* Unset */
633 c->x86_max_cores = 1;
634#ifdef CONFIG_X86_64
635 c->x86_coreid_bits = 0;
636 c->x86_clflush_size = 64;
637#else
638 c->cpuid_level = -1; /* CPUID not detected */
639 c->x86_clflush_size = 32;
640#endif
641 c->x86_cache_alignment = c->x86_clflush_size;
642 memset(&c->x86_capability, 0, sizeof c->x86_capability);
643
644 if (!have_cpuid_p()) {
645 /*
646 * First of all, decide if this is a 486 or higher
647 * It's a 486 if we can modify the AC flag
648 */
649 if (flag_is_changeable_p(X86_EFLAGS_AC))
650 c->x86 = 4;
651 else
652 c->x86 = 3;
653 }
654
655 generic_identify(c);
656
657 if (this_cpu->c_identify)
658 this_cpu->c_identify(c);
659
660#ifdef CONFIG_X86_64
661 c->apicid = phys_pkg_id(0);
662#endif
663
664 /*
665 * Vendor-specific initialization. In this section we
666 * canonicalize the feature flags, meaning if there are
667 * features a certain CPU supports which CPUID doesn't
668 * tell us, CPUID claiming incorrect flags, or other bugs,
669 * we handle them here.
670 *
671 * At the end of this section, c->x86_capability better
672 * indicate the features this CPU genuinely supports!
673 */
674 if (this_cpu->c_init)
675 this_cpu->c_init(c);
676
677 /* Disable the PN if appropriate */
678 squash_the_stupid_serial_number(c);
679
680 /*
681 * The vendor-specific functions might have changed features. Now
682 * we do "generic changes."
683 */
684
685 /* If the model name is still unset, do table lookup. */
686 if (!c->x86_model_id[0]) {
687 char *p;
688 p = table_lookup_model(c);
689 if (p)
690 strcpy(c->x86_model_id, p);
691 else
692 /* Last resort... */
693 sprintf(c->x86_model_id, "%02x/%02x",
694 c->x86, c->x86_model);
695 }
696
697#ifdef CONFIG_X86_64
698 detect_ht(c);
699#endif
700
701 /*
702 * On SMP, boot_cpu_data holds the common feature set between
703 * all CPUs; so make sure that we indicate which features are
704 * common between the CPUs. The first time this routine gets
705 * executed, c == &boot_cpu_data.
706 */
707 if (c != &boot_cpu_data) {
708 /* AND the already accumulated flags with these */
709 for (i = 0; i < NCAPINTS; i++)
710 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
711 }
712
713 /* Clear all flags overriden by options */
714 for (i = 0; i < NCAPINTS; i++)
715 c->x86_capability[i] &= ~cleared_cpu_caps[i];
716
717#ifdef CONFIG_X86_MCE
718 /* Init Machine Check Exception if available. */
719 mcheck_init(c);
720#endif
721
722 select_idle_routine(c);
723
724#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
725 numa_add_cpu(smp_processor_id());
726#endif
727}
728
729void __init identify_boot_cpu(void)
730{
731 identify_cpu(&boot_cpu_data);
732#ifdef CONFIG_X86_32
733 sysenter_setup();
734 enable_sep_cpu();
735#endif
736}
737
738void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
739{
740 BUG_ON(c == &boot_cpu_data);
741 identify_cpu(c);
742#ifdef CONFIG_X86_32
743 enable_sep_cpu();
744#endif
745 mtrr_ap_init();
746}
747
748struct msr_range {
749 unsigned min;
750 unsigned max;
751};
752
753static struct msr_range msr_range_array[] __cpuinitdata = {
754 { 0x00000000, 0x00000418},
755 { 0xc0000000, 0xc000040b},
756 { 0xc0010000, 0xc0010142},
757 { 0xc0011000, 0xc001103b},
758};
759
760static void __cpuinit print_cpu_msr(void)
761{
762 unsigned index;
763 u64 val;
764 int i;
765 unsigned index_min, index_max;
766
767 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
768 index_min = msr_range_array[i].min;
769 index_max = msr_range_array[i].max;
770 for (index = index_min; index < index_max; index++) {
771 if (rdmsrl_amd_safe(index, &val))
772 continue;
773 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
774 }
775 }
776}
777
778static int show_msr __cpuinitdata;
779static __init int setup_show_msr(char *arg)
780{
781 int num;
782
783 get_option(&arg, &num);
784
785 if (num > 0)
786 show_msr = num;
787 return 1;
788}
789__setup("show_msr=", setup_show_msr);
790
791static __init int setup_noclflush(char *arg)
792{
793 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
794 return 1;
795}
796__setup("noclflush", setup_noclflush);
797
798void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
799{
800 char *vendor = NULL;
801
802 if (c->x86_vendor < X86_VENDOR_NUM)
803 vendor = this_cpu->c_vendor;
804 else if (c->cpuid_level >= 0)
805 vendor = c->x86_vendor_id;
806
807 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
808 printk(KERN_CONT "%s ", vendor);
809
810 if (c->x86_model_id[0])
811 printk(KERN_CONT "%s", c->x86_model_id);
812 else
813 printk(KERN_CONT "%d86", c->x86);
814
815 if (c->x86_mask || c->cpuid_level >= 0)
816 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
817 else
818 printk(KERN_CONT "\n");
819
820#ifdef CONFIG_SMP
821 if (c->cpu_index < show_msr)
822 print_cpu_msr();
823#else
824 if (show_msr)
825 print_cpu_msr();
826#endif
827}
828
829static __init int setup_disablecpuid(char *arg)
830{
831 int bit;
832 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
833 setup_clear_cpu_cap(bit);
834 else
835 return 0;
836 return 1;
837}
838__setup("clearcpuid=", setup_disablecpuid);
839
840cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
841
842#ifdef CONFIG_X86_64
843struct x8664_pda **_cpu_pda __read_mostly;
844EXPORT_SYMBOL(_cpu_pda);
845
846struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
847
848char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
849
850unsigned long __supported_pte_mask __read_mostly = ~0UL;
851EXPORT_SYMBOL_GPL(__supported_pte_mask);
852
853static int do_not_nx __cpuinitdata;
854
855/* noexec=on|off
856Control non executable mappings for 64bit processes.
857
858on Enable(default)
859off Disable
860*/
861static int __init nonx_setup(char *str)
862{
863 if (!str)
864 return -EINVAL;
865 if (!strncmp(str, "on", 2)) {
866 __supported_pte_mask |= _PAGE_NX;
867 do_not_nx = 0;
868 } else if (!strncmp(str, "off", 3)) {
869 do_not_nx = 1;
870 __supported_pte_mask &= ~_PAGE_NX;
871 }
872 return 0;
873}
874early_param("noexec", nonx_setup);
875
876int force_personality32;
877
878/* noexec32=on|off
879Control non executable heap for 32bit processes.
880To control the stack too use noexec=off
881
882on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
883off PROT_READ implies PROT_EXEC
884*/
885static int __init nonx32_setup(char *str)
886{
887 if (!strcmp(str, "on"))
888 force_personality32 &= ~READ_IMPLIES_EXEC;
889 else if (!strcmp(str, "off"))
890 force_personality32 |= READ_IMPLIES_EXEC;
891 return 1;
892}
893__setup("noexec32=", nonx32_setup);
894
895void pda_init(int cpu)
896{
897 struct x8664_pda *pda = cpu_pda(cpu);
898
899 /* Setup up data that may be needed in __get_free_pages early */
900 loadsegment(fs, 0);
901 loadsegment(gs, 0);
902 /* Memory clobbers used to order PDA accessed */
903 mb();
904 wrmsrl(MSR_GS_BASE, pda);
905 mb();
906
907 pda->cpunumber = cpu;
908 pda->irqcount = -1;
909 pda->kernelstack = (unsigned long)stack_thread_info() -
910 PDA_STACKOFFSET + THREAD_SIZE;
911 pda->active_mm = &init_mm;
912 pda->mmu_state = 0;
913
914 if (cpu == 0) {
915 /* others are initialized in smpboot.c */
916 pda->pcurrent = &init_task;
917 pda->irqstackptr = boot_cpu_stack;
918 pda->irqstackptr += IRQSTACKSIZE - 64;
919 } else {
920 if (!pda->irqstackptr) {
921 pda->irqstackptr = (char *)
922 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
923 if (!pda->irqstackptr)
924 panic("cannot allocate irqstack for cpu %d",
925 cpu);
926 pda->irqstackptr += IRQSTACKSIZE - 64;
927 }
928
929 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
930 pda->nodenumber = cpu_to_node(cpu);
931 }
932}
933
934char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
935 DEBUG_STKSZ] __page_aligned_bss;
936
937extern asmlinkage void ignore_sysret(void);
938
939/* May not be marked __init: used by software suspend */
940void syscall_init(void)
941{
942 /*
943 * LSTAR and STAR live in a bit strange symbiosis.
944 * They both write to the same internal register. STAR allows to
945 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
946 */
947 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
948 wrmsrl(MSR_LSTAR, system_call);
949 wrmsrl(MSR_CSTAR, ignore_sysret);
950
951#ifdef CONFIG_IA32_EMULATION
952 syscall32_cpu_init();
953#endif
954
955 /* Flags to clear on syscall */
956 wrmsrl(MSR_SYSCALL_MASK,
957 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
958}
959
960void __cpuinit check_efer(void)
961{
962 unsigned long efer;
963
964 rdmsrl(MSR_EFER, efer);
965 if (!(efer & EFER_NX) || do_not_nx)
966 __supported_pte_mask &= ~_PAGE_NX;
967}
968
969unsigned long kernel_eflags;
970
971/*
972 * Copies of the original ist values from the tss are only accessed during
973 * debugging, no special alignment required.
974 */
975DEFINE_PER_CPU(struct orig_ist, orig_ist);
976
977#else
978
979/* Make sure %fs is initialized properly in idle threads */
980struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
981{
982 memset(regs, 0, sizeof(struct pt_regs));
983 regs->fs = __KERNEL_PERCPU;
984 return regs;
985}
986#endif
987
988/*
989 * cpu_init() initializes state that is per-CPU. Some data is already
990 * initialized (naturally) in the bootstrap process, such as the GDT
991 * and IDT. We reload them nevertheless, this function acts as a
992 * 'CPU state barrier', nothing should get across.
993 * A lot of state is already set up in PDA init for 64 bit
994 */
995#ifdef CONFIG_X86_64
996void __cpuinit cpu_init(void)
997{
998 int cpu = stack_smp_processor_id();
999 struct tss_struct *t = &per_cpu(init_tss, cpu);
1000 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
1001 unsigned long v;
1002 char *estacks = NULL;
1003 struct task_struct *me;
1004 int i;
1005
1006 /* CPU 0 is initialised in head64.c */
1007 if (cpu != 0)
1008 pda_init(cpu);
1009 else
1010 estacks = boot_exception_stacks;
1011
1012 me = current;
1013
1014 if (cpu_test_and_set(cpu, cpu_initialized))
1015 panic("CPU#%d already initialized!\n", cpu);
1016
1017 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1018
1019 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1020
1021 /*
1022 * Initialize the per-CPU GDT with the boot GDT,
1023 * and set up the GDT descriptor:
1024 */
1025
1026 switch_to_new_gdt();
1027 load_idt((const struct desc_ptr *)&idt_descr);
1028
1029 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1030 syscall_init();
1031
1032 wrmsrl(MSR_FS_BASE, 0);
1033 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1034 barrier();
1035
1036 check_efer();
1037 if (cpu != 0 && x2apic)
1038 enable_x2apic();
1039
1040 /*
1041 * set up and load the per-CPU TSS
1042 */
1043 if (!orig_ist->ist[0]) {
1044 static const unsigned int order[N_EXCEPTION_STACKS] = {
1045 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1046 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1047 };
1048 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1049 if (cpu) {
1050 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1051 if (!estacks)
1052 panic("Cannot allocate exception "
1053 "stack %ld %d\n", v, cpu);
1054 }
1055 estacks += PAGE_SIZE << order[v];
1056 orig_ist->ist[v] = t->x86_tss.ist[v] =
1057 (unsigned long)estacks;
1058 }
1059 }
1060
1061 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1062 /*
1063 * <= is required because the CPU will access up to
1064 * 8 bits beyond the end of the IO permission bitmap.
1065 */
1066 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1067 t->io_bitmap[i] = ~0UL;
1068
1069 atomic_inc(&init_mm.mm_count);
1070 me->active_mm = &init_mm;
1071 if (me->mm)
1072 BUG();
1073 enter_lazy_tlb(&init_mm, me);
1074
1075 load_sp0(t, &current->thread);
1076 set_tss_desc(cpu, t);
1077 load_TR_desc();
1078 load_LDT(&init_mm.context);
1079
1080#ifdef CONFIG_KGDB
1081 /*
1082 * If the kgdb is connected no debug regs should be altered. This
1083 * is only applicable when KGDB and a KGDB I/O module are built
1084 * into the kernel and you are using early debugging with
1085 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1086 */
1087 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1088 arch_kgdb_ops.correct_hw_break();
1089 else {
1090#endif
1091 /*
1092 * Clear all 6 debug registers:
1093 */
1094
1095 set_debugreg(0UL, 0);
1096 set_debugreg(0UL, 1);
1097 set_debugreg(0UL, 2);
1098 set_debugreg(0UL, 3);
1099 set_debugreg(0UL, 6);
1100 set_debugreg(0UL, 7);
1101#ifdef CONFIG_KGDB
1102 /* If the kgdb is connected no debug regs should be altered. */
1103 }
1104#endif
1105
1106 fpu_init();
1107
1108 raw_local_save_flags(kernel_eflags);
1109
1110 if (is_uv_system())
1111 uv_cpu_init();
1112}
1113
1114#else
1115
1116void __cpuinit cpu_init(void)
1117{
1118 int cpu = smp_processor_id();
1119 struct task_struct *curr = current;
1120 struct tss_struct *t = &per_cpu(init_tss, cpu);
1121 struct thread_struct *thread = &curr->thread;
1122
1123 if (cpu_test_and_set(cpu, cpu_initialized)) {
1124 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1125 for (;;) local_irq_enable();
1126 }
1127
1128 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1129
1130 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1131 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1132
1133 load_idt(&idt_descr);
1134 switch_to_new_gdt();
1135
1136 /*
1137 * Set up and load the per-CPU TSS and LDT
1138 */
1139 atomic_inc(&init_mm.mm_count);
1140 curr->active_mm = &init_mm;
1141 if (curr->mm)
1142 BUG();
1143 enter_lazy_tlb(&init_mm, curr);
1144
1145 load_sp0(t, thread);
1146 set_tss_desc(cpu, t);
1147 load_TR_desc();
1148 load_LDT(&init_mm.context);
1149
1150#ifdef CONFIG_DOUBLEFAULT
1151 /* Set up doublefault TSS pointer in the GDT */
1152 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1153#endif
1154
1155 /* Clear %gs. */
1156 asm volatile ("mov %0, %%gs" : : "r" (0));
1157
1158 /* Clear all 6 debug registers: */
1159 set_debugreg(0, 0);
1160 set_debugreg(0, 1);
1161 set_debugreg(0, 2);
1162 set_debugreg(0, 3);
1163 set_debugreg(0, 6);
1164 set_debugreg(0, 7);
1165
1166 /*
1167 * Force FPU initialization:
1168 */
1169 if (cpu_has_xsave)
1170 current_thread_info()->status = TS_XSAVE;
1171 else
1172 current_thread_info()->status = 0;
1173 clear_used_math();
1174 mxcsr_feature_mask_init();
1175
1176 /*
1177 * Boot processor to setup the FP and extended state context info.
1178 */
1179 if (!smp_processor_id())
1180 init_thread_xstate();
1181
1182 xsave_init();
1183}
1184
1185#ifdef CONFIG_HOTPLUG_CPU
1186void __cpuinit cpu_uninit(void)
1187{
1188 int cpu = raw_smp_processor_id();
1189 cpu_clear(cpu, cpu_initialized);
1190
1191 /* lazy TLB state */
1192 per_cpu(cpu_tlbstate, cpu).state = 0;
1193 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1194}
1195#endif
1196
1197#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 22:36:12 -0500