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authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-25 01:22:09 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:32:44 -0500
commiteedd62ed53512e6749764427ffe5a1c9e41175c6 (patch)
treece0bb6c8213f432df213188fd460390d3bc39f3c /arch
parent44f25fb4d0754c6c2ab5bf97990a671e19152139 (diff)
[POWERPC] 83xx: mpc834x_mds - Convert device tree source to dts-v1
Move mpc834x_mds device tree source forward to dts-v1 format. Nothing too complex in this one, so it boils down to just adding a bunch of 0x in the right places and converting clock speeds to decimal. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts252
1 files changed, 127 insertions, 125 deletions
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 4120e92fcecf..d2c0e8ab8b7c 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8349EMDS"; 15 model = "MPC8349EMDS";
14 compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS"; 16 compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
@@ -31,10 +33,10 @@
31 PowerPC,8349@0 { 33 PowerPC,8349@0 {
32 device_type = "cpu"; 34 device_type = "cpu";
33 reg = <0>; 35 reg = <0>;
34 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>;
35 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>;
36 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <32768>;
37 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <32768>;
38 timebase-frequency = <0>; // from bootloader 40 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader 41 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader 42 clock-frequency = <0>; // from bootloader
@@ -43,26 +45,26 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <00000000 10000000>; // 256MB at 0 48 reg = <0x00000000 0x10000000>; // 256MB at 0
47 }; 49 };
48 50
49 bcsr@e2400000 { 51 bcsr@e2400000 {
50 device_type = "board-control"; 52 device_type = "board-control";
51 reg = <e2400000 8000>; 53 reg = <0xe2400000 0x8000>;
52 }; 54 };
53 55
54 soc8349@e0000000 { 56 soc8349@e0000000 {
55 #address-cells = <1>; 57 #address-cells = <1>;
56 #size-cells = <1>; 58 #size-cells = <1>;
57 device_type = "soc"; 59 device_type = "soc";
58 ranges = <0 e0000000 00100000>; 60 ranges = <0x0 0xe0000000 0x00100000>;
59 reg = <e0000000 00000200>; 61 reg = <0xe0000000 0x00000200>;
60 bus-frequency = <0>; 62 bus-frequency = <0>;
61 63
62 wdt@200 { 64 wdt@200 {
63 device_type = "watchdog"; 65 device_type = "watchdog";
64 compatible = "mpc83xx_wdt"; 66 compatible = "mpc83xx_wdt";
65 reg = <200 100>; 67 reg = <0x200 0x100>;
66 }; 68 };
67 69
68 i2c@3000 { 70 i2c@3000 {
@@ -70,14 +72,14 @@
70 #size-cells = <0>; 72 #size-cells = <0>;
71 cell-index = <0>; 73 cell-index = <0>;
72 compatible = "fsl-i2c"; 74 compatible = "fsl-i2c";
73 reg = <3000 100>; 75 reg = <0x3000 0x100>;
74 interrupts = <e 8>; 76 interrupts = <14 8>;
75 interrupt-parent = < &ipic >; 77 interrupt-parent = <&ipic>;
76 dfsrr; 78 dfsrr;
77 79
78 rtc@68 { 80 rtc@68 {
79 compatible = "dallas,ds1374"; 81 compatible = "dallas,ds1374";
80 reg = <68>; 82 reg = <0x68>;
81 }; 83 };
82 }; 84 };
83 85
@@ -86,41 +88,41 @@
86 #size-cells = <0>; 88 #size-cells = <0>;
87 cell-index = <1>; 89 cell-index = <1>;
88 compatible = "fsl-i2c"; 90 compatible = "fsl-i2c";
89 reg = <3100 100>; 91 reg = <0x3100 0x100>;
90 interrupts = <f 8>; 92 interrupts = <15 8>;
91 interrupt-parent = < &ipic >; 93 interrupt-parent = <&ipic>;
92 dfsrr; 94 dfsrr;
93 }; 95 };
94 96
95 spi@7000 { 97 spi@7000 {
96 device_type = "spi"; 98 device_type = "spi";
97 compatible = "fsl_spi"; 99 compatible = "fsl_spi";
98 reg = <7000 1000>; 100 reg = <0x7000 0x1000>;
99 interrupts = <10 8>; 101 interrupts = <16 8>;
100 interrupt-parent = < &ipic >; 102 interrupt-parent = <&ipic>;
101 mode = "cpu"; 103 mode = "cpu";
102 }; 104 };
103 105
104 /* phy type (ULPI or SERIAL) are only types supportted for MPH */ 106 /* phy type (ULPI or SERIAL) are only types supported for MPH */
105 /* port = 0 or 1 */ 107 /* port = 0 or 1 */
106 usb@22000 { 108 usb@22000 {
107 compatible = "fsl-usb2-mph"; 109 compatible = "fsl-usb2-mph";
108 reg = <22000 1000>; 110 reg = <0x22000 0x1000>;
109 #address-cells = <1>; 111 #address-cells = <1>;
110 #size-cells = <0>; 112 #size-cells = <0>;
111 interrupt-parent = < &ipic >; 113 interrupt-parent = <&ipic>;
112 interrupts = <27 8>; 114 interrupts = <39 8>;
113 phy_type = "ulpi"; 115 phy_type = "ulpi";
114 port1; 116 port1;
115 }; 117 };
116 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 118 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
117 usb@23000 { 119 usb@23000 {
118 compatible = "fsl-usb2-dr"; 120 compatible = "fsl-usb2-dr";
119 reg = <23000 1000>; 121 reg = <0x23000 0x1000>;
120 #address-cells = <1>; 122 #address-cells = <1>;
121 #size-cells = <0>; 123 #size-cells = <0>;
122 interrupt-parent = < &ipic >; 124 interrupt-parent = <&ipic>;
123 interrupts = <26 8>; 125 interrupts = <38 8>;
124 dr_mode = "otg"; 126 dr_mode = "otg";
125 phy_type = "ulpi"; 127 phy_type = "ulpi";
126 }; 128 };
@@ -129,18 +131,18 @@
129 #address-cells = <1>; 131 #address-cells = <1>;
130 #size-cells = <0>; 132 #size-cells = <0>;
131 compatible = "fsl,gianfar-mdio"; 133 compatible = "fsl,gianfar-mdio";
132 reg = <24520 20>; 134 reg = <0x24520 0x20>;
133 135
134 phy0: ethernet-phy@0 { 136 phy0: ethernet-phy@0 {
135 interrupt-parent = < &ipic >; 137 interrupt-parent = <&ipic>;
136 interrupts = <11 8>; 138 interrupts = <17 8>;
137 reg = <0>; 139 reg = <0x0>;
138 device_type = "ethernet-phy"; 140 device_type = "ethernet-phy";
139 }; 141 };
140 phy1: ethernet-phy@1 { 142 phy1: ethernet-phy@1 {
141 interrupt-parent = < &ipic >; 143 interrupt-parent = <&ipic>;
142 interrupts = <12 8>; 144 interrupts = <18 8>;
143 reg = <1>; 145 reg = <0x1>;
144 device_type = "ethernet-phy"; 146 device_type = "ethernet-phy";
145 }; 147 };
146 }; 148 };
@@ -150,11 +152,11 @@
150 device_type = "network"; 152 device_type = "network";
151 model = "TSEC"; 153 model = "TSEC";
152 compatible = "gianfar"; 154 compatible = "gianfar";
153 reg = <24000 1000>; 155 reg = <0x24000 0x1000>;
154 local-mac-address = [ 00 00 00 00 00 00 ]; 156 local-mac-address = [ 00 00 00 00 00 00 ];
155 interrupts = <20 8 21 8 22 8>; 157 interrupts = <32 8 33 8 34 8>;
156 interrupt-parent = < &ipic >; 158 interrupt-parent = <&ipic>;
157 phy-handle = < &phy0 >; 159 phy-handle = <&phy0>;
158 linux,network-index = <0>; 160 linux,network-index = <0>;
159 }; 161 };
160 162
@@ -163,11 +165,11 @@
163 device_type = "network"; 165 device_type = "network";
164 model = "TSEC"; 166 model = "TSEC";
165 compatible = "gianfar"; 167 compatible = "gianfar";
166 reg = <25000 1000>; 168 reg = <0x25000 0x1000>;
167 local-mac-address = [ 00 00 00 00 00 00 ]; 169 local-mac-address = [ 00 00 00 00 00 00 ];
168 interrupts = <23 8 24 8 25 8>; 170 interrupts = <35 8 36 8 37 8>;
169 interrupt-parent = < &ipic >; 171 interrupt-parent = <&ipic>;
170 phy-handle = < &phy1 >; 172 phy-handle = <&phy1>;
171 linux,network-index = <1>; 173 linux,network-index = <1>;
172 }; 174 };
173 175
@@ -175,20 +177,20 @@
175 cell-index = <0>; 177 cell-index = <0>;
176 device_type = "serial"; 178 device_type = "serial";
177 compatible = "ns16550"; 179 compatible = "ns16550";
178 reg = <4500 100>; 180 reg = <0x4500 0x100>;
179 clock-frequency = <0>; 181 clock-frequency = <0>;
180 interrupts = <9 8>; 182 interrupts = <9 8>;
181 interrupt-parent = < &ipic >; 183 interrupt-parent = <&ipic>;
182 }; 184 };
183 185
184 serial1: serial@4600 { 186 serial1: serial@4600 {
185 cell-index = <1>; 187 cell-index = <1>;
186 device_type = "serial"; 188 device_type = "serial";
187 compatible = "ns16550"; 189 compatible = "ns16550";
188 reg = <4600 100>; 190 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 191 clock-frequency = <0>;
190 interrupts = <a 8>; 192 interrupts = <10 8>;
191 interrupt-parent = < &ipic >; 193 interrupt-parent = <&ipic>;
192 }; 194 };
193 195
194 /* May need to remove if on a part without crypto engine */ 196 /* May need to remove if on a part without crypto engine */
@@ -196,15 +198,15 @@
196 device_type = "crypto"; 198 device_type = "crypto";
197 model = "SEC2"; 199 model = "SEC2";
198 compatible = "talitos"; 200 compatible = "talitos";
199 reg = <30000 10000>; 201 reg = <0x30000 0x10000>;
200 interrupts = <b 8>; 202 interrupts = <11 8>;
201 interrupt-parent = < &ipic >; 203 interrupt-parent = <&ipic>;
202 num-channels = <4>; 204 num-channels = <4>;
203 channel-fifo-len = <18>; 205 channel-fifo-len = <0x18>;
204 exec-units-mask = <0000007e>; 206 exec-units-mask = <0x0000007e>;
205 /* desc mask is for rev2.0, 207 /* desc mask is for rev2.0,
206 * we need runtime fixup for >2.0 */ 208 * we need runtime fixup for >2.0 */
207 descriptor-types-mask = <01010ebf>; 209 descriptor-types-mask = <0x01010ebf>;
208 }; 210 };
209 211
210 /* IPIC 212 /* IPIC
@@ -217,129 +219,129 @@
217 interrupt-controller; 219 interrupt-controller;
218 #address-cells = <0>; 220 #address-cells = <0>;
219 #interrupt-cells = <2>; 221 #interrupt-cells = <2>;
220 reg = <700 100>; 222 reg = <0x700 0x100>;
221 device_type = "ipic"; 223 device_type = "ipic";
222 }; 224 };
223 }; 225 };
224 226
225 pci0: pci@e0008500 { 227 pci0: pci@e0008500 {
226 cell-index = <1>; 228 cell-index = <1>;
227 interrupt-map-mask = <f800 0 0 7>; 229 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
228 interrupt-map = < 230 interrupt-map = <
229 231
230 /* IDSEL 0x11 */ 232 /* IDSEL 0x11 */
231 8800 0 0 1 &ipic 14 8 233 0x8800 0x0 0x0 0x1 &ipic 20 0x8
232 8800 0 0 2 &ipic 15 8 234 0x8800 0x0 0x0 0x2 &ipic 21 0x8
233 8800 0 0 3 &ipic 16 8 235 0x8800 0x0 0x0 0x3 &ipic 22 0x8
234 8800 0 0 4 &ipic 17 8 236 0x8800 0x0 0x0 0x4 &ipic 23 0x8
235 237
236 /* IDSEL 0x12 */ 238 /* IDSEL 0x12 */
237 9000 0 0 1 &ipic 16 8 239 0x9000 0x0 0x0 0x1 &ipic 22 0x8
238 9000 0 0 2 &ipic 17 8 240 0x9000 0x0 0x0 0x2 &ipic 23 0x8
239 9000 0 0 3 &ipic 14 8 241 0x9000 0x0 0x0 0x3 &ipic 20 0x8
240 9000 0 0 4 &ipic 15 8 242 0x9000 0x0 0x0 0x4 &ipic 21 0x8
241 243
242 /* IDSEL 0x13 */ 244 /* IDSEL 0x13 */
243 9800 0 0 1 &ipic 17 8 245 0x9800 0x0 0x0 0x1 &ipic 23 0x8
244 9800 0 0 2 &ipic 14 8 246 0x9800 0x0 0x0 0x2 &ipic 20 0x8
245 9800 0 0 3 &ipic 15 8 247 0x9800 0x0 0x0 0x3 &ipic 21 0x8
246 9800 0 0 4 &ipic 16 8 248 0x9800 0x0 0x0 0x4 &ipic 22 0x8
247 249
248 /* IDSEL 0x15 */ 250 /* IDSEL 0x15 */
249 a800 0 0 1 &ipic 14 8 251 0xa800 0x0 0x0 0x1 &ipic 20 0x8
250 a800 0 0 2 &ipic 15 8 252 0xa800 0x0 0x0 0x2 &ipic 21 0x8
251 a800 0 0 3 &ipic 16 8 253 0xa800 0x0 0x0 0x3 &ipic 22 0x8
252 a800 0 0 4 &ipic 17 8 254 0xa800 0x0 0x0 0x4 &ipic 23 0x8
253 255
254 /* IDSEL 0x16 */ 256 /* IDSEL 0x16 */
255 b000 0 0 1 &ipic 17 8 257 0xb000 0x0 0x0 0x1 &ipic 23 0x8
256 b000 0 0 2 &ipic 14 8 258 0xb000 0x0 0x0 0x2 &ipic 20 0x8
257 b000 0 0 3 &ipic 15 8 259 0xb000 0x0 0x0 0x3 &ipic 21 0x8
258 b000 0 0 4 &ipic 16 8 260 0xb000 0x0 0x0 0x4 &ipic 22 0x8
259 261
260 /* IDSEL 0x17 */ 262 /* IDSEL 0x17 */
261 b800 0 0 1 &ipic 16 8 263 0xb800 0x0 0x0 0x1 &ipic 22 0x8
262 b800 0 0 2 &ipic 17 8 264 0xb800 0x0 0x0 0x2 &ipic 23 0x8
263 b800 0 0 3 &ipic 14 8 265 0xb800 0x0 0x0 0x3 &ipic 20 0x8
264 b800 0 0 4 &ipic 15 8 266 0xb800 0x0 0x0 0x4 &ipic 21 0x8
265 267
266 /* IDSEL 0x18 */ 268 /* IDSEL 0x18 */
267 c000 0 0 1 &ipic 15 8 269 0xc000 0x0 0x0 0x1 &ipic 21 0x8
268 c000 0 0 2 &ipic 16 8 270 0xc000 0x0 0x0 0x2 &ipic 22 0x8
269 c000 0 0 3 &ipic 17 8 271 0xc000 0x0 0x0 0x3 &ipic 23 0x8
270 c000 0 0 4 &ipic 14 8>; 272 0xc000 0x0 0x0 0x4 &ipic 20 8>;
271 interrupt-parent = < &ipic >; 273 interrupt-parent = <&ipic>;
272 interrupts = <42 8>; 274 interrupts = <66 8>;
273 bus-range = <0 0>; 275 bus-range = <0 0>;
274 ranges = <02000000 0 90000000 90000000 0 10000000 276 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
275 42000000 0 80000000 80000000 0 10000000 277 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
276 01000000 0 00000000 e2000000 0 00100000>; 278 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
277 clock-frequency = <3f940aa>; 279 clock-frequency = <66666666>;
278 #interrupt-cells = <1>; 280 #interrupt-cells = <1>;
279 #size-cells = <2>; 281 #size-cells = <2>;
280 #address-cells = <3>; 282 #address-cells = <3>;
281 reg = <e0008500 100>; 283 reg = <0xe0008500 0x100>;
282 compatible = "fsl,mpc8349-pci"; 284 compatible = "fsl,mpc8349-pci";
283 device_type = "pci"; 285 device_type = "pci";
284 }; 286 };
285 287
286 pci1: pci@e0008600 { 288 pci1: pci@e0008600 {
287 cell-index = <2>; 289 cell-index = <2>;
288 interrupt-map-mask = <f800 0 0 7>; 290 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
289 interrupt-map = < 291 interrupt-map = <
290 292
291 /* IDSEL 0x11 */ 293 /* IDSEL 0x11 */
292 8800 0 0 1 &ipic 14 8 294 0x8800 0x0 0x0 0x1 &ipic 20 0x8
293 8800 0 0 2 &ipic 15 8 295 0x8800 0x0 0x0 0x2 &ipic 21 0x8
294 8800 0 0 3 &ipic 16 8 296 0x8800 0x0 0x0 0x3 &ipic 22 0x8
295 8800 0 0 4 &ipic 17 8 297 0x8800 0x0 0x0 0x4 &ipic 23 0x8
296 298
297 /* IDSEL 0x12 */ 299 /* IDSEL 0x12 */
298 9000 0 0 1 &ipic 16 8 300 0x9000 0x0 0x0 0x1 &ipic 22 0x8
299 9000 0 0 2 &ipic 17 8 301 0x9000 0x0 0x0 0x2 &ipic 23 0x8
300 9000 0 0 3 &ipic 14 8 302 0x9000 0x0 0x0 0x3 &ipic 20 0x8
301 9000 0 0 4 &ipic 15 8 303 0x9000 0x0 0x0 0x4 &ipic 21 0x8
302 304
303 /* IDSEL 0x13 */ 305 /* IDSEL 0x13 */
304 9800 0 0 1 &ipic 17 8 306 0x9800 0x0 0x0 0x1 &ipic 23 0x8
305 9800 0 0 2 &ipic 14 8 307 0x9800 0x0 0x0 0x2 &ipic 20 0x8
306 9800 0 0 3 &ipic 15 8 308 0x9800 0x0 0x0 0x3 &ipic 21 0x8
307 9800 0 0 4 &ipic 16 8 309 0x9800 0x0 0x0 0x4 &ipic 22 0x8
308 310
309 /* IDSEL 0x15 */ 311 /* IDSEL 0x15 */
310 a800 0 0 1 &ipic 14 8 312 0xa800 0x0 0x0 0x1 &ipic 20 0x8
311 a800 0 0 2 &ipic 15 8 313 0xa800 0x0 0x0 0x2 &ipic 21 0x8
312 a800 0 0 3 &ipic 16 8 314 0xa800 0x0 0x0 0x3 &ipic 22 0x8
313 a800 0 0 4 &ipic 17 8 315 0xa800 0x0 0x0 0x4 &ipic 23 0x8
314 316
315 /* IDSEL 0x16 */ 317 /* IDSEL 0x16 */
316 b000 0 0 1 &ipic 17 8 318 0xb000 0x0 0x0 0x1 &ipic 23 0x8
317 b000 0 0 2 &ipic 14 8 319 0xb000 0x0 0x0 0x2 &ipic 20 0x8
318 b000 0 0 3 &ipic 15 8 320 0xb000 0x0 0x0 0x3 &ipic 21 0x8
319 b000 0 0 4 &ipic 16 8 321 0xb000 0x0 0x0 0x4 &ipic 22 0x8
320 322
321 /* IDSEL 0x17 */ 323 /* IDSEL 0x17 */
322 b800 0 0 1 &ipic 16 8 324 0xb800 0x0 0x0 0x1 &ipic 22 0x8
323 b800 0 0 2 &ipic 17 8 325 0xb800 0x0 0x0 0x2 &ipic 23 0x8
324 b800 0 0 3 &ipic 14 8 326 0xb800 0x0 0x0 0x3 &ipic 20 0x8
325 b800 0 0 4 &ipic 15 8 327 0xb800 0x0 0x0 0x4 &ipic 21 0x8
326 328
327 /* IDSEL 0x18 */ 329 /* IDSEL 0x18 */
328 c000 0 0 1 &ipic 15 8 330 0xc000 0x0 0x0 0x1 &ipic 21 0x8
329 c000 0 0 2 &ipic 16 8 331 0xc000 0x0 0x0 0x2 &ipic 22 0x8
330 c000 0 0 3 &ipic 17 8 332 0xc000 0x0 0x0 0x3 &ipic 23 0x8
331 c000 0 0 4 &ipic 14 8>; 333 0xc000 0x0 0x0 0x4 &ipic 20 8>;
332 interrupt-parent = < &ipic >; 334 interrupt-parent = <&ipic>;
333 interrupts = <42 8>; 335 interrupts = <66 8>;
334 bus-range = <0 0>; 336 bus-range = <0 0>;
335 ranges = <02000000 0 b0000000 b0000000 0 10000000 337 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
336 42000000 0 a0000000 a0000000 0 10000000 338 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
337 01000000 0 00000000 e2100000 0 00100000>; 339 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
338 clock-frequency = <3f940aa>; 340 clock-frequency = <66666666>;
339 #interrupt-cells = <1>; 341 #interrupt-cells = <1>;
340 #size-cells = <2>; 342 #size-cells = <2>;
341 #address-cells = <3>; 343 #address-cells = <3>;
342 reg = <e0008600 100>; 344 reg = <0xe0008600 0x100>;
343 compatible = "fsl,mpc8349-pci"; 345 compatible = "fsl,mpc8349-pci";
344 device_type = "pci"; 346 device_type = "pci";
345 }; 347 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 21:02:53 -0500