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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-17 16:28:39 -0500
committerRalf Baechle <ralf@linux-mips.org>2008-12-22 03:54:47 -0500
commited2b03ed3cec2a4719d04ef208319f9de6a4258a (patch)
tree302f49c0e98a736a5949a92538bce999fb5bc41a /arch
parent08d9d1c4d44ce43856da048cb0737ef769b61e9a (diff)
MIPS: MIPS64R2: Fix buggy __arch_swab64
The way the code is written it was assuming dshd has the function of a hypothetical dshw instruction ... Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/byteorder.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index 2988d29a0867..33790b9e0cc0 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -50,9 +50,8 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
50static inline __attribute_const__ __u64 __arch_swab64(__u64 x) 50static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
51{ 51{
52 __asm__( 52 __asm__(
53 " dsbh %0, %1 \n" 53 " dsbh %0, %1\n"
54 " dshd %0, %0 \n" 54 " dshd %0, %0"
55 " drotr %0, %0, 32 \n"
56 : "=r" (x) 55 : "=r" (x)
57 : "r" (x)); 56 : "r" (x));
58 57