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authorTony Lindgren <tony@atomide.com>2012-08-27 20:43:01 -0400
committerTony Lindgren <tony@atomide.com>2012-09-12 21:06:30 -0400
commitec2c0825ca3183a646a24717966cc7752e8b0393 (patch)
tree55a80bb4cc0a16eeb288f80352f3144d33556c51 /arch
parent7d7e1eba7e92c2f9c76db80adc24836e7a114bfb (diff)
ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ
Remove hardcoded IRQs in irqs.h and related files as these are no longer needed. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/common.h3
-rw-r--r--arch/arm/mach-omap2/include/mach/irqs.h2
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/include/plat/irqs-44xx.h144
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h183
5 files changed, 4 insertions, 329 deletions
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7e60a69bfe61..4cdb08c8ab52 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -26,12 +26,13 @@
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H 26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
27#ifndef __ASSEMBLER__ 27#ifndef __ASSEMBLER__
28 28
29#include <linux/irq.h>
29#include <linux/delay.h> 30#include <linux/delay.h>
30#include <linux/i2c/twl.h> 31#include <linux/i2c/twl.h>
31#include <plat/common.h> 32#include <plat/common.h>
32#include <asm/proc-fns.h> 33#include <asm/proc-fns.h>
33 34
34#define OMAP_INTC_START 0 35#define OMAP_INTC_START NR_IRQS
35 36
36#ifdef CONFIG_SOC_OMAP2420 37#ifdef CONFIG_SOC_OMAP2420
37extern void omap242x_map_common_io(void); 38extern void omap242x_map_common_io(void);
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab7725696..ba5282cafa42 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,5 +1,3 @@
1/* 1/*
2 * arch/arm/mach-omap2/include/mach/irqs.h 2 * arch/arm/mach-omap2/include/mach/irqs.h
3 */ 3 */
4
5#include <plat/irqs.h>
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c..d15a4a6d6146 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
25 bool "TI OMAP2/3/4" 25 bool "TI OMAP2/3/4"
26 select CLKDEV_LOOKUP 26 select CLKDEV_LOOKUP
27 select GENERIC_IRQ_CHIP 27 select GENERIC_IRQ_CHIP
28 select SPARSE_IRQ
28 select OMAP_DM_TIMER 29 select OMAP_DM_TIMER
29 select USE_OF 30 select USE_OF
30 select PROC_DEVICETREE if PROC_FS 31 select PROC_DEVICETREE if PROC_FS
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c80116..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * OMAP4 Interrupt lines definitions
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Santosh Shilimkar (santosh.shilimkar@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
21#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
22
23/* OMAP44XX IRQs numbers definitions */
24#define OMAP44XX_IRQ_LOCALTIMER 29
25#define OMAP44XX_IRQ_LOCALWDT 30
26
27#define OMAP44XX_IRQ_GIC_START 32
28
29#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START)
30#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START)
31#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START)
32#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
33#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START)
34#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START)
35#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START)
36#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START)
37#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START)
38#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START)
39#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START)
40#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START)
41#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START)
42#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START)
43#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START)
44#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START)
45#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START)
46#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START)
47#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START)
48#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START)
49#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START)
50#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START)
51#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START)
52#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START)
53#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START)
54#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START)
55#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START)
56#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START)
57#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START)
58#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START)
59#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START)
60#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START)
61#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START)
62#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START)
63#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START)
64#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START)
65#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START)
66#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START)
67#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START)
68#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START)
69#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START)
70#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START)
71#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START)
72#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START)
73#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START)
74#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START)
75#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START)
76#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START)
77#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START)
78#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START)
79#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START)
80#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START)
81#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START)
82#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START)
83#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START)
84#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START)
85#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START)
86#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START)
87#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START)
88#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START)
89#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START)
90#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START)
91#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START)
92#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START)
93#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START)
94#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START)
95#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START)
96#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START)
97#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START)
98#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START)
99#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START)
100#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START)
101#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START)
102#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START)
103#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START)
104#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START)
105#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START)
106#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START)
107#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START)
108#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START)
109#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START)
110#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START)
111#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START)
112#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START)
113#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START)
114#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START)
115#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START)
116#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START)
117#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START)
118#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START)
119#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START)
120#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START)
121#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START)
122#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START)
123#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START)
124#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START)
125#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START)
126#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START)
127#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START)
128#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START)
129#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START)
130#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START)
131#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START)
132#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START)
133#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START)
134#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START)
135#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START)
136#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START)
137#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START)
138#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START)
139#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START)
140#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START)
141#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START)
142#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START)
143
144#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index fc3959cdac31..729992d7d26a 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,9 +28,6 @@
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H 28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H 29#define __ASM_ARCH_OMAP15XX_IRQS_H
30 30
31/* All OMAP4 specific defines are moved to irqs-44xx.h */
32#include "irqs-44xx.h"
33
34/* 31/*
35 * IRQ numbers for interrupt handler 1 32 * IRQ numbers for interrupt handler 1
36 * 33 *
@@ -242,125 +239,6 @@
242#define INT_7XX_DMA_CH15 (62 + IH2_BASE) 239#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
243#define INT_7XX_NAND (63 + IH2_BASE) 240#define INT_7XX_NAND (63 + IH2_BASE)
244 241
245#define INT_24XX_SYS_NIRQ 7
246#define INT_24XX_SDMA_IRQ0 12
247#define INT_24XX_SDMA_IRQ1 13
248#define INT_24XX_SDMA_IRQ2 14
249#define INT_24XX_SDMA_IRQ3 15
250#define INT_24XX_CAM_IRQ 24
251#define INT_24XX_DSS_IRQ 25
252#define INT_24XX_MAIL_U0_MPU 26
253#define INT_24XX_DSP_UMA 27
254#define INT_24XX_DSP_MMU 28
255#define INT_24XX_GPIO_BANK1 29
256#define INT_24XX_GPIO_BANK2 30
257#define INT_24XX_GPIO_BANK3 31
258#define INT_24XX_GPIO_BANK4 32
259#define INT_24XX_GPIO_BANK5 33
260#define INT_24XX_MAIL_U3_MPU 34
261#define INT_24XX_GPTIMER1 37
262#define INT_24XX_GPTIMER2 38
263#define INT_24XX_GPTIMER3 39
264#define INT_24XX_GPTIMER4 40
265#define INT_24XX_GPTIMER5 41
266#define INT_24XX_GPTIMER6 42
267#define INT_24XX_GPTIMER7 43
268#define INT_24XX_GPTIMER8 44
269#define INT_24XX_GPTIMER9 45
270#define INT_24XX_GPTIMER10 46
271#define INT_24XX_GPTIMER11 47
272#define INT_24XX_GPTIMER12 48
273#define INT_24XX_SHA1MD5 51
274#define INT_24XX_MCBSP4_IRQ_TX 54
275#define INT_24XX_MCBSP4_IRQ_RX 55
276#define INT_24XX_I2C1_IRQ 56
277#define INT_24XX_I2C2_IRQ 57
278#define INT_24XX_HDQ_IRQ 58
279#define INT_24XX_MCBSP1_IRQ_TX 59
280#define INT_24XX_MCBSP1_IRQ_RX 60
281#define INT_24XX_MCBSP2_IRQ_TX 62
282#define INT_24XX_MCBSP2_IRQ_RX 63
283#define INT_24XX_SPI1_IRQ 65
284#define INT_24XX_SPI2_IRQ 66
285#define INT_24XX_UART1_IRQ 72
286#define INT_24XX_UART2_IRQ 73
287#define INT_24XX_UART3_IRQ 74
288#define INT_24XX_USB_IRQ_GEN 75
289#define INT_24XX_USB_IRQ_NISO 76
290#define INT_24XX_USB_IRQ_ISO 77
291#define INT_24XX_USB_IRQ_HGEN 78
292#define INT_24XX_USB_IRQ_HSOF 79
293#define INT_24XX_USB_IRQ_OTG 80
294#define INT_24XX_MCBSP5_IRQ_TX 81
295#define INT_24XX_MCBSP5_IRQ_RX 82
296#define INT_24XX_MMC_IRQ 83
297#define INT_24XX_MMC2_IRQ 86
298#define INT_24XX_MCBSP3_IRQ_TX 89
299#define INT_24XX_MCBSP3_IRQ_RX 90
300#define INT_24XX_SPI3_IRQ 91
301
302#define INT_243X_MCBSP2_IRQ 16
303#define INT_243X_MCBSP3_IRQ 17
304#define INT_243X_MCBSP4_IRQ 18
305#define INT_243X_MCBSP5_IRQ 19
306#define INT_243X_MCBSP1_IRQ 64
307#define INT_243X_HS_USB_MC 92
308#define INT_243X_HS_USB_DMA 93
309#define INT_243X_CARKIT_IRQ 94
310
311#define INT_34XX_BENCH_MPU_EMUL 3
312#define INT_34XX_ST_MCBSP2_IRQ 4
313#define INT_34XX_ST_MCBSP3_IRQ 5
314#define INT_34XX_SSM_ABORT_IRQ 6
315#define INT_34XX_SYS_NIRQ 7
316#define INT_34XX_D2D_FW_IRQ 8
317#define INT_34XX_L3_DBG_IRQ 9
318#define INT_34XX_L3_APP_IRQ 10
319#define INT_34XX_PRCM_MPU_IRQ 11
320#define INT_34XX_MCBSP1_IRQ 16
321#define INT_34XX_MCBSP2_IRQ 17
322#define INT_34XX_GPMC_IRQ 20
323#define INT_34XX_MCBSP3_IRQ 22
324#define INT_34XX_MCBSP4_IRQ 23
325#define INT_34XX_CAM_IRQ 24
326#define INT_34XX_MCBSP5_IRQ 27
327#define INT_34XX_GPIO_BANK1 29
328#define INT_34XX_GPIO_BANK2 30
329#define INT_34XX_GPIO_BANK3 31
330#define INT_34XX_GPIO_BANK4 32
331#define INT_34XX_GPIO_BANK5 33
332#define INT_34XX_GPIO_BANK6 34
333#define INT_34XX_USIM_IRQ 35
334#define INT_34XX_WDT3_IRQ 36
335#define INT_34XX_SPI4_IRQ 48
336#define INT_34XX_SHA1MD52_IRQ 49
337#define INT_34XX_FPKA_READY_IRQ 50
338#define INT_34XX_SHA1MD51_IRQ 51
339#define INT_34XX_RNG_IRQ 52
340#define INT_34XX_I2C3_IRQ 61
341#define INT_34XX_FPKA_ERROR_IRQ 64
342#define INT_34XX_PBIAS_IRQ 75
343#define INT_34XX_OHCI_IRQ 76
344#define INT_34XX_EHCI_IRQ 77
345#define INT_34XX_TLL_IRQ 78
346#define INT_34XX_PARTHASH_IRQ 79
347#define INT_34XX_MMC3_IRQ 94
348#define INT_34XX_GPT12_IRQ 95
349
350#define INT_36XX_UART4_IRQ 80
351
352#define INT_35XX_HECC0_IRQ 24
353#define INT_35XX_HECC1_IRQ 28
354#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
355#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
356#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
357#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
358#define INT_35XX_USBOTG_IRQ 71
359#define INT_35XX_UART4_IRQ 84
360#define INT_35XX_CCDC_VD0_IRQ 88
361#define INT_35XX_CCDC_VD1_IRQ 92
362#define INT_35XX_CCDC_VD2_IRQ 93
363
364/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and 242/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
365 * 16 MPUIO lines */ 243 * 16 MPUIO lines */
366#define OMAP_MAX_GPIO_LINES 192 244#define OMAP_MAX_GPIO_LINES 192
@@ -377,66 +255,7 @@
377#endif 255#endif
378#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) 256#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
379 257
380/* External TWL4030 can handle interrupts on 2430 and 34xx boards */ 258#define NR_IRQS OMAP_FPGA_IRQ_END
381#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
382#ifdef CONFIG_TWL4030_CORE
383#define TWL4030_BASE_NR_IRQS 8
384#define TWL4030_PWR_NR_IRQS 8
385#else
386#define TWL4030_BASE_NR_IRQS 0
387#define TWL4030_PWR_NR_IRQS 0
388#endif
389#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
390#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
391#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
392
393/* External TWL4030 gpio interrupts are optional */
394#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
395#ifdef CONFIG_GPIO_TWL4030
396#define TWL4030_GPIO_NR_IRQS 18
397#else
398#define TWL4030_GPIO_NR_IRQS 0
399#endif
400#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
401
402#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
403#ifdef CONFIG_TWL4030_CORE
404#define TWL6030_BASE_NR_IRQS 20
405#else
406#define TWL6030_BASE_NR_IRQS 0
407#endif
408#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
409
410#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
411#ifdef CONFIG_TWL6040_CODEC
412#define TWL6040_CODEC_NR_IRQS 6
413#else
414#define TWL6040_CODEC_NR_IRQS 0
415#endif
416#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
417
418/* Total number of interrupts depends on the enabled blocks above */
419#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
420#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
421#else
422#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
423#endif
424
425/* GPMC related */
426#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
427#define OMAP_GPMC_NR_IRQS 8
428#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
429
430/* PRCM IRQ handler */
431#ifdef CONFIG_ARCH_OMAP2PLUS
432#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
433#define OMAP_PRCM_NR_IRQS 64
434#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
435#else
436#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
437#endif
438
439#define NR_IRQS OMAP_PRCM_IRQ_END
440 259
441#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 260#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
442 261
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 10:06:20 -0500