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authorKevin Hilman <khilman@ti.com>2011-05-20 05:53:37 -0400
committerKevin Hilman <khilman@ti.com>2011-05-27 11:43:34 -0400
commite5cdb13ff95e1400bc94d3e6610fc5e95be3b5b1 (patch)
tree0421e5fc4819966c366fd68a6cdfc5f89422c430 /arch
parent5ee1a81b84ee8b0bd0b4f8cdbac48b472863c1f2 (diff)
GPIO: OMAP: move to drivers/gpio
Move OMAP GPIO driver to drivers/gpio. Builds whenever CONFIG_ARCH_OMAP=y. Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/gpio.c2009
2 files changed, 1 insertions, 2010 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a4a12859fdd5..f0233e6abcdf 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
7 usb.o fb.o io.o counter_32k.o 7 usb.o fb.o io.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
deleted file mode 100644
index 44acabd5f530..000000000000
--- a/arch/arm/plat-omap/gpio.c
+++ /dev/null
@@ -1,2009 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/syscore_ops.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
26
27#include <mach/hardware.h>
28#include <asm/irq.h>
29#include <mach/irqs.h>
30#include <mach/gpio.h>
31#include <asm/mach/irq.h>
32
33struct gpio_bank {
34 unsigned long pbase;
35 void __iomem *base;
36 u16 irq;
37 u16 virtual_irq_start;
38 int method;
39#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
40 u32 suspend_wakeup;
41 u32 saved_wakeup;
42#endif
43 u32 non_wakeup_gpios;
44 u32 enabled_non_wakeup_gpios;
45
46 u32 saved_datain;
47 u32 saved_fallingdetect;
48 u32 saved_risingdetect;
49 u32 level_mask;
50 u32 toggle_mask;
51 spinlock_t lock;
52 struct gpio_chip chip;
53 struct clk *dbck;
54 u32 mod_usage;
55 u32 dbck_enable_mask;
56 struct device *dev;
57 bool dbck_flag;
58 int stride;
59};
60
61#ifdef CONFIG_ARCH_OMAP3
62struct omap3_gpio_regs {
63 u32 irqenable1;
64 u32 irqenable2;
65 u32 wake_en;
66 u32 ctrl;
67 u32 oe;
68 u32 leveldetect0;
69 u32 leveldetect1;
70 u32 risingdetect;
71 u32 fallingdetect;
72 u32 dataout;
73};
74
75static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
76#endif
77
78/*
79 * TODO: Cleanup gpio_bank usage as it is having information
80 * related to all instances of the device
81 */
82static struct gpio_bank *gpio_bank;
83
84static int bank_width;
85
86/* TODO: Analyze removing gpio_bank_count usage from driver code */
87int gpio_bank_count;
88
89static inline struct gpio_bank *get_gpio_bank(int gpio)
90{
91 if (cpu_is_omap15xx()) {
92 if (OMAP_GPIO_IS_MPUIO(gpio))
93 return &gpio_bank[0];
94 return &gpio_bank[1];
95 }
96 if (cpu_is_omap16xx()) {
97 if (OMAP_GPIO_IS_MPUIO(gpio))
98 return &gpio_bank[0];
99 return &gpio_bank[1 + (gpio >> 4)];
100 }
101 if (cpu_is_omap7xx()) {
102 if (OMAP_GPIO_IS_MPUIO(gpio))
103 return &gpio_bank[0];
104 return &gpio_bank[1 + (gpio >> 5)];
105 }
106 if (cpu_is_omap24xx())
107 return &gpio_bank[gpio >> 5];
108 if (cpu_is_omap34xx() || cpu_is_omap44xx())
109 return &gpio_bank[gpio >> 5];
110 BUG();
111 return NULL;
112}
113
114static inline int get_gpio_index(int gpio)
115{
116 if (cpu_is_omap7xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap24xx())
119 return gpio & 0x1f;
120 if (cpu_is_omap34xx() || cpu_is_omap44xx())
121 return gpio & 0x1f;
122 return gpio & 0x0f;
123}
124
125static inline int gpio_valid(int gpio)
126{
127 if (gpio < 0)
128 return -1;
129 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
130 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
131 return -1;
132 return 0;
133 }
134 if (cpu_is_omap15xx() && gpio < 16)
135 return 0;
136 if ((cpu_is_omap16xx()) && gpio < 64)
137 return 0;
138 if (cpu_is_omap7xx() && gpio < 192)
139 return 0;
140 if (cpu_is_omap2420() && gpio < 128)
141 return 0;
142 if (cpu_is_omap2430() && gpio < 160)
143 return 0;
144 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
145 return 0;
146 return -1;
147}
148
149static int check_gpio(int gpio)
150{
151 if (unlikely(gpio_valid(gpio) < 0)) {
152 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
153 dump_stack();
154 return -1;
155 }
156 return 0;
157}
158
159static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
160{
161 void __iomem *reg = bank->base;
162 u32 l;
163
164 switch (bank->method) {
165#ifdef CONFIG_ARCH_OMAP1
166 case METHOD_MPUIO:
167 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
168 break;
169#endif
170#ifdef CONFIG_ARCH_OMAP15XX
171 case METHOD_GPIO_1510:
172 reg += OMAP1510_GPIO_DIR_CONTROL;
173 break;
174#endif
175#ifdef CONFIG_ARCH_OMAP16XX
176 case METHOD_GPIO_1610:
177 reg += OMAP1610_GPIO_DIRECTION;
178 break;
179#endif
180#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
181 case METHOD_GPIO_7XX:
182 reg += OMAP7XX_GPIO_DIR_CONTROL;
183 break;
184#endif
185#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
186 case METHOD_GPIO_24XX:
187 reg += OMAP24XX_GPIO_OE;
188 break;
189#endif
190#if defined(CONFIG_ARCH_OMAP4)
191 case METHOD_GPIO_44XX:
192 reg += OMAP4_GPIO_OE;
193 break;
194#endif
195 default:
196 WARN_ON(1);
197 return;
198 }
199 l = __raw_readl(reg);
200 if (is_input)
201 l |= 1 << gpio;
202 else
203 l &= ~(1 << gpio);
204 __raw_writel(l, reg);
205}
206
207static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
208{
209 void __iomem *reg = bank->base;
210 u32 l = 0;
211
212 switch (bank->method) {
213#ifdef CONFIG_ARCH_OMAP1
214 case METHOD_MPUIO:
215 reg += OMAP_MPUIO_OUTPUT / bank->stride;
216 l = __raw_readl(reg);
217 if (enable)
218 l |= 1 << gpio;
219 else
220 l &= ~(1 << gpio);
221 break;
222#endif
223#ifdef CONFIG_ARCH_OMAP15XX
224 case METHOD_GPIO_1510:
225 reg += OMAP1510_GPIO_DATA_OUTPUT;
226 l = __raw_readl(reg);
227 if (enable)
228 l |= 1 << gpio;
229 else
230 l &= ~(1 << gpio);
231 break;
232#endif
233#ifdef CONFIG_ARCH_OMAP16XX
234 case METHOD_GPIO_1610:
235 if (enable)
236 reg += OMAP1610_GPIO_SET_DATAOUT;
237 else
238 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
239 l = 1 << gpio;
240 break;
241#endif
242#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
243 case METHOD_GPIO_7XX:
244 reg += OMAP7XX_GPIO_DATA_OUTPUT;
245 l = __raw_readl(reg);
246 if (enable)
247 l |= 1 << gpio;
248 else
249 l &= ~(1 << gpio);
250 break;
251#endif
252#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
253 case METHOD_GPIO_24XX:
254 if (enable)
255 reg += OMAP24XX_GPIO_SETDATAOUT;
256 else
257 reg += OMAP24XX_GPIO_CLEARDATAOUT;
258 l = 1 << gpio;
259 break;
260#endif
261#ifdef CONFIG_ARCH_OMAP4
262 case METHOD_GPIO_44XX:
263 if (enable)
264 reg += OMAP4_GPIO_SETDATAOUT;
265 else
266 reg += OMAP4_GPIO_CLEARDATAOUT;
267 l = 1 << gpio;
268 break;
269#endif
270 default:
271 WARN_ON(1);
272 return;
273 }
274 __raw_writel(l, reg);
275}
276
277static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
278{
279 void __iomem *reg;
280
281 if (check_gpio(gpio) < 0)
282 return -EINVAL;
283 reg = bank->base;
284 switch (bank->method) {
285#ifdef CONFIG_ARCH_OMAP1
286 case METHOD_MPUIO:
287 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
288 break;
289#endif
290#ifdef CONFIG_ARCH_OMAP15XX
291 case METHOD_GPIO_1510:
292 reg += OMAP1510_GPIO_DATA_INPUT;
293 break;
294#endif
295#ifdef CONFIG_ARCH_OMAP16XX
296 case METHOD_GPIO_1610:
297 reg += OMAP1610_GPIO_DATAIN;
298 break;
299#endif
300#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
301 case METHOD_GPIO_7XX:
302 reg += OMAP7XX_GPIO_DATA_INPUT;
303 break;
304#endif
305#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
306 case METHOD_GPIO_24XX:
307 reg += OMAP24XX_GPIO_DATAIN;
308 break;
309#endif
310#ifdef CONFIG_ARCH_OMAP4
311 case METHOD_GPIO_44XX:
312 reg += OMAP4_GPIO_DATAIN;
313 break;
314#endif
315 default:
316 return -EINVAL;
317 }
318 return (__raw_readl(reg)
319 & (1 << get_gpio_index(gpio))) != 0;
320}
321
322static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
323{
324 void __iomem *reg;
325
326 if (check_gpio(gpio) < 0)
327 return -EINVAL;
328 reg = bank->base;
329
330 switch (bank->method) {
331#ifdef CONFIG_ARCH_OMAP1
332 case METHOD_MPUIO:
333 reg += OMAP_MPUIO_OUTPUT / bank->stride;
334 break;
335#endif
336#ifdef CONFIG_ARCH_OMAP15XX
337 case METHOD_GPIO_1510:
338 reg += OMAP1510_GPIO_DATA_OUTPUT;
339 break;
340#endif
341#ifdef CONFIG_ARCH_OMAP16XX
342 case METHOD_GPIO_1610:
343 reg += OMAP1610_GPIO_DATAOUT;
344 break;
345#endif
346#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
347 case METHOD_GPIO_7XX:
348 reg += OMAP7XX_GPIO_DATA_OUTPUT;
349 break;
350#endif
351#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
352 case METHOD_GPIO_24XX:
353 reg += OMAP24XX_GPIO_DATAOUT;
354 break;
355#endif
356#ifdef CONFIG_ARCH_OMAP4
357 case METHOD_GPIO_44XX:
358 reg += OMAP4_GPIO_DATAOUT;
359 break;
360#endif
361 default:
362 return -EINVAL;
363 }
364
365 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
366}
367
368#define MOD_REG_BIT(reg, bit_mask, set) \
369do { \
370 int l = __raw_readl(base + reg); \
371 if (set) l |= bit_mask; \
372 else l &= ~bit_mask; \
373 __raw_writel(l, base + reg); \
374} while(0)
375
376/**
377 * _set_gpio_debounce - low level gpio debounce time
378 * @bank: the gpio bank we're acting upon
379 * @gpio: the gpio number on this @gpio
380 * @debounce: debounce time to use
381 *
382 * OMAP's debounce time is in 31us steps so we need
383 * to convert and round up to the closest unit.
384 */
385static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
386 unsigned debounce)
387{
388 void __iomem *reg = bank->base;
389 u32 val;
390 u32 l;
391
392 if (!bank->dbck_flag)
393 return;
394
395 if (debounce < 32)
396 debounce = 0x01;
397 else if (debounce > 7936)
398 debounce = 0xff;
399 else
400 debounce = (debounce / 0x1f) - 1;
401
402 l = 1 << get_gpio_index(gpio);
403
404 if (bank->method == METHOD_GPIO_44XX)
405 reg += OMAP4_GPIO_DEBOUNCINGTIME;
406 else
407 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
408
409 __raw_writel(debounce, reg);
410
411 reg = bank->base;
412 if (bank->method == METHOD_GPIO_44XX)
413 reg += OMAP4_GPIO_DEBOUNCENABLE;
414 else
415 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
416
417 val = __raw_readl(reg);
418
419 if (debounce) {
420 val |= l;
421 clk_enable(bank->dbck);
422 } else {
423 val &= ~l;
424 clk_disable(bank->dbck);
425 }
426 bank->dbck_enable_mask = val;
427
428 __raw_writel(val, reg);
429}
430
431#ifdef CONFIG_ARCH_OMAP2PLUS
432static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
433 int trigger)
434{
435 void __iomem *base = bank->base;
436 u32 gpio_bit = 1 << gpio;
437 u32 val;
438
439 if (cpu_is_omap44xx()) {
440 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
441 trigger & IRQ_TYPE_LEVEL_LOW);
442 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
443 trigger & IRQ_TYPE_LEVEL_HIGH);
444 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
445 trigger & IRQ_TYPE_EDGE_RISING);
446 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
447 trigger & IRQ_TYPE_EDGE_FALLING);
448 } else {
449 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
450 trigger & IRQ_TYPE_LEVEL_LOW);
451 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
452 trigger & IRQ_TYPE_LEVEL_HIGH);
453 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
454 trigger & IRQ_TYPE_EDGE_RISING);
455 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
456 trigger & IRQ_TYPE_EDGE_FALLING);
457 }
458 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
459 if (cpu_is_omap44xx()) {
460 if (trigger != 0)
461 __raw_writel(1 << gpio, bank->base+
462 OMAP4_GPIO_IRQWAKEN0);
463 else {
464 val = __raw_readl(bank->base +
465 OMAP4_GPIO_IRQWAKEN0);
466 __raw_writel(val & (~(1 << gpio)), bank->base +
467 OMAP4_GPIO_IRQWAKEN0);
468 }
469 } else {
470 /*
471 * GPIO wakeup request can only be generated on edge
472 * transitions
473 */
474 if (trigger & IRQ_TYPE_EDGE_BOTH)
475 __raw_writel(1 << gpio, bank->base
476 + OMAP24XX_GPIO_SETWKUENA);
477 else
478 __raw_writel(1 << gpio, bank->base
479 + OMAP24XX_GPIO_CLEARWKUENA);
480 }
481 }
482 /* This part needs to be executed always for OMAP34xx */
483 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
484 /*
485 * Log the edge gpio and manually trigger the IRQ
486 * after resume if the input level changes
487 * to avoid irq lost during PER RET/OFF mode
488 * Applies for omap2 non-wakeup gpio and all omap3 gpios
489 */
490 if (trigger & IRQ_TYPE_EDGE_BOTH)
491 bank->enabled_non_wakeup_gpios |= gpio_bit;
492 else
493 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
494 }
495
496 if (cpu_is_omap44xx()) {
497 bank->level_mask =
498 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
499 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
500 } else {
501 bank->level_mask =
502 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
503 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
504 }
505}
506#endif
507
508#ifdef CONFIG_ARCH_OMAP1
509/*
510 * This only applies to chips that can't do both rising and falling edge
511 * detection at once. For all other chips, this function is a noop.
512 */
513static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
514{
515 void __iomem *reg = bank->base;
516 u32 l = 0;
517
518 switch (bank->method) {
519 case METHOD_MPUIO:
520 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
521 break;
522#ifdef CONFIG_ARCH_OMAP15XX
523 case METHOD_GPIO_1510:
524 reg += OMAP1510_GPIO_INT_CONTROL;
525 break;
526#endif
527#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
528 case METHOD_GPIO_7XX:
529 reg += OMAP7XX_GPIO_INT_CONTROL;
530 break;
531#endif
532 default:
533 return;
534 }
535
536 l = __raw_readl(reg);
537 if ((l >> gpio) & 1)
538 l &= ~(1 << gpio);
539 else
540 l |= 1 << gpio;
541
542 __raw_writel(l, reg);
543}
544#endif
545
546static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
547{
548 void __iomem *reg = bank->base;
549 u32 l = 0;
550
551 switch (bank->method) {
552#ifdef CONFIG_ARCH_OMAP1
553 case METHOD_MPUIO:
554 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
555 l = __raw_readl(reg);
556 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
557 bank->toggle_mask |= 1 << gpio;
558 if (trigger & IRQ_TYPE_EDGE_RISING)
559 l |= 1 << gpio;
560 else if (trigger & IRQ_TYPE_EDGE_FALLING)
561 l &= ~(1 << gpio);
562 else
563 goto bad;
564 break;
565#endif
566#ifdef CONFIG_ARCH_OMAP15XX
567 case METHOD_GPIO_1510:
568 reg += OMAP1510_GPIO_INT_CONTROL;
569 l = __raw_readl(reg);
570 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
571 bank->toggle_mask |= 1 << gpio;
572 if (trigger & IRQ_TYPE_EDGE_RISING)
573 l |= 1 << gpio;
574 else if (trigger & IRQ_TYPE_EDGE_FALLING)
575 l &= ~(1 << gpio);
576 else
577 goto bad;
578 break;
579#endif
580#ifdef CONFIG_ARCH_OMAP16XX
581 case METHOD_GPIO_1610:
582 if (gpio & 0x08)
583 reg += OMAP1610_GPIO_EDGE_CTRL2;
584 else
585 reg += OMAP1610_GPIO_EDGE_CTRL1;
586 gpio &= 0x07;
587 l = __raw_readl(reg);
588 l &= ~(3 << (gpio << 1));
589 if (trigger & IRQ_TYPE_EDGE_RISING)
590 l |= 2 << (gpio << 1);
591 if (trigger & IRQ_TYPE_EDGE_FALLING)
592 l |= 1 << (gpio << 1);
593 if (trigger)
594 /* Enable wake-up during idle for dynamic tick */
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
596 else
597 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
598 break;
599#endif
600#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
601 case METHOD_GPIO_7XX:
602 reg += OMAP7XX_GPIO_INT_CONTROL;
603 l = __raw_readl(reg);
604 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
605 bank->toggle_mask |= 1 << gpio;
606 if (trigger & IRQ_TYPE_EDGE_RISING)
607 l |= 1 << gpio;
608 else if (trigger & IRQ_TYPE_EDGE_FALLING)
609 l &= ~(1 << gpio);
610 else
611 goto bad;
612 break;
613#endif
614#ifdef CONFIG_ARCH_OMAP2PLUS
615 case METHOD_GPIO_24XX:
616 case METHOD_GPIO_44XX:
617 set_24xx_gpio_triggering(bank, gpio, trigger);
618 return 0;
619#endif
620 default:
621 goto bad;
622 }
623 __raw_writel(l, reg);
624 return 0;
625bad:
626 return -EINVAL;
627}
628
629static int gpio_irq_type(struct irq_data *d, unsigned type)
630{
631 struct gpio_bank *bank;
632 unsigned gpio;
633 int retval;
634 unsigned long flags;
635
636 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
637 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
638 else
639 gpio = d->irq - IH_GPIO_BASE;
640
641 if (check_gpio(gpio) < 0)
642 return -EINVAL;
643
644 if (type & ~IRQ_TYPE_SENSE_MASK)
645 return -EINVAL;
646
647 /* OMAP1 allows only only edge triggering */
648 if (!cpu_class_is_omap2()
649 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
650 return -EINVAL;
651
652 bank = irq_data_get_irq_chip_data(d);
653 spin_lock_irqsave(&bank->lock, flags);
654 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
655 spin_unlock_irqrestore(&bank->lock, flags);
656
657 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
658 __irq_set_handler_locked(d->irq, handle_level_irq);
659 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
660 __irq_set_handler_locked(d->irq, handle_edge_irq);
661
662 return retval;
663}
664
665static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
666{
667 void __iomem *reg = bank->base;
668
669 switch (bank->method) {
670#ifdef CONFIG_ARCH_OMAP1
671 case METHOD_MPUIO:
672 /* MPUIO irqstatus is reset by reading the status register,
673 * so do nothing here */
674 return;
675#endif
676#ifdef CONFIG_ARCH_OMAP15XX
677 case METHOD_GPIO_1510:
678 reg += OMAP1510_GPIO_INT_STATUS;
679 break;
680#endif
681#ifdef CONFIG_ARCH_OMAP16XX
682 case METHOD_GPIO_1610:
683 reg += OMAP1610_GPIO_IRQSTATUS1;
684 break;
685#endif
686#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
687 case METHOD_GPIO_7XX:
688 reg += OMAP7XX_GPIO_INT_STATUS;
689 break;
690#endif
691#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
692 case METHOD_GPIO_24XX:
693 reg += OMAP24XX_GPIO_IRQSTATUS1;
694 break;
695#endif
696#if defined(CONFIG_ARCH_OMAP4)
697 case METHOD_GPIO_44XX:
698 reg += OMAP4_GPIO_IRQSTATUS0;
699 break;
700#endif
701 default:
702 WARN_ON(1);
703 return;
704 }
705 __raw_writel(gpio_mask, reg);
706
707 /* Workaround for clearing DSP GPIO interrupts to allow retention */
708 if (cpu_is_omap24xx() || cpu_is_omap34xx())
709 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
710 else if (cpu_is_omap44xx())
711 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
712
713 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
714 __raw_writel(gpio_mask, reg);
715
716 /* Flush posted write for the irq status to avoid spurious interrupts */
717 __raw_readl(reg);
718 }
719}
720
721static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
722{
723 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
724}
725
726static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
727{
728 void __iomem *reg = bank->base;
729 int inv = 0;
730 u32 l;
731 u32 mask;
732
733 switch (bank->method) {
734#ifdef CONFIG_ARCH_OMAP1
735 case METHOD_MPUIO:
736 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
737 mask = 0xffff;
738 inv = 1;
739 break;
740#endif
741#ifdef CONFIG_ARCH_OMAP15XX
742 case METHOD_GPIO_1510:
743 reg += OMAP1510_GPIO_INT_MASK;
744 mask = 0xffff;
745 inv = 1;
746 break;
747#endif
748#ifdef CONFIG_ARCH_OMAP16XX
749 case METHOD_GPIO_1610:
750 reg += OMAP1610_GPIO_IRQENABLE1;
751 mask = 0xffff;
752 break;
753#endif
754#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
755 case METHOD_GPIO_7XX:
756 reg += OMAP7XX_GPIO_INT_MASK;
757 mask = 0xffffffff;
758 inv = 1;
759 break;
760#endif
761#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
762 case METHOD_GPIO_24XX:
763 reg += OMAP24XX_GPIO_IRQENABLE1;
764 mask = 0xffffffff;
765 break;
766#endif
767#if defined(CONFIG_ARCH_OMAP4)
768 case METHOD_GPIO_44XX:
769 reg += OMAP4_GPIO_IRQSTATUSSET0;
770 mask = 0xffffffff;
771 break;
772#endif
773 default:
774 WARN_ON(1);
775 return 0;
776 }
777
778 l = __raw_readl(reg);
779 if (inv)
780 l = ~l;
781 l &= mask;
782 return l;
783}
784
785static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
786{
787 void __iomem *reg = bank->base;
788 u32 l;
789
790 switch (bank->method) {
791#ifdef CONFIG_ARCH_OMAP1
792 case METHOD_MPUIO:
793 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
794 l = __raw_readl(reg);
795 if (enable)
796 l &= ~(gpio_mask);
797 else
798 l |= gpio_mask;
799 break;
800#endif
801#ifdef CONFIG_ARCH_OMAP15XX
802 case METHOD_GPIO_1510:
803 reg += OMAP1510_GPIO_INT_MASK;
804 l = __raw_readl(reg);
805 if (enable)
806 l &= ~(gpio_mask);
807 else
808 l |= gpio_mask;
809 break;
810#endif
811#ifdef CONFIG_ARCH_OMAP16XX
812 case METHOD_GPIO_1610:
813 if (enable)
814 reg += OMAP1610_GPIO_SET_IRQENABLE1;
815 else
816 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
817 l = gpio_mask;
818 break;
819#endif
820#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
821 case METHOD_GPIO_7XX:
822 reg += OMAP7XX_GPIO_INT_MASK;
823 l = __raw_readl(reg);
824 if (enable)
825 l &= ~(gpio_mask);
826 else
827 l |= gpio_mask;
828 break;
829#endif
830#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
831 case METHOD_GPIO_24XX:
832 if (enable)
833 reg += OMAP24XX_GPIO_SETIRQENABLE1;
834 else
835 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
836 l = gpio_mask;
837 break;
838#endif
839#ifdef CONFIG_ARCH_OMAP4
840 case METHOD_GPIO_44XX:
841 if (enable)
842 reg += OMAP4_GPIO_IRQSTATUSSET0;
843 else
844 reg += OMAP4_GPIO_IRQSTATUSCLR0;
845 l = gpio_mask;
846 break;
847#endif
848 default:
849 WARN_ON(1);
850 return;
851 }
852 __raw_writel(l, reg);
853}
854
855static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
856{
857 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
858}
859
860/*
861 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
862 * 1510 does not seem to have a wake-up register. If JTAG is connected
863 * to the target, system will wake up always on GPIO events. While
864 * system is running all registered GPIO interrupts need to have wake-up
865 * enabled. When system is suspended, only selected GPIO interrupts need
866 * to have wake-up enabled.
867 */
868static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
869{
870 unsigned long uninitialized_var(flags);
871
872 switch (bank->method) {
873#ifdef CONFIG_ARCH_OMAP16XX
874 case METHOD_MPUIO:
875 case METHOD_GPIO_1610:
876 spin_lock_irqsave(&bank->lock, flags);
877 if (enable)
878 bank->suspend_wakeup |= (1 << gpio);
879 else
880 bank->suspend_wakeup &= ~(1 << gpio);
881 spin_unlock_irqrestore(&bank->lock, flags);
882 return 0;
883#endif
884#ifdef CONFIG_ARCH_OMAP2PLUS
885 case METHOD_GPIO_24XX:
886 case METHOD_GPIO_44XX:
887 if (bank->non_wakeup_gpios & (1 << gpio)) {
888 printk(KERN_ERR "Unable to modify wakeup on "
889 "non-wakeup GPIO%d\n",
890 (bank - gpio_bank) * 32 + gpio);
891 return -EINVAL;
892 }
893 spin_lock_irqsave(&bank->lock, flags);
894 if (enable)
895 bank->suspend_wakeup |= (1 << gpio);
896 else
897 bank->suspend_wakeup &= ~(1 << gpio);
898 spin_unlock_irqrestore(&bank->lock, flags);
899 return 0;
900#endif
901 default:
902 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
903 bank->method);
904 return -EINVAL;
905 }
906}
907
908static void _reset_gpio(struct gpio_bank *bank, int gpio)
909{
910 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
911 _set_gpio_irqenable(bank, gpio, 0);
912 _clear_gpio_irqstatus(bank, gpio);
913 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
914}
915
916/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
917static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
918{
919 unsigned int gpio = d->irq - IH_GPIO_BASE;
920 struct gpio_bank *bank;
921 int retval;
922
923 if (check_gpio(gpio) < 0)
924 return -ENODEV;
925 bank = irq_data_get_irq_chip_data(d);
926 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
927
928 return retval;
929}
930
931static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
932{
933 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
934 unsigned long flags;
935
936 spin_lock_irqsave(&bank->lock, flags);
937
938 /* Set trigger to none. You need to enable the desired trigger with
939 * request_irq() or set_irq_type().
940 */
941 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
942
943#ifdef CONFIG_ARCH_OMAP15XX
944 if (bank->method == METHOD_GPIO_1510) {
945 void __iomem *reg;
946
947 /* Claim the pin for MPU */
948 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
949 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
950 }
951#endif
952 if (!cpu_class_is_omap1()) {
953 if (!bank->mod_usage) {
954 void __iomem *reg = bank->base;
955 u32 ctrl;
956
957 if (cpu_is_omap24xx() || cpu_is_omap34xx())
958 reg += OMAP24XX_GPIO_CTRL;
959 else if (cpu_is_omap44xx())
960 reg += OMAP4_GPIO_CTRL;
961 ctrl = __raw_readl(reg);
962 /* Module is enabled, clocks are not gated */
963 ctrl &= 0xFFFFFFFE;
964 __raw_writel(ctrl, reg);
965 }
966 bank->mod_usage |= 1 << offset;
967 }
968 spin_unlock_irqrestore(&bank->lock, flags);
969
970 return 0;
971}
972
973static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
974{
975 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
976 unsigned long flags;
977
978 spin_lock_irqsave(&bank->lock, flags);
979#ifdef CONFIG_ARCH_OMAP16XX
980 if (bank->method == METHOD_GPIO_1610) {
981 /* Disable wake-up during idle for dynamic tick */
982 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
983 __raw_writel(1 << offset, reg);
984 }
985#endif
986#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
987 if (bank->method == METHOD_GPIO_24XX) {
988 /* Disable wake-up during idle for dynamic tick */
989 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
990 __raw_writel(1 << offset, reg);
991 }
992#endif
993#ifdef CONFIG_ARCH_OMAP4
994 if (bank->method == METHOD_GPIO_44XX) {
995 /* Disable wake-up during idle for dynamic tick */
996 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
997 __raw_writel(1 << offset, reg);
998 }
999#endif
1000 if (!cpu_class_is_omap1()) {
1001 bank->mod_usage &= ~(1 << offset);
1002 if (!bank->mod_usage) {
1003 void __iomem *reg = bank->base;
1004 u32 ctrl;
1005
1006 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1007 reg += OMAP24XX_GPIO_CTRL;
1008 else if (cpu_is_omap44xx())
1009 reg += OMAP4_GPIO_CTRL;
1010 ctrl = __raw_readl(reg);
1011 /* Module is disabled, clocks are gated */
1012 ctrl |= 1;
1013 __raw_writel(ctrl, reg);
1014 }
1015 }
1016 _reset_gpio(bank, bank->chip.base + offset);
1017 spin_unlock_irqrestore(&bank->lock, flags);
1018}
1019
1020/*
1021 * We need to unmask the GPIO bank interrupt as soon as possible to
1022 * avoid missing GPIO interrupts for other lines in the bank.
1023 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1024 * in the bank to avoid missing nested interrupts for a GPIO line.
1025 * If we wait to unmask individual GPIO lines in the bank after the
1026 * line's interrupt handler has been run, we may miss some nested
1027 * interrupts.
1028 */
1029static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1030{
1031 void __iomem *isr_reg = NULL;
1032 u32 isr;
1033 unsigned int gpio_irq, gpio_index;
1034 struct gpio_bank *bank;
1035 u32 retrigger = 0;
1036 int unmasked = 0;
1037 struct irq_chip *chip = irq_desc_get_chip(desc);
1038
1039 chained_irq_enter(chip, desc);
1040
1041 bank = irq_get_handler_data(irq);
1042#ifdef CONFIG_ARCH_OMAP1
1043 if (bank->method == METHOD_MPUIO)
1044 isr_reg = bank->base +
1045 OMAP_MPUIO_GPIO_INT / bank->stride;
1046#endif
1047#ifdef CONFIG_ARCH_OMAP15XX
1048 if (bank->method == METHOD_GPIO_1510)
1049 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1050#endif
1051#if defined(CONFIG_ARCH_OMAP16XX)
1052 if (bank->method == METHOD_GPIO_1610)
1053 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1054#endif
1055#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1056 if (bank->method == METHOD_GPIO_7XX)
1057 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1058#endif
1059#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1060 if (bank->method == METHOD_GPIO_24XX)
1061 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1062#endif
1063#if defined(CONFIG_ARCH_OMAP4)
1064 if (bank->method == METHOD_GPIO_44XX)
1065 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1066#endif
1067
1068 if (WARN_ON(!isr_reg))
1069 goto exit;
1070
1071 while(1) {
1072 u32 isr_saved, level_mask = 0;
1073 u32 enabled;
1074
1075 enabled = _get_gpio_irqbank_mask(bank);
1076 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1077
1078 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1079 isr &= 0x0000ffff;
1080
1081 if (cpu_class_is_omap2()) {
1082 level_mask = bank->level_mask & enabled;
1083 }
1084
1085 /* clear edge sensitive interrupts before handler(s) are
1086 called so that we don't miss any interrupt occurred while
1087 executing them */
1088 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1089 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1090 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1091
1092 /* if there is only edge sensitive GPIO pin interrupts
1093 configured, we could unmask GPIO bank interrupt immediately */
1094 if (!level_mask && !unmasked) {
1095 unmasked = 1;
1096 chained_irq_exit(chip, desc);
1097 }
1098
1099 isr |= retrigger;
1100 retrigger = 0;
1101 if (!isr)
1102 break;
1103
1104 gpio_irq = bank->virtual_irq_start;
1105 for (; isr != 0; isr >>= 1, gpio_irq++) {
1106 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1107
1108 if (!(isr & 1))
1109 continue;
1110
1111#ifdef CONFIG_ARCH_OMAP1
1112 /*
1113 * Some chips can't respond to both rising and falling
1114 * at the same time. If this irq was requested with
1115 * both flags, we need to flip the ICR data for the IRQ
1116 * to respond to the IRQ for the opposite direction.
1117 * This will be indicated in the bank toggle_mask.
1118 */
1119 if (bank->toggle_mask & (1 << gpio_index))
1120 _toggle_gpio_edge_triggering(bank, gpio_index);
1121#endif
1122
1123 generic_handle_irq(gpio_irq);
1124 }
1125 }
1126 /* if bank has any level sensitive GPIO pin interrupt
1127 configured, we must unmask the bank interrupt only after
1128 handler(s) are executed in order to avoid spurious bank
1129 interrupt */
1130exit:
1131 if (!unmasked)
1132 chained_irq_exit(chip, desc);
1133}
1134
1135static void gpio_irq_shutdown(struct irq_data *d)
1136{
1137 unsigned int gpio = d->irq - IH_GPIO_BASE;
1138 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1139
1140 _reset_gpio(bank, gpio);
1141}
1142
1143static void gpio_ack_irq(struct irq_data *d)
1144{
1145 unsigned int gpio = d->irq - IH_GPIO_BASE;
1146 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1147
1148 _clear_gpio_irqstatus(bank, gpio);
1149}
1150
1151static void gpio_mask_irq(struct irq_data *d)
1152{
1153 unsigned int gpio = d->irq - IH_GPIO_BASE;
1154 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1155
1156 _set_gpio_irqenable(bank, gpio, 0);
1157 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1158}
1159
1160static void gpio_unmask_irq(struct irq_data *d)
1161{
1162 unsigned int gpio = d->irq - IH_GPIO_BASE;
1163 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1164 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1165 u32 trigger = irqd_get_trigger_type(d);
1166
1167 if (trigger)
1168 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1169
1170 /* For level-triggered GPIOs, the clearing must be done after
1171 * the HW source is cleared, thus after the handler has run */
1172 if (bank->level_mask & irq_mask) {
1173 _set_gpio_irqenable(bank, gpio, 0);
1174 _clear_gpio_irqstatus(bank, gpio);
1175 }
1176
1177 _set_gpio_irqenable(bank, gpio, 1);
1178}
1179
1180static struct irq_chip gpio_irq_chip = {
1181 .name = "GPIO",
1182 .irq_shutdown = gpio_irq_shutdown,
1183 .irq_ack = gpio_ack_irq,
1184 .irq_mask = gpio_mask_irq,
1185 .irq_unmask = gpio_unmask_irq,
1186 .irq_set_type = gpio_irq_type,
1187 .irq_set_wake = gpio_wake_enable,
1188};
1189
1190/*---------------------------------------------------------------------*/
1191
1192#ifdef CONFIG_ARCH_OMAP1
1193
1194/* MPUIO uses the always-on 32k clock */
1195
1196static void mpuio_ack_irq(struct irq_data *d)
1197{
1198 /* The ISR is reset automatically, so do nothing here. */
1199}
1200
1201static void mpuio_mask_irq(struct irq_data *d)
1202{
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207}
1208
1209static void mpuio_unmask_irq(struct irq_data *d)
1210{
1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215}
1216
1217static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
1223#ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1225 .irq_set_wake = gpio_wake_enable,
1226#endif
1227};
1228
1229
1230#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231
1232
1233#ifdef CONFIG_ARCH_OMAP16XX
1234
1235#include <linux/platform_device.h>
1236
1237static int omap_mpuio_suspend_noirq(struct device *dev)
1238{
1239 struct platform_device *pdev = to_platform_device(dev);
1240 struct gpio_bank *bank = platform_get_drvdata(pdev);
1241 void __iomem *mask_reg = bank->base +
1242 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&bank->lock, flags);
1246 bank->saved_wakeup = __raw_readl(mask_reg);
1247 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1248 spin_unlock_irqrestore(&bank->lock, flags);
1249
1250 return 0;
1251}
1252
1253static int omap_mpuio_resume_noirq(struct device *dev)
1254{
1255 struct platform_device *pdev = to_platform_device(dev);
1256 struct gpio_bank *bank = platform_get_drvdata(pdev);
1257 void __iomem *mask_reg = bank->base +
1258 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&bank->lock, flags);
1262 __raw_writel(bank->saved_wakeup, mask_reg);
1263 spin_unlock_irqrestore(&bank->lock, flags);
1264
1265 return 0;
1266}
1267
1268static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1269 .suspend_noirq = omap_mpuio_suspend_noirq,
1270 .resume_noirq = omap_mpuio_resume_noirq,
1271};
1272
1273/* use platform_driver for this. */
1274static struct platform_driver omap_mpuio_driver = {
1275 .driver = {
1276 .name = "mpuio",
1277 .pm = &omap_mpuio_dev_pm_ops,
1278 },
1279};
1280
1281static struct platform_device omap_mpuio_device = {
1282 .name = "mpuio",
1283 .id = -1,
1284 .dev = {
1285 .driver = &omap_mpuio_driver.driver,
1286 }
1287 /* could list the /proc/iomem resources */
1288};
1289
1290static inline void mpuio_init(void)
1291{
1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1293 platform_set_drvdata(&omap_mpuio_device, bank);
1294
1295 if (platform_driver_register(&omap_mpuio_driver) == 0)
1296 (void) platform_device_register(&omap_mpuio_device);
1297}
1298
1299#else
1300static inline void mpuio_init(void) {}
1301#endif /* 16xx */
1302
1303#else
1304
1305extern struct irq_chip mpuio_irq_chip;
1306
1307#define bank_is_mpuio(bank) 0
1308static inline void mpuio_init(void) {}
1309
1310#endif
1311
1312/*---------------------------------------------------------------------*/
1313
1314/* REVISIT these are stupid implementations! replace by ones that
1315 * don't switch on METHOD_* and which mostly avoid spinlocks
1316 */
1317
1318static int gpio_input(struct gpio_chip *chip, unsigned offset)
1319{
1320 struct gpio_bank *bank;
1321 unsigned long flags;
1322
1323 bank = container_of(chip, struct gpio_bank, chip);
1324 spin_lock_irqsave(&bank->lock, flags);
1325 _set_gpio_direction(bank, offset, 1);
1326 spin_unlock_irqrestore(&bank->lock, flags);
1327 return 0;
1328}
1329
1330static int gpio_is_input(struct gpio_bank *bank, int mask)
1331{
1332 void __iomem *reg = bank->base;
1333
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
1356 }
1357 return __raw_readl(reg) & mask;
1358}
1359
1360static int gpio_get(struct gpio_chip *chip, unsigned offset)
1361{
1362 struct gpio_bank *bank;
1363 void __iomem *reg;
1364 int gpio;
1365 u32 mask;
1366
1367 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio);
1369 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio);
1371
1372 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio);
1374 else
1375 return _get_gpio_dataout(bank, gpio);
1376}
1377
1378static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1379{
1380 struct gpio_bank *bank;
1381 unsigned long flags;
1382
1383 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0;
1389}
1390
1391static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1392 unsigned debounce)
1393{
1394 struct gpio_bank *bank;
1395 unsigned long flags;
1396
1397 bank = container_of(chip, struct gpio_bank, chip);
1398
1399 if (!bank->dbck) {
1400 bank->dbck = clk_get(bank->dev, "dbclk");
1401 if (IS_ERR(bank->dbck))
1402 dev_err(bank->dev, "Could not get gpio dbck\n");
1403 }
1404
1405 spin_lock_irqsave(&bank->lock, flags);
1406 _set_gpio_debounce(bank, offset, debounce);
1407 spin_unlock_irqrestore(&bank->lock, flags);
1408
1409 return 0;
1410}
1411
1412static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1413{
1414 struct gpio_bank *bank;
1415 unsigned long flags;
1416
1417 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags);
1421}
1422
1423static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1424{
1425 struct gpio_bank *bank;
1426
1427 bank = container_of(chip, struct gpio_bank, chip);
1428 return bank->virtual_irq_start + offset;
1429}
1430
1431/*---------------------------------------------------------------------*/
1432
1433static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1434{
1435 u32 rev;
1436
1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1441 else if (cpu_is_omap44xx())
1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1443 else
1444 return;
1445
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f);
1448}
1449
1450/* This lock class tells lockdep that GPIO irqs are in a different
1451 * category than their parents, so it won't report false recursion.
1452 */
1453static struct lock_class_key gpio_lock_class;
1454
1455static inline int init_gpio_info(struct platform_device *pdev)
1456{
1457 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1458 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1459 GFP_KERNEL);
1460 if (!gpio_bank) {
1461 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1462 return -ENOMEM;
1463 }
1464 return 0;
1465}
1466
1467/* TODO: Cleanup cpu_is_* checks */
1468static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1469{
1470 if (cpu_class_is_omap2()) {
1471 if (cpu_is_omap44xx()) {
1472 __raw_writel(0xffffffff, bank->base +
1473 OMAP4_GPIO_IRQSTATUSCLR0);
1474 __raw_writel(0x00000000, bank->base +
1475 OMAP4_GPIO_DEBOUNCENABLE);
1476 /* Initialize interface clk ungated, module enabled */
1477 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1478 } else if (cpu_is_omap34xx()) {
1479 __raw_writel(0x00000000, bank->base +
1480 OMAP24XX_GPIO_IRQENABLE1);
1481 __raw_writel(0xffffffff, bank->base +
1482 OMAP24XX_GPIO_IRQSTATUS1);
1483 __raw_writel(0x00000000, bank->base +
1484 OMAP24XX_GPIO_DEBOUNCE_EN);
1485
1486 /* Initialize interface clk ungated, module enabled */
1487 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1488 } else if (cpu_is_omap24xx()) {
1489 static const u32 non_wakeup_gpios[] = {
1490 0xe203ffc0, 0x08700040
1491 };
1492 if (id < ARRAY_SIZE(non_wakeup_gpios))
1493 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1494 }
1495 } else if (cpu_class_is_omap1()) {
1496 if (bank_is_mpuio(bank))
1497 __raw_writew(0xffff, bank->base +
1498 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1499 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1510_GPIO_INT_MASK);
1502 __raw_writew(0x0000, bank->base
1503 + OMAP1510_GPIO_INT_STATUS);
1504 }
1505 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1506 __raw_writew(0x0000, bank->base
1507 + OMAP1610_GPIO_IRQENABLE1);
1508 __raw_writew(0xffff, bank->base
1509 + OMAP1610_GPIO_IRQSTATUS1);
1510 __raw_writew(0x0014, bank->base
1511 + OMAP1610_GPIO_SYSCONFIG);
1512
1513 /*
1514 * Enable system clock for GPIO module.
1515 * The CAM_CLK_CTRL *is* really the right place.
1516 */
1517 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1518 ULPD_CAM_CLK_CTRL);
1519 }
1520 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1521 __raw_writel(0xffffffff, bank->base
1522 + OMAP7XX_GPIO_INT_MASK);
1523 __raw_writel(0x00000000, bank->base
1524 + OMAP7XX_GPIO_INT_STATUS);
1525 }
1526 }
1527}
1528
1529static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1530{
1531 int j;
1532 static int gpio;
1533
1534 bank->mod_usage = 0;
1535 /*
1536 * REVISIT eventually switch from OMAP-specific gpio structs
1537 * over to the generic ones
1538 */
1539 bank->chip.request = omap_gpio_request;
1540 bank->chip.free = omap_gpio_free;
1541 bank->chip.direction_input = gpio_input;
1542 bank->chip.get = gpio_get;
1543 bank->chip.direction_output = gpio_output;
1544 bank->chip.set_debounce = gpio_debounce;
1545 bank->chip.set = gpio_set;
1546 bank->chip.to_irq = gpio_2irq;
1547 if (bank_is_mpuio(bank)) {
1548 bank->chip.label = "mpuio";
1549#ifdef CONFIG_ARCH_OMAP16XX
1550 bank->chip.dev = &omap_mpuio_device.dev;
1551#endif
1552 bank->chip.base = OMAP_MPUIO(0);
1553 } else {
1554 bank->chip.label = "gpio";
1555 bank->chip.base = gpio;
1556 gpio += bank_width;
1557 }
1558 bank->chip.ngpio = bank_width;
1559
1560 gpiochip_add(&bank->chip);
1561
1562 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) {
1564 irq_set_lockdep_class(j, &gpio_lock_class);
1565 irq_set_chip_data(j, bank);
1566 if (bank_is_mpuio(bank))
1567 irq_set_chip(j, &mpuio_irq_chip);
1568 else
1569 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID);
1572 }
1573 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank);
1575}
1576
1577static int __devinit omap_gpio_probe(struct platform_device *pdev)
1578{
1579 static int gpio_init_done;
1580 struct omap_gpio_platform_data *pdata;
1581 struct resource *res;
1582 int id;
1583 struct gpio_bank *bank;
1584
1585 if (!pdev->dev.platform_data)
1586 return -EINVAL;
1587
1588 pdata = pdev->dev.platform_data;
1589
1590 if (!gpio_init_done) {
1591 int ret;
1592
1593 ret = init_gpio_info(pdev);
1594 if (ret)
1595 return ret;
1596 }
1597
1598 id = pdev->id;
1599 bank = &gpio_bank[id];
1600
1601 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1602 if (unlikely(!res)) {
1603 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1604 return -ENODEV;
1605 }
1606
1607 bank->irq = res->start;
1608 bank->virtual_irq_start = pdata->virtual_irq_start;
1609 bank->method = pdata->bank_type;
1610 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag;
1612 bank->stride = pdata->bank_stride;
1613 bank_width = pdata->bank_width;
1614
1615 spin_lock_init(&bank->lock);
1616
1617 /* Static mapping, never released */
1618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619 if (unlikely(!res)) {
1620 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1621 return -ENODEV;
1622 }
1623
1624 bank->base = ioremap(res->start, resource_size(res));
1625 if (!bank->base) {
1626 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1627 return -ENOMEM;
1628 }
1629
1630 pm_runtime_enable(bank->dev);
1631 pm_runtime_get_sync(bank->dev);
1632
1633 omap_gpio_mod_init(bank, id);
1634 omap_gpio_chip_init(bank);
1635 omap_gpio_show_rev(bank);
1636
1637 if (!gpio_init_done)
1638 gpio_init_done = 1;
1639
1640 return 0;
1641}
1642
1643#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1644static int omap_gpio_suspend(void)
1645{
1646 int i;
1647
1648 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1649 return 0;
1650
1651 for (i = 0; i < gpio_bank_count; i++) {
1652 struct gpio_bank *bank = &gpio_bank[i];
1653 void __iomem *wake_status;
1654 void __iomem *wake_clear;
1655 void __iomem *wake_set;
1656 unsigned long flags;
1657
1658 switch (bank->method) {
1659#ifdef CONFIG_ARCH_OMAP16XX
1660 case METHOD_GPIO_1610:
1661 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1662 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1663 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1664 break;
1665#endif
1666#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1667 case METHOD_GPIO_24XX:
1668 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1669 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1670 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1671 break;
1672#endif
1673#ifdef CONFIG_ARCH_OMAP4
1674 case METHOD_GPIO_44XX:
1675 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1677 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1678 break;
1679#endif
1680 default:
1681 continue;
1682 }
1683
1684 spin_lock_irqsave(&bank->lock, flags);
1685 bank->saved_wakeup = __raw_readl(wake_status);
1686 __raw_writel(0xffffffff, wake_clear);
1687 __raw_writel(bank->suspend_wakeup, wake_set);
1688 spin_unlock_irqrestore(&bank->lock, flags);
1689 }
1690
1691 return 0;
1692}
1693
1694static void omap_gpio_resume(void)
1695{
1696 int i;
1697
1698 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1699 return;
1700
1701 for (i = 0; i < gpio_bank_count; i++) {
1702 struct gpio_bank *bank = &gpio_bank[i];
1703 void __iomem *wake_clear;
1704 void __iomem *wake_set;
1705 unsigned long flags;
1706
1707 switch (bank->method) {
1708#ifdef CONFIG_ARCH_OMAP16XX
1709 case METHOD_GPIO_1610:
1710 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1711 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1712 break;
1713#endif
1714#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1715 case METHOD_GPIO_24XX:
1716 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1717 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1718 break;
1719#endif
1720#ifdef CONFIG_ARCH_OMAP4
1721 case METHOD_GPIO_44XX:
1722 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1723 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1724 break;
1725#endif
1726 default:
1727 continue;
1728 }
1729
1730 spin_lock_irqsave(&bank->lock, flags);
1731 __raw_writel(0xffffffff, wake_clear);
1732 __raw_writel(bank->saved_wakeup, wake_set);
1733 spin_unlock_irqrestore(&bank->lock, flags);
1734 }
1735}
1736
1737static struct syscore_ops omap_gpio_syscore_ops = {
1738 .suspend = omap_gpio_suspend,
1739 .resume = omap_gpio_resume,
1740};
1741
1742#endif
1743
1744#ifdef CONFIG_ARCH_OMAP2PLUS
1745
1746static int workaround_enabled;
1747
1748void omap2_gpio_prepare_for_idle(int off_mode)
1749{
1750 int i, c = 0;
1751 int min = 0;
1752
1753 if (cpu_is_omap34xx())
1754 min = 1;
1755
1756 for (i = min; i < gpio_bank_count; i++) {
1757 struct gpio_bank *bank = &gpio_bank[i];
1758 u32 l1 = 0, l2 = 0;
1759 int j;
1760
1761 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1762 clk_disable(bank->dbck);
1763
1764 if (!off_mode)
1765 continue;
1766
1767 /* If going to OFF, remove triggering for all
1768 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1769 * generated. See OMAP2420 Errata item 1.101. */
1770 if (!(bank->enabled_non_wakeup_gpios))
1771 continue;
1772
1773 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1774 bank->saved_datain = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_DATAIN);
1776 l1 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_FALLINGDETECT);
1778 l2 = __raw_readl(bank->base +
1779 OMAP24XX_GPIO_RISINGDETECT);
1780 }
1781
1782 if (cpu_is_omap44xx()) {
1783 bank->saved_datain = __raw_readl(bank->base +
1784 OMAP4_GPIO_DATAIN);
1785 l1 = __raw_readl(bank->base +
1786 OMAP4_GPIO_FALLINGDETECT);
1787 l2 = __raw_readl(bank->base +
1788 OMAP4_GPIO_RISINGDETECT);
1789 }
1790
1791 bank->saved_fallingdetect = l1;
1792 bank->saved_risingdetect = l2;
1793 l1 &= ~bank->enabled_non_wakeup_gpios;
1794 l2 &= ~bank->enabled_non_wakeup_gpios;
1795
1796 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1797 __raw_writel(l1, bank->base +
1798 OMAP24XX_GPIO_FALLINGDETECT);
1799 __raw_writel(l2, bank->base +
1800 OMAP24XX_GPIO_RISINGDETECT);
1801 }
1802
1803 if (cpu_is_omap44xx()) {
1804 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1805 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1806 }
1807
1808 c++;
1809 }
1810 if (!c) {
1811 workaround_enabled = 0;
1812 return;
1813 }
1814 workaround_enabled = 1;
1815}
1816
1817void omap2_gpio_resume_after_idle(void)
1818{
1819 int i;
1820 int min = 0;
1821
1822 if (cpu_is_omap34xx())
1823 min = 1;
1824 for (i = min; i < gpio_bank_count; i++) {
1825 struct gpio_bank *bank = &gpio_bank[i];
1826 u32 l = 0, gen, gen0, gen1;
1827 int j;
1828
1829 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1830 clk_enable(bank->dbck);
1831
1832 if (!workaround_enabled)
1833 continue;
1834
1835 if (!(bank->enabled_non_wakeup_gpios))
1836 continue;
1837
1838 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
1840 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1841 __raw_writel(bank->saved_risingdetect,
1842 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1843 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1844 }
1845
1846 if (cpu_is_omap44xx()) {
1847 __raw_writel(bank->saved_fallingdetect,
1848 bank->base + OMAP4_GPIO_FALLINGDETECT);
1849 __raw_writel(bank->saved_risingdetect,
1850 bank->base + OMAP4_GPIO_RISINGDETECT);
1851 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1852 }
1853
1854 /* Check if any of the non-wakeup interrupt GPIOs have changed
1855 * state. If so, generate an IRQ by software. This is
1856 * horribly racy, but it's the best we can do to work around
1857 * this silicon bug. */
1858 l ^= bank->saved_datain;
1859 l &= bank->enabled_non_wakeup_gpios;
1860
1861 /*
1862 * No need to generate IRQs for the rising edge for gpio IRQs
1863 * configured with falling edge only; and vice versa.
1864 */
1865 gen0 = l & bank->saved_fallingdetect;
1866 gen0 &= bank->saved_datain;
1867
1868 gen1 = l & bank->saved_risingdetect;
1869 gen1 &= ~(bank->saved_datain);
1870
1871 /* FIXME: Consider GPIO IRQs with level detections properly! */
1872 gen = l & (~(bank->saved_fallingdetect) &
1873 ~(bank->saved_risingdetect));
1874 /* Consider all GPIO IRQs needed to be updated */
1875 gen |= gen0 | gen1;
1876
1877 if (gen) {
1878 u32 old0, old1;
1879
1880 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1881 old0 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT0);
1883 old1 = __raw_readl(bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT1);
1885 __raw_writel(old0 | gen, bank->base +
1886 OMAP24XX_GPIO_LEVELDETECT0);
1887 __raw_writel(old1 | gen, bank->base +
1888 OMAP24XX_GPIO_LEVELDETECT1);
1889 __raw_writel(old0, bank->base +
1890 OMAP24XX_GPIO_LEVELDETECT0);
1891 __raw_writel(old1, bank->base +
1892 OMAP24XX_GPIO_LEVELDETECT1);
1893 }
1894
1895 if (cpu_is_omap44xx()) {
1896 old0 = __raw_readl(bank->base +
1897 OMAP4_GPIO_LEVELDETECT0);
1898 old1 = __raw_readl(bank->base +
1899 OMAP4_GPIO_LEVELDETECT1);
1900 __raw_writel(old0 | l, bank->base +
1901 OMAP4_GPIO_LEVELDETECT0);
1902 __raw_writel(old1 | l, bank->base +
1903 OMAP4_GPIO_LEVELDETECT1);
1904 __raw_writel(old0, bank->base +
1905 OMAP4_GPIO_LEVELDETECT0);
1906 __raw_writel(old1, bank->base +
1907 OMAP4_GPIO_LEVELDETECT1);
1908 }
1909 }
1910 }
1911
1912}
1913
1914#endif
1915
1916#ifdef CONFIG_ARCH_OMAP3
1917/* save the registers of bank 2-6 */
1918void omap_gpio_save_context(void)
1919{
1920 int i;
1921
1922 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1923 for (i = 1; i < gpio_bank_count; i++) {
1924 struct gpio_bank *bank = &gpio_bank[i];
1925 gpio_context[i].irqenable1 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1927 gpio_context[i].irqenable2 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1929 gpio_context[i].wake_en =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1931 gpio_context[i].ctrl =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1933 gpio_context[i].oe =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1935 gpio_context[i].leveldetect0 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1937 gpio_context[i].leveldetect1 =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1939 gpio_context[i].risingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1941 gpio_context[i].fallingdetect =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1943 gpio_context[i].dataout =
1944 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1945 }
1946}
1947
1948/* restore the required registers of bank 2-6 */
1949void omap_gpio_restore_context(void)
1950{
1951 int i;
1952
1953 for (i = 1; i < gpio_bank_count; i++) {
1954 struct gpio_bank *bank = &gpio_bank[i];
1955 __raw_writel(gpio_context[i].irqenable1,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1957 __raw_writel(gpio_context[i].irqenable2,
1958 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1959 __raw_writel(gpio_context[i].wake_en,
1960 bank->base + OMAP24XX_GPIO_WAKE_EN);
1961 __raw_writel(gpio_context[i].ctrl,
1962 bank->base + OMAP24XX_GPIO_CTRL);
1963 __raw_writel(gpio_context[i].oe,
1964 bank->base + OMAP24XX_GPIO_OE);
1965 __raw_writel(gpio_context[i].leveldetect0,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1967 __raw_writel(gpio_context[i].leveldetect1,
1968 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1969 __raw_writel(gpio_context[i].risingdetect,
1970 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1971 __raw_writel(gpio_context[i].fallingdetect,
1972 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1973 __raw_writel(gpio_context[i].dataout,
1974 bank->base + OMAP24XX_GPIO_DATAOUT);
1975 }
1976}
1977#endif
1978
1979static struct platform_driver omap_gpio_driver = {
1980 .probe = omap_gpio_probe,
1981 .driver = {
1982 .name = "omap_gpio",
1983 },
1984};
1985
1986/*
1987 * gpio driver register needs to be done before
1988 * machine_init functions access gpio APIs.
1989 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1990 */
1991static int __init omap_gpio_drv_reg(void)
1992{
1993 return platform_driver_register(&omap_gpio_driver);
1994}
1995postcore_initcall(omap_gpio_drv_reg);
1996
1997static int __init omap_gpio_sysinit(void)
1998{
1999 mpuio_init();
2000
2001#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2002 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2003 register_syscore_ops(&omap_gpio_syscore_ops);
2004#endif
2005
2006 return 0;
2007}
2008
2009arch_initcall(omap_gpio_sysinit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 20:48:47 -0400