ARM: kvm: use inner-shareable barriers after TLB flushing

When flushing the TLB at PL2 in response to remapping at stage-2 or VMID
rollover, we have a dsb instruction to ensure completion of the command
before continuing.

Since we only care about other processors for TLB invalidation, use the
inner-shareable variant of the dsb instruction instead.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

2 files changed, 3 insertions, 3 deletions

diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index f048338135f7..1b9844d369cc 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -142,7 +142,7 @@ target:	@ We're now in the trampoline code, switch page tables
 
         @ Invalidate the old TLBs
         mcr     p15, 4, r0, c8, c7, 0   @ TLBIALLH
-        dsb
+        dsb     ish
 
         eret
 
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index 16cd4ba5d7fd..f85052facffc 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -55,7 +55,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
         mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
         isb
         mcr     p15, 0, r0, c8, c3, 0   @ TLBIALLIS (rt ignored)
-        dsb
+        dsb     ish
         isb
         mov     r2, #0
         mov     r3, #0
@@ -79,7 +79,7 @@ ENTRY(__kvm_flush_vm_context)
         mcr     p15, 4, r0, c8, c3, 4
         /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */
         mcr     p15, 0, r0, c7, c1, 0
-        dsb
+        dsb     ish
         isb                             @ Not necessary if followed by eret
 
         bx      lr