Merge remote-tracking branch 'kumar/next' into merge

22 files changed, 688 insertions, 45 deletions

diff --git a/arch/powerpc/boot/dts/p1020mbg-pc.dtsi b/arch/powerpc/boot/dts/p1020mbg-pc.dtsi
new file mode 100644
index 000000000000..a24699cfea9c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020mbg-pc.dtsi
@@ -0,0 +1,151 @@
+/*
+ * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x4000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* 128KB for DTB Image */
+                        reg = <0x0 0x00020000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@20000 {
+                        /* 3.875 MB for Linux Kernel Image */
+                        reg = <0x00020000 0x003e0000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 58MB for Root file System */
+                        reg = <0x00400000 0x03a00000>;
+                        label = "NOR Root File System";
+                };
+
+                partition@3e00000 {
+                        /* This location must not be altered  */
+                        /* 1M for Vitesse 7385 Switch firmware */
+                        reg = <0x3e00000 0x00100000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@3f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x03f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        L2switch@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "vitesse-7385";
+                reg = <0x2 0x0 0x20000>;
+        };
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        /* USB2 is shared with localbus, so it must be disabled
+           by default. We can't put 'status = "disabled";' here
+           since U-Boot doesn't clear the status property when
+           it enables USB2. OTOH, U-Boot does create a new node
+           when there isn't any. So, just comment it out.
+        */
+        usb@23000 {
+                status = "disabled";
+                phy_type = "ulpi";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
new file mode 100644
index 000000000000..ab8f076eae90
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
@@ -0,0 +1,89 @@
+/*
+ * P1020 MBG-PC Device Tree Source (32-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020MBG-PC";
+        compatible = "fsl,P1020MBG-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0x0 0xffe05000 0x0 0x1000>;
+
+                /* NOR and L2 switch */
+                ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+                          0x1 0x0 0x0 0xffa00000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                reg = <0x0 0xffe09000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0x0 0xffe0a000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020mbg-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts b/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts
new file mode 100644
index 000000000000..9e9f401419b1
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts
@@ -0,0 +1,89 @@
+/*
+ * P1020 MBG-PC Device Tree Source (36-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020MBG-PC";
+        compatible = "fsl,P1020MBG-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0x0 0x1000>;
+
+                /* NOR and L2 switch */
+                ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+                          0x1 0x0 0xf 0xffa00000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020mbg-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020utm-pc.dtsi b/arch/powerpc/boot/dts/p1020utm-pc.dtsi
new file mode 100644
index 000000000000..7ea85eabcc5c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020utm-pc.dtsi
@@ -0,0 +1,140 @@
+/*
+ * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x2000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* 256KB for DTB Image */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@40000 {
+                        /* 3.75 MB for Linux Kernel Image */
+                        reg = <0x00040000 0x003c0000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 27MB for Root file System */
+                        reg = <0x00400000 0x01b00000>;
+                        label = "NOR Root File System";
+                };
+
+                partition@1f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x01f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <1 1 0 0>;
+                        reg = <0x2>;
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                phy-handle = <&phy2>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        /* USB2 is shared with localbus, so it must be disabled
+           by default. We can't put 'status = "disabled";' here
+           since U-Boot doesn't clear the status property when
+           it enables USB2. OTOH, U-Boot does create a new node
+           when there isn't any. So, just comment it out.
+        */
+        usb@23000 {
+                status = "disabled";
+                phy_type = "ulpi";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020utm-pc_32b.dts b/arch/powerpc/boot/dts/p1020utm-pc_32b.dts
new file mode 100644
index 000000000000..4bfdd8971cdb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020utm-pc_32b.dts
@@ -0,0 +1,89 @@
+/*
+ * P1020 UTM-PC Device Tree Source (32-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020UTM-PC";
+        compatible = "fsl,P1020UTM-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0x0 0xffe05000 0x0 0x1000>;
+
+                /* NOR */
+                ranges = <0x0 0x0 0x0 0xec000000 0x02000000
+                          0x1 0x0 0x0 0xffa00000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                reg = <0x0 0xffe09000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0x0 0xffe0a000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020utm-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020utm-pc_36b.dts b/arch/powerpc/boot/dts/p1020utm-pc_36b.dts
new file mode 100644
index 000000000000..abec53557501
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020utm-pc_36b.dts
@@ -0,0 +1,89 @@
+/*
+ * P1020 UTM-PC Device Tree Source (36-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020UTM-PC";
+        compatible = "fsl,P1020UTM-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0x0 0x1000>;
+
+                /* NOR */
+                ranges = <0x0 0x0 0xf 0xec000000 0x02000000
+                          0x1 0x0 0xf 0xffa00000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0x0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020utm-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 4f957db01230..285213976a7f 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -135,7 +135,6 @@
                 reg = <0xf 0xfe200000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                fsl,msi = <&msi0>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -151,7 +150,6 @@
                 reg = <0xf 0xfe201000 0 0x1000>;
                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                fsl,msi = <&msi1>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -167,7 +165,6 @@
                 reg = <0xf 0xfe202000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index f469145abaeb..22a215e94162 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -173,7 +173,6 @@
                 reg = <0xf 0xfe200000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                fsl,msi = <&msi0>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -189,7 +188,6 @@
                 reg = <0xf 0xfe201000 0 0x1000>;
                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                fsl,msi = <&msi1>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -205,7 +203,6 @@
                 reg = <0xf 0xfe202000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -221,7 +218,6 @@
                 reg = <0xf 0xfe203000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
index 529042e4b9a2..9ae875c8a211 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -212,7 +212,6 @@
                 reg = <0xf 0xfe200000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                fsl,msi = <&msi0>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -228,7 +227,6 @@
                 reg = <0xf 0xfe201000 0 0x1000>;
                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                fsl,msi = <&msi1>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 6d60e54e50a0..3e204609d02e 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -141,7 +141,6 @@
                 reg = <0xf 0xfe200000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                fsl,msi = <&msi0>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -157,7 +156,6 @@
                 reg = <0xf 0xfe201000 0 0x1000>;
                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                fsl,msi = <&msi1>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -173,7 +171,6 @@
                 reg = <0xf 0xfe202000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index 1c250684c902..27c07ed6adc1 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -173,7 +173,6 @@
                 reg = <0xf 0xfe200000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                fsl,msi = <&msi0>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -189,7 +188,6 @@
                 reg = <0xf 0xfe201000 0 0x1000>;
                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                fsl,msi = <&msi1>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -205,7 +203,6 @@
                 reg = <0xf 0xfe202000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
@@ -221,7 +218,6 @@
                 reg = <0xf 0xfe203000 0 0x1000>;
                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
-                fsl,msi = <&msi2>;
                 pcie@0 {
                         ranges = <0x02000000 0 0xe0000000
                                   0x02000000 0 0xe0000000
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index f8aef205d222..91db656294e8 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -116,6 +116,7 @@ CONFIG_SERIAL_8250_RSA=y
 CONFIG_HW_RANDOM=y
 CONFIG_NVRAM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MPC=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 82b13bfcf3c0..6798343580f0 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -71,6 +71,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MPC=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 # CONFIG_HID_SUPPORT is not set
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cc87a8441566..d6b6df5e8743 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -117,6 +117,7 @@ CONFIG_SERIAL_8250_RSA=y
 CONFIG_SERIAL_QE=m
 CONFIG_NVRAM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
 CONFIG_SPI=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 48d6682f2434..5b0e2926becd 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -119,6 +119,7 @@ CONFIG_SERIAL_8250_RSA=y
 CONFIG_SERIAL_QE=m
 CONFIG_NVRAM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
 CONFIG_SPI=y
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index f3b0c2cc9fea..976835d8f22e 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -134,10 +134,15 @@
  * whether they will be clobbered.
  *
  * Note that r11 can be used as an output parameter.
+ *
+ * The "memory" clobber is only necessary for hcalls where the Hypervisor
+ * will read or write guest memory. However, we add it to all hcalls because
+ * the impact is minimal, and we want to ensure that it's present for the
+ * hcalls that need it.
 */
 
 /* List of common clobbered registers.  Do not use this macro. */
-#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc"
+#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory"
 
 #define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
 #define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index ce04530d2000..aa4c488589ce 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -16,15 +16,6 @@
 #define __ASM_POWERPC_FSL_GUTS_H__
 #ifdef __KERNEL__
 
-/*
- * These #ifdefs are safe because it's not possible to build a kernel that
- * runs on e500 and e600 cores.
- */
-
-#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
-#error Only 85xx and 86xx SOCs are supported
-#endif
-
 /**
  * Global Utility Registers.
  *
@@ -36,11 +27,7 @@
  * different names.  In these cases, one name is chosen to avoid extraneous
  * #ifdefs.
  */
-#ifdef CONFIG_PPC_85xx
-struct ccsr_guts_85xx {
-#else
-struct ccsr_guts_86xx {
-#endif
+struct ccsr_guts {
         __be32  porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
         __be32  porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
         __be32  porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
@@ -77,11 +64,8 @@ struct ccsr_guts_86xx {
         u8      res0a8[0xb0 - 0xa8];
         __be32  rstcr;          /* 0x.00b0 - Reset Control Register */
         u8      res0b4[0xc0 - 0xb4];
-#ifdef CONFIG_PPC_85xx
-        __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register */
-#else
-        __be32  elbcvselcr;     /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
-#endif
+        __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register
+                                             Called 'elbcvselcr' on 86xx SOCs */
         u8      res0c4[0x224 - 0xc4];
         __be32  iodelay1;       /* 0x.0224 - IO delay control register 1 */
         __be32  iodelay2;       /* 0x.0228 - IO delay control register 2 */
@@ -136,7 +120,7 @@ struct ccsr_guts_86xx {
  * ch: The channel on the DMA controller (0, 1, 2, or 3)
  * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
  */
-static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
+static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
         unsigned int co, unsigned int ch, unsigned int device)
 {
         unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
@@ -172,7 +156,7 @@ static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
  * ch: The channel on the DMA controller (0, 1, 2, or 3)
  * value: the new value for the bit (0 or 1)
  */
-static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts,
+static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
         unsigned int co, unsigned int ch, unsigned int value)
 {
         if ((ch == 0) || (ch == 3)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 3754ddc00af7..9a6f04406e0d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -270,7 +270,7 @@ static void __init mpc85xx_mds_qe_init(void)
 
         if (machine_is(p1021_mds)) {
 
-                struct ccsr_guts_85xx __iomem *guts;
+                struct ccsr_guts __iomem *guts;
 
                 np = of_find_node_by_name(NULL, "global-utilities");
                 if (np) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 9848f9e39853..313fce4f5574 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -127,7 +127,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
         if (machine_is(p1025_rdb)) {
 
-                struct ccsr_guts_85xx __iomem *guts;
+                struct ccsr_guts __iomem *guts;
 
                 np = of_find_node_by_name(NULL, "global-utilities");
                 if (np) {
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 0fe88e39945e..e74b7cde9aee 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -150,7 +150,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 {
         struct device_node *guts_node;
         struct device_node *indirect_node = NULL;
-        struct ccsr_guts_85xx __iomem *guts;
+        struct ccsr_guts __iomem *guts;
         u8 __iomem *lbc_lcs0_ba = NULL;
         u8 __iomem *lbc_lcs1_ba = NULL;
         u8 b;
@@ -269,7 +269,7 @@ exit:
 void p1022ds_set_pixel_clock(unsigned int pixclock)
 {
         struct device_node *guts_np = NULL;
-        struct ccsr_guts_85xx __iomem *guts;
+        struct ccsr_guts __iomem *guts;
         unsigned long freq;
         u64 temp;
         u32 pxclk;
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index bbc615206c67..62cd3c555bfb 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -225,7 +225,7 @@ void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 {
         struct device_node *guts_np = NULL;
-        struct ccsr_guts_86xx __iomem *guts;
+        struct ccsr_guts __iomem *guts;
         unsigned long freq;
         u64 temp;
         u32 pxclk;
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index ceb09cbd2329..818e763f8265 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2006-2010 Freescale Semicondutor, Inc. All rights reserved.
  *
  * Authors:     Shlomi Gridish <gridish@freescale.com>
  *              Li Yang <leoli@freescale.com>
@@ -266,7 +266,19 @@ EXPORT_SYMBOL(qe_clock_source);
 static void qe_snums_init(void)
 {
         int i;
-        static const u8 snum_init[] = {
+        static const u8 snum_init_76[] = {
+                0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
+                0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
+                0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
+                0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
+                0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
+                0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
+                0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
+                0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
+                0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
+                0xF4, 0xF5, 0xFC, 0xFD,
+        };
+        static const u8 snum_init_46[] = {
                 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
                 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
                 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
@@ -274,9 +286,15 @@ static void qe_snums_init(void)
                 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
                 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
         };
+        static const u8 *snum_init;
 
         qe_num_of_snum = qe_get_num_of_snums();
 
+        if (qe_num_of_snum == 76)
+                snum_init = snum_init_76;
+        else
+                snum_init = snum_init_46;
+
         for (i = 0; i < qe_num_of_snum; i++) {
                 snums[i].num = snum_init[i];
                 snums[i].state = QE_SNUM_STATE_FREE;