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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-09 17:36:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-09 17:36:27 -0400
commite30f4192456971623b40c97a027346b69457ef69 (patch)
tree11a9a7ccfdc18f5e448661f65b8bbf2a1007b79a /arch
parentb32729b1eeae7ef8f5709923b36b5a0906d213df (diff)
parenteacd0e950dc2100af54f2a94ae29105bf48ab921 (diff)
Merge tag 'arc-v3.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC port updates from Vineet Gupta: "Support for two new platforms based on ARC700: - Abilis TB10x SoC [Chritisian/Pierrick] - Simulator only System-C Model [Mischa] ARC specific MM improvements: - Avoid full TLB flush (ASID increment) on munmap (even single page) - VIPT Cache Flushing improvements + Delayed dcache flush for non-aliasing dcache (big performance boost) + icache flush aliasing agnostic (no need to kill all possible aliases) Others: - Avoid needless rebuild of DTB files for every kernel build - Remove builtin cmdline as that is already provided by DeviceTree/bootargs - Fixing unaligned access emulation corner case - checkpatch fixes [Sachin] - Various fixlets [Noam] - Minor build failures/cleanups" * tag 'arc-v3.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (35 commits) ARC: [mm] Lazy D-cache flush (non aliasing VIPT) ARC: [mm] micro-optimize page size icache invalidate ARC: [mm] remove the pessimistic all-alias-invalidate icache helpers ARC: [mm] consolidate icache/dcache sync code ARC: [mm] optimise icache flush for kernel mappings ARC: [mm] optimise icache flush for user mappings ARC: [mm] optimize needless full mm TLB flush on munmap ARC: Add support for nSIM OSCI System C model ARC: [TB10x] Adapt device tree to new compatible string ARC: [TB10x] Add support for TB10x platform ARC: [TB10x] Device tree of TB100 and TB101 Development Kits ARC: Prepare interrupt code for external controllers ARC: Allow embedded arc-intc to be properly placed in DT intc hierarchy ARC: [cmdline] Don't overwrite u-boot provided bootargs ARC: [cmdline] Remove CONFIG_CMDLINE ARC: [plat-arcfpga] defconfig update ARC: unaligned access emulation broken if callee-reg dest of LD/ST ARC: unaligned access emulation error handling consolidation ARC: Debug/crash-printing Improvements ARC: fix typo with clock speed ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arc/Kconfig31
-rw-r--r--arch/arc/Makefile15
-rw-r--r--arch/arc/boot/Makefile19
-rw-r--r--arch/arc/boot/dts/Makefile4
-rw-r--r--arch/arc/boot/dts/abilis_tb100.dtsi340
-rw-r--r--arch/arc/boot/dts/abilis_tb100_dvk.dts127
-rw-r--r--arch/arc/boot/dts/abilis_tb101.dtsi349
-rw-r--r--arch/arc/boot/dts/abilis_tb101_dvk.dts127
-rw-r--r--arch/arc/boot/dts/abilis_tb10x.dtsi247
-rw-r--r--arch/arc/boot/dts/nsimosci.dts77
-rw-r--r--arch/arc/configs/fpga_defconfig3
-rw-r--r--arch/arc/configs/nsimosci_defconfig75
-rw-r--r--arch/arc/configs/tb10x_defconfig117
-rw-r--r--arch/arc/include/asm/cacheflush.h16
-rw-r--r--arch/arc/include/asm/irq.h3
-rw-r--r--arch/arc/include/asm/serial.h10
-rw-r--r--arch/arc/include/asm/tlb.h16
-rw-r--r--arch/arc/kernel/asm-offsets.c2
-rw-r--r--arch/arc/kernel/clk.c2
-rw-r--r--arch/arc/kernel/disasm.c2
-rw-r--r--arch/arc/kernel/entry.S8
-rw-r--r--arch/arc/kernel/irq.c25
-rw-r--r--arch/arc/kernel/kprobes.c1
-rw-r--r--arch/arc/kernel/module.c4
-rw-r--r--arch/arc/kernel/setup.c36
-rw-r--r--arch/arc/kernel/time.c1
-rw-r--r--arch/arc/kernel/traps.c24
-rw-r--r--arch/arc/kernel/troubleshoot.c50
-rw-r--r--arch/arc/mm/cache_arc700.c269
-rw-r--r--arch/arc/mm/extable.c4
-rw-r--r--arch/arc/mm/fault.c1
-rw-r--r--arch/arc/mm/init.c3
-rw-r--r--arch/arc/mm/ioremap.c2
-rw-r--r--arch/arc/mm/tlb.c32
-rw-r--r--arch/arc/plat-arcfpga/platform.c12
-rw-r--r--arch/arc/plat-tb10x/Kconfig36
-rw-r--r--arch/arc/plat-tb10x/Makefile21
-rw-r--r--arch/arc/plat-tb10x/tb10x.c71
38 files changed, 1840 insertions, 342 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index e6f4eca09ee3..491ae7923b10 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -16,8 +16,6 @@ config ARC
16 select GENERIC_FIND_FIRST_BIT 16 select GENERIC_FIND_FIRST_BIT
17 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 17 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_SHOW 18 select GENERIC_IRQ_SHOW
19 select GENERIC_KERNEL_EXECVE
20 select GENERIC_KERNEL_THREAD
21 select GENERIC_PENDING_IRQ if SMP 19 select GENERIC_PENDING_IRQ if SMP
22 select GENERIC_SMP_IDLE_THREAD 20 select GENERIC_SMP_IDLE_THREAD
23 select HAVE_ARCH_KGDB 21 select HAVE_ARCH_KGDB
@@ -61,9 +59,6 @@ config GENERIC_CALIBRATE_DELAY
61config GENERIC_HWEIGHT 59config GENERIC_HWEIGHT
62 def_bool y 60 def_bool y
63 61
64config BINFMT_ELF
65 def_bool y
66
67config STACKTRACE_SUPPORT 62config STACKTRACE_SUPPORT
68 def_bool y 63 def_bool y
69 select STACKTRACE 64 select STACKTRACE
@@ -82,6 +77,7 @@ menu "ARC Architecture Configuration"
82menu "ARC Platform/SoC/Board" 77menu "ARC Platform/SoC/Board"
83 78
84source "arch/arc/plat-arcfpga/Kconfig" 79source "arch/arc/plat-arcfpga/Kconfig"
80source "arch/arc/plat-tb10x/Kconfig"
85#New platform adds here 81#New platform adds here
86 82
87endmenu 83endmenu
@@ -134,9 +130,6 @@ if SMP
134config ARC_HAS_COH_CACHES 130config ARC_HAS_COH_CACHES
135 def_bool n 131 def_bool n
136 132
137config ARC_HAS_COH_LLSC
138 def_bool n
139
140config ARC_HAS_COH_RTSC 133config ARC_HAS_COH_RTSC
141 def_bool n 134 def_bool n
142 135
@@ -304,6 +297,9 @@ config ARC_FPU_SAVE_RESTORE
304 based on actual usage of FPU by a task. Thus our implemn does 297 based on actual usage of FPU by a task. Thus our implemn does
305 this for all tasks in system. 298 this for all tasks in system.
306 299
300config ARC_CANT_LLSC
301 def_bool n
302
307menuconfig ARC_CPU_REL_4_10 303menuconfig ARC_CPU_REL_4_10
308 bool "Enable support for Rel 4.10 features" 304 bool "Enable support for Rel 4.10 features"
309 default n 305 default n
@@ -314,9 +310,7 @@ menuconfig ARC_CPU_REL_4_10
314config ARC_HAS_LLSC 310config ARC_HAS_LLSC
315 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 311 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
316 default y 312 default y
317 depends on ARC_CPU_770 313 depends on ARC_CPU_770 && !ARC_CANT_LLSC
318 # if SMP, enable LLSC ONLY if ARC implementation has coherent atomics
319 depends on !SMP || ARC_HAS_COH_LLSC
320 314
321config ARC_HAS_SWAPE 315config ARC_HAS_SWAPE
322 bool "Insn: SWAPE (endian-swap)" 316 bool "Insn: SWAPE (endian-swap)"
@@ -415,13 +409,6 @@ config ARC_DBG_TLB_MISS_COUNT
415 Counts number of I and D TLB Misses and exports them via Debugfs 409 Counts number of I and D TLB Misses and exports them via Debugfs
416 The counters can be cleared via Debugfs as well 410 The counters can be cleared via Debugfs as well
417 411
418config CMDLINE
419 string "Kernel command line to built-in"
420 default "print-fatal-signals=1"
421 help
422 The default command line which will be appended to the optional
423 u-boot provided command line (see below)
424
425config CMDLINE_UBOOT 412config CMDLINE_UBOOT
426 bool "Support U-boot kernel command line passing" 413 bool "Support U-boot kernel command line passing"
427 default n 414 default n
@@ -430,8 +417,8 @@ config CMDLINE_UBOOT
430 command line from the U-boot environment to the Linux kernel then 417 command line from the U-boot environment to the Linux kernel then
431 switch this option on. 418 switch this option on.
432 ARC U-boot will setup the cmdline in RAM/flash and set r2 to point 419 ARC U-boot will setup the cmdline in RAM/flash and set r2 to point
433 to it. kernel startup code will copy the string into cmdline buffer 420 to it. kernel startup code will append this to DeviceTree
434 and also append CONFIG_CMDLINE. 421 /bootargs provided cmdline args.
435 422
436config ARC_BUILTIN_DTB_NAME 423config ARC_BUILTIN_DTB_NAME
437 string "Built in DTB" 424 string "Built in DTB"
@@ -441,6 +428,10 @@ config ARC_BUILTIN_DTB_NAME
441 428
442source "kernel/Kconfig.preempt" 429source "kernel/Kconfig.preempt"
443 430
431menu "Executable file formats"
432source "fs/Kconfig.binfmt"
433endmenu
434
444endmenu # "ARC Architecture Configuration" 435endmenu # "ARC Architecture Configuration"
445 436
446source "mm/Kconfig" 437source "mm/Kconfig"
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 92379c7cbc1a..183397fd289e 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -8,6 +8,10 @@
8 8
9UTS_MACHINE := arc 9UTS_MACHINE := arc
10 10
11ifeq ($(CROSS_COMPILE),)
12CROSS_COMPILE := arc-elf32-
13endif
14
11KBUILD_DEFCONFIG := fpga_defconfig 15KBUILD_DEFCONFIG := fpga_defconfig
12 16
13cflags-y += -mA7 -fno-common -pipe -fno-builtin -D__linux__ 17cflags-y += -mA7 -fno-common -pipe -fno-builtin -D__linux__
@@ -87,20 +91,23 @@ core-y += arch/arc/
87core-y += arch/arc/boot/dts/ 91core-y += arch/arc/boot/dts/
88 92
89core-$(CONFIG_ARC_PLAT_FPGA_LEGACY) += arch/arc/plat-arcfpga/ 93core-$(CONFIG_ARC_PLAT_FPGA_LEGACY) += arch/arc/plat-arcfpga/
94core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
90 95
91drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ 96drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/
92 97
93libs-y += arch/arc/lib/ $(LIBGCC) 98libs-y += arch/arc/lib/ $(LIBGCC)
94 99
100boot := arch/arc/boot
101
95#default target for make without any arguements. 102#default target for make without any arguements.
96KBUILD_IMAGE := bootpImage 103KBUILD_IMAGE := bootpImage
97 104
98all: $(KBUILD_IMAGE) 105all: $(KBUILD_IMAGE)
99boot := arch/arc/boot
100
101bootpImage: vmlinux 106bootpImage: vmlinux
102 107
103uImage: vmlinux 108boot_targets += uImage uImage.bin uImage.gz
109
110$(boot_targets): vmlinux
104 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ 111 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
105 112
106%.dtb %.dtb.S %.dtb.o: scripts 113%.dtb %.dtb.S %.dtb.o: scripts
diff --git a/arch/arc/boot/Makefile b/arch/arc/boot/Makefile
index 7d514c24e095..e597cb34c16a 100644
--- a/arch/arc/boot/Makefile
+++ b/arch/arc/boot/Makefile
@@ -3,7 +3,6 @@ targets := vmlinux.bin vmlinux.bin.gz uImage
3# uImage build relies on mkimage being availble on your host for ARC target 3# uImage build relies on mkimage being availble on your host for ARC target
4# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage 4# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
5# and make sure it's reacable from your PATH 5# and make sure it's reacable from your PATH
6MKIMAGE := $(srctree)/scripts/mkuboot.sh
7 6
8OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S 7OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
9 8
@@ -12,7 +11,12 @@ LINUX_START_TEXT = $$(readelf -h vmlinux | \
12 11
13UIMAGE_LOADADDR = $(CONFIG_LINUX_LINK_BASE) 12UIMAGE_LOADADDR = $(CONFIG_LINUX_LINK_BASE)
14UIMAGE_ENTRYADDR = $(LINUX_START_TEXT) 13UIMAGE_ENTRYADDR = $(LINUX_START_TEXT)
15UIMAGE_COMPRESSION = gzip 14
15suffix-y := bin
16suffix-$(CONFIG_KERNEL_GZIP) := gz
17
18targets += uImage uImage.bin uImage.gz
19extra-y += vmlinux.bin vmlinux.bin.gz
16 20
17$(obj)/vmlinux.bin: vmlinux FORCE 21$(obj)/vmlinux.bin: vmlinux FORCE
18 $(call if_changed,objcopy) 22 $(call if_changed,objcopy)
@@ -20,7 +24,12 @@ $(obj)/vmlinux.bin: vmlinux FORCE
20$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE 24$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
21 $(call if_changed,gzip) 25 $(call if_changed,gzip)
22 26
23$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE 27$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
24 $(call if_changed,uimage) 28 $(call if_changed,uimage,none)
29
30$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
31 $(call if_changed,uimage,gzip)
25 32
26PHONY += FORCE 33$(obj)/uImage: $(obj)/uImage.$(suffix-y)
34 @ln -sf $(notdir $<) $@
35 @echo ' Image $@ is ready'
diff --git a/arch/arc/boot/dts/Makefile b/arch/arc/boot/dts/Makefile
index 5776835d583f..faf240e29ec2 100644
--- a/arch/arc/boot/dts/Makefile
+++ b/arch/arc/boot/dts/Makefile
@@ -8,6 +8,8 @@ endif
8obj-y += $(builtindtb-y).dtb.o 8obj-y += $(builtindtb-y).dtb.o
9targets += $(builtindtb-y).dtb 9targets += $(builtindtb-y).dtb
10 10
11.SECONDARY: $(obj)/$(builtindtb-y).dtb.S
12
11dtbs: $(addprefix $(obj)/, $(builtindtb-y).dtb) 13dtbs: $(addprefix $(obj)/, $(builtindtb-y).dtb)
12 14
13clean-files := *.dtb 15clean-files := *.dtb *.dtb.S
diff --git a/arch/arc/boot/dts/abilis_tb100.dtsi b/arch/arc/boot/dts/abilis_tb100.dtsi
new file mode 100644
index 000000000000..941ad118a7e7
--- /dev/null
+++ b/arch/arc/boot/dts/abilis_tb100.dtsi
@@ -0,0 +1,340 @@
1/*
2 * Abilis Systems TB100 SOC device tree
3 *
4 * Copyright (C) Abilis Systems 2013
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/include/ "abilis_tb10x.dtsi"
23
24/* interrupt specifiers
25 * --------------------
26 * 0: rising, 1: low, 2: high, 3: falling,
27 */
28
29/ {
30 clock-frequency = <500000000>; /* 500 MHZ */
31
32 soc100 {
33 bus-frequency = <166666666>;
34
35 pll0: oscillator {
36 clock-frequency = <1000000000>;
37 };
38 cpu_clk: clkdiv_cpu {
39 clock-mult = <1>;
40 clock-div = <2>;
41 };
42 ahb_clk: clkdiv_ahb {
43 clock-mult = <1>;
44 clock-div = <6>;
45 };
46
47 iomux: iomux@FF10601c {
48 /* Port 1 */
49 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
50 pingrp = "mis0_pins";
51 };
52 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
53 pingrp = "mis1_pins";
54 };
55 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
56 pingrp = "gpioa_pins";
57 };
58 pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */
59 pingrp = "mip1_pins";
60 };
61 /* Port 2 */
62 pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */
63 pingrp = "mis2_pins";
64 };
65 pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */
66 pingrp = "mis3_pins";
67 };
68 pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */
69 pingrp = "gpioc_pins";
70 };
71 pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */
72 pingrp = "mip3_pins";
73 };
74 /* Port 3 */
75 pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */
76 pingrp = "mis4_pins";
77 };
78 pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */
79 pingrp = "mis5_pins";
80 };
81 pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */
82 pingrp = "gpioe_pins";
83 };
84 pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */
85 pingrp = "mip5_pins";
86 };
87 /* Port 4 */
88 pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */
89 pingrp = "mis6_pins";
90 };
91 pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */
92 pingrp = "mis7_pins";
93 };
94 pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */
95 pingrp = "gpiog_pins";
96 };
97 pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */
98 pingrp = "mip7_pins";
99 };
100 /* Port 5 */
101 pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */
102 pingrp = "gpioj_pins";
103 };
104 pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */
105 pingrp = "gpiok_pins";
106 };
107 pctl_ciplus: pctl-ciplus { /* CI+ interface */
108 pingrp = "ciplus_pins";
109 };
110 pctl_mcard: pctl-mcard { /* M-Card interface */
111 pingrp = "mcard_pins";
112 };
113 /* Port 6 */
114 pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */
115 pingrp = "mop_pins";
116 };
117 pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */
118 pingrp = "mos0_pins";
119 };
120 pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */
121 pingrp = "mos1_pins";
122 };
123 pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */
124 pingrp = "mos2_pins";
125 };
126 pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */
127 pingrp = "mos3_pins";
128 };
129 /* Port 7 */
130 pctl_uart0: pctl-uart0 { /* UART 0 */
131 pingrp = "uart0_pins";
132 };
133 pctl_uart1: pctl-uart1 { /* UART 1 */
134 pingrp = "uart1_pins";
135 };
136 pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */
137 pingrp = "gpiol_pins";
138 };
139 pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */
140 pingrp = "gpiom_pins";
141 };
142 /* Port 8 */
143 pctl_spi3: pctl-spi3 {
144 pingrp = "spi3_pins";
145 };
146 /* Port 9 */
147 pctl_spi1: pctl-spi1 {
148 pingrp = "spi1_pins";
149 };
150 pctl_gpio_n: pctl-gpio-n {
151 pingrp = "gpion_pins";
152 };
153 /* Unmuxed GPIOs */
154 pctl_gpio_b: pctl-gpio-b {
155 pingrp = "gpiob_pins";
156 };
157 pctl_gpio_d: pctl-gpio-d {
158 pingrp = "gpiod_pins";
159 };
160 pctl_gpio_f: pctl-gpio-f {
161 pingrp = "gpiof_pins";
162 };
163 pctl_gpio_h: pctl-gpio-h {
164 pingrp = "gpioh_pins";
165 };
166 pctl_gpio_i: pctl-gpio-i {
167 pingrp = "gpioi_pins";
168 };
169 };
170
171 gpioa: gpio@FF140000 {
172 compatible = "abilis,tb10x-gpio";
173 interrupt-controller;
174 #interrupt-cells = <1>;
175 interrupt-parent = <&tb10x_ictl>;
176 interrupts = <27 1>;
177 reg = <0xFF140000 0x1000>;
178 gpio-controller;
179 #gpio-cells = <1>;
180 gpio-base = <0>;
181 gpio-pins = <&pctl_gpio_a>;
182 };
183 gpiob: gpio@FF141000 {
184 compatible = "abilis,tb10x-gpio";
185 interrupt-controller;
186 #interrupt-cells = <1>;
187 interrupt-parent = <&tb10x_ictl>;
188 interrupts = <27 1>;
189 reg = <0xFF141000 0x1000>;
190 gpio-controller;
191 #gpio-cells = <1>;
192 gpio-base = <3>;
193 gpio-pins = <&pctl_gpio_b>;
194 };
195 gpioc: gpio@FF142000 {
196 compatible = "abilis,tb10x-gpio";
197 interrupt-controller;
198 #interrupt-cells = <1>;
199 interrupt-parent = <&tb10x_ictl>;
200 interrupts = <27 1>;
201 reg = <0xFF142000 0x1000>;
202 gpio-controller;
203 #gpio-cells = <1>;
204 gpio-base = <5>;
205 gpio-pins = <&pctl_gpio_c>;
206 };
207 gpiod: gpio@FF143000 {
208 compatible = "abilis,tb10x-gpio";
209 interrupt-controller;
210 #interrupt-cells = <1>;
211 interrupt-parent = <&tb10x_ictl>;
212 interrupts = <27 1>;
213 reg = <0xFF143000 0x1000>;
214 gpio-controller;
215 #gpio-cells = <1>;
216 gpio-base = <8>;
217 gpio-pins = <&pctl_gpio_d>;
218 };
219 gpioe: gpio@FF144000 {
220 compatible = "abilis,tb10x-gpio";
221 interrupt-controller;
222 #interrupt-cells = <1>;
223 interrupt-parent = <&tb10x_ictl>;
224 interrupts = <27 1>;
225 reg = <0xFF144000 0x1000>;
226 gpio-controller;
227 #gpio-cells = <1>;
228 gpio-base = <10>;
229 gpio-pins = <&pctl_gpio_e>;
230 };
231 gpiof: gpio@FF145000 {
232 compatible = "abilis,tb10x-gpio";
233 interrupt-controller;
234 #interrupt-cells = <1>;
235 interrupt-parent = <&tb10x_ictl>;
236 interrupts = <27 1>;
237 reg = <0xFF145000 0x1000>;
238 gpio-controller;
239 #gpio-cells = <1>;
240 gpio-base = <13>;
241 gpio-pins = <&pctl_gpio_f>;
242 };
243 gpiog: gpio@FF146000 {
244 compatible = "abilis,tb10x-gpio";
245 interrupt-controller;
246 #interrupt-cells = <1>;
247 interrupt-parent = <&tb10x_ictl>;
248 interrupts = <27 1>;
249 reg = <0xFF146000 0x1000>;
250 gpio-controller;
251 #gpio-cells = <1>;
252 gpio-base = <15>;
253 gpio-pins = <&pctl_gpio_g>;
254 };
255 gpioh: gpio@FF147000 {
256 compatible = "abilis,tb10x-gpio";
257 interrupt-controller;
258 #interrupt-cells = <1>;
259 interrupt-parent = <&tb10x_ictl>;
260 interrupts = <27 1>;
261 reg = <0xFF147000 0x1000>;
262 gpio-controller;
263 #gpio-cells = <1>;
264 gpio-base = <18>;
265 gpio-pins = <&pctl_gpio_h>;
266 };
267 gpioi: gpio@FF148000 {
268 compatible = "abilis,tb10x-gpio";
269 interrupt-controller;
270 #interrupt-cells = <1>;
271 interrupt-parent = <&tb10x_ictl>;
272 interrupts = <27 1>;
273 reg = <0xFF148000 0x1000>;
274 gpio-controller;
275 #gpio-cells = <1>;
276 gpio-base = <20>;
277 gpio-pins = <&pctl_gpio_i>;
278 };
279 gpioj: gpio@FF149000 {
280 compatible = "abilis,tb10x-gpio";
281 interrupt-controller;
282 #interrupt-cells = <1>;
283 interrupt-parent = <&tb10x_ictl>;
284 interrupts = <27 1>;
285 reg = <0xFF149000 0x1000>;
286 gpio-controller;
287 #gpio-cells = <1>;
288 gpio-base = <32>;
289 gpio-pins = <&pctl_gpio_j>;
290 };
291 gpiok: gpio@FF14a000 {
292 compatible = "abilis,tb10x-gpio";
293 interrupt-controller;
294 #interrupt-cells = <1>;
295 interrupt-parent = <&tb10x_ictl>;
296 interrupts = <27 1>;
297 reg = <0xFF14A000 0x1000>;
298 gpio-controller;
299 #gpio-cells = <1>;
300 gpio-base = <64>;
301 gpio-pins = <&pctl_gpio_k>;
302 };
303 gpiol: gpio@FF14b000 {
304 compatible = "abilis,tb10x-gpio";
305 interrupt-controller;
306 #interrupt-cells = <1>;
307 interrupt-parent = <&tb10x_ictl>;
308 interrupts = <27 1>;
309 reg = <0xFF14B000 0x1000>;
310 gpio-controller;
311 #gpio-cells = <1>;
312 gpio-base = <86>;
313 gpio-pins = <&pctl_gpio_l>;
314 };
315 gpiom: gpio@FF14c000 {
316 compatible = "abilis,tb10x-gpio";
317 interrupt-controller;
318 #interrupt-cells = <1>;
319 interrupt-parent = <&tb10x_ictl>;
320 interrupts = <27 1>;
321 reg = <0xFF14C000 0x1000>;
322 gpio-controller;
323 #gpio-cells = <1>;
324 gpio-base = <90>;
325 gpio-pins = <&pctl_gpio_m>;
326 };
327 gpion: gpio@FF14d000 {
328 compatible = "abilis,tb10x-gpio";
329 interrupt-controller;
330 #interrupt-cells = <1>;
331 interrupt-parent = <&tb10x_ictl>;
332 interrupts = <27 1>;
333 reg = <0xFF14D000 0x1000>;
334 gpio-controller;
335 #gpio-cells = <1>;
336 gpio-base = <94>;
337 gpio-pins = <&pctl_gpio_n>;
338 };
339 };
340};
diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts
new file mode 100644
index 000000000000..c0fd3623c393
--- /dev/null
+++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts
@@ -0,0 +1,127 @@
1/*
2 * Abilis Systems TB100 Development Kit PCB device tree
3 *
4 * Copyright (C) Abilis Systems 2013
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/dts-v1/;
23
24/include/ "abilis_tb100.dtsi"
25
26/ {
27 chosen {
28 bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
29 };
30
31 aliases { };
32
33 memory {
34 device_type = "memory";
35 reg = <0x80000000 0x08000000>; /* 128M */
36 };
37
38 soc100 {
39 uart@FF100000 {
40 pinctrl-names = "abilis,simple-default";
41 pinctrl-0 = <&pctl_uart0>;
42 };
43 ethernet@FE100000 {
44 phy-mode = "rgmii";
45 };
46
47 i2c0: i2c@FF120000 {
48 sda-hold-time = <432>;
49 };
50 i2c1: i2c@FF121000 {
51 sda-hold-time = <432>;
52 };
53 i2c2: i2c@FF122000 {
54 sda-hold-time = <432>;
55 };
56 i2c3: i2c@FF123000 {
57 sda-hold-time = <432>;
58 };
59 i2c4: i2c@FF124000 {
60 sda-hold-time = <432>;
61 };
62
63 leds {
64 compatible = "gpio-leds";
65 power {
66 label = "Power";
67 gpios = <&gpioi 0>;
68 linux,default-trigger = "default-on";
69 };
70 heartbeat {
71 label = "Heartbeat";
72 gpios = <&gpioi 1>;
73 linux,default-trigger = "heartbeat";
74 };
75 led2 {
76 label = "LED2";
77 gpios = <&gpioi 2>;
78 default-state = "off";
79 };
80 led3 {
81 label = "LED3";
82 gpios = <&gpioi 3>;
83 default-state = "off";
84 };
85 led4 {
86 label = "LED4";
87 gpios = <&gpioi 4>;
88 default-state = "off";
89 };
90 led5 {
91 label = "LED5";
92 gpios = <&gpioi 5>;
93 default-state = "off";
94 };
95 led6 {
96 label = "LED6";
97 gpios = <&gpioi 6>;
98 default-state = "off";
99 };
100 led7 {
101 label = "LED7";
102 gpios = <&gpioi 7>;
103 default-state = "off";
104 };
105 led8 {
106 label = "LED8";
107 gpios = <&gpioi 8>;
108 default-state = "off";
109 };
110 led9 {
111 label = "LED9";
112 gpios = <&gpioi 9>;
113 default-state = "off";
114 };
115 led10 {
116 label = "LED10";
117 gpios = <&gpioi 10>;
118 default-state = "off";
119 };
120 led11 {
121 label = "LED11";
122 gpios = <&gpioi 11>;
123 default-state = "off";
124 };
125 };
126 };
127};
diff --git a/arch/arc/boot/dts/abilis_tb101.dtsi b/arch/arc/boot/dts/abilis_tb101.dtsi
new file mode 100644
index 000000000000..fd25c212049f
--- /dev/null
+++ b/arch/arc/boot/dts/abilis_tb101.dtsi
@@ -0,0 +1,349 @@
1/*
2 * Abilis Systems TB101 SOC device tree
3 *
4 * Copyright (C) Abilis Systems 2013
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/include/ "abilis_tb10x.dtsi"
23
24/* interrupt specifiers
25 * --------------------
26 * 0: rising, 1: low, 2: high, 3: falling,
27 */
28
29/ {
30 clock-frequency = <500000000>; /* 500 MHZ */
31
32 soc100 {
33 bus-frequency = <166666666>;
34
35 pll0: oscillator {
36 clock-frequency = <1000000000>;
37 };
38 cpu_clk: clkdiv_cpu {
39 clock-mult = <1>;
40 clock-div = <2>;
41 };
42 ahb_clk: clkdiv_ahb {
43 clock-mult = <1>;
44 clock-div = <6>;
45 };
46
47 iomux: iomux@FF10601c {
48 /* Port 1 */
49 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
50 pingrp = "mis0_pins";
51 };
52 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
53 pingrp = "mis1_pins";
54 };
55 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
56 pingrp = "gpioa_pins";
57 };
58 pctl_tsin_p1: pctl-tsin-p1 { /* Parallel TS-in 1 */
59 pingrp = "mip1_pins";
60 };
61 /* Port 2 */
62 pctl_tsin_s2: pctl-tsin-s2 { /* Serial TS-in 2 */
63 pingrp = "mis2_pins";
64 };
65 pctl_tsin_s3: pctl-tsin-s3 { /* Serial TS-in 3 */
66 pingrp = "mis3_pins";
67 };
68 pctl_gpio_c: pctl-gpio-c { /* GPIO bank C */
69 pingrp = "gpioc_pins";
70 };
71 pctl_tsin_p3: pctl-tsin-p3 { /* Parallel TS-in 3 */
72 pingrp = "mip3_pins";
73 };
74 /* Port 3 */
75 pctl_tsin_s4: pctl-tsin-s4 { /* Serial TS-in 4 */
76 pingrp = "mis4_pins";
77 };
78 pctl_tsin_s5: pctl-tsin-s5 { /* Serial TS-in 5 */
79 pingrp = "mis5_pins";
80 };
81 pctl_gpio_e: pctl-gpio-e { /* GPIO bank E */
82 pingrp = "gpioe_pins";
83 };
84 pctl_tsin_p5: pctl-tsin-p5 { /* Parallel TS-in 5 */
85 pingrp = "mip5_pins";
86 };
87 /* Port 4 */
88 pctl_tsin_s6: pctl-tsin-s6 { /* Serial TS-in 6 */
89 pingrp = "mis6_pins";
90 };
91 pctl_tsin_s7: pctl-tsin-s7 { /* Serial TS-in 7 */
92 pingrp = "mis7_pins";
93 };
94 pctl_gpio_g: pctl-gpio-g { /* GPIO bank G */
95 pingrp = "gpiog_pins";
96 };
97 pctl_tsin_p7: pctl-tsin-p7 { /* Parallel TS-in 7 */
98 pingrp = "mip7_pins";
99 };
100 /* Port 5 */
101 pctl_gpio_j: pctl-gpio-j { /* GPIO bank J */
102 pingrp = "gpioj_pins";
103 };
104 pctl_gpio_k: pctl-gpio-k { /* GPIO bank K */
105 pingrp = "gpiok_pins";
106 };
107 pctl_ciplus: pctl-ciplus { /* CI+ interface */
108 pingrp = "ciplus_pins";
109 };
110 pctl_mcard: pctl-mcard { /* M-Card interface */
111 pingrp = "mcard_pins";
112 };
113 pctl_stc0: pctl-stc0 { /* Smart card I/F 0 */
114 pingrp = "stc0_pins";
115 };
116 pctl_stc1: pctl-stc1 { /* Smart card I/F 1 */
117 pingrp = "stc1_pins";
118 };
119 /* Port 6 */
120 pctl_tsout_p: pctl-tsout-p { /* Parallel TS-out */
121 pingrp = "mop_pins";
122 };
123 pctl_tsout_s0: pctl-tsout-s0 { /* Serial TS-out 0 */
124 pingrp = "mos0_pins";
125 };
126 pctl_tsout_s1: pctl-tsout-s1 { /* Serial TS-out 1 */
127 pingrp = "mos1_pins";
128 };
129 pctl_tsout_s2: pctl-tsout-s2 { /* Serial TS-out 2 */
130 pingrp = "mos2_pins";
131 };
132 pctl_tsout_s3: pctl-tsout-s3 { /* Serial TS-out 3 */
133 pingrp = "mos3_pins";
134 };
135 /* Port 7 */
136 pctl_uart0: pctl-uart0 { /* UART 0 */
137 pingrp = "uart0_pins";
138 };
139 pctl_uart1: pctl-uart1 { /* UART 1 */
140 pingrp = "uart1_pins";
141 };
142 pctl_gpio_l: pctl-gpio-l { /* GPIO bank L */
143 pingrp = "gpiol_pins";
144 };
145 pctl_gpio_m: pctl-gpio-m { /* GPIO bank M */
146 pingrp = "gpiom_pins";
147 };
148 /* Port 8 */
149 pctl_spi3: pctl-spi3 {
150 pingrp = "spi3_pins";
151 };
152 pctl_jtag: pctl-jtag {
153 pingrp = "jtag_pins";
154 };
155 /* Port 9 */
156 pctl_spi1: pctl-spi1 {
157 pingrp = "spi1_pins";
158 };
159 pctl_gpio_n: pctl-gpio-n {
160 pingrp = "gpion_pins";
161 };
162 /* Unmuxed GPIOs */
163 pctl_gpio_b: pctl-gpio-b {
164 pingrp = "gpiob_pins";
165 };
166 pctl_gpio_d: pctl-gpio-d {
167 pingrp = "gpiod_pins";
168 };
169 pctl_gpio_f: pctl-gpio-f {
170 pingrp = "gpiof_pins";
171 };
172 pctl_gpio_h: pctl-gpio-h {
173 pingrp = "gpioh_pins";
174 };
175 pctl_gpio_i: pctl-gpio-i {
176 pingrp = "gpioi_pins";
177 };
178 };
179
180 gpioa: gpio@FF140000 {
181 compatible = "abilis,tb10x-gpio";
182 interrupt-controller;
183 #interrupt-cells = <1>;
184 interrupt-parent = <&tb10x_ictl>;
185 interrupts = <27 1>;
186 reg = <0xFF140000 0x1000>;
187 gpio-controller;
188 #gpio-cells = <1>;
189 gpio-base = <0>;
190 gpio-pins = <&pctl_gpio_a>;
191 };
192 gpiob: gpio@FF141000 {
193 compatible = "abilis,tb10x-gpio";
194 interrupt-controller;
195 #interrupt-cells = <1>;
196 interrupt-parent = <&tb10x_ictl>;
197 interrupts = <27 1>;
198 reg = <0xFF141000 0x1000>;
199 gpio-controller;
200 #gpio-cells = <1>;
201 gpio-base = <3>;
202 gpio-pins = <&pctl_gpio_b>;
203 };
204 gpioc: gpio@FF142000 {
205 compatible = "abilis,tb10x-gpio";
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 interrupt-parent = <&tb10x_ictl>;
209 interrupts = <27 1>;
210 reg = <0xFF142000 0x1000>;
211 gpio-controller;
212 #gpio-cells = <1>;
213 gpio-base = <5>;
214 gpio-pins = <&pctl_gpio_c>;
215 };
216 gpiod: gpio@FF143000 {
217 compatible = "abilis,tb10x-gpio";
218 interrupt-controller;
219 #interrupt-cells = <1>;
220 interrupt-parent = <&tb10x_ictl>;
221 interrupts = <27 1>;
222 reg = <0xFF143000 0x1000>;
223 gpio-controller;
224 #gpio-cells = <1>;
225 gpio-base = <8>;
226 gpio-pins = <&pctl_gpio_d>;
227 };
228 gpioe: gpio@FF144000 {
229 compatible = "abilis,tb10x-gpio";
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 interrupt-parent = <&tb10x_ictl>;
233 interrupts = <27 1>;
234 reg = <0xFF144000 0x1000>;
235 gpio-controller;
236 #gpio-cells = <1>;
237 gpio-base = <10>;
238 gpio-pins = <&pctl_gpio_e>;
239 };
240 gpiof: gpio@FF145000 {
241 compatible = "abilis,tb10x-gpio";
242 interrupt-controller;
243 #interrupt-cells = <1>;
244 interrupt-parent = <&tb10x_ictl>;
245 interrupts = <27 1>;
246 reg = <0xFF145000 0x1000>;
247 gpio-controller;
248 #gpio-cells = <1>;
249 gpio-base = <13>;
250 gpio-pins = <&pctl_gpio_f>;
251 };
252 gpiog: gpio@FF146000 {
253 compatible = "abilis,tb10x-gpio";
254 interrupt-controller;
255 #interrupt-cells = <1>;
256 interrupt-parent = <&tb10x_ictl>;
257 interrupts = <27 1>;
258 reg = <0xFF146000 0x1000>;
259 gpio-controller;
260 #gpio-cells = <1>;
261 gpio-base = <15>;
262 gpio-pins = <&pctl_gpio_g>;
263 };
264 gpioh: gpio@FF147000 {
265 compatible = "abilis,tb10x-gpio";
266 interrupt-controller;
267 #interrupt-cells = <1>;
268 interrupt-parent = <&tb10x_ictl>;
269 interrupts = <27 1>;
270 reg = <0xFF147000 0x1000>;
271 gpio-controller;
272 #gpio-cells = <1>;
273 gpio-base = <18>;
274 gpio-pins = <&pctl_gpio_h>;
275 };
276 gpioi: gpio@FF148000 {
277 compatible = "abilis,tb10x-gpio";
278 interrupt-controller;
279 #interrupt-cells = <1>;
280 interrupt-parent = <&tb10x_ictl>;
281 interrupts = <27 1>;
282 reg = <0xFF148000 0x1000>;
283 gpio-controller;
284 #gpio-cells = <1>;
285 gpio-base = <20>;
286 gpio-pins = <&pctl_gpio_i>;
287 };
288 gpioj: gpio@FF149000 {
289 compatible = "abilis,tb10x-gpio";
290 interrupt-controller;
291 #interrupt-cells = <1>;
292 interrupt-parent = <&tb10x_ictl>;
293 interrupts = <27 1>;
294 reg = <0xFF149000 0x1000>;
295 gpio-controller;
296 #gpio-cells = <1>;
297 gpio-base = <32>;
298 gpio-pins = <&pctl_gpio_j>;
299 };
300 gpiok: gpio@FF14a000 {
301 compatible = "abilis,tb10x-gpio";
302 interrupt-controller;
303 #interrupt-cells = <1>;
304 interrupt-parent = <&tb10x_ictl>;
305 interrupts = <27 1>;
306 reg = <0xFF14A000 0x1000>;
307 gpio-controller;
308 #gpio-cells = <1>;
309 gpio-base = <64>;
310 gpio-pins = <&pctl_gpio_k>;
311 };
312 gpiol: gpio@FF14b000 {
313 compatible = "abilis,tb10x-gpio";
314 interrupt-controller;
315 #interrupt-cells = <1>;
316 interrupt-parent = <&tb10x_ictl>;
317 interrupts = <27 1>;
318 reg = <0xFF14B000 0x1000>;
319 gpio-controller;
320 #gpio-cells = <1>;
321 gpio-base = <86>;
322 gpio-pins = <&pctl_gpio_l>;
323 };
324 gpiom: gpio@FF14c000 {
325 compatible = "abilis,tb10x-gpio";
326 interrupt-controller;
327 #interrupt-cells = <1>;
328 interrupt-parent = <&tb10x_ictl>;
329 interrupts = <27 1>;
330 reg = <0xFF14C000 0x1000>;
331 gpio-controller;
332 #gpio-cells = <1>;
333 gpio-base = <90>;
334 gpio-pins = <&pctl_gpio_m>;
335 };
336 gpion: gpio@FF14d000 {
337 compatible = "abilis,tb10x-gpio";
338 interrupt-controller;
339 #interrupt-cells = <1>;
340 interrupt-parent = <&tb10x_ictl>;
341 interrupts = <27 1>;
342 reg = <0xFF14D000 0x1000>;
343 gpio-controller;
344 #gpio-cells = <1>;
345 gpio-base = <94>;
346 gpio-pins = <&pctl_gpio_n>;
347 };
348 };
349};
diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts
new file mode 100644
index 000000000000..6f8c381f6268
--- /dev/null
+++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts
@@ -0,0 +1,127 @@
1/*
2 * Abilis Systems TB101 Development Kit PCB device tree
3 *
4 * Copyright (C) Abilis Systems 2013
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/dts-v1/;
23
24/include/ "abilis_tb101.dtsi"
25
26/ {
27 chosen {
28 bootargs = "earlycon=uart8250,mmio32,0xff100000,9600n8 console=ttyS0,9600n8";
29 };
30
31 aliases { };
32
33 memory {
34 device_type = "memory";
35 reg = <0x80000000 0x08000000>; /* 128M */
36 };
37
38 soc100 {
39 uart@FF100000 {
40 pinctrl-names = "abilis,simple-default";
41 pinctrl-0 = <&pctl_uart0>;
42 };
43 ethernet@FE100000 {
44 phy-mode = "rgmii";
45 };
46
47 i2c0: i2c@FF120000 {
48 sda-hold-time = <432>;
49 };
50 i2c1: i2c@FF121000 {
51 sda-hold-time = <432>;
52 };
53 i2c2: i2c@FF122000 {
54 sda-hold-time = <432>;
55 };
56 i2c3: i2c@FF123000 {
57 sda-hold-time = <432>;
58 };
59 i2c4: i2c@FF124000 {
60 sda-hold-time = <432>;
61 };
62
63 leds {
64 compatible = "gpio-leds";
65 power {
66 label = "Power";
67 gpios = <&gpioi 0>;
68 linux,default-trigger = "default-on";
69 };
70 heartbeat {
71 label = "Heartbeat";
72 gpios = <&gpioi 1>;
73 linux,default-trigger = "heartbeat";
74 };
75 led2 {
76 label = "LED2";
77 gpios = <&gpioi 2>;
78 default-state = "off";
79 };
80 led3 {
81 label = "LED3";
82 gpios = <&gpioi 3>;
83 default-state = "off";
84 };
85 led4 {
86 label = "LED4";
87 gpios = <&gpioi 4>;
88 default-state = "off";
89 };
90 led5 {
91 label = "LED5";
92 gpios = <&gpioi 5>;
93 default-state = "off";
94 };
95 led6 {
96 label = "LED6";
97 gpios = <&gpioi 6>;
98 default-state = "off";
99 };
100 led7 {
101 label = "LED7";
102 gpios = <&gpioi 7>;
103 default-state = "off";
104 };
105 led8 {
106 label = "LED8";
107 gpios = <&gpioi 8>;
108 default-state = "off";
109 };
110 led9 {
111 label = "LED9";
112 gpios = <&gpioi 9>;
113 default-state = "off";
114 };
115 led10 {
116 label = "LED10";
117 gpios = <&gpioi 10>;
118 default-state = "off";
119 };
120 led11 {
121 label = "LED11";
122 gpios = <&gpioi 11>;
123 default-state = "off";
124 };
125 };
126 };
127};
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
new file mode 100644
index 000000000000..a6139fc5aaa3
--- /dev/null
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -0,0 +1,247 @@
1/*
2 * Abilis Systems TB10X SOC device tree
3 *
4 * Copyright (C) Abilis Systems 2013
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/* interrupt specifiers
23 * --------------------
24 * 0: rising, 1: low, 2: high, 3: falling,
25 */
26
27/ {
28 compatible = "abilis,arc-tb10x";
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "snps,arc770d";
38 reg = <0>;
39 };
40 };
41
42 soc100 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 device_type = "soc";
46 ranges = <0xfe000000 0xfe000000 0x02000000
47 0x000F0000 0x000F0000 0x00010000>;
48 compatible = "abilis,tb10x", "simple-bus";
49
50 pll0: oscillator {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-output-names = "pll0";
54 };
55 cpu_clk: clkdiv_cpu {
56 compatible = "fixed-factor-clock";
57 #clock-cells = <0>;
58 clocks = <&pll0>;
59 clock-output-names = "cpu_clk";
60 };
61 ahb_clk: clkdiv_ahb {
62 compatible = "fixed-factor-clock";
63 #clock-cells = <0>;
64 clocks = <&pll0>;
65 clock-output-names = "ahb_clk";
66 };
67
68 iomux: iomux@FF10601c {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "abilis,tb10x-iomux";
72 reg = <0xFF10601c 0x4>;
73 };
74
75 intc: interrupt-controller {
76 compatible = "snps,arc700-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80 tb10x_ictl: pic@fe002000 {
81 compatible = "abilis,tb10x_ictl";
82 reg = <0xFE002000 0x20>;
83 interrupt-controller;
84 #interrupt-cells = <2>;
85 interrupt-parent = <&intc>;
86 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
87 20 21 22 23 24 25 26 27 28 29 30 31>;
88 };
89
90 uart@FF100000 {
91 compatible = "snps,dw-apb-uart",
92 "abilis,simple-pinctrl";
93 reg = <0xFF100000 0x100>;
94 clock-frequency = <166666666>;
95 interrupts = <25 1>;
96 reg-shift = <2>;
97 reg-io-width = <4>;
98 interrupt-parent = <&tb10x_ictl>;
99 };
100 ethernet@FE100000 {
101 compatible = "snps,dwmac-3.70a","snps,dwmac";
102 reg = <0xFE100000 0x1058>;
103 interrupt-parent = <&tb10x_ictl>;
104 interrupts = <6 1>;
105 interrupt-names = "macirq";
106 clocks = <&ahb_clk>;
107 clock-names = "stmmaceth";
108 };
109 dma@FE000000 {
110 compatible = "snps,dma-spear1340";
111 reg = <0xFE000000 0x400>;
112 interrupt-parent = <&tb10x_ictl>;
113 interrupts = <14 1>;
114 dma-channels = <6>;
115 dma-requests = <0>;
116 dma-masters = <1>;
117 #dma-cells = <3>;
118 chan_allocation_order = <0>;
119 chan_priority = <1>;
120 block_size = <0x7ff>;
121 data_width = <2 0 0 0>;
122 clocks = <&ahb_clk>;
123 clock-names = "hclk";
124 };
125
126 i2c0: i2c@FF120000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "snps,designware-i2c";
130 reg = <0xFF120000 0x1000>;
131 interrupt-parent = <&tb10x_ictl>;
132 interrupts = <12 1>;
133 clocks = <&ahb_clk>;
134 };
135 i2c1: i2c@FF121000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "snps,designware-i2c";
139 reg = <0xFF121000 0x1000>;
140 interrupt-parent = <&tb10x_ictl>;
141 interrupts = <12 1>;
142 clocks = <&ahb_clk>;
143 };
144 i2c2: i2c@FF122000 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "snps,designware-i2c";
148 reg = <0xFF122000 0x1000>;
149 interrupt-parent = <&tb10x_ictl>;
150 interrupts = <12 1>;
151 clocks = <&ahb_clk>;
152 };
153 i2c3: i2c@FF123000 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "snps,designware-i2c";
157 reg = <0xFF123000 0x1000>;
158 interrupt-parent = <&tb10x_ictl>;
159 interrupts = <12 1>;
160 clocks = <&ahb_clk>;
161 };
162 i2c4: i2c@FF124000 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "snps,designware-i2c";
166 reg = <0xFF124000 0x1000>;
167 interrupt-parent = <&tb10x_ictl>;
168 interrupts = <12 1>;
169 clocks = <&ahb_clk>;
170 };
171
172 spi0: spi@0xFE010000 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 cell-index = <0>;
176 compatible = "abilis,tb100-spi";
177 num-cs = <1>;
178 reg = <0xFE010000 0x20>;
179 interrupt-parent = <&tb10x_ictl>;
180 interrupts = <26 1>;
181 clocks = <&ahb_clk>;
182 };
183 spi1: spi@0xFE011000 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 cell-index = <1>;
187 compatible = "abilis,tb100-spi",
188 "abilis,simple-pinctrl";
189 num-cs = <2>;
190 reg = <0xFE011000 0x20>;
191 interrupt-parent = <&tb10x_ictl>;
192 interrupts = <10 1>;
193 clocks = <&ahb_clk>;
194 };
195
196 tb10x_tsm: tb10x-tsm@ff316000 {
197 compatible = "abilis,tb100-tsm";
198 reg = <0xff316000 0x400>;
199 interrupt-parent = <&tb10x_ictl>;
200 interrupts = <17 1>;
201 output-clkdiv = <4>;
202 global-packet-delay = <0x21>;
203 port-packet-delay = <0>;
204 };
205 tb10x_stream_proc: tb10x-stream-proc {
206 compatible = "abilis,tb100-streamproc";
207 reg = <0xfff00000 0x200>,
208 <0x000f0000 0x10000>,
209 <0xfff00200 0x105>,
210 <0xff10600c 0x1>,
211 <0xfe001018 0x1>;
212 reg-names = "mbox",
213 "sp_iccm",
214 "mbox_irq",
215 "cpuctrl",
216 "a6it_int_force";
217 interrupt-parent = <&tb10x_ictl>;
218 interrupts = <20 1>, <19 1>;
219 interrupt-names = "cmd_irq", "event_irq";
220 };
221 tb10x_mdsc0: tb10x-mdscr@FF300000 {
222 compatible = "abilis,tb100-mdscr";
223 reg = <0xFF300000 0x7000>;
224 tb100-mdscr-manage-tsin;
225 };
226 tb10x_mscr0: tb10x-mdscr@FF307000 {
227 compatible = "abilis,tb100-mdscr";
228 reg = <0xFF307000 0x7000>;
229 };
230 tb10x_scr0: tb10x-mdscr@ff30e000 {
231 compatible = "abilis,tb100-mdscr";
232 reg = <0xFF30e000 0x4000>;
233 tb100-mdscr-manage-tsin;
234 };
235 tb10x_scr1: tb10x-mdscr@ff312000 {
236 compatible = "abilis,tb100-mdscr";
237 reg = <0xFF312000 0x4000>;
238 tb100-mdscr-manage-tsin;
239 };
240 tb10x_wfb: tb10x-wfb@ff319000 {
241 compatible = "abilis,tb100-wfb";
242 reg = <0xff319000 0x1000>;
243 interrupt-parent = <&tb10x_ictl>;
244 interrupts = <16 1>;
245 };
246 };
247};
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
new file mode 100644
index 000000000000..ea16d782af58
--- /dev/null
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton.dtsi"
11
12/ {
13 compatible = "snps,nsimosci";
14 clock-frequency = <80000000>; /* 80 MHZ */
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&intc>;
18
19 chosen {
20 bootargs = "console=tty0 consoleblank=0";
21 };
22
23 aliases {
24 serial0 = &uart0;
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x80000000 0x10000000>; /* 256M */
30 };
31
32 fpga {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
36
37 /* child and parent address space 1:1 mapped */
38 ranges;
39
40 intc: interrupt-controller {
41 compatible = "snps,arc700-intc";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 };
45
46 uart0: serial@c0000000 {
47 compatible = "snps,dw-apb-uart";
48 reg = <0xc0000000 0x2000>;
49 interrupts = <11>;
50 #clock-frequency = <80000000>;
51 clock-frequency = <3686400>;
52 baud = <115200>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 status = "okay";
56 };
57
58 pgu0: pgu@c9000000 {
59 compatible = "snps,arcpgufb";
60 reg = <0xc9000000 0x400>;
61 };
62
63 ps2: ps2@c9001000 {
64 compatible = "snps,arc_ps2";
65 reg = <0xc9000400 0x14>;
66 interrupts = <13>;
67 interrupt-names = "arc_ps2_irq";
68 };
69
70 eth0: ethernet@c0003000 {
71 compatible = "snps,oscilan";
72 reg = <0xc0003000 0x44>;
73 interrupts = <7>, <8>;
74 interrupt-names = "rx", "tx";
75 };
76 };
77};
diff --git a/arch/arc/configs/fpga_defconfig b/arch/arc/configs/fpga_defconfig
index b8698067ebbe..95350be6ef6f 100644
--- a/arch/arc/configs/fpga_defconfig
+++ b/arch/arc/configs/fpga_defconfig
@@ -9,7 +9,7 @@ CONFIG_NAMESPACES=y
9# CONFIG_UTS_NS is not set 9# CONFIG_UTS_NS is not set
10# CONFIG_PID_NS is not set 10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y 11CONFIG_BLK_DEV_INITRD=y
12CONFIG_INITRAMFS_SOURCE="../arc_initramfs" 12CONFIG_INITRAMFS_SOURCE="../arc_initramfs/"
13CONFIG_KALLSYMS_ALL=y 13CONFIG_KALLSYMS_ALL=y
14CONFIG_EMBEDDED=y 14CONFIG_EMBEDDED=y
15# CONFIG_SLUB_DEBUG is not set 15# CONFIG_SLUB_DEBUG is not set
@@ -24,6 +24,7 @@ CONFIG_ARC_PLAT_FPGA_LEGACY=y
24CONFIG_ARC_BOARD_ML509=y 24CONFIG_ARC_BOARD_ML509=y
25# CONFIG_ARC_HAS_RTSC is not set 25# CONFIG_ARC_HAS_RTSC is not set
26CONFIG_ARC_BUILTIN_DTB_NAME="angel4" 26CONFIG_ARC_BUILTIN_DTB_NAME="angel4"
27CONFIG_PREEMPT=y
27# CONFIG_COMPACTION is not set 28# CONFIG_COMPACTION is not set
28# CONFIG_CROSS_MEMORY_ATTACH is not set 29# CONFIG_CROSS_MEMORY_ATTACH is not set
29CONFIG_NET=y 30CONFIG_NET=y
diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig
new file mode 100644
index 000000000000..446c96c24eff
--- /dev/null
+++ b/arch/arc/configs/nsimosci_defconfig
@@ -0,0 +1,75 @@
1CONFIG_CROSS_COMPILE="arc-elf32-"
2# CONFIG_LOCALVERSION_AUTO is not set
3CONFIG_DEFAULT_HOSTNAME="ARCLinux"
4# CONFIG_SWAP is not set
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y
8CONFIG_NAMESPACES=y
9# CONFIG_UTS_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_INITRAMFS_SOURCE="../arc_initramfs"
13CONFIG_KALLSYMS_ALL=y
14CONFIG_EMBEDDED=y
15# CONFIG_SLUB_DEBUG is not set
16# CONFIG_COMPAT_BRK is not set
17CONFIG_KPROBES=y
18CONFIG_MODULES=y
19# CONFIG_LBDAF is not set
20# CONFIG_BLK_DEV_BSG is not set
21# CONFIG_IOSCHED_DEADLINE is not set
22# CONFIG_IOSCHED_CFQ is not set
23CONFIG_ARC_PLAT_FPGA_LEGACY=y
24CONFIG_ARC_BOARD_ML509=y
25# CONFIG_ARC_IDE is not set
26# CONFIG_ARCTANGENT_EMAC is not set
27# CONFIG_ARC_HAS_RTSC is not set
28CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
29# CONFIG_COMPACTION is not set
30# CONFIG_CROSS_MEMORY_ATTACH is not set
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_UNIX_DIAG=y
35CONFIG_NET_KEY=y
36CONFIG_INET=y
37# CONFIG_IPV6 is not set
38# CONFIG_STANDALONE is not set
39# CONFIG_PREVENT_FIRMWARE_BUILD is not set
40# CONFIG_FIRMWARE_IN_KERNEL is not set
41# CONFIG_BLK_DEV is not set
42CONFIG_NETDEVICES=y
43# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
44# CONFIG_MOUSE_PS2_ALPS is not set
45# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
46# CONFIG_MOUSE_PS2_SYNAPTICS is not set
47# CONFIG_MOUSE_PS2_TRACKPOINT is not set
48CONFIG_MOUSE_PS2_TOUCHKIT=y
49# CONFIG_SERIO_I8042 is not set
50# CONFIG_SERIO_SERPORT is not set
51CONFIG_SERIO_ARC_PS2=y
52# CONFIG_LEGACY_PTYS is not set
53# CONFIG_DEVKMEM is not set
54CONFIG_SERIAL_8250=y
55CONFIG_SERIAL_8250_CONSOLE=y
56CONFIG_SERIAL_8250_DW=y
57CONFIG_SERIAL_ARC=y
58CONFIG_SERIAL_ARC_CONSOLE=y
59# CONFIG_HW_RANDOM is not set
60# CONFIG_HWMON is not set
61CONFIG_FB=y
62# CONFIG_VGA_CONSOLE is not set
63CONFIG_FRAMEBUFFER_CONSOLE=y
64CONFIG_LOGO=y
65# CONFIG_HID is not set
66# CONFIG_USB_SUPPORT is not set
67# CONFIG_IOMMU_SUPPORT is not set
68CONFIG_EXT2_FS=y
69CONFIG_EXT2_FS_XATTR=y
70CONFIG_TMPFS=y
71# CONFIG_MISC_FILESYSTEMS is not set
72CONFIG_NFS_FS=y
73# CONFIG_ENABLE_WARN_DEPRECATED is not set
74# CONFIG_ENABLE_MUST_CHECK is not set
75CONFIG_XZ_DEC=y
diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig
new file mode 100644
index 000000000000..4fa5cd9f2202
--- /dev/null
+++ b/arch/arc/configs/tb10x_defconfig
@@ -0,0 +1,117 @@
1CONFIG_CROSS_COMPILE="arc-elf32-"
2# CONFIG_LOCALVERSION_AUTO is not set
3CONFIG_DEFAULT_HOSTNAME="tb10x"
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_HIGH_RES_TIMERS=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_BSD_PROCESS_ACCT_V3=y
9CONFIG_IKCONFIG=y
10CONFIG_IKCONFIG_PROC=y
11CONFIG_LOG_BUF_SHIFT=16
12CONFIG_BLK_DEV_INITRD=y
13CONFIG_INITRAMFS_SOURCE="../tb10x-rootfs.cpio"
14CONFIG_INITRAMFS_ROOT_UID=2100
15CONFIG_INITRAMFS_ROOT_GID=501
16# CONFIG_RD_GZIP is not set
17CONFIG_SYSCTL_SYSCALL=y
18CONFIG_KALLSYMS_ALL=y
19# CONFIG_AIO is not set
20CONFIG_EMBEDDED=y
21# CONFIG_COMPAT_BRK is not set
22CONFIG_SLAB=y
23CONFIG_MODULES=y
24CONFIG_MODULE_FORCE_LOAD=y
25CONFIG_MODULE_UNLOAD=y
26# CONFIG_BLOCK is not set
27CONFIG_ARC_PLAT_TB10X=y
28CONFIG_ARC_CACHE_LINE_SHIFT=5
29# CONFIG_ARC_HAS_RTSC is not set
30CONFIG_ARC_STACK_NONEXEC=y
31CONFIG_HZ=250
32CONFIG_ARC_BUILTIN_DTB_NAME="abilis_tb100_dvk"
33CONFIG_PREEMPT_VOLUNTARY=y
34# CONFIG_COMPACTION is not set
35# CONFIG_CROSS_MEMORY_ATTACH is not set
36CONFIG_NET=y
37CONFIG_PACKET=y
38CONFIG_UNIX=y
39CONFIG_INET=y
40CONFIG_IP_MULTICAST=y
41# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
42# CONFIG_INET_XFRM_MODE_TUNNEL is not set
43# CONFIG_INET_XFRM_MODE_BEET is not set
44# CONFIG_INET_LRO is not set
45# CONFIG_INET_DIAG is not set
46# CONFIG_IPV6 is not set
47# CONFIG_WIRELESS is not set
48# CONFIG_FIRMWARE_IN_KERNEL is not set
49CONFIG_PROC_DEVICETREE=y
50CONFIG_NETDEVICES=y
51# CONFIG_NET_CADENCE is not set
52# CONFIG_NET_VENDOR_BROADCOM is not set
53# CONFIG_NET_VENDOR_INTEL is not set
54# CONFIG_NET_VENDOR_MARVELL is not set
55# CONFIG_NET_VENDOR_MICREL is not set
56# CONFIG_NET_VENDOR_NATSEMI is not set
57# CONFIG_NET_VENDOR_SEEQ is not set
58CONFIG_STMMAC_ETH=y
59CONFIG_STMMAC_DEBUG_FS=y
60CONFIG_STMMAC_DA=y
61CONFIG_STMMAC_CHAINED=y
62# CONFIG_NET_VENDOR_WIZNET is not set
63# CONFIG_WLAN is not set
64# CONFIG_INPUT is not set
65# CONFIG_SERIO is not set
66# CONFIG_VT is not set
67CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
68# CONFIG_LEGACY_PTYS is not set
69# CONFIG_DEVKMEM is not set
70CONFIG_SERIAL_8250=y
71CONFIG_SERIAL_8250_CONSOLE=y
72CONFIG_SERIAL_8250_NR_UARTS=1
73CONFIG_SERIAL_8250_RUNTIME_UARTS=1
74CONFIG_SERIAL_8250_DW=y
75# CONFIG_HW_RANDOM is not set
76CONFIG_I2C=y
77# CONFIG_I2C_COMPAT is not set
78CONFIG_I2C_DESIGNWARE_PLATFORM=y
79CONFIG_GPIO_SYSFS=y
80# CONFIG_HWMON is not set
81# CONFIG_USB_SUPPORT is not set
82CONFIG_NEW_LEDS=y
83CONFIG_LEDS_CLASS=y
84CONFIG_LEDS_GPIO=y
85CONFIG_LEDS_TRIGGERS=y
86CONFIG_LEDS_TRIGGER_TIMER=y
87CONFIG_LEDS_TRIGGER_ONESHOT=y
88CONFIG_LEDS_TRIGGER_HEARTBEAT=y
89CONFIG_LEDS_TRIGGER_CPU=y
90CONFIG_LEDS_TRIGGER_GPIO=y
91CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
92CONFIG_LEDS_TRIGGER_TRANSIENT=y
93CONFIG_DMADEVICES=y
94CONFIG_DW_DMAC=y
95CONFIG_NET_DMA=y
96CONFIG_ASYNC_TX_DMA=y
97# CONFIG_IOMMU_SUPPORT is not set
98# CONFIG_DNOTIFY is not set
99CONFIG_PROC_KCORE=y
100CONFIG_TMPFS=y
101CONFIG_CONFIGFS_FS=y
102# CONFIG_MISC_FILESYSTEMS is not set
103# CONFIG_NETWORK_FILESYSTEMS is not set
104# CONFIG_ENABLE_WARN_DEPRECATED is not set
105CONFIG_MAGIC_SYSRQ=y
106CONFIG_STRIP_ASM_SYMS=y
107CONFIG_DEBUG_FS=y
108CONFIG_HEADERS_CHECK=y
109CONFIG_DEBUG_SECTION_MISMATCH=y
110CONFIG_DETECT_HUNG_TASK=y
111CONFIG_SCHEDSTATS=y
112CONFIG_TIMER_STATS=y
113CONFIG_DEBUG_INFO=y
114CONFIG_DEBUG_MEMORY_INIT=y
115CONFIG_DEBUG_STACKOVERFLOW=y
116# CONFIG_CRYPTO_ANSI_CPRNG is not set
117# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index 97ee96f26505..ee1f6eae82d2 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -20,12 +20,20 @@
20 20
21#include <linux/mm.h> 21#include <linux/mm.h>
22 22
23/*
24 * Semantically we need this because icache doesn't snoop dcache/dma.
25 * However ARC Cache flush requires paddr as well as vaddr, latter not available
26 * in the flush_icache_page() API. So we no-op it but do the equivalent work
27 * in update_mmu_cache()
28 */
29#define flush_icache_page(vma, page)
30
23void flush_cache_all(void); 31void flush_cache_all(void);
24 32
25void flush_icache_range(unsigned long start, unsigned long end); 33void flush_icache_range(unsigned long start, unsigned long end);
26void flush_icache_page(struct vm_area_struct *vma, struct page *page); 34void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len);
27void flush_icache_range_vaddr(unsigned long paddr, unsigned long u_vaddr, 35void __inv_icache_page(unsigned long paddr, unsigned long vaddr);
28 int len); 36void __flush_dcache_page(unsigned long paddr);
29 37
30#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 38#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
31 39
@@ -58,7 +66,7 @@ void dma_cache_wback(unsigned long start, unsigned long sz);
58do { \ 66do { \
59 memcpy(dst, src, len); \ 67 memcpy(dst, src, len); \
60 if (vma->vm_flags & VM_EXEC) \ 68 if (vma->vm_flags & VM_EXEC) \
61 flush_icache_range_vaddr((unsigned long)(dst), vaddr, len);\ 69 __sync_icache_dcache((unsigned long)(dst), vaddr, len); \
62} while (0) 70} while (0)
63 71
64#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 72#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 4c588f9820cf..57898a17eb82 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -9,7 +9,8 @@
9#ifndef __ASM_ARC_IRQ_H 9#ifndef __ASM_ARC_IRQ_H
10#define __ASM_ARC_IRQ_H 10#define __ASM_ARC_IRQ_H
11 11
12#define NR_IRQS 32 12#define NR_CPU_IRQS 32 /* number of interrupt lines of ARC770 CPU */
13#define NR_IRQS 128 /* allow some CPU external IRQ handling */
13 14
14/* Platform Independent IRQs */ 15/* Platform Independent IRQs */
15#define TIMER0_IRQ 3 16#define TIMER0_IRQ 3
diff --git a/arch/arc/include/asm/serial.h b/arch/arc/include/asm/serial.h
index 4dff5a1e4128..602b0970a764 100644
--- a/arch/arc/include/asm/serial.h
+++ b/arch/arc/include/asm/serial.h
@@ -22,4 +22,14 @@
22 22
23#define BASE_BAUD (arc_get_core_freq() / 16) 23#define BASE_BAUD (arc_get_core_freq() / 16)
24 24
25/*
26 * This is definitely going to break early 8250 consoles on multi-platform
27 * images but hey, it won't add any code complexity for a debug feature of
28 * one broken driver.
29 */
30#ifdef CONFIG_ARC_PLAT_TB10X
31#undef BASE_BAUD
32#define BASE_BAUD (arc_get_core_freq() / 16 / 3)
33#endif
34
25#endif /* _ASM_ARC_SERIAL_H */ 35#endif /* _ASM_ARC_SERIAL_H */
diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h
index 3eb2ce0bdfa3..fe91719866a5 100644
--- a/arch/arc/include/asm/tlb.h
+++ b/arch/arc/include/asm/tlb.h
@@ -21,20 +21,28 @@
21 21
22#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
23 23
24#define tlb_flush(tlb) local_flush_tlb_mm((tlb)->mm) 24#define tlb_flush(tlb) \
25do { \
26 if (tlb->fullmm) \
27 flush_tlb_mm((tlb)->mm); \
28} while (0)
25 29
26/* 30/*
27 * This pair is called at time of munmap/exit to flush cache and TLB entries 31 * This pair is called at time of munmap/exit to flush cache and TLB entries
28 * for mappings being torn down. 32 * for mappings being torn down.
29 * 1) cache-flush part -implemented via tlb_start_vma( ) can be NOP (for now) 33 * 1) cache-flush part -implemented via tlb_start_vma( ) can be NOP (for now)
30 * as we don't support aliasing configs in our VIPT D$. 34 * as we don't support aliasing configs in our VIPT D$.
31 * 2) tlb-flush part - implemted via tlb_end_vma( ) can be NOP as well- 35 * 2) tlb-flush part - implemted via tlb_end_vma( ) flushes the TLB range
32 * albiet for difft reasons - its better handled by moving to new ASID
33 * 36 *
34 * Note, read http://lkml.org/lkml/2004/1/15/6 37 * Note, read http://lkml.org/lkml/2004/1/15/6
35 */ 38 */
36#define tlb_start_vma(tlb, vma) 39#define tlb_start_vma(tlb, vma)
37#define tlb_end_vma(tlb, vma) 40
41#define tlb_end_vma(tlb, vma) \
42do { \
43 if (!tlb->fullmm) \
44 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
45} while (0)
38 46
39#define __tlb_remove_tlb_entry(tlb, ptep, address) 47#define __tlb_remove_tlb_entry(tlb, ptep, address)
40 48
diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c
index 0dc148ebce74..7dcda7025241 100644
--- a/arch/arc/kernel/asm-offsets.c
+++ b/arch/arc/kernel/asm-offsets.c
@@ -11,9 +11,9 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/thread_info.h> 12#include <linux/thread_info.h>
13#include <linux/kbuild.h> 13#include <linux/kbuild.h>
14#include <linux/ptrace.h>
14#include <asm/hardirq.h> 15#include <asm/hardirq.h>
15#include <asm/page.h> 16#include <asm/page.h>
16#include <asm/ptrace.h>
17 17
18int main(void) 18int main(void)
19{ 19{
diff --git a/arch/arc/kernel/clk.c b/arch/arc/kernel/clk.c
index 66ce0dc917fb..10c7b0b5a079 100644
--- a/arch/arc/kernel/clk.c
+++ b/arch/arc/kernel/clk.c
@@ -8,7 +8,7 @@
8 8
9#include <asm/clk.h> 9#include <asm/clk.h>
10 10
11unsigned long core_freq = 800000000; 11unsigned long core_freq = 80000000;
12 12
13/* 13/*
14 * As of now we default to device-tree provided clock 14 * As of now we default to device-tree provided clock
diff --git a/arch/arc/kernel/disasm.c b/arch/arc/kernel/disasm.c
index d14764ae2c60..b8a549c4f540 100644
--- a/arch/arc/kernel/disasm.c
+++ b/arch/arc/kernel/disasm.c
@@ -12,8 +12,8 @@
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/kprobes.h> 13#include <linux/kprobes.h>
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/uaccess.h>
15#include <asm/disasm.h> 16#include <asm/disasm.h>
16#include <asm/uaccess.h>
17 17
18#if defined(CONFIG_KGDB) || defined(CONFIG_ARC_MISALIGN_ACCESS) || \ 18#if defined(CONFIG_KGDB) || defined(CONFIG_ARC_MISALIGN_ACCESS) || \
19 defined(CONFIG_KPROBES) 19 defined(CONFIG_KPROBES)
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 91eeab81f52d..0c6d664d4a83 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -393,12 +393,14 @@ ARC_ENTRY EV_TLBProtV
393#ifdef CONFIG_ARC_MISALIGN_ACCESS 393#ifdef CONFIG_ARC_MISALIGN_ACCESS
394 SAVE_CALLEE_SAVED_USER 394 SAVE_CALLEE_SAVED_USER
395 mov r3, sp ; callee_regs 395 mov r3, sp ; callee_regs
396#endif
397 396
398 bl do_misaligned_access 397 bl do_misaligned_access
399 398
400#ifdef CONFIG_ARC_MISALIGN_ACCESS 399 ; TBD: optimize - do this only if a callee reg was involved
401 DISCARD_CALLEE_SAVED_USER 400 ; either a dst of emulated LD/ST or src with address-writeback
401 RESTORE_CALLEE_SAVED_USER
402#else
403 bl do_misaligned_error
402#endif 404#endif
403 405
404 b ret_from_exception 406 b ret_from_exception
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index 551c10dff481..8115fa531575 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -11,6 +11,8 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/irqdomain.h> 13#include <linux/irqdomain.h>
14#include <linux/irqchip.h>
15#include "../../drivers/irqchip/irqchip.h"
14#include <asm/sections.h> 16#include <asm/sections.h>
15#include <asm/irq.h> 17#include <asm/irq.h>
16#include <asm/mach_desc.h> 18#include <asm/mach_desc.h>
@@ -26,7 +28,7 @@
26 * -Disable all IRQs (on CPU side) 28 * -Disable all IRQs (on CPU side)
27 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 29 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
28 */ 30 */
29void __init arc_init_IRQ(void) 31void __cpuinit arc_init_IRQ(void)
30{ 32{
31 int level_mask = 0; 33 int level_mask = 0;
32 34
@@ -97,15 +99,13 @@ static const struct irq_domain_ops arc_intc_domain_ops = {
97 99
98static struct irq_domain *root_domain; 100static struct irq_domain *root_domain;
99 101
100void __init init_onchip_IRQ(void) 102static int __init
103init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
101{ 104{
102 struct device_node *intc = NULL; 105 if (parent)
106 panic("DeviceTree incore intc not a root irq controller\n");
103 107
104 intc = of_find_compatible_node(NULL, NULL, "snps,arc700-intc"); 108 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
105 if(!intc)
106 panic("DeviceTree Missing incore intc\n");
107
108 root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
109 &arc_intc_domain_ops, NULL); 109 &arc_intc_domain_ops, NULL);
110 110
111 if (!root_domain) 111 if (!root_domain)
@@ -113,8 +113,12 @@ void __init init_onchip_IRQ(void)
113 113
114 /* with this we don't need to export root_domain */ 114 /* with this we don't need to export root_domain */
115 irq_set_default_host(root_domain); 115 irq_set_default_host(root_domain);
116
117 return 0;
116} 118}
117 119
120IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
121
118/* 122/*
119 * Late Interrupt system init called from start_kernel for Boot CPU only 123 * Late Interrupt system init called from start_kernel for Boot CPU only
120 * 124 *
@@ -123,12 +127,13 @@ void __init init_onchip_IRQ(void)
123 */ 127 */
124void __init init_IRQ(void) 128void __init init_IRQ(void)
125{ 129{
126 init_onchip_IRQ();
127
128 /* Any external intc can be setup here */ 130 /* Any external intc can be setup here */
129 if (machine_desc->init_irq) 131 if (machine_desc->init_irq)
130 machine_desc->init_irq(); 132 machine_desc->init_irq();
131 133
134 /* process the entire interrupt tree in one go */
135 irqchip_init();
136
132#ifdef CONFIG_SMP 137#ifdef CONFIG_SMP
133 /* Master CPU can initialize it's side of IPI */ 138 /* Master CPU can initialize it's side of IPI */
134 if (machine_desc->init_smp) 139 if (machine_desc->init_smp)
diff --git a/arch/arc/kernel/kprobes.c b/arch/arc/kernel/kprobes.c
index 3bfeacb674de..5a7b80e2d883 100644
--- a/arch/arc/kernel/kprobes.c
+++ b/arch/arc/kernel/kprobes.c
@@ -10,7 +10,6 @@
10#include <linux/kprobes.h> 10#include <linux/kprobes.h>
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/kprobes.h>
14#include <linux/kdebug.h> 13#include <linux/kdebug.h>
15#include <linux/sched.h> 14#include <linux/sched.h>
16#include <linux/uaccess.h> 15#include <linux/uaccess.h>
diff --git a/arch/arc/kernel/module.c b/arch/arc/kernel/module.c
index cdd359352c0a..376e04622962 100644
--- a/arch/arc/kernel/module.c
+++ b/arch/arc/kernel/module.c
@@ -47,7 +47,7 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
47 } 47 }
48 } 48 }
49#endif 49#endif
50 return 0; 50 return 0;
51} 51}
52 52
53void module_arch_cleanup(struct module *mod) 53void module_arch_cleanup(struct module *mod)
@@ -141,5 +141,5 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
141 mod->arch.unw_info = unw; 141 mod->arch.unw_info = unw;
142 } 142 }
143#endif 143#endif
144 return 0; 144 return 0;
145} 145}
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 2d95ac07df7b..b2b3731dd1e9 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -14,14 +14,13 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/cpu.h> 15#include <linux/cpu.h>
16#include <linux/of_fdt.h> 16#include <linux/of_fdt.h>
17#include <linux/cache.h>
17#include <asm/sections.h> 18#include <asm/sections.h>
18#include <asm/arcregs.h> 19#include <asm/arcregs.h>
19#include <asm/tlb.h> 20#include <asm/tlb.h>
20#include <asm/cache.h>
21#include <asm/setup.h> 21#include <asm/setup.h>
22#include <asm/page.h> 22#include <asm/page.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/arcregs.h>
25#include <asm/prom.h> 24#include <asm/prom.h>
26#include <asm/unwind.h> 25#include <asm/unwind.h>
27#include <asm/clk.h> 26#include <asm/clk.h>
@@ -32,14 +31,14 @@
32int running_on_hw = 1; /* vs. on ISS */ 31int running_on_hw = 1; /* vs. on ISS */
33 32
34char __initdata command_line[COMMAND_LINE_SIZE]; 33char __initdata command_line[COMMAND_LINE_SIZE];
35struct machine_desc *machine_desc __initdata; 34struct machine_desc *machine_desc __cpuinitdata;
36 35
37struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 36struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
38 37
39struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 38struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
40 39
41 40
42void __init read_arc_build_cfg_regs(void) 41void __cpuinit read_arc_build_cfg_regs(void)
43{ 42{
44 struct bcr_perip uncached_space; 43 struct bcr_perip uncached_space;
45 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 44 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
@@ -238,7 +237,7 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
238 return buf; 237 return buf;
239} 238}
240 239
241void __init arc_chk_ccms(void) 240void __cpuinit arc_chk_ccms(void)
242{ 241{
243#if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM) 242#if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM)
244 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 243 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
@@ -273,7 +272,7 @@ void __init arc_chk_ccms(void)
273 * hardware has dedicated regs which need to be saved/restored on ctx-sw 272 * hardware has dedicated regs which need to be saved/restored on ctx-sw
274 * (Single Precision uses core regs), thus kernel is kind of oblivious to it 273 * (Single Precision uses core regs), thus kernel is kind of oblivious to it
275 */ 274 */
276void __init arc_chk_fpu(void) 275void __cpuinit arc_chk_fpu(void)
277{ 276{
278 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 277 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
279 278
@@ -294,7 +293,7 @@ void __init arc_chk_fpu(void)
294 * such as only for boot CPU etc 293 * such as only for boot CPU etc
295 */ 294 */
296 295
297void __init setup_processor(void) 296void __cpuinit setup_processor(void)
298{ 297{
299 char str[512]; 298 char str[512];
300 int cpu_id = smp_processor_id(); 299 int cpu_id = smp_processor_id();
@@ -319,23 +318,20 @@ void __init setup_processor(void)
319 318
320void __init setup_arch(char **cmdline_p) 319void __init setup_arch(char **cmdline_p)
321{ 320{
321 /* This also populates @boot_command_line from /bootargs */
322 machine_desc = setup_machine_fdt(__dtb_start);
323 if (!machine_desc)
324 panic("Embedded DT invalid\n");
325
326 /* Append any u-boot provided cmdline */
322#ifdef CONFIG_CMDLINE_UBOOT 327#ifdef CONFIG_CMDLINE_UBOOT
323 /* Make sure that a whitespace is inserted before */ 328 /* Add a whitespace seperator between the 2 cmdlines */
324 strlcat(command_line, " ", sizeof(command_line)); 329 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
330 strlcat(boot_command_line, command_line, COMMAND_LINE_SIZE);
325#endif 331#endif
326 /*
327 * Append .config cmdline to base command line, which might already
328 * contain u-boot "bootargs" (handled by head.S, if so configured)
329 */
330 strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
331 332
332 /* Save unparsed command line copy for /proc/cmdline */ 333 /* Save unparsed command line copy for /proc/cmdline */
333 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 334 *cmdline_p = boot_command_line;
334 *cmdline_p = command_line;
335
336 machine_desc = setup_machine_fdt(__dtb_start);
337 if (!machine_desc)
338 panic("Embedded DT invalid\n");
339 335
340 /* To force early parsing of things like mem=xxx */ 336 /* To force early parsing of things like mem=xxx */
341 parse_early_param(); 337 parse_early_param();
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index f13f72807aa5..09f4309aa2c0 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -33,7 +33,6 @@
33#include <linux/module.h> 33#include <linux/module.h>
34#include <linux/sched.h> 34#include <linux/sched.h>
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/interrupt.h>
37#include <linux/time.h> 36#include <linux/time.h>
38#include <linux/init.h> 37#include <linux/init.h>
39#include <linux/timex.h> 38#include <linux/timex.h>
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index 7496995371e8..0471d9c9dd54 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -16,11 +16,12 @@
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/kdebug.h> 17#include <linux/kdebug.h>
18#include <linux/uaccess.h> 18#include <linux/uaccess.h>
19#include <asm/ptrace.h> 19#include <linux/ptrace.h>
20#include <linux/kprobes.h>
21#include <linux/kgdb.h>
20#include <asm/setup.h> 22#include <asm/setup.h>
21#include <asm/kprobes.h>
22#include <asm/unaligned.h> 23#include <asm/unaligned.h>
23#include <asm/kgdb.h> 24#include <asm/kprobes.h>
24 25
25void __init trap_init(void) 26void __init trap_init(void)
26{ 27{
@@ -83,6 +84,7 @@ DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
83DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC) 84DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
84DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR) 85DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
85DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT) 86DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
87DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
86 88
87#ifdef CONFIG_ARC_MISALIGN_ACCESS 89#ifdef CONFIG_ARC_MISALIGN_ACCESS
88/* 90/*
@@ -91,21 +93,11 @@ DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
91int do_misaligned_access(unsigned long cause, unsigned long address, 93int do_misaligned_access(unsigned long cause, unsigned long address,
92 struct pt_regs *regs, struct callee_regs *cregs) 94 struct pt_regs *regs, struct callee_regs *cregs)
93{ 95{
94 if (misaligned_fixup(address, regs, cause, cregs) != 0) { 96 if (misaligned_fixup(address, regs, cause, cregs) != 0)
95 siginfo_t info; 97 return do_misaligned_error(cause, address, regs);
96 98
97 info.si_signo = SIGBUS;
98 info.si_errno = 0;
99 info.si_code = BUS_ADRALN;
100 info.si_addr = (void __user *)address;
101 return handle_exception(cause, "Misaligned Access", regs,
102 &info);
103 }
104 return 0; 99 return 0;
105} 100}
106
107#else
108DO_ERROR_INFO(SIGSEGV, "Misaligned Access", do_misaligned_access, SEGV_ACCERR)
109#endif 101#endif
110 102
111/* 103/*
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index 0aec01985bf9..11c301b81c92 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -26,7 +26,6 @@ static noinline void print_reg_file(long *reg_rev, int start_num)
26 char buf[512]; 26 char buf[512];
27 int n = 0, len = sizeof(buf); 27 int n = 0, len = sizeof(buf);
28 28
29 /* weird loop because pt_regs regs rev r12..r0, r25..r13 */
30 for (i = start_num; i < start_num + 13; i++) { 29 for (i = start_num; i < start_num + 13; i++) {
31 n += scnprintf(buf + n, len - n, "r%02u: 0x%08lx\t", 30 n += scnprintf(buf + n, len - n, "r%02u: 0x%08lx\t",
32 i, (unsigned long)*reg_rev); 31 i, (unsigned long)*reg_rev);
@@ -34,13 +33,18 @@ static noinline void print_reg_file(long *reg_rev, int start_num)
34 if (((i + 1) % 3) == 0) 33 if (((i + 1) % 3) == 0)
35 n += scnprintf(buf + n, len - n, "\n"); 34 n += scnprintf(buf + n, len - n, "\n");
36 35
36 /* because pt_regs has regs reversed: r12..r0, r25..r13 */
37 reg_rev--; 37 reg_rev--;
38 } 38 }
39 39
40 if (start_num != 0) 40 if (start_num != 0)
41 n += scnprintf(buf + n, len - n, "\n\n"); 41 n += scnprintf(buf + n, len - n, "\n\n");
42 42
43 pr_info("%s", buf); 43 /* To continue printing callee regs on same line as scratch regs */
44 if (start_num == 0)
45 pr_info("%s", buf);
46 else
47 pr_cont("%s\n", buf);
44} 48}
45 49
46static void show_callee_regs(struct callee_regs *cregs) 50static void show_callee_regs(struct callee_regs *cregs)
@@ -83,6 +87,10 @@ static void show_faulting_vma(unsigned long address, char *buf)
83 dev_t dev = 0; 87 dev_t dev = 0;
84 char *nm = buf; 88 char *nm = buf;
85 89
90 /* can't use print_vma_addr() yet as it doesn't check for
91 * non-inclusive vma
92 */
93
86 vma = find_vma(current->active_mm, address); 94 vma = find_vma(current->active_mm, address);
87 95
88 /* check against the find_vma( ) behaviour which returns the next VMA 96 /* check against the find_vma( ) behaviour which returns the next VMA
@@ -98,10 +106,13 @@ static void show_faulting_vma(unsigned long address, char *buf)
98 ino = inode->i_ino; 106 ino = inode->i_ino;
99 } 107 }
100 pr_info(" @off 0x%lx in [%s]\n" 108 pr_info(" @off 0x%lx in [%s]\n"
101 " VMA: 0x%08lx to 0x%08lx\n\n", 109 " VMA: 0x%08lx to 0x%08lx\n",
102 address - vma->vm_start, nm, vma->vm_start, vma->vm_end); 110 vma->vm_start < TASK_UNMAPPED_BASE ?
103 } else 111 address : address - vma->vm_start,
112 nm, vma->vm_start, vma->vm_end);
113 } else {
104 pr_info(" @No matching VMA found\n"); 114 pr_info(" @No matching VMA found\n");
115 }
105} 116}
106 117
107static void show_ecr_verbose(struct pt_regs *regs) 118static void show_ecr_verbose(struct pt_regs *regs)
@@ -110,7 +121,7 @@ static void show_ecr_verbose(struct pt_regs *regs)
110 unsigned long address; 121 unsigned long address;
111 122
112 cause_reg = current->thread.cause_code; 123 cause_reg = current->thread.cause_code;
113 pr_info("\n[ECR]: 0x%08x => ", cause_reg); 124 pr_info("\n[ECR ]: 0x%08x => ", cause_reg);
114 125
115 /* For Data fault, this is data address not instruction addr */ 126 /* For Data fault, this is data address not instruction addr */
116 address = current->thread.fault_address; 127 address = current->thread.fault_address;
@@ -120,7 +131,7 @@ static void show_ecr_verbose(struct pt_regs *regs)
120 131
121 /* For DTLB Miss or ProtV, display the memory involved too */ 132 /* For DTLB Miss or ProtV, display the memory involved too */
122 if (vec == ECR_V_DTLB_MISS) { 133 if (vec == ECR_V_DTLB_MISS) {
123 pr_cont("Invalid (%s) @ 0x%08lx by insn @ 0x%08lx\n", 134 pr_cont("Invalid %s 0x%08lx by insn @ 0x%08lx\n",
124 (cause_code == 0x01) ? "Read From" : 135 (cause_code == 0x01) ? "Read From" :
125 ((cause_code == 0x02) ? "Write to" : "EX"), 136 ((cause_code == 0x02) ? "Write to" : "EX"),
126 address, regs->ret); 137 address, regs->ret);
@@ -168,20 +179,23 @@ void show_regs(struct pt_regs *regs)
168 if (current->thread.cause_code) 179 if (current->thread.cause_code)
169 show_ecr_verbose(regs); 180 show_ecr_verbose(regs);
170 181
171 pr_info("[EFA]: 0x%08lx\n", current->thread.fault_address); 182 pr_info("[EFA ]: 0x%08lx\n[BLINK ]: %pS\n[ERET ]: %pS\n",
172 pr_info("[ERET]: 0x%08lx (PC of Faulting Instr)\n", regs->ret); 183 current->thread.fault_address,
184 (void *)regs->blink, (void *)regs->ret);
173 185
174 show_faulting_vma(regs->ret, buf); /* faulting code, not data */ 186 if (user_mode(regs))
187 show_faulting_vma(regs->ret, buf); /* faulting code, not data */
175 188
176 /* can't use print_vma_addr() yet as it doesn't check for 189 pr_info("[STAT32]: 0x%08lx", regs->status32);
177 * non-inclusive vma 190
178 */ 191#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit : ""
192 if (!user_mode(regs))
193 pr_cont(" : %2s %2s %2s %2s %2s\n",
194 STS_BIT(regs, AE), STS_BIT(regs, A2), STS_BIT(regs, A1),
195 STS_BIT(regs, E2), STS_BIT(regs, E1));
179 196
180 /* print special regs */ 197 pr_info("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n",
181 pr_info("status32: 0x%08lx\n", regs->status32); 198 regs->bta, regs->sp, regs->fp);
182 pr_info(" SP: 0x%08lx\tFP: 0x%08lx\n", regs->sp, regs->fp);
183 pr_info("BTA: 0x%08lx\tBLINK: 0x%08lx\n",
184 regs->bta, regs->blink);
185 pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", 199 pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
186 regs->lp_start, regs->lp_end, regs->lp_count); 200 regs->lp_start, regs->lp_end, regs->lp_count);
187 201
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 88d617d84234..c854cf95f706 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -72,16 +72,6 @@
72#include <asm/cachectl.h> 72#include <asm/cachectl.h>
73#include <asm/setup.h> 73#include <asm/setup.h>
74 74
75
76#ifdef CONFIG_ARC_HAS_ICACHE
77static void __ic_line_inv_no_alias(unsigned long, int);
78static void __ic_line_inv_2_alias(unsigned long, int);
79static void __ic_line_inv_4_alias(unsigned long, int);
80
81/* Holds the ptr to flush routine, dependign on size due to aliasing issues */
82static void (*___flush_icache_rtn) (unsigned long, int);
83#endif
84
85char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) 75char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
86{ 76{
87 int n = 0; 77 int n = 0;
@@ -109,7 +99,7 @@ char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
109 * the cpuinfo structure for later use. 99 * the cpuinfo structure for later use.
110 * No Validation done here, simply read/convert the BCRs 100 * No Validation done here, simply read/convert the BCRs
111 */ 101 */
112void __init read_decode_cache_bcr(void) 102void __cpuinit read_decode_cache_bcr(void)
113{ 103{
114 struct bcr_cache ibcr, dbcr; 104 struct bcr_cache ibcr, dbcr;
115 struct cpuinfo_arc_cache *p_ic, *p_dc; 105 struct cpuinfo_arc_cache *p_ic, *p_dc;
@@ -141,7 +131,7 @@ void __init read_decode_cache_bcr(void)
141 * 3. Enable the Caches, setup default flush mode for D-Cache 131 * 3. Enable the Caches, setup default flush mode for D-Cache
142 * 3. Calculate the SHMLBA used by user space 132 * 3. Calculate the SHMLBA used by user space
143 */ 133 */
144void __init arc_cache_init(void) 134void __cpuinit arc_cache_init(void)
145{ 135{
146 unsigned int temp; 136 unsigned int temp;
147 unsigned int cpu = smp_processor_id(); 137 unsigned int cpu = smp_processor_id();
@@ -171,30 +161,6 @@ void __init arc_cache_init(void)
171 161
172 } 162 }
173#endif 163#endif
174
175 /*
176 * if Cache way size is <= page size then no aliasing exhibited
177 * otherwise ratio determines num of aliases.
178 * e.g. 32K I$, 2 way set assoc, 8k pg size
179 * way-sz = 32k/2 = 16k
180 * way-pg-ratio = 16k/8k = 2, so 2 aliases possible
181 * (meaning 1 line could be in 2 possible locations).
182 */
183 way_pg_ratio = ic->sz / ARC_ICACHE_WAYS / PAGE_SIZE;
184 switch (way_pg_ratio) {
185 case 0:
186 case 1:
187 ___flush_icache_rtn = __ic_line_inv_no_alias;
188 break;
189 case 2:
190 ___flush_icache_rtn = __ic_line_inv_2_alias;
191 break;
192 case 4:
193 ___flush_icache_rtn = __ic_line_inv_4_alias;
194 break;
195 default:
196 panic("Unsupported I-Cache Sz\n");
197 }
198#endif 164#endif
199 165
200 /* Enable/disable I-Cache */ 166 /* Enable/disable I-Cache */
@@ -391,75 +357,38 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
391/* 357/*
392 * I-Cache Aliasing in ARC700 VIPT caches 358 * I-Cache Aliasing in ARC700 VIPT caches
393 * 359 *
394 * For fetching code from I$, ARC700 uses vaddr (embedded in program code) 360 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
395 * to "index" into SET of cache-line and paddr from MMU to match the TAG 361 * The orig Cache Management Module "CDU" only required paddr to invalidate a
396 * in the WAYS of SET. 362 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
363 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
364 * the exact same line.
397 * 365 *
398 * However the CDU iterface (to flush/inv) lines from software, only takes 366 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
399 * paddr (to have simpler hardware interface). For simpler cases, using paddr 367 * paddr alone could not be used to correctly index the cache.
400 * alone suffices.
401 * e.g. 2-way-set-assoc, 16K I$ (8k MMU pg sz, 32b cache line size):
402 * way_sz = cache_sz / num_ways = 16k/2 = 8k
403 * num_sets = way_sz / line_sz = 8k/32 = 256 => 8 bits
404 * Ignoring the bottom 5 bits corresp to the off within a 32b cacheline,
405 * bits req for calc set-index = bits 12:5 (0 based). Since this range fits
406 * inside the bottom 13 bits of paddr, which are same for vaddr and paddr
407 * (with 8k pg sz), paddr alone can be safely used by CDU to unambigously
408 * locate a cache-line.
409 *
410 * However for a difft sized cache, say 32k I$, above math yields need
411 * for 14 bits of vaddr to locate a cache line, which can't be provided by
412 * paddr, since the bit 13 (0 based) might differ between the two.
413 *
414 * This lack of extra bits needed for correct line addressing, defines the
415 * classical problem of Cache aliasing with VIPT architectures
416 * num_aliases = 1 << extra_bits
417 * e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz => 2 aliases
418 * 2-way-set-assoc, 64K I$ with 8k MMU pg sz => 4 aliases
419 * 2-way-set-assoc, 16K I$ with 8k MMU pg sz => NO aliases
420 * 368 *
421 * ------------------ 369 * ------------------
422 * MMU v1/v2 (Fixed Page Size 8k) 370 * MMU v1/v2 (Fixed Page Size 8k)
423 * ------------------ 371 * ------------------
424 * The solution was to provide CDU with these additonal vaddr bits. These 372 * The solution was to provide CDU with these additonal vaddr bits. These
425 * would be bits [x:13], x would depend on cache-geom. 373 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
374 * standard page size of 8k.
426 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits 375 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
427 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the 376 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
428 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they 377 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
429 * represent the offset within cache-line. The adv of using this "clumsy" 378 * represent the offset within cache-line. The adv of using this "clumsy"
430 * interface for additional info was no new reg was needed in CDU. 379 * interface for additional info was no new reg was needed in CDU programming
380 * model.
431 * 381 *
432 * 17:13 represented the max num of bits passable, actual bits needed were 382 * 17:13 represented the max num of bits passable, actual bits needed were
433 * fewer, based on the num-of-aliases possible. 383 * fewer, based on the num-of-aliases possible.
434 * -for 2 alias possibility, only bit 13 needed (32K cache) 384 * -for 2 alias possibility, only bit 13 needed (32K cache)
435 * -for 4 alias possibility, bits 14:13 needed (64K cache) 385 * -for 4 alias possibility, bits 14:13 needed (64K cache)
436 * 386 *
437 * Since vaddr was not available for all instances of I$ flush req by core
438 * kernel, the only safe way (non-optimal though) was to kill all possible
439 * lines which could represent an alias (even if they didnt represent one
440 * in execution).
441 * e.g. for 64K I$, 4 aliases possible, so we did
442 * flush start
443 * flush start | 0x01
444 * flush start | 0x2
445 * flush start | 0x3
446 *
447 * The penalty was invoking the operation itself, since tag match is anyways
448 * paddr based, a line which didn't represent an alias would not match the
449 * paddr, hence wont be killed
450 *
451 * Note that aliasing concerns are independent of line-sz for a given cache
452 * geometry (size + set_assoc) because the extra bits required by line-sz are
453 * reduced from the set calc.
454 * e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz and using math above
455 * 32b line-sz: 9 bits set-index-calc, 5 bits offset-in-line => 1 extra bit
456 * 64b line-sz: 8 bits set-index-calc, 6 bits offset-in-line => 1 extra bit
457 *
458 * ------------------ 387 * ------------------
459 * MMU v3 388 * MMU v3
460 * ------------------ 389 * ------------------
461 * This ver of MMU supports var page sizes (1k-16k) - Linux will support 390 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
462 * 8k (default), 16k and 4k. 391 * only support 8k (default), 16k and 4k.
463 * However from hardware perspective, smaller page sizes aggrevate aliasing 392 * However from hardware perspective, smaller page sizes aggrevate aliasing
464 * meaning more vaddr bits needed to disambiguate the cache-line-op ; 393 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
465 * the existing scheme of piggybacking won't work for certain configurations. 394 * the existing scheme of piggybacking won't work for certain configurations.
@@ -468,115 +397,29 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
468 */ 397 */
469 398
470/*********************************************************** 399/***********************************************************
471 * Machine specific helpers for per line I-Cache invalidate. 400 * Machine specific helper for per line I-Cache invalidate.
472 * 3 routines to accpunt for 1, 2, 4 aliases possible
473 */ 401 */
474 402static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
475static void __ic_line_inv_no_alias(unsigned long start, int num_lines) 403 unsigned long sz)
476{
477 while (num_lines-- > 0) {
478#if (CONFIG_ARC_MMU_VER > 2)
479 write_aux_reg(ARC_REG_IC_PTAG, start);
480#endif
481 write_aux_reg(ARC_REG_IC_IVIL, start);
482 start += ARC_ICACHE_LINE_LEN;
483 }
484}
485
486static void __ic_line_inv_2_alias(unsigned long start, int num_lines)
487{
488 while (num_lines-- > 0) {
489
490#if (CONFIG_ARC_MMU_VER > 2)
491 /*
492 * MMU v3, CDU prog model (for line ops) now uses a new IC_PTAG
493 * reg to pass the "tag" bits and existing IVIL reg only looks
494 * at bits relevant for "index" (details above)
495 * Programming Notes:
496 * -when writing tag to PTAG reg, bit chopping can be avoided,
497 * CDU ignores non-tag bits.
498 * -Ideally "index" must be computed from vaddr, but it is not
499 * avail in these rtns. So to be safe, we kill the lines in all
500 * possible indexes corresp to num of aliases possible for
501 * given cache config.
502 */
503 write_aux_reg(ARC_REG_IC_PTAG, start);
504 write_aux_reg(ARC_REG_IC_IVIL,
505 start & ~(0x1 << PAGE_SHIFT));
506 write_aux_reg(ARC_REG_IC_IVIL, start | (0x1 << PAGE_SHIFT));
507#else
508 write_aux_reg(ARC_REG_IC_IVIL, start);
509 write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
510#endif
511 start += ARC_ICACHE_LINE_LEN;
512 }
513}
514
515static void __ic_line_inv_4_alias(unsigned long start, int num_lines)
516{
517 while (num_lines-- > 0) {
518
519#if (CONFIG_ARC_MMU_VER > 2)
520 write_aux_reg(ARC_REG_IC_PTAG, start);
521
522 write_aux_reg(ARC_REG_IC_IVIL,
523 start & ~(0x3 << PAGE_SHIFT));
524 write_aux_reg(ARC_REG_IC_IVIL,
525 start & ~(0x2 << PAGE_SHIFT));
526 write_aux_reg(ARC_REG_IC_IVIL,
527 start & ~(0x1 << PAGE_SHIFT));
528 write_aux_reg(ARC_REG_IC_IVIL, start | (0x3 << PAGE_SHIFT));
529#else
530 write_aux_reg(ARC_REG_IC_IVIL, start);
531 write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
532 write_aux_reg(ARC_REG_IC_IVIL, start | 0x02);
533 write_aux_reg(ARC_REG_IC_IVIL, start | 0x03);
534#endif
535 start += ARC_ICACHE_LINE_LEN;
536 }
537}
538
539static void __ic_line_inv(unsigned long start, unsigned long sz)
540{ 404{
541 unsigned long flags; 405 unsigned long flags;
542 int num_lines, slack; 406 int num_lines, slack;
407 unsigned int addr;
543 408
544 /* 409 /*
545 * Ensure we properly floor/ceil the non-line aligned/sized requests 410 * Ensure we properly floor/ceil the non-line aligned/sized requests:
546 * and have @start - aligned to cache line, and integral @num_lines
547 * However page sized flushes can be compile time optimised. 411 * However page sized flushes can be compile time optimised.
548 * -@start will be cache-line aligned already (being page aligned) 412 * -@phy_start will be cache-line aligned already (being page aligned)
549 * -@sz will be integral multiple of line size (being page sized). 413 * -@sz will be integral multiple of line size (being page sized).
550 */ 414 */
551 if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) { 415 if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
552 slack = start & ~ICACHE_LINE_MASK; 416 slack = phy_start & ~ICACHE_LINE_MASK;
553 sz += slack; 417 sz += slack;
554 start -= slack; 418 phy_start -= slack;
555 } 419 }
556 420
557 num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN); 421 num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
558 422
559 local_irq_save(flags);
560 (*___flush_icache_rtn) (start, num_lines);
561 local_irq_restore(flags);
562}
563
564/* Unlike routines above, having vaddr for flush op (along with paddr),
565 * prevents the need to speculatively kill the lines in multiple sets
566 * based on ratio of way_sz : pg_sz
567 */
568static void __ic_line_inv_vaddr(unsigned long phy_start,
569 unsigned long vaddr, unsigned long sz)
570{
571 unsigned long flags;
572 int num_lines, slack;
573 unsigned int addr;
574
575 slack = phy_start & ~ICACHE_LINE_MASK;
576 sz += slack;
577 phy_start -= slack;
578 num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
579
580#if (CONFIG_ARC_MMU_VER > 2) 423#if (CONFIG_ARC_MMU_VER > 2)
581 vaddr &= ~ICACHE_LINE_MASK; 424 vaddr &= ~ICACHE_LINE_MASK;
582 addr = phy_start; 425 addr = phy_start;
@@ -595,7 +438,7 @@ static void __ic_line_inv_vaddr(unsigned long phy_start,
595 write_aux_reg(ARC_REG_IC_IVIL, vaddr); 438 write_aux_reg(ARC_REG_IC_IVIL, vaddr);
596 vaddr += ARC_ICACHE_LINE_LEN; 439 vaddr += ARC_ICACHE_LINE_LEN;
597#else 440#else
598 /* this paddr contains vaddrs bits as needed */ 441 /* paddr contains stuffed vaddrs bits */
599 write_aux_reg(ARC_REG_IC_IVIL, addr); 442 write_aux_reg(ARC_REG_IC_IVIL, addr);
600#endif 443#endif
601 addr += ARC_ICACHE_LINE_LEN; 444 addr += ARC_ICACHE_LINE_LEN;
@@ -605,7 +448,6 @@ static void __ic_line_inv_vaddr(unsigned long phy_start,
605 448
606#else 449#else
607 450
608#define __ic_line_inv(start, sz)
609#define __ic_line_inv_vaddr(pstart, vstart, sz) 451#define __ic_line_inv_vaddr(pstart, vstart, sz)
610 452
611#endif /* CONFIG_ARC_HAS_ICACHE */ 453#endif /* CONFIG_ARC_HAS_ICACHE */
@@ -615,10 +457,10 @@ static void __ic_line_inv_vaddr(unsigned long phy_start,
615 * Exported APIs 457 * Exported APIs
616 */ 458 */
617 459
618/* TBD: use pg_arch_1 to optimize this */
619void flush_dcache_page(struct page *page) 460void flush_dcache_page(struct page *page)
620{ 461{
621 __dc_line_op((unsigned long)page_address(page), PAGE_SIZE, OP_FLUSH); 462 /* Make a note that dcache is not yet flushed for this page */
463 set_bit(PG_arch_1, &page->flags);
622} 464}
623EXPORT_SYMBOL(flush_dcache_page); 465EXPORT_SYMBOL(flush_dcache_page);
624 466
@@ -642,8 +484,8 @@ void dma_cache_wback(unsigned long start, unsigned long sz)
642EXPORT_SYMBOL(dma_cache_wback); 484EXPORT_SYMBOL(dma_cache_wback);
643 485
644/* 486/*
645 * This is API for making I/D Caches consistent when modifying code 487 * This is API for making I/D Caches consistent when modifying
646 * (loadable modules, kprobes, etc) 488 * kernel code (loadable modules, kprobes, kgdb...)
647 * This is called on insmod, with kernel virtual address for CODE of 489 * This is called on insmod, with kernel virtual address for CODE of
648 * the module. ARC cache maintenance ops require PHY address thus we 490 * the module. ARC cache maintenance ops require PHY address thus we
649 * need to convert vmalloc addr to PHY addr 491 * need to convert vmalloc addr to PHY addr
@@ -652,7 +494,6 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
652{ 494{
653 unsigned int tot_sz, off, sz; 495 unsigned int tot_sz, off, sz;
654 unsigned long phy, pfn; 496 unsigned long phy, pfn;
655 unsigned long flags;
656 497
657 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */ 498 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
658 499
@@ -673,8 +514,13 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
673 514
674 /* Case: Kernel Phy addr (0x8000_0000 onwards) */ 515 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
675 if (likely(kstart > PAGE_OFFSET)) { 516 if (likely(kstart > PAGE_OFFSET)) {
676 __ic_line_inv(kstart, kend - kstart); 517 /*
677 __dc_line_op(kstart, kend - kstart, OP_FLUSH); 518 * The 2nd arg despite being paddr will be used to index icache
519 * This is OK since no alternate virtual mappings will exist
520 * given the callers for this case: kprobe/kgdb in built-in
521 * kernel code only.
522 */
523 __sync_icache_dcache(kstart, kstart, kend - kstart);
678 return; 524 return;
679 } 525 }
680 526
@@ -692,42 +538,41 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
692 pfn = vmalloc_to_pfn((void *)kstart); 538 pfn = vmalloc_to_pfn((void *)kstart);
693 phy = (pfn << PAGE_SHIFT) + off; 539 phy = (pfn << PAGE_SHIFT) + off;
694 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); 540 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
695 local_irq_save(flags); 541 __sync_icache_dcache(phy, kstart, sz);
696 __dc_line_op(phy, sz, OP_FLUSH);
697 __ic_line_inv(phy, sz);
698 local_irq_restore(flags);
699 kstart += sz; 542 kstart += sz;
700 tot_sz -= sz; 543 tot_sz -= sz;
701 } 544 }
702} 545}
703 546
704/* 547/*
705 * Optimised ver of flush_icache_range() with spec callers: ptrace/signals 548 * General purpose helper to make I and D cache lines consistent.
706 * where vaddr is also available. This allows passing both vaddr and paddr 549 * @paddr is phy addr of region
707 * bits to CDU for cache flush, short-circuting the current pessimistic algo 550 * @vaddr is typically user or kernel vaddr (vmalloc)
708 * which kills all possible aliases. 551 * Howver in one instance, flush_icache_range() by kprobe (for a breakpt in
709 * An added adv of knowing that vaddr is user-vaddr avoids various checks 552 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
710 * and handling for k-vaddr, k-paddr as done in orig ver above 553 * use a paddr to index the cache (despite VIPT). This is fine since since a
554 * built-in kernel page will not have any virtual mappings (not even kernel)
555 * kprobe on loadable module is different as it will have kvaddr.
711 */ 556 */
712void flush_icache_range_vaddr(unsigned long paddr, unsigned long u_vaddr, 557void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
713 int len)
714{ 558{
715 __ic_line_inv_vaddr(paddr, u_vaddr, len); 559 unsigned long flags;
560
561 local_irq_save(flags);
562 __ic_line_inv_vaddr(paddr, vaddr, len);
716 __dc_line_op(paddr, len, OP_FLUSH); 563 __dc_line_op(paddr, len, OP_FLUSH);
564 local_irq_restore(flags);
717} 565}
718 566
719/* 567/* wrapper to compile time eliminate alignment checks in flush loop */
720 * XXX: This also needs to be optim using pg_arch_1 568void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
721 * This is called when a page-cache page is about to be mapped into a
722 * user process' address space. It offers an opportunity for a
723 * port to ensure d-cache/i-cache coherency if necessary.
724 */
725void flush_icache_page(struct vm_area_struct *vma, struct page *page)
726{ 569{
727 if (!(vma->vm_flags & VM_EXEC)) 570 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
728 return; 571}
729 572
730 __ic_line_inv((unsigned long)page_address(page), PAGE_SIZE); 573void __flush_dcache_page(unsigned long paddr)
574{
575 __dc_line_op(paddr, PAGE_SIZE, OP_FLUSH_N_INV);
731} 576}
732 577
733void flush_icache_all(void) 578void flush_icache_all(void)
diff --git a/arch/arc/mm/extable.c b/arch/arc/mm/extable.c
index 014172ba8432..aa652e281324 100644
--- a/arch/arc/mm/extable.c
+++ b/arch/arc/mm/extable.c
@@ -27,7 +27,7 @@ int fixup_exception(struct pt_regs *regs)
27 27
28#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE 28#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
29 29
30long arc_copy_from_user_noinline(void *to, const void __user * from, 30long arc_copy_from_user_noinline(void *to, const void __user *from,
31 unsigned long n) 31 unsigned long n)
32{ 32{
33 return __arc_copy_from_user(to, from, n); 33 return __arc_copy_from_user(to, from, n);
@@ -48,7 +48,7 @@ unsigned long arc_clear_user_noinline(void __user *to,
48} 48}
49EXPORT_SYMBOL(arc_clear_user_noinline); 49EXPORT_SYMBOL(arc_clear_user_noinline);
50 50
51long arc_strncpy_from_user_noinline (char *dst, const char __user *src, 51long arc_strncpy_from_user_noinline(char *dst, const char __user *src,
52 long count) 52 long count)
53{ 53{
54 return __arc_strncpy_from_user(dst, src, count); 54 return __arc_strncpy_from_user(dst, src, count);
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index af55aab803d2..689ffd86d5e9 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -12,7 +12,6 @@
12#include <linux/sched.h> 12#include <linux/sched.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/ptrace.h> 14#include <linux/ptrace.h>
15#include <linux/version.h>
16#include <linux/uaccess.h> 15#include <linux/uaccess.h>
17#include <linux/kdebug.h> 16#include <linux/kdebug.h>
18#include <asm/pgalloc.h> 17#include <asm/pgalloc.h>
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 727d4794ea0f..4a177365b2c4 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -10,9 +10,6 @@
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12#include <linux/memblock.h> 12#include <linux/memblock.h>
13#ifdef CONFIG_BLOCK_DEV_RAM
14#include <linux/blk.h>
15#endif
16#include <linux/swap.h> 13#include <linux/swap.h>
17#include <linux/module.h> 14#include <linux/module.h>
18#include <asm/page.h> 15#include <asm/page.h>
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 3e5c92c79936..739e65f355de 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -12,7 +12,7 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <asm/cache.h> 15#include <linux/cache.h>
16 16
17void __iomem *ioremap(unsigned long paddr, unsigned long size) 17void __iomem *ioremap(unsigned long paddr, unsigned long size)
18{ 18{
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 9b9ce23f4ec3..003d69ac6ffa 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -418,23 +418,37 @@ void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
418 local_irq_restore(flags); 418 local_irq_restore(flags);
419} 419}
420 420
421/* arch hook called by core VM at the end of handle_mm_fault( ), 421/*
422 * when a new PTE is entered in Page Tables or an existing one 422 * Called at the end of pagefault, for a userspace mapped page
423 * is modified. We aggresively pre-install a TLB entry 423 * -pre-install the corresponding TLB entry into MMU
424 * -Finalize the delayed D-cache flush (wback+inv kernel mapping)
424 */ 425 */
425 426void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
426void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddress,
427 pte_t *ptep) 427 pte_t *ptep)
428{ 428{
429 unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
430
431 create_tlb(vma, vaddr, ptep);
429 432
430 create_tlb(vma, vaddress, ptep); 433 /* icache doesn't snoop dcache, thus needs to be made coherent here */
434 if (vma->vm_flags & VM_EXEC) {
435 struct page *page = pfn_to_page(pte_pfn(*ptep));
436
437 /* if page was dcache dirty, flush now */
438 int dirty = test_and_clear_bit(PG_arch_1, &page->flags);
439 if (dirty) {
440 unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
441 __flush_dcache_page(paddr);
442 __inv_icache_page(paddr, vaddr);
443 }
444 }
431} 445}
432 446
433/* Read the Cache Build Confuration Registers, Decode them and save into 447/* Read the Cache Build Confuration Registers, Decode them and save into
434 * the cpuinfo structure for later use. 448 * the cpuinfo structure for later use.
435 * No Validation is done here, simply read/convert the BCRs 449 * No Validation is done here, simply read/convert the BCRs
436 */ 450 */
437void __init read_decode_mmu_bcr(void) 451void __cpuinit read_decode_mmu_bcr(void)
438{ 452{
439 unsigned int tmp; 453 unsigned int tmp;
440 struct bcr_mmu_1_2 *mmu2; /* encoded MMU2 attr */ 454 struct bcr_mmu_1_2 *mmu2; /* encoded MMU2 attr */
@@ -466,7 +480,7 @@ void __init read_decode_mmu_bcr(void)
466char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) 480char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
467{ 481{
468 int n = 0; 482 int n = 0;
469 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[smp_processor_id()].mmu; 483 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
470 484
471 n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ", 485 n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
472 p_mmu->ver, TO_KB(p_mmu->pg_sz)); 486 p_mmu->ver, TO_KB(p_mmu->pg_sz));
@@ -480,7 +494,7 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
480 return buf; 494 return buf;
481} 495}
482 496
483void __init arc_mmu_init(void) 497void __cpuinit arc_mmu_init(void)
484{ 498{
485 char str[256]; 499 char str[256];
486 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; 500 struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c
index 4e20a1a5104d..b3700c064c06 100644
--- a/arch/arc/plat-arcfpga/platform.c
+++ b/arch/arc/plat-arcfpga/platform.c
@@ -224,3 +224,15 @@ MACHINE_START(ML509, "ml509")
224 .init_smp = iss_model_init_smp, 224 .init_smp = iss_model_init_smp,
225#endif 225#endif
226MACHINE_END 226MACHINE_END
227
228static const char *nsimosci_compat[] __initdata = {
229 "snps,nsimosci",
230 NULL,
231};
232
233MACHINE_START(NSIMOSCI, "nsimosci")
234 .dt_compat = nsimosci_compat,
235 .init_early = NULL,
236 .init_machine = plat_fpga_populate_dev,
237 .init_irq = NULL,
238MACHINE_END
diff --git a/arch/arc/plat-tb10x/Kconfig b/arch/arc/plat-tb10x/Kconfig
new file mode 100644
index 000000000000..4e121272c4e5
--- /dev/null
+++ b/arch/arc/plat-tb10x/Kconfig
@@ -0,0 +1,36 @@
1# Abilis Systems TB10x platform kernel configuration file
2#
3# Author: Christian Ruppert <christian.ruppert@abilis.com>
4#
5# This program is free software; you can redistribute it and/or modify
6# it under the terms of the GNU General Public License version 2 as
7# published by the Free Software Foundation.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17
18
19menuconfig ARC_PLAT_TB10X
20 bool "Abilis TB10x"
21 select COMMON_CLK
22 select PINCTRL
23 select PINMUX
24 select ARCH_REQUIRE_GPIOLIB
25 help
26 Support for platforms based on the TB10x home media gateway SOC by
27 Abilis Systems. TB10x is based on the ARC700 CPU architecture.
28 Say Y if you are building a kernel for one of the SOCs in this
29 series (e.g. TB100 or TB101). If in doubt say N.
30
31if ARC_PLAT_TB10X
32
33config GENERIC_GPIO
34 def_bool y
35
36endif
diff --git a/arch/arc/plat-tb10x/Makefile b/arch/arc/plat-tb10x/Makefile
new file mode 100644
index 000000000000..89611d25ef35
--- /dev/null
+++ b/arch/arc/plat-tb10x/Makefile
@@ -0,0 +1,21 @@
1# Abilis Systems TB10x platform Makefile
2#
3# Author: Christian Ruppert <christian.ruppert@abilis.com>
4#
5# This program is free software; you can redistribute it and/or modify
6# it under the terms of the GNU General Public License version 2 as
7# published by the Free Software Foundation.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17
18
19KBUILD_CFLAGS += -Iarch/arc/plat-tb10x/include
20
21obj-y += tb10x.o
diff --git a/arch/arc/plat-tb10x/tb10x.c b/arch/arc/plat-tb10x/tb10x.c
new file mode 100644
index 000000000000..d3567691c7e1
--- /dev/null
+++ b/arch/arc/plat-tb10x/tb10x.c
@@ -0,0 +1,71 @@
1/*
2 * Abilis Systems TB10x platform initialisation
3 *
4 * Copyright (C) Abilis Systems 2012
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22
23#include <linux/init.h>
24#include <linux/of_platform.h>
25#include <linux/clk-provider.h>
26#include <linux/pinctrl/consumer.h>
27
28#include <asm/mach_desc.h>
29
30
31static void __init tb10x_platform_init(void)
32{
33 of_clk_init(NULL);
34 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
35}
36
37static void __init tb10x_platform_late_init(void)
38{
39 struct device_node *dn;
40
41 /*
42 * Pinctrl documentation recommends setting up the iomux here for
43 * all modules which don't require control over the pins themselves.
44 * Modules which need this kind of assistance are compatible with
45 * "abilis,simple-pinctrl", i.e. we can easily iterate over them.
46 * TODO: Does this recommended method work cleanly with pins required
47 * by modules?
48 */
49 for_each_compatible_node(dn, NULL, "abilis,simple-pinctrl") {
50 struct platform_device *pd = of_find_device_by_node(dn);
51 struct pinctrl *pctl;
52
53 pctl = pinctrl_get_select(&pd->dev, "abilis,simple-default");
54 if (IS_ERR(pctl)) {
55 int ret = PTR_ERR(pctl);
56 dev_err(&pd->dev, "Could not set up pinctrl: %d\n",
57 ret);
58 }
59 }
60}
61
62static const char *tb10x_compat[] __initdata = {
63 "abilis,arc-tb10x",
64 NULL,
65};
66
67MACHINE_START(TB10x, "tb10x")
68 .dt_compat = tb10x_compat,
69 .init_machine = tb10x_platform_init,
70 .init_late = tb10x_platform_late_init,
71MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 07:26:44 -0400