[ARM] S3C24XX: Split pll code out of regs-clock.h

Move the PLL calculation code into it's own header
file for re-use with the other plat-s3c24xx based
systems such as the S3C24A0.

Note, we change the name of s3c2410_get_pll to the
more generically named s3c24xx_get_pll as well as
the related defintions.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

7 files changed, 49 insertions, 41 deletions

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index b3f90aa78076..2a5d90e957fb 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -42,13 +42,6 @@
 #define S3C2410_CLKCON_IIS           (1<<17)
 #define S3C2410_CLKCON_SPI           (1<<18)
 
-#define S3C2410_PLLCON_MDIVSHIFT     12
-#define S3C2410_PLLCON_PDIVSHIFT     4
-#define S3C2410_PLLCON_SDIVSHIFT     0
-#define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
-#define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
-#define S3C2410_PLLCON_SDIVMASK      3
-
 /* DCLKCON register addresses in gpio.h */
 
 #define S3C2410_DCLKCON_DCLK0EN      (1<<0)
@@ -76,32 +69,6 @@
 #define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
 #define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
 
-#ifndef __ASSEMBLY__
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C2410_PLLCON_MDIVMASK;
-        pdiv &= S3C2410_PLLCON_PDIVMASK;
-        sdiv &= S3C2410_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#endif /* __ASSEMBLY__ */
-
 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 
 /* extra registers */
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 32d550fcff4d..836508b829bb 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/pll.h>
 #include <plat/pm.h>
 
 static struct map_desc h1940_iodesc[] __initdata = {
@@ -223,10 +224,9 @@ static void __init h1940_init(void)
                               S3C2410_MISCCR_USBSUSPND0 |
                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 
-        tmp = (
-                 0x78 << S3C2410_PLLCON_MDIVSHIFT)
-              | (0x02 << S3C2410_PLLCON_PDIVSHIFT)
-              | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
+        tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
+              | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
+              | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
         writel(tmp, S3C2410_UPLLCON);
 
         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 1db39c609d78..4e23bc05f4b5 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -35,6 +35,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
+#include <plat/pll.h>
 
 /* Initial IO mappings */
 
@@ -74,7 +75,7 @@ void __init s3c2410_init_clocks(int xtal)
         /* now we've got our machine bits initialised, work out what
          * clocks we've got */
 
-        fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
+        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
 
         tmp = __raw_readl(S3C2410_CLKDIVN);
 
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 22d22a035782..4bd2b5fb8669 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -47,6 +47,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/pm.h>
+#include <plat/pll.h>
 
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -165,7 +166,7 @@ void __init s3c2412_init_clocks(int xtal)
         /* now we've got our machine bits initialised, work out what
          * clocks we've got */
 
-        fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
+        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
 
         clk_mpll.rate = fclk;
 
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index bf2633bd3996..1ff1b9836042 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -49,6 +49,7 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/pll.h>
 
 /* clock information */
 
@@ -332,7 +333,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
         /* initialise the main system clocks */
 
         clk_xtal.rate = xtal;
-        clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
+        clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
 
         clk_mpll.rate = fclk;
         clk_h.rate = hclk;
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
new file mode 100644
index 000000000000..7ea8bffa7a9c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -0,0 +1,37 @@
+/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - common pll registers and code
+ */
+
+#define S3C24XX_PLLCON_MDIVSHIFT        12
+#define S3C24XX_PLLCON_PDIVSHIFT        4
+#define S3C24XX_PLLCON_SDIVSHIFT        0
+#define S3C24XX_PLLCON_MDIVMASK         ((1<<(1+(19-12)))-1)
+#define S3C24XX_PLLCON_PDIVMASK         ((1<<5)-1)
+#define S3C24XX_PLLCON_SDIVMASK         3
+
+#include <asm/div64.h>
+
+static inline unsigned int
+s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
+        pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
+        sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
+
+        mdiv &= S3C24XX_PLLCON_MDIVMASK;
+        pdiv &= S3C24XX_PLLCON_PDIVMASK;
+        sdiv &= S3C24XX_PLLCON_SDIVMASK;
+
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+
+        return (unsigned int)fvco;
+}
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index d1152d1f9ba0..7f33cef20bac 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -42,6 +42,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/pll.h>
 
 static struct map_desc s3c244x_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
@@ -80,7 +81,7 @@ void __init s3c244x_init_clocks(int xtal)
         /* now we've got our machine bits initialised, work out what
          * clocks we've got */
 
-        fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
+        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
 
         clkdiv = __raw_readl(S3C2410_CLKDIVN);
         camdiv = __raw_readl(S3C2440_CAMDIVN);