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authorTony Lindgren <tony@atomide.com>2009-12-11 19:16:32 -0500
committerTony Lindgren <tony@atomide.com>2009-12-11 19:16:32 -0500
commitddaa912a2164d7ce7a03fcb384ed37e712bb4549 (patch)
tree332356ed70bd9db782f4865e0b162258c9ce1d68 /arch
parent15ac7afe515631ec36966b1cf632a87276536f57 (diff)
omap: mux: Add new style pin multiplexing data for 34xx
Add new style mux data for 34xx. This should also work with 3630 easily by adding the processor subset and ball data. Note that this data is __initdata, and gets optimized out except for the GPIO pins if CONFIG_OMAP_MUX is not set. Also note that this data uses omap3630 naming for the SDMMC registers instead of 34xx naming with just MMC. Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/Kconfig9
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/mux.h2
-rw-r--r--arch/arm/mach-omap2/mux34xx.c1579
-rw-r--r--arch/arm/mach-omap2/mux34xx.h356
5 files changed, 1949 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0cd25ceadb43..7da18f091932 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -24,6 +24,15 @@ config ARCH_OMAP3430
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX 24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG 25 select ARCH_OMAP_OTG
26 26
27config OMAP_PACKAGE_CBC
28 bool
29
30config OMAP_PACKAGE_CBB
31 bool
32
33config OMAP_PACKAGE_CUS
34 bool
35
27comment "OMAP Board Type" 36comment "OMAP Board Type"
28 depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4 37 depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
29 38
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 10c0539c4b01..6e348e528f8d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
26obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 26obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
27obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o 27obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
28 28
29# Pin multiplexing
30obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
31
29# SMS/SDRC 32# SMS/SDRC
30obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 33obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
31# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 34# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index bebe9cc60858..a6bd58f02f72 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,6 +7,8 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10#include "mux34xx.h"
11
10#define OMAP_MUX_TERMINATOR 0xffff 12#define OMAP_MUX_TERMINATOR 0xffff
11 13
12/* 34xx mux mode options for each pin. See TRM for options */ 14/* 34xx mux mode options for each pin. See TRM for options */
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
new file mode 100644
index 000000000000..116d5b22581a
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -0,0 +1,1579 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP3_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap3
42 */
43static struct omap_mux __initdata omap3_muxmodes[] = {
44 _OMAP3_MUXENTRY(CAM_D0, 99,
45 "cam_d0", NULL, NULL, NULL,
46 "gpio_99", NULL, NULL, "safe_mode"),
47 _OMAP3_MUXENTRY(CAM_D1, 100,
48 "cam_d1", NULL, NULL, NULL,
49 "gpio_100", NULL, NULL, "safe_mode"),
50 _OMAP3_MUXENTRY(CAM_D10, 109,
51 "cam_d10", NULL, NULL, NULL,
52 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
53 _OMAP3_MUXENTRY(CAM_D11, 110,
54 "cam_d11", NULL, NULL, NULL,
55 "gpio_110", "hw_dbg9", NULL, "safe_mode"),
56 _OMAP3_MUXENTRY(CAM_D2, 101,
57 "cam_d2", NULL, NULL, NULL,
58 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
59 _OMAP3_MUXENTRY(CAM_D3, 102,
60 "cam_d3", NULL, NULL, NULL,
61 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
62 _OMAP3_MUXENTRY(CAM_D4, 103,
63 "cam_d4", NULL, NULL, NULL,
64 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
65 _OMAP3_MUXENTRY(CAM_D5, 104,
66 "cam_d5", NULL, NULL, NULL,
67 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
68 _OMAP3_MUXENTRY(CAM_D6, 105,
69 "cam_d6", NULL, NULL, NULL,
70 "gpio_105", NULL, NULL, "safe_mode"),
71 _OMAP3_MUXENTRY(CAM_D7, 106,
72 "cam_d7", NULL, NULL, NULL,
73 "gpio_106", NULL, NULL, "safe_mode"),
74 _OMAP3_MUXENTRY(CAM_D8, 107,
75 "cam_d8", NULL, NULL, NULL,
76 "gpio_107", NULL, NULL, "safe_mode"),
77 _OMAP3_MUXENTRY(CAM_D9, 108,
78 "cam_d9", NULL, NULL, NULL,
79 "gpio_108", NULL, NULL, "safe_mode"),
80 _OMAP3_MUXENTRY(CAM_FLD, 98,
81 "cam_fld", NULL, "cam_global_reset", NULL,
82 "gpio_98", "hw_dbg3", NULL, "safe_mode"),
83 _OMAP3_MUXENTRY(CAM_HS, 94,
84 "cam_hs", NULL, NULL, NULL,
85 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
86 _OMAP3_MUXENTRY(CAM_PCLK, 97,
87 "cam_pclk", NULL, NULL, NULL,
88 "gpio_97", "hw_dbg2", NULL, "safe_mode"),
89 _OMAP3_MUXENTRY(CAM_STROBE, 126,
90 "cam_strobe", NULL, NULL, NULL,
91 "gpio_126", "hw_dbg11", NULL, "safe_mode"),
92 _OMAP3_MUXENTRY(CAM_VS, 95,
93 "cam_vs", NULL, NULL, NULL,
94 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
95 _OMAP3_MUXENTRY(CAM_WEN, 167,
96 "cam_wen", NULL, "cam_shutter", NULL,
97 "gpio_167", "hw_dbg10", NULL, "safe_mode"),
98 _OMAP3_MUXENTRY(CAM_XCLKA, 96,
99 "cam_xclka", NULL, NULL, NULL,
100 "gpio_96", NULL, NULL, "safe_mode"),
101 _OMAP3_MUXENTRY(CAM_XCLKB, 111,
102 "cam_xclkb", NULL, NULL, NULL,
103 "gpio_111", NULL, NULL, "safe_mode"),
104 _OMAP3_MUXENTRY(CSI2_DX0, 112,
105 "csi2_dx0", NULL, NULL, NULL,
106 "gpio_112", NULL, NULL, "safe_mode"),
107 _OMAP3_MUXENTRY(CSI2_DX1, 114,
108 "csi2_dx1", NULL, NULL, NULL,
109 "gpio_114", NULL, NULL, "safe_mode"),
110 _OMAP3_MUXENTRY(CSI2_DY0, 113,
111 "csi2_dy0", NULL, NULL, NULL,
112 "gpio_113", NULL, NULL, "safe_mode"),
113 _OMAP3_MUXENTRY(CSI2_DY1, 115,
114 "csi2_dy1", NULL, NULL, NULL,
115 "gpio_115", NULL, NULL, "safe_mode"),
116 _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
117 "dss_acbias", NULL, NULL, NULL,
118 "gpio_69", NULL, NULL, "safe_mode"),
119 _OMAP3_MUXENTRY(DSS_DATA0, 70,
120 "dss_data0", NULL, "uart1_cts", NULL,
121 "gpio_70", NULL, NULL, "safe_mode"),
122 _OMAP3_MUXENTRY(DSS_DATA1, 71,
123 "dss_data1", NULL, "uart1_rts", NULL,
124 "gpio_71", NULL, NULL, "safe_mode"),
125 _OMAP3_MUXENTRY(DSS_DATA10, 80,
126 "dss_data10", NULL, NULL, NULL,
127 "gpio_80", NULL, NULL, "safe_mode"),
128 _OMAP3_MUXENTRY(DSS_DATA11, 81,
129 "dss_data11", NULL, NULL, NULL,
130 "gpio_81", NULL, NULL, "safe_mode"),
131 _OMAP3_MUXENTRY(DSS_DATA12, 82,
132 "dss_data12", NULL, NULL, NULL,
133 "gpio_82", NULL, NULL, "safe_mode"),
134 _OMAP3_MUXENTRY(DSS_DATA13, 83,
135 "dss_data13", NULL, NULL, NULL,
136 "gpio_83", NULL, NULL, "safe_mode"),
137 _OMAP3_MUXENTRY(DSS_DATA14, 84,
138 "dss_data14", NULL, NULL, NULL,
139 "gpio_84", NULL, NULL, "safe_mode"),
140 _OMAP3_MUXENTRY(DSS_DATA15, 85,
141 "dss_data15", NULL, NULL, NULL,
142 "gpio_85", NULL, NULL, "safe_mode"),
143 _OMAP3_MUXENTRY(DSS_DATA16, 86,
144 "dss_data16", NULL, NULL, NULL,
145 "gpio_86", NULL, NULL, "safe_mode"),
146 _OMAP3_MUXENTRY(DSS_DATA17, 87,
147 "dss_data17", NULL, NULL, NULL,
148 "gpio_87", NULL, NULL, "safe_mode"),
149 _OMAP3_MUXENTRY(DSS_DATA18, 88,
150 "dss_data18", NULL, "mcspi3_clk", "dss_data0",
151 "gpio_88", NULL, NULL, "safe_mode"),
152 _OMAP3_MUXENTRY(DSS_DATA19, 89,
153 "dss_data19", NULL, "mcspi3_simo", "dss_data1",
154 "gpio_89", NULL, NULL, "safe_mode"),
155 _OMAP3_MUXENTRY(DSS_DATA20, 90,
156 "dss_data20", NULL, "mcspi3_somi", "dss_data2",
157 "gpio_90", NULL, NULL, "safe_mode"),
158 _OMAP3_MUXENTRY(DSS_DATA21, 91,
159 "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
160 "gpio_91", NULL, NULL, "safe_mode"),
161 _OMAP3_MUXENTRY(DSS_DATA22, 92,
162 "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
163 "gpio_92", NULL, NULL, "safe_mode"),
164 _OMAP3_MUXENTRY(DSS_DATA23, 93,
165 "dss_data23", NULL, NULL, "dss_data5",
166 "gpio_93", NULL, NULL, "safe_mode"),
167 _OMAP3_MUXENTRY(DSS_DATA2, 72,
168 "dss_data2", NULL, NULL, NULL,
169 "gpio_72", NULL, NULL, "safe_mode"),
170 _OMAP3_MUXENTRY(DSS_DATA3, 73,
171 "dss_data3", NULL, NULL, NULL,
172 "gpio_73", NULL, NULL, "safe_mode"),
173 _OMAP3_MUXENTRY(DSS_DATA4, 74,
174 "dss_data4", NULL, "uart3_rx_irrx", NULL,
175 "gpio_74", NULL, NULL, "safe_mode"),
176 _OMAP3_MUXENTRY(DSS_DATA5, 75,
177 "dss_data5", NULL, "uart3_tx_irtx", NULL,
178 "gpio_75", NULL, NULL, "safe_mode"),
179 _OMAP3_MUXENTRY(DSS_DATA6, 76,
180 "dss_data6", NULL, "uart1_tx", NULL,
181 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
182 _OMAP3_MUXENTRY(DSS_DATA7, 77,
183 "dss_data7", NULL, "uart1_rx", NULL,
184 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
185 _OMAP3_MUXENTRY(DSS_DATA8, 78,
186 "dss_data8", NULL, NULL, NULL,
187 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
188 _OMAP3_MUXENTRY(DSS_DATA9, 79,
189 "dss_data9", NULL, NULL, NULL,
190 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
191 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
192 "dss_hsync", NULL, NULL, NULL,
193 "gpio_67", "hw_dbg13", NULL, "safe_mode"),
194 _OMAP3_MUXENTRY(DSS_PCLK, 66,
195 "dss_pclk", NULL, NULL, NULL,
196 "gpio_66", "hw_dbg12", NULL, "safe_mode"),
197 _OMAP3_MUXENTRY(DSS_VSYNC, 68,
198 "dss_vsync", NULL, NULL, NULL,
199 "gpio_68", NULL, NULL, "safe_mode"),
200 _OMAP3_MUXENTRY(ETK_CLK, 12,
201 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
202 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
203 _OMAP3_MUXENTRY(ETK_CTL, 13,
204 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
205 "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
206 _OMAP3_MUXENTRY(ETK_D0, 14,
207 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
208 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
209 _OMAP3_MUXENTRY(ETK_D1, 15,
210 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
211 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
212 _OMAP3_MUXENTRY(ETK_D10, 24,
213 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
214 "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
215 _OMAP3_MUXENTRY(ETK_D11, 25,
216 "etk_d11", NULL, NULL, "hsusb2_stp",
217 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
218 _OMAP3_MUXENTRY(ETK_D12, 26,
219 "etk_d12", NULL, NULL, "hsusb2_dir",
220 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
221 _OMAP3_MUXENTRY(ETK_D13, 27,
222 "etk_d13", NULL, NULL, "hsusb2_nxt",
223 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
224 _OMAP3_MUXENTRY(ETK_D14, 28,
225 "etk_d14", NULL, NULL, "hsusb2_data0",
226 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
227 _OMAP3_MUXENTRY(ETK_D15, 29,
228 "etk_d15", NULL, NULL, "hsusb2_data1",
229 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
230 _OMAP3_MUXENTRY(ETK_D2, 16,
231 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
232 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
233 _OMAP3_MUXENTRY(ETK_D3, 17,
234 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
235 "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
236 _OMAP3_MUXENTRY(ETK_D4, 18,
237 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
238 "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
239 _OMAP3_MUXENTRY(ETK_D5, 19,
240 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
241 "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
242 _OMAP3_MUXENTRY(ETK_D6, 20,
243 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
244 "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
245 _OMAP3_MUXENTRY(ETK_D7, 21,
246 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
247 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
248 _OMAP3_MUXENTRY(ETK_D8, 22,
249 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
250 "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
251 _OMAP3_MUXENTRY(ETK_D9, 23,
252 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
253 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
254 _OMAP3_MUXENTRY(GPMC_A1, 34,
255 "gpmc_a1", NULL, NULL, NULL,
256 "gpio_34", NULL, NULL, "safe_mode"),
257 _OMAP3_MUXENTRY(GPMC_A10, 43,
258 "gpmc_a10", "sys_ndmareq3", NULL, NULL,
259 "gpio_43", NULL, NULL, "safe_mode"),
260 _OMAP3_MUXENTRY(GPMC_A2, 35,
261 "gpmc_a2", NULL, NULL, NULL,
262 "gpio_35", NULL, NULL, "safe_mode"),
263 _OMAP3_MUXENTRY(GPMC_A3, 36,
264 "gpmc_a3", NULL, NULL, NULL,
265 "gpio_36", NULL, NULL, "safe_mode"),
266 _OMAP3_MUXENTRY(GPMC_A4, 37,
267 "gpmc_a4", NULL, NULL, NULL,
268 "gpio_37", NULL, NULL, "safe_mode"),
269 _OMAP3_MUXENTRY(GPMC_A5, 38,
270 "gpmc_a5", NULL, NULL, NULL,
271 "gpio_38", NULL, NULL, "safe_mode"),
272 _OMAP3_MUXENTRY(GPMC_A6, 39,
273 "gpmc_a6", NULL, NULL, NULL,
274 "gpio_39", NULL, NULL, "safe_mode"),
275 _OMAP3_MUXENTRY(GPMC_A7, 40,
276 "gpmc_a7", NULL, NULL, NULL,
277 "gpio_40", NULL, NULL, "safe_mode"),
278 _OMAP3_MUXENTRY(GPMC_A8, 41,
279 "gpmc_a8", NULL, NULL, NULL,
280 "gpio_41", NULL, NULL, "safe_mode"),
281 _OMAP3_MUXENTRY(GPMC_A9, 42,
282 "gpmc_a9", "sys_ndmareq2", NULL, NULL,
283 "gpio_42", NULL, NULL, "safe_mode"),
284 _OMAP3_MUXENTRY(GPMC_CLK, 59,
285 "gpmc_clk", NULL, NULL, NULL,
286 "gpio_59", NULL, NULL, "safe_mode"),
287 _OMAP3_MUXENTRY(GPMC_D10, 46,
288 "gpmc_d10", NULL, NULL, NULL,
289 "gpio_46", NULL, NULL, "safe_mode"),
290 _OMAP3_MUXENTRY(GPMC_D11, 47,
291 "gpmc_d11", NULL, NULL, NULL,
292 "gpio_47", NULL, NULL, "safe_mode"),
293 _OMAP3_MUXENTRY(GPMC_D12, 48,
294 "gpmc_d12", NULL, NULL, NULL,
295 "gpio_48", NULL, NULL, "safe_mode"),
296 _OMAP3_MUXENTRY(GPMC_D13, 49,
297 "gpmc_d13", NULL, NULL, NULL,
298 "gpio_49", NULL, NULL, "safe_mode"),
299 _OMAP3_MUXENTRY(GPMC_D14, 50,
300 "gpmc_d14", NULL, NULL, NULL,
301 "gpio_50", NULL, NULL, "safe_mode"),
302 _OMAP3_MUXENTRY(GPMC_D15, 51,
303 "gpmc_d15", NULL, NULL, NULL,
304 "gpio_51", NULL, NULL, "safe_mode"),
305 _OMAP3_MUXENTRY(GPMC_D8, 44,
306 "gpmc_d8", NULL, NULL, NULL,
307 "gpio_44", NULL, NULL, "safe_mode"),
308 _OMAP3_MUXENTRY(GPMC_D9, 45,
309 "gpmc_d9", NULL, NULL, NULL,
310 "gpio_45", NULL, NULL, "safe_mode"),
311 _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
312 "gpmc_nbe0_cle", NULL, NULL, NULL,
313 "gpio_60", NULL, NULL, "safe_mode"),
314 _OMAP3_MUXENTRY(GPMC_NBE1, 61,
315 "gpmc_nbe1", NULL, NULL, NULL,
316 "gpio_61", NULL, NULL, "safe_mode"),
317 _OMAP3_MUXENTRY(GPMC_NCS1, 52,
318 "gpmc_ncs1", NULL, NULL, NULL,
319 "gpio_52", NULL, NULL, "safe_mode"),
320 _OMAP3_MUXENTRY(GPMC_NCS2, 53,
321 "gpmc_ncs2", NULL, NULL, NULL,
322 "gpio_53", NULL, NULL, "safe_mode"),
323 _OMAP3_MUXENTRY(GPMC_NCS3, 54,
324 "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
325 "gpio_54", NULL, NULL, "safe_mode"),
326 _OMAP3_MUXENTRY(GPMC_NCS4, 55,
327 "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
328 "gpio_55", NULL, NULL, "safe_mode"),
329 _OMAP3_MUXENTRY(GPMC_NCS5, 56,
330 "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
331 "gpio_56", NULL, NULL, "safe_mode"),
332 _OMAP3_MUXENTRY(GPMC_NCS6, 57,
333 "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
334 "gpio_57", NULL, NULL, "safe_mode"),
335 _OMAP3_MUXENTRY(GPMC_NCS7, 58,
336 "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
337 "gpio_58", NULL, NULL, "safe_mode"),
338 _OMAP3_MUXENTRY(GPMC_NWP, 62,
339 "gpmc_nwp", NULL, NULL, NULL,
340 "gpio_62", NULL, NULL, "safe_mode"),
341 _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
342 "gpmc_wait1", NULL, NULL, NULL,
343 "gpio_63", NULL, NULL, "safe_mode"),
344 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
345 "gpmc_wait2", NULL, NULL, NULL,
346 "gpio_64", NULL, NULL, "safe_mode"),
347 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
348 "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
349 "gpio_65", NULL, NULL, "safe_mode"),
350 _OMAP3_MUXENTRY(HDQ_SIO, 170,
351 "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
352 "gpio_170", NULL, NULL, "safe_mode"),
353 _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
354 "hsusb0_clk", NULL, NULL, NULL,
355 "gpio_120", NULL, NULL, "safe_mode"),
356 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
357 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
358 "gpio_125", NULL, NULL, "safe_mode"),
359 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
360 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
361 "gpio_130", NULL, NULL, "safe_mode"),
362 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
363 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
364 "gpio_131", NULL, NULL, "safe_mode"),
365 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
366 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
367 "gpio_169", NULL, NULL, "safe_mode"),
368 _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
369 "hsusb0_data4", NULL, NULL, NULL,
370 "gpio_188", NULL, NULL, "safe_mode"),
371 _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
372 "hsusb0_data5", NULL, NULL, NULL,
373 "gpio_189", NULL, NULL, "safe_mode"),
374 _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
375 "hsusb0_data6", NULL, NULL, NULL,
376 "gpio_190", NULL, NULL, "safe_mode"),
377 _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
378 "hsusb0_data7", NULL, NULL, NULL,
379 "gpio_191", NULL, NULL, "safe_mode"),
380 _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
381 "hsusb0_dir", NULL, NULL, NULL,
382 "gpio_122", NULL, NULL, "safe_mode"),
383 _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
384 "hsusb0_nxt", NULL, NULL, NULL,
385 "gpio_124", NULL, NULL, "safe_mode"),
386 _OMAP3_MUXENTRY(HSUSB0_STP, 121,
387 "hsusb0_stp", NULL, NULL, NULL,
388 "gpio_121", NULL, NULL, "safe_mode"),
389 _OMAP3_MUXENTRY(I2C2_SCL, 168,
390 "i2c2_scl", NULL, NULL, NULL,
391 "gpio_168", NULL, NULL, "safe_mode"),
392 _OMAP3_MUXENTRY(I2C2_SDA, 183,
393 "i2c2_sda", NULL, NULL, NULL,
394 "gpio_183", NULL, NULL, "safe_mode"),
395 _OMAP3_MUXENTRY(I2C3_SCL, 184,
396 "i2c3_scl", NULL, NULL, NULL,
397 "gpio_184", NULL, NULL, "safe_mode"),
398 _OMAP3_MUXENTRY(I2C3_SDA, 185,
399 "i2c3_sda", NULL, NULL, NULL,
400 "gpio_185", NULL, NULL, "safe_mode"),
401 _OMAP3_MUXENTRY(I2C4_SCL, 0,
402 "i2c4_scl", "sys_nvmode1", NULL, NULL,
403 NULL, NULL, NULL, "safe_mode"),
404 _OMAP3_MUXENTRY(I2C4_SDA, 0,
405 "i2c4_sda", "sys_nvmode2", NULL, NULL,
406 NULL, NULL, NULL, "safe_mode"),
407 _OMAP3_MUXENTRY(JTAG_EMU0, 11,
408 "jtag_emu0", NULL, NULL, NULL,
409 "gpio_11", NULL, NULL, "safe_mode"),
410 _OMAP3_MUXENTRY(JTAG_EMU1, 31,
411 "jtag_emu1", NULL, NULL, NULL,
412 "gpio_31", NULL, NULL, "safe_mode"),
413 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
414 "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
415 "gpio_156", NULL, NULL, "safe_mode"),
416 _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
417 "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
418 "gpio_162", NULL, NULL, "safe_mode"),
419 _OMAP3_MUXENTRY(MCBSP1_DR, 159,
420 "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
421 "gpio_159", NULL, NULL, "safe_mode"),
422 _OMAP3_MUXENTRY(MCBSP1_DX, 158,
423 "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
424 "gpio_158", NULL, NULL, "safe_mode"),
425 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
426 "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
427 "gpio_157", NULL, NULL, "safe_mode"),
428 _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
429 "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
430 "gpio_161", NULL, NULL, "safe_mode"),
431 _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
432 "mcbsp2_clkx", NULL, NULL, NULL,
433 "gpio_117", NULL, NULL, "safe_mode"),
434 _OMAP3_MUXENTRY(MCBSP2_DR, 118,
435 "mcbsp2_dr", NULL, NULL, NULL,
436 "gpio_118", NULL, NULL, "safe_mode"),
437 _OMAP3_MUXENTRY(MCBSP2_DX, 119,
438 "mcbsp2_dx", NULL, NULL, NULL,
439 "gpio_119", NULL, NULL, "safe_mode"),
440 _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
441 "mcbsp2_fsx", NULL, NULL, NULL,
442 "gpio_116", NULL, NULL, "safe_mode"),
443 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
444 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
445 "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
446 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
447 "mcbsp3_dr", "uart2_rts", NULL, NULL,
448 "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
449 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
450 "mcbsp3_dx", "uart2_cts", NULL, NULL,
451 "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
452 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
453 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
454 "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
455 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
456 "mcbsp4_clkx", NULL, NULL, NULL,
457 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
458 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
459 "mcbsp4_dr", NULL, NULL, NULL,
460 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
461 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
462 "mcbsp4_dx", NULL, NULL, NULL,
463 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
464 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
465 "mcbsp4_fsx", NULL, NULL, NULL,
466 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
467 _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
468 "mcbsp_clks", NULL, "cam_shutter", NULL,
469 "gpio_160", "uart1_cts", NULL, "safe_mode"),
470 _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
471 "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
472 "gpio_171", NULL, NULL, "safe_mode"),
473 _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
474 "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
475 "gpio_174", NULL, NULL, "safe_mode"),
476 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
477 "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
478 "gpio_175", NULL, NULL, "safe_mode"),
479 _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
480 "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
481 "gpio_176", NULL, NULL, "safe_mode"),
482 _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
483 "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
484 "gpio_177", "mm2_txdat", NULL, "safe_mode"),
485 _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
486 "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
487 "gpio_172", NULL, NULL, "safe_mode"),
488 _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
489 "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
490 "gpio_173", NULL, NULL, "safe_mode"),
491 _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
492 "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
493 "gpio_178", NULL, NULL, "safe_mode"),
494 _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
495 "mcspi2_cs0", "gpt11_pwm_evt",
496 "hsusb2_tll_data6", "hsusb2_data6",
497 "gpio_181", NULL, NULL, "safe_mode"),
498 _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
499 "mcspi2_cs1", "gpt8_pwm_evt",
500 "hsusb2_tll_data3", "hsusb2_data3",
501 "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
502 _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
503 "mcspi2_simo", "gpt9_pwm_evt",
504 "hsusb2_tll_data4", "hsusb2_data4",
505 "gpio_179", NULL, NULL, "safe_mode"),
506 _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
507 "mcspi2_somi", "gpt10_pwm_evt",
508 "hsusb2_tll_data5", "hsusb2_data5",
509 "gpio_180", NULL, NULL, "safe_mode"),
510 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
511 "sdmmc1_clk", NULL, NULL, NULL,
512 "gpio_120", NULL, NULL, "safe_mode"),
513 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
514 "sdmmc1_cmd", NULL, NULL, NULL,
515 "gpio_121", NULL, NULL, "safe_mode"),
516 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
517 "sdmmc1_dat0", NULL, NULL, NULL,
518 "gpio_122", NULL, NULL, "safe_mode"),
519 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
520 "sdmmc1_dat1", NULL, NULL, NULL,
521 "gpio_123", NULL, NULL, "safe_mode"),
522 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
523 "sdmmc1_dat2", NULL, NULL, NULL,
524 "gpio_124", NULL, NULL, "safe_mode"),
525 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
526 "sdmmc1_dat3", NULL, NULL, NULL,
527 "gpio_125", NULL, NULL, "safe_mode"),
528 _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
529 "sdmmc1_dat4", NULL, "sim_io", NULL,
530 "gpio_126", NULL, NULL, "safe_mode"),
531 _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
532 "sdmmc1_dat5", NULL, "sim_clk", NULL,
533 "gpio_127", NULL, NULL, "safe_mode"),
534 _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
535 "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
536 "gpio_128", NULL, NULL, "safe_mode"),
537 _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
538 "sdmmc1_dat7", NULL, "sim_rst", NULL,
539 "gpio_129", NULL, NULL, "safe_mode"),
540 _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
541 "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
542 "gpio_130", NULL, NULL, "safe_mode"),
543 _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
544 "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
545 "gpio_131", NULL, NULL, "safe_mode"),
546 _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
547 "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
548 "gpio_132", NULL, NULL, "safe_mode"),
549 _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
550 "sdmmc2_dat1", NULL, NULL, NULL,
551 "gpio_133", NULL, NULL, "safe_mode"),
552 _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
553 "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
554 "gpio_134", NULL, NULL, "safe_mode"),
555 _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
556 "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
557 "gpio_135", NULL, NULL, "safe_mode"),
558 _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
559 "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
560 "gpio_136", NULL, NULL, "safe_mode"),
561 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
562 "sdmmc2_dat5", "sdmmc2_dir_dat1",
563 "cam_global_reset", "sdmmc3_dat1",
564 "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
565 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
566 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
567 "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
568 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
569 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
570 "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
571 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
572 "sdrc_cke0", NULL, NULL, NULL,
573 NULL, NULL, NULL, "safe_mode"),
574 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
575 "sdrc_cke1", NULL, NULL, NULL,
576 NULL, NULL, NULL, "safe_mode"),
577 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
578 "sys_boot0", NULL, NULL, NULL,
579 "gpio_2", NULL, NULL, "safe_mode"),
580 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
581 "sys_boot1", NULL, NULL, NULL,
582 "gpio_3", NULL, NULL, "safe_mode"),
583 _OMAP3_MUXENTRY(SYS_BOOT2, 4,
584 "sys_boot2", NULL, NULL, NULL,
585 "gpio_4", NULL, NULL, "safe_mode"),
586 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
587 "sys_boot3", NULL, NULL, NULL,
588 "gpio_5", NULL, NULL, "safe_mode"),
589 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
590 "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
591 "gpio_6", NULL, NULL, "safe_mode"),
592 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
593 "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
594 "gpio_7", NULL, NULL, "safe_mode"),
595 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
596 "sys_boot6", NULL, NULL, NULL,
597 "gpio_8", NULL, NULL, "safe_mode"),
598 _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
599 "sys_clkout1", NULL, NULL, NULL,
600 "gpio_10", NULL, NULL, "safe_mode"),
601 _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
602 "sys_clkout2", NULL, NULL, NULL,
603 "gpio_186", NULL, NULL, "safe_mode"),
604 _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
605 "sys_clkreq", NULL, NULL, NULL,
606 "gpio_1", NULL, NULL, "safe_mode"),
607 _OMAP3_MUXENTRY(SYS_NIRQ, 0,
608 "sys_nirq", NULL, NULL, NULL,
609 "gpio_0", NULL, NULL, "safe_mode"),
610 _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
611 "sys_nreswarm", NULL, NULL, NULL,
612 "gpio_30", NULL, NULL, "safe_mode"),
613 _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
614 "sys_off_mode", NULL, NULL, NULL,
615 "gpio_9", NULL, NULL, "safe_mode"),
616 _OMAP3_MUXENTRY(UART1_CTS, 150,
617 "uart1_cts", NULL, NULL, NULL,
618 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
619 _OMAP3_MUXENTRY(UART1_RTS, 149,
620 "uart1_rts", NULL, NULL, NULL,
621 "gpio_149", NULL, NULL, "safe_mode"),
622 _OMAP3_MUXENTRY(UART1_RX, 151,
623 "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
624 "gpio_151", NULL, NULL, "safe_mode"),
625 _OMAP3_MUXENTRY(UART1_TX, 148,
626 "uart1_tx", NULL, NULL, NULL,
627 "gpio_148", NULL, NULL, "safe_mode"),
628 _OMAP3_MUXENTRY(UART2_CTS, 144,
629 "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
630 "gpio_144", NULL, NULL, "safe_mode"),
631 _OMAP3_MUXENTRY(UART2_RTS, 145,
632 "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
633 "gpio_145", NULL, NULL, "safe_mode"),
634 _OMAP3_MUXENTRY(UART2_RX, 147,
635 "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
636 "gpio_147", NULL, NULL, "safe_mode"),
637 _OMAP3_MUXENTRY(UART2_TX, 146,
638 "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
639 "gpio_146", NULL, NULL, "safe_mode"),
640 _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
641 "uart3_cts_rctx", NULL, NULL, NULL,
642 "gpio_163", NULL, NULL, "safe_mode"),
643 _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
644 "uart3_rts_sd", NULL, NULL, NULL,
645 "gpio_164", NULL, NULL, "safe_mode"),
646 _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
647 "uart3_rx_irrx", NULL, NULL, NULL,
648 "gpio_165", NULL, NULL, "safe_mode"),
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"),
652 { .reg_offset = OMAP_MUX_TERMINATOR },
653};
654
655/*
656 * Signals different on CBC package compared to the superset
657 */
658#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
659struct omap_mux __initdata omap3_cbc_subset[] = {
660 { .reg_offset = OMAP_MUX_TERMINATOR },
661};
662#else
663#define omap3_cbc_subset NULL
664#endif
665
666/*
667 * Balls for CBC package
668 * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
669 *
670 * FIXME: What's up with the outdated TI documentation? See:
671 *
672 * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
673 * http://community.ti.com/forums/t/10982.aspx
674 */
675#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
676 && defined(CONFIG_OMAP_PACKAGE_CBC)
677struct omap_ball __initdata omap3_cbc_ball[] = {
678 _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
679 _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
680 _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
681 _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
682 _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
683 _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
684 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
685 _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
686 _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
687 _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
688 _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
689 _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
690 _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
691 _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
692 _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
693 _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
694 _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
695 _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
696 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
697 _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
698 _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
699 _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
700 _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
701 _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
702 _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
703 _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
704 _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
705 _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
706 _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
707 _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
708 _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
709 _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
710 _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
711 _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
712 _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
713 _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
714 _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
715 _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
716 _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
717 _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
718 _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
719 _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
720 _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
721 _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
722 _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
723 _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
724 _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
725 _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
726 _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
727 _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
728 _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
729 _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
730 _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
731 _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
732 _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
733 _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
734 _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
735 _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
736 _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
737 _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
738 _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
739 _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
740 _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
741 _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
742 _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
743 _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
744 _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
745 _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
746 _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
747 _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
748 _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
749 _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
750 _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
751 _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
752 _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
753 _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
754 _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
755 _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
756 _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
757 _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
758 _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
759 _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
760 _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
761 _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
762 _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
763 _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
764 _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
765 _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
766 _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
767 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
768 _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
769 _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
770 _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
771 _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
772 _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
773 _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
774 _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
775 _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
776 _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
777 _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
778 _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
779 _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
780 _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
781 _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
782 _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
783 _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
784 _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
785 _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
786 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
787 _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
788 _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
789 _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
790 _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
791 _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
792 _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
793 _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
794 _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
795 _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
796 _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
797 _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
798 _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
799 _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
800 _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
801 _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
802 _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
803 _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
804 _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
805 _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
806 _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
807 _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
808 _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
809 _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
810 _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
811 _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
812 _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
813 _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
814 _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
815 _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
816 _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
817 _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
818 _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
819 _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
820 _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
821 _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
822 _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
823 _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
824 _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
825 _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
826 _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
827 _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
828 _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
829 _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
830 _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
831 _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
832 _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
833 _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
834 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
835 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
836 _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
837 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
838 _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
839 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
840 _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
841 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
842 _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
843 _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
844 _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
845 _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
846 _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
847 _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
848 _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
849 _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
850 _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
851 _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
852 _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
853 _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
854 _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
855 _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
856 _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
857 _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
858 _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
859 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
860 _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
861 _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
862 _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
863 _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
864 _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
865 _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
866 _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
867 _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
868 _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
869 _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
870 _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
871 _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
872 _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
873 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
874 _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
875 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
876 _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
877 { .reg_offset = OMAP_MUX_TERMINATOR },
878};
879#else
880#define omap3_cbc_ball NULL
881#endif
882
883/*
884 * Signals different on CUS package compared to superset
885 */
886#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
887struct omap_mux __initdata omap3_cus_subset[] = {
888 _OMAP3_MUXENTRY(CAM_D10, 109,
889 "cam_d10", NULL, NULL, NULL,
890 "gpio_109", NULL, NULL, "safe_mode"),
891 _OMAP3_MUXENTRY(CAM_D11, 110,
892 "cam_d11", NULL, NULL, NULL,
893 "gpio_110", NULL, NULL, "safe_mode"),
894 _OMAP3_MUXENTRY(CAM_D2, 101,
895 "cam_d2", NULL, NULL, NULL,
896 "gpio_101", NULL, NULL, "safe_mode"),
897 _OMAP3_MUXENTRY(CAM_D3, 102,
898 "cam_d3", NULL, NULL, NULL,
899 "gpio_102", NULL, NULL, "safe_mode"),
900 _OMAP3_MUXENTRY(CAM_D4, 103,
901 "cam_d4", NULL, NULL, NULL,
902 "gpio_103", NULL, NULL, "safe_mode"),
903 _OMAP3_MUXENTRY(CAM_D5, 104,
904 "cam_d5", NULL, NULL, NULL,
905 "gpio_104", NULL, NULL, "safe_mode"),
906 _OMAP3_MUXENTRY(CAM_FLD, 98,
907 "cam_fld", NULL, "cam_global_reset", NULL,
908 "gpio_98", NULL, NULL, "safe_mode"),
909 _OMAP3_MUXENTRY(CAM_HS, 94,
910 "cam_hs", NULL, NULL, NULL,
911 "gpio_94", NULL, NULL, "safe_mode"),
912 _OMAP3_MUXENTRY(CAM_PCLK, 97,
913 "cam_pclk", NULL, NULL, NULL,
914 "gpio_97", NULL, NULL, "safe_mode"),
915 _OMAP3_MUXENTRY(CAM_STROBE, 126,
916 "cam_strobe", NULL, NULL, NULL,
917 "gpio_126", NULL, NULL, "safe_mode"),
918 _OMAP3_MUXENTRY(CAM_VS, 95,
919 "cam_vs", NULL, NULL, NULL,
920 "gpio_95", NULL, NULL, "safe_mode"),
921 _OMAP3_MUXENTRY(CAM_WEN, 167,
922 "cam_wen", NULL, "cam_shutter", NULL,
923 "gpio_167", NULL, NULL, "safe_mode"),
924 _OMAP3_MUXENTRY(DSS_DATA6, 76,
925 "dss_data6", NULL, "uart1_tx", NULL,
926 "gpio_76", NULL, NULL, "safe_mode"),
927 _OMAP3_MUXENTRY(DSS_DATA7, 77,
928 "dss_data7", NULL, "uart1_rx", NULL,
929 "gpio_77", NULL, NULL, "safe_mode"),
930 _OMAP3_MUXENTRY(DSS_DATA8, 78,
931 "dss_data8", NULL, NULL, NULL,
932 "gpio_78", NULL, NULL, "safe_mode"),
933 _OMAP3_MUXENTRY(DSS_DATA9, 79,
934 "dss_data9", NULL, NULL, NULL,
935 "gpio_79", NULL, NULL, "safe_mode"),
936 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
937 "dss_hsync", NULL, NULL, NULL,
938 "gpio_67", NULL, NULL, "safe_mode"),
939 _OMAP3_MUXENTRY(DSS_PCLK, 66,
940 "dss_pclk", NULL, NULL, NULL,
941 "gpio_66", NULL, NULL, "safe_mode"),
942 _OMAP3_MUXENTRY(ETK_CLK, 12,
943 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
944 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
945 _OMAP3_MUXENTRY(ETK_CTL, 13,
946 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
947 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
948 _OMAP3_MUXENTRY(ETK_D0, 14,
949 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
950 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
951 _OMAP3_MUXENTRY(ETK_D1, 15,
952 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
953 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
954 _OMAP3_MUXENTRY(ETK_D10, 24,
955 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
956 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
957 _OMAP3_MUXENTRY(ETK_D11, 25,
958 "etk_d11", NULL, NULL, "hsusb2_stp",
959 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
960 _OMAP3_MUXENTRY(ETK_D12, 26,
961 "etk_d12", NULL, NULL, "hsusb2_dir",
962 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
963 _OMAP3_MUXENTRY(ETK_D13, 27,
964 "etk_d13", NULL, NULL, "hsusb2_nxt",
965 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
966 _OMAP3_MUXENTRY(ETK_D14, 28,
967 "etk_d14", NULL, NULL, "hsusb2_data0",
968 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
969 _OMAP3_MUXENTRY(ETK_D15, 29,
970 "etk_d15", NULL, NULL, "hsusb2_data1",
971 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
972 _OMAP3_MUXENTRY(ETK_D2, 16,
973 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
974 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
975 _OMAP3_MUXENTRY(ETK_D3, 17,
976 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
977 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
978 _OMAP3_MUXENTRY(ETK_D4, 18,
979 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
980 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
981 _OMAP3_MUXENTRY(ETK_D5, 19,
982 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
983 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
984 _OMAP3_MUXENTRY(ETK_D6, 20,
985 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
986 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
987 _OMAP3_MUXENTRY(ETK_D7, 21,
988 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
989 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
990 _OMAP3_MUXENTRY(ETK_D8, 22,
991 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
992 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
993 _OMAP3_MUXENTRY(ETK_D9, 23,
994 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
995 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
996 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
997 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
998 "gpio_142", NULL, NULL, "safe_mode"),
999 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
1000 "mcbsp3_dr", "uart2_rts", NULL, NULL,
1001 "gpio_141", NULL, NULL, "safe_mode"),
1002 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
1003 "mcbsp3_dx", "uart2_cts", NULL, NULL,
1004 "gpio_140", NULL, NULL, "safe_mode"),
1005 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
1006 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
1007 "gpio_143", NULL, NULL, "safe_mode"),
1008 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
1009 "sdmmc2_dat5", "sdmmc2_dir_dat1",
1010 "cam_global_reset", "sdmmc3_dat1",
1011 "gpio_137", NULL, NULL, "safe_mode"),
1012 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
1013 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
1014 "gpio_138", NULL, NULL, "safe_mode"),
1015 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
1016 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
1017 "gpio_139", NULL, NULL, "safe_mode"),
1018 _OMAP3_MUXENTRY(UART1_CTS, 150,
1019 "uart1_cts", NULL, NULL, NULL,
1020 "gpio_150", NULL, NULL, "safe_mode"),
1021 { .reg_offset = OMAP_MUX_TERMINATOR },
1022};
1023#else
1024#define omap3_cus_subset NULL
1025#endif
1026
1027/*
1028 * Balls for CUS package
1029 * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
1030 */
1031#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1032 && defined(CONFIG_OMAP_PACKAGE_CUS)
1033struct omap_ball __initdata omap3_cus_ball[] = {
1034 _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
1035 _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
1036 _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
1037 _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
1038 _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
1039 _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
1040 _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
1041 _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
1042 _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
1043 _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
1044 _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
1045 _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
1046 _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
1047 _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
1048 _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
1049 _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
1050 _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
1051 _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
1052 _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
1053 _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
1054 _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
1055 _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
1056 _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
1057 _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
1058 _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
1059 _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
1060 _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
1061 _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
1062 _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
1063 _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
1064 _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
1065 _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
1066 _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
1067 _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
1068 _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
1069 _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
1070 _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
1071 _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
1072 _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
1073 _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
1074 _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
1075 _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
1076 _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
1077 _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
1078 _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
1079 _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
1080 _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
1081 _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
1082 _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
1083 _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
1084 _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
1085 _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
1086 _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
1087 _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
1088 _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
1089 _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
1090 _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
1091 _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
1092 _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
1093 _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
1094 _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
1095 _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
1096 _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
1097 _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
1098 _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
1099 _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
1100 _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
1101 _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
1102 _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
1103 _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
1104 _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
1105 _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
1106 _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
1107 _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
1108 _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
1109 _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
1110 _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
1111 _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
1112 _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
1113 _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
1114 _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
1115 _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
1116 _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
1117 _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
1118 _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
1119 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
1120 _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
1121 _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
1122 _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
1123 _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
1124 _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
1125 _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
1126 _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
1127 _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
1128 _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
1129 _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
1130 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
1131 _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
1132 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
1133 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
1134 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
1135 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
1136 _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
1137 _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
1138 _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
1139 _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
1140 _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
1141 _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
1142 _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
1143 _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
1144 _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
1145 _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
1146 _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
1147 _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
1148 _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
1149 _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
1150 _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
1151 _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
1152 _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
1153 _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
1154 _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
1155 _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
1156 _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
1157 _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
1158 _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
1159 _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
1160 _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
1161 _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
1162 _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
1163 _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
1164 _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
1165 _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
1166 _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
1167 _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
1168 _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
1169 _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
1170 _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
1171 _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
1172 _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
1173 _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
1174 _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
1175 _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
1176 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
1177 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
1178 _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
1179 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
1180 _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
1181 _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
1182 _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
1183 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
1184 _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
1185 _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
1186 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
1187 _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
1188 _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
1189 _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
1190 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
1191 _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
1192 _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
1193 _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
1194 _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
1195 _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
1196 _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
1197 _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
1198 _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
1199 _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
1200 _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
1201 _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
1202 _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
1203 _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
1204 _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
1205 _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
1206 _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
1207 _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
1208 _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
1209 _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
1210 _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
1211 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
1212 _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
1213 _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
1214 _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
1215 { .reg_offset = OMAP_MUX_TERMINATOR },
1216};
1217#else
1218#define omap3_cus_ball NULL
1219#endif
1220
1221/*
1222 * Signals different on CBB package comapared to superset
1223 */
1224#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
1225struct omap_mux __initdata omap3_cbb_subset[] = {
1226 _OMAP3_MUXENTRY(CAM_D10, 109,
1227 "cam_d10", NULL, NULL, NULL,
1228 "gpio_109", NULL, NULL, "safe_mode"),
1229 _OMAP3_MUXENTRY(CAM_D11, 110,
1230 "cam_d11", NULL, NULL, NULL,
1231 "gpio_110", NULL, NULL, "safe_mode"),
1232 _OMAP3_MUXENTRY(CAM_D2, 101,
1233 "cam_d2", NULL, NULL, NULL,
1234 "gpio_101", NULL, NULL, "safe_mode"),
1235 _OMAP3_MUXENTRY(CAM_D3, 102,
1236 "cam_d3", NULL, NULL, NULL,
1237 "gpio_102", NULL, NULL, "safe_mode"),
1238 _OMAP3_MUXENTRY(CAM_D4, 103,
1239 "cam_d4", NULL, NULL, NULL,
1240 "gpio_103", NULL, NULL, "safe_mode"),
1241 _OMAP3_MUXENTRY(CAM_D5, 104,
1242 "cam_d5", NULL, NULL, NULL,
1243 "gpio_104", NULL, NULL, "safe_mode"),
1244 _OMAP3_MUXENTRY(CAM_FLD, 98,
1245 "cam_fld", NULL, "cam_global_reset", NULL,
1246 "gpio_98", NULL, NULL, "safe_mode"),
1247 _OMAP3_MUXENTRY(CAM_HS, 94,
1248 "cam_hs", NULL, NULL, NULL,
1249 "gpio_94", NULL, NULL, "safe_mode"),
1250 _OMAP3_MUXENTRY(CAM_PCLK, 97,
1251 "cam_pclk", NULL, NULL, NULL,
1252 "gpio_97", NULL, NULL, "safe_mode"),
1253 _OMAP3_MUXENTRY(CAM_STROBE, 126,
1254 "cam_strobe", NULL, NULL, NULL,
1255 "gpio_126", NULL, NULL, "safe_mode"),
1256 _OMAP3_MUXENTRY(CAM_VS, 95,
1257 "cam_vs", NULL, NULL, NULL,
1258 "gpio_95", NULL, NULL, "safe_mode"),
1259 _OMAP3_MUXENTRY(CAM_WEN, 167,
1260 "cam_wen", NULL, "cam_shutter", NULL,
1261 "gpio_167", NULL, NULL, "safe_mode"),
1262 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1263 "dss_data6", NULL, "uart1_tx", NULL,
1264 "gpio_76", NULL, NULL, "safe_mode"),
1265 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1266 "dss_data7", NULL, "uart1_rx", NULL,
1267 "gpio_77", NULL, NULL, "safe_mode"),
1268 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1269 "dss_data8", NULL, NULL, NULL,
1270 "gpio_78", NULL, NULL, "safe_mode"),
1271 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1272 "dss_data9", NULL, NULL, NULL,
1273 "gpio_79", NULL, NULL, "safe_mode"),
1274 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
1275 "dss_hsync", NULL, NULL, NULL,
1276 "gpio_67", NULL, NULL, "safe_mode"),
1277 _OMAP3_MUXENTRY(DSS_PCLK, 66,
1278 "dss_pclk", NULL, NULL, NULL,
1279 "gpio_66", NULL, NULL, "safe_mode"),
1280 _OMAP3_MUXENTRY(ETK_CLK, 12,
1281 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
1282 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
1283 _OMAP3_MUXENTRY(ETK_CTL, 13,
1284 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
1285 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
1286 _OMAP3_MUXENTRY(ETK_D0, 14,
1287 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
1288 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
1289 _OMAP3_MUXENTRY(ETK_D1, 15,
1290 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1291 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1292 _OMAP3_MUXENTRY(ETK_D10, 24,
1293 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1294 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1295 _OMAP3_MUXENTRY(ETK_D11, 25,
1296 "etk_d11", NULL, NULL, "hsusb2_stp",
1297 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1298 _OMAP3_MUXENTRY(ETK_D12, 26,
1299 "etk_d12", NULL, NULL, "hsusb2_dir",
1300 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1301 _OMAP3_MUXENTRY(ETK_D13, 27,
1302 "etk_d13", NULL, NULL, "hsusb2_nxt",
1303 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1304 _OMAP3_MUXENTRY(ETK_D14, 28,
1305 "etk_d14", NULL, NULL, "hsusb2_data0",
1306 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1307 _OMAP3_MUXENTRY(ETK_D15, 29,
1308 "etk_d15", NULL, NULL, "hsusb2_data1",
1309 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1310 _OMAP3_MUXENTRY(ETK_D2, 16,
1311 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1312 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1313 _OMAP3_MUXENTRY(ETK_D3, 17,
1314 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1315 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1316 _OMAP3_MUXENTRY(ETK_D4, 18,
1317 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1318 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1319 _OMAP3_MUXENTRY(ETK_D5, 19,
1320 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1321 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1322 _OMAP3_MUXENTRY(ETK_D6, 20,
1323 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1324 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1325 _OMAP3_MUXENTRY(ETK_D7, 21,
1326 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1327 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1328 _OMAP3_MUXENTRY(ETK_D8, 22,
1329 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1330 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1331 _OMAP3_MUXENTRY(ETK_D9, 23,
1332 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1333 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1334 { .reg_offset = OMAP_MUX_TERMINATOR },
1335};
1336#else
1337#define omap3_cbb_subset NULL
1338#endif
1339
1340/*
1341 * Balls for CBB package
1342 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1343 */
1344#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1345 && defined(CONFIG_OMAP_PACKAGE_CBB)
1346struct omap_ball __initdata omap3_cbb_ball[] = {
1347 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1348 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1349 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1350 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1351 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1352 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1353 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1354 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1355 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1356 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1357 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1358 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1359 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1360 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1361 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1362 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1363 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1364 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1365 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1366 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1367 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1368 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1369 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1370 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1371 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1372 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1373 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1374 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1375 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1376 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1377 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1378 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1379 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1380 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1381 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1382 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1383 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1384 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1385 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1386 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1387 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1388 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1389 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1390 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1391 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1392 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1393 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1394 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1395 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1396 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1397 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1398 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1399 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1400 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1401 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1402 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1403 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1404 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1405 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1406 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1407 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1408 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1409 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1410 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1411 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1412 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1413 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1414 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1415 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1416 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1417 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1418 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1419 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1420 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1421 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1422 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1423 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1424 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1425 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1426 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1427 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1428 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1429 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1430 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1431 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1432 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1433 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1434 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1435 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1436 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1437 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1438 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1439 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1440 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1441 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1442 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1443 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1444 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1445 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1446 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1447 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1448 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1449 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1450 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1451 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1452 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1453 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1454 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1455 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1456 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1457 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1458 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1459 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1460 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1461 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1462 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1463 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1464 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1465 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1466 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1467 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1468 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1469 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1470 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1471 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1472 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1473 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1474 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1475 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1476 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1477 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1478 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1479 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1480 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1481 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1482 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1483 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1484 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1485 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1486 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1487 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1488 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1489 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1490 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1491 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1492 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1493 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1494 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1495 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1496 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1497 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1498 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1499 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1500 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1501 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1502 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1503 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1504 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1505 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1506 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1507 _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
1508 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
1509 _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
1510 _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
1511 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1512 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1513 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1514 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1515 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1516 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1517 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1518 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1519 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1520 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1521 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1522 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
1523 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
1524 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
1525 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
1526 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
1527 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
1528 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
1529 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
1530 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
1531 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
1532 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
1533 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
1534 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
1535 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
1536 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
1537 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
1538 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
1539 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
1540 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
1541 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
1542 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
1543 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
1544 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
1545 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
1546 { .reg_offset = OMAP_MUX_TERMINATOR },
1547};
1548#else
1549#define omap3_cbb_ball NULL
1550#endif
1551
1552int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
1553{
1554 struct omap_mux *package_subset;
1555 struct omap_ball *package_balls;
1556
1557 switch (flags & OMAP_PACKAGE_MASK) {
1558 case (OMAP_PACKAGE_CBC):
1559 package_subset = omap3_cbc_subset;
1560 package_balls = omap3_cbc_ball;
1561 break;
1562 case (OMAP_PACKAGE_CBB):
1563 package_subset = omap3_cbb_subset;
1564 package_balls = omap3_cbb_ball;
1565 break;
1566 case (OMAP_PACKAGE_CUS):
1567 package_subset = omap3_cus_subset;
1568 package_balls = omap3_cus_ball;
1569 break;
1570 default:
1571 printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
1572 return -EINVAL;
1573 }
1574
1575 return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
1576 OMAP3_CONTROL_PADCONF_MUX_SIZE,
1577 omap3_muxmodes, package_subset, board_subset,
1578 package_balls);
1579}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
new file mode 100644
index 000000000000..a7cc8713bd3f
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.h
@@ -0,0 +1,356 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
11
12#define OMAP3_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 16-bits wide.
24 *
25 * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
26 * of CHASSIS for some registers. For the defines, we follow the
27 * 36XX naming, and use SDMMC and CHASSIS.
28 */
29#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
30#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
31#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
32#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
33#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
34#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
35#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
36#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
37#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
38#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
39#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
40#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
41#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
42#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
43#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
44#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
45#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
46#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
47#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
48#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
49#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
50#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
51#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
52#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
53#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
54#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
55#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
56#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
57#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
58#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
59#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
60#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
61#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
62#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
63#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
64#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
65#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
66#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
67#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
68#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
69#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
70#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
71#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
72#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
73#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
74#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
75#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
76#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
77#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
78#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
79#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
80#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
81#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
82#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
83#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
84#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
85#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
86#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
87#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
88#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
89#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
90#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
91#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
92#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
93#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
94#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
95#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
96#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
97#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
98#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
99#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
100#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
101#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
102#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
103#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
104#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
105#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
106#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
107#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
108#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
109#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
110#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
111#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
112#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
113#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
114#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
115#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
116#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
117#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
118#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
119#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
120#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
121#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
122#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
123#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
124#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
125#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
126#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
127#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
128#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
129#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
130#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
131#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
132#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
133#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
134#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
135#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
136#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
137#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
138#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
139#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
140#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
141#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
142#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
143#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
144#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
145#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
146#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
147#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
148#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
149#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
150#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
151#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
152#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
153#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
154#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
155#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
156#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
157#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
158#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
159#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
160#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
161#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
162#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
163#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
164#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
165#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
166#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
167#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
168#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
169#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
170#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
171#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
172#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
173#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
174#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
175#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
176#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
177#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
178#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
179#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
180#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
181#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
182#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
183#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
184#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
185#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
186#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
187#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
188#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
189#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
190#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
191#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
192#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
193#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
194#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
195#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
196#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
197#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
198#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
199#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
200#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
201#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
202#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
203#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
204#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
205#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
206#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
207#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
208#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
209#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
210#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
211#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
212#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
213#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
214#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
215#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
216#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
217#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
218#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
219#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
220#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
221#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
222#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
223#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
224#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
225#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
226#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
227#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
228#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
229#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
230#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
231#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
232#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
233#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
234#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
235#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
236#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
237#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
238#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
239#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
240#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
241#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
242#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
243#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
244#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
245#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
246#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
247#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
248#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
249#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
250#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
251#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
252#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
253#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
254#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
255#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
256#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
257#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
258#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
259#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
260#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
261#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
262#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
263#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
264#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
265#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
266#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
267#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
268#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
269#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
270#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
271#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
272#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
273#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
274#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
275#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
276#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
277#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
278#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
279#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
280#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
281#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
282#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
283#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
284/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
285#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
286#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
287#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
288#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
289#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
290#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
291#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
292#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
293#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
294#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
295#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
296#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
297#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
298#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
299#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
300#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
301#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
302#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
303#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
304#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
305#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
306#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
307#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
308#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
309#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
310#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
311#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
312#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
313#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
314#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
315#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
316#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
317#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
318#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
319#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
320#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
321#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
322#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
323#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
324#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
325#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
326#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
327#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
328#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
329#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
330#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
331#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
332#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
333#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
334#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
335#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
336#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
337#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
338#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
339#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
340#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
341#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
342#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
343#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
344#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
345#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
346#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
347#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
348#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
349#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
350#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
351#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
352#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
353#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
354
355#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
356 (OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 02:44:59 -0500