Merge branch 'timers/clockevents-next' of git://git.linaro.org/people/dlezcano/clockevents into timers/core

* Support for memory mapped arch_timers
* Trivial fixes to the moxart timer code
* Documentation updates

Trivial conflicts in drivers/clocksource/arm_arch_timer.c. Fixed up
the newly added __cpuinit annotations as well.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

2 files changed, 15 insertions, 22 deletions

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index e406d575c94f..5665134bfa3e 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -17,7 +17,8 @@ int arch_timer_arch_init(void);
  * nicely work out which register we want, and chuck away the rest of
  * the code. At least it does so with a recent GCC (4.6.3).
  */
-static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
+static __always_inline
+void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
 {
         if (access == ARCH_TIMER_PHYS_ACCESS) {
                 switch (reg) {
@@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
                         asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
                         break;
                 }
-        }
-
-        if (access == ARCH_TIMER_VIRT_ACCESS) {
+        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                 switch (reg) {
                 case ARCH_TIMER_REG_CTRL:
                         asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
@@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
         isb();
 }
 
-static inline u32 arch_timer_reg_read(const int access, const int reg)
+static __always_inline
+u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 {
         u32 val = 0;
 
@@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
                         asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
                         break;
                 }
-        }
-
-        if (access == ARCH_TIMER_VIRT_ACCESS) {
+        } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                 switch (reg) {
                 case ARCH_TIMER_REG_CTRL:
                         asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index 98abd476992d..c9f1d2816c2b 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -26,7 +26,13 @@
 
 #include <clocksource/arm_arch_timer.h>
 
-static inline void arch_timer_reg_write(int access, int reg, u32 val)
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code.
+ */
+static __always_inline
+void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
 {
         if (access == ARCH_TIMER_PHYS_ACCESS) {
                 switch (reg) {
@@ -36,8 +42,6 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val)
                 case ARCH_TIMER_REG_TVAL:
                         asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
                         break;
-                default:
-                        BUILD_BUG();
                 }
         } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                 switch (reg) {
@@ -47,17 +51,14 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val)
                 case ARCH_TIMER_REG_TVAL:
                         asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
                         break;
-                default:
-                        BUILD_BUG();
                 }
-        } else {
-                BUILD_BUG();
         }
 
         isb();
 }
 
-static inline u32 arch_timer_reg_read(int access, int reg)
+static __always_inline
+u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 {
         u32 val;
 
@@ -69,8 +70,6 @@ static inline u32 arch_timer_reg_read(int access, int reg)
                 case ARCH_TIMER_REG_TVAL:
                         asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
                         break;
-                default:
-                        BUILD_BUG();
                 }
         } else if (access == ARCH_TIMER_VIRT_ACCESS) {
                 switch (reg) {
@@ -80,11 +79,7 @@ static inline u32 arch_timer_reg_read(int access, int reg)
                 case ARCH_TIMER_REG_TVAL:
                         asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
                         break;
-                default:
-                        BUILD_BUG();
                 }
-        } else {
-                BUILD_BUG();
         }
 
         return val;