diff options
author | Jason Liu <jason.hui@linaro.org> | 2011-08-26 01:35:23 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-08-26 02:51:00 -0400 |
commit | c52c983551ba3fb991f91eff4d924a375b0f9b83 (patch) | |
tree | 514eae16cd8bbaf5916aa62781e2f025ec8f57e5 /arch | |
parent | 8d75a2620dc3e33ce504044c375c443ed7ed4128 (diff) |
ARM: mx5: use generic function for displaying silicon revision
Update to use generic function for displaying silicon revision
Tested on my mx53 loco board:
CPU identified as i.MX53, silicon rev 2.0
Test on my mx51 babbage board:
CPU identified as i.MX51, silicon rev 3.0
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-mx5/cpu.c | 74 |
2 files changed, 19 insertions, 61 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996f463b..0e23e1d2af9c 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -1548,9 +1548,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
1548 | clk_enable(&main_bus_clk); | 1548 | clk_enable(&main_bus_clk); |
1549 | 1549 | ||
1550 | clk_enable(&iim_clk); | 1550 | clk_enable(&iim_clk); |
1551 | mx51_revision(); | 1551 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
1552 | clk_disable(&iim_clk); | 1552 | clk_disable(&iim_clk); |
1553 | mx51_display_revision(); | ||
1554 | 1553 | ||
1555 | /* move usb_phy_clk to 24MHz */ | 1554 | /* move usb_phy_clk to 24MHz */ |
1556 | clk_set_parent(&usb_phy1_clk, &osc_clk); | 1555 | clk_set_parent(&usb_phy1_clk, &osc_clk); |
@@ -1592,9 +1591,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, | |||
1592 | clk_enable(&main_bus_clk); | 1591 | clk_enable(&main_bus_clk); |
1593 | 1592 | ||
1594 | clk_enable(&iim_clk); | 1593 | clk_enable(&iim_clk); |
1595 | mx53_revision(); | 1594 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
1596 | clk_disable(&iim_clk); | 1595 | clk_disable(&iim_clk); |
1597 | mx53_display_revision(); | ||
1598 | 1596 | ||
1599 | /* Set SDHC parents to be PLL2 */ | 1597 | /* Set SDHC parents to be PLL2 */ |
1600 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); | 1598 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); |
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 86f87da59c64..5c5328257dca 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
@@ -18,7 +18,7 @@ | |||
18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
20 | 20 | ||
21 | static int cpu_silicon_rev = -1; | 21 | static int mx5_cpu_rev = -1; |
22 | 22 | ||
23 | #define IIM_SREV 0x24 | 23 | #define IIM_SREV 0x24 |
24 | #define MX50_HW_ADADIG_DIGPROG 0xB0 | 24 | #define MX50_HW_ADADIG_DIGPROG 0xB0 |
@@ -28,11 +28,14 @@ static int get_mx51_srev(void) | |||
28 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); | 28 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
29 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | 29 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; |
30 | 30 | ||
31 | if (rev == 0x0) | 31 | switch (rev) { |
32 | case 0x0: | ||
32 | return IMX_CHIP_REVISION_2_0; | 33 | return IMX_CHIP_REVISION_2_0; |
33 | else if (rev == 0x10) | 34 | case 0x10: |
34 | return IMX_CHIP_REVISION_3_0; | 35 | return IMX_CHIP_REVISION_3_0; |
35 | return 0; | 36 | default: |
37 | return IMX_CHIP_REVISION_UNKNOWN; | ||
38 | } | ||
36 | } | 39 | } |
37 | 40 | ||
38 | /* | 41 | /* |
@@ -45,33 +48,13 @@ int mx51_revision(void) | |||
45 | if (!cpu_is_mx51()) | 48 | if (!cpu_is_mx51()) |
46 | return -EINVAL; | 49 | return -EINVAL; |
47 | 50 | ||
48 | if (cpu_silicon_rev == -1) | 51 | if (mx5_cpu_rev == -1) |
49 | cpu_silicon_rev = get_mx51_srev(); | 52 | mx5_cpu_rev = get_mx51_srev(); |
50 | 53 | ||
51 | return cpu_silicon_rev; | 54 | return mx5_cpu_rev; |
52 | } | 55 | } |
53 | EXPORT_SYMBOL(mx51_revision); | 56 | EXPORT_SYMBOL(mx51_revision); |
54 | 57 | ||
55 | void mx51_display_revision(void) | ||
56 | { | ||
57 | int rev; | ||
58 | char *srev; | ||
59 | rev = mx51_revision(); | ||
60 | |||
61 | switch (rev) { | ||
62 | case IMX_CHIP_REVISION_2_0: | ||
63 | srev = IMX_CHIP_REVISION_2_0_STRING; | ||
64 | break; | ||
65 | case IMX_CHIP_REVISION_3_0: | ||
66 | srev = IMX_CHIP_REVISION_3_0_STRING; | ||
67 | break; | ||
68 | default: | ||
69 | srev = IMX_CHIP_REVISION_UNKNOWN_STRING; | ||
70 | } | ||
71 | printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); | ||
72 | } | ||
73 | EXPORT_SYMBOL(mx51_display_revision); | ||
74 | |||
75 | #ifdef CONFIG_NEON | 58 | #ifdef CONFIG_NEON |
76 | 59 | ||
77 | /* | 60 | /* |
@@ -121,10 +104,10 @@ int mx53_revision(void) | |||
121 | if (!cpu_is_mx53()) | 104 | if (!cpu_is_mx53()) |
122 | return -EINVAL; | 105 | return -EINVAL; |
123 | 106 | ||
124 | if (cpu_silicon_rev == -1) | 107 | if (mx5_cpu_rev == -1) |
125 | cpu_silicon_rev = get_mx53_srev(); | 108 | mx5_cpu_rev = get_mx53_srev(); |
126 | 109 | ||
127 | return cpu_silicon_rev; | 110 | return mx5_cpu_rev; |
128 | } | 111 | } |
129 | EXPORT_SYMBOL(mx53_revision); | 112 | EXPORT_SYMBOL(mx53_revision); |
130 | 113 | ||
@@ -134,7 +117,7 @@ static int get_mx50_srev(void) | |||
134 | u32 rev; | 117 | u32 rev; |
135 | 118 | ||
136 | if (!anatop) { | 119 | if (!anatop) { |
137 | cpu_silicon_rev = -EINVAL; | 120 | mx5_cpu_rev = -EINVAL; |
138 | return 0; | 121 | return 0; |
139 | } | 122 | } |
140 | 123 | ||
@@ -159,36 +142,13 @@ int mx50_revision(void) | |||
159 | if (!cpu_is_mx50()) | 142 | if (!cpu_is_mx50()) |
160 | return -EINVAL; | 143 | return -EINVAL; |
161 | 144 | ||
162 | if (cpu_silicon_rev == -1) | 145 | if (mx5_cpu_rev == -1) |
163 | cpu_silicon_rev = get_mx50_srev(); | 146 | mx5_cpu_rev = get_mx50_srev(); |
164 | 147 | ||
165 | return cpu_silicon_rev; | 148 | return mx5_cpu_rev; |
166 | } | 149 | } |
167 | EXPORT_SYMBOL(mx50_revision); | 150 | EXPORT_SYMBOL(mx50_revision); |
168 | 151 | ||
169 | void mx53_display_revision(void) | ||
170 | { | ||
171 | int rev; | ||
172 | char *srev; | ||
173 | rev = mx53_revision(); | ||
174 | |||
175 | switch (rev) { | ||
176 | case IMX_CHIP_REVISION_1_0: | ||
177 | srev = IMX_CHIP_REVISION_1_0_STRING; | ||
178 | break; | ||
179 | case IMX_CHIP_REVISION_2_0: | ||
180 | srev = IMX_CHIP_REVISION_2_0_STRING; | ||
181 | break; | ||
182 | case IMX_CHIP_REVISION_2_1: | ||
183 | srev = IMX_CHIP_REVISION_2_1_STRING; | ||
184 | break; | ||
185 | default: | ||
186 | srev = IMX_CHIP_REVISION_UNKNOWN_STRING; | ||
187 | } | ||
188 | printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); | ||
189 | } | ||
190 | EXPORT_SYMBOL(mx53_display_revision); | ||
191 | |||
192 | static int __init post_cpu_init(void) | 152 | static int __init post_cpu_init(void) |
193 | { | 153 | { |
194 | unsigned int reg; | 154 | unsigned int reg; |