[ARM] pxafb: allow better platform configurable smart panel timing

For smart panels (LCD panel with internal framebuffer), the following
LCCR3 register bits have different meanings than the parallel one:

  LCCR3_PCP - controls the L_PCLK_WR polarity
  LCCR3_HSP - controls the L_LCLK_A0 polarity
  LCCR3_VSP - controls the L_FCLK_RD polarity

To keep minimum change to the original parallel timing, the .lcd_conn
flags and 'pxafb_mode_info.sync' are re-used to reflect this:

  LCD_PCLK_EDGE_{RISE,FALL} - configures LCCR3_PCP
  sync & FB_SYNC_{HOR,VERT}_HIGH_ACT - configures LCCR3_{HSP,VSP}

Signed-off-by: Eric Miao <eric.miao@marvell.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index cb44410cd456..4201a889ff4e 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -95,6 +95,10 @@ struct pxafb_mode_info {
          *    in pxa27x and pxa3xx, initialize them to the same value or
          *    the larger one will be used
          * 3. same to {rd,wr}_pulse_width
+         *
+         * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
+         * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
+         * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
          */
         unsigned        a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
         unsigned        a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */