diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-04-30 15:18:41 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-05-12 11:46:52 -0400 |
commit | c1dcb14ec2ae3c594ce1c2db953004083f2bd4a0 (patch) | |
tree | 1724db98ba009b3b8af1750af09f2992bc106eeb /arch | |
parent | ff6814d53016081947ff4021e00db3f806a561c9 (diff) |
[MIPS] Alchemy common code style cleanup
Fix many errors and warnings given by checkpatch.pl:
- use of C99 // comments;
- missing space between the type and asterisk in a variable declaration;
- space between the asterisk and function/variable name;
- leading spaces instead of tabs;
- space after opening and before closing parentheses;
- initialization of a 'static' variable to 0;
- missing spaces around assignement/comparison operator;
- brace not on the same line with condition (or 'else') in the 'if'/'switch'
statement;
- missing space between 'if'/'for'/'while' and opening parenthesis;
- use of assignement in 'if' statement's condition;
- printk() without KERN_* facility level;
- EXPORT_SYMBOL() not following its function immediately;
- unnecessary braces for single-statement block;
- adding new 'typedef' (where including <linux/types.h> will do);
- use of 'extern' in the .c file (where it can be avoided by including header);
- line over 80 characters.
In addition to these changes, also do the following:
- insert missing space after opening brace and/or before closing brace in the
structure initializers;
- insert spaces between operator and its operands;
- put the function's result type and name/parameters on the same line;
- properly indent multi-line expressions;
- remove commented out code;
- remove useless initializers and code;
- remove needless parentheses;
- fix broken/excess indentation;
- add missing spaces between operator and its operands;
- insert missing and remove excess new lines;
- group 'else' and 'if' together where possible;
- make au1xxx_platform_init() 'static';
- regroup variable declarations in pm_do_freq() for prettier look;
- replace numeric literals with the matching macros;
- fix printk() format specifiers mismatching the argument types;
- make the multi-line comment style consistent with the kernel style elsewhere
by adding empty first line and/or adding space on their left side;
- make two-line comments that only have one line of text one-line;
- fix typos/errors, capitalize acronyms, etc. in the comments;
- fix/remove obsolete references in the comments;
- reformat some comments;
- add comment about the CPU:counter clock ratio to calc_clock();
- update MontaVista copyright;
- remove Pete Popov's and Steve Longerbeam's old email addresses...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/au1000/common/Makefile | 7 | ||||
-rw-r--r-- | arch/mips/au1000/common/au1xxx_irqmap.c | 145 | ||||
-rw-r--r-- | arch/mips/au1000/common/clocks.c | 24 | ||||
-rw-r--r-- | arch/mips/au1000/common/cputable.c | 5 | ||||
-rw-r--r-- | arch/mips/au1000/common/dbdma.c | 389 | ||||
-rw-r--r-- | arch/mips/au1000/common/dbg_io.c | 32 | ||||
-rw-r--r-- | arch/mips/au1000/common/dma.c | 56 | ||||
-rw-r--r-- | arch/mips/au1000/common/gpio.c | 6 | ||||
-rw-r--r-- | arch/mips/au1000/common/irq.c | 6 | ||||
-rw-r--r-- | arch/mips/au1000/common/pci.c | 11 | ||||
-rw-r--r-- | arch/mips/au1000/common/platform.c | 7 | ||||
-rw-r--r-- | arch/mips/au1000/common/power.c | 157 | ||||
-rw-r--r-- | arch/mips/au1000/common/prom.c | 21 | ||||
-rw-r--r-- | arch/mips/au1000/common/puts.c | 35 | ||||
-rw-r--r-- | arch/mips/au1000/common/reset.c | 33 | ||||
-rw-r--r-- | arch/mips/au1000/common/setup.c | 60 | ||||
-rw-r--r-- | arch/mips/au1000/common/time.c | 78 |
17 files changed, 500 insertions, 572 deletions
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 90e2d7a46e8e..dd0e19dacfcf 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile | |||
@@ -1,9 +1,8 @@ | |||
1 | # | 1 | # |
2 | # Copyright 2000 MontaVista Software Inc. | 2 | # Copyright 2000, 2008 MontaVista Software Inc. |
3 | # Author: MontaVista Software, Inc. | 3 | # Author: MontaVista Software, Inc. <source@mvista.com> |
4 | # ppopov@mvista.com or source@mvista.com | ||
5 | # | 4 | # |
6 | # Makefile for the Alchemy Au1000 CPU, generic files. | 5 | # Makefile for the Alchemy Au1xx0 CPUs, generic files. |
7 | # | 6 | # |
8 | 7 | ||
9 | obj-y += prom.o irq.o puts.o time.o reset.o \ | 8 | obj-y += prom.o irq.o puts.o time.o reset.o \ |
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c index 37a10a01de9d..c7ca1596394c 100644 --- a/arch/mips/au1000/common/au1xxx_irqmap.c +++ b/arch/mips/au1000/common/au1xxx_irqmap.c | |||
@@ -40,20 +40,20 @@ | |||
40 | struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | 40 | struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { |
41 | 41 | ||
42 | #if defined(CONFIG_SOC_AU1000) | 42 | #if defined(CONFIG_SOC_AU1000) |
43 | { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, | 43 | { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
44 | { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, | 44 | { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
45 | { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0}, | 45 | { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 }, |
46 | { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, | 46 | { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, |
47 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0}, | 47 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
48 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0}, | 48 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
49 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, | 49 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, |
50 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, | 50 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, |
51 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, | 51 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, |
52 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, | 52 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, |
53 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, | 53 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, |
54 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, | 54 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, |
55 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, | 55 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, |
56 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, | 56 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, |
57 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 57 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
58 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 58 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
59 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 59 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -62,32 +62,32 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
62 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 62 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
63 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 63 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
64 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 64 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
65 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0}, | 65 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, |
66 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0}, | 66 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, |
67 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | 67 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, |
68 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | 68 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
69 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | 69 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, |
70 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | 70 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, |
71 | { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 71 | { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
72 | { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 72 | { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
73 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | 73 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, |
74 | 74 | ||
75 | #elif defined(CONFIG_SOC_AU1500) | 75 | #elif defined(CONFIG_SOC_AU1500) |
76 | 76 | ||
77 | { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, | 77 | { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
78 | { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, | 78 | { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, |
79 | { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, | 79 | { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, |
80 | { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, | 80 | { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, |
81 | { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, | 81 | { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, |
82 | { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, | 82 | { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, |
83 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, | 83 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, |
84 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, | 84 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, |
85 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, | 85 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, |
86 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, | 86 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, |
87 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, | 87 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, |
88 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, | 88 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, |
89 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, | 89 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, |
90 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, | 90 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, |
91 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 91 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
92 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 92 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
93 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 93 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -100,26 +100,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
100 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | 100 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
101 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | 101 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, |
102 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | 102 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, |
103 | { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 103 | { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
104 | { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 104 | { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
105 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | 105 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, |
106 | 106 | ||
107 | #elif defined(CONFIG_SOC_AU1100) | 107 | #elif defined(CONFIG_SOC_AU1100) |
108 | 108 | ||
109 | { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, | 109 | { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
110 | { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, | 110 | { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
111 | { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0}, | 111 | { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, |
112 | { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, | 112 | { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, |
113 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0}, | 113 | { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
114 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0}, | 114 | { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
115 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, | 115 | { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, |
116 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, | 116 | { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, |
117 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, | 117 | { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, |
118 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, | 118 | { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, |
119 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, | 119 | { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, |
120 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, | 120 | { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, |
121 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, | 121 | { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, |
122 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, | 122 | { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, |
123 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 123 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
124 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 124 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
125 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 125 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -128,33 +128,33 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
128 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 128 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
129 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 129 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
130 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 130 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
131 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0}, | 131 | { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, |
132 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0}, | 132 | { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, |
133 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | 133 | { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, |
134 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | 134 | { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
135 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | 135 | { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, |
136 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, | 136 | { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, |
137 | { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 137 | { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
138 | /*{ AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0},*/ | 138 | /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */ |
139 | { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, | 139 | { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, |
140 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, | 140 | { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, |
141 | 141 | ||
142 | #elif defined(CONFIG_SOC_AU1550) | 142 | #elif defined(CONFIG_SOC_AU1550) |
143 | 143 | ||
144 | { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, | 144 | { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
145 | { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, | 145 | { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, |
146 | { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, | 146 | { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, |
147 | { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 147 | { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
148 | { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0}, | 148 | { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 }, |
149 | { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, | 149 | { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, |
150 | { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, | 150 | { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, |
151 | { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, | 151 | { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, |
152 | { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, | 152 | { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
153 | { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, | 153 | { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, |
154 | { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0}, | 154 | { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
155 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, | 155 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
156 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, | 156 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 }, |
157 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, | 157 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 }, |
158 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 158 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
159 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 159 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
160 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 160 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -163,26 +163,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
163 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 163 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
164 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 164 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
165 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 165 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
166 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, | 166 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 }, |
167 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | 167 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, |
168 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | 168 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
169 | { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, | 169 | { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, |
170 | { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 170 | { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
171 | { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 171 | { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
172 | 172 | ||
173 | #elif defined(CONFIG_SOC_AU1200) | 173 | #elif defined(CONFIG_SOC_AU1200) |
174 | 174 | ||
175 | { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, | 175 | { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
176 | { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, | 176 | { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, |
177 | { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0}, | 177 | { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, |
178 | { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0}, | 178 | { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
179 | { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, | 179 | { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, |
180 | { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, | 180 | { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
181 | { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, | 181 | { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, |
182 | { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0}, | 182 | { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, |
183 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, | 183 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, |
184 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, | 184 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 }, |
185 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, | 185 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 }, |
186 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 186 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
187 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 187 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
188 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 188 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -191,10 +191,10 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
191 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 191 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
192 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 192 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
193 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 193 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
194 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, | 194 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 }, |
195 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, | 195 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, |
196 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, | 196 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, |
197 | { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0}, | 197 | { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 }, |
198 | 198 | ||
199 | #else | 199 | #else |
200 | #error "Error: Unknown Alchemy SOC" | 200 | #error "Error: Unknown Alchemy SOC" |
@@ -203,4 +203,3 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { | |||
203 | }; | 203 | }; |
204 | 204 | ||
205 | int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); | 205 | int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); |
206 | |||
diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/au1000/common/clocks.c index 3ce6cace0eb0..46f8ee0e2657 100644 --- a/arch/mips/au1000/common/clocks.c +++ b/arch/mips/au1000/common/clocks.c | |||
@@ -1,10 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * BRIEF MODULE DESCRIPTION | 2 | * BRIEF MODULE DESCRIPTION |
3 | * Simple Au1000 clocks routines. | 3 | * Simple Au1xx0 clocks routines. |
4 | * | 4 | * |
5 | * Copyright 2001 MontaVista Software Inc. | 5 | * Copyright 2001, 2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. | 6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | * ppopov@mvista.com or source@mvista.com | ||
8 | * | 7 | * |
9 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
10 | * under the terms of the GNU General Public License as published by the | 9 | * under the terms of the GNU General Public License as published by the |
@@ -30,8 +29,8 @@ | |||
30 | #include <linux/module.h> | 29 | #include <linux/module.h> |
31 | #include <asm/mach-au1x00/au1000.h> | 30 | #include <asm/mach-au1x00/au1000.h> |
32 | 31 | ||
33 | static unsigned int au1x00_clock; // Hz | 32 | static unsigned int au1x00_clock; /* Hz */ |
34 | static unsigned int lcd_clock; // KHz | 33 | static unsigned int lcd_clock; /* KHz */ |
35 | static unsigned long uart_baud_base; | 34 | static unsigned long uart_baud_base; |
36 | 35 | ||
37 | /* | 36 | /* |
@@ -47,8 +46,6 @@ unsigned int get_au1x00_speed(void) | |||
47 | return au1x00_clock; | 46 | return au1x00_clock; |
48 | } | 47 | } |
49 | 48 | ||
50 | |||
51 | |||
52 | /* | 49 | /* |
53 | * The UART baud base is not known at compile time ... if | 50 | * The UART baud base is not known at compile time ... if |
54 | * we want to be able to use the same code on different | 51 | * we want to be able to use the same code on different |
@@ -73,24 +70,23 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) | |||
73 | void set_au1x00_lcd_clock(void) | 70 | void set_au1x00_lcd_clock(void) |
74 | { | 71 | { |
75 | unsigned int static_cfg0; | 72 | unsigned int static_cfg0; |
76 | unsigned int sys_busclk = | 73 | unsigned int sys_busclk = (get_au1x00_speed() / 1000) / |
77 | (get_au1x00_speed()/1000) / | 74 | ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2); |
78 | ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2); | ||
79 | 75 | ||
80 | static_cfg0 = au_readl(MEM_STCFG0); | 76 | static_cfg0 = au_readl(MEM_STCFG0); |
81 | 77 | ||
82 | if (static_cfg0 & (1<<11)) | 78 | if (static_cfg0 & (1 << 11)) |
83 | lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ | 79 | lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ |
84 | else | 80 | else |
85 | lcd_clock = sys_busclk / 4; | 81 | lcd_clock = sys_busclk / 4; |
86 | 82 | ||
87 | if (lcd_clock > 50000) /* Epson MAX */ | 83 | if (lcd_clock > 50000) /* Epson MAX */ |
88 | printk("warning: LCD clock too high (%d KHz)\n", lcd_clock); | 84 | printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", |
85 | lcd_clock); | ||
89 | } | 86 | } |
90 | 87 | ||
91 | unsigned int get_au1x00_lcd_clock(void) | 88 | unsigned int get_au1x00_lcd_clock(void) |
92 | { | 89 | { |
93 | return lcd_clock; | 90 | return lcd_clock; |
94 | } | 91 | } |
95 | |||
96 | EXPORT_SYMBOL(get_au1x00_lcd_clock); | 92 | EXPORT_SYMBOL(get_au1x00_lcd_clock); |
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c index 8c93a05d7382..ba6430bc2d03 100644 --- a/arch/mips/au1000/common/cputable.c +++ b/arch/mips/au1000/common/cputable.c | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | #include <asm/mach-au1x00/au1000.h> | 15 | #include <asm/mach-au1x00/au1000.h> |
16 | 16 | ||
17 | struct cpu_spec* cur_cpu_spec[NR_CPUS]; | 17 | struct cpu_spec *cur_cpu_spec[NR_CPUS]; |
18 | 18 | ||
19 | /* With some thought, we can probably use the mask to reduce the | 19 | /* With some thought, we can probably use the mask to reduce the |
20 | * size of the table. | 20 | * size of the table. |
@@ -39,8 +39,7 @@ struct cpu_spec cpu_specs[] = { | |||
39 | { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } | 39 | { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } |
40 | }; | 40 | }; |
41 | 41 | ||
42 | void | 42 | void set_cpuspec(void) |
43 | set_cpuspec(void) | ||
44 | { | 43 | { |
45 | struct cpu_spec *sp; | 44 | struct cpu_spec *sp; |
46 | u32 prid; | 45 | u32 prid; |
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 53377dfc0640..42d555236de1 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c | |||
@@ -53,12 +53,11 @@ | |||
53 | */ | 53 | */ |
54 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); | 54 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); |
55 | 55 | ||
56 | /* I couldn't find a macro that did this...... | 56 | /* I couldn't find a macro that did this... */ |
57 | */ | ||
58 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) | 57 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) |
59 | 58 | ||
60 | static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; | 59 | static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
61 | static int dbdma_initialized=0; | 60 | static int dbdma_initialized; |
62 | static void au1xxx_dbdma_init(void); | 61 | static void au1xxx_dbdma_init(void); |
63 | 62 | ||
64 | static dbdev_tab_t dbdev_tab[] = { | 63 | static dbdev_tab_t dbdev_tab[] = { |
@@ -149,7 +148,7 @@ static dbdev_tab_t dbdev_tab[] = { | |||
149 | 148 | ||
150 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | 149 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, |
151 | 150 | ||
152 | #endif // CONFIG_SOC_AU1200 | 151 | #endif /* CONFIG_SOC_AU1200 */ |
153 | 152 | ||
154 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | 153 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
155 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | 154 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
@@ -177,8 +176,7 @@ static dbdev_tab_t dbdev_tab[] = { | |||
177 | 176 | ||
178 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; | 177 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; |
179 | 178 | ||
180 | static dbdev_tab_t * | 179 | static dbdev_tab_t *find_dbdev_id(u32 id) |
181 | find_dbdev_id(u32 id) | ||
182 | { | 180 | { |
183 | int i; | 181 | int i; |
184 | dbdev_tab_t *p; | 182 | dbdev_tab_t *p; |
@@ -190,29 +188,27 @@ find_dbdev_id(u32 id) | |||
190 | return NULL; | 188 | return NULL; |
191 | } | 189 | } |
192 | 190 | ||
193 | void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) | 191 | void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) |
194 | { | 192 | { |
195 | return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 193 | return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
196 | } | 194 | } |
197 | EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); | 195 | EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); |
198 | 196 | ||
199 | u32 | 197 | u32 au1xxx_ddma_add_device(dbdev_tab_t *dev) |
200 | au1xxx_ddma_add_device(dbdev_tab_t *dev) | ||
201 | { | 198 | { |
202 | u32 ret = 0; | 199 | u32 ret = 0; |
203 | dbdev_tab_t *p=NULL; | 200 | dbdev_tab_t *p; |
204 | static u16 new_id=0x1000; | 201 | static u16 new_id = 0x1000; |
205 | 202 | ||
206 | p = find_dbdev_id(~0); | 203 | p = find_dbdev_id(~0); |
207 | if ( NULL != p ) | 204 | if (NULL != p) { |
208 | { | ||
209 | memcpy(p, dev, sizeof(dbdev_tab_t)); | 205 | memcpy(p, dev, sizeof(dbdev_tab_t)); |
210 | p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); | 206 | p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); |
211 | ret = p->dev_id; | 207 | ret = p->dev_id; |
212 | new_id++; | 208 | new_id++; |
213 | #if 0 | 209 | #if 0 |
214 | printk("add_device: id:%x flags:%x padd:%x\n", | 210 | printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n", |
215 | p->dev_id, p->dev_flags, p->dev_physaddr ); | 211 | p->dev_id, p->dev_flags, p->dev_physaddr); |
216 | #endif | 212 | #endif |
217 | } | 213 | } |
218 | 214 | ||
@@ -220,10 +216,8 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev) | |||
220 | } | 216 | } |
221 | EXPORT_SYMBOL(au1xxx_ddma_add_device); | 217 | EXPORT_SYMBOL(au1xxx_ddma_add_device); |
222 | 218 | ||
223 | /* Allocate a channel and return a non-zero descriptor if successful. | 219 | /* Allocate a channel and return a non-zero descriptor if successful. */ |
224 | */ | 220 | u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, |
225 | u32 | ||
226 | au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | ||
227 | void (*callback)(int, void *), void *callparam) | 221 | void (*callback)(int, void *), void *callparam) |
228 | { | 222 | { |
229 | unsigned long flags; | 223 | unsigned long flags; |
@@ -234,7 +228,8 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
234 | chan_tab_t *ctp; | 228 | chan_tab_t *ctp; |
235 | au1x_dma_chan_t *cp; | 229 | au1x_dma_chan_t *cp; |
236 | 230 | ||
237 | /* We do the intialization on the first channel allocation. | 231 | /* |
232 | * We do the intialization on the first channel allocation. | ||
238 | * We have to wait because of the interrupt handler initialization | 233 | * We have to wait because of the interrupt handler initialization |
239 | * which can't be done successfully during board set up. | 234 | * which can't be done successfully during board set up. |
240 | */ | 235 | */ |
@@ -242,16 +237,17 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
242 | au1xxx_dbdma_init(); | 237 | au1xxx_dbdma_init(); |
243 | dbdma_initialized = 1; | 238 | dbdma_initialized = 1; |
244 | 239 | ||
245 | if ((stp = find_dbdev_id(srcid)) == NULL) | 240 | stp = find_dbdev_id(srcid); |
241 | if (stp == NULL) | ||
246 | return 0; | 242 | return 0; |
247 | if ((dtp = find_dbdev_id(destid)) == NULL) | 243 | dtp = find_dbdev_id(destid); |
244 | if (dtp == NULL) | ||
248 | return 0; | 245 | return 0; |
249 | 246 | ||
250 | used = 0; | 247 | used = 0; |
251 | rv = 0; | 248 | rv = 0; |
252 | 249 | ||
253 | /* Check to see if we can get both channels. | 250 | /* Check to see if we can get both channels. */ |
254 | */ | ||
255 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | 251 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); |
256 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || | 252 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || |
257 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { | 253 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { |
@@ -261,35 +257,30 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
261 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { | 257 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { |
262 | /* Got destination */ | 258 | /* Got destination */ |
263 | dtp->dev_flags |= DEV_FLAGS_INUSE; | 259 | dtp->dev_flags |= DEV_FLAGS_INUSE; |
264 | } | 260 | } else { |
265 | else { | 261 | /* Can't get dest. Release src. */ |
266 | /* Can't get dest. Release src. | ||
267 | */ | ||
268 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | 262 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
269 | used++; | 263 | used++; |
270 | } | 264 | } |
271 | } | 265 | } else |
272 | else { | ||
273 | used++; | 266 | used++; |
274 | } | ||
275 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | 267 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
276 | 268 | ||
277 | if (!used) { | 269 | if (!used) { |
278 | /* Let's see if we can allocate a channel for it. | 270 | /* Let's see if we can allocate a channel for it. */ |
279 | */ | ||
280 | ctp = NULL; | 271 | ctp = NULL; |
281 | chan = 0; | 272 | chan = 0; |
282 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | 273 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); |
283 | for (i=0; i<NUM_DBDMA_CHANS; i++) { | 274 | for (i = 0; i < NUM_DBDMA_CHANS; i++) |
284 | if (chan_tab_ptr[i] == NULL) { | 275 | if (chan_tab_ptr[i] == NULL) { |
285 | /* If kmalloc fails, it is caught below same | 276 | /* |
277 | * If kmalloc fails, it is caught below same | ||
286 | * as a channel not available. | 278 | * as a channel not available. |
287 | */ | 279 | */ |
288 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); | 280 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); |
289 | chan_tab_ptr[i] = ctp; | 281 | chan_tab_ptr[i] = ctp; |
290 | break; | 282 | break; |
291 | } | 283 | } |
292 | } | ||
293 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | 284 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
294 | 285 | ||
295 | if (ctp != NULL) { | 286 | if (ctp != NULL) { |
@@ -304,8 +295,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
304 | ctp->chan_callback = callback; | 295 | ctp->chan_callback = callback; |
305 | ctp->chan_callparam = callparam; | 296 | ctp->chan_callparam = callparam; |
306 | 297 | ||
307 | /* Initialize channel configuration. | 298 | /* Initialize channel configuration. */ |
308 | */ | ||
309 | i = 0; | 299 | i = 0; |
310 | if (stp->dev_intlevel) | 300 | if (stp->dev_intlevel) |
311 | i |= DDMA_CFG_SED; | 301 | i |= DDMA_CFG_SED; |
@@ -326,8 +316,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
326 | * operations. | 316 | * operations. |
327 | */ | 317 | */ |
328 | rv = (u32)(&chan_tab_ptr[chan]); | 318 | rv = (u32)(&chan_tab_ptr[chan]); |
329 | } | 319 | } else { |
330 | else { | ||
331 | /* Release devices */ | 320 | /* Release devices */ |
332 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | 321 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
333 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | 322 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; |
@@ -337,11 +326,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
337 | } | 326 | } |
338 | EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); | 327 | EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); |
339 | 328 | ||
340 | /* Set the device width if source or destination is a FIFO. | 329 | /* |
330 | * Set the device width if source or destination is a FIFO. | ||
341 | * Should be 8, 16, or 32 bits. | 331 | * Should be 8, 16, or 32 bits. |
342 | */ | 332 | */ |
343 | u32 | 333 | u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits) |
344 | au1xxx_dbdma_set_devwidth(u32 chanid, int bits) | ||
345 | { | 334 | { |
346 | u32 rv; | 335 | u32 rv; |
347 | chan_tab_t *ctp; | 336 | chan_tab_t *ctp; |
@@ -365,10 +354,8 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits) | |||
365 | } | 354 | } |
366 | EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); | 355 | EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); |
367 | 356 | ||
368 | /* Allocate a descriptor ring, initializing as much as possible. | 357 | /* Allocate a descriptor ring, initializing as much as possible. */ |
369 | */ | 358 | u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries) |
370 | u32 | ||
371 | au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | ||
372 | { | 359 | { |
373 | int i; | 360 | int i; |
374 | u32 desc_base, srcid, destid; | 361 | u32 desc_base, srcid, destid; |
@@ -378,43 +365,45 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
378 | dbdev_tab_t *stp, *dtp; | 365 | dbdev_tab_t *stp, *dtp; |
379 | au1x_ddma_desc_t *dp; | 366 | au1x_ddma_desc_t *dp; |
380 | 367 | ||
381 | /* I guess we could check this to be within the | 368 | /* |
369 | * I guess we could check this to be within the | ||
382 | * range of the table...... | 370 | * range of the table...... |
383 | */ | 371 | */ |
384 | ctp = *((chan_tab_t **)chanid); | 372 | ctp = *((chan_tab_t **)chanid); |
385 | stp = ctp->chan_src; | 373 | stp = ctp->chan_src; |
386 | dtp = ctp->chan_dest; | 374 | dtp = ctp->chan_dest; |
387 | 375 | ||
388 | /* The descriptors must be 32-byte aligned. There is a | 376 | /* |
377 | * The descriptors must be 32-byte aligned. There is a | ||
389 | * possibility the allocation will give us such an address, | 378 | * possibility the allocation will give us such an address, |
390 | * and if we try that first we are likely to not waste larger | 379 | * and if we try that first we are likely to not waste larger |
391 | * slabs of memory. | 380 | * slabs of memory. |
392 | */ | 381 | */ |
393 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), | 382 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), |
394 | GFP_KERNEL|GFP_DMA); | 383 | GFP_KERNEL|GFP_DMA); |
395 | if (desc_base == 0) | 384 | if (desc_base == 0) |
396 | return 0; | 385 | return 0; |
397 | 386 | ||
398 | if (desc_base & 0x1f) { | 387 | if (desc_base & 0x1f) { |
399 | /* Lost....do it again, allocate extra, and round | 388 | /* |
389 | * Lost....do it again, allocate extra, and round | ||
400 | * the address base. | 390 | * the address base. |
401 | */ | 391 | */ |
402 | kfree((const void *)desc_base); | 392 | kfree((const void *)desc_base); |
403 | i = entries * sizeof(au1x_ddma_desc_t); | 393 | i = entries * sizeof(au1x_ddma_desc_t); |
404 | i += (sizeof(au1x_ddma_desc_t) - 1); | 394 | i += (sizeof(au1x_ddma_desc_t) - 1); |
405 | if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0) | 395 | desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA); |
396 | if (desc_base == 0) | ||
406 | return 0; | 397 | return 0; |
407 | 398 | ||
408 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); | 399 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); |
409 | } | 400 | } |
410 | dp = (au1x_ddma_desc_t *)desc_base; | 401 | dp = (au1x_ddma_desc_t *)desc_base; |
411 | 402 | ||
412 | /* Keep track of the base descriptor. | 403 | /* Keep track of the base descriptor. */ |
413 | */ | ||
414 | ctp->chan_desc_base = dp; | 404 | ctp->chan_desc_base = dp; |
415 | 405 | ||
416 | /* Initialize the rings with as much information as we know. | 406 | /* Initialize the rings with as much information as we know. */ |
417 | */ | ||
418 | srcid = stp->dev_id; | 407 | srcid = stp->dev_id; |
419 | destid = dtp->dev_id; | 408 | destid = dtp->dev_id; |
420 | 409 | ||
@@ -426,11 +415,12 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
426 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; | 415 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; |
427 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); | 416 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); |
428 | 417 | ||
429 | /* is it mem to mem transfer? */ | 418 | /* Is it mem to mem transfer? */ |
430 | if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && | 419 | if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || |
431 | ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) { | 420 | (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && |
432 | cmd0 |= DSCR_CMD0_MEM; | 421 | ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || |
433 | } | 422 | (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) |
423 | cmd0 |= DSCR_CMD0_MEM; | ||
434 | 424 | ||
435 | switch (stp->dev_devwidth) { | 425 | switch (stp->dev_devwidth) { |
436 | case 8: | 426 | case 8: |
@@ -458,15 +448,17 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
458 | break; | 448 | break; |
459 | } | 449 | } |
460 | 450 | ||
461 | /* If the device is marked as an in/out FIFO, ensure it is | 451 | /* |
452 | * If the device is marked as an in/out FIFO, ensure it is | ||
462 | * set non-coherent. | 453 | * set non-coherent. |
463 | */ | 454 | */ |
464 | if (stp->dev_flags & DEV_FLAGS_IN) | 455 | if (stp->dev_flags & DEV_FLAGS_IN) |
465 | cmd0 |= DSCR_CMD0_SN; /* Source in fifo */ | 456 | cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */ |
466 | if (dtp->dev_flags & DEV_FLAGS_OUT) | 457 | if (dtp->dev_flags & DEV_FLAGS_OUT) |
467 | cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */ | 458 | cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */ |
468 | 459 | ||
469 | /* Set up source1. For now, assume no stride and increment. | 460 | /* |
461 | * Set up source1. For now, assume no stride and increment. | ||
470 | * A channel attribute update can change this later. | 462 | * A channel attribute update can change this later. |
471 | */ | 463 | */ |
472 | switch (stp->dev_tsize) { | 464 | switch (stp->dev_tsize) { |
@@ -485,19 +477,19 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
485 | break; | 477 | break; |
486 | } | 478 | } |
487 | 479 | ||
488 | /* If source input is fifo, set static address. | 480 | /* If source input is FIFO, set static address. */ |
489 | */ | ||
490 | if (stp->dev_flags & DEV_FLAGS_IN) { | 481 | if (stp->dev_flags & DEV_FLAGS_IN) { |
491 | if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) | 482 | if (stp->dev_flags & DEV_FLAGS_BURSTABLE) |
492 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); | 483 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); |
493 | else | 484 | else |
494 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); | 485 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
495 | |||
496 | } | 486 | } |
487 | |||
497 | if (stp->dev_physaddr) | 488 | if (stp->dev_physaddr) |
498 | src0 = stp->dev_physaddr; | 489 | src0 = stp->dev_physaddr; |
499 | 490 | ||
500 | /* Set up dest1. For now, assume no stride and increment. | 491 | /* |
492 | * Set up dest1. For now, assume no stride and increment. | ||
501 | * A channel attribute update can change this later. | 493 | * A channel attribute update can change this later. |
502 | */ | 494 | */ |
503 | switch (dtp->dev_tsize) { | 495 | switch (dtp->dev_tsize) { |
@@ -516,22 +508,24 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
516 | break; | 508 | break; |
517 | } | 509 | } |
518 | 510 | ||
519 | /* If destination output is fifo, set static address. | 511 | /* If destination output is FIFO, set static address. */ |
520 | */ | ||
521 | if (dtp->dev_flags & DEV_FLAGS_OUT) { | 512 | if (dtp->dev_flags & DEV_FLAGS_OUT) { |
522 | if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE ) | 513 | if (dtp->dev_flags & DEV_FLAGS_BURSTABLE) |
523 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); | 514 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); |
524 | else | 515 | else |
525 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); | 516 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); |
526 | } | 517 | } |
518 | |||
527 | if (dtp->dev_physaddr) | 519 | if (dtp->dev_physaddr) |
528 | dest0 = dtp->dev_physaddr; | 520 | dest0 = dtp->dev_physaddr; |
529 | 521 | ||
530 | #if 0 | 522 | #if 0 |
531 | printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", | 523 | printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x " |
532 | dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 ); | 524 | "source1:%x dest0:%x dest1:%x\n", |
525 | dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, | ||
526 | src1, dest0, dest1); | ||
533 | #endif | 527 | #endif |
534 | for (i=0; i<entries; i++) { | 528 | for (i = 0; i < entries; i++) { |
535 | dp->dscr_cmd0 = cmd0; | 529 | dp->dscr_cmd0 = cmd0; |
536 | dp->dscr_cmd1 = cmd1; | 530 | dp->dscr_cmd1 = cmd1; |
537 | dp->dscr_source0 = src0; | 531 | dp->dscr_source0 = src0; |
@@ -545,49 +539,49 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |||
545 | dp++; | 539 | dp++; |
546 | } | 540 | } |
547 | 541 | ||
548 | /* Make last descrptor point to the first. | 542 | /* Make last descrptor point to the first. */ |
549 | */ | ||
550 | dp--; | 543 | dp--; |
551 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); | 544 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); |
552 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | 545 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; |
553 | 546 | ||
554 | return (u32)(ctp->chan_desc_base); | 547 | return (u32)ctp->chan_desc_base; |
555 | } | 548 | } |
556 | EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); | 549 | EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); |
557 | 550 | ||
558 | /* Put a source buffer into the DMA ring. | 551 | /* |
552 | * Put a source buffer into the DMA ring. | ||
559 | * This updates the source pointer and byte count. Normally used | 553 | * This updates the source pointer and byte count. Normally used |
560 | * for memory to fifo transfers. | 554 | * for memory to fifo transfers. |
561 | */ | 555 | */ |
562 | u32 | 556 | u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) |
563 | _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) | ||
564 | { | 557 | { |
565 | chan_tab_t *ctp; | 558 | chan_tab_t *ctp; |
566 | au1x_ddma_desc_t *dp; | 559 | au1x_ddma_desc_t *dp; |
567 | 560 | ||
568 | /* I guess we could check this to be within the | 561 | /* |
562 | * I guess we could check this to be within the | ||
569 | * range of the table...... | 563 | * range of the table...... |
570 | */ | 564 | */ |
571 | ctp = *((chan_tab_t **)chanid); | 565 | ctp = *(chan_tab_t **)chanid; |
572 | 566 | ||
573 | /* We should have multiple callers for a particular channel, | 567 | /* |
568 | * We should have multiple callers for a particular channel, | ||
574 | * an interrupt doesn't affect this pointer nor the descriptor, | 569 | * an interrupt doesn't affect this pointer nor the descriptor, |
575 | * so no locking should be needed. | 570 | * so no locking should be needed. |
576 | */ | 571 | */ |
577 | dp = ctp->put_ptr; | 572 | dp = ctp->put_ptr; |
578 | 573 | ||
579 | /* If the descriptor is valid, we are way ahead of the DMA | 574 | /* |
575 | * If the descriptor is valid, we are way ahead of the DMA | ||
580 | * engine, so just return an error condition. | 576 | * engine, so just return an error condition. |
581 | */ | 577 | */ |
582 | if (dp->dscr_cmd0 & DSCR_CMD0_V) { | 578 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
583 | return 0; | 579 | return 0; |
584 | } | ||
585 | 580 | ||
586 | /* Load up buffer address and byte count. | 581 | /* Load up buffer address and byte count. */ |
587 | */ | ||
588 | dp->dscr_source0 = virt_to_phys(buf); | 582 | dp->dscr_source0 = virt_to_phys(buf); |
589 | dp->dscr_cmd1 = nbytes; | 583 | dp->dscr_cmd1 = nbytes; |
590 | /* Check flags */ | 584 | /* Check flags */ |
591 | if (flags & DDMA_FLAGS_IE) | 585 | if (flags & DDMA_FLAGS_IE) |
592 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | 586 | dp->dscr_cmd0 |= DSCR_CMD0_IE; |
593 | if (flags & DDMA_FLAGS_NOIE) | 587 | if (flags & DDMA_FLAGS_NOIE) |
@@ -595,23 +589,21 @@ _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) | |||
595 | 589 | ||
596 | /* | 590 | /* |
597 | * There is an errata on the Au1200/Au1550 parts that could result | 591 | * There is an errata on the Au1200/Au1550 parts that could result |
598 | * in "stale" data being DMA'd. It has to do with the snoop logic on | 592 | * in "stale" data being DMA'ed. It has to do with the snoop logic on |
599 | * the dache eviction buffer. NONCOHERENT_IO is on by default for | 593 | * the cache eviction buffer. DMA_NONCOHERENT is on by default for |
600 | * these parts. If it is fixedin the future, these dma_cache_inv will | 594 | * these parts. If it is fixed in the future, these dma_cache_inv will |
601 | * just be nothing more than empty macros. See io.h. | 595 | * just be nothing more than empty macros. See io.h. |
602 | * */ | 596 | */ |
603 | dma_cache_wback_inv((unsigned long)buf, nbytes); | 597 | dma_cache_wback_inv((unsigned long)buf, nbytes); |
604 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ | 598 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
605 | au_sync(); | 599 | au_sync(); |
606 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); | 600 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
607 | ctp->chan_ptr->ddma_dbell = 0; | 601 | ctp->chan_ptr->ddma_dbell = 0; |
608 | 602 | ||
609 | /* Get next descriptor pointer. | 603 | /* Get next descriptor pointer. */ |
610 | */ | ||
611 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 604 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
612 | 605 | ||
613 | /* return something not zero. | 606 | /* Return something non-zero. */ |
614 | */ | ||
615 | return nbytes; | 607 | return nbytes; |
616 | } | 608 | } |
617 | EXPORT_SYMBOL(_au1xxx_dbdma_put_source); | 609 | EXPORT_SYMBOL(_au1xxx_dbdma_put_source); |
@@ -654,81 +646,77 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) | |||
654 | dp->dscr_dest0 = virt_to_phys(buf); | 646 | dp->dscr_dest0 = virt_to_phys(buf); |
655 | dp->dscr_cmd1 = nbytes; | 647 | dp->dscr_cmd1 = nbytes; |
656 | #if 0 | 648 | #if 0 |
657 | printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", | 649 | printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", |
658 | dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, | 650 | dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, |
659 | dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 ); | 651 | dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); |
660 | #endif | 652 | #endif |
661 | /* | 653 | /* |
662 | * There is an errata on the Au1200/Au1550 parts that could result in | 654 | * There is an errata on the Au1200/Au1550 parts that could result in |
663 | * "stale" data being DMA'd. It has to do with the snoop logic on the | 655 | * "stale" data being DMA'ed. It has to do with the snoop logic on the |
664 | * dache eviction buffer. NONCOHERENT_IO is on by default for these | 656 | * cache eviction buffer. DMA_NONCOHERENT is on by default for these |
665 | * parts. If it is fixedin the future, these dma_cache_inv will just | 657 | * parts. If it is fixed in the future, these dma_cache_inv will just |
666 | * be nothing more than empty macros. See io.h. | 658 | * be nothing more than empty macros. See io.h. |
667 | * */ | 659 | */ |
668 | dma_cache_inv((unsigned long)buf, nbytes); | 660 | dma_cache_inv((unsigned long)buf, nbytes); |
669 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ | 661 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
670 | au_sync(); | 662 | au_sync(); |
671 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); | 663 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
672 | ctp->chan_ptr->ddma_dbell = 0; | 664 | ctp->chan_ptr->ddma_dbell = 0; |
673 | 665 | ||
674 | /* Get next descriptor pointer. | 666 | /* Get next descriptor pointer. */ |
675 | */ | ||
676 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 667 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
677 | 668 | ||
678 | /* return something not zero. | 669 | /* Return something non-zero. */ |
679 | */ | ||
680 | return nbytes; | 670 | return nbytes; |
681 | } | 671 | } |
682 | EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); | 672 | EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); |
683 | 673 | ||
684 | /* Get a destination buffer into the DMA ring. | 674 | /* |
675 | * Get a destination buffer into the DMA ring. | ||
685 | * Normally used to get a full buffer from the ring during fifo | 676 | * Normally used to get a full buffer from the ring during fifo |
686 | * to memory transfers. This does not set the valid bit, you will | 677 | * to memory transfers. This does not set the valid bit, you will |
687 | * have to put another destination buffer to keep the DMA going. | 678 | * have to put another destination buffer to keep the DMA going. |
688 | */ | 679 | */ |
689 | u32 | 680 | u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) |
690 | au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) | ||
691 | { | 681 | { |
692 | chan_tab_t *ctp; | 682 | chan_tab_t *ctp; |
693 | au1x_ddma_desc_t *dp; | 683 | au1x_ddma_desc_t *dp; |
694 | u32 rv; | 684 | u32 rv; |
695 | 685 | ||
696 | /* I guess we could check this to be within the | 686 | /* |
687 | * I guess we could check this to be within the | ||
697 | * range of the table...... | 688 | * range of the table...... |
698 | */ | 689 | */ |
699 | ctp = *((chan_tab_t **)chanid); | 690 | ctp = *((chan_tab_t **)chanid); |
700 | 691 | ||
701 | /* We should have multiple callers for a particular channel, | 692 | /* |
693 | * We should have multiple callers for a particular channel, | ||
702 | * an interrupt doesn't affect this pointer nor the descriptor, | 694 | * an interrupt doesn't affect this pointer nor the descriptor, |
703 | * so no locking should be needed. | 695 | * so no locking should be needed. |
704 | */ | 696 | */ |
705 | dp = ctp->get_ptr; | 697 | dp = ctp->get_ptr; |
706 | 698 | ||
707 | /* If the descriptor is valid, we are way ahead of the DMA | 699 | /* |
700 | * If the descriptor is valid, we are way ahead of the DMA | ||
708 | * engine, so just return an error condition. | 701 | * engine, so just return an error condition. |
709 | */ | 702 | */ |
710 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | 703 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
711 | return 0; | 704 | return 0; |
712 | 705 | ||
713 | /* Return buffer address and byte count. | 706 | /* Return buffer address and byte count. */ |
714 | */ | ||
715 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); | 707 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); |
716 | *nbytes = dp->dscr_cmd1; | 708 | *nbytes = dp->dscr_cmd1; |
717 | rv = dp->dscr_stat; | 709 | rv = dp->dscr_stat; |
718 | 710 | ||
719 | /* Get next descriptor pointer. | 711 | /* Get next descriptor pointer. */ |
720 | */ | ||
721 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 712 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
722 | 713 | ||
723 | /* return something not zero. | 714 | /* Return something non-zero. */ |
724 | */ | ||
725 | return rv; | 715 | return rv; |
726 | } | 716 | } |
727 | |||
728 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); | 717 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); |
729 | 718 | ||
730 | void | 719 | void au1xxx_dbdma_stop(u32 chanid) |
731 | au1xxx_dbdma_stop(u32 chanid) | ||
732 | { | 720 | { |
733 | chan_tab_t *ctp; | 721 | chan_tab_t *ctp; |
734 | au1x_dma_chan_t *cp; | 722 | au1x_dma_chan_t *cp; |
@@ -743,7 +731,7 @@ au1xxx_dbdma_stop(u32 chanid) | |||
743 | udelay(1); | 731 | udelay(1); |
744 | halt_timeout++; | 732 | halt_timeout++; |
745 | if (halt_timeout > 100) { | 733 | if (halt_timeout > 100) { |
746 | printk("warning: DMA channel won't halt\n"); | 734 | printk(KERN_WARNING "warning: DMA channel won't halt\n"); |
747 | break; | 735 | break; |
748 | } | 736 | } |
749 | } | 737 | } |
@@ -753,12 +741,12 @@ au1xxx_dbdma_stop(u32 chanid) | |||
753 | } | 741 | } |
754 | EXPORT_SYMBOL(au1xxx_dbdma_stop); | 742 | EXPORT_SYMBOL(au1xxx_dbdma_stop); |
755 | 743 | ||
756 | /* Start using the current descriptor pointer. If the dbdma encounters | 744 | /* |
757 | * a not valid descriptor, it will stop. In this case, we can just | 745 | * Start using the current descriptor pointer. If the DBDMA encounters |
746 | * a non-valid descriptor, it will stop. In this case, we can just | ||
758 | * continue by adding a buffer to the list and starting again. | 747 | * continue by adding a buffer to the list and starting again. |
759 | */ | 748 | */ |
760 | void | 749 | void au1xxx_dbdma_start(u32 chanid) |
761 | au1xxx_dbdma_start(u32 chanid) | ||
762 | { | 750 | { |
763 | chan_tab_t *ctp; | 751 | chan_tab_t *ctp; |
764 | au1x_dma_chan_t *cp; | 752 | au1x_dma_chan_t *cp; |
@@ -773,8 +761,7 @@ au1xxx_dbdma_start(u32 chanid) | |||
773 | } | 761 | } |
774 | EXPORT_SYMBOL(au1xxx_dbdma_start); | 762 | EXPORT_SYMBOL(au1xxx_dbdma_start); |
775 | 763 | ||
776 | void | 764 | void au1xxx_dbdma_reset(u32 chanid) |
777 | au1xxx_dbdma_reset(u32 chanid) | ||
778 | { | 765 | { |
779 | chan_tab_t *ctp; | 766 | chan_tab_t *ctp; |
780 | au1x_ddma_desc_t *dp; | 767 | au1x_ddma_desc_t *dp; |
@@ -784,14 +771,14 @@ au1xxx_dbdma_reset(u32 chanid) | |||
784 | ctp = *((chan_tab_t **)chanid); | 771 | ctp = *((chan_tab_t **)chanid); |
785 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | 772 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; |
786 | 773 | ||
787 | /* Run through the descriptors and reset the valid indicator. | 774 | /* Run through the descriptors and reset the valid indicator. */ |
788 | */ | ||
789 | dp = ctp->chan_desc_base; | 775 | dp = ctp->chan_desc_base; |
790 | 776 | ||
791 | do { | 777 | do { |
792 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; | 778 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; |
793 | /* reset our SW status -- this is used to determine | 779 | /* |
794 | * if a descriptor is in use by upper level SW. Since | 780 | * Reset our software status -- this is used to determine |
781 | * if a descriptor is in use by upper level software. Since | ||
795 | * posting can reset 'V' bit. | 782 | * posting can reset 'V' bit. |
796 | */ | 783 | */ |
797 | dp->sw_status = 0; | 784 | dp->sw_status = 0; |
@@ -800,8 +787,7 @@ au1xxx_dbdma_reset(u32 chanid) | |||
800 | } | 787 | } |
801 | EXPORT_SYMBOL(au1xxx_dbdma_reset); | 788 | EXPORT_SYMBOL(au1xxx_dbdma_reset); |
802 | 789 | ||
803 | u32 | 790 | u32 au1xxx_get_dma_residue(u32 chanid) |
804 | au1xxx_get_dma_residue(u32 chanid) | ||
805 | { | 791 | { |
806 | chan_tab_t *ctp; | 792 | chan_tab_t *ctp; |
807 | au1x_dma_chan_t *cp; | 793 | au1x_dma_chan_t *cp; |
@@ -810,18 +796,15 @@ au1xxx_get_dma_residue(u32 chanid) | |||
810 | ctp = *((chan_tab_t **)chanid); | 796 | ctp = *((chan_tab_t **)chanid); |
811 | cp = ctp->chan_ptr; | 797 | cp = ctp->chan_ptr; |
812 | 798 | ||
813 | /* This is only valid if the channel is stopped. | 799 | /* This is only valid if the channel is stopped. */ |
814 | */ | ||
815 | rv = cp->ddma_bytecnt; | 800 | rv = cp->ddma_bytecnt; |
816 | au_sync(); | 801 | au_sync(); |
817 | 802 | ||
818 | return rv; | 803 | return rv; |
819 | } | 804 | } |
820 | |||
821 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); | 805 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); |
822 | 806 | ||
823 | void | 807 | void au1xxx_dbdma_chan_free(u32 chanid) |
824 | au1xxx_dbdma_chan_free(u32 chanid) | ||
825 | { | 808 | { |
826 | chan_tab_t *ctp; | 809 | chan_tab_t *ctp; |
827 | dbdev_tab_t *stp, *dtp; | 810 | dbdev_tab_t *stp, *dtp; |
@@ -842,8 +825,7 @@ au1xxx_dbdma_chan_free(u32 chanid) | |||
842 | } | 825 | } |
843 | EXPORT_SYMBOL(au1xxx_dbdma_chan_free); | 826 | EXPORT_SYMBOL(au1xxx_dbdma_chan_free); |
844 | 827 | ||
845 | static irqreturn_t | 828 | static irqreturn_t dbdma_interrupt(int irq, void *dev_id) |
846 | dbdma_interrupt(int irq, void *dev_id) | ||
847 | { | 829 | { |
848 | u32 intstat; | 830 | u32 intstat; |
849 | u32 chan_index; | 831 | u32 chan_index; |
@@ -859,13 +841,12 @@ dbdma_interrupt(int irq, void *dev_id) | |||
859 | cp = ctp->chan_ptr; | 841 | cp = ctp->chan_ptr; |
860 | dp = ctp->cur_ptr; | 842 | dp = ctp->cur_ptr; |
861 | 843 | ||
862 | /* Reset interrupt. | 844 | /* Reset interrupt. */ |
863 | */ | ||
864 | cp->ddma_irq = 0; | 845 | cp->ddma_irq = 0; |
865 | au_sync(); | 846 | au_sync(); |
866 | 847 | ||
867 | if (ctp->chan_callback) | 848 | if (ctp->chan_callback) |
868 | (ctp->chan_callback)(irq, ctp->chan_callparam); | 849 | ctp->chan_callback(irq, ctp->chan_callparam); |
869 | 850 | ||
870 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 851 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
871 | return IRQ_RETVAL(1); | 852 | return IRQ_RETVAL(1); |
@@ -890,47 +871,47 @@ static void au1xxx_dbdma_init(void) | |||
890 | 871 | ||
891 | if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, | 872 | if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, |
892 | "Au1xxx dbdma", (void *)dbdma_gptr)) | 873 | "Au1xxx dbdma", (void *)dbdma_gptr)) |
893 | printk("Can't get 1550 dbdma irq"); | 874 | printk(KERN_ERR "Can't get 1550 dbdma irq"); |
894 | } | 875 | } |
895 | 876 | ||
896 | void | 877 | void au1xxx_dbdma_dump(u32 chanid) |
897 | au1xxx_dbdma_dump(u32 chanid) | ||
898 | { | 878 | { |
899 | chan_tab_t *ctp; | 879 | chan_tab_t *ctp; |
900 | au1x_ddma_desc_t *dp; | 880 | au1x_ddma_desc_t *dp; |
901 | dbdev_tab_t *stp, *dtp; | 881 | dbdev_tab_t *stp, *dtp; |
902 | au1x_dma_chan_t *cp; | 882 | au1x_dma_chan_t *cp; |
903 | u32 i = 0; | 883 | u32 i = 0; |
904 | 884 | ||
905 | ctp = *((chan_tab_t **)chanid); | 885 | ctp = *((chan_tab_t **)chanid); |
906 | stp = ctp->chan_src; | 886 | stp = ctp->chan_src; |
907 | dtp = ctp->chan_dest; | 887 | dtp = ctp->chan_dest; |
908 | cp = ctp->chan_ptr; | 888 | cp = ctp->chan_ptr; |
909 | 889 | ||
910 | printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", | 890 | printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", |
911 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab); | 891 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, |
912 | printk("desc base %x, get %x, put %x, cur %x\n", | 892 | dtp - dbdev_tab); |
913 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), | 893 | printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", |
914 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | 894 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), |
915 | 895 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | |
916 | printk("dbdma chan %x\n", (u32)cp); | 896 | |
917 | printk("cfg %08x, desptr %08x, statptr %08x\n", | 897 | printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp); |
918 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); | 898 | printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n", |
919 | printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", | 899 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); |
920 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt); | 900 | printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", |
921 | 901 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, | |
922 | 902 | cp->ddma_bytecnt); | |
923 | /* Run through the descriptors | 903 | |
924 | */ | 904 | /* Run through the descriptors */ |
925 | dp = ctp->chan_desc_base; | 905 | dp = ctp->chan_desc_base; |
926 | 906 | ||
927 | do { | 907 | do { |
928 | printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", | 908 | printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", |
929 | i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); | 909 | i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); |
930 | printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", | 910 | printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", |
931 | dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); | 911 | dp->dscr_source0, dp->dscr_source1, |
932 | printk("stat %08x, nxtptr %08x\n", | 912 | dp->dscr_dest0, dp->dscr_dest1); |
933 | dp->dscr_stat, dp->dscr_nxtptr); | 913 | printk(KERN_DEBUG "stat %08x, nxtptr %08x\n", |
914 | dp->dscr_stat, dp->dscr_nxtptr); | ||
934 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 915 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
935 | } while (dp != ctp->chan_desc_base); | 916 | } while (dp != ctp->chan_desc_base); |
936 | } | 917 | } |
@@ -938,32 +919,33 @@ au1xxx_dbdma_dump(u32 chanid) | |||
938 | /* Put a descriptor into the DMA ring. | 919 | /* Put a descriptor into the DMA ring. |
939 | * This updates the source/destination pointers and byte count. | 920 | * This updates the source/destination pointers and byte count. |
940 | */ | 921 | */ |
941 | u32 | 922 | u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) |
942 | au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) | ||
943 | { | 923 | { |
944 | chan_tab_t *ctp; | 924 | chan_tab_t *ctp; |
945 | au1x_ddma_desc_t *dp; | 925 | au1x_ddma_desc_t *dp; |
946 | u32 nbytes=0; | 926 | u32 nbytes = 0; |
947 | 927 | ||
948 | /* I guess we could check this to be within the | 928 | /* |
949 | * range of the table...... | 929 | * I guess we could check this to be within the |
950 | */ | 930 | * range of the table...... |
931 | */ | ||
951 | ctp = *((chan_tab_t **)chanid); | 932 | ctp = *((chan_tab_t **)chanid); |
952 | 933 | ||
953 | /* We should have multiple callers for a particular channel, | 934 | /* |
954 | * an interrupt doesn't affect this pointer nor the descriptor, | 935 | * We should have multiple callers for a particular channel, |
955 | * so no locking should be needed. | 936 | * an interrupt doesn't affect this pointer nor the descriptor, |
956 | */ | 937 | * so no locking should be needed. |
938 | */ | ||
957 | dp = ctp->put_ptr; | 939 | dp = ctp->put_ptr; |
958 | 940 | ||
959 | /* If the descriptor is valid, we are way ahead of the DMA | 941 | /* |
960 | * engine, so just return an error condition. | 942 | * If the descriptor is valid, we are way ahead of the DMA |
961 | */ | 943 | * engine, so just return an error condition. |
944 | */ | ||
962 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | 945 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
963 | return 0; | 946 | return 0; |
964 | 947 | ||
965 | /* Load up buffer addresses and byte count. | 948 | /* Load up buffer addresses and byte count. */ |
966 | */ | ||
967 | dp->dscr_dest0 = dscr->dscr_dest0; | 949 | dp->dscr_dest0 = dscr->dscr_dest0; |
968 | dp->dscr_source0 = dscr->dscr_source0; | 950 | dp->dscr_source0 = dscr->dscr_source0; |
969 | dp->dscr_dest1 = dscr->dscr_dest1; | 951 | dp->dscr_dest1 = dscr->dscr_dest1; |
@@ -975,14 +957,11 @@ au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) | |||
975 | dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; | 957 | dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; |
976 | ctp->chan_ptr->ddma_dbell = 0; | 958 | ctp->chan_ptr->ddma_dbell = 0; |
977 | 959 | ||
978 | /* Get next descriptor pointer. | 960 | /* Get next descriptor pointer. */ |
979 | */ | ||
980 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | 961 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
981 | 962 | ||
982 | /* return something not zero. | 963 | /* Return something non-zero. */ |
983 | */ | ||
984 | return nbytes; | 964 | return nbytes; |
985 | } | 965 | } |
986 | 966 | ||
987 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ | 967 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |
988 | |||
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c index eae1bb2ca26e..af5be7df2f2a 100644 --- a/arch/mips/au1000/common/dbg_io.c +++ b/arch/mips/au1000/common/dbg_io.c | |||
@@ -1,3 +1,4 @@ | |||
1 | #include <linux/types.h> | ||
1 | 2 | ||
2 | #include <asm/mach-au1x00/au1000.h> | 3 | #include <asm/mach-au1x00/au1000.h> |
3 | 4 | ||
@@ -8,12 +9,6 @@ | |||
8 | * uart to be used for debugging. | 9 | * uart to be used for debugging. |
9 | */ | 10 | */ |
10 | #define DEBUG_BASE UART_DEBUG_BASE | 11 | #define DEBUG_BASE UART_DEBUG_BASE |
11 | /**/ | ||
12 | |||
13 | /* we need uint32 uint8 */ | ||
14 | /* #include "types.h" */ | ||
15 | typedef unsigned char uint8; | ||
16 | typedef unsigned int uint32; | ||
17 | 12 | ||
18 | #define UART16550_BAUD_2400 2400 | 13 | #define UART16550_BAUD_2400 2400 |
19 | #define UART16550_BAUD_4800 4800 | 14 | #define UART16550_BAUD_4800 4800 |
@@ -51,17 +46,15 @@ typedef unsigned int uint32; | |||
51 | #define UART_MOD_CNTRL 0x100 /* Module Control */ | 46 | #define UART_MOD_CNTRL 0x100 /* Module Control */ |
52 | 47 | ||
53 | /* memory-mapped read/write of the port */ | 48 | /* memory-mapped read/write of the port */ |
54 | #define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) | 49 | #define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) |
55 | #define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y)) | 50 | #define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y)) |
56 | 51 | ||
57 | extern unsigned long calc_clock(void); | 52 | extern unsigned long calc_clock(void); |
58 | 53 | ||
59 | void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | 54 | void debugInit(u32 baud, u8 data, u8 parity, u8 stop) |
60 | { | 55 | { |
61 | 56 | if (UART16550_READ(UART_MOD_CNTRL) != 0x3) | |
62 | if (UART16550_READ(UART_MOD_CNTRL) != 0x3) { | ||
63 | UART16550_WRITE(UART_MOD_CNTRL, 3); | 57 | UART16550_WRITE(UART_MOD_CNTRL, 3); |
64 | } | ||
65 | calc_clock(); | 58 | calc_clock(); |
66 | 59 | ||
67 | /* disable interrupts */ | 60 | /* disable interrupts */ |
@@ -69,7 +62,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | |||
69 | 62 | ||
70 | /* set up baud rate */ | 63 | /* set up baud rate */ |
71 | { | 64 | { |
72 | uint32 divisor; | 65 | u32 divisor; |
73 | 66 | ||
74 | /* set divisor */ | 67 | /* set divisor */ |
75 | divisor = get_au1x00_uart_baud_base() / baud; | 68 | divisor = get_au1x00_uart_baud_base() / baud; |
@@ -80,9 +73,9 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | |||
80 | UART16550_WRITE(UART_LCR, (data | parity | stop)); | 73 | UART16550_WRITE(UART_LCR, (data | parity | stop)); |
81 | } | 74 | } |
82 | 75 | ||
83 | static int remoteDebugInitialized = 0; | 76 | static int remoteDebugInitialized; |
84 | 77 | ||
85 | uint8 getDebugChar(void) | 78 | u8 getDebugChar(void) |
86 | { | 79 | { |
87 | if (!remoteDebugInitialized) { | 80 | if (!remoteDebugInitialized) { |
88 | remoteDebugInitialized = 1; | 81 | remoteDebugInitialized = 1; |
@@ -92,15 +85,13 @@ uint8 getDebugChar(void) | |||
92 | UART16550_STOP_1BIT); | 85 | UART16550_STOP_1BIT); |
93 | } | 86 | } |
94 | 87 | ||
95 | while((UART16550_READ(UART_LSR) & 0x1) == 0); | 88 | while ((UART16550_READ(UART_LSR) & 0x1) == 0); |
96 | return UART16550_READ(UART_RX); | 89 | return UART16550_READ(UART_RX); |
97 | } | 90 | } |
98 | 91 | ||
99 | 92 | ||
100 | int putDebugChar(uint8 byte) | 93 | int putDebugChar(u8 byte) |
101 | { | 94 | { |
102 | // int i; | ||
103 | |||
104 | if (!remoteDebugInitialized) { | 95 | if (!remoteDebugInitialized) { |
105 | remoteDebugInitialized = 1; | 96 | remoteDebugInitialized = 1; |
106 | debugInit(UART16550_BAUD_115200, | 97 | debugInit(UART16550_BAUD_115200, |
@@ -109,9 +100,8 @@ int putDebugChar(uint8 byte) | |||
109 | UART16550_STOP_1BIT); | 100 | UART16550_STOP_1BIT); |
110 | } | 101 | } |
111 | 102 | ||
112 | while ((UART16550_READ(UART_LSR)&0x40) == 0); | 103 | while ((UART16550_READ(UART_LSR) & 0x40) == 0); |
113 | UART16550_WRITE(UART_TX, byte); | 104 | UART16550_WRITE(UART_TX, byte); |
114 | //for (i=0;i<0xfff;i++); | ||
115 | 105 | ||
116 | return 1; | 106 | return 1; |
117 | } | 107 | } |
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/au1000/common/dma.c index 95f69ea146e9..d6fbda232e6a 100644 --- a/arch/mips/au1000/common/dma.c +++ b/arch/mips/au1000/common/dma.c | |||
@@ -1,12 +1,11 @@ | |||
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * BRIEF MODULE DESCRIPTION | 3 | * BRIEF MODULE DESCRIPTION |
4 | * A DMA channel allocator for Au1000. API is modeled loosely off of | 4 | * A DMA channel allocator for Au1x00. API is modeled loosely off of |
5 | * linux/kernel/dma.c. | 5 | * linux/kernel/dma.c. |
6 | * | 6 | * |
7 | * Copyright 2000 MontaVista Software Inc. | 7 | * Copyright 2000, 2008 MontaVista Software Inc. |
8 | * Author: MontaVista Software, Inc. | 8 | * Author: MontaVista Software, Inc. <source@mvista.com> |
9 | * stevel@mvista.com or source@mvista.com | ||
10 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) | 9 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) |
11 | * | 10 | * |
12 | * This program is free software; you can redistribute it and/or modify it | 11 | * This program is free software; you can redistribute it and/or modify it |
@@ -39,7 +38,8 @@ | |||
39 | #include <asm/mach-au1x00/au1000.h> | 38 | #include <asm/mach-au1x00/au1000.h> |
40 | #include <asm/mach-au1x00/au1000_dma.h> | 39 | #include <asm/mach-au1x00/au1000_dma.h> |
41 | 40 | ||
42 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) | 41 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ |
42 | defined(CONFIG_SOC_AU1100) | ||
43 | /* | 43 | /* |
44 | * A note on resource allocation: | 44 | * A note on resource allocation: |
45 | * | 45 | * |
@@ -56,7 +56,6 @@ | |||
56 | * returned from request_dma. | 56 | * returned from request_dma. |
57 | */ | 57 | */ |
58 | 58 | ||
59 | |||
60 | DEFINE_SPINLOCK(au1000_dma_spin_lock); | 59 | DEFINE_SPINLOCK(au1000_dma_spin_lock); |
61 | 60 | ||
62 | struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { | 61 | struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { |
@@ -71,7 +70,7 @@ struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { | |||
71 | }; | 70 | }; |
72 | EXPORT_SYMBOL(au1000_dma_table); | 71 | EXPORT_SYMBOL(au1000_dma_table); |
73 | 72 | ||
74 | // Device FIFO addresses and default DMA modes | 73 | /* Device FIFO addresses and default DMA modes */ |
75 | static const struct dma_dev { | 74 | static const struct dma_dev { |
76 | unsigned int fifo_addr; | 75 | unsigned int fifo_addr; |
77 | unsigned int dma_mode; | 76 | unsigned int dma_mode; |
@@ -80,8 +79,8 @@ static const struct dma_dev { | |||
80 | {UART0_ADDR + UART_RX, 0}, | 79 | {UART0_ADDR + UART_RX, 0}, |
81 | {0, 0}, | 80 | {0, 0}, |
82 | {0, 0}, | 81 | {0, 0}, |
83 | {AC97C_DATA, DMA_DW16 }, // coherent | 82 | {AC97C_DATA, DMA_DW16 }, /* coherent */ |
84 | {AC97C_DATA, DMA_DR | DMA_DW16 }, // coherent | 83 | {AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */ |
85 | {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, | 84 | {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, |
86 | {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, | 85 | {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, |
87 | {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, | 86 | {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, |
@@ -101,10 +100,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos, | |||
101 | struct dma_chan *chan; | 100 | struct dma_chan *chan; |
102 | 101 | ||
103 | for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) { | 102 | for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) { |
104 | if ((chan = get_dma_chan(i)) != NULL) { | 103 | chan = get_dma_chan(i); |
104 | if (chan != NULL) | ||
105 | len += sprintf(buf + len, "%2d: %s\n", | 105 | len += sprintf(buf + len, "%2d: %s\n", |
106 | i, chan->dev_str); | 106 | i, chan->dev_str); |
107 | } | ||
108 | } | 107 | } |
109 | 108 | ||
110 | if (fpos >= len) { | 109 | if (fpos >= len) { |
@@ -113,18 +112,19 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos, | |||
113 | return 0; | 112 | return 0; |
114 | } | 113 | } |
115 | *start = buf + fpos; | 114 | *start = buf + fpos; |
116 | if ((len -= fpos) > length) | 115 | len -= fpos; |
116 | if (len > length) | ||
117 | return length; | 117 | return length; |
118 | *eof = 1; | 118 | *eof = 1; |
119 | return len; | 119 | return len; |
120 | } | 120 | } |
121 | 121 | ||
122 | // Device FIFO addresses and default DMA modes - 2nd bank | 122 | /* Device FIFO addresses and default DMA modes - 2nd bank */ |
123 | static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = { | 123 | static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = { |
124 | {SD0_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent | 124 | { SD0_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ |
125 | {SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8}, // coherent | 125 | { SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }, /* coherent */ |
126 | {SD1_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent | 126 | { SD1_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ |
127 | {SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8} // coherent | 127 | { SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 } /* coherent */ |
128 | }; | 128 | }; |
129 | 129 | ||
130 | void dump_au1000_dma_channel(unsigned int dmanr) | 130 | void dump_au1000_dma_channel(unsigned int dmanr) |
@@ -150,7 +150,6 @@ void dump_au1000_dma_channel(unsigned int dmanr) | |||
150 | au_readl(chan->io + DMA_BUFFER1_COUNT)); | 150 | au_readl(chan->io + DMA_BUFFER1_COUNT)); |
151 | } | 151 | } |
152 | 152 | ||
153 | |||
154 | /* | 153 | /* |
155 | * Finds a free channel, and binds the requested device to it. | 154 | * Finds a free channel, and binds the requested device to it. |
156 | * Returns the allocated channel number, or negative on error. | 155 | * Returns the allocated channel number, or negative on error. |
@@ -169,14 +168,14 @@ int request_au1000_dma(int dev_id, const char *dev_str, | |||
169 | if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) | 168 | if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) |
170 | return -EINVAL; | 169 | return -EINVAL; |
171 | #else | 170 | #else |
172 | if (dev_id < 0 || dev_id >= DMA_NUM_DEV) | 171 | if (dev_id < 0 || dev_id >= DMA_NUM_DEV) |
173 | return -EINVAL; | 172 | return -EINVAL; |
174 | #endif | 173 | #endif |
175 | 174 | ||
176 | for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) { | 175 | for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) |
177 | if (au1000_dma_table[i].dev_id < 0) | 176 | if (au1000_dma_table[i].dev_id < 0) |
178 | break; | 177 | break; |
179 | } | 178 | |
180 | if (i == NUM_AU1000_DMA_CHANNELS) | 179 | if (i == NUM_AU1000_DMA_CHANNELS) |
181 | return -ENODEV; | 180 | return -ENODEV; |
182 | 181 | ||
@@ -185,15 +184,15 @@ int request_au1000_dma(int dev_id, const char *dev_str, | |||
185 | if (dev_id >= DMA_NUM_DEV) { | 184 | if (dev_id >= DMA_NUM_DEV) { |
186 | dev_id -= DMA_NUM_DEV; | 185 | dev_id -= DMA_NUM_DEV; |
187 | dev = &dma_dev_table_bank2[dev_id]; | 186 | dev = &dma_dev_table_bank2[dev_id]; |
188 | } else { | 187 | } else |
189 | dev = &dma_dev_table[dev_id]; | 188 | dev = &dma_dev_table[dev_id]; |
190 | } | ||
191 | 189 | ||
192 | if (irqhandler) { | 190 | if (irqhandler) { |
193 | chan->irq = AU1000_DMA_INT_BASE + i; | 191 | chan->irq = AU1000_DMA_INT_BASE + i; |
194 | chan->irq_dev = irq_dev_id; | 192 | chan->irq_dev = irq_dev_id; |
195 | if ((ret = request_irq(chan->irq, irqhandler, irqflags, | 193 | ret = request_irq(chan->irq, irqhandler, irqflags, dev_str, |
196 | dev_str, chan->irq_dev))) { | 194 | chan->irq_dev); |
195 | if (ret) { | ||
197 | chan->irq = 0; | 196 | chan->irq = 0; |
198 | chan->irq_dev = NULL; | 197 | chan->irq_dev = NULL; |
199 | return ret; | 198 | return ret; |
@@ -203,7 +202,7 @@ int request_au1000_dma(int dev_id, const char *dev_str, | |||
203 | chan->irq_dev = NULL; | 202 | chan->irq_dev = NULL; |
204 | } | 203 | } |
205 | 204 | ||
206 | // fill it in | 205 | /* fill it in */ |
207 | chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; | 206 | chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; |
208 | chan->dev_id = dev_id; | 207 | chan->dev_id = dev_id; |
209 | chan->dev_str = dev_str; | 208 | chan->dev_str = dev_str; |
@@ -220,8 +219,9 @@ EXPORT_SYMBOL(request_au1000_dma); | |||
220 | void free_au1000_dma(unsigned int dmanr) | 219 | void free_au1000_dma(unsigned int dmanr) |
221 | { | 220 | { |
222 | struct dma_chan *chan = get_dma_chan(dmanr); | 221 | struct dma_chan *chan = get_dma_chan(dmanr); |
222 | |||
223 | if (!chan) { | 223 | if (!chan) { |
224 | printk("Trying to free DMA%d\n", dmanr); | 224 | printk(KERN_ERR "Error trying to free DMA%d\n", dmanr); |
225 | return; | 225 | return; |
226 | } | 226 | } |
227 | 227 | ||
@@ -235,4 +235,4 @@ void free_au1000_dma(unsigned int dmanr) | |||
235 | } | 235 | } |
236 | EXPORT_SYMBOL(free_au1000_dma); | 236 | EXPORT_SYMBOL(free_au1000_dma); |
237 | 237 | ||
238 | #endif // AU1000 AU1500 AU1100 | 238 | #endif /* AU1000 AU1500 AU1100 */ |
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c index 525452589971..b485d94ce8a5 100644 --- a/arch/mips/au1000/common/gpio.c +++ b/arch/mips/au1000/common/gpio.c | |||
@@ -69,7 +69,7 @@ static int au1xxx_gpio2_direction_output(unsigned gpio, int value) | |||
69 | 69 | ||
70 | static int au1xxx_gpio1_read(unsigned gpio) | 70 | static int au1xxx_gpio1_read(unsigned gpio) |
71 | { | 71 | { |
72 | return ((gpio1->pinstaterd >> gpio) & 0x01); | 72 | return (gpio1->pinstaterd >> gpio) & 0x01; |
73 | } | 73 | } |
74 | 74 | ||
75 | static void au1xxx_gpio1_write(unsigned gpio, int value) | 75 | static void au1xxx_gpio1_write(unsigned gpio, int value) |
@@ -104,7 +104,6 @@ int au1xxx_gpio_get_value(unsigned gpio) | |||
104 | else | 104 | else |
105 | return au1xxx_gpio1_read(gpio); | 105 | return au1xxx_gpio1_read(gpio); |
106 | } | 106 | } |
107 | |||
108 | EXPORT_SYMBOL(au1xxx_gpio_get_value); | 107 | EXPORT_SYMBOL(au1xxx_gpio_get_value); |
109 | 108 | ||
110 | void au1xxx_gpio_set_value(unsigned gpio, int value) | 109 | void au1xxx_gpio_set_value(unsigned gpio, int value) |
@@ -118,7 +117,6 @@ void au1xxx_gpio_set_value(unsigned gpio, int value) | |||
118 | else | 117 | else |
119 | au1xxx_gpio1_write(gpio, value); | 118 | au1xxx_gpio1_write(gpio, value); |
120 | } | 119 | } |
121 | |||
122 | EXPORT_SYMBOL(au1xxx_gpio_set_value); | 120 | EXPORT_SYMBOL(au1xxx_gpio_set_value); |
123 | 121 | ||
124 | int au1xxx_gpio_direction_input(unsigned gpio) | 122 | int au1xxx_gpio_direction_input(unsigned gpio) |
@@ -132,7 +130,6 @@ int au1xxx_gpio_direction_input(unsigned gpio) | |||
132 | 130 | ||
133 | return au1xxx_gpio1_direction_input(gpio); | 131 | return au1xxx_gpio1_direction_input(gpio); |
134 | } | 132 | } |
135 | |||
136 | EXPORT_SYMBOL(au1xxx_gpio_direction_input); | 133 | EXPORT_SYMBOL(au1xxx_gpio_direction_input); |
137 | 134 | ||
138 | int au1xxx_gpio_direction_output(unsigned gpio, int value) | 135 | int au1xxx_gpio_direction_output(unsigned gpio, int value) |
@@ -146,5 +143,4 @@ int au1xxx_gpio_direction_output(unsigned gpio, int value) | |||
146 | 143 | ||
147 | return au1xxx_gpio1_direction_output(gpio, value); | 144 | return au1xxx_gpio1_direction_output(gpio, value); |
148 | } | 145 | } |
149 | |||
150 | EXPORT_SYMBOL(au1xxx_gpio_direction_output); | 146 | EXPORT_SYMBOL(au1xxx_gpio_direction_output); |
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index f0626992fd75..40c6ceceb5f9 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c | |||
@@ -210,10 +210,8 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) | |||
210 | au_sync(); | 210 | au_sync(); |
211 | } | 211 | } |
212 | 212 | ||
213 | |||
214 | static inline void mask_and_ack_level_irq(unsigned int irq_nr) | 213 | static inline void mask_and_ack_level_irq(unsigned int irq_nr) |
215 | { | 214 | { |
216 | |||
217 | local_disable_irq(irq_nr); | 215 | local_disable_irq(irq_nr); |
218 | au_sync(); | 216 | au_sync(); |
219 | #if defined(CONFIG_MIPS_PB1000) | 217 | #if defined(CONFIG_MIPS_PB1000) |
@@ -263,14 +261,14 @@ void restore_local_and_enable(int controller, unsigned long mask) | |||
263 | unsigned long flags, new_mask; | 261 | unsigned long flags, new_mask; |
264 | 262 | ||
265 | spin_lock_irqsave(&irq_lock, flags); | 263 | spin_lock_irqsave(&irq_lock, flags); |
266 | for (i = 0; i < 32; i++) { | 264 | for (i = 0; i < 32; i++) |
267 | if (mask & (1 << i)) { | 265 | if (mask & (1 << i)) { |
268 | if (controller) | 266 | if (controller) |
269 | local_enable_irq(i + 32); | 267 | local_enable_irq(i + 32); |
270 | else | 268 | else |
271 | local_enable_irq(i); | 269 | local_enable_irq(i); |
272 | } | 270 | } |
273 | } | 271 | |
274 | if (controller) | 272 | if (controller) |
275 | new_mask = au_readl(IC1_MASKSET); | 273 | new_mask = au_readl(IC1_MASKSET); |
276 | else | 274 | else |
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 7e966b31e3e1..7866cf50cf99 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c | |||
@@ -2,9 +2,8 @@ | |||
2 | * BRIEF MODULE DESCRIPTION | 2 | * BRIEF MODULE DESCRIPTION |
3 | * Alchemy/AMD Au1x00 PCI support. | 3 | * Alchemy/AMD Au1x00 PCI support. |
4 | * | 4 | * |
5 | * Copyright 2001-2003, 2007 MontaVista Software Inc. | 5 | * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. | 6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | * ppopov@mvista.com or source@mvista.com | ||
8 | * | 7 | * |
9 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | 8 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) |
10 | * | 9 | * |
@@ -86,9 +85,9 @@ static int __init au1x_pci_setup(void) | |||
86 | u32 prid = read_c0_prid(); | 85 | u32 prid = read_c0_prid(); |
87 | 86 | ||
88 | if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { | 87 | if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { |
89 | au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), | 88 | au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), |
90 | Au1500_PCI_CFG); | 89 | Au1500_PCI_CFG); |
91 | printk("Non-coherent PCI accesses enabled\n"); | 90 | printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); |
92 | } | 91 | } |
93 | } | 92 | } |
94 | #endif | 93 | #endif |
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index dbefa9ef63b5..8cae7753ef79 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c | |||
@@ -302,16 +302,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { | |||
302 | #endif | 302 | #endif |
303 | }; | 303 | }; |
304 | 304 | ||
305 | int __init au1xxx_platform_init(void) | 305 | static int __init au1xxx_platform_init(void) |
306 | { | 306 | { |
307 | unsigned int uartclk = get_au1x00_uart_baud_base() * 16; | 307 | unsigned int uartclk = get_au1x00_uart_baud_base() * 16; |
308 | int i; | 308 | int i; |
309 | 309 | ||
310 | /* Fill up uartclk. */ | 310 | /* Fill up uartclk. */ |
311 | for (i = 0; au1x00_uart_data[i].flags ; i++) | 311 | for (i = 0; au1x00_uart_data[i].flags; i++) |
312 | au1x00_uart_data[i].uartclk = uartclk; | 312 | au1x00_uart_data[i].uartclk = uartclk; |
313 | 313 | ||
314 | return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); | 314 | return platform_add_devices(au1xxx_platform_devices, |
315 | ARRAY_SIZE(au1xxx_platform_devices)); | ||
315 | } | 316 | } |
316 | 317 | ||
317 | arch_initcall(au1xxx_platform_init); | 318 | arch_initcall(au1xxx_platform_init); |
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index a8cd2c1b9e1b..2166b9e1e80c 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c | |||
@@ -1,10 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * BRIEF MODULE DESCRIPTION | 2 | * BRIEF MODULE DESCRIPTION |
3 | * Au1000 Power Management routines. | 3 | * Au1xx0 Power Management routines. |
4 | * | 4 | * |
5 | * Copyright 2001 MontaVista Software Inc. | 5 | * Copyright 2001, 2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. | 6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | * ppopov@mvista.com or source@mvista.com | ||
8 | * | 7 | * |
9 | * Some of the routines are right out of init/main.c, whose | 8 | * Some of the routines are right out of init/main.c, whose |
10 | * copyrights apply here. | 9 | * copyrights apply here. |
@@ -43,10 +42,10 @@ | |||
43 | #ifdef CONFIG_PM | 42 | #ifdef CONFIG_PM |
44 | 43 | ||
45 | #define DEBUG 1 | 44 | #define DEBUG 1 |
46 | #ifdef DEBUG | 45 | #ifdef DEBUG |
47 | # define DPRINTK(fmt, args...) printk("%s: " fmt, __func__, ## args) | 46 | #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args) |
48 | #else | 47 | #else |
49 | # define DPRINTK(fmt, args...) | 48 | #define DPRINTK(fmt, args...) |
50 | #endif | 49 | #endif |
51 | 50 | ||
52 | static void au1000_calibrate_delay(void); | 51 | static void au1000_calibrate_delay(void); |
@@ -57,7 +56,8 @@ extern void local_enable_irq(unsigned int irq_nr); | |||
57 | 56 | ||
58 | static DEFINE_SPINLOCK(pm_lock); | 57 | static DEFINE_SPINLOCK(pm_lock); |
59 | 58 | ||
60 | /* We need to save/restore a bunch of core registers that are | 59 | /* |
60 | * We need to save/restore a bunch of core registers that are | ||
61 | * either volatile or reset to some state across a processor sleep. | 61 | * either volatile or reset to some state across a processor sleep. |
62 | * If reading a register doesn't provide a proper result for a | 62 | * If reading a register doesn't provide a proper result for a |
63 | * later restore, we have to provide a function for loading that | 63 | * later restore, we have to provide a function for loading that |
@@ -78,24 +78,25 @@ static unsigned int sleep_usbhost_enable; | |||
78 | static unsigned int sleep_usbdev_enable; | 78 | static unsigned int sleep_usbdev_enable; |
79 | static unsigned int sleep_static_memctlr[4][3]; | 79 | static unsigned int sleep_static_memctlr[4][3]; |
80 | 80 | ||
81 | /* Define this to cause the value you write to /proc/sys/pm/sleep to | 81 | /* |
82 | * Define this to cause the value you write to /proc/sys/pm/sleep to | ||
82 | * set the TOY timer for the amount of time you want to sleep. | 83 | * set the TOY timer for the amount of time you want to sleep. |
83 | * This is done mainly for testing, but may be useful in other cases. | 84 | * This is done mainly for testing, but may be useful in other cases. |
84 | * The value is number of 32KHz ticks to sleep. | 85 | * The value is number of 32KHz ticks to sleep. |
85 | */ | 86 | */ |
86 | #define SLEEP_TEST_TIMEOUT 1 | 87 | #define SLEEP_TEST_TIMEOUT 1 |
87 | #ifdef SLEEP_TEST_TIMEOUT | 88 | #ifdef SLEEP_TEST_TIMEOUT |
88 | static int sleep_ticks; | 89 | static int sleep_ticks; |
89 | void wakeup_counter0_set(int ticks); | 90 | void wakeup_counter0_set(int ticks); |
90 | #endif | 91 | #endif |
91 | 92 | ||
92 | static void | 93 | static void save_core_regs(void) |
93 | save_core_regs(void) | ||
94 | { | 94 | { |
95 | extern void save_au1xxx_intctl(void); | 95 | extern void save_au1xxx_intctl(void); |
96 | extern void pm_eth0_shutdown(void); | 96 | extern void pm_eth0_shutdown(void); |
97 | 97 | ||
98 | /* Do the serial ports.....these really should be a pm_* | 98 | /* |
99 | * Do the serial ports.....these really should be a pm_* | ||
99 | * registered function by the driver......but of course the | 100 | * registered function by the driver......but of course the |
100 | * standard serial driver doesn't understand our Au1xxx | 101 | * standard serial driver doesn't understand our Au1xxx |
101 | * unique registers. | 102 | * unique registers. |
@@ -106,27 +107,24 @@ save_core_regs(void) | |||
106 | sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); | 107 | sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); |
107 | sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); | 108 | sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); |
108 | 109 | ||
109 | /* Shutdown USB host/device. | 110 | /* Shutdown USB host/device. */ |
110 | */ | ||
111 | sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); | 111 | sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); |
112 | 112 | ||
113 | /* There appears to be some undocumented reset register.... | 113 | /* There appears to be some undocumented reset register.... */ |
114 | */ | ||
115 | au_writel(0, 0xb0100004); au_sync(); | 114 | au_writel(0, 0xb0100004); au_sync(); |
116 | au_writel(0, USB_HOST_CONFIG); au_sync(); | 115 | au_writel(0, USB_HOST_CONFIG); au_sync(); |
117 | 116 | ||
118 | sleep_usbdev_enable = au_readl(USBD_ENABLE); | 117 | sleep_usbdev_enable = au_readl(USBD_ENABLE); |
119 | au_writel(0, USBD_ENABLE); au_sync(); | 118 | au_writel(0, USBD_ENABLE); au_sync(); |
120 | 119 | ||
121 | /* Save interrupt controller state. | 120 | /* Save interrupt controller state. */ |
122 | */ | ||
123 | save_au1xxx_intctl(); | 121 | save_au1xxx_intctl(); |
124 | 122 | ||
125 | /* Clocks and PLLs. | 123 | /* Clocks and PLLs. */ |
126 | */ | ||
127 | sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); | 124 | sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); |
128 | 125 | ||
129 | /* We don't really need to do this one, but unless we | 126 | /* |
127 | * We don't really need to do this one, but unless we | ||
130 | * write it again it won't have a valid value if we | 128 | * write it again it won't have a valid value if we |
131 | * happen to read it. | 129 | * happen to read it. |
132 | */ | 130 | */ |
@@ -134,8 +132,7 @@ save_core_regs(void) | |||
134 | 132 | ||
135 | sleep_pin_function = au_readl(SYS_PINFUNC); | 133 | sleep_pin_function = au_readl(SYS_PINFUNC); |
136 | 134 | ||
137 | /* Save the static memory controller configuration. | 135 | /* Save the static memory controller configuration. */ |
138 | */ | ||
139 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); | 136 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); |
140 | sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); | 137 | sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); |
141 | sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); | 138 | sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); |
@@ -150,8 +147,7 @@ save_core_regs(void) | |||
150 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); | 147 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); |
151 | } | 148 | } |
152 | 149 | ||
153 | static void | 150 | static void restore_core_regs(void) |
154 | restore_core_regs(void) | ||
155 | { | 151 | { |
156 | extern void restore_au1xxx_intctl(void); | 152 | extern void restore_au1xxx_intctl(void); |
157 | extern void wakeup_counter0_adjust(void); | 153 | extern void wakeup_counter0_adjust(void); |
@@ -160,8 +156,7 @@ restore_core_regs(void) | |||
160 | au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); | 156 | au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); |
161 | au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); | 157 | au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); |
162 | 158 | ||
163 | /* Restore the static memory controller configuration. | 159 | /* Restore the static memory controller configuration. */ |
164 | */ | ||
165 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); | 160 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); |
166 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); | 161 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); |
167 | au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); | 162 | au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); |
@@ -175,7 +170,8 @@ restore_core_regs(void) | |||
175 | au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); | 170 | au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); |
176 | au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); | 171 | au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); |
177 | 172 | ||
178 | /* Enable the UART if it was enabled before sleep. | 173 | /* |
174 | * Enable the UART if it was enabled before sleep. | ||
179 | * I guess I should define module control bits........ | 175 | * I guess I should define module control bits........ |
180 | */ | 176 | */ |
181 | if (sleep_uart0_enable & 0x02) { | 177 | if (sleep_uart0_enable & 0x02) { |
@@ -202,7 +198,7 @@ void wakeup_from_suspend(void) | |||
202 | int au_sleep(void) | 198 | int au_sleep(void) |
203 | { | 199 | { |
204 | unsigned long wakeup, flags; | 200 | unsigned long wakeup, flags; |
205 | extern void save_and_sleep(void); | 201 | extern void save_and_sleep(void); |
206 | 202 | ||
207 | spin_lock_irqsave(&pm_lock, flags); | 203 | spin_lock_irqsave(&pm_lock, flags); |
208 | 204 | ||
@@ -210,23 +206,22 @@ int au_sleep(void) | |||
210 | 206 | ||
211 | flush_cache_all(); | 207 | flush_cache_all(); |
212 | 208 | ||
213 | /** The code below is all system dependent and we should probably | 209 | /** |
210 | ** The code below is all system dependent and we should probably | ||
214 | ** have a function call out of here to set this up. You need | 211 | ** have a function call out of here to set this up. You need |
215 | ** to configure the GPIO or timer interrupts that will bring | 212 | ** to configure the GPIO or timer interrupts that will bring |
216 | ** you out of sleep. | 213 | ** you out of sleep. |
217 | ** For testing, the TOY counter wakeup is useful. | 214 | ** For testing, the TOY counter wakeup is useful. |
218 | **/ | 215 | **/ |
219 | |||
220 | #if 0 | 216 | #if 0 |
221 | au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); | 217 | au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); |
222 | 218 | ||
223 | /* gpio 6 can cause a wake up event */ | 219 | /* GPIO 6 can cause a wake up event */ |
224 | wakeup = au_readl(SYS_WAKEMSK); | 220 | wakeup = au_readl(SYS_WAKEMSK); |
225 | wakeup &= ~(1 << 8); /* turn off match20 wakeup */ | 221 | wakeup &= ~(1 << 8); /* turn off match20 wakeup */ |
226 | wakeup |= 1 << 6; /* turn on gpio 6 wakeup */ | 222 | wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ |
227 | #else | 223 | #else |
228 | /* For testing, allow match20 to wake us up. | 224 | /* For testing, allow match20 to wake us up. */ |
229 | */ | ||
230 | #ifdef SLEEP_TEST_TIMEOUT | 225 | #ifdef SLEEP_TEST_TIMEOUT |
231 | wakeup_counter0_set(sleep_ticks); | 226 | wakeup_counter0_set(sleep_ticks); |
232 | #endif | 227 | #endif |
@@ -240,7 +235,8 @@ int au_sleep(void) | |||
240 | 235 | ||
241 | save_and_sleep(); | 236 | save_and_sleep(); |
242 | 237 | ||
243 | /* after a wakeup, the cpu vectors back to 0x1fc00000 so | 238 | /* |
239 | * After a wakeup, the cpu vectors back to 0x1fc00000, so | ||
244 | * it's up to the boot code to get us back here. | 240 | * it's up to the boot code to get us back here. |
245 | */ | 241 | */ |
246 | restore_core_regs(); | 242 | restore_core_regs(); |
@@ -248,24 +244,22 @@ int au_sleep(void) | |||
248 | return 0; | 244 | return 0; |
249 | } | 245 | } |
250 | 246 | ||
251 | static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, | 247 | static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, |
252 | void __user *buffer, size_t * len, loff_t *ppos) | 248 | void __user *buffer, size_t *len, loff_t *ppos) |
253 | { | 249 | { |
254 | #ifdef SLEEP_TEST_TIMEOUT | 250 | #ifdef SLEEP_TEST_TIMEOUT |
255 | #define TMPBUFLEN2 16 | 251 | #define TMPBUFLEN2 16 |
256 | char buf[TMPBUFLEN2], *p; | 252 | char buf[TMPBUFLEN2], *p; |
257 | #endif | 253 | #endif |
258 | 254 | ||
259 | if (!write) { | 255 | if (!write) |
260 | *len = 0; | 256 | *len = 0; |
261 | } else { | 257 | else { |
262 | #ifdef SLEEP_TEST_TIMEOUT | 258 | #ifdef SLEEP_TEST_TIMEOUT |
263 | if (*len > TMPBUFLEN2 - 1) { | 259 | if (*len > TMPBUFLEN2 - 1) |
264 | return -EFAULT; | 260 | return -EFAULT; |
265 | } | 261 | if (copy_from_user(buf, buffer, *len)) |
266 | if (copy_from_user(buf, buffer, *len)) { | ||
267 | return -EFAULT; | 262 | return -EFAULT; |
268 | } | ||
269 | buf[*len] = 0; | 263 | buf[*len] = 0; |
270 | p = buf; | 264 | p = buf; |
271 | sleep_ticks = simple_strtoul(p, &p, 0); | 265 | sleep_ticks = simple_strtoul(p, &p, 0); |
@@ -276,8 +270,8 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, | |||
276 | return 0; | 270 | return 0; |
277 | } | 271 | } |
278 | 272 | ||
279 | static int pm_do_freq(ctl_table * ctl, int write, struct file *file, | 273 | static int pm_do_freq(ctl_table *ctl, int write, struct file *file, |
280 | void __user *buffer, size_t * len, loff_t *ppos) | 274 | void __user *buffer, size_t *len, loff_t *ppos) |
281 | { | 275 | { |
282 | int retval = 0, i; | 276 | int retval = 0, i; |
283 | unsigned long val, pll; | 277 | unsigned long val, pll; |
@@ -285,14 +279,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file, | |||
285 | #define MAX_CPU_FREQ 396 | 279 | #define MAX_CPU_FREQ 396 |
286 | char buf[TMPBUFLEN], *p; | 280 | char buf[TMPBUFLEN], *p; |
287 | unsigned long flags, intc0_mask, intc1_mask; | 281 | unsigned long flags, intc0_mask, intc1_mask; |
288 | unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk, | 282 | unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; |
289 | old_refresh; | ||
290 | unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; | 283 | unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; |
284 | unsigned long baud_rate; | ||
291 | 285 | ||
292 | spin_lock_irqsave(&pm_lock, flags); | 286 | spin_lock_irqsave(&pm_lock, flags); |
293 | if (!write) { | 287 | if (!write) |
294 | *len = 0; | 288 | *len = 0; |
295 | } else { | 289 | else { |
296 | /* Parse the new frequency */ | 290 | /* Parse the new frequency */ |
297 | if (*len > TMPBUFLEN - 1) { | 291 | if (*len > TMPBUFLEN - 1) { |
298 | spin_unlock_irqrestore(&pm_lock, flags); | 292 | spin_unlock_irqrestore(&pm_lock, flags); |
@@ -312,7 +306,7 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file, | |||
312 | 306 | ||
313 | pll = val / 12; | 307 | pll = val / 12; |
314 | if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ | 308 | if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ |
315 | /* revisit this for higher speed cpus */ | 309 | /* Revisit this for higher speed CPUs */ |
316 | spin_unlock_irqrestore(&pm_lock, flags); | 310 | spin_unlock_irqrestore(&pm_lock, flags); |
317 | return -EFAULT; | 311 | return -EFAULT; |
318 | } | 312 | } |
@@ -321,30 +315,28 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file, | |||
321 | old_cpu_freq = get_au1x00_speed(); | 315 | old_cpu_freq = get_au1x00_speed(); |
322 | 316 | ||
323 | new_cpu_freq = pll * 12 * 1000000; | 317 | new_cpu_freq = pll * 12 * 1000000; |
324 | new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); | 318 | new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) |
319 | & 0x03) + 2) * 16)); | ||
325 | set_au1x00_speed(new_cpu_freq); | 320 | set_au1x00_speed(new_cpu_freq); |
326 | set_au1x00_uart_baud_base(new_baud_base); | 321 | set_au1x00_uart_baud_base(new_baud_base); |
327 | 322 | ||
328 | old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; | 323 | old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; |
329 | new_refresh = | 324 | new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | |
330 | ((old_refresh * new_cpu_freq) / | 325 | (au_readl(MEM_SDREFCFG) & ~0x1ffffff); |
331 | old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff); | ||
332 | 326 | ||
333 | au_writel(pll, SYS_CPUPLL); | 327 | au_writel(pll, SYS_CPUPLL); |
334 | au_sync_delay(1); | 328 | au_sync_delay(1); |
335 | au_writel(new_refresh, MEM_SDREFCFG); | 329 | au_writel(new_refresh, MEM_SDREFCFG); |
336 | au_sync_delay(1); | 330 | au_sync_delay(1); |
337 | 331 | ||
338 | for (i = 0; i < 4; i++) { | 332 | for (i = 0; i < 4; i++) |
339 | if (au_readl | 333 | if (au_readl(UART_BASE + UART_MOD_CNTRL + |
340 | (UART_BASE + UART_MOD_CNTRL + | 334 | i * 0x00100000) == 3) { |
341 | i * 0x00100000) == 3) { | 335 | old_clk = au_readl(UART_BASE + UART_CLK + |
342 | old_clk = | 336 | i * 0x00100000); |
343 | au_readl(UART_BASE + UART_CLK + | ||
344 | i * 0x00100000); | ||
345 | // baud_rate = baud_base/clk | ||
346 | baud_rate = old_baud_base / old_clk; | 337 | baud_rate = old_baud_base / old_clk; |
347 | /* we won't get an exact baud rate and the error | 338 | /* |
339 | * We won't get an exact baud rate and the error | ||
348 | * could be significant enough that our new | 340 | * could be significant enough that our new |
349 | * calculation will result in a clock that will | 341 | * calculation will result in a clock that will |
350 | * give us a baud rate that's too far off from | 342 | * give us a baud rate that's too far off from |
@@ -359,18 +351,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file, | |||
359 | else if (baud_rate > 17000) | 351 | else if (baud_rate > 17000) |
360 | baud_rate = 19200; | 352 | baud_rate = 19200; |
361 | else | 353 | else |
362 | (baud_rate = 9600); | 354 | baud_rate = 9600; |
363 | // new_clk = new_baud_base/baud_rate | ||
364 | new_clk = new_baud_base / baud_rate; | 355 | new_clk = new_baud_base / baud_rate; |
365 | au_writel(new_clk, | 356 | au_writel(new_clk, UART_BASE + UART_CLK + |
366 | UART_BASE + UART_CLK + | 357 | i * 0x00100000); |
367 | i * 0x00100000); | ||
368 | au_sync_delay(10); | 358 | au_sync_delay(10); |
369 | } | 359 | } |
370 | } | ||
371 | } | 360 | } |
372 | 361 | ||
373 | |||
374 | /* | 362 | /* |
375 | * We don't want _any_ interrupts other than match20. Otherwise our | 363 | * We don't want _any_ interrupts other than match20. Otherwise our |
376 | * au1000_calibrate_delay() calculation will be off, potentially a lot. | 364 | * au1000_calibrate_delay() calculation will be off, potentially a lot. |
@@ -428,14 +416,15 @@ static int __init pm_init(void) | |||
428 | 416 | ||
429 | __initcall(pm_init); | 417 | __initcall(pm_init); |
430 | 418 | ||
431 | |||
432 | /* | 419 | /* |
433 | * This is right out of init/main.c | 420 | * This is right out of init/main.c |
434 | */ | 421 | */ |
435 | 422 | ||
436 | /* This is the number of bits of precision for the loops_per_jiffy. Each | 423 | /* |
437 | bit takes on average 1.5/HZ seconds. This (like the original) is a little | 424 | * This is the number of bits of precision for the loops_per_jiffy. |
438 | better than 1% */ | 425 | * Each bit takes on average 1.5/HZ seconds. This (like the original) |
426 | * is a little better than 1%. | ||
427 | */ | ||
439 | #define LPS_PREC 8 | 428 | #define LPS_PREC 8 |
440 | 429 | ||
441 | static void au1000_calibrate_delay(void) | 430 | static void au1000_calibrate_delay(void) |
@@ -443,14 +432,14 @@ static void au1000_calibrate_delay(void) | |||
443 | unsigned long ticks, loopbit; | 432 | unsigned long ticks, loopbit; |
444 | int lps_precision = LPS_PREC; | 433 | int lps_precision = LPS_PREC; |
445 | 434 | ||
446 | loops_per_jiffy = (1 << 12); | 435 | loops_per_jiffy = 1 << 12; |
447 | 436 | ||
448 | while (loops_per_jiffy <<= 1) { | 437 | while (loops_per_jiffy <<= 1) { |
449 | /* wait for "start of" clock tick */ | 438 | /* Wait for "start of" clock tick */ |
450 | ticks = jiffies; | 439 | ticks = jiffies; |
451 | while (ticks == jiffies) | 440 | while (ticks == jiffies) |
452 | /* nothing */ ; | 441 | /* nothing */ ; |
453 | /* Go .. */ | 442 | /* Go ... */ |
454 | ticks = jiffies; | 443 | ticks = jiffies; |
455 | __delay(loops_per_jiffy); | 444 | __delay(loops_per_jiffy); |
456 | ticks = jiffies - ticks; | 445 | ticks = jiffies - ticks; |
@@ -458,8 +447,10 @@ static void au1000_calibrate_delay(void) | |||
458 | break; | 447 | break; |
459 | } | 448 | } |
460 | 449 | ||
461 | /* Do a binary approximation to get loops_per_jiffy set to equal one clock | 450 | /* |
462 | (up to lps_precision bits) */ | 451 | * Do a binary approximation to get loops_per_jiffy set to be equal |
452 | * one clock (up to lps_precision bits) | ||
453 | */ | ||
463 | loops_per_jiffy >>= 1; | 454 | loops_per_jiffy >>= 1; |
464 | loopbit = loops_per_jiffy; | 455 | loopbit = loops_per_jiffy; |
465 | while (lps_precision-- && (loopbit >>= 1)) { | 456 | while (lps_precision-- && (loopbit >>= 1)) { |
@@ -472,4 +463,4 @@ static void au1000_calibrate_delay(void) | |||
472 | loops_per_jiffy &= ~loopbit; | 463 | loops_per_jiffy &= ~loopbit; |
473 | } | 464 | } |
474 | } | 465 | } |
475 | #endif /* CONFIG_PM */ | 466 | #endif /* CONFIG_PM */ |
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c index f10af829e4ec..18b310b475ca 100644 --- a/arch/mips/au1000/common/prom.c +++ b/arch/mips/au1000/common/prom.c | |||
@@ -3,9 +3,8 @@ | |||
3 | * BRIEF MODULE DESCRIPTION | 3 | * BRIEF MODULE DESCRIPTION |
4 | * PROM library initialisation code, supports YAMON and U-Boot. | 4 | * PROM library initialisation code, supports YAMON and U-Boot. |
5 | * | 5 | * |
6 | * Copyright 2000, 2001, 2006 MontaVista Software Inc. | 6 | * Copyright 2000-2001, 2006, 2008 MontaVista Software Inc. |
7 | * Author: MontaVista Software, Inc. | 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
8 | * ppopov@mvista.com or source@mvista.com | ||
9 | * | 8 | * |
10 | * This file was derived from Carsten Langgaard's | 9 | * This file was derived from Carsten Langgaard's |
11 | * arch/mips/mips-boards/xx files. | 10 | * arch/mips/mips-boards/xx files. |
@@ -57,7 +56,7 @@ void prom_init_cmdline(void) | |||
57 | actr = 1; /* Always ignore argv[0] */ | 56 | actr = 1; /* Always ignore argv[0] */ |
58 | 57 | ||
59 | cp = &(arcs_cmdline[0]); | 58 | cp = &(arcs_cmdline[0]); |
60 | while(actr < prom_argc) { | 59 | while (actr < prom_argc) { |
61 | strcpy(cp, prom_argv[actr]); | 60 | strcpy(cp, prom_argv[actr]); |
62 | cp += strlen(prom_argv[actr]); | 61 | cp += strlen(prom_argv[actr]); |
63 | *cp++ = ' '; | 62 | *cp++ = ' '; |
@@ -84,10 +83,8 @@ char *prom_getenv(char *envname) | |||
84 | if (yamon) { | 83 | if (yamon) { |
85 | if (strcmp(envname, *env++) == 0) | 84 | if (strcmp(envname, *env++) == 0) |
86 | return *env; | 85 | return *env; |
87 | } else { | 86 | } else if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=') |
88 | if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=') | 87 | return *env + i + 1; |
89 | return *env + i + 1; | ||
90 | } | ||
91 | env++; | 88 | env++; |
92 | } | 89 | } |
93 | 90 | ||
@@ -110,13 +107,13 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) | |||
110 | { | 107 | { |
111 | int i; | 108 | int i; |
112 | 109 | ||
113 | for(i = 0; i < 6; i++) { | 110 | for (i = 0; i < 6; i++) { |
114 | unsigned char num; | 111 | unsigned char num; |
115 | 112 | ||
116 | if((*str == '.') || (*str == ':')) | 113 | if ((*str == '.') || (*str == ':')) |
117 | str++; | 114 | str++; |
118 | num = str2hexnum(*str++) << 4; | 115 | num = str2hexnum(*str++) << 4; |
119 | num |= (str2hexnum(*str++)); | 116 | num |= str2hexnum(*str++); |
120 | ea[i] = num; | 117 | ea[i] = num; |
121 | } | 118 | } |
122 | } | 119 | } |
diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/au1000/common/puts.c index e34c67e89293..55bbe24d45b6 100644 --- a/arch/mips/au1000/common/puts.c +++ b/arch/mips/au1000/common/puts.c | |||
@@ -1,11 +1,10 @@ | |||
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * BRIEF MODULE DESCRIPTION | 3 | * BRIEF MODULE DESCRIPTION |
4 | * Low level uart routines to directly access a 16550 uart. | 4 | * Low level UART routines to directly access Alchemy UART. |
5 | * | 5 | * |
6 | * Copyright 2001 MontaVista Software Inc. | 6 | * Copyright 2001, 2008 MontaVista Software Inc. |
7 | * Author: MontaVista Software, Inc. | 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
8 | * ppopov@mvista.com or source@mvista.com | ||
9 | * | 8 | * |
10 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
11 | * under the terms of the GNU General Public License as published by the | 10 | * under the terms of the GNU General Public License as published by the |
@@ -40,12 +39,12 @@ | |||
40 | 39 | ||
41 | static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE; | 40 | static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE; |
42 | 41 | ||
43 | |||
44 | #ifdef SLOW_DOWN | 42 | #ifdef SLOW_DOWN |
45 | static inline void slow_down(void) | 43 | static inline void slow_down(void) |
46 | { | 44 | { |
47 | int k; | 45 | int k; |
48 | for (k=0; k<10000; k++); | 46 | |
47 | for (k = 0; k < 10000; k++); | ||
49 | } | 48 | } |
50 | #else | 49 | #else |
51 | #define slow_down() | 50 | #define slow_down() |
@@ -54,16 +53,16 @@ static inline void slow_down(void) | |||
54 | void | 53 | void |
55 | prom_putchar(const unsigned char c) | 54 | prom_putchar(const unsigned char c) |
56 | { | 55 | { |
57 | unsigned char ch; | 56 | unsigned char ch; |
58 | int i = 0; | 57 | int i = 0; |
58 | |||
59 | do { | ||
60 | ch = com1[SER_CMD]; | ||
61 | slow_down(); | ||
62 | i++; | ||
63 | if (i > TIMEOUT) | ||
64 | break; | ||
65 | } while (0 == (ch & TX_BUSY)); | ||
59 | 66 | ||
60 | do { | 67 | com1[SER_DATA] = c; |
61 | ch = com1[SER_CMD]; | ||
62 | slow_down(); | ||
63 | i++; | ||
64 | if (i>TIMEOUT) { | ||
65 | break; | ||
66 | } | ||
67 | } while (0 == (ch & TX_BUSY)); | ||
68 | com1[SER_DATA] = c; | ||
69 | } | 68 | } |
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c index 60cec537c745..d555429c8d6f 100644 --- a/arch/mips/au1000/common/reset.c +++ b/arch/mips/au1000/common/reset.c | |||
@@ -1,11 +1,10 @@ | |||
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * BRIEF MODULE DESCRIPTION | 3 | * BRIEF MODULE DESCRIPTION |
4 | * Au1000 reset routines. | 4 | * Au1xx0 reset routines. |
5 | * | 5 | * |
6 | * Copyright 2001 MontaVista Software Inc. | 6 | * Copyright 2001, 2006, 2008 MontaVista Software Inc. |
7 | * Author: MontaVista Software, Inc. | 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
8 | * ppopov@mvista.com or source@mvista.com | ||
9 | * | 8 | * |
10 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
11 | * under the terms of the GNU General Public License as published by the | 10 | * under the terms of the GNU General Public License as published by the |
@@ -28,10 +27,11 @@ | |||
28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
29 | */ | 28 | */ |
30 | 29 | ||
30 | #include <asm/cacheflush.h> | ||
31 | |||
31 | #include <asm/mach-au1x00/au1000.h> | 32 | #include <asm/mach-au1x00/au1000.h> |
32 | 33 | ||
33 | extern int au_sleep(void); | 34 | extern int au_sleep(void); |
34 | extern void (*flush_cache_all)(void); | ||
35 | 35 | ||
36 | void au1000_restart(char *command) | 36 | void au1000_restart(char *command) |
37 | { | 37 | { |
@@ -40,8 +40,8 @@ void au1000_restart(char *command) | |||
40 | u32 prid = read_c0_prid(); | 40 | u32 prid = read_c0_prid(); |
41 | 41 | ||
42 | printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); | 42 | printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); |
43 | switch (prid & 0xFF000000) | 43 | |
44 | { | 44 | switch (prid & 0xFF000000) { |
45 | case 0x00000000: /* Au1000 */ | 45 | case 0x00000000: /* Au1000 */ |
46 | au_writel(0x02, 0xb0000010); /* ac97_enable */ | 46 | au_writel(0x02, 0xb0000010); /* ac97_enable */ |
47 | au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */ | 47 | au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */ |
@@ -138,9 +138,6 @@ void au1000_restart(char *command) | |||
138 | au_writel(0x00, 0xb1900064); /* sys_auxpll */ | 138 | au_writel(0x00, 0xb1900064); /* sys_auxpll */ |
139 | au_writel(0x00, 0xb1900100); /* sys_pininputen */ | 139 | au_writel(0x00, 0xb1900100); /* sys_pininputen */ |
140 | break; | 140 | break; |
141 | |||
142 | default: | ||
143 | break; | ||
144 | } | 141 | } |
145 | 142 | ||
146 | set_c0_status(ST0_BEV | ST0_ERL); | 143 | set_c0_status(ST0_BEV | ST0_ERL); |
@@ -158,25 +155,25 @@ void au1000_restart(char *command) | |||
158 | void au1000_halt(void) | 155 | void au1000_halt(void) |
159 | { | 156 | { |
160 | #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) | 157 | #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) |
161 | /* power off system */ | 158 | /* Power off system */ |
162 | printk("\n** Powering off...\n"); | 159 | printk(KERN_NOTICE "\n** Powering off...\n"); |
163 | au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C); | 160 | au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C); |
164 | au_sync(); | 161 | au_sync(); |
165 | while(1); /* should not get here */ | 162 | while (1); /* should not get here */ |
166 | #else | 163 | #else |
167 | printk(KERN_NOTICE "\n** You can safely turn off the power\n"); | 164 | printk(KERN_NOTICE "\n** You can safely turn off the power\n"); |
168 | #ifdef CONFIG_MIPS_MIRAGE | 165 | #ifdef CONFIG_MIPS_MIRAGE |
169 | au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); | 166 | au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); |
170 | #endif | 167 | #endif |
171 | #ifdef CONFIG_MIPS_DB1200 | 168 | #ifdef CONFIG_MIPS_DB1200 |
172 | au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C); | 169 | au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); |
173 | #endif | 170 | #endif |
174 | #ifdef CONFIG_PM | 171 | #ifdef CONFIG_PM |
175 | au_sleep(); | 172 | au_sleep(); |
176 | 173 | ||
177 | /* should not get here */ | 174 | /* Should not get here */ |
178 | printk(KERN_ERR "Unable to put cpu in sleep mode\n"); | 175 | printk(KERN_ERR "Unable to put CPU in sleep mode\n"); |
179 | while(1); | 176 | while (1); |
180 | #else | 177 | #else |
181 | while (1) | 178 | while (1) |
182 | __asm__(".set\tmips3\n\t" | 179 | __asm__(".set\tmips3\n\t" |
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 0e86f7a6b4a7..1ac6b06f42a3 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c | |||
@@ -1,7 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2000 MontaVista Software Inc. | 2 | * Copyright 2000, 2007-2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. | 3 | * Author: MontaVista Software, Inc. <source@mvista.com |
4 | * ppopov@mvista.com or source@mvista.com | ||
5 | * | 4 | * |
6 | * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. | 5 | * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. |
7 | * | 6 | * |
@@ -48,7 +47,7 @@ void __init plat_mem_setup(void) | |||
48 | { | 47 | { |
49 | struct cpu_spec *sp; | 48 | struct cpu_spec *sp; |
50 | char *argptr; | 49 | char *argptr; |
51 | unsigned long prid, cpufreq, bclk = 1; | 50 | unsigned long prid, cpufreq, bclk; |
52 | 51 | ||
53 | set_cpuspec(); | 52 | set_cpuspec(); |
54 | sp = cur_cpu_spec[0]; | 53 | sp = cur_cpu_spec[0]; |
@@ -66,42 +65,39 @@ void __init plat_mem_setup(void) | |||
66 | cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; | 65 | cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; |
67 | printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); | 66 | printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); |
68 | 67 | ||
69 | bclk = sp->cpu_bclk; | 68 | if (sp->cpu_bclk) { |
70 | if (bclk) | ||
71 | { | ||
72 | /* Enable BCLK switching */ | 69 | /* Enable BCLK switching */ |
73 | bclk = au_readl(0xB190003C); | 70 | bclk = au_readl(SYS_POWERCTRL); |
74 | au_writel(bclk | 0x60, 0xB190003C); | 71 | au_writel(bclk | 0x60, SYS_POWERCTRL); |
75 | printk("BCLK switching enabled!\n"); | 72 | printk(KERN_INFO "BCLK switching enabled!\n"); |
76 | } | 73 | } |
77 | 74 | ||
78 | if (sp->cpu_od) { | 75 | if (sp->cpu_od) |
79 | /* Various early Au1000 Errata corrected by this */ | 76 | /* Various early Au1xx0 errata corrected by this */ |
80 | set_c0_config(1<<19); /* Set Config[OD] */ | 77 | set_c0_config(1 << 19); /* Set Config[OD] */ |
81 | } | 78 | else |
82 | else { | ||
83 | /* Clear to obtain best system bus performance */ | 79 | /* Clear to obtain best system bus performance */ |
84 | clear_c0_config(1<<19); /* Clear Config[OD] */ | 80 | clear_c0_config(1 << 19); /* Clear Config[OD] */ |
85 | } | ||
86 | 81 | ||
87 | argptr = prom_getcmdline(); | 82 | argptr = prom_getcmdline(); |
88 | 83 | ||
89 | #ifdef CONFIG_SERIAL_8250_CONSOLE | 84 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
90 | if ((argptr = strstr(argptr, "console=")) == NULL) { | 85 | argptr = strstr(argptr, "console="); |
86 | if (argptr == NULL) { | ||
91 | argptr = prom_getcmdline(); | 87 | argptr = prom_getcmdline(); |
92 | strcat(argptr, " console=ttyS0,115200"); | 88 | strcat(argptr, " console=ttyS0,115200"); |
93 | } | 89 | } |
94 | #endif | 90 | #endif |
95 | 91 | ||
96 | #ifdef CONFIG_FB_AU1100 | 92 | #ifdef CONFIG_FB_AU1100 |
97 | if ((argptr = strstr(argptr, "video=")) == NULL) { | 93 | argptr = strstr(argptr, "video="); |
98 | argptr = prom_getcmdline(); | 94 | if (argptr == NULL) { |
99 | /* default panel */ | 95 | argptr = prom_getcmdline(); |
100 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ | 96 | /* default panel */ |
101 | } | 97 | /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ |
98 | } | ||
102 | #endif | 99 | #endif |
103 | 100 | ||
104 | |||
105 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | 101 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) |
106 | /* au1000 does not support vra, au1500 and au1100 do */ | 102 | /* au1000 does not support vra, au1500 and au1100 do */ |
107 | strcat(argptr, " au1000_audio=vra"); | 103 | strcat(argptr, " au1000_audio=vra"); |
@@ -129,7 +125,7 @@ void __init plat_mem_setup(void) | |||
129 | /* This routine should be valid for all Au1x based boards */ | 125 | /* This routine should be valid for all Au1x based boards */ |
130 | phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) | 126 | phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) |
131 | { | 127 | { |
132 | /* Don't fixup 36 bit addresses */ | 128 | /* Don't fixup 36-bit addresses */ |
133 | if ((phys_addr >> 32) != 0) | 129 | if ((phys_addr >> 32) != 0) |
134 | return phys_addr; | 130 | return phys_addr; |
135 | 131 | ||
@@ -145,17 +141,17 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) | |||
145 | } | 141 | } |
146 | #endif | 142 | #endif |
147 | 143 | ||
148 | /* All Au1x SOCs have a pcmcia controller */ | 144 | /* |
149 | /* We setup our 32 bit pseudo addresses to be equal to the | 145 | * All Au1xx0 SOCs have a PCMCIA controller. |
150 | * 36 bit addr >> 4, to make it easier to check the address | 146 | * We setup our 32-bit pseudo addresses to be equal to the |
147 | * 36-bit addr >> 4, to make it easier to check the address | ||
151 | * and fix it. | 148 | * and fix it. |
152 | * The Au1x socket 0 phys attribute address is 0xF 4000 0000. | 149 | * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. |
153 | * The pseudo address we use is 0xF400 0000. Any address over | 150 | * The pseudo address we use is 0xF400 0000. Any address over |
154 | * 0xF400 0000 is a pcmcia pseudo address. | 151 | * 0xF400 0000 is a PCMCIA pseudo address. |
155 | */ | 152 | */ |
156 | if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) { | 153 | if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) |
157 | return (phys_t)(phys_addr << 4); | 154 | return (phys_t)(phys_addr << 4); |
158 | } | ||
159 | 155 | ||
160 | /* default nop */ | 156 | /* default nop */ |
161 | return phys_addr; | 157 | return phys_addr; |
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index bdb6d73b26fb..563d9390a872 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c | |||
@@ -25,11 +25,9 @@ | |||
25 | * | 25 | * |
26 | * Setting up the clock on the MIPS boards. | 26 | * Setting up the clock on the MIPS boards. |
27 | * | 27 | * |
28 | * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This | 28 | * We provide the clock interrupt processing and the timer offset compute |
29 | * will use the user interface gettimeofday() functions from the | 29 | * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is |
30 | * arch/mips/kernel/time.c, and we provide the clock interrupt processing | 30 | * available. -- Dan |
31 | * and the timer offset compute functions. If CONFIG_PM is selected, | ||
32 | * we also ensure the 32KHz timer is available. -- Dan | ||
33 | */ | 31 | */ |
34 | 32 | ||
35 | #include <linux/types.h> | 33 | #include <linux/types.h> |
@@ -47,8 +45,7 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */ | |||
47 | #if HZ < 100 || HZ > 1000 | 45 | #if HZ < 100 || HZ > 1000 |
48 | #error "unsupported HZ value! Must be in [100,1000]" | 46 | #error "unsupported HZ value! Must be in [100,1000]" |
49 | #endif | 47 | #endif |
50 | #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */ | 48 | #define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */ |
51 | extern void startup_match20_interrupt(irq_handler_t handler); | ||
52 | static unsigned long last_pc0, last_match20; | 49 | static unsigned long last_pc0, last_match20; |
53 | #endif | 50 | #endif |
54 | 51 | ||
@@ -61,7 +58,7 @@ static irqreturn_t counter0_irq(int irq, void *dev_id) | |||
61 | { | 58 | { |
62 | unsigned long pc0; | 59 | unsigned long pc0; |
63 | int time_elapsed; | 60 | int time_elapsed; |
64 | static int jiffie_drift = 0; | 61 | static int jiffie_drift; |
65 | 62 | ||
66 | if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { | 63 | if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { |
67 | /* should never happen! */ | 64 | /* should never happen! */ |
@@ -70,13 +67,11 @@ static irqreturn_t counter0_irq(int irq, void *dev_id) | |||
70 | } | 67 | } |
71 | 68 | ||
72 | pc0 = au_readl(SYS_TOYREAD); | 69 | pc0 = au_readl(SYS_TOYREAD); |
73 | if (pc0 < last_match20) { | 70 | if (pc0 < last_match20) |
74 | /* counter overflowed */ | 71 | /* counter overflowed */ |
75 | time_elapsed = (0xffffffff - last_match20) + pc0; | 72 | time_elapsed = (0xffffffff - last_match20) + pc0; |
76 | } | 73 | else |
77 | else { | ||
78 | time_elapsed = pc0 - last_match20; | 74 | time_elapsed = pc0 - last_match20; |
79 | } | ||
80 | 75 | ||
81 | while (time_elapsed > 0) { | 76 | while (time_elapsed > 0) { |
82 | do_timer(1); | 77 | do_timer(1); |
@@ -92,8 +87,9 @@ static irqreturn_t counter0_irq(int irq, void *dev_id) | |||
92 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); | 87 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); |
93 | au_sync(); | 88 | au_sync(); |
94 | 89 | ||
95 | /* our counter ticks at 10.009765625 ms/tick, we we're running | 90 | /* |
96 | * almost 10uS too slow per tick. | 91 | * Our counter ticks at 10.009765625 ms/tick, we we're running |
92 | * almost 10 uS too slow per tick. | ||
97 | */ | 93 | */ |
98 | 94 | ||
99 | if (jiffie_drift >= 999) { | 95 | if (jiffie_drift >= 999) { |
@@ -117,20 +113,17 @@ struct irqaction counter0_action = { | |||
117 | /* When we wakeup from sleep, we have to "catch up" on all of the | 113 | /* When we wakeup from sleep, we have to "catch up" on all of the |
118 | * timer ticks we have missed. | 114 | * timer ticks we have missed. |
119 | */ | 115 | */ |
120 | void | 116 | void wakeup_counter0_adjust(void) |
121 | wakeup_counter0_adjust(void) | ||
122 | { | 117 | { |
123 | unsigned long pc0; | 118 | unsigned long pc0; |
124 | int time_elapsed; | 119 | int time_elapsed; |
125 | 120 | ||
126 | pc0 = au_readl(SYS_TOYREAD); | 121 | pc0 = au_readl(SYS_TOYREAD); |
127 | if (pc0 < last_match20) { | 122 | if (pc0 < last_match20) |
128 | /* counter overflowed */ | 123 | /* counter overflowed */ |
129 | time_elapsed = (0xffffffff - last_match20) + pc0; | 124 | time_elapsed = (0xffffffff - last_match20) + pc0; |
130 | } | 125 | else |
131 | else { | ||
132 | time_elapsed = pc0 - last_match20; | 126 | time_elapsed = pc0 - last_match20; |
133 | } | ||
134 | 127 | ||
135 | while (time_elapsed > 0) { | 128 | while (time_elapsed > 0) { |
136 | time_elapsed -= MATCH20_INC; | 129 | time_elapsed -= MATCH20_INC; |
@@ -143,10 +136,8 @@ wakeup_counter0_adjust(void) | |||
143 | 136 | ||
144 | } | 137 | } |
145 | 138 | ||
146 | /* This is just for debugging to set the timer for a sleep delay. | 139 | /* This is just for debugging to set the timer for a sleep delay. */ |
147 | */ | 140 | void wakeup_counter0_set(int ticks) |
148 | void | ||
149 | wakeup_counter0_set(int ticks) | ||
150 | { | 141 | { |
151 | unsigned long pc0; | 142 | unsigned long pc0; |
152 | 143 | ||
@@ -157,21 +148,22 @@ wakeup_counter0_set(int ticks) | |||
157 | } | 148 | } |
158 | #endif | 149 | #endif |
159 | 150 | ||
160 | /* I haven't found anyone that doesn't use a 12 MHz source clock, | 151 | /* |
152 | * I haven't found anyone that doesn't use a 12 MHz source clock, | ||
161 | * but just in case..... | 153 | * but just in case..... |
162 | */ | 154 | */ |
163 | #define AU1000_SRC_CLK 12000000 | 155 | #define AU1000_SRC_CLK 12000000 |
164 | 156 | ||
165 | /* | 157 | /* |
166 | * We read the real processor speed from the PLL. This is important | 158 | * We read the real processor speed from the PLL. This is important |
167 | * because it is more accurate than computing it from the 32KHz | 159 | * because it is more accurate than computing it from the 32 KHz |
168 | * counter, if it exists. If we don't have an accurate processor | 160 | * counter, if it exists. If we don't have an accurate processor |
169 | * speed, all of the peripherals that derive their clocks based on | 161 | * speed, all of the peripherals that derive their clocks based on |
170 | * this advertised speed will introduce error and sometimes not work | 162 | * this advertised speed will introduce error and sometimes not work |
171 | * properly. This function is futher convoluted to still allow configurations | 163 | * properly. This function is futher convoluted to still allow configurations |
172 | * to do that in case they have really, really old silicon with a | 164 | * to do that in case they have really, really old silicon with a |
173 | * write-only PLL register, that we need the 32KHz when power management | 165 | * write-only PLL register, that we need the 32 KHz when power management |
174 | * "wait" is enabled, and we need to detect if the 32KHz isn't present | 166 | * "wait" is enabled, and we need to detect if the 32 KHz isn't present |
175 | * but requested......got it? :-) -- Dan | 167 | * but requested......got it? :-) -- Dan |
176 | */ | 168 | */ |
177 | unsigned long calc_clock(void) | 169 | unsigned long calc_clock(void) |
@@ -182,8 +174,7 @@ unsigned long calc_clock(void) | |||
182 | 174 | ||
183 | spin_lock_irqsave(&time_lock, flags); | 175 | spin_lock_irqsave(&time_lock, flags); |
184 | 176 | ||
185 | /* Power management cares if we don't have a 32KHz counter. | 177 | /* Power management cares if we don't have a 32 KHz counter. */ |
186 | */ | ||
187 | no_au1xxx_32khz = 0; | 178 | no_au1xxx_32khz = 0; |
188 | counter = au_readl(SYS_COUNTER_CNTRL); | 179 | counter = au_readl(SYS_COUNTER_CNTRL); |
189 | if (counter & SYS_CNTRL_E0) { | 180 | if (counter & SYS_CNTRL_E0) { |
@@ -193,7 +184,7 @@ unsigned long calc_clock(void) | |||
193 | 184 | ||
194 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); | 185 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); |
195 | /* RTC now ticks at 32.768/16 kHz */ | 186 | /* RTC now ticks at 32.768/16 kHz */ |
196 | au_writel(trim_divide-1, SYS_RTCTRIM); | 187 | au_writel(trim_divide - 1, SYS_RTCTRIM); |
197 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); | 188 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); |
198 | 189 | ||
199 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); | 190 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); |
@@ -215,9 +206,11 @@ unsigned long calc_clock(void) | |||
215 | #endif | 206 | #endif |
216 | else | 207 | else |
217 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; | 208 | cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; |
209 | /* On Alchemy CPU:counter ratio is 1:1 */ | ||
218 | mips_hpt_frequency = cpu_speed; | 210 | mips_hpt_frequency = cpu_speed; |
219 | // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) | 211 | /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ |
220 | set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); | 212 | set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) |
213 | & 0x03) + 2) * 16)); | ||
221 | spin_unlock_irqrestore(&time_lock, flags); | 214 | spin_unlock_irqrestore(&time_lock, flags); |
222 | return cpu_speed; | 215 | return cpu_speed; |
223 | } | 216 | } |
@@ -228,10 +221,10 @@ void __init plat_time_init(void) | |||
228 | 221 | ||
229 | est_freq += 5000; /* round */ | 222 | est_freq += 5000; /* round */ |
230 | est_freq -= est_freq%10000; | 223 | est_freq -= est_freq%10000; |
231 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | 224 | printk(KERN_INFO "CPU frequency %u.%02u MHz\n", |
232 | (est_freq%1000000)*100/1000000); | 225 | est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); |
233 | set_au1x00_speed(est_freq); | 226 | set_au1x00_speed(est_freq); |
234 | set_au1x00_lcd_clock(); // program the LCD clock | 227 | set_au1x00_lcd_clock(); /* program the LCD clock */ |
235 | 228 | ||
236 | #ifdef CONFIG_PM | 229 | #ifdef CONFIG_PM |
237 | /* | 230 | /* |
@@ -243,30 +236,29 @@ void __init plat_time_init(void) | |||
243 | * counter 0 interrupt as a special irq and it doesn't show | 236 | * counter 0 interrupt as a special irq and it doesn't show |
244 | * up under /proc/interrupts. | 237 | * up under /proc/interrupts. |
245 | * | 238 | * |
246 | * Check to ensure we really have a 32KHz oscillator before | 239 | * Check to ensure we really have a 32 KHz oscillator before |
247 | * we do this. | 240 | * we do this. |
248 | */ | 241 | */ |
249 | if (no_au1xxx_32khz) | 242 | if (no_au1xxx_32khz) |
250 | printk("WARNING: no 32KHz clock found.\n"); | 243 | printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); |
251 | else { | 244 | else { |
252 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); | 245 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); |
253 | au_writel(0, SYS_TOYWRITE); | 246 | au_writel(0, SYS_TOYWRITE); |
254 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); | 247 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); |
255 | 248 | ||
256 | au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK); | 249 | au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK); |
257 | au_writel(~0, SYS_WAKESRC); | 250 | au_writel(~0, SYS_WAKESRC); |
258 | au_sync(); | 251 | au_sync(); |
259 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); | 252 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); |
260 | 253 | ||
261 | /* setup match20 to interrupt once every HZ */ | 254 | /* Setup match20 to interrupt once every HZ */ |
262 | last_pc0 = last_match20 = au_readl(SYS_TOYREAD); | 255 | last_pc0 = last_match20 = au_readl(SYS_TOYREAD); |
263 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); | 256 | au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); |
264 | au_sync(); | 257 | au_sync(); |
265 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); | 258 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); |
266 | setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); | 259 | setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); |
267 | 260 | ||
268 | /* We can use the real 'wait' instruction. | 261 | /* We can use the real 'wait' instruction. */ |
269 | */ | ||
270 | allow_au1k_wait = 1; | 262 | allow_au1k_wait = 1; |
271 | } | 263 | } |
272 | 264 | ||