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authorStephen Boyd <sboyd@codeaurora.org>2015-03-13 14:09:34 -0400
committerKumar Gala <galak@codeaurora.org>2015-03-27 12:31:02 -0400
commitc0c89fafa289ea241ba3fb22d6f583f8089a719e (patch)
tree43e48055d1330a7fece805554b87f372d63e718d /arch
parent9eccca0843205f87c00404b663188b88eb248051 (diff)
ARM: Remove mach-msm and associated ARM architecture code
The maintainers for mach-msm no longer have any plans to support or test the platforms supported by this architecture[1]. Most likely there aren't any active users of this code anyway, so let's delete it. [1] http://lkml.kernel.org/r/20150307031212.GA8434@fifo99.com Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Kconfig.debug29
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/msm_defconfig121
-rw-r--r--arch/arm/include/debug/msm.S14
-rw-r--r--arch/arm/mach-msm/Kconfig109
-rw-r--r--arch/arm/mach-msm/Makefile23
-rw-r--r--arch/arm/mach-msm/Makefile.boot3
-rw-r--r--arch/arm/mach-msm/board-halibut.c110
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c191
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c254
-rw-r--r--arch/arm/mach-msm/board-sapphire.c114
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c233
-rw-r--r--arch/arm/mach-msm/board-trout-mmc.c185
-rw-r--r--arch/arm/mach-msm/board-trout-panel.c292
-rw-r--r--arch/arm/mach-msm/board-trout.c111
-rw-r--r--arch/arm/mach-msm/board-trout.h162
-rw-r--r--arch/arm/mach-msm/clock-pcom.c176
-rw-r--r--arch/arm/mach-msm/clock-pcom.h145
-rw-r--r--arch/arm/mach-msm/clock.c28
-rw-r--r--arch/arm/mach-msm/clock.h43
-rw-r--r--arch/arm/mach-msm/common.h41
-rw-r--r--arch/arm/mach-msm/devices-msm7x00.c480
-rw-r--r--arch/arm/mach-msm/devices-msm7x30.c246
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c388
-rw-r--r--arch/arm/mach-msm/devices.h53
-rw-r--r--arch/arm/mach-msm/dma.c298
-rw-r--r--arch/arm/mach-msm/gpiomux-8x50.c51
-rw-r--r--arch/arm/mach-msm/gpiomux-v1.h67
-rw-r--r--arch/arm/mach-msm/gpiomux.c111
-rw-r--r--arch/arm/mach-msm/gpiomux.h84
-rw-r--r--arch/arm/mach-msm/include/mach/clk.h31
-rw-r--r--arch/arm/mach-msm/include/mach/dma.h151
-rw-r--r--arch/arm/mach-msm/include/mach/entry-macro.S36
-rw-r--r--arch/arm/mach-msm/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x00.h75
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x30.h153
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x50.h88
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h37
-rw-r--r--arch/arm/mach-msm/include/mach/msm_gpiomux.h38
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h108
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h103
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h125
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h53
-rw-r--r--arch/arm/mach-msm/include/mach/msm_smd.h109
-rw-r--r--arch/arm/mach-msm/include/mach/sirc.h98
-rw-r--r--arch/arm/mach-msm/include/mach/vreg.h29
-rw-r--r--arch/arm/mach-msm/io.c161
-rw-r--r--arch/arm/mach-msm/irq-vic.c363
-rw-r--r--arch/arm/mach-msm/irq.c151
-rw-r--r--arch/arm/mach-msm/last_radio_log.c71
-rw-r--r--arch/arm/mach-msm/proc_comm.c129
-rw-r--r--arch/arm/mach-msm/proc_comm.h258
-rw-r--r--arch/arm/mach-msm/sirc.c172
-rw-r--r--arch/arm/mach-msm/smd.c1034
-rw-r--r--arch/arm/mach-msm/smd_debug.c311
-rw-r--r--arch/arm/mach-msm/smd_private.h403
-rw-r--r--arch/arm/mach-msm/vreg.c220
58 files changed, 4 insertions, 8699 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a2bc9b..adc85072bd29 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -625,18 +625,6 @@ config ARCH_PXA
625 help 625 help
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 627
628config ARCH_MSM
629 bool "Qualcomm MSM (non-multiplatform)"
630 select ARCH_REQUIRE_GPIOLIB
631 select COMMON_CLK
632 select GENERIC_CLOCKEVENTS
633 help
634 Support for Qualcomm MSM/QSD based systems. This runs on the
635 apps processor of the MSM/QSD and depends on a shared memory
636 interface to the modem processor which runs the baseband
637 stack and controls some vital subsystems
638 (clock and power control, etc).
639
640config ARCH_SHMOBILE_LEGACY 628config ARCH_SHMOBILE_LEGACY
641 bool "Renesas ARM SoCs (non-multiplatform)" 629 bool "Renesas ARM SoCs (non-multiplatform)"
642 select ARCH_SHMOBILE 630 select ARCH_SHMOBILE
@@ -890,8 +878,6 @@ source "arch/arm/mach-ks8695/Kconfig"
890 878
891source "arch/arm/mach-meson/Kconfig" 879source "arch/arm/mach-meson/Kconfig"
892 880
893source "arch/arm/mach-msm/Kconfig"
894
895source "arch/arm/mach-moxart/Kconfig" 881source "arch/arm/mach-moxart/Kconfig"
896 882
897source "arch/arm/mach-mv78xx0/Kconfig" 883source "arch/arm/mach-mv78xx0/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de7518341..b010202043c5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -448,25 +448,6 @@ choice
448 Say Y here if you want kernel low-level debugging support 448 Say Y here if you want kernel low-level debugging support
449 on MMP UART3. 449 on MMP UART3.
450 450
451 config DEBUG_MSM_UART
452 bool "Kernel low-level debugging messages via MSM UART"
453 depends on ARCH_MSM
454 help
455 Say Y here if you want the debug print routines to direct
456 their output to the serial port on MSM devices.
457
458 ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT #
459 MSM7X00A, QSD8X50 0xa9a00000 0xe1000000 UART1
460 MSM7X00A, QSD8X50 0xa9b00000 0xe1000000 UART2
461 MSM7X00A, QSD8X50 0xa9c00000 0xe1000000 UART3
462
463 MSM7X30 0xaca00000 0xe1000000 UART1
464 MSM7X30 0xacb00000 0xe1000000 UART2
465 MSM7X30 0xacc00000 0xe1000000 UART3
466
467 Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
468 options based on your needs.
469
470 config DEBUG_QCOM_UARTDM 451 config DEBUG_QCOM_UARTDM
471 bool "Kernel low-level debugging messages via QCOM UARTDM" 452 bool "Kernel low-level debugging messages via QCOM UARTDM"
472 depends on ARCH_QCOM 453 depends on ARCH_QCOM
@@ -1295,7 +1276,7 @@ config DEBUG_LL_INCLUDE
1295 DEBUG_IMX6SL_UART || \ 1276 DEBUG_IMX6SL_UART || \
1296 DEBUG_IMX6SX_UART 1277 DEBUG_IMX6SX_UART
1297 default "debug/ks8695.S" if DEBUG_KS8695_UART 1278 default "debug/ks8695.S" if DEBUG_KS8695_UART
1298 default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM 1279 default "debug/msm.S" if DEBUG_QCOM_UARTDM
1299 default "debug/netx.S" if DEBUG_NETX_UART 1280 default "debug/netx.S" if DEBUG_NETX_UART
1300 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 1281 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
1301 default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 1282 default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
@@ -1388,7 +1369,6 @@ config DEBUG_UART_PHYS
1388 default 0x80230000 if DEBUG_PICOXCELL_UART 1369 default 0x80230000 if DEBUG_PICOXCELL_UART
1389 default 0x808c0000 if ARCH_EP93XX 1370 default 0x808c0000 if ARCH_EP93XX
1390 default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART 1371 default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
1391 default 0xa9a00000 if DEBUG_MSM_UART
1392 default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1 1372 default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
1393 default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX 1373 default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
1394 default 0xc0013000 if DEBUG_U300_UART 1374 default 0xc0013000 if DEBUG_U300_UART
@@ -1433,7 +1413,7 @@ config DEBUG_UART_PHYS
1433 DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1413 DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1434 DEBUG_LL_UART_EFM32 || \ 1414 DEBUG_LL_UART_EFM32 || \
1435 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ 1415 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1436 DEBUG_MSM_UART || DEBUG_NETX_UART || \ 1416 DEBUG_NETX_UART || \
1437 DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ 1417 DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
1438 DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ 1418 DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
1439 DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ 1419 DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
@@ -1446,7 +1426,6 @@ config DEBUG_UART_VIRT
1446 hex "Virtual base address of debug UART" 1426 hex "Virtual base address of debug UART"
1447 default 0xe0000a00 if DEBUG_NETX_UART 1427 default 0xe0000a00 if DEBUG_NETX_UART
1448 default 0xe0010fe0 if ARCH_RPC 1428 default 0xe0010fe0 if ARCH_RPC
1449 default 0xe1000000 if DEBUG_MSM_UART
1450 default 0xf0000be0 if ARCH_EBSA110 1429 default 0xf0000be0 if ARCH_EBSA110
1451 default 0xf0010000 if DEBUG_ASM9260_UART 1430 default 0xf0010000 if DEBUG_ASM9260_UART
1452 default 0xf01fb000 if DEBUG_NOMADIK_UART 1431 default 0xf01fb000 if DEBUG_NOMADIK_UART
@@ -1526,7 +1505,7 @@ config DEBUG_UART_VIRT
1526 default DEBUG_UART_PHYS if !MMU 1505 default DEBUG_UART_PHYS if !MMU
1527 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1506 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1528 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ 1507 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1529 DEBUG_MSM_UART || DEBUG_NETX_UART || \ 1508 DEBUG_NETX_UART || \
1530 DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ 1509 DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
1531 DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \ 1510 DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
1532 DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 1511 DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
@@ -1556,7 +1535,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
1556 1535
1557config DEBUG_UNCOMPRESS 1536config DEBUG_UNCOMPRESS
1558 bool 1537 bool
1559 depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG 1538 depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG
1560 default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ 1539 default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
1561 (!DEBUG_TEGRA_UART || !ZBOOT_ROM) 1540 (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
1562 help 1541 help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7f99cd652203..fa03c13ddfec 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,7 +136,6 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000
136ifeq ($(CONFIG_ARCH_SA1100),y) 136ifeq ($(CONFIG_ARCH_SA1100),y)
137textofs-$(CONFIG_SA1111) := 0x00208000 137textofs-$(CONFIG_SA1111) := 0x00208000
138endif 138endif
139textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
140textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 139textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
141textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 140textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
142textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 141textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
@@ -170,7 +169,6 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
170machine-$(CONFIG_ARCH_MESON) += meson 169machine-$(CONFIG_ARCH_MESON) += meson
171machine-$(CONFIG_ARCH_MMP) += mmp 170machine-$(CONFIG_ARCH_MMP) += mmp
172machine-$(CONFIG_ARCH_MOXART) += moxart 171machine-$(CONFIG_ARCH_MOXART) += moxart
173machine-$(CONFIG_ARCH_MSM) += msm
174machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 172machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
175machine-$(CONFIG_ARCH_MVEBU) += mvebu 173machine-$(CONFIG_ARCH_MVEBU) += mvebu
176machine-$(CONFIG_ARCH_MXC) += imx 174machine-$(CONFIG_ARCH_MXC) += imx
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
deleted file mode 100644
index dd18c9e527d6..000000000000
--- a/arch/arm/configs/msm_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
1CONFIG_SYSVIPC=y
2CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_KALLSYMS_ALL=y
9CONFIG_EMBEDDED=y
10# CONFIG_SLUB_DEBUG is not set
11# CONFIG_COMPAT_BRK is not set
12CONFIG_PROFILING=y
13CONFIG_OPROFILE=y
14CONFIG_KPROBES=y
15CONFIG_MODULES=y
16CONFIG_MODULE_UNLOAD=y
17CONFIG_MODULE_FORCE_UNLOAD=y
18CONFIG_MODVERSIONS=y
19CONFIG_PARTITION_ADVANCED=y
20CONFIG_ARCH_MSM=y
21CONFIG_PREEMPT=y
22CONFIG_AEABI=y
23CONFIG_HIGHMEM=y
24CONFIG_HIGHPTE=y
25CONFIG_CLEANCACHE=y
26CONFIG_AUTO_ZRELADDR=y
27CONFIG_VFP=y
28# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_INET=y
33CONFIG_IP_ADVANCED_ROUTER=y
34CONFIG_IP_MULTIPLE_TABLES=y
35CONFIG_IP_ROUTE_VERBOSE=y
36CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_LRO is not set
42# CONFIG_IPV6 is not set
43CONFIG_CFG80211=y
44CONFIG_RFKILL=y
45CONFIG_BLK_DEV_LOOP=y
46CONFIG_BLK_DEV_RAM=y
47CONFIG_SCSI=y
48CONFIG_BLK_DEV_SD=y
49CONFIG_CHR_DEV_SG=y
50CONFIG_CHR_DEV_SCH=y
51CONFIG_SCSI_MULTI_LUN=y
52CONFIG_SCSI_CONSTANTS=y
53CONFIG_SCSI_LOGGING=y
54CONFIG_SCSI_SCAN_ASYNC=y
55CONFIG_NETDEVICES=y
56CONFIG_DUMMY=y
57CONFIG_SLIP=y
58CONFIG_SLIP_COMPRESSED=y
59CONFIG_SLIP_MODE_SLIP6=y
60CONFIG_USB_USBNET=y
61# CONFIG_USB_NET_AX8817X is not set
62# CONFIG_USB_NET_ZAURUS is not set
63CONFIG_INPUT_EVDEV=y
64# CONFIG_KEYBOARD_ATKBD is not set
65# CONFIG_MOUSE_PS2 is not set
66CONFIG_INPUT_JOYSTICK=y
67CONFIG_INPUT_TOUCHSCREEN=y
68CONFIG_INPUT_MISC=y
69CONFIG_INPUT_UINPUT=y
70CONFIG_SERIO_LIBPS2=y
71# CONFIG_LEGACY_PTYS is not set
72CONFIG_SERIAL_MSM=y
73CONFIG_SERIAL_MSM_CONSOLE=y
74# CONFIG_HW_RANDOM is not set
75CONFIG_I2C=y
76CONFIG_I2C_CHARDEV=y
77CONFIG_SPI=y
78CONFIG_DEBUG_GPIO=y
79CONFIG_GPIO_SYSFS=y
80CONFIG_THERMAL=y
81CONFIG_REGULATOR=y
82CONFIG_MEDIA_SUPPORT=y
83CONFIG_FB=y
84CONFIG_SOUND=y
85CONFIG_SND=y
86CONFIG_SND_DYNAMIC_MINORS=y
87# CONFIG_SND_ARM is not set
88# CONFIG_SND_SPI is not set
89# CONFIG_SND_USB is not set
90CONFIG_SND_SOC=y
91CONFIG_USB=y
92CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
93CONFIG_USB_MON=y
94CONFIG_USB_EHCI_HCD=y
95CONFIG_USB_ACM=y
96CONFIG_USB_SERIAL=y
97CONFIG_USB_GADGET=y
98CONFIG_USB_GADGET_DEBUG_FILES=y
99CONFIG_USB_GADGET_VBUS_DRAW=500
100CONFIG_RTC_CLASS=y
101CONFIG_STAGING=y
102CONFIG_EXT2_FS=y
103CONFIG_EXT2_FS_XATTR=y
104CONFIG_EXT3_FS=y
105# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
106CONFIG_EXT4_FS=y
107CONFIG_FUSE_FS=y
108CONFIG_VFAT_FS=y
109CONFIG_TMPFS=y
110CONFIG_NFS_FS=y
111CONFIG_NFS_V3_ACL=y
112CONFIG_NFS_V4=y
113CONFIG_CIFS=y
114CONFIG_PRINTK_TIME=y
115CONFIG_DYNAMIC_DEBUG=y
116CONFIG_DEBUG_INFO=y
117CONFIG_MAGIC_SYSRQ=y
118CONFIG_LOCKUP_DETECTOR=y
119# CONFIG_DETECT_HUNG_TASK is not set
120# CONFIG_SCHED_DEBUG is not set
121CONFIG_TIMER_STATS=y
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
index e55a9426b496..b03024fa671f 100644
--- a/arch/arm/include/debug/msm.S
+++ b/arch/arm/include/debug/msm.S
@@ -16,24 +16,17 @@
16 */ 16 */
17 17
18 .macro addruart, rp, rv, tmp 18 .macro addruart, rp, rv, tmp
19#ifdef CONFIG_DEBUG_UART_PHYS
20 ldr \rp, =CONFIG_DEBUG_UART_PHYS 19 ldr \rp, =CONFIG_DEBUG_UART_PHYS
21 ldr \rv, =CONFIG_DEBUG_UART_VIRT 20 ldr \rv, =CONFIG_DEBUG_UART_VIRT
22#endif
23 .endm 21 .endm
24 22
25 .macro senduart, rd, rx 23 .macro senduart, rd, rx
26ARM_BE8(rev \rd, \rd ) 24ARM_BE8(rev \rd, \rd )
27#ifdef CONFIG_DEBUG_QCOM_UARTDM
28 @ Write the 1 character to UARTDM_TF 25 @ Write the 1 character to UARTDM_TF
29 str \rd, [\rx, #0x70] 26 str \rd, [\rx, #0x70]
30#else
31 str \rd, [\rx, #0x0C]
32#endif
33 .endm 27 .endm
34 28
35 .macro waituart, rd, rx 29 .macro waituart, rd, rx
36#ifdef CONFIG_DEBUG_QCOM_UARTDM
37 @ check for TX_EMT in UARTDM_SR 30 @ check for TX_EMT in UARTDM_SR
38 ldr \rd, [\rx, #0x08] 31 ldr \rd, [\rx, #0x08]
39ARM_BE8(rev \rd, \rd ) 32ARM_BE8(rev \rd, \rd )
@@ -55,13 +48,6 @@ ARM_BE8(rev \rd, \rd )
55 str \rd, [\rx, #0x40] 48 str \rd, [\rx, #0x40]
56 @ UARTDM reg. Read to induce delay 49 @ UARTDM reg. Read to induce delay
57 ldr \rd, [\rx, #0x08] 50 ldr \rd, [\rx, #0x08]
58#else
59 @ wait for TX_READY
601001: ldr \rd, [\rx, #0x08]
61ARM_BE8(rev \rd, \rd )
62 tst \rd, #0x04
63 beq 1001b
64#endif
65 .endm 51 .endm
66 52
67 .macro busyuart, rd, rx 53 .macro busyuart, rd, rx
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
deleted file mode 100644
index a6b50e62a495..000000000000
--- a/arch/arm/mach-msm/Kconfig
+++ /dev/null
@@ -1,109 +0,0 @@
1if ARCH_MSM
2
3choice
4 prompt "Qualcomm MSM SoC Type"
5 default ARCH_MSM7X00A
6 depends on ARCH_MSM
7
8config ARCH_MSM7X00A
9 bool "MSM7x00A / MSM7x01A"
10 select ARCH_MSM_ARM11
11 select CPU_V6
12 select GPIO_MSM_V1
13 select MACH_TROUT if !MACH_HALIBUT
14 select MSM_PROC_COMM
15 select MSM_SMD
16 select CLKSRC_QCOM
17 select MSM_SMD_PKG3
18
19config ARCH_MSM7X30
20 bool "MSM7x30"
21 select ARCH_MSM_SCORPION
22 select CPU_V7
23 select GPIO_MSM_V1
24 select MACH_MSM7X30_SURF # if !
25 select MSM_GPIOMUX
26 select MSM_PROC_COMM
27 select MSM_SMD
28 select CLKSRC_QCOM
29 select MSM_VIC
30
31config ARCH_QSD8X50
32 bool "QSD8X50"
33 select ARCH_MSM_SCORPION
34 select CPU_V7
35 select GPIO_MSM_V1
36 select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
37 select MSM_GPIOMUX
38 select MSM_PROC_COMM
39 select MSM_SMD
40 select CLKSRC_QCOM
41 select MSM_VIC
42
43endchoice
44
45config MSM_SOC_REV_A
46 bool
47
48config ARCH_MSM_ARM11
49 bool
50
51config ARCH_MSM_SCORPION
52 bool
53
54config MSM_VIC
55 bool
56
57menu "Qualcomm MSM Board Type"
58 depends on ARCH_MSM
59
60config MACH_HALIBUT
61 depends on ARCH_MSM
62 depends on ARCH_MSM7X00A
63 bool "Halibut Board (QCT SURF7201A)"
64 help
65 Support for the Qualcomm SURF7201A eval board.
66
67config MACH_TROUT
68 depends on ARCH_MSM
69 depends on ARCH_MSM7X00A
70 bool "HTC Dream (aka trout)"
71 help
72 Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
73
74config MACH_MSM7X30_SURF
75 depends on ARCH_MSM7X30
76 bool "MSM7x30 SURF"
77 help
78 Support for the Qualcomm MSM7x30 SURF eval board.
79
80config MACH_QSD8X50_SURF
81 depends on ARCH_QSD8X50
82 bool "QSD8x50 SURF"
83 help
84 Support for the Qualcomm QSD8x50 SURF eval board.
85
86config MACH_QSD8X50A_ST1_5
87 depends on ARCH_QSD8X50
88 bool "QSD8x50A ST1.5"
89 select MSM_SOC_REV_A
90 help
91 Support for the Qualcomm ST1.5.
92
93endmenu
94
95config MSM_SMD_PKG3
96 bool
97
98config MSM_PROC_COMM
99 bool
100
101config MSM_SMD
102 bool
103
104config MSM_GPIOMUX
105 bool
106 help
107 Support for MSM V1 TLMM GPIOMUX architecture.
108
109endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
deleted file mode 100644
index 27c078a568df..000000000000
--- a/arch/arm/mach-msm/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
1obj-$(CONFIG_MSM_PROC_COMM) += clock.o
2
3obj-$(CONFIG_MSM_VIC) += irq-vic.o
4
5obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
6obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
7
8obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
9
10obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
11obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
12obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
13
14obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
15obj-$(CONFIG_MSM_SMD) += last_radio_log.o
16
17obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
18obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
22obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
23obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
deleted file mode 100644
index 9b803a578b4d..000000000000
--- a/arch/arm/mach-msm/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x10008000
2params_phys-y := 0x10000100
3initrd_phys-y := 0x10800000
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
deleted file mode 100644
index fc832040c6e9..000000000000
--- a/arch/arm/mach-msm/board-halibut.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/* linux/arch/arm/mach-msm/board-halibut.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/input.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/smc91x.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30#include <asm/setup.h>
31
32#include <mach/irqs.h>
33#include <mach/msm_iomap.h>
34
35#include <linux/mtd/nand.h>
36#include <linux/mtd/partitions.h>
37
38#include "devices.h"
39#include "common.h"
40
41static struct resource smc91x_resources[] = {
42 [0] = {
43 .start = 0x9C004300,
44 .end = 0x9C004400,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = MSM_GPIO_TO_INT(49),
49 .end = MSM_GPIO_TO_INT(49),
50 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
51 },
52};
53
54static struct smc91x_platdata smc91x_platdata = {
55 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
56};
57
58static struct platform_device smc91x_device = {
59 .name = "smc91x",
60 .id = 0,
61 .num_resources = ARRAY_SIZE(smc91x_resources),
62 .resource = smc91x_resources,
63 .dev.platform_data = &smc91x_platdata,
64};
65
66static struct platform_device *devices[] __initdata = {
67 &msm_clock_7x01a,
68 &msm_device_gpio_7201,
69 &msm_device_uart3,
70 &msm_device_smd,
71 &msm_device_nand,
72 &msm_device_hsusb,
73 &msm_device_i2c,
74 &smc91x_device,
75};
76
77static void __init halibut_init_early(void)
78{
79 arch_ioremap_caller = __msm_ioremap_caller;
80}
81
82static void __init halibut_init_irq(void)
83{
84 msm_init_irq();
85}
86
87static void __init halibut_init(void)
88{
89 platform_add_devices(devices, ARRAY_SIZE(devices));
90}
91
92static void __init halibut_map_io(void)
93{
94 msm_map_common_io();
95}
96
97static void __init halibut_init_late(void)
98{
99 smd_debugfs_init();
100}
101
102MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
103 .atag_offset = 0x100,
104 .map_io = halibut_map_io,
105 .init_early = halibut_init_early,
106 .init_irq = halibut_init_irq,
107 .init_machine = halibut_init,
108 .init_late = halibut_init_late,
109 .init_time = msm7x01_timer_init,
110MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
deleted file mode 100644
index 8f5ecdc4f3ce..000000000000
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/gpio.h>
18#include <linux/kernel.h>
19#include <linux/irq.h>
20#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/smsc911x.h>
24#include <linux/usb/msm_hsusb.h>
25#include <linux/clkdev.h>
26#include <linux/memblock.h>
27
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/memory.h>
31#include <asm/setup.h>
32
33#include <mach/clk.h>
34#include <mach/msm_iomap.h>
35#include <mach/dma.h>
36
37#include <mach/vreg.h>
38#include "devices.h"
39#include "gpiomux.h"
40#include "proc_comm.h"
41#include "common.h"
42
43static void __init msm7x30_fixup(struct tag *tag, char **cmdline)
44{
45 for (; tag->hdr.size; tag = tag_next(tag))
46 if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
47 tag->u.mem.start = 0;
48 tag->u.mem.size += SZ_2M;
49 }
50}
51
52static void __init msm7x30_reserve(void)
53{
54 memblock_remove(0x0, SZ_2M);
55}
56
57static int hsusb_phy_init_seq[] = {
58 0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */
59 0x02, 0x36, /* Disable CDR Auto Reset feature */
60 -1
61};
62
63static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
64{
65 int ret;
66
67 if (assert) {
68 ret = clk_reset(link_clk, CLK_RESET_ASSERT);
69 if (ret)
70 pr_err("usb hs_clk assert failed\n");
71 } else {
72 ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
73 if (ret)
74 pr_err("usb hs_clk deassert failed\n");
75 }
76 return ret;
77}
78
79static int hsusb_phy_clk_reset(struct clk *phy_clk)
80{
81 int ret;
82
83 ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
84 if (ret) {
85 pr_err("usb phy clk assert failed\n");
86 return ret;
87 }
88 usleep_range(10000, 12000);
89 ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
90 if (ret)
91 pr_err("usb phy clk deassert failed\n");
92 return ret;
93}
94
95static struct msm_otg_platform_data msm_otg_pdata = {
96 .phy_init_seq = hsusb_phy_init_seq,
97 .mode = USB_DR_MODE_PERIPHERAL,
98 .otg_control = OTG_PHY_CONTROL,
99 .link_clk_reset = hsusb_link_clk_reset,
100 .phy_clk_reset = hsusb_phy_clk_reset,
101};
102
103struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
104#ifdef CONFIG_SERIAL_MSM_CONSOLE
105 [49] = { /* UART2 RFR */
106 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
107 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
108 },
109 [50] = { /* UART2 CTS */
110 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
111 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
112 },
113 [51] = { /* UART2 RX */
114 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
115 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
116 },
117 [52] = { /* UART2 TX */
118 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
119 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
120 },
121#endif
122};
123
124static struct platform_device *devices[] __initdata = {
125 &msm_clock_7x30,
126 &msm_device_gpio_7x30,
127#if defined(CONFIG_SERIAL_MSM)
128 &msm_device_uart2,
129#endif
130 &msm_device_smd,
131 &msm_device_otg,
132 &msm_device_hsusb,
133 &msm_device_hsusb_host,
134};
135
136static void __init msm7x30_init_irq(void)
137{
138 msm_init_irq();
139}
140
141static void __init msm7x30_init(void)
142{
143 msm_device_otg.dev.platform_data = &msm_otg_pdata;
144 msm_device_hsusb.dev.parent = &msm_device_otg.dev;
145 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
146
147 platform_add_devices(devices, ARRAY_SIZE(devices));
148}
149
150static void __init msm7x30_map_io(void)
151{
152 msm_map_msm7x30_io();
153}
154
155static void __init msm7x30_init_late(void)
156{
157 smd_debugfs_init();
158}
159
160MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
161 .atag_offset = 0x100,
162 .fixup = msm7x30_fixup,
163 .reserve = msm7x30_reserve,
164 .map_io = msm7x30_map_io,
165 .init_irq = msm7x30_init_irq,
166 .init_machine = msm7x30_init,
167 .init_late = msm7x30_init_late,
168 .init_time = msm7x30_timer_init,
169MACHINE_END
170
171MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
172 .atag_offset = 0x100,
173 .fixup = msm7x30_fixup,
174 .reserve = msm7x30_reserve,
175 .map_io = msm7x30_map_io,
176 .init_irq = msm7x30_init_irq,
177 .init_machine = msm7x30_init,
178 .init_late = msm7x30_init_late,
179 .init_time = msm7x30_timer_init,
180MACHINE_END
181
182MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
183 .atag_offset = 0x100,
184 .fixup = msm7x30_fixup,
185 .reserve = msm7x30_reserve,
186 .map_io = msm7x30_map_io,
187 .init_irq = msm7x30_init_irq,
188 .init_machine = msm7x30_init,
189 .init_late = msm7x30_init_late,
190 .init_time = msm7x30_timer_init,
191MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
deleted file mode 100644
index 10016a3bc698..000000000000
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/gpio.h>
18#include <linux/kernel.h>
19#include <linux/irq.h>
20#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/usb/msm_hsusb.h>
23#include <linux/err.h>
24#include <linux/clkdev.h>
25#include <linux/smc91x.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/io.h>
30#include <asm/setup.h>
31
32#include <mach/irqs.h>
33#include <mach/sirc.h>
34#include <mach/vreg.h>
35#include <mach/clk.h>
36#include <linux/platform_data/mmc-msm_sdcc.h>
37
38#include "devices.h"
39#include "common.h"
40
41static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
42static const unsigned qsd8x50_surf_smc91x_gpio __initconst = 156;
43
44/* Leave smc91x resources empty here, as we'll fill them in
45 * at run-time: they vary from board to board, and the true
46 * configuration won't be known until boot.
47 */
48static struct resource smc91x_resources[] = {
49 [0] = {
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
54 },
55};
56
57static struct smc91x_platdata smc91x_platdata = {
58 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
59};
60
61static struct platform_device smc91x_device = {
62 .name = "smc91x",
63 .id = 0,
64 .num_resources = ARRAY_SIZE(smc91x_resources),
65 .resource = smc91x_resources,
66 .dev.platform_data = &smc91x_platdata,
67};
68
69static int __init msm_init_smc91x(void)
70{
71 if (machine_is_qsd8x50_surf()) {
72 smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
73 smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
74 smc91x_resources[1].start =
75 gpio_to_irq(qsd8x50_surf_smc91x_gpio);
76 smc91x_resources[1].end =
77 gpio_to_irq(qsd8x50_surf_smc91x_gpio);
78 platform_device_register(&smc91x_device);
79 }
80
81 return 0;
82}
83module_init(msm_init_smc91x);
84
85static int hsusb_phy_init_seq[] = {
86 0x08, 0x31, /* Increase HS Driver Amplitude */
87 0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
88 -1
89};
90
91static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
92{
93 int ret;
94
95 if (assert) {
96 ret = clk_reset(link_clk, CLK_RESET_ASSERT);
97 if (ret)
98 pr_err("usb hs_clk assert failed\n");
99 } else {
100 ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
101 if (ret)
102 pr_err("usb hs_clk deassert failed\n");
103 }
104 return ret;
105}
106
107static int hsusb_phy_clk_reset(struct clk *phy_clk)
108{
109 int ret;
110
111 ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
112 if (ret) {
113 pr_err("usb phy clk assert failed\n");
114 return ret;
115 }
116 usleep_range(10000, 12000);
117 ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
118 if (ret)
119 pr_err("usb phy clk deassert failed\n");
120 return ret;
121}
122
123static struct msm_otg_platform_data msm_otg_pdata = {
124 .phy_init_seq = hsusb_phy_init_seq,
125 .mode = USB_DR_MODE_PERIPHERAL,
126 .otg_control = OTG_PHY_CONTROL,
127 .link_clk_reset = hsusb_link_clk_reset,
128 .phy_clk_reset = hsusb_phy_clk_reset,
129};
130
131static struct platform_device *devices[] __initdata = {
132 &msm_clock_8x50,
133 &msm_device_gpio_8x50,
134 &msm_device_uart3,
135 &msm_device_smd,
136 &msm_device_otg,
137 &msm_device_hsusb,
138 &msm_device_hsusb_host,
139};
140
141static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
142 {51, "sdc1_dat_3"},
143 {52, "sdc1_dat_2"},
144 {53, "sdc1_dat_1"},
145 {54, "sdc1_dat_0"},
146 {55, "sdc1_cmd"},
147 {56, "sdc1_clk"}
148};
149
150static struct vreg *vreg_mmc;
151static unsigned long vreg_sts;
152
153static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
154{
155 int rc = 0;
156 struct platform_device *pdev;
157
158 pdev = container_of(dv, struct platform_device, dev);
159
160 if (vdd == 0) {
161 if (!vreg_sts)
162 return 0;
163
164 clear_bit(pdev->id, &vreg_sts);
165
166 if (!vreg_sts) {
167 rc = vreg_disable(vreg_mmc);
168 if (rc)
169 pr_err("vreg_mmc disable failed for slot "
170 "%d: %d\n", pdev->id, rc);
171 }
172 return 0;
173 }
174
175 if (!vreg_sts) {
176 rc = vreg_set_level(vreg_mmc, 2900);
177 if (rc)
178 pr_err("vreg_mmc set level failed for slot %d: %d\n",
179 pdev->id, rc);
180 rc = vreg_enable(vreg_mmc);
181 if (rc)
182 pr_err("vreg_mmc enable failed for slot %d: %d\n",
183 pdev->id, rc);
184 }
185 set_bit(pdev->id, &vreg_sts);
186 return 0;
187}
188
189static struct msm_mmc_gpio_data sdc1_gpio = {
190 .gpio = sdc1_gpio_cfg,
191 .size = ARRAY_SIZE(sdc1_gpio_cfg),
192};
193
194static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
195 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
196 .translate_vdd = msm_sdcc_setup_power,
197 .gpio_data = &sdc1_gpio,
198};
199
200static void __init qsd8x50_init_mmc(void)
201{
202 vreg_mmc = vreg_get(NULL, "gp5");
203
204 if (IS_ERR(vreg_mmc)) {
205 pr_err("vreg get for vreg_mmc failed (%ld)\n",
206 PTR_ERR(vreg_mmc));
207 return;
208 }
209
210 msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
211}
212
213static void __init qsd8x50_map_io(void)
214{
215 msm_map_qsd8x50_io();
216}
217
218static void __init qsd8x50_init_irq(void)
219{
220 msm_init_irq();
221 msm_init_sirc();
222}
223
224static void __init qsd8x50_init(void)
225{
226 msm_device_otg.dev.platform_data = &msm_otg_pdata;
227 msm_device_hsusb.dev.parent = &msm_device_otg.dev;
228 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
229 platform_add_devices(devices, ARRAY_SIZE(devices));
230 qsd8x50_init_mmc();
231}
232
233static void __init qsd8x50_init_late(void)
234{
235 smd_debugfs_init();
236}
237
238MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
239 .atag_offset = 0x100,
240 .map_io = qsd8x50_map_io,
241 .init_irq = qsd8x50_init_irq,
242 .init_machine = qsd8x50_init,
243 .init_late = qsd8x50_init_late,
244 .init_time = qsd8x50_timer_init,
245MACHINE_END
246
247MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
248 .atag_offset = 0x100,
249 .map_io = qsd8x50_map_io,
250 .init_irq = qsd8x50_init_irq,
251 .init_machine = qsd8x50_init,
252 .init_late = qsd8x50_init_late,
253 .init_time = qsd8x50_timer_init,
254MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
deleted file mode 100644
index e50967926dcd..000000000000
--- a/arch/arm/mach-msm/board-sapphire.c
+++ /dev/null
@@ -1,114 +0,0 @@
1/* linux/arch/arm/mach-msm/board-sapphire.c
2 * Copyright (C) 2007-2009 HTC Corporation.
3 * Author: Thomas Tsai <thomas_tsai@htc.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13*/
14#include <linux/gpio.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/input.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/device.h>
22
23#include <linux/delay.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30#include <mach/vreg.h>
31
32#include <asm/io.h>
33#include <asm/delay.h>
34#include <asm/setup.h>
35
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
38#include <linux/memblock.h>
39
40#include "gpio_chip.h"
41#include "board-sapphire.h"
42#include "proc_comm.h"
43#include "devices.h"
44#include "common.h"
45
46void msm_init_irq(void);
47void msm_init_gpio(void);
48
49static struct platform_device *devices[] __initdata = {
50 &msm_device_smd,
51 &msm_device_dmov,
52 &msm_device_nand,
53 &msm_device_uart1,
54 &msm_device_uart3,
55};
56
57void msm_timer_init(void);
58
59static void __init sapphire_init_irq(void)
60{
61 msm_init_irq();
62}
63
64static void __init sapphire_init(void)
65{
66 platform_add_devices(devices, ARRAY_SIZE(devices));
67}
68
69static struct map_desc sapphire_io_desc[] __initdata = {
70 {
71 .virtual = SAPPHIRE_CPLD_BASE,
72 .pfn = __phys_to_pfn(SAPPHIRE_CPLD_START),
73 .length = SAPPHIRE_CPLD_SIZE,
74 .type = MT_DEVICE_NONSHARED
75 }
76};
77
78static void __init sapphire_fixup(struct tag *tags, char **cmdline)
79{
80 int smi_sz = parse_tag_smi((const struct tag *)tags);
81
82 if (smi_sz == 32) {
83 memblock_add(PHYS_OFFSET, 84*SZ_1M);
84 } else if (smi_sz == 64) {
85 memblock_add(PHYS_OFFSET, 101*SZ_1M);
86 } else {
87 memblock_add(PHYS_OFFSET, 101*SZ_1M);
88 /* Give a default value when not get smi size */
89 smi_sz = 64;
90 }
91}
92
93static void __init sapphire_map_io(void)
94{
95 msm_map_common_io();
96 iotable_init(sapphire_io_desc, ARRAY_SIZE(sapphire_io_desc));
97 msm_clock_init();
98}
99
100static void __init sapphire_init_late(void)
101{
102 smd_debugfs_init();
103}
104
105MACHINE_START(SAPPHIRE, "sapphire")
106/* Maintainer: Brian Swetland <swetland@google.com> */
107 .atag_offset = 0x100,
108 .fixup = sapphire_fixup,
109 .map_io = sapphire_map_io,
110 .init_irq = sapphire_init_irq,
111 .init_machine = sapphire_init,
112 .init_late = sapphire_init_late,
113 .init_time = msm_timer_init,
114MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
deleted file mode 100644
index 722ad63b7edc..000000000000
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ /dev/null
@@ -1,233 +0,0 @@
1/*
2 * linux/arch/arm/mach-msm/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 * Copyright (C) 2008 Google, Inc.
6 * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/gpio.h>
20
21#include "board-trout.h"
22
23static uint8_t trout_int_mask[2] = {
24 [0] = 0xff, /* mask all interrupts */
25 [1] = 0xff,
26};
27static uint8_t trout_sleep_int_mask[] = {
28 [0] = 0xff,
29 [1] = 0xff,
30};
31
32struct msm_gpio_chip {
33 struct gpio_chip chip;
34 void __iomem *reg; /* Base of register bank */
35 u8 shadow;
36};
37
38#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
39
40static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
41{
42 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
43 unsigned mask = 1 << offset;
44
45 return !!(readb(msm_gpio->reg) & mask);
46}
47
48static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
49{
50 struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
51 unsigned mask = 1 << offset;
52
53 if (val)
54 msm_gpio->shadow |= mask;
55 else
56 msm_gpio->shadow &= ~mask;
57
58 writeb(msm_gpio->shadow, msm_gpio->reg);
59}
60
61static int msm_gpiolib_direction_input(struct gpio_chip *chip,
62 unsigned offset)
63{
64 msm_gpiolib_set(chip, offset, 0);
65 return 0;
66}
67
68static int msm_gpiolib_direction_output(struct gpio_chip *chip,
69 unsigned offset, int val)
70{
71 msm_gpiolib_set(chip, offset, val);
72 return 0;
73}
74
75static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
76{
77 return TROUT_GPIO_TO_INT(offset + chip->base);
78}
79
80#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
81 { \
82 .chip = { \
83 .label = name, \
84 .direction_input = msm_gpiolib_direction_input,\
85 .direction_output = msm_gpiolib_direction_output, \
86 .get = msm_gpiolib_get, \
87 .set = msm_gpiolib_set, \
88 .to_irq = trout_gpio_to_irq, \
89 .base = base_gpio, \
90 .ngpio = 8, \
91 }, \
92 .reg = reg_num + TROUT_CPLD_BASE, \
93 .shadow = shadow_val, \
94 }
95
96static struct msm_gpio_chip msm_gpio_banks[] = {
97#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
98 /* H2W pins <-> UART1 */
99 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
100#else
101 /* H2W pins <-> UART3, Bluetooth <-> UART1 */
102 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80),
103#endif
104 /* I2C pull */
105 TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04),
106 TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0),
107 /* mmdi 32k en */
108 TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04),
109 TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0),
110 TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0),
111 TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
112};
113
114static void trout_gpio_irq_ack(struct irq_data *d)
115{
116 int bank = TROUT_INT_TO_BANK(d->irq);
117 uint8_t mask = TROUT_INT_TO_MASK(d->irq);
118 int reg = TROUT_BANK_TO_STAT_REG(bank);
119 /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
120 writeb(mask, TROUT_CPLD_BASE + reg);
121}
122
123static void trout_gpio_irq_mask(struct irq_data *d)
124{
125 unsigned long flags;
126 uint8_t reg_val;
127 int bank = TROUT_INT_TO_BANK(d->irq);
128 uint8_t mask = TROUT_INT_TO_MASK(d->irq);
129 int reg = TROUT_BANK_TO_MASK_REG(bank);
130
131 local_irq_save(flags);
132 reg_val = trout_int_mask[bank] |= mask;
133 /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
134 d->irq, bank, reg_val);*/
135 writeb(reg_val, TROUT_CPLD_BASE + reg);
136 local_irq_restore(flags);
137}
138
139static void trout_gpio_irq_unmask(struct irq_data *d)
140{
141 unsigned long flags;
142 uint8_t reg_val;
143 int bank = TROUT_INT_TO_BANK(d->irq);
144 uint8_t mask = TROUT_INT_TO_MASK(d->irq);
145 int reg = TROUT_BANK_TO_MASK_REG(bank);
146
147 local_irq_save(flags);
148 reg_val = trout_int_mask[bank] &= ~mask;
149 /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
150 d->irq, bank, reg_val);*/
151 writeb(reg_val, TROUT_CPLD_BASE + reg);
152 local_irq_restore(flags);
153}
154
155int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
156{
157 unsigned long flags;
158 int bank = TROUT_INT_TO_BANK(d->irq);
159 uint8_t mask = TROUT_INT_TO_MASK(d->irq);
160
161 local_irq_save(flags);
162 if(on)
163 trout_sleep_int_mask[bank] &= ~mask;
164 else
165 trout_sleep_int_mask[bank] |= mask;
166 local_irq_restore(flags);
167 return 0;
168}
169
170static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
171{
172 int j, m;
173 unsigned v;
174 int bank;
175 int stat_reg;
176 int int_base = TROUT_INT_START;
177 uint8_t int_mask;
178
179 for (bank = 0; bank < 2; bank++) {
180 stat_reg = TROUT_BANK_TO_STAT_REG(bank);
181 v = readb(TROUT_CPLD_BASE + stat_reg);
182 int_mask = trout_int_mask[bank];
183 if (v & int_mask) {
184 writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg);
185 printk(KERN_ERR "trout_gpio_irq_handler: got masked "
186 "interrupt: %d:%02x\n", bank, v & int_mask);
187 }
188 v &= ~int_mask;
189 while (v) {
190 m = v & -v;
191 j = fls(m) - 1;
192 /*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b"
193 "it %d irq %d\n", bank, v, m, j, int_base + j);*/
194 v &= ~m;
195 generic_handle_irq(int_base + j);
196 }
197 int_base += TROUT_INT_BANK0_COUNT;
198 }
199 desc->irq_data.chip->irq_ack(&desc->irq_data);
200}
201
202static struct irq_chip trout_gpio_irq_chip = {
203 .name = "troutgpio",
204 .irq_ack = trout_gpio_irq_ack,
205 .irq_mask = trout_gpio_irq_mask,
206 .irq_unmask = trout_gpio_irq_unmask,
207 .irq_set_wake = trout_gpio_irq_set_wake,
208};
209
210/*
211 * Called from the processor-specific init to enable GPIO pin support.
212 */
213int __init trout_init_gpio(void)
214{
215 int i;
216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
217 irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
218 handle_edge_irq);
219 set_irq_flags(i, IRQF_VALID);
220 }
221
222 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
223 gpiochip_add(&msm_gpio_banks[i].chip);
224
225 irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
226 irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
227 irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
228
229 return 0;
230}
231
232postcore_initcall(trout_init_gpio);
233
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
deleted file mode 100644
index 3723e55819d6..000000000000
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ /dev/null
@@ -1,185 +0,0 @@
1/* linux/arch/arm/mach-msm/board-trout-mmc.c
2** Author: Brian Swetland <swetland@google.com>
3*/
4#include <linux/gpio.h>
5#include <linux/kernel.h>
6#include <linux/init.h>
7#include <linux/platform_device.h>
8#include <linux/delay.h>
9#include <linux/mmc/host.h>
10#include <linux/mmc/sdio_ids.h>
11#include <linux/err.h>
12#include <linux/debugfs.h>
13
14#include <asm/io.h>
15
16#include <mach/vreg.h>
17
18#include <linux/platform_data/mmc-msm_sdcc.h>
19
20#include "devices.h"
21
22#include "board-trout.h"
23
24#include "proc_comm.h"
25
26#define DEBUG_SDSLOT_VDD 1
27
28/* ---- COMMON ---- */
29static void config_gpio_table(uint32_t *table, int len)
30{
31 int n;
32 unsigned id;
33 for(n = 0; n < len; n++) {
34 id = table[n];
35 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0);
36 }
37}
38
39/* ---- SDCARD ---- */
40
41static uint32_t sdcard_on_gpio_table[] = {
42 PCOM_GPIO_CFG(62, 2, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA), /* CLK */
43 PCOM_GPIO_CFG(63, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* CMD */
44 PCOM_GPIO_CFG(64, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT3 */
45 PCOM_GPIO_CFG(65, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT2 */
46 PCOM_GPIO_CFG(66, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT1 */
47 PCOM_GPIO_CFG(67, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT0 */
48};
49
50static uint32_t sdcard_off_gpio_table[] = {
51 PCOM_GPIO_CFG(62, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CLK */
52 PCOM_GPIO_CFG(63, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CMD */
53 PCOM_GPIO_CFG(64, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT3 */
54 PCOM_GPIO_CFG(65, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT2 */
55 PCOM_GPIO_CFG(66, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT1 */
56 PCOM_GPIO_CFG(67, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT0 */
57};
58
59static uint opt_disable_sdcard;
60
61static int __init trout_disablesdcard_setup(char *str)
62{
63 int cal = simple_strtol(str, NULL, 0);
64
65 opt_disable_sdcard = cal;
66 return 1;
67}
68
69__setup("board_trout.disable_sdcard=", trout_disablesdcard_setup);
70
71static struct vreg *vreg_sdslot; /* SD slot power */
72
73struct mmc_vdd_xlat {
74 int mask;
75 int level;
76};
77
78static struct mmc_vdd_xlat mmc_vdd_table[] = {
79 { MMC_VDD_165_195, 1800 },
80 { MMC_VDD_20_21, 2050 },
81 { MMC_VDD_21_22, 2150 },
82 { MMC_VDD_22_23, 2250 },
83 { MMC_VDD_23_24, 2350 },
84 { MMC_VDD_24_25, 2450 },
85 { MMC_VDD_25_26, 2550 },
86 { MMC_VDD_26_27, 2650 },
87 { MMC_VDD_27_28, 2750 },
88 { MMC_VDD_28_29, 2850 },
89 { MMC_VDD_29_30, 2950 },
90};
91
92static unsigned int sdslot_vdd = 0xffffffff;
93static unsigned int sdslot_vreg_enabled;
94
95static uint32_t trout_sdslot_switchvdd(struct device *dev, unsigned int vdd)
96{
97 int i, rc;
98
99 BUG_ON(!vreg_sdslot);
100
101 if (vdd == sdslot_vdd)
102 return 0;
103
104 sdslot_vdd = vdd;
105
106 if (vdd == 0) {
107#if DEBUG_SDSLOT_VDD
108 printk("%s: Disabling SD slot power\n", __func__);
109#endif
110 config_gpio_table(sdcard_off_gpio_table,
111 ARRAY_SIZE(sdcard_off_gpio_table));
112 vreg_disable(vreg_sdslot);
113 sdslot_vreg_enabled = 0;
114 return 0;
115 }
116
117 if (!sdslot_vreg_enabled) {
118 rc = vreg_enable(vreg_sdslot);
119 if (rc) {
120 printk(KERN_ERR "%s: Error enabling vreg (%d)\n",
121 __func__, rc);
122 }
123 config_gpio_table(sdcard_on_gpio_table,
124 ARRAY_SIZE(sdcard_on_gpio_table));
125 sdslot_vreg_enabled = 1;
126 }
127
128 for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) {
129 if (mmc_vdd_table[i].mask == (1 << vdd)) {
130#if DEBUG_SDSLOT_VDD
131 printk("%s: Setting level to %u\n",
132 __func__, mmc_vdd_table[i].level);
133#endif
134 rc = vreg_set_level(vreg_sdslot,
135 mmc_vdd_table[i].level);
136 if (rc) {
137 printk(KERN_ERR
138 "%s: Error setting vreg level (%d)\n",
139 __func__, rc);
140 }
141 return 0;
142 }
143 }
144
145 printk(KERN_ERR "%s: Invalid VDD %d specified\n", __func__, vdd);
146 return 0;
147}
148
149static unsigned int trout_sdslot_status(struct device *dev)
150{
151 unsigned int status;
152
153 status = (unsigned int) gpio_get_value(TROUT_GPIO_SDMC_CD_N);
154 return (!status);
155}
156
157#define TROUT_MMC_VDD MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \
158 | MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \
159 | MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \
160 | MMC_VDD_28_29 | MMC_VDD_29_30
161
162static struct msm_mmc_platform_data trout_sdslot_data = {
163 .ocr_mask = TROUT_MMC_VDD,
164 .status = trout_sdslot_status,
165 .translate_vdd = trout_sdslot_switchvdd,
166};
167
168int __init trout_init_mmc(unsigned int sys_rev)
169{
170 sdslot_vreg_enabled = 0;
171
172 vreg_sdslot = vreg_get(0, "gp6");
173 if (IS_ERR(vreg_sdslot))
174 return PTR_ERR(vreg_sdslot);
175
176 irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
177
178 if (!opt_disable_sdcard)
179 msm_add_sdcc(2, &trout_sdslot_data,
180 TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0);
181 else
182 printk(KERN_INFO "trout: SD-Card interface disabled\n");
183 return 0;
184}
185
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
deleted file mode 100644
index 77b0a26f897f..000000000000
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ /dev/null
@@ -1,292 +0,0 @@
1/* linux/arch/arm/mach-msm/board-trout-mddi.c
2** Author: Brian Swetland <swetland@google.com>
3*/
4#include <linux/gpio.h>
5#include <linux/kernel.h>
6#include <linux/init.h>
7#include <linux/platform_device.h>
8#include <linux/delay.h>
9#include <linux/leds.h>
10#include <linux/err.h>
11
12#include <asm/io.h>
13#include <asm/mach-types.h>
14#include <asm/system_info.h>
15
16#include <linux/platform_data/video-msm_fb.h>
17#include <mach/vreg.h>
18
19#include "board-trout.h"
20#include "proc_comm.h"
21#include "clock-pcom.h"
22#include "devices.h"
23
24#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
25
26#define MDDI_CLIENT_CORE_BASE 0x108000
27#define LCD_CONTROL_BLOCK_BASE 0x110000
28#define SPI_BLOCK_BASE 0x120000
29#define I2C_BLOCK_BASE 0x130000
30#define PWM_BLOCK_BASE 0x140000
31#define GPIO_BLOCK_BASE 0x150000
32#define SYSTEM_BLOCK1_BASE 0x160000
33#define SYSTEM_BLOCK2_BASE 0x170000
34
35
36#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
37#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
38#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
39
40#define V_VDDE2E_VDD2_GPIO 0
41#define MDDI_RST_N 82
42
43#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
44#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
45#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
46#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
47#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
48#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
49#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
50#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
51#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
52#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
53#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
54#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
55#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
56#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
57#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
58#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
59#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
60#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
61#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
62#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
63#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
64#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
65
66#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
67#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
68#define START (LCD_CONTROL_BLOCK_BASE|0x08)
69#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
70#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
71#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
72#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
73#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
74#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
75#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
76#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
77#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
78#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
79#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
80#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
81#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
82#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
83#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
84#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
85#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
86#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
87#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
88#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
89#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
90#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
91#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
92#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
93#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
94#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
95#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
96#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
97#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
98#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
99#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
100#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
101
102#define SSICTL (SPI_BLOCK_BASE|0x00)
103#define SSITIME (SPI_BLOCK_BASE|0x04)
104#define SSITX (SPI_BLOCK_BASE|0x08)
105#define SSIRX (SPI_BLOCK_BASE|0x0C)
106#define SSIINTC (SPI_BLOCK_BASE|0x10)
107#define SSIINTS (SPI_BLOCK_BASE|0x14)
108#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
109#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
110#define SSIID (SPI_BLOCK_BASE|0x20)
111
112#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
113#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
114#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
115#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
116#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
117
118#define GPIODATA (GPIO_BLOCK_BASE|0x00)
119#define GPIODIR (GPIO_BLOCK_BASE|0x04)
120#define GPIOIS (GPIO_BLOCK_BASE|0x08)
121#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
122#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
123#define GPIOIE (GPIO_BLOCK_BASE|0x14)
124#define GPIORIS (GPIO_BLOCK_BASE|0x18)
125#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
126#define GPIOIC (GPIO_BLOCK_BASE|0x20)
127#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
128#define GPIOPC (GPIO_BLOCK_BASE|0x28)
129#define GPIOID (GPIO_BLOCK_BASE|0x30)
130
131#define SPI_WRITE(reg, val) \
132 { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
133 { 0, 5 },
134
135#define SPI_WRITE1(reg) \
136 { SSITX, (reg) & 0xff }, \
137 { 0, 5 },
138
139struct mddi_table {
140 uint32_t reg;
141 uint32_t value;
142};
143static struct mddi_table mddi_toshiba_init_table[] = {
144 { DPSET0, 0x09e90046 },
145 { DPSET1, 0x00000118 },
146 { DPSUS, 0x00000000 },
147 { DPRUN, 0x00000001 },
148 { 1, 14 }, /* msleep 14 */
149 { SYSCKENA, 0x00000001 },
150 { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
151
152 { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
153 { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
154 { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
155 { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
156 { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
157
158 { GPIOIBE, 0x000003FF },
159 { GPIOIS, 0x00000000 },
160 { GPIOIC, 0x000003FF },
161 { GPIOIE, 0x00000000 },
162
163 { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
164 { 1, 1 }, /* msleep 1 */
165 { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
166 { DRAMPWR, 0x00000001 }, /* eDRAM power */
167};
168
169#define GPIOSEL_VWAKEINT (1U << 0)
170#define INTMASK_VWAKEOUT (1U << 0)
171
172
173static int trout_new_backlight = 1;
174static struct vreg *vreg_mddi_1v5;
175static struct vreg *vreg_lcm_2v85;
176
177static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
178 struct mddi_table *table, size_t count)
179{
180 int i;
181 for (i = 0; i < count; i++) {
182 uint32_t reg = table[i].reg;
183 uint32_t value = table[i].value;
184
185 if (reg == 0)
186 udelay(value);
187 else if (reg == 1)
188 msleep(value);
189 else
190 client_data->remote_write(client_data, value, reg);
191 }
192}
193
194static int trout_mddi_toshiba_client_init(
195 struct msm_mddi_bridge_platform_data *bridge_data,
196 struct msm_mddi_client_data *client_data)
197{
198 int panel_id;
199
200 client_data->auto_hibernate(client_data, 0);
201 trout_process_mddi_table(client_data, mddi_toshiba_init_table,
202 ARRAY_SIZE(mddi_toshiba_init_table));
203 client_data->auto_hibernate(client_data, 1);
204 panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
205 if (panel_id > 1) {
206 printk(KERN_WARNING "unknown panel id at mddi_enable\n");
207 return -1;
208 }
209 return 0;
210}
211
212static int trout_mddi_toshiba_client_uninit(
213 struct msm_mddi_bridge_platform_data *bridge_data,
214 struct msm_mddi_client_data *client_data)
215{
216 return 0;
217}
218
219static struct resource resources_msm_fb[] = {
220 {
221 .start = MSM_FB_BASE,
222 .end = MSM_FB_BASE + MSM_FB_SIZE,
223 .flags = IORESOURCE_MEM,
224 },
225};
226
227struct msm_mddi_bridge_platform_data toshiba_client_data = {
228 .init = trout_mddi_toshiba_client_init,
229 .uninit = trout_mddi_toshiba_client_uninit,
230 .fb_data = {
231 .xres = 320,
232 .yres = 480,
233 .width = 45,
234 .height = 67,
235 .output_format = 0,
236 },
237};
238
239static struct msm_mddi_platform_data mddi_pdata = {
240 .clk_rate = 122880000,
241 .fb_resource = resources_msm_fb,
242 .num_clients = 1,
243 .client_platform_data = {
244 {
245 .product_id = (0xd263 << 16 | 0),
246 .name = "mddi_c_d263_0000",
247 .id = 0,
248 .client_data = &toshiba_client_data,
249 .clk_rate = 0,
250 },
251 },
252};
253
254int __init trout_init_panel(void)
255{
256 int rc;
257
258 if (!machine_is_trout())
259 return 0;
260 vreg_mddi_1v5 = vreg_get(0, "gp2");
261 if (IS_ERR(vreg_mddi_1v5))
262 return PTR_ERR(vreg_mddi_1v5);
263 vreg_lcm_2v85 = vreg_get(0, "gp4");
264 if (IS_ERR(vreg_lcm_2v85))
265 return PTR_ERR(vreg_lcm_2v85);
266
267 trout_new_backlight = system_rev >= 5;
268 if (trout_new_backlight) {
269 uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
270 GPIO_NO_PULL, GPIO_8MA);
271 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
272 } else {
273 uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
274 GPIO_NO_PULL, GPIO_8MA);
275 uint32_t id = P_GP_CLK;
276 uint32_t rate = 19200000;
277
278 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
279
280 msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
281 if (id < 0)
282 pr_err("trout_init_panel: set clock rate failed\n");
283 }
284
285 rc = platform_device_register(&msm_device_mdp);
286 if (rc)
287 return rc;
288 msm_device_mddi0.dev.platform_data = &mddi_pdata;
289 return platform_device_register(&msm_device_mddi0);
290}
291
292device_initcall(trout_init_panel);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
deleted file mode 100644
index ba3edd3a46cb..000000000000
--- a/arch/arm/mach-msm/board-trout.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/* linux/arch/arm/mach-msm/board-trout.c
2 *
3 * Copyright (C) 2009 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#define pr_fmt(fmt) "%s: " fmt, __func__
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/clkdev.h>
22#include <linux/memblock.h>
23
24#include <asm/system_info.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/setup.h>
29
30#include <mach/hardware.h>
31#include <mach/msm_iomap.h>
32
33#include "devices.h"
34#include "board-trout.h"
35#include "common.h"
36
37extern int trout_init_mmc(unsigned int);
38
39static struct platform_device *devices[] __initdata = {
40 &msm_clock_7x01a,
41 &msm_device_gpio_7201,
42 &msm_device_uart3,
43 &msm_device_smd,
44 &msm_device_nand,
45 &msm_device_hsusb,
46 &msm_device_i2c,
47};
48
49static void __init trout_init_early(void)
50{
51 arch_ioremap_caller = __msm_ioremap_caller;
52}
53
54static void __init trout_init_irq(void)
55{
56 msm_init_irq();
57}
58
59static void __init trout_fixup(struct tag *tags, char **cmdline)
60{
61 memblock_add(PHYS_OFFSET, 101*SZ_1M);
62}
63
64static void __init trout_init(void)
65{
66 int rc;
67
68 platform_add_devices(devices, ARRAY_SIZE(devices));
69
70 if (IS_ENABLED(CONFIG_MMC)) {
71 rc = trout_init_mmc(system_rev);
72 if (rc)
73 pr_crit("MMC init failure (%d)\n", rc);
74 }
75}
76
77static struct map_desc trout_io_desc[] __initdata = {
78 {
79 .virtual = (unsigned long)TROUT_CPLD_BASE,
80 .pfn = __phys_to_pfn(TROUT_CPLD_START),
81 .length = TROUT_CPLD_SIZE,
82 .type = MT_DEVICE_NONSHARED
83 }
84};
85
86static void __init trout_map_io(void)
87{
88 msm_map_common_io();
89 iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
90
91#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
92 /* route UART3 to the "H2W" extended usb connector */
93 writeb(0x80, TROUT_CPLD_BASE + 0x00);
94#endif
95}
96
97static void __init trout_init_late(void)
98{
99 smd_debugfs_init();
100}
101
102MACHINE_START(TROUT, "HTC Dream")
103 .atag_offset = 0x100,
104 .fixup = trout_fixup,
105 .map_io = trout_map_io,
106 .init_early = trout_init_early,
107 .init_irq = trout_init_irq,
108 .init_machine = trout_init,
109 .init_late = trout_init_late,
110 .init_time = msm7x01_timer_init,
111MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
deleted file mode 100644
index adb757abbb92..000000000000
--- a/arch/arm/mach-msm/board-trout.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/* linux/arch/arm/mach-msm/board-trout.h
2** Author: Brian Swetland <swetland@google.com>
3*/
4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
6
7#include "common.h"
8
9#define MSM_SMI_BASE 0x00000000
10#define MSM_SMI_SIZE 0x00800000
11
12#define MSM_EBI_BASE 0x10000000
13#define MSM_EBI_SIZE 0x06e00000
14
15#define MSM_PMEM_GPU0_BASE 0x00000000
16#define MSM_PMEM_GPU0_SIZE 0x00700000
17
18#define MSM_PMEM_MDP_BASE 0x02000000
19#define MSM_PMEM_MDP_SIZE 0x00800000
20
21#define MSM_PMEM_ADSP_BASE 0x02800000
22#define MSM_PMEM_ADSP_SIZE 0x00800000
23
24#define MSM_PMEM_CAMERA_BASE 0x03000000
25#define MSM_PMEM_CAMERA_SIZE 0x00800000
26
27#define MSM_FB_BASE 0x03800000
28#define MSM_FB_SIZE 0x00100000
29
30#define MSM_LINUX_BASE MSM_EBI_BASE
31#define MSM_LINUX_SIZE 0x06500000
32
33#define MSM_PMEM_GPU1_SIZE 0x800000
34#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
35
36#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000)
37#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K)
38
39#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
40#error invalid memory map
41#endif
42
43#define DECLARE_MSM_IOMAP
44#include <mach/msm_iomap.h>
45
46#define TROUT_4_BALL_UP_0 1
47#define TROUT_4_BALL_LEFT_0 18
48#define TROUT_4_BALL_DOWN_0 57
49#define TROUT_4_BALL_RIGHT_0 91
50
51#define TROUT_5_BALL_UP_0 94
52#define TROUT_5_BALL_LEFT_0 18
53#define TROUT_5_BALL_DOWN_0 90
54#define TROUT_5_BALL_RIGHT_0 19
55
56#define TROUT_POWER_KEY 20
57
58#define TROUT_4_TP_LS_EN 19
59#define TROUT_5_TP_LS_EN 1
60
61#define TROUT_CPLD_BASE IOMEM(0xE8100000)
62#define TROUT_CPLD_START 0x98000000
63#define TROUT_CPLD_SIZE SZ_4K
64
65#define TROUT_GPIO_CABLE_IN1 (83)
66#define TROUT_GPIO_CABLE_IN2 (49)
67
68#define TROUT_GPIO_START (128)
69
70#define TROUT_GPIO_INT_MASK0_REG (0x0c)
71#define TROUT_GPIO_INT_STAT0_REG (0x0e)
72#define TROUT_GPIO_INT_MASK1_REG (0x14)
73#define TROUT_GPIO_INT_STAT1_REG (0x10)
74
75#define TROUT_GPIO_HAPTIC_PWM (28)
76#define TROUT_GPIO_PS_HOLD (25)
77
78#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00)
79#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08)
80#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10)
81#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18)
82#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20)
83#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28)
84#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30)
85#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48)
86
87#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0)
88#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1)
89#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2)
90#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3)
91#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4)
92#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5)
93#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6)
94#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7)
95
96#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0)
97#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1)
98#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2)
99#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3)
100#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4)
101#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5)
102#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6)
103#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7)
104
105#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0)
106#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1)
107#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2)
108#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3)
109#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4)
110#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5)
111#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6)
112#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7)
113
114#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0)
115#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1)
116#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2)
117#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3)
118
119#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0)
120#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1)
121#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2)
122#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3)
123#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4)
124#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5)
125#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6)
126#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7)
127#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N)
128#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N)
129
130#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0)
131#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1)
132#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4)
133#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5)
134#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6)
135#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7)
136
137#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0)
138#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N)
139#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
140#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
141
142#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
143 (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
144
145#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
146#define TROUT_INT_BANK0_COUNT (8)
147#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
148#define TROUT_INT_BANK1_COUNT (1)
149#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
150 TROUT_INT_BANK1_COUNT - 1)
151#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
152 (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
153 (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
154
155#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
156#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
157#define TROUT_BANK_TO_MASK_REG(bank) \
158 (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
159#define TROUT_BANK_TO_STAT_REG(bank) \
160 (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
161
162#endif /* GUARD */
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
deleted file mode 100644
index f5b69d736ee5..000000000000
--- a/arch/arm/mach-msm/clock-pcom.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/module.h>
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22
23#include <mach/clk.h>
24
25#include "proc_comm.h"
26#include "clock.h"
27#include "clock-pcom.h"
28
29struct clk_pcom {
30 unsigned id;
31 unsigned long flags;
32 struct msm_clk msm_clk;
33};
34
35static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
36{
37 return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
38}
39
40static int pc_clk_enable(struct clk_hw *hw)
41{
42 unsigned id = to_clk_pcom(hw)->id;
43 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
44 if (rc < 0)
45 return rc;
46 else
47 return (int)id < 0 ? -EINVAL : 0;
48}
49
50static void pc_clk_disable(struct clk_hw *hw)
51{
52 unsigned id = to_clk_pcom(hw)->id;
53 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
54}
55
56static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
57{
58 int rc;
59 unsigned id = to_clk_pcom(hw)->id;
60
61 if (action == CLK_RESET_ASSERT)
62 rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
63 else
64 rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_DEASSERT, &id, NULL);
65
66 if (rc < 0)
67 return rc;
68 else
69 return (int)id < 0 ? -EINVAL : 0;
70}
71
72static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
73 unsigned long p_rate)
74{
75 struct clk_pcom *p = to_clk_pcom(hw);
76 unsigned id = p->id, rate = new_rate;
77 int rc;
78
79 /*
80 * The rate _might_ be rounded off to the nearest KHz value by the
81 * remote function. So a return value of 0 doesn't necessarily mean
82 * that the exact rate was set successfully.
83 */
84 if (p->flags & CLKFLAG_MIN)
85 rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
86 else
87 rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
88 if (rc < 0)
89 return rc;
90 else
91 return (int)id < 0 ? -EINVAL : 0;
92}
93
94static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
95{
96 unsigned id = to_clk_pcom(hw)->id;
97 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
98 return 0;
99 else
100 return id;
101}
102
103static int pc_clk_is_enabled(struct clk_hw *hw)
104{
105 unsigned id = to_clk_pcom(hw)->id;
106 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
107 return 0;
108 else
109 return id;
110}
111
112static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
113 unsigned long *p_rate)
114{
115 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
116 return rate;
117}
118
119static struct clk_ops clk_ops_pcom = {
120 .enable = pc_clk_enable,
121 .disable = pc_clk_disable,
122 .set_rate = pc_clk_set_rate,
123 .recalc_rate = pc_clk_recalc_rate,
124 .is_enabled = pc_clk_is_enabled,
125 .round_rate = pc_clk_round_rate,
126};
127
128static int msm_clock_pcom_probe(struct platform_device *pdev)
129{
130 const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
131 int i, ret;
132
133 for (i = 0; i < pdata->num_lookups; i++) {
134 const struct clk_pcom_desc *desc = &pdata->lookup[i];
135 struct clk *c;
136 struct clk_pcom *p;
137 struct clk_hw *hw;
138 struct clk_init_data init;
139
140 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
141 if (!p)
142 return -ENOMEM;
143
144 p->id = desc->id;
145 p->flags = desc->flags;
146 p->msm_clk.reset = pc_clk_reset;
147
148 hw = &p->msm_clk.hw;
149 hw->init = &init;
150
151 init.name = desc->name;
152 init.ops = &clk_ops_pcom;
153 init.num_parents = 0;
154 init.flags = CLK_IS_ROOT;
155
156 if (!(p->flags & CLKFLAG_AUTO_OFF))
157 init.flags |= CLK_IGNORE_UNUSED;
158
159 c = devm_clk_register(&pdev->dev, hw);
160 ret = clk_register_clkdev(c, desc->con, desc->dev);
161 if (ret)
162 return ret;
163 }
164
165 return 0;
166}
167
168static struct platform_driver msm_clock_pcom_driver = {
169 .probe = msm_clock_pcom_probe,
170 .driver = {
171 .name = "msm-clock-pcom",
172 },
173};
174module_platform_driver(msm_clock_pcom_driver);
175
176MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
deleted file mode 100644
index 5bb164fd46a8..000000000000
--- a/arch/arm/mach-msm/clock-pcom.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
15#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
16
17/* clock IDs used by the modem processor */
18
19#define P_ACPU_CLK 0 /* Applications processor clock */
20#define P_ADM_CLK 1 /* Applications data mover clock */
21#define P_ADSP_CLK 2 /* ADSP clock */
22#define P_EBI1_CLK 3 /* External bus interface 1 clock */
23#define P_EBI2_CLK 4 /* External bus interface 2 clock */
24#define P_ECODEC_CLK 5 /* External CODEC clock */
25#define P_EMDH_CLK 6 /* External MDDI host clock */
26#define P_GP_CLK 7 /* General purpose clock */
27#define P_GRP_3D_CLK 8 /* Graphics clock */
28#define P_I2C_CLK 9 /* I2C clock */
29#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
30#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
31#define P_IMEM_CLK 12 /* Internal graphics memory clock */
32#define P_MDC_CLK 13 /* MDDI client clock */
33#define P_MDP_CLK 14 /* Mobile display processor clock */
34#define P_PBUS_CLK 15 /* Peripheral bus clock */
35#define P_PCM_CLK 16 /* PCM clock */
36#define P_PMDH_CLK 17 /* Primary MDDI host clock */
37#define P_SDAC_CLK 18 /* Stereo DAC clock */
38#define P_SDC1_CLK 19 /* Secure Digital Card clocks */
39#define P_SDC1_P_CLK 20
40#define P_SDC2_CLK 21
41#define P_SDC2_P_CLK 22
42#define P_SDC3_CLK 23
43#define P_SDC3_P_CLK 24
44#define P_SDC4_CLK 25
45#define P_SDC4_P_CLK 26
46#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */
47#define P_TSIF_REF_CLK 28
48#define P_TV_DAC_CLK 29 /* TV clocks */
49#define P_TV_ENC_CLK 30
50#define P_UART1_CLK 31 /* UART clocks */
51#define P_UART2_CLK 32
52#define P_UART3_CLK 33
53#define P_UART1DM_CLK 34
54#define P_UART2DM_CLK 35
55#define P_USB_HS_CLK 36 /* High speed USB core clock */
56#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */
57#define P_USB_OTG_CLK 38 /* Full speed USB clock */
58#define P_VDC_CLK 39 /* Video controller clock */
59#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */
60#define P_VFE_CLK 41 /* VFE MDDI client clock */
61#define P_MDP_LCDC_PCLK_CLK 42
62#define P_MDP_LCDC_PAD_PCLK_CLK 43
63#define P_MDP_VSYNC_CLK 44
64#define P_SPI_CLK 45
65#define P_VFE_AXI_CLK 46
66#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */
67#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */
68#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */
69#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */
70#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */
71#define P_USB_PHY_CLK 52 /* USB PHY clock */
72#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
73#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
74#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
75#define P_CAM_M_CLK 56
76#define P_CAMIF_PAD_P_CLK 57
77#define P_GRP_2D_CLK 58
78#define P_GRP_2D_P_CLK 59
79#define P_I2S_CLK 60
80#define P_JPEG_CLK 61
81#define P_JPEG_P_CLK 62
82#define P_LPA_CODEC_CLK 63
83#define P_LPA_CORE_CLK 64
84#define P_LPA_P_CLK 65
85#define P_MDC_IO_CLK 66
86#define P_MDC_P_CLK 67
87#define P_MFC_CLK 68
88#define P_MFC_DIV2_CLK 69
89#define P_MFC_P_CLK 70
90#define P_QUP_I2C_CLK 71
91#define P_ROTATOR_IMEM_CLK 72
92#define P_ROTATOR_P_CLK 73
93#define P_VFE_CAMIF_CLK 74
94#define P_VFE_P_CLK 75
95#define P_VPE_CLK 76
96#define P_I2C_2_CLK 77
97#define P_MI2S_CODEC_RX_S_CLK 78
98#define P_MI2S_CODEC_RX_M_CLK 79
99#define P_MI2S_CODEC_TX_S_CLK 80
100#define P_MI2S_CODEC_TX_M_CLK 81
101#define P_PMDH_P_CLK 82
102#define P_EMDH_P_CLK 83
103#define P_SPI_P_CLK 84
104#define P_TSIF_P_CLK 85
105#define P_MDP_P_CLK 86
106#define P_SDAC_M_CLK 87
107#define P_MI2S_S_CLK 88
108#define P_MI2S_M_CLK 89
109#define P_AXI_ROTATOR_CLK 90
110#define P_HDMI_CLK 91
111#define P_CSI0_CLK 92
112#define P_CSI0_VFE_CLK 93
113#define P_CSI0_P_CLK 94
114#define P_CSI1_CLK 95
115#define P_CSI1_VFE_CLK 96
116#define P_CSI1_P_CLK 97
117#define P_GSBI_CLK 98
118#define P_GSBI_P_CLK 99
119#define P_CE_CLK 100 /* Crypto engine */
120#define P_CODEC_SSBI_CLK 101
121
122#define P_NR_CLKS 102
123
124struct clk_pcom_desc {
125 unsigned id;
126 const char *name;
127 const char *con;
128 const char *dev;
129 unsigned long flags;
130};
131
132struct pcom_clk_pdata {
133 struct clk_pcom_desc *lookup;
134 u32 num_lookups;
135};
136
137#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
138 .id = P_##clk_id, \
139 .name = #clk_id, \
140 .con = clk_name, \
141 .dev = clk_dev, \
142 .flags = clk_flags, \
143 }
144
145#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
deleted file mode 100644
index 35ea02b52483..000000000000
--- a/arch/arm/mach-msm/clock.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* arch/arm/mach-msm/clock.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/module.h>
19
20#include "clock.h"
21
22int clk_reset(struct clk *clk, enum clk_reset_action action)
23{
24 struct clk_hw *hw = __clk_get_hw(clk);
25 struct msm_clk *m = to_msm_clk(hw);
26 return m->reset(hw, action);
27}
28EXPORT_SYMBOL(clk_reset);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
deleted file mode 100644
index 42d29dd7aafc..000000000000
--- a/arch/arm/mach-msm/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/* arch/arm/mach-msm/clock.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
18#define __ARCH_ARM_MACH_MSM_CLOCK_H
19
20#include <linux/clk-provider.h>
21#include <mach/clk.h>
22
23#define CLK_FIRST_AVAILABLE_FLAG 0x00000100
24#define CLKFLAG_AUTO_OFF 0x00000200
25#define CLKFLAG_MIN 0x00000400
26#define CLKFLAG_MAX 0x00000800
27
28#define OFF CLKFLAG_AUTO_OFF
29#define CLK_MIN CLKFLAG_MIN
30#define CLK_MAX CLKFLAG_MAX
31#define CLK_MINMAX (CLK_MIN | CLK_MAX)
32
33struct msm_clk {
34 int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
35 struct clk_hw hw;
36};
37
38static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
39{
40 return container_of(hw, struct msm_clk, hw);
41}
42
43#endif
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
deleted file mode 100644
index 572479a3c7be..000000000000
--- a/arch/arm/mach-msm/common.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_COMMON_H
13#define __MACH_COMMON_H
14
15extern void msm7x01_timer_init(void);
16extern void msm7x30_timer_init(void);
17extern void qsd8x50_timer_init(void);
18
19extern void msm_map_common_io(void);
20extern void msm_map_msm7x30_io(void);
21extern void msm_map_qsd8x50_io(void);
22
23extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
24 unsigned int mtype, void *caller);
25
26struct msm_mmc_platform_data;
27
28extern void msm_add_devices(void);
29extern void msm_init_irq(void);
30extern void msm_init_gpio(void);
31extern int msm_add_sdcc(unsigned int controller,
32 struct msm_mmc_platform_data *plat,
33 unsigned int stat_irq, unsigned long stat_irq_flags);
34
35#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
36extern int smd_debugfs_init(void);
37#else
38static inline int smd_debugfs_init(void) { return 0; }
39#endif
40
41#endif
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
deleted file mode 100644
index d83404d4b328..000000000000
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ /dev/null
@@ -1,480 +0,0 @@
1/* linux/arch/arm/mach-msm/devices.c
2 *
3 * Copyright (C) 2008 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/clkdev.h>
19
20#include <mach/irqs.h>
21#include <mach/msm_iomap.h>
22#include "devices.h"
23
24#include <asm/mach/flash.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27
28#include "clock.h"
29#include "clock-pcom.h"
30#include <linux/platform_data/mmc-msm_sdcc.h>
31
32static struct resource msm_gpio_resources[] = {
33 {
34 .start = 32 + 0,
35 .end = 32 + 0,
36 .flags = IORESOURCE_IRQ,
37 },
38 {
39 .start = 32 + 1,
40 .end = 32 + 1,
41 .flags = IORESOURCE_IRQ,
42 },
43 {
44 .start = 0xa9200800,
45 .end = 0xa9200800 + SZ_4K - 1,
46 .flags = IORESOURCE_MEM,
47 .name = "gpio1"
48 },
49 {
50 .start = 0xa9300C00,
51 .end = 0xa9300C00 + SZ_4K - 1,
52 .flags = IORESOURCE_MEM,
53 .name = "gpio2"
54 },
55};
56
57struct platform_device msm_device_gpio_7201 = {
58 .name = "gpio-msm-7201",
59 .num_resources = ARRAY_SIZE(msm_gpio_resources),
60 .resource = msm_gpio_resources,
61};
62
63static struct resource resources_uart1[] = {
64 {
65 .start = INT_UART1,
66 .end = INT_UART1,
67 .flags = IORESOURCE_IRQ,
68 },
69 {
70 .start = MSM_UART1_PHYS,
71 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
72 .flags = IORESOURCE_MEM,
73 .name = "uart_resource"
74 },
75};
76
77static struct resource resources_uart2[] = {
78 {
79 .start = INT_UART2,
80 .end = INT_UART2,
81 .flags = IORESOURCE_IRQ,
82 },
83 {
84 .start = MSM_UART2_PHYS,
85 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
86 .flags = IORESOURCE_MEM,
87 .name = "uart_resource"
88 },
89};
90
91static struct resource resources_uart3[] = {
92 {
93 .start = INT_UART3,
94 .end = INT_UART3,
95 .flags = IORESOURCE_IRQ,
96 },
97 {
98 .start = MSM_UART3_PHYS,
99 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
100 .flags = IORESOURCE_MEM,
101 .name = "uart_resource"
102 },
103};
104
105struct platform_device msm_device_uart1 = {
106 .name = "msm_serial",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(resources_uart1),
109 .resource = resources_uart1,
110};
111
112struct platform_device msm_device_uart2 = {
113 .name = "msm_serial",
114 .id = 1,
115 .num_resources = ARRAY_SIZE(resources_uart2),
116 .resource = resources_uart2,
117};
118
119struct platform_device msm_device_uart3 = {
120 .name = "msm_serial",
121 .id = 2,
122 .num_resources = ARRAY_SIZE(resources_uart3),
123 .resource = resources_uart3,
124};
125
126static struct resource resources_i2c[] = {
127 {
128 .start = MSM_I2C_PHYS,
129 .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
130 .flags = IORESOURCE_MEM,
131 },
132 {
133 .start = INT_PWB_I2C,
134 .end = INT_PWB_I2C,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139struct platform_device msm_device_i2c = {
140 .name = "msm_i2c",
141 .id = 0,
142 .num_resources = ARRAY_SIZE(resources_i2c),
143 .resource = resources_i2c,
144};
145
146static struct resource resources_hsusb[] = {
147 {
148 .start = MSM_HSUSB_PHYS,
149 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
150 .flags = IORESOURCE_MEM,
151 },
152 {
153 .start = INT_USB_HS,
154 .end = INT_USB_HS,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159struct platform_device msm_device_hsusb = {
160 .name = "msm_hsusb",
161 .id = -1,
162 .num_resources = ARRAY_SIZE(resources_hsusb),
163 .resource = resources_hsusb,
164 .dev = {
165 .coherent_dma_mask = 0xffffffff,
166 },
167};
168
169struct flash_platform_data msm_nand_data = {
170 .parts = NULL,
171 .nr_parts = 0,
172};
173
174static struct resource resources_nand[] = {
175 [0] = {
176 .start = 7,
177 .end = 7,
178 .flags = IORESOURCE_DMA,
179 },
180};
181
182struct platform_device msm_device_nand = {
183 .name = "msm_nand",
184 .id = -1,
185 .num_resources = ARRAY_SIZE(resources_nand),
186 .resource = resources_nand,
187 .dev = {
188 .platform_data = &msm_nand_data,
189 },
190};
191
192struct platform_device msm_device_smd = {
193 .name = "msm_smd",
194 .id = -1,
195};
196
197static struct resource resources_sdc1[] = {
198 {
199 .start = MSM_SDC1_PHYS,
200 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .start = INT_SDC1_0,
205 .end = INT_SDC1_0,
206 .flags = IORESOURCE_IRQ,
207 .name = "cmd_irq",
208 },
209 {
210 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
211 .name = "status_irq"
212 },
213 {
214 .start = 8,
215 .end = 8,
216 .flags = IORESOURCE_DMA,
217 },
218};
219
220static struct resource resources_sdc2[] = {
221 {
222 .start = MSM_SDC2_PHYS,
223 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
224 .flags = IORESOURCE_MEM,
225 },
226 {
227 .start = INT_SDC2_0,
228 .end = INT_SDC2_0,
229 .flags = IORESOURCE_IRQ,
230 .name = "cmd_irq",
231 },
232 {
233 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
234 .name = "status_irq"
235 },
236 {
237 .start = 8,
238 .end = 8,
239 .flags = IORESOURCE_DMA,
240 },
241};
242
243static struct resource resources_sdc3[] = {
244 {
245 .start = MSM_SDC3_PHYS,
246 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 {
250 .start = INT_SDC3_0,
251 .end = INT_SDC3_0,
252 .flags = IORESOURCE_IRQ,
253 .name = "cmd_irq",
254 },
255 {
256 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
257 .name = "status_irq"
258 },
259 {
260 .start = 8,
261 .end = 8,
262 .flags = IORESOURCE_DMA,
263 },
264};
265
266static struct resource resources_sdc4[] = {
267 {
268 .start = MSM_SDC4_PHYS,
269 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = INT_SDC4_0,
274 .end = INT_SDC4_0,
275 .flags = IORESOURCE_IRQ,
276 .name = "cmd_irq",
277 },
278 {
279 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
280 .name = "status_irq"
281 },
282 {
283 .start = 8,
284 .end = 8,
285 .flags = IORESOURCE_DMA,
286 },
287};
288
289struct platform_device msm_device_sdc1 = {
290 .name = "msm_sdcc",
291 .id = 1,
292 .num_resources = ARRAY_SIZE(resources_sdc1),
293 .resource = resources_sdc1,
294 .dev = {
295 .coherent_dma_mask = 0xffffffff,
296 },
297};
298
299struct platform_device msm_device_sdc2 = {
300 .name = "msm_sdcc",
301 .id = 2,
302 .num_resources = ARRAY_SIZE(resources_sdc2),
303 .resource = resources_sdc2,
304 .dev = {
305 .coherent_dma_mask = 0xffffffff,
306 },
307};
308
309struct platform_device msm_device_sdc3 = {
310 .name = "msm_sdcc",
311 .id = 3,
312 .num_resources = ARRAY_SIZE(resources_sdc3),
313 .resource = resources_sdc3,
314 .dev = {
315 .coherent_dma_mask = 0xffffffff,
316 },
317};
318
319struct platform_device msm_device_sdc4 = {
320 .name = "msm_sdcc",
321 .id = 4,
322 .num_resources = ARRAY_SIZE(resources_sdc4),
323 .resource = resources_sdc4,
324 .dev = {
325 .coherent_dma_mask = 0xffffffff,
326 },
327};
328
329static struct platform_device *msm_sdcc_devices[] __initdata = {
330 &msm_device_sdc1,
331 &msm_device_sdc2,
332 &msm_device_sdc3,
333 &msm_device_sdc4,
334};
335
336int __init msm_add_sdcc(unsigned int controller,
337 struct msm_mmc_platform_data *plat,
338 unsigned int stat_irq, unsigned long stat_irq_flags)
339{
340 struct platform_device *pdev;
341 struct resource *res;
342
343 if (controller < 1 || controller > 4)
344 return -EINVAL;
345
346 pdev = msm_sdcc_devices[controller-1];
347 pdev->dev.platform_data = plat;
348
349 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
350 if (!res)
351 return -EINVAL;
352 else if (stat_irq) {
353 res->start = res->end = stat_irq;
354 res->flags &= ~IORESOURCE_DISABLED;
355 res->flags |= stat_irq_flags;
356 }
357
358 return platform_device_register(pdev);
359}
360
361static struct resource resources_mddi0[] = {
362 {
363 .start = MSM_PMDH_PHYS,
364 .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = INT_MDDI_PRI,
369 .end = INT_MDDI_PRI,
370 .flags = IORESOURCE_IRQ,
371 },
372};
373
374static struct resource resources_mddi1[] = {
375 {
376 .start = MSM_EMDH_PHYS,
377 .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .start = INT_MDDI_EXT,
382 .end = INT_MDDI_EXT,
383 .flags = IORESOURCE_IRQ,
384 },
385};
386
387struct platform_device msm_device_mddi0 = {
388 .name = "msm_mddi",
389 .id = 0,
390 .num_resources = ARRAY_SIZE(resources_mddi0),
391 .resource = resources_mddi0,
392 .dev = {
393 .coherent_dma_mask = 0xffffffff,
394 },
395};
396
397struct platform_device msm_device_mddi1 = {
398 .name = "msm_mddi",
399 .id = 1,
400 .num_resources = ARRAY_SIZE(resources_mddi1),
401 .resource = resources_mddi1,
402 .dev = {
403 .coherent_dma_mask = 0xffffffff,
404 },
405};
406
407static struct resource resources_mdp[] = {
408 {
409 .start = MSM_MDP_PHYS,
410 .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
411 .name = "mdp",
412 .flags = IORESOURCE_MEM
413 },
414 {
415 .start = INT_MDP,
416 .end = INT_MDP,
417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421struct platform_device msm_device_mdp = {
422 .name = "msm_mdp",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(resources_mdp),
425 .resource = resources_mdp,
426};
427
428static struct clk_pcom_desc msm_clocks_7x01a[] = {
429 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
430 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
431 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
432 CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
433 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
434 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF),
435 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
436 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF),
437 CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0),
438 CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
439 CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
440 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
441 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
442 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
443 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0),
444 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
445 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
446 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
447 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
448 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
449 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
450 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
451 CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
452 CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
453 CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
454 CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
455 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
456 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
457 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
458 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
459 CLK_PCOM("core", UART1_CLK, "msm_serial.0", OFF),
460 CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0),
461 CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF),
462 CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF),
463 CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0),
464 CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF),
465 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF),
466 CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
467 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ),
468 CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
469 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
470};
471
472static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
473 .lookup = msm_clocks_7x01a,
474 .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
475};
476
477struct platform_device msm_clock_7x01a = {
478 .name = "msm-clock-pcom",
479 .dev.platform_data = &msm_clock_7x01a_pdata,
480};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
deleted file mode 100644
index c15ea8ab20a7..000000000000
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <linux/dma-mapping.h>
20#include <linux/clkdev.h>
21#include <mach/irqs.h>
22#include <mach/msm_iomap.h>
23#include <mach/dma.h>
24
25#include "devices.h"
26#include "smd_private.h"
27#include "common.h"
28
29#include <asm/mach/flash.h>
30
31#include "clock.h"
32#include "clock-pcom.h"
33
34#include <linux/platform_data/mmc-msm_sdcc.h>
35
36static struct resource msm_gpio_resources[] = {
37 {
38 .start = 32 + 18,
39 .end = 32 + 18,
40 .flags = IORESOURCE_IRQ,
41 },
42 {
43 .start = 32 + 19,
44 .end = 32 + 19,
45 .flags = IORESOURCE_IRQ,
46 },
47 {
48 .start = 0xac001000,
49 .end = 0xac001000 + SZ_4K - 1,
50 .flags = IORESOURCE_MEM,
51 .name = "gpio1"
52 },
53 {
54 .start = 0xac101400,
55 .end = 0xac101400 + SZ_4K - 1,
56 .flags = IORESOURCE_MEM,
57 .name = "gpio2"
58 },
59};
60
61struct platform_device msm_device_gpio_7x30 = {
62 .name = "gpio-msm-7x30",
63 .num_resources = ARRAY_SIZE(msm_gpio_resources),
64 .resource = msm_gpio_resources,
65};
66
67static struct resource resources_uart2[] = {
68 {
69 .start = INT_UART2,
70 .end = INT_UART2,
71 .flags = IORESOURCE_IRQ,
72 },
73 {
74 .start = MSM_UART2_PHYS,
75 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
76 .flags = IORESOURCE_MEM,
77 .name = "uart_resource"
78 },
79};
80
81struct platform_device msm_device_uart2 = {
82 .name = "msm_serial",
83 .id = 1,
84 .num_resources = ARRAY_SIZE(resources_uart2),
85 .resource = resources_uart2,
86};
87
88struct platform_device msm_device_smd = {
89 .name = "msm_smd",
90 .id = -1,
91};
92
93static struct resource resources_otg[] = {
94 {
95 .start = MSM_HSUSB_PHYS,
96 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
97 .flags = IORESOURCE_MEM,
98 },
99 {
100 .start = INT_USB_HS,
101 .end = INT_USB_HS,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106struct platform_device msm_device_otg = {
107 .name = "msm_otg",
108 .id = -1,
109 .num_resources = ARRAY_SIZE(resources_otg),
110 .resource = resources_otg,
111 .dev = {
112 .coherent_dma_mask = 0xffffffff,
113 },
114};
115
116static struct resource resources_hsusb[] = {
117 {
118 .start = MSM_HSUSB_PHYS,
119 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
120 .flags = IORESOURCE_MEM,
121 },
122 {
123 .start = INT_USB_HS,
124 .end = INT_USB_HS,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129struct platform_device msm_device_hsusb = {
130 .name = "msm_hsusb",
131 .id = -1,
132 .num_resources = ARRAY_SIZE(resources_hsusb),
133 .resource = resources_hsusb,
134 .dev = {
135 .coherent_dma_mask = 0xffffffff,
136 },
137};
138
139static u64 dma_mask = 0xffffffffULL;
140static struct resource resources_hsusb_host[] = {
141 {
142 .start = MSM_HSUSB_PHYS,
143 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
144 .flags = IORESOURCE_MEM,
145 },
146 {
147 .start = INT_USB_HS,
148 .end = INT_USB_HS,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153struct platform_device msm_device_hsusb_host = {
154 .name = "msm_hsusb_host",
155 .id = -1,
156 .num_resources = ARRAY_SIZE(resources_hsusb_host),
157 .resource = resources_hsusb_host,
158 .dev = {
159 .dma_mask = &dma_mask,
160 .coherent_dma_mask = 0xffffffffULL,
161 },
162};
163
164static struct clk_pcom_desc msm_clocks_7x30[] = {
165 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
166 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
167 CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
168 CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF),
169 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
170 CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0),
171 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
172 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
173 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
174 CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF),
175 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
176 CLK_PCOM("grp_2d_clk", GRP_2D_CLK, NULL, 0),
177 CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0),
178 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
179 CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0),
180 CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0),
181 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
182 CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
183 CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF),
184 CLK_PCOM("lpa_codec_clk", LPA_CODEC_CLK, NULL, 0),
185 CLK_PCOM("lpa_core_clk", LPA_CORE_CLK, NULL, 0),
186 CLK_PCOM("lpa_pclk", LPA_P_CLK, NULL, 0),
187 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
188 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
189 CLK_PCOM("mddi_pclk", PMDH_P_CLK, NULL, 0),
190 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
191 CLK_PCOM("mdp_pclk", MDP_P_CLK, NULL, 0),
192 CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
193 CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
194 CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
195 CLK_PCOM("mfc_clk", MFC_CLK, NULL, 0),
196 CLK_PCOM("mfc_div2_clk", MFC_DIV2_CLK, NULL, 0),
197 CLK_PCOM("mfc_pclk", MFC_P_CLK, NULL, 0),
198 CLK_PCOM("mi2s_m_clk", MI2S_M_CLK, NULL, 0),
199 CLK_PCOM("mi2s_s_clk", MI2S_S_CLK, NULL, 0),
200 CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK, NULL, 0),
201 CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK, NULL, 0),
202 CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK, NULL, 0),
203 CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK, NULL, 0),
204 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
205 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
206 CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK, NULL, 0),
207 CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF),
208 CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF),
209 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
210 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
211 CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0),
212 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
213 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
214 CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0),
215 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
216 CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
217 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
218 CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF),
219 CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
220 CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
221 CLK_PCOM("usb_hs2_core_clk", USB_HS2_CORE_CLK, NULL, OFF),
222 CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
223 CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
224 CLK_PCOM("usb_hs3_core_clk", USB_HS3_CORE_CLK, NULL, OFF),
225 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
226 CLK_PCOM("vfe_camif_clk", VFE_CAMIF_CLK, NULL, 0),
227 CLK_PCOM("vfe_clk", VFE_CLK, NULL, 0),
228 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, 0),
229 CLK_PCOM("vfe_pclk", VFE_P_CLK, NULL, OFF),
230 CLK_PCOM("vpe_clk", VPE_CLK, NULL, 0),
231
232 /* 7x30 v2 hardware only. */
233 CLK_PCOM("csi_clk", CSI0_CLK, NULL, 0),
234 CLK_PCOM("csi_pclk", CSI0_P_CLK, NULL, 0),
235 CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0),
236};
237
238static struct pcom_clk_pdata msm_clock_7x30_pdata = {
239 .lookup = msm_clocks_7x30,
240 .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
241};
242
243struct platform_device msm_clock_7x30 = {
244 .name = "msm-clock-pcom",
245 .dev.platform_data = &msm_clock_7x30_pdata,
246};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
deleted file mode 100644
index 9e1e9ce07b1a..000000000000
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ /dev/null
@@ -1,388 +0,0 @@
1/*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/clkdev.h>
19#include <linux/dma-mapping.h>
20
21#include <mach/irqs.h>
22#include <mach/msm_iomap.h>
23#include <mach/dma.h>
24
25#include "devices.h"
26#include "common.h"
27
28#include <asm/mach/flash.h>
29
30#include <linux/platform_data/mmc-msm_sdcc.h>
31#include "clock.h"
32#include "clock-pcom.h"
33
34static struct resource msm_gpio_resources[] = {
35 {
36 .start = 64 + 165 + 9,
37 .end = 64 + 165 + 9,
38 .flags = IORESOURCE_IRQ,
39 },
40 {
41 .start = 64 + 165 + 10,
42 .end = 64 + 165 + 10,
43 .flags = IORESOURCE_IRQ,
44 },
45 {
46 .start = 0xa9000800,
47 .end = 0xa9000800 + SZ_4K - 1,
48 .flags = IORESOURCE_MEM,
49 .name = "gpio1"
50 },
51 {
52 .start = 0xa9100C00,
53 .end = 0xa9100C00 + SZ_4K - 1,
54 .flags = IORESOURCE_MEM,
55 .name = "gpio2"
56 },
57};
58
59struct platform_device msm_device_gpio_8x50 = {
60 .name = "gpio-msm-8x50",
61 .num_resources = ARRAY_SIZE(msm_gpio_resources),
62 .resource = msm_gpio_resources,
63};
64
65static struct resource resources_uart3[] = {
66 {
67 .start = INT_UART3,
68 .end = INT_UART3,
69 .flags = IORESOURCE_IRQ,
70 },
71 {
72 .start = MSM_UART3_PHYS,
73 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75 .name = "uart_resource"
76 },
77};
78
79struct platform_device msm_device_uart3 = {
80 .name = "msm_serial",
81 .id = 2,
82 .num_resources = ARRAY_SIZE(resources_uart3),
83 .resource = resources_uart3,
84};
85
86struct platform_device msm_device_smd = {
87 .name = "msm_smd",
88 .id = -1,
89};
90
91static struct resource resources_otg[] = {
92 {
93 .start = MSM_HSUSB_PHYS,
94 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .start = INT_USB_HS,
99 .end = INT_USB_HS,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104struct platform_device msm_device_otg = {
105 .name = "msm_otg",
106 .id = -1,
107 .num_resources = ARRAY_SIZE(resources_otg),
108 .resource = resources_otg,
109 .dev = {
110 .coherent_dma_mask = 0xffffffff,
111 },
112};
113
114static struct resource resources_hsusb[] = {
115 {
116 .start = MSM_HSUSB_PHYS,
117 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
118 .flags = IORESOURCE_MEM,
119 },
120 {
121 .start = INT_USB_HS,
122 .end = INT_USB_HS,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device msm_device_hsusb = {
128 .name = "msm_hsusb",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(resources_hsusb),
131 .resource = resources_hsusb,
132 .dev = {
133 .coherent_dma_mask = 0xffffffff,
134 },
135};
136
137static u64 dma_mask = 0xffffffffULL;
138static struct resource resources_hsusb_host[] = {
139 {
140 .start = MSM_HSUSB_PHYS,
141 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
142 .flags = IORESOURCE_MEM,
143 },
144 {
145 .start = INT_USB_HS,
146 .end = INT_USB_HS,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151struct platform_device msm_device_hsusb_host = {
152 .name = "msm_hsusb_host",
153 .id = -1,
154 .num_resources = ARRAY_SIZE(resources_hsusb_host),
155 .resource = resources_hsusb_host,
156 .dev = {
157 .dma_mask = &dma_mask,
158 .coherent_dma_mask = 0xffffffffULL,
159 },
160};
161
162static struct resource resources_sdc1[] = {
163 {
164 .start = MSM_SDC1_PHYS,
165 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 {
169 .start = INT_SDC1_0,
170 .end = INT_SDC1_0,
171 .flags = IORESOURCE_IRQ,
172 .name = "cmd_irq",
173 },
174 {
175 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
176 .name = "status_irq"
177 },
178 {
179 .start = 8,
180 .end = 8,
181 .flags = IORESOURCE_DMA,
182 },
183};
184
185static struct resource resources_sdc2[] = {
186 {
187 .start = MSM_SDC2_PHYS,
188 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .start = INT_SDC2_0,
193 .end = INT_SDC2_0,
194 .flags = IORESOURCE_IRQ,
195 .name = "cmd_irq",
196 },
197 {
198 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
199 .name = "status_irq"
200 },
201 {
202 .start = 8,
203 .end = 8,
204 .flags = IORESOURCE_DMA,
205 },
206};
207
208static struct resource resources_sdc3[] = {
209 {
210 .start = MSM_SDC3_PHYS,
211 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
212 .flags = IORESOURCE_MEM,
213 },
214 {
215 .start = INT_SDC3_0,
216 .end = INT_SDC3_0,
217 .flags = IORESOURCE_IRQ,
218 .name = "cmd_irq",
219 },
220 {
221 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
222 .name = "status_irq"
223 },
224 {
225 .start = 8,
226 .end = 8,
227 .flags = IORESOURCE_DMA,
228 },
229};
230
231static struct resource resources_sdc4[] = {
232 {
233 .start = MSM_SDC4_PHYS,
234 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
235 .flags = IORESOURCE_MEM,
236 },
237 {
238 .start = INT_SDC4_0,
239 .end = INT_SDC4_0,
240 .flags = IORESOURCE_IRQ,
241 .name = "cmd_irq",
242 },
243 {
244 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
245 .name = "status_irq"
246 },
247 {
248 .start = 8,
249 .end = 8,
250 .flags = IORESOURCE_DMA,
251 },
252};
253
254struct platform_device msm_device_sdc1 = {
255 .name = "msm_sdcc",
256 .id = 1,
257 .num_resources = ARRAY_SIZE(resources_sdc1),
258 .resource = resources_sdc1,
259 .dev = {
260 .coherent_dma_mask = 0xffffffff,
261 },
262};
263
264struct platform_device msm_device_sdc2 = {
265 .name = "msm_sdcc",
266 .id = 2,
267 .num_resources = ARRAY_SIZE(resources_sdc2),
268 .resource = resources_sdc2,
269 .dev = {
270 .coherent_dma_mask = 0xffffffff,
271 },
272};
273
274struct platform_device msm_device_sdc3 = {
275 .name = "msm_sdcc",
276 .id = 3,
277 .num_resources = ARRAY_SIZE(resources_sdc3),
278 .resource = resources_sdc3,
279 .dev = {
280 .coherent_dma_mask = 0xffffffff,
281 },
282};
283
284struct platform_device msm_device_sdc4 = {
285 .name = "msm_sdcc",
286 .id = 4,
287 .num_resources = ARRAY_SIZE(resources_sdc4),
288 .resource = resources_sdc4,
289 .dev = {
290 .coherent_dma_mask = 0xffffffff,
291 },
292};
293
294static struct platform_device *msm_sdcc_devices[] __initdata = {
295 &msm_device_sdc1,
296 &msm_device_sdc2,
297 &msm_device_sdc3,
298 &msm_device_sdc4,
299};
300
301int __init msm_add_sdcc(unsigned int controller,
302 struct msm_mmc_platform_data *plat,
303 unsigned int stat_irq, unsigned long stat_irq_flags)
304{
305 struct platform_device *pdev;
306 struct resource *res;
307
308 if (controller < 1 || controller > 4)
309 return -EINVAL;
310
311 pdev = msm_sdcc_devices[controller-1];
312 pdev->dev.platform_data = plat;
313
314 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
315 if (!res)
316 return -EINVAL;
317 else if (stat_irq) {
318 res->start = res->end = stat_irq;
319 res->flags &= ~IORESOURCE_DISABLED;
320 res->flags |= stat_irq_flags;
321 }
322
323 return platform_device_register(pdev);
324}
325
326static struct clk_pcom_desc msm_clocks_8x50[] = {
327 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
328 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
329 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
330 CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
331 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
332 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
333 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
334 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
335 CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0),
336 CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
337 CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
338 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
339 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
340 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
341 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
342 CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
343 CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
344 CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
345 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
346 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
347 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
348 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
349 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
350 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
351 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
352 CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
353 CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
354 CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
355 CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
356 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
357 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
358 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
359 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
360 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
361 CLK_PCOM("core", UART1_CLK, NULL, OFF),
362 CLK_PCOM("core", UART2_CLK, NULL, 0),
363 CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF),
364 CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF),
365 CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0),
366 CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
367 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
368 CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
369 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
370 CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
371 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
372 CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
373 CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
374 CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
375 CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
376 CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
377 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
378};
379
380static struct pcom_clk_pdata msm_clock_8x50_pdata = {
381 .lookup = msm_clocks_8x50,
382 .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
383};
384
385struct platform_device msm_clock_8x50 = {
386 .name = "msm-clock-pcom",
387 .dev.platform_data = &msm_clock_8x50_pdata,
388};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
deleted file mode 100644
index dccefad9f9b9..000000000000
--- a/arch/arm/mach-msm/devices.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/* linux/arch/arm/mach-msm/devices.h
2 *
3 * Copyright (C) 2008 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
17#define __ARCH_ARM_MACH_MSM_DEVICES_H
18
19extern struct platform_device msm_device_gpio_7201;
20extern struct platform_device msm_device_gpio_7x30;
21extern struct platform_device msm_device_gpio_8x50;
22
23extern struct platform_device msm_device_uart1;
24extern struct platform_device msm_device_uart2;
25extern struct platform_device msm_device_uart3;
26
27extern struct platform_device msm8960_device_uart_gsbi2;
28extern struct platform_device msm8960_device_uart_gsbi5;
29
30extern struct platform_device msm_device_sdc1;
31extern struct platform_device msm_device_sdc2;
32extern struct platform_device msm_device_sdc3;
33extern struct platform_device msm_device_sdc4;
34
35extern struct platform_device msm_device_hsusb;
36extern struct platform_device msm_device_otg;
37extern struct platform_device msm_device_hsusb_host;
38
39extern struct platform_device msm_device_i2c;
40
41extern struct platform_device msm_device_smd;
42
43extern struct platform_device msm_device_nand;
44
45extern struct platform_device msm_device_mddi0;
46extern struct platform_device msm_device_mddi1;
47extern struct platform_device msm_device_mdp;
48
49extern struct platform_device msm_clock_7x01a;
50extern struct platform_device msm_clock_7x30;
51extern struct platform_device msm_clock_8x50;
52
53#endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
deleted file mode 100644
index fb9762464718..000000000000
--- a/arch/arm/mach-msm/dma.c
+++ /dev/null
@@ -1,298 +0,0 @@
1/* linux/arch/arm/mach-msm/dma.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/completion.h>
21#include <linux/module.h>
22#include <mach/dma.h>
23#include <mach/msm_iomap.h>
24
25#define MSM_DMOV_CHANNEL_COUNT 16
26
27#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
28#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
29#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
30#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
31
32#if defined(CONFIG_ARCH_MSM7X30)
33#define DMOV_SD_AARM DMOV_SD2
34#else
35#define DMOV_SD_AARM DMOV_SD3
36#endif
37
38#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
39#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
40#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
41#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
42#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
43#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
44#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
45#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
46
47#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
48#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
49
50#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
51
52enum {
53 MSM_DMOV_PRINT_ERRORS = 1,
54 MSM_DMOV_PRINT_IO = 2,
55 MSM_DMOV_PRINT_FLOW = 4
56};
57
58static DEFINE_SPINLOCK(msm_dmov_lock);
59static struct clk *msm_dmov_clk;
60static unsigned int channel_active;
61static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
62static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
63unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS;
64
65#define MSM_DMOV_DPRINTF(mask, format, args...) \
66 do { \
67 if ((mask) & msm_dmov_print_mask) \
68 printk(KERN_ERR format, args); \
69 } while (0)
70#define PRINT_ERROR(format, args...) \
71 MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_ERRORS, format, args);
72#define PRINT_IO(format, args...) \
73 MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_IO, format, args);
74#define PRINT_FLOW(format, args...) \
75 MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args);
76
77void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
78{
79 writel((graceful << 31), DMOV_FLUSH0(id));
80}
81EXPORT_SYMBOL_GPL(msm_dmov_stop_cmd);
82
83void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
84{
85 unsigned long irq_flags;
86 unsigned int status;
87
88 spin_lock_irqsave(&msm_dmov_lock, irq_flags);
89 if (!channel_active)
90 clk_enable(msm_dmov_clk);
91 dsb();
92 status = readl(DMOV_STATUS(id));
93 if (list_empty(&ready_commands[id]) &&
94 (status & DMOV_STATUS_CMD_PTR_RDY)) {
95#if 0
96 if (list_empty(&active_commands[id])) {
97 PRINT_FLOW("msm_dmov_enqueue_cmd(%d), enable interrupt\n", id);
98 writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id));
99 }
100#endif
101 if (cmd->execute_func)
102 cmd->execute_func(cmd);
103 PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status);
104 list_add_tail(&cmd->list, &active_commands[id]);
105 if (!channel_active)
106 enable_irq(INT_ADM_AARM);
107 channel_active |= 1U << id;
108 writel(cmd->cmdptr, DMOV_CMD_PTR(id));
109 } else {
110 if (!channel_active)
111 clk_disable(msm_dmov_clk);
112 if (list_empty(&active_commands[id]))
113 PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status);
114
115 PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status %x\n", id, status);
116 list_add_tail(&cmd->list, &ready_commands[id]);
117 }
118 spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
119}
120EXPORT_SYMBOL_GPL(msm_dmov_enqueue_cmd);
121
122struct msm_dmov_exec_cmdptr_cmd {
123 struct msm_dmov_cmd dmov_cmd;
124 struct completion complete;
125 unsigned id;
126 unsigned int result;
127 struct msm_dmov_errdata err;
128};
129
130static void
131dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd,
132 unsigned int result,
133 struct msm_dmov_errdata *err)
134{
135 struct msm_dmov_exec_cmdptr_cmd *cmd = container_of(_cmd, struct msm_dmov_exec_cmdptr_cmd, dmov_cmd);
136 cmd->result = result;
137 if (result != 0x80000002 && err)
138 memcpy(&cmd->err, err, sizeof(struct msm_dmov_errdata));
139
140 complete(&cmd->complete);
141}
142
143int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr)
144{
145 struct msm_dmov_exec_cmdptr_cmd cmd;
146
147 PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr);
148
149 cmd.dmov_cmd.cmdptr = cmdptr;
150 cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func;
151 cmd.dmov_cmd.execute_func = NULL;
152 cmd.id = id;
153 init_completion(&cmd.complete);
154
155 msm_dmov_enqueue_cmd(id, &cmd.dmov_cmd);
156 wait_for_completion(&cmd.complete);
157
158 if (cmd.result != 0x80000002) {
159 PRINT_ERROR("dmov_exec_cmdptr(%d): ERROR, result: %x\n", id, cmd.result);
160 PRINT_ERROR("dmov_exec_cmdptr(%d): flush: %x %x %x %x\n",
161 id, cmd.err.flush[0], cmd.err.flush[1], cmd.err.flush[2], cmd.err.flush[3]);
162 return -EIO;
163 }
164 PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr);
165 return 0;
166}
167
168
169static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
170{
171 unsigned int int_status, mask, id;
172 unsigned long irq_flags;
173 unsigned int ch_status;
174 unsigned int ch_result;
175 struct msm_dmov_cmd *cmd;
176
177 spin_lock_irqsave(&msm_dmov_lock, irq_flags);
178
179 int_status = readl(DMOV_ISR); /* read and clear interrupt */
180 PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status);
181
182 while (int_status) {
183 mask = int_status & -int_status;
184 id = fls(mask) - 1;
185 PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n", int_status, mask, id);
186 int_status &= ~mask;
187 ch_status = readl(DMOV_STATUS(id));
188 if (!(ch_status & DMOV_STATUS_RSLT_VALID)) {
189 PRINT_FLOW("msm_datamover_irq_handler id %d, result not valid %x\n", id, ch_status);
190 continue;
191 }
192 do {
193 ch_result = readl(DMOV_RSLT(id));
194 if (list_empty(&active_commands[id])) {
195 PRINT_ERROR("msm_datamover_irq_handler id %d, got result "
196 "with no active command, status %x, result %x\n",
197 id, ch_status, ch_result);
198 cmd = NULL;
199 } else
200 cmd = list_entry(active_commands[id].next, typeof(*cmd), list);
201 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x, result %x\n", id, ch_status, ch_result);
202 if (ch_result & DMOV_RSLT_DONE) {
203 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n",
204 id, ch_status);
205 PRINT_IO("msm_datamover_irq_handler id %d, got result "
206 "for %p, result %x\n", id, cmd, ch_result);
207 if (cmd) {
208 list_del(&cmd->list);
209 dsb();
210 cmd->complete_func(cmd, ch_result, NULL);
211 }
212 }
213 if (ch_result & DMOV_RSLT_FLUSH) {
214 struct msm_dmov_errdata errdata;
215
216 errdata.flush[0] = readl(DMOV_FLUSH0(id));
217 errdata.flush[1] = readl(DMOV_FLUSH1(id));
218 errdata.flush[2] = readl(DMOV_FLUSH2(id));
219 errdata.flush[3] = readl(DMOV_FLUSH3(id));
220 errdata.flush[4] = readl(DMOV_FLUSH4(id));
221 errdata.flush[5] = readl(DMOV_FLUSH5(id));
222 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
223 PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
224 if (cmd) {
225 list_del(&cmd->list);
226 dsb();
227 cmd->complete_func(cmd, ch_result, &errdata);
228 }
229 }
230 if (ch_result & DMOV_RSLT_ERROR) {
231 struct msm_dmov_errdata errdata;
232
233 errdata.flush[0] = readl(DMOV_FLUSH0(id));
234 errdata.flush[1] = readl(DMOV_FLUSH1(id));
235 errdata.flush[2] = readl(DMOV_FLUSH2(id));
236 errdata.flush[3] = readl(DMOV_FLUSH3(id));
237 errdata.flush[4] = readl(DMOV_FLUSH4(id));
238 errdata.flush[5] = readl(DMOV_FLUSH5(id));
239
240 PRINT_ERROR("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
241 PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
242 if (cmd) {
243 list_del(&cmd->list);
244 dsb();
245 cmd->complete_func(cmd, ch_result, &errdata);
246 }
247 /* this does not seem to work, once we get an error */
248 /* the datamover will no longer accept commands */
249 writel(0, DMOV_FLUSH0(id));
250 }
251 ch_status = readl(DMOV_STATUS(id));
252 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
253 if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
254 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
255 list_move_tail(&cmd->list, &active_commands[id]);
256 if (cmd->execute_func)
257 cmd->execute_func(cmd);
258 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
259 writel(cmd->cmdptr, DMOV_CMD_PTR(id));
260 }
261 } while (ch_status & DMOV_STATUS_RSLT_VALID);
262 if (list_empty(&active_commands[id]) && list_empty(&ready_commands[id]))
263 channel_active &= ~(1U << id);
264 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
265 }
266
267 if (!channel_active) {
268 disable_irq_nosync(INT_ADM_AARM);
269 clk_disable(msm_dmov_clk);
270 }
271
272 spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
273 return IRQ_HANDLED;
274}
275
276static int __init msm_init_datamover(void)
277{
278 int i;
279 int ret;
280 struct clk *clk;
281
282 for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
283 INIT_LIST_HEAD(&ready_commands[i]);
284 INIT_LIST_HEAD(&active_commands[i]);
285 writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i));
286 }
287 clk = clk_get(NULL, "adm_clk");
288 if (IS_ERR(clk))
289 return PTR_ERR(clk);
290 clk_prepare(clk);
291 msm_dmov_clk = clk;
292 ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
293 if (ret)
294 return ret;
295 disable_irq(INT_ADM_AARM);
296 return 0;
297}
298module_init(msm_init_datamover);
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
deleted file mode 100644
index f7a4ea593c95..000000000000
--- a/arch/arm/mach-msm/gpiomux-8x50.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include "gpiomux.h"
18
19#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
20 #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
21 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
22 #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
23 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
24#else
25 #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
26 #define SDCC_CLK_ACTV_CFG 0
27#endif
28
29#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
30 | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
31
32struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
33 [86] = { /* UART3 RX */
34 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
35 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
36 },
37 [87] = { /* UART3 TX */
38 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
39 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
40 },
41 /* SDC1 data[3:0] & CMD */
42 [51 ... 55] = {
43 .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
44 .suspended = SDC1_SUSPEND_CONFIG
45 },
46 /* SDC1 CLK */
47 [56] = {
48 .active = SDCC_CLK_ACTV_CFG,
49 .suspended = SDC1_SUSPEND_CONFIG
50 },
51};
diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h
deleted file mode 100644
index 71d86feba450..000000000000
--- a/arch/arm/mach-msm/gpiomux-v1.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
18#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
19
20#if defined(CONFIG_ARCH_MSM7X30)
21#define GPIOMUX_NGPIOS 182
22#elif defined(CONFIG_ARCH_QSD8X50)
23#define GPIOMUX_NGPIOS 165
24#else
25#define GPIOMUX_NGPIOS 133
26#endif
27
28typedef u32 gpiomux_config_t;
29
30enum {
31 GPIOMUX_DRV_2MA = 0UL << 17,
32 GPIOMUX_DRV_4MA = 1UL << 17,
33 GPIOMUX_DRV_6MA = 2UL << 17,
34 GPIOMUX_DRV_8MA = 3UL << 17,
35 GPIOMUX_DRV_10MA = 4UL << 17,
36 GPIOMUX_DRV_12MA = 5UL << 17,
37 GPIOMUX_DRV_14MA = 6UL << 17,
38 GPIOMUX_DRV_16MA = 7UL << 17,
39};
40
41enum {
42 GPIOMUX_FUNC_GPIO = 0UL,
43 GPIOMUX_FUNC_1 = 1UL,
44 GPIOMUX_FUNC_2 = 2UL,
45 GPIOMUX_FUNC_3 = 3UL,
46 GPIOMUX_FUNC_4 = 4UL,
47 GPIOMUX_FUNC_5 = 5UL,
48 GPIOMUX_FUNC_6 = 6UL,
49 GPIOMUX_FUNC_7 = 7UL,
50 GPIOMUX_FUNC_8 = 8UL,
51 GPIOMUX_FUNC_9 = 9UL,
52 GPIOMUX_FUNC_A = 10UL,
53 GPIOMUX_FUNC_B = 11UL,
54 GPIOMUX_FUNC_C = 12UL,
55 GPIOMUX_FUNC_D = 13UL,
56 GPIOMUX_FUNC_E = 14UL,
57 GPIOMUX_FUNC_F = 15UL,
58};
59
60enum {
61 GPIOMUX_PULL_NONE = 0UL << 15,
62 GPIOMUX_PULL_DOWN = 1UL << 15,
63 GPIOMUX_PULL_KEEPER = 2UL << 15,
64 GPIOMUX_PULL_UP = 3UL << 15,
65};
66
67#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
deleted file mode 100644
index 2b8e2d217082..000000000000
--- a/arch/arm/mach-msm/gpiomux.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/module.h>
18#include <linux/spinlock.h>
19#include "gpiomux.h"
20#include "proc_comm.h"
21
22static DEFINE_SPINLOCK(gpiomux_lock);
23
24static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
25{
26 unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) |
27 ((gpio & 0x3ff) << 4);
28 unsigned tlmm_disable = 0;
29 int rc;
30
31 rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
32 &tlmm_config, &tlmm_disable);
33 if (rc)
34 pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
35 __func__, rc, tlmm_config, tlmm_disable);
36}
37
38int msm_gpiomux_write(unsigned gpio,
39 gpiomux_config_t active,
40 gpiomux_config_t suspended)
41{
42 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
43 unsigned long irq_flags;
44 gpiomux_config_t setting;
45
46 if (gpio >= GPIOMUX_NGPIOS)
47 return -EINVAL;
48
49 spin_lock_irqsave(&gpiomux_lock, irq_flags);
50
51 if (active & GPIOMUX_VALID)
52 cfg->active = active;
53
54 if (suspended & GPIOMUX_VALID)
55 cfg->suspended = suspended;
56
57 setting = cfg->ref ? active : suspended;
58 if (setting & GPIOMUX_VALID)
59 __msm_gpiomux_write(gpio, setting);
60
61 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
62 return 0;
63}
64EXPORT_SYMBOL(msm_gpiomux_write);
65
66int msm_gpiomux_get(unsigned gpio)
67{
68 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
69 unsigned long irq_flags;
70
71 if (gpio >= GPIOMUX_NGPIOS)
72 return -EINVAL;
73
74 spin_lock_irqsave(&gpiomux_lock, irq_flags);
75 if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
76 __msm_gpiomux_write(gpio, cfg->active);
77 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
78 return 0;
79}
80EXPORT_SYMBOL(msm_gpiomux_get);
81
82int msm_gpiomux_put(unsigned gpio)
83{
84 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
85 unsigned long irq_flags;
86
87 if (gpio >= GPIOMUX_NGPIOS)
88 return -EINVAL;
89
90 spin_lock_irqsave(&gpiomux_lock, irq_flags);
91 BUG_ON(cfg->ref == 0);
92 if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
93 __msm_gpiomux_write(gpio, cfg->suspended);
94 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
95 return 0;
96}
97EXPORT_SYMBOL(msm_gpiomux_put);
98
99static int __init gpiomux_init(void)
100{
101 unsigned n;
102
103 for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
104 msm_gpiomux_configs[n].ref = 0;
105 if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
106 continue;
107 __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
108 }
109 return 0;
110}
111postcore_initcall(gpiomux_init);
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
deleted file mode 100644
index 4410d7766f93..000000000000
--- a/arch/arm/mach-msm/gpiomux.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
18#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
19
20#include <linux/bitops.h>
21#include <linux/errno.h>
22#include <mach/msm_gpiomux.h>
23#include "gpiomux-v1.h"
24
25/**
26 * struct msm_gpiomux_config: gpiomux settings for one gpio line.
27 *
28 * A complete gpiomux config is the bitwise-or of a drive-strength,
29 * function, and pull. For functions other than GPIO, the OE
30 * is hard-wired according to the function. For GPIO mode,
31 * OE is controlled by gpiolib.
32 *
33 * Available settings differ by target; see the gpiomux header
34 * specific to your target arch for available configurations.
35 *
36 * @active: The configuration to be installed when the line is
37 * active, or its reference count is > 0.
38 * @suspended: The configuration to be installed when the line
39 * is suspended, or its reference count is 0.
40 * @ref: The reference count of the line. For internal use of
41 * the gpiomux framework only.
42 */
43struct msm_gpiomux_config {
44 gpiomux_config_t active;
45 gpiomux_config_t suspended;
46 unsigned ref;
47};
48
49/**
50 * @GPIOMUX_VALID: If set, the config field contains 'good data'.
51 * The absence of this bit will prevent the gpiomux
52 * system from applying the configuration under all
53 * circumstances.
54 */
55enum {
56 GPIOMUX_VALID = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
57 GPIOMUX_CTL_MASK = GPIOMUX_VALID,
58};
59
60#ifdef CONFIG_MSM_GPIOMUX
61
62/* Each architecture must provide its own instance of this table.
63 * To avoid having gpiomux manage any given gpio, one or both of
64 * the entries can avoid setting GPIOMUX_VALID - the absence
65 * of that flag will prevent the configuration from being applied
66 * during state transitions.
67 */
68extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
69
70/* Install a new configuration to the gpio line. To avoid overwriting
71 * a configuration, leave the VALID bit out.
72 */
73int msm_gpiomux_write(unsigned gpio,
74 gpiomux_config_t active,
75 gpiomux_config_t suspended);
76#else
77static inline int msm_gpiomux_write(unsigned gpio,
78 gpiomux_config_t active,
79 gpiomux_config_t suspended)
80{
81 return -ENOSYS;
82}
83#endif
84#endif
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
deleted file mode 100644
index fd4f4a7a83b3..000000000000
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_CLK_H
13#define __MACH_CLK_H
14
15/* Magic rate value for use with PM QOS to request the board's maximum
16 * supported AXI rate. PM QOS will only pass positive s32 rate values
17 * through to the clock driver, so INT_MAX is used.
18 */
19#define MSM_AXI_MAX_FREQ LONG_MAX
20
21enum clk_reset_action {
22 CLK_RESET_DEASSERT = 0,
23 CLK_RESET_ASSERT = 1
24};
25
26struct clk;
27
28/* Assert/Deassert reset to a hardware block associated with a clock */
29int clk_reset(struct clk *clk, enum clk_reset_action action);
30
31#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
deleted file mode 100644
index a72d48d42342..000000000000
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* linux/include/asm-arm/arch-msm/dma.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_DMA_H
17
18#include <linux/list.h>
19
20struct msm_dmov_errdata {
21 uint32_t flush[6];
22};
23
24struct msm_dmov_cmd {
25 struct list_head list;
26 unsigned int cmdptr;
27 void (*complete_func)(struct msm_dmov_cmd *cmd,
28 unsigned int result,
29 struct msm_dmov_errdata *err);
30 void (*execute_func)(struct msm_dmov_cmd *cmd);
31 void *data;
32};
33
34#ifndef CONFIG_ARCH_MSM8X60
35void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
36void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
37int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
38#else
39static inline
40void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
41static inline
42void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
43static inline
44int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
45#endif
46
47#define DMOV_CMD_LIST (0 << 29) /* does not work */
48#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
49#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
50#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
51#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
52
53#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
54#define DMOV_RSLT_ERROR (1 << 3)
55#define DMOV_RSLT_FLUSH (1 << 2)
56#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
57#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
58
59#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
60#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
61#define DMOV_STATUS_RSLT_VALID (1 << 1)
62#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
63
64#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
65#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
66#define DMOV_CONFIG_IRQ_EN (1 << 0)
67
68/* channel assignments */
69
70#define DMOV_NAND_CHAN 7
71#define DMOV_NAND_CRCI_CMD 5
72#define DMOV_NAND_CRCI_DATA 4
73
74#define DMOV_SDC1_CHAN 8
75#define DMOV_SDC1_CRCI 6
76
77#define DMOV_SDC2_CHAN 8
78#define DMOV_SDC2_CRCI 7
79
80#define DMOV_TSIF_CHAN 10
81#define DMOV_TSIF_CRCI 10
82
83#define DMOV_USB_CHAN 11
84
85/* no client rate control ifc (eg, ram) */
86#define DMOV_NONE_CRCI 0
87
88
89/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
90 * is going to walk a list of 32bit pointers as described below. Each
91 * pointer points to a *array* of dmov_s, etc structs. The last pointer
92 * in the list is marked with CMD_PTR_LP. The last struct in each array
93 * is marked with CMD_LC (see below).
94 */
95#define CMD_PTR_ADDR(addr) ((addr) >> 3)
96#define CMD_PTR_LP (1 << 31) /* last pointer */
97#define CMD_PTR_PT (3 << 29) /* ? */
98
99/* Single Item Mode */
100typedef struct {
101 unsigned cmd;
102 unsigned src;
103 unsigned dst;
104 unsigned len;
105} dmov_s;
106
107/* Scatter/Gather Mode */
108typedef struct {
109 unsigned cmd;
110 unsigned src_dscr;
111 unsigned dst_dscr;
112 unsigned _reserved;
113} dmov_sg;
114
115/* Box mode */
116typedef struct {
117 uint32_t cmd;
118 uint32_t src_row_addr;
119 uint32_t dst_row_addr;
120 uint32_t src_dst_len;
121 uint32_t num_rows;
122 uint32_t row_offset;
123} dmov_box;
124
125/* bits for the cmd field of the above structures */
126
127#define CMD_LC (1 << 31) /* last command */
128#define CMD_FR (1 << 22) /* force result -- does not work? */
129#define CMD_OCU (1 << 21) /* other channel unblock */
130#define CMD_OCB (1 << 20) /* other channel block */
131#define CMD_TCB (1 << 19) /* ? */
132#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
133#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
134
135#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
136#define CMD_MODE_SG (1 << 0) /* untested */
137#define CMD_MODE_IND_SG (2 << 0) /* untested */
138#define CMD_MODE_BOX (3 << 0) /* untested */
139
140#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
141#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
142#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
143
144#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
145#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
146#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
147
148#define CMD_DST_CRCI(n) (((n) & 15) << 7)
149#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
150
151#endif
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
deleted file mode 100644
index f2ae9087f654..000000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ /dev/null
@@ -1,36 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#if !defined(CONFIG_ARM_GIC)
20#include <mach/msm_iomap.h>
21
22 .macro get_irqnr_preamble, base, tmp
23 @ enable imprecise aborts
24 cpsie a
25 mov \base, #MSM_VIC_BASE
26 .endm
27
28 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
29 @ 0xD0 has irq# or old irq# if the irq has been handled
30 @ 0xD4 has irq# or -1 if none pending *but* if you just
31 @ read 0xD4 you never get the first irq for some reason
32 ldr \irqnr, [\base, #0xD0]
33 ldr \irqnr, [\base, #0xD4]
34 cmp \irqnr, #0xffffffff
35 .endm
36#endif
diff --git a/arch/arm/mach-msm/include/mach/hardware.h b/arch/arm/mach-msm/include/mach/hardware.h
deleted file mode 100644
index 2d126091ae41..000000000000
--- a/arch/arm/mach-msm/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-msm/include/mach/hardware.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_HARDWARE_H
17
18#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x00.h b/arch/arm/mach-msm/include/mach/irqs-7x00.h
deleted file mode 100644
index f1fe70612fe9..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x00.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 */
6
7#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
8#define __ASM_ARCH_MSM_IRQS_7X00_H
9
10/* MSM ARM11 Interrupt Numbers */
11/* See 80-VE113-1 A, pp219-221 */
12
13#define INT_A9_M2A_0 0
14#define INT_A9_M2A_1 1
15#define INT_A9_M2A_2 2
16#define INT_A9_M2A_3 3
17#define INT_A9_M2A_4 4
18#define INT_A9_M2A_5 5
19#define INT_A9_M2A_6 6
20#define INT_GP_TIMER_EXP 7
21#define INT_DEBUG_TIMER_EXP 8
22#define INT_UART1 9
23#define INT_UART2 10
24#define INT_UART3 11
25#define INT_UART1_RX 12
26#define INT_UART2_RX 13
27#define INT_UART3_RX 14
28#define INT_USB_OTG 15
29#define INT_MDDI_PRI 16
30#define INT_MDDI_EXT 17
31#define INT_MDDI_CLIENT 18
32#define INT_MDP 19
33#define INT_GRAPHICS 20
34#define INT_ADM_AARM 21
35#define INT_ADSP_A11 22
36#define INT_ADSP_A9_A11 23
37#define INT_SDC1_0 24
38#define INT_SDC1_1 25
39#define INT_SDC2_0 26
40#define INT_SDC2_1 27
41#define INT_KEYSENSE 28
42#define INT_TCHSCRN_SSBI 29
43#define INT_TCHSCRN1 30
44#define INT_TCHSCRN2 31
45
46#define INT_GPIO_GROUP1 (32 + 0)
47#define INT_GPIO_GROUP2 (32 + 1)
48#define INT_PWB_I2C (32 + 2)
49#define INT_SOFTRESET (32 + 3)
50#define INT_NAND_WR_ER_DONE (32 + 4)
51#define INT_NAND_OP_DONE (32 + 5)
52#define INT_PBUS_ARM11 (32 + 6)
53#define INT_AXI_MPU_SMI (32 + 7)
54#define INT_AXI_MPU_EBI1 (32 + 8)
55#define INT_AD_HSSD (32 + 9)
56#define INT_ARM11_PMU (32 + 10)
57#define INT_ARM11_DMA (32 + 11)
58#define INT_TSIF_IRQ (32 + 12)
59#define INT_UART1DM_IRQ (32 + 13)
60#define INT_UART1DM_RX (32 + 14)
61#define INT_USB_HS (32 + 15)
62#define INT_SDC3_0 (32 + 16)
63#define INT_SDC3_1 (32 + 17)
64#define INT_SDC4_0 (32 + 18)
65#define INT_SDC4_1 (32 + 19)
66#define INT_UART2DM_RX (32 + 20)
67#define INT_UART2DM_IRQ (32 + 21)
68
69/* 22-31 are reserved */
70
71#define NR_MSM_IRQS 64
72#define NR_GPIO_IRQS 122
73#define NR_BOARD_IRQS 64
74
75#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
deleted file mode 100644
index 1f15902655fd..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-7x30.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
14#define __ASM_ARCH_MSM_IRQS_7X30_H
15
16/* MSM ACPU Interrupt Numbers */
17
18#define INT_DEBUG_TIMER_EXP 0
19#define INT_GPT0_TIMER_EXP 1
20#define INT_GPT1_TIMER_EXP 2
21#define INT_WDT0_ACCSCSSBARK 3
22#define INT_WDT1_ACCSCSSBARK 4
23#define INT_AVS_SVIC 5
24#define INT_AVS_SVIC_SW_DONE 6
25#define INT_SC_DBG_RX_FULL 7
26#define INT_SC_DBG_TX_EMPTY 8
27#define INT_ARM11_PM 9
28#define INT_AVS_REQ_DOWN 10
29#define INT_AVS_REQ_UP 11
30#define INT_SC_ACG 12
31/* SCSS_VICFIQSTS0[13:15] are RESERVED */
32#define INT_L2_SVICCPUIRPTREQ 16
33#define INT_L2_SVICDMANSIRPTREQ 17
34#define INT_L2_SVICDMASIRPTREQ 18
35#define INT_L2_SVICSLVIRPTREQ 19
36#define INT_AD5A_MPROC_APPS_0 20
37#define INT_AD5A_MPROC_APPS_1 21
38#define INT_A9_M2A_0 22
39#define INT_A9_M2A_1 23
40#define INT_A9_M2A_2 24
41#define INT_A9_M2A_3 25
42#define INT_A9_M2A_4 26
43#define INT_A9_M2A_5 27
44#define INT_A9_M2A_6 28
45#define INT_A9_M2A_7 29
46#define INT_A9_M2A_8 30
47#define INT_A9_M2A_9 31
48
49#define INT_AXI_EBI1_SC (32 + 0)
50#define INT_IMEM_ERR (32 + 1)
51#define INT_AXI_EBI0_SC (32 + 2)
52#define INT_PBUS_SC_IRQC (32 + 3)
53#define INT_PERPH_BUS_BPM (32 + 4)
54#define INT_CC_TEMP_SENSE (32 + 5)
55#define INT_UXMC_EBI0 (32 + 6)
56#define INT_UXMC_EBI1 (32 + 7)
57#define INT_EBI2_OP_DONE (32 + 8)
58#define INT_EBI2_WR_ER_DONE (32 + 9)
59#define INT_TCSR_SPSS_CE (32 + 10)
60#define INT_EMDH (32 + 11)
61#define INT_PMDH (32 + 12)
62#define INT_MDC (32 + 13)
63#define INT_MIDI_TO_SUPSS (32 + 14)
64#define INT_LPA_2 (32 + 15)
65#define INT_GPIO_GROUP1_SECURE (32 + 16)
66#define INT_GPIO_GROUP2_SECURE (32 + 17)
67#define INT_GPIO_GROUP1 (32 + 18)
68#define INT_GPIO_GROUP2 (32 + 19)
69#define INT_MPRPH_SOFTRESET (32 + 20)
70#define INT_PWB_I2C (32 + 21)
71#define INT_PWB_I2C_2 (32 + 22)
72#define INT_TSSC_SAMPLE (32 + 23)
73#define INT_TSSC_PENUP (32 + 24)
74#define INT_TCHSCRN_SSBI (32 + 25)
75#define INT_FM_RDS (32 + 26)
76#define INT_KEYSENSE (32 + 27)
77#define INT_USB_OTG_HS (32 + 28)
78#define INT_USB_OTG_HS2 (32 + 29)
79#define INT_USB_OTG_HS3 (32 + 30)
80#define INT_CSI (32 + 31)
81
82#define INT_SPI_OUTPUT (64 + 0)
83#define INT_SPI_INPUT (64 + 1)
84#define INT_SPI_ERROR (64 + 2)
85#define INT_UART1 (64 + 3)
86#define INT_UART1_RX (64 + 4)
87#define INT_UART2 (64 + 5)
88#define INT_UART2_RX (64 + 6)
89#define INT_UART3 (64 + 7)
90#define INT_UART3_RX (64 + 8)
91#define INT_UART1DM_IRQ (64 + 9)
92#define INT_UART1DM_RX (64 + 10)
93#define INT_UART2DM_IRQ (64 + 11)
94#define INT_UART2DM_RX (64 + 12)
95#define INT_TSIF (64 + 13)
96#define INT_ADM_SC1 (64 + 14)
97#define INT_ADM_SC2 (64 + 15)
98#define INT_MDP (64 + 16)
99#define INT_VPE (64 + 17)
100#define INT_GRP_2D (64 + 18)
101#define INT_GRP_3D (64 + 19)
102#define INT_ROTATOR (64 + 20)
103#define INT_MFC720 (64 + 21)
104#define INT_JPEG (64 + 22)
105#define INT_VFE (64 + 23)
106#define INT_TV_ENC (64 + 24)
107#define INT_PMIC_SSBI (64 + 25)
108#define INT_MPM_1 (64 + 26)
109#define INT_TCSR_SPSS_SAMPLE (64 + 27)
110#define INT_TCSR_SPSS_PENUP (64 + 28)
111#define INT_MPM_2 (64 + 29)
112#define INT_SDC1_0 (64 + 30)
113#define INT_SDC1_1 (64 + 31)
114
115#define INT_SDC3_0 (96 + 0)
116#define INT_SDC3_1 (96 + 1)
117#define INT_SDC2_0 (96 + 2)
118#define INT_SDC2_1 (96 + 3)
119#define INT_SDC4_0 (96 + 4)
120#define INT_SDC4_1 (96 + 5)
121#define INT_PWB_QUP_IN (96 + 6)
122#define INT_PWB_QUP_OUT (96 + 7)
123#define INT_PWB_QUP_ERR (96 + 8)
124#define INT_SCSS_WDT0_BITE (96 + 9)
125/* SCSS_VICFIQSTS3[10:31] are RESERVED */
126
127/* Retrofit universal macro names */
128#define INT_ADM_AARM INT_ADM_SC2
129#define INT_USB_HS INT_USB_OTG_HS
130#define INT_USB_OTG INT_USB_OTG_HS
131#define INT_TCHSCRN1 INT_TSSC_SAMPLE
132#define INT_TCHSCRN2 INT_TSSC_PENUP
133#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
134#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0
135#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1
136#define INT_MDDI_EXT INT_EMDH
137#define INT_MDDI_PRI INT_PMDH
138#define INT_MDDI_CLIENT INT_MDC
139#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE
140#define INT_NAND_OP_DONE INT_EBI2_OP_DONE
141
142#define NR_MSM_IRQS 128
143#define NR_GPIO_IRQS 182
144#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
145#define NR_PMIC8058_GPIO_IRQS 40
146#define NR_PMIC8058_MPP_IRQS 12
147#define NR_PMIC8058_MISC_IRQS 8
148#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\
149 NR_PMIC8058_MPP_IRQS +\
150 NR_PMIC8058_MISC_IRQS)
151#define NR_BOARD_IRQS NR_PMIC8058_IRQS
152
153#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
deleted file mode 100644
index 26adbe0e9406..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-8x50.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
14#define __ASM_ARCH_MSM_IRQS_8XXX_H
15
16/* MSM ACPU Interrupt Numbers */
17
18#define INT_A9_M2A_0 0
19#define INT_A9_M2A_1 1
20#define INT_A9_M2A_2 2
21#define INT_A9_M2A_3 3
22#define INT_A9_M2A_4 4
23#define INT_A9_M2A_5 5
24#define INT_A9_M2A_6 6
25#define INT_GP_TIMER_EXP 7
26#define INT_DEBUG_TIMER_EXP 8
27#define INT_SIRC_0 9
28#define INT_SDC3_0 10
29#define INT_SDC3_1 11
30#define INT_SDC4_0 12
31#define INT_SDC4_1 13
32#define INT_AD6_EXT_VFR 14
33#define INT_USB_OTG 15
34#define INT_MDDI_PRI 16
35#define INT_MDDI_EXT 17
36#define INT_MDDI_CLIENT 18
37#define INT_MDP 19
38#define INT_GRAPHICS 20
39#define INT_ADM_AARM 21
40#define INT_ADSP_A11 22
41#define INT_ADSP_A9_A11 23
42#define INT_SDC1_0 24
43#define INT_SDC1_1 25
44#define INT_SDC2_0 26
45#define INT_SDC2_1 27
46#define INT_KEYSENSE 28
47#define INT_TCHSCRN_SSBI 29
48#define INT_TCHSCRN1 30
49#define INT_TCHSCRN2 31
50
51#define INT_TCSR_MPRPH_SC1 (32 + 0)
52#define INT_USB_FS2 (32 + 1)
53#define INT_PWB_I2C (32 + 2)
54#define INT_SOFTRESET (32 + 3)
55#define INT_NAND_WR_ER_DONE (32 + 4)
56#define INT_NAND_OP_DONE (32 + 5)
57#define INT_TCSR_MPRPH_SC2 (32 + 6)
58#define INT_OP_PEN (32 + 7)
59#define INT_AD_HSSD (32 + 8)
60#define INT_ARM11_PM (32 + 9)
61#define INT_SDMA_NON_SECURE (32 + 10)
62#define INT_TSIF_IRQ (32 + 11)
63#define INT_UART1DM_IRQ (32 + 12)
64#define INT_UART1DM_RX (32 + 13)
65#define INT_SDMA_SECURE (32 + 14)
66#define INT_SI2S_SLAVE (32 + 15)
67#define INT_SC_I2CPU (32 + 16)
68#define INT_SC_DBG_RDTRFULL (32 + 17)
69#define INT_SC_DBG_WDTRFULL (32 + 18)
70#define INT_SCPLL_CTL_DONE (32 + 19)
71#define INT_UART2DM_IRQ (32 + 20)
72#define INT_UART2DM_RX (32 + 21)
73#define INT_VDC_MEC (32 + 22)
74#define INT_VDC_DB (32 + 23)
75#define INT_VDC_AXI (32 + 24)
76#define INT_VFE (32 + 25)
77#define INT_USB_HS (32 + 26)
78#define INT_AUDIO_OUT0 (32 + 27)
79#define INT_AUDIO_OUT1 (32 + 28)
80#define INT_CRYPTO (32 + 29)
81#define INT_AD6M_IDLE (32 + 30)
82#define INT_SIRC_1 (32 + 31)
83
84#define NR_GPIO_IRQS 165
85#define NR_MSM_IRQS 64
86#define NR_BOARD_IRQS 64
87
88#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
deleted file mode 100644
index 164d355c96ea..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_IRQS_H
18#define __ASM_ARCH_MSM_IRQS_H
19
20#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
21
22#if defined(CONFIG_ARCH_MSM7X30)
23#include "irqs-7x30.h"
24#elif defined(CONFIG_ARCH_QSD8X50)
25#include "irqs-8x50.h"
26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM_ARM11)
28#include "irqs-7x00.h"
29#else
30#error "Unknown architecture specification"
31#endif
32
33#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
34#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
35#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
36
37#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_gpiomux.h b/arch/arm/mach-msm/include/mach/msm_gpiomux.h
deleted file mode 100644
index 0c7d3936e02f..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_gpiomux.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _LINUX_MSM_GPIOMUX_H
14#define _LINUX_MSM_GPIOMUX_H
15
16#ifdef CONFIG_MSM_GPIOMUX
17
18/* Increment a gpio's reference count, possibly activating the line. */
19int __must_check msm_gpiomux_get(unsigned gpio);
20
21/* Decrement a gpio's reference count, possibly suspending the line. */
22int msm_gpiomux_put(unsigned gpio);
23
24#else
25
26static inline int __must_check msm_gpiomux_get(unsigned gpio)
27{
28 return -ENOSYS;
29}
30
31static inline int msm_gpiomux_put(unsigned gpio)
32{
33 return -ENOSYS;
34}
35
36#endif
37
38#endif /* _LINUX_MSM_GPIOMUX_H */
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
deleted file mode 100644
index 67dc0e98b958..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * The MSM peripherals are spread all over across 768MB of physical
18 * space, which makes just having a simple IO_ADDRESS macro to slide
19 * them into the right virtual location rough. Instead, we will
20 * provide a master phys->virt mapping for peripherals here.
21 *
22 */
23
24#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
25#define __ASM_ARCH_MSM_IOMAP_7X00_H
26
27#include <asm/sizes.h>
28
29/* Physical base address and size of peripherals.
30 * Ordered by the virtual base addresses they will be mapped at.
31 *
32 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
33 * instruction, otherwise entry-macro.S will not compile.
34 *
35 * If you add or remove entries here, you'll want to edit the
36 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
37 * changes.
38 *
39 */
40
41#define MSM_VIC_BASE IOMEM(0xE0000000)
42#define MSM_VIC_PHYS 0xC0000000
43#define MSM_VIC_SIZE SZ_4K
44
45#define MSM7X00_CSR_PHYS 0xC0100000
46#define MSM7X00_CSR_SIZE SZ_4K
47
48#define MSM_DMOV_BASE IOMEM(0xE0002000)
49#define MSM_DMOV_PHYS 0xA9700000
50#define MSM_DMOV_SIZE SZ_4K
51
52#define MSM7X00_GPIO1_PHYS 0xA9200000
53#define MSM7X00_GPIO1_SIZE SZ_4K
54
55#define MSM7X00_GPIO2_PHYS 0xA9300000
56#define MSM7X00_GPIO2_SIZE SZ_4K
57
58#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
59#define MSM_CLK_CTL_PHYS 0xA8600000
60#define MSM_CLK_CTL_SIZE SZ_4K
61
62#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
63#define MSM_SHARED_RAM_PHYS 0x01F00000
64#define MSM_SHARED_RAM_SIZE SZ_1M
65
66#define MSM_UART1_PHYS 0xA9A00000
67#define MSM_UART1_SIZE SZ_4K
68
69#define MSM_UART2_PHYS 0xA9B00000
70#define MSM_UART2_SIZE SZ_4K
71
72#define MSM_UART3_PHYS 0xA9C00000
73#define MSM_UART3_SIZE SZ_4K
74
75#define MSM_SDC1_PHYS 0xA0400000
76#define MSM_SDC1_SIZE SZ_4K
77
78#define MSM_SDC2_PHYS 0xA0500000
79#define MSM_SDC2_SIZE SZ_4K
80
81#define MSM_SDC3_PHYS 0xA0600000
82#define MSM_SDC3_SIZE SZ_4K
83
84#define MSM_SDC4_PHYS 0xA0700000
85#define MSM_SDC4_SIZE SZ_4K
86
87#define MSM_I2C_PHYS 0xA9900000
88#define MSM_I2C_SIZE SZ_4K
89
90#define MSM_HSUSB_PHYS 0xA0800000
91#define MSM_HSUSB_SIZE SZ_4K
92
93#define MSM_PMDH_PHYS 0xAA600000
94#define MSM_PMDH_SIZE SZ_4K
95
96#define MSM_EMDH_PHYS 0xAA700000
97#define MSM_EMDH_SIZE SZ_4K
98
99#define MSM_MDP_PHYS 0xAA200000
100#define MSM_MDP_SIZE 0x000F0000
101
102#define MSM_MDC_PHYS 0xAA500000
103#define MSM_MDC_SIZE SZ_1M
104
105#define MSM_AD5_PHYS 0xAC000000
106#define MSM_AD5_SIZE (SZ_1M*13)
107
108#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
deleted file mode 100644
index 198202c267c8..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
24#define __ASM_ARCH_MSM_IOMAP_7X30_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xC0080000
40#define MSM_VIC_SIZE SZ_4K
41
42#define MSM7X30_CSR_PHYS 0xC0100000
43#define MSM7X30_CSR_SIZE SZ_4K
44
45#define MSM_DMOV_BASE IOMEM(0xE0002000)
46#define MSM_DMOV_PHYS 0xAC400000
47#define MSM_DMOV_SIZE SZ_4K
48
49#define MSM7X30_GPIO1_PHYS 0xAC001000
50#define MSM7X30_GPIO1_SIZE SZ_4K
51
52#define MSM7X30_GPIO2_PHYS 0xAC101000
53#define MSM7X30_GPIO2_SIZE SZ_4K
54
55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
56#define MSM_CLK_CTL_PHYS 0xAB800000
57#define MSM_CLK_CTL_SIZE SZ_4K
58
59#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
60#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
61#define MSM_CLK_CTL_SH2_SIZE SZ_4K
62
63#define MSM_ACC_BASE IOMEM(0xE0007000)
64#define MSM_ACC_PHYS 0xC0101000
65#define MSM_ACC_SIZE SZ_4K
66
67#define MSM_SAW_BASE IOMEM(0xE0008000)
68#define MSM_SAW_PHYS 0xC0102000
69#define MSM_SAW_SIZE SZ_4K
70
71#define MSM_GCC_BASE IOMEM(0xE0009000)
72#define MSM_GCC_PHYS 0xC0182000
73#define MSM_GCC_SIZE SZ_4K
74
75#define MSM_TCSR_BASE IOMEM(0xE000A000)
76#define MSM_TCSR_PHYS 0xAB600000
77#define MSM_TCSR_SIZE SZ_4K
78
79#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
80#define MSM_SHARED_RAM_PHYS 0x00100000
81#define MSM_SHARED_RAM_SIZE SZ_1M
82
83#define MSM_UART1_PHYS 0xACA00000
84#define MSM_UART1_SIZE SZ_4K
85
86#define MSM_UART2_PHYS 0xACB00000
87#define MSM_UART2_SIZE SZ_4K
88
89#define MSM_UART3_PHYS 0xACC00000
90#define MSM_UART3_SIZE SZ_4K
91
92#define MSM_MDC_BASE IOMEM(0xE0200000)
93#define MSM_MDC_PHYS 0xAA500000
94#define MSM_MDC_SIZE SZ_1M
95
96#define MSM_AD5_BASE IOMEM(0xE0300000)
97#define MSM_AD5_PHYS 0xA7000000
98#define MSM_AD5_SIZE (SZ_1M*13)
99
100#define MSM_HSUSB_PHYS 0xA3600000
101#define MSM_HSUSB_SIZE SZ_1K
102
103#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
deleted file mode 100644
index 0faa894729b7..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
24#define __ASM_ARCH_MSM_IOMAP_8X50_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xAC000000
40#define MSM_VIC_SIZE SZ_4K
41
42#define QSD8X50_CSR_PHYS 0xAC100000
43#define QSD8X50_CSR_SIZE SZ_4K
44
45#define MSM_DMOV_BASE IOMEM(0xE0002000)
46#define MSM_DMOV_PHYS 0xA9700000
47#define MSM_DMOV_SIZE SZ_4K
48
49#define QSD8X50_GPIO1_PHYS 0xA9000000
50#define QSD8X50_GPIO1_SIZE SZ_4K
51
52#define QSD8X50_GPIO2_PHYS 0xA9100000
53#define QSD8X50_GPIO2_SIZE SZ_4K
54
55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
56#define MSM_CLK_CTL_PHYS 0xA8600000
57#define MSM_CLK_CTL_SIZE SZ_4K
58
59#define MSM_SIRC_BASE IOMEM(0xE1006000)
60#define MSM_SIRC_PHYS 0xAC200000
61#define MSM_SIRC_SIZE SZ_4K
62
63#define MSM_SCPLL_BASE IOMEM(0xE1007000)
64#define MSM_SCPLL_PHYS 0xA8800000
65#define MSM_SCPLL_SIZE SZ_4K
66
67#ifdef CONFIG_MSM_SOC_REV_A
68#define MSM_SMI_BASE 0xE0000000
69#else
70#define MSM_SMI_BASE 0x00000000
71#endif
72
73#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
74#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
75#define MSM_SHARED_RAM_SIZE SZ_1M
76
77#define MSM_UART1_PHYS 0xA9A00000
78#define MSM_UART1_SIZE SZ_4K
79
80#define MSM_UART2_PHYS 0xA9B00000
81#define MSM_UART2_SIZE SZ_4K
82
83#define MSM_UART3_PHYS 0xA9C00000
84#define MSM_UART3_SIZE SZ_4K
85
86#define MSM_MDC_BASE IOMEM(0xE0200000)
87#define MSM_MDC_PHYS 0xAA500000
88#define MSM_MDC_SIZE SZ_1M
89
90#define MSM_AD5_BASE IOMEM(0xE0300000)
91#define MSM_AD5_PHYS 0xAC000000
92#define MSM_AD5_SIZE (SZ_1M*13)
93
94
95#define MSM_I2C_SIZE SZ_4K
96#define MSM_I2C_PHYS 0xA9900000
97
98#define MSM_HSUSB_PHYS 0xA0800000
99#define MSM_HSUSB_SIZE SZ_1K
100
101#define MSM_NAND_PHYS 0xA0A00000
102
103
104#define MSM_TSIF_PHYS (0xa0100000)
105#define MSM_TSIF_SIZE (0x200)
106
107#define MSM_TSSC_PHYS 0xAA300000
108
109#define MSM_UART1DM_PHYS 0xA0200000
110#define MSM_UART2DM_PHYS 0xA0900000
111
112
113#define MSM_SDC1_PHYS 0xA0300000
114#define MSM_SDC1_SIZE SZ_4K
115
116#define MSM_SDC2_PHYS 0xA0400000
117#define MSM_SDC2_SIZE SZ_4K
118
119#define MSM_SDC3_PHYS 0xA0500000
120#define MSM_SDC3_SIZE SZ_4K
121
122#define MSM_SDC4_PHYS 0xA0600000
123#define MSM_SDC4_SIZE SZ_4K
124
125#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
deleted file mode 100644
index 0e4f49157684..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_H
24#define __ASM_ARCH_MSM_IOMAP_H
25
26#include <asm/sizes.h>
27
28/* Physical base address and size of peripherals.
29 * Ordered by the virtual base addresses they will be mapped at.
30 *
31 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
32 * instruction, otherwise entry-macro.S will not compile.
33 *
34 * If you add or remove entries here, you'll want to edit the
35 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
36 * changes.
37 *
38 */
39
40#if defined(CONFIG_ARCH_MSM7X30)
41#include "msm_iomap-7x30.h"
42#elif defined(CONFIG_ARCH_QSD8X50)
43#include "msm_iomap-8x50.h"
44#else
45#include "msm_iomap-7x00.h"
46#endif
47
48/* Virtual addresses shared across all MSM targets. */
49#define MSM_CSR_BASE IOMEM(0xE0001000)
50#define MSM_GPIO1_BASE IOMEM(0xE0003000)
51#define MSM_GPIO2_BASE IOMEM(0xE0004000)
52
53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
deleted file mode 100644
index 029463ec8756..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/* linux/include/asm-arm/arch-msm/msm_smd.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_SMD_H
18#define __ASM_ARCH_MSM_SMD_H
19
20typedef struct smd_channel smd_channel_t;
21
22extern int (*msm_check_for_modem_crash)(void);
23
24/* warning: notify() may be called before open returns */
25int smd_open(const char *name, smd_channel_t **ch, void *priv,
26 void (*notify)(void *priv, unsigned event));
27
28#define SMD_EVENT_DATA 1
29#define SMD_EVENT_OPEN 2
30#define SMD_EVENT_CLOSE 3
31
32int smd_close(smd_channel_t *ch);
33
34/* passing a null pointer for data reads and discards */
35int smd_read(smd_channel_t *ch, void *data, int len);
36
37/* Write to stream channels may do a partial write and return
38** the length actually written.
39** Write to packet channels will never do a partial write --
40** it will return the requested length written or an error.
41*/
42int smd_write(smd_channel_t *ch, const void *data, int len);
43int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
44
45int smd_write_avail(smd_channel_t *ch);
46int smd_read_avail(smd_channel_t *ch);
47
48/* Returns the total size of the current packet being read.
49** Returns 0 if no packets available or a stream channel.
50*/
51int smd_cur_packet_size(smd_channel_t *ch);
52
53/* used for tty unthrottling and the like -- causes the notify()
54** callback to be called from the same lock context as is used
55** when it is called from channel updates
56*/
57void smd_kick(smd_channel_t *ch);
58
59
60#if 0
61/* these are interruptable waits which will block you until the specified
62** number of bytes are readable or writable.
63*/
64int smd_wait_until_readable(smd_channel_t *ch, int bytes);
65int smd_wait_until_writable(smd_channel_t *ch, int bytes);
66#endif
67
68typedef enum {
69 SMD_PORT_DS = 0,
70 SMD_PORT_DIAG,
71 SMD_PORT_RPC_CALL,
72 SMD_PORT_RPC_REPLY,
73 SMD_PORT_BT,
74 SMD_PORT_CONTROL,
75 SMD_PORT_MEMCPY_SPARE1,
76 SMD_PORT_DATA1,
77 SMD_PORT_DATA2,
78 SMD_PORT_DATA3,
79 SMD_PORT_DATA4,
80 SMD_PORT_DATA5,
81 SMD_PORT_DATA6,
82 SMD_PORT_DATA7,
83 SMD_PORT_DATA8,
84 SMD_PORT_DATA9,
85 SMD_PORT_DATA10,
86 SMD_PORT_DATA11,
87 SMD_PORT_DATA12,
88 SMD_PORT_DATA13,
89 SMD_PORT_DATA14,
90 SMD_PORT_DATA15,
91 SMD_PORT_DATA16,
92 SMD_PORT_DATA17,
93 SMD_PORT_DATA18,
94 SMD_PORT_DATA19,
95 SMD_PORT_DATA20,
96 SMD_PORT_GPS_NMEA,
97 SMD_PORT_BRIDGE_1,
98 SMD_PORT_BRIDGE_2,
99 SMD_PORT_BRIDGE_3,
100 SMD_PORT_BRIDGE_4,
101 SMD_PORT_BRIDGE_5,
102 SMD_PORT_LOOPBACK,
103 SMD_PORT_CS_APPS_MODEM,
104 SMD_PORT_CS_APPS_DSP,
105 SMD_PORT_CS_MODEM_DSP,
106 SMD_NUM_PORTS,
107} smd_port_id_type;
108
109#endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
deleted file mode 100644
index ef55868a5b8a..000000000000
--- a/arch/arm/mach-msm/include/mach/sirc.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_SIRC_H
14#define __ASM_ARCH_MSM_SIRC_H
15
16struct sirc_regs_t {
17 void *int_enable;
18 void *int_enable_clear;
19 void *int_enable_set;
20 void *int_type;
21 void *int_polarity;
22 void *int_clear;
23};
24
25struct sirc_cascade_regs {
26 void *int_status;
27 unsigned int cascade_irq;
28};
29
30void msm_init_sirc(void);
31void msm_sirc_enter_sleep(void);
32void msm_sirc_exit_sleep(void);
33
34#if defined(CONFIG_ARCH_MSM_SCORPION)
35
36#include <mach/msm_iomap.h>
37
38/*
39 * Secondary interrupt controller interrupts
40 */
41
42#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
43
44#define INT_UART1 (FIRST_SIRC_IRQ + 0)
45#define INT_UART2 (FIRST_SIRC_IRQ + 1)
46#define INT_UART3 (FIRST_SIRC_IRQ + 2)
47#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
48#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
49#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
50#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
51#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
52#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
53#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
54#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
55#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
56#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
57#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
58#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
59#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
60#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
61#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
62#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
63#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
64#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
65#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
66#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
67#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
68#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
69#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
70#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
71#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
72
73#if defined(CONFIG_MSM_SOC_REV_A)
74#define NR_SIRC_IRQS 28
75#define SIRC_MASK 0x0FFFFFFF
76#else
77#define NR_SIRC_IRQS 23
78#define SIRC_MASK 0x007FFFFF
79#endif
80
81#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
82
83#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
84#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
85#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
86#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
87#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
88#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
89#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
90#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
91#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
92#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
93#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
94#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
95
96#endif
97
98#endif
diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h
deleted file mode 100644
index 6626e7864e28..000000000000
--- a/arch/arm/mach-msm/include/mach/vreg.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/include/asm-arm/arch-msm/vreg.h
2 *
3 * Copyright (C) 2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ARCH_ARM_MACH_MSM_VREG_H
18#define __ARCH_ARM_MACH_MSM_VREG_H
19
20struct vreg;
21
22struct vreg *vreg_get(struct device *dev, const char *id);
23void vreg_put(struct vreg *vreg);
24
25int vreg_enable(struct vreg *vreg);
26int vreg_disable(struct vreg *vreg);
27int vreg_set_level(struct vreg *vreg, unsigned mv);
28
29#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
deleted file mode 100644
index b042dca1f633..000000000000
--- a/arch/arm/mach-msm/io.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/* arch/arm/mach-msm/io.c
2 *
3 * MSM7K, QSD io support
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/bug.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/export.h>
25
26#include <mach/hardware.h>
27#include <asm/page.h>
28#include <mach/msm_iomap.h>
29#include <asm/mach/map.h>
30
31#include "common.h"
32
33#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
34 .virtual = (unsigned long) MSM_##name##_BASE, \
35 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
36 .length = chip##_##name##_SIZE, \
37 .type = mem_type, \
38 }
39
40#define MSM_DEVICE_TYPE(name, mem_type) \
41 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
42#define MSM_CHIP_DEVICE(name, chip) \
43 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
44#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
45
46#if defined(CONFIG_ARCH_MSM7X00A)
47static struct map_desc msm_io_desc[] __initdata = {
48 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
49 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
50 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
51 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
52 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
54 {
55 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
56 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
57 .length = MSM_SHARED_RAM_SIZE,
58 .type = MT_DEVICE,
59 },
60#if defined(CONFIG_DEBUG_MSM_UART)
61 {
62 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
63 .length = SZ_4K,
64 .type = MT_DEVICE_NONSHARED,
65 }
66#endif
67};
68
69void __init msm_map_common_io(void)
70{
71 size_t size = ARRAY_SIZE(msm_io_desc);
72
73 /* Make sure the peripheral register window is closed, since
74 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
75 * pages are peripheral interface or not.
76 */
77 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
78#if defined(CONFIG_DEBUG_MSM_UART)
79#ifdef CONFIG_MMU
80 debug_ll_addr(&msm_io_desc[size - 1].pfn,
81 &msm_io_desc[size - 1].virtual);
82#endif
83 msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
84#endif
85 iotable_init(msm_io_desc, size);
86}
87#endif
88
89#ifdef CONFIG_ARCH_QSD8X50
90static struct map_desc qsd8x50_io_desc[] __initdata = {
91 MSM_DEVICE(VIC),
92 MSM_CHIP_DEVICE(CSR, QSD8X50),
93 MSM_DEVICE(DMOV),
94 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
95 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
96 MSM_DEVICE(CLK_CTL),
97 MSM_DEVICE(SIRC),
98 MSM_DEVICE(SCPLL),
99 MSM_DEVICE(AD5),
100 MSM_DEVICE(MDC),
101 {
102 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
103 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
104 .length = MSM_SHARED_RAM_SIZE,
105 .type = MT_DEVICE,
106 },
107};
108
109void __init msm_map_qsd8x50_io(void)
110{
111 debug_ll_io_init();
112 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
113}
114#endif /* CONFIG_ARCH_QSD8X50 */
115
116#ifdef CONFIG_ARCH_MSM7X30
117static struct map_desc msm7x30_io_desc[] __initdata = {
118 MSM_DEVICE(VIC),
119 MSM_CHIP_DEVICE(CSR, MSM7X30),
120 MSM_DEVICE(DMOV),
121 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
122 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
123 MSM_DEVICE(CLK_CTL),
124 MSM_DEVICE(CLK_CTL_SH2),
125 MSM_DEVICE(AD5),
126 MSM_DEVICE(MDC),
127 MSM_DEVICE(ACC),
128 MSM_DEVICE(SAW),
129 MSM_DEVICE(GCC),
130 MSM_DEVICE(TCSR),
131 {
132 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
133 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
134 .length = MSM_SHARED_RAM_SIZE,
135 .type = MT_DEVICE,
136 },
137};
138
139void __init msm_map_msm7x30_io(void)
140{
141 debug_ll_io_init();
142 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
143}
144#endif /* CONFIG_ARCH_MSM7X30 */
145
146#ifdef CONFIG_ARCH_MSM7X00A
147void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
148 unsigned int mtype, void *caller)
149{
150 if (mtype == MT_DEVICE) {
151 /* The peripherals in the 88000000 - D0000000 range
152 * are only accessible by type MT_DEVICE_NONSHARED.
153 * Adjust mtype as necessary to make this "just work."
154 */
155 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
156 mtype = MT_DEVICE_NONSHARED;
157 }
158
159 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
160}
161#endif
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
deleted file mode 100644
index 1b54f807c2d0..000000000000
--- a/arch/arm/mach-msm/irq-vic.c
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/ptrace.h>
21#include <linux/timer.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24
25#include <asm/cacheflush.h>
26
27#include <mach/hardware.h>
28
29#include <mach/msm_iomap.h>
30
31#include "smd_private.h"
32
33enum {
34 IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
35 IRQ_DEBUG_SLEEP_INT = 1U << 1,
36 IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
37 IRQ_DEBUG_SLEEP = 1U << 3,
38 IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
39};
40static int msm_irq_debug_mask;
41module_param_named(debug_mask, msm_irq_debug_mask, int,
42 S_IRUGO | S_IWUSR | S_IWGRP);
43
44#define VIC_REG(off) (MSM_VIC_BASE + (off))
45#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
46#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
47
48#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
49#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
50#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
51#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
52#define VIC_INT_EN0 VIC_REG(0x0010)
53#define VIC_INT_EN1 VIC_REG(0x0014)
54#define VIC_INT_EN2 VIC_REG(0x0018)
55#define VIC_INT_EN3 VIC_REG(0x001C)
56#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
57#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
58#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
59#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
60#define VIC_INT_ENSET0 VIC_REG(0x0030)
61#define VIC_INT_ENSET1 VIC_REG(0x0034)
62#define VIC_INT_ENSET2 VIC_REG(0x0038)
63#define VIC_INT_ENSET3 VIC_REG(0x003C)
64#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
65#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
66#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
67#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
68#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
69#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
70#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
71#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
72#define VIC_NO_PEND_VAL VIC_REG(0x0060)
73
74#if defined(CONFIG_ARCH_MSM_SCORPION)
75#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
76#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
77#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */
78#else
79#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
80#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
81#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
82#endif
83
84#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
85#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
86#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
87#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
88#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
89#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
90#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
91#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
92#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
93#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
94#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
95#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
96#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
97#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
98#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
99#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
100#define VIC_SOFTINT0 VIC_REG(0x00C0)
101#define VIC_SOFTINT1 VIC_REG(0x00C4)
102#define VIC_SOFTINT2 VIC_REG(0x00C8)
103#define VIC_SOFTINT3 VIC_REG(0x00CC)
104#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
105#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
106#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
107
108#if defined(CONFIG_ARCH_MSM_SCORPION)
109#define VIC_FIQ_VEC_RD VIC_REG(0x00DC)
110#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
111#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
112#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
113#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
114#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
115#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
116#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
117#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
118#else
119#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
120#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
121#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
122#endif
123
124#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
125#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
126
127#if defined(CONFIG_ARCH_MSM7X30)
128#define VIC_NUM_REGS 4
129#else
130#define VIC_NUM_REGS 2
131#endif
132
133#if VIC_NUM_REGS == 2
134#define DPRINT_REGS(base_reg, format, ...) \
135 printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
136 readl(base_reg ## 0), readl(base_reg ## 1))
137#define DPRINT_ARRAY(array, format, ...) \
138 printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
139 array[0], array[1])
140#elif VIC_NUM_REGS == 4
141#define DPRINT_REGS(base_reg, format, ...) \
142 printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
143 readl(base_reg ## 0), readl(base_reg ## 1), \
144 readl(base_reg ## 2), readl(base_reg ## 3))
145#define DPRINT_ARRAY(array, format, ...) \
146 printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
147 array[0], array[1], \
148 array[2], array[3])
149#else
150#error "VIC_NUM_REGS set to illegal value"
151#endif
152
153static uint32_t msm_irq_smsm_wake_enable[2];
154static struct {
155 uint32_t int_en[2];
156 uint32_t int_type;
157 uint32_t int_polarity;
158 uint32_t int_select;
159} msm_irq_shadow_reg[VIC_NUM_REGS];
160static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
161
162#define SMSM_FAKE_IRQ (0xff)
163static uint8_t msm_irq_to_smsm[NR_IRQS] = {
164 [INT_MDDI_EXT] = 1,
165 [INT_MDDI_PRI] = 2,
166 [INT_MDDI_CLIENT] = 3,
167 [INT_USB_OTG] = 4,
168
169 [INT_PWB_I2C] = 5,
170 [INT_SDC1_0] = 6,
171 [INT_SDC1_1] = 7,
172 [INT_SDC2_0] = 8,
173
174 [INT_SDC2_1] = 9,
175 [INT_ADSP_A9_A11] = 10,
176 [INT_UART1] = 11,
177 [INT_UART2] = 12,
178
179 [INT_UART3] = 13,
180 [INT_UART1_RX] = 14,
181 [INT_UART2_RX] = 15,
182 [INT_UART3_RX] = 16,
183
184 [INT_UART1DM_IRQ] = 17,
185 [INT_UART1DM_RX] = 18,
186 [INT_KEYSENSE] = 19,
187#if !defined(CONFIG_ARCH_MSM7X30)
188 [INT_AD_HSSD] = 20,
189#endif
190
191 [INT_NAND_WR_ER_DONE] = 21,
192 [INT_NAND_OP_DONE] = 22,
193 [INT_TCHSCRN1] = 23,
194 [INT_TCHSCRN2] = 24,
195
196 [INT_TCHSCRN_SSBI] = 25,
197 [INT_USB_HS] = 26,
198 [INT_UART2DM_RX] = 27,
199 [INT_UART2DM_IRQ] = 28,
200
201 [INT_SDC4_1] = 29,
202 [INT_SDC4_0] = 30,
203 [INT_SDC3_1] = 31,
204 [INT_SDC3_0] = 32,
205
206 /* fake wakeup interrupts */
207 [INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
208 [INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
209 [INT_A9_M2A_0] = SMSM_FAKE_IRQ,
210 [INT_A9_M2A_1] = SMSM_FAKE_IRQ,
211 [INT_A9_M2A_5] = SMSM_FAKE_IRQ,
212 [INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
213 [INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
214 [INT_ADSP_A11] = SMSM_FAKE_IRQ,
215#ifdef CONFIG_ARCH_QSD8X50
216 [INT_SIRC_0] = SMSM_FAKE_IRQ,
217 [INT_SIRC_1] = SMSM_FAKE_IRQ,
218#endif
219};
220
221static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
222{
223 int i;
224
225 for (i = 0; i < VIC_NUM_REGS; i++)
226 writel(val, base + (i * 4));
227}
228
229static void msm_irq_ack(struct irq_data *d)
230{
231 void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq);
232 writel(1 << (d->irq & 31), reg);
233}
234
235static void msm_irq_mask(struct irq_data *d)
236{
237 void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq);
238 unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
239 uint32_t mask = 1UL << (d->irq & 31);
240 int smsm_irq = msm_irq_to_smsm[d->irq];
241
242 msm_irq_shadow_reg[index].int_en[0] &= ~mask;
243 writel(mask, reg);
244 if (smsm_irq == 0)
245 msm_irq_idle_disable[index] &= ~mask;
246 else {
247 mask = 1UL << (smsm_irq - 1);
248 msm_irq_smsm_wake_enable[0] &= ~mask;
249 }
250}
251
252static void msm_irq_unmask(struct irq_data *d)
253{
254 void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq);
255 unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
256 uint32_t mask = 1UL << (d->irq & 31);
257 int smsm_irq = msm_irq_to_smsm[d->irq];
258
259 msm_irq_shadow_reg[index].int_en[0] |= mask;
260 writel(mask, reg);
261
262 if (smsm_irq == 0)
263 msm_irq_idle_disable[index] |= mask;
264 else {
265 mask = 1UL << (smsm_irq - 1);
266 msm_irq_smsm_wake_enable[0] |= mask;
267 }
268}
269
270static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
271{
272 unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
273 uint32_t mask = 1UL << (d->irq & 31);
274 int smsm_irq = msm_irq_to_smsm[d->irq];
275
276 if (smsm_irq == 0) {
277 printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq);
278 return -EINVAL;
279 }
280 if (on)
281 msm_irq_shadow_reg[index].int_en[1] |= mask;
282 else
283 msm_irq_shadow_reg[index].int_en[1] &= ~mask;
284
285 if (smsm_irq == SMSM_FAKE_IRQ)
286 return 0;
287
288 mask = 1UL << (smsm_irq - 1);
289 if (on)
290 msm_irq_smsm_wake_enable[1] |= mask;
291 else
292 msm_irq_smsm_wake_enable[1] &= ~mask;
293 return 0;
294}
295
296static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
297{
298 void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq);
299 void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq);
300 unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
301 int b = 1 << (d->irq & 31);
302 uint32_t polarity;
303 uint32_t type;
304
305 polarity = msm_irq_shadow_reg[index].int_polarity;
306 if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
307 polarity |= b;
308 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
309 polarity &= ~b;
310 writel(polarity, preg);
311 msm_irq_shadow_reg[index].int_polarity = polarity;
312
313 type = msm_irq_shadow_reg[index].int_type;
314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315 type |= b;
316 __irq_set_handler_locked(d->irq, handle_edge_irq);
317 }
318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
319 type &= ~b;
320 __irq_set_handler_locked(d->irq, handle_level_irq);
321 }
322 writel(type, treg);
323 msm_irq_shadow_reg[index].int_type = type;
324 return 0;
325}
326
327static struct irq_chip msm_irq_chip = {
328 .name = "msm",
329 .irq_disable = msm_irq_mask,
330 .irq_ack = msm_irq_ack,
331 .irq_mask = msm_irq_mask,
332 .irq_unmask = msm_irq_unmask,
333 .irq_set_wake = msm_irq_set_wake,
334 .irq_set_type = msm_irq_set_type,
335};
336
337void __init msm_init_irq(void)
338{
339 unsigned n;
340
341 /* select level interrupts */
342 msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
343
344 /* select highlevel interrupts */
345 msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
346
347 /* select IRQ for all INTs */
348 msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
349
350 /* disable all INTs */
351 msm_irq_write_all_regs(VIC_INT_EN0, 0);
352
353 /* don't use vic */
354 writel(0, VIC_CONFIG);
355
356 /* enable interrupt controller */
357 writel(3, VIC_INT_MASTEREN);
358
359 for (n = 0; n < NR_MSM_IRQS; n++) {
360 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
361 set_irq_flags(n, IRQF_VALID);
362 }
363}
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
deleted file mode 100644
index ea514be390c6..000000000000
--- a/arch/arm/mach-msm/irq.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/* linux/arch/arm/mach-msm/irq.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/ptrace.h>
21#include <linux/timer.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26
27#include <mach/msm_iomap.h>
28
29#define VIC_REG(off) (MSM_VIC_BASE + (off))
30
31#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
32#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
33#define VIC_INT_EN0 VIC_REG(0x0010)
34#define VIC_INT_EN1 VIC_REG(0x0014)
35#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
36#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
37#define VIC_INT_ENSET0 VIC_REG(0x0030)
38#define VIC_INT_ENSET1 VIC_REG(0x0034)
39#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
40#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
41#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
42#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
43#define VIC_NO_PEND_VAL VIC_REG(0x0060)
44#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
45#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
46#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
47#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
48#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
49#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
50#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
51#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
52#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
53#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
54#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
55#define VIC_SOFTINT0 VIC_REG(0x00C0)
56#define VIC_SOFTINT1 VIC_REG(0x00C4)
57#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
58#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
59#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
60#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
61#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
62#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
63
64#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
65#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
66
67static void msm_irq_ack(struct irq_data *d)
68{
69 void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
70 writel(1 << (d->irq & 31), reg);
71}
72
73static void msm_irq_mask(struct irq_data *d)
74{
75 void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
76 writel(1 << (d->irq & 31), reg);
77}
78
79static void msm_irq_unmask(struct irq_data *d)
80{
81 void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
82 writel(1 << (d->irq & 31), reg);
83}
84
85static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
86{
87 return -EINVAL;
88}
89
90static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
91{
92 void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
93 void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
94 int b = 1 << (d->irq & 31);
95
96 if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
97 writel(readl(preg) | b, preg);
98 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
99 writel(readl(preg) & (~b), preg);
100
101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
102 writel(readl(treg) | b, treg);
103 __irq_set_handler_locked(d->irq, handle_edge_irq);
104 }
105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
106 writel(readl(treg) & (~b), treg);
107 __irq_set_handler_locked(d->irq, handle_level_irq);
108 }
109 return 0;
110}
111
112static struct irq_chip msm_irq_chip = {
113 .name = "msm",
114 .irq_ack = msm_irq_ack,
115 .irq_mask = msm_irq_mask,
116 .irq_unmask = msm_irq_unmask,
117 .irq_set_wake = msm_irq_set_wake,
118 .irq_set_type = msm_irq_set_type,
119};
120
121void __init msm_init_irq(void)
122{
123 unsigned n;
124
125 /* select level interrupts */
126 writel(0, VIC_INT_TYPE0);
127 writel(0, VIC_INT_TYPE1);
128
129 /* select highlevel interrupts */
130 writel(0, VIC_INT_POLARITY0);
131 writel(0, VIC_INT_POLARITY1);
132
133 /* select IRQ for all INTs */
134 writel(0, VIC_INT_SELECT0);
135 writel(0, VIC_INT_SELECT1);
136
137 /* disable all INTs */
138 writel(0, VIC_INT_EN0);
139 writel(0, VIC_INT_EN1);
140
141 /* don't use 1136 vic */
142 writel(0, VIC_CONFIG);
143
144 /* enable interrupt controller */
145 writel(1, VIC_INT_MASTEREN);
146
147 for (n = 0; n < NR_MSM_IRQS; n++) {
148 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
149 set_irq_flags(n, IRQF_VALID);
150 }
151}
diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c
deleted file mode 100644
index 9c392a29fc7e..000000000000
--- a/arch/arm/mach-msm/last_radio_log.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/* arch/arm/mach-msm/last_radio_log.c
2 *
3 * Extract the log from a modem crash though SMEM
4 *
5 * Copyright (C) 2007 Google, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/fs.h>
21#include <linux/proc_fs.h>
22#include <linux/uaccess.h>
23
24#include "smd_private.h"
25
26static void *radio_log_base;
27static size_t radio_log_size;
28
29extern void *smem_item(unsigned id, unsigned *size);
30
31static ssize_t last_radio_log_read(struct file *file, char __user *buf,
32 size_t len, loff_t *offset)
33{
34 return simple_read_from_buffer(buf, len, offset,
35 radio_log_base, radio_log_size);
36}
37
38static struct file_operations last_radio_log_fops = {
39 .read = last_radio_log_read,
40 .llseek = default_llseek,
41};
42
43void msm_init_last_radio_log(struct module *owner)
44{
45 struct proc_dir_entry *entry;
46
47 if (last_radio_log_fops.owner) {
48 pr_err("%s: already claimed\n", __func__);
49 return;
50 }
51
52 radio_log_base = smem_item(SMEM_CLKREGIM_BSP, &radio_log_size);
53 if (!radio_log_base) {
54 pr_err("%s: could not retrieve SMEM_CLKREGIM_BSP\n", __func__);
55 return;
56 }
57
58 entry = proc_create("last_radio_log", S_IRUGO, NULL,
59 &last_radio_log_fops);
60 if (!entry) {
61 pr_err("%s: could not create proc entry for radio log\n",
62 __func__);
63 return;
64 }
65
66 pr_err("%s: last radio log is %d bytes long\n", __func__,
67 radio_log_size);
68 last_radio_log_fops.owner = owner;
69 proc_set_size(entry, radio_log_size);
70}
71EXPORT_SYMBOL(msm_init_last_radio_log);
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
deleted file mode 100644
index 507f5ca80697..000000000000
--- a/arch/arm/mach-msm/proc_comm.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/* arch/arm/mach-msm/proc_comm.c
2 *
3 * Copyright (C) 2007-2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/io.h>
20#include <linux/spinlock.h>
21#include <mach/msm_iomap.h>
22
23#include "proc_comm.h"
24
25static inline void msm_a2m_int(uint32_t irq)
26{
27#if defined(CONFIG_ARCH_MSM7X30)
28 writel(1 << irq, MSM_GCC_BASE + 0x8);
29#else
30 writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
31#endif
32}
33
34static inline void notify_other_proc_comm(void)
35{
36 msm_a2m_int(6);
37}
38
39#define APP_COMMAND 0x00
40#define APP_STATUS 0x04
41#define APP_DATA1 0x08
42#define APP_DATA2 0x0C
43
44#define MDM_COMMAND 0x10
45#define MDM_STATUS 0x14
46#define MDM_DATA1 0x18
47#define MDM_DATA2 0x1C
48
49static DEFINE_SPINLOCK(proc_comm_lock);
50
51/* The higher level SMD support will install this to
52 * provide a way to check for and handle modem restart.
53 */
54int (*msm_check_for_modem_crash)(void);
55
56/* Poll for a state change, checking for possible
57 * modem crashes along the way (so we don't wait
58 * forever while the ARM9 is blowing up).
59 *
60 * Return an error in the event of a modem crash and
61 * restart so the msm_proc_comm() routine can restart
62 * the operation from the beginning.
63 */
64static int proc_comm_wait_for(void __iomem *addr, unsigned value)
65{
66 for (;;) {
67 if (readl(addr) == value)
68 return 0;
69
70 if (msm_check_for_modem_crash)
71 if (msm_check_for_modem_crash())
72 return -EAGAIN;
73 }
74}
75
76int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
77{
78 void __iomem *base = MSM_SHARED_RAM_BASE;
79 unsigned long flags;
80 int ret;
81
82 spin_lock_irqsave(&proc_comm_lock, flags);
83
84 for (;;) {
85 if (proc_comm_wait_for(base + MDM_STATUS, PCOM_READY))
86 continue;
87
88 writel(cmd, base + APP_COMMAND);
89 writel(data1 ? *data1 : 0, base + APP_DATA1);
90 writel(data2 ? *data2 : 0, base + APP_DATA2);
91
92 notify_other_proc_comm();
93
94 if (proc_comm_wait_for(base + APP_COMMAND, PCOM_CMD_DONE))
95 continue;
96
97 if (readl(base + APP_STATUS) != PCOM_CMD_FAIL) {
98 if (data1)
99 *data1 = readl(base + APP_DATA1);
100 if (data2)
101 *data2 = readl(base + APP_DATA2);
102 ret = 0;
103 } else {
104 ret = -EIO;
105 }
106 break;
107 }
108
109 writel(PCOM_CMD_IDLE, base + APP_COMMAND);
110
111 spin_unlock_irqrestore(&proc_comm_lock, flags);
112
113 return ret;
114}
115
116/*
117 * We need to wait for the ARM9 to at least partially boot
118 * up before we can continue. Since the ARM9 does resource
119 * allocation, if we dont' wait we could end up crashing or in
120 * and unknown state. This function should be called early to
121 * wait on the ARM9.
122 */
123void proc_comm_boot_wait(void)
124{
125 void __iomem *base = MSM_SHARED_RAM_BASE;
126
127 proc_comm_wait_for(base + MDM_STATUS, PCOM_READY);
128
129}
diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h
deleted file mode 100644
index e8d043a0e990..000000000000
--- a/arch/arm/mach-msm/proc_comm.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/* arch/arm/mach-msm/proc_comm.h
2 *
3 * Copyright (c) 2007 QUALCOMM Incorporated
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef _ARCH_ARM_MACH_MSM_PROC_COMM_H_
17#define _ARCH_ARM_MACH_MSM_PROC_COMM_H_
18
19#include <linux/init.h>
20
21enum {
22 PCOM_CMD_IDLE = 0x0,
23 PCOM_CMD_DONE,
24 PCOM_RESET_APPS,
25 PCOM_RESET_CHIP,
26 PCOM_CONFIG_NAND_MPU,
27 PCOM_CONFIG_USB_CLKS,
28 PCOM_GET_POWER_ON_STATUS,
29 PCOM_GET_WAKE_UP_STATUS,
30 PCOM_GET_BATT_LEVEL,
31 PCOM_CHG_IS_CHARGING,
32 PCOM_POWER_DOWN,
33 PCOM_USB_PIN_CONFIG,
34 PCOM_USB_PIN_SEL,
35 PCOM_SET_RTC_ALARM,
36 PCOM_NV_READ,
37 PCOM_NV_WRITE,
38 PCOM_GET_UUID_HIGH,
39 PCOM_GET_UUID_LOW,
40 PCOM_GET_HW_ENTROPY,
41 PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
42 PCOM_CLKCTL_RPC_ENABLE,
43 PCOM_CLKCTL_RPC_DISABLE,
44 PCOM_CLKCTL_RPC_RESET,
45 PCOM_CLKCTL_RPC_SET_FLAGS,
46 PCOM_CLKCTL_RPC_SET_RATE,
47 PCOM_CLKCTL_RPC_MIN_RATE,
48 PCOM_CLKCTL_RPC_MAX_RATE,
49 PCOM_CLKCTL_RPC_RATE,
50 PCOM_CLKCTL_RPC_PLL_REQUEST,
51 PCOM_CLKCTL_RPC_ENABLED,
52 PCOM_VREG_SWITCH,
53 PCOM_VREG_SET_LEVEL,
54 PCOM_GPIO_TLMM_CONFIG_GROUP,
55 PCOM_GPIO_TLMM_UNCONFIG_GROUP,
56 PCOM_NV_WRITE_BYTES_4_7,
57 PCOM_CONFIG_DISP,
58 PCOM_GET_FTM_BOOT_COUNT,
59 PCOM_RPC_GPIO_TLMM_CONFIG_EX,
60 PCOM_PM_MPP_CONFIG,
61 PCOM_GPIO_IN,
62 PCOM_GPIO_OUT,
63 PCOM_RESET_MODEM,
64 PCOM_RESET_CHIP_IMM,
65 PCOM_PM_VID_EN,
66 PCOM_VREG_PULLDOWN,
67 PCOM_GET_MODEM_VERSION,
68 PCOM_CLK_REGIME_SEC_RESET,
69 PCOM_CLK_REGIME_SEC_RESET_ASSERT,
70 PCOM_CLK_REGIME_SEC_RESET_DEASSERT,
71 PCOM_CLK_REGIME_SEC_PLL_REQUEST_WRP,
72 PCOM_CLK_REGIME_SEC_ENABLE,
73 PCOM_CLK_REGIME_SEC_DISABLE,
74 PCOM_CLK_REGIME_SEC_IS_ON,
75 PCOM_CLK_REGIME_SEC_SEL_CLK_INV,
76 PCOM_CLK_REGIME_SEC_SEL_CLK_SRC,
77 PCOM_CLK_REGIME_SEC_SEL_CLK_DIV,
78 PCOM_CLK_REGIME_SEC_ICODEC_CLK_ENABLE,
79 PCOM_CLK_REGIME_SEC_ICODEC_CLK_DISABLE,
80 PCOM_CLK_REGIME_SEC_SEL_SPEED,
81 PCOM_CLK_REGIME_SEC_CONFIG_GP_CLK_WRP,
82 PCOM_CLK_REGIME_SEC_CONFIG_MDH_CLK_WRP,
83 PCOM_CLK_REGIME_SEC_USB_XTAL_ON,
84 PCOM_CLK_REGIME_SEC_USB_XTAL_OFF,
85 PCOM_CLK_REGIME_SEC_SET_QDSP_DME_MODE,
86 PCOM_CLK_REGIME_SEC_SWITCH_ADSP_CLK,
87 PCOM_CLK_REGIME_SEC_GET_MAX_ADSP_CLK_KHZ,
88 PCOM_CLK_REGIME_SEC_GET_I2C_CLK_KHZ,
89 PCOM_CLK_REGIME_SEC_MSM_GET_CLK_FREQ_KHZ,
90 PCOM_CLK_REGIME_SEC_SEL_VFE_SRC,
91 PCOM_CLK_REGIME_SEC_MSM_SEL_CAMCLK,
92 PCOM_CLK_REGIME_SEC_MSM_SEL_LCDCLK,
93 PCOM_CLK_REGIME_SEC_VFE_RAIL_OFF,
94 PCOM_CLK_REGIME_SEC_VFE_RAIL_ON,
95 PCOM_CLK_REGIME_SEC_GRP_RAIL_OFF,
96 PCOM_CLK_REGIME_SEC_GRP_RAIL_ON,
97 PCOM_CLK_REGIME_SEC_VDC_RAIL_OFF,
98 PCOM_CLK_REGIME_SEC_VDC_RAIL_ON,
99 PCOM_CLK_REGIME_SEC_LCD_CTRL,
100 PCOM_CLK_REGIME_SEC_REGISTER_FOR_CPU_RESOURCE,
101 PCOM_CLK_REGIME_SEC_DEREGISTER_FOR_CPU_RESOURCE,
102 PCOM_CLK_REGIME_SEC_RESOURCE_REQUEST_WRP,
103 PCOM_CLK_REGIME_MSM_SEC_SEL_CLK_OWNER,
104 PCOM_CLK_REGIME_SEC_DEVMAN_REQUEST_WRP,
105 PCOM_GPIO_CONFIG,
106 PCOM_GPIO_CONFIGURE_GROUP,
107 PCOM_GPIO_TLMM_SET_PORT,
108 PCOM_GPIO_TLMM_CONFIG_EX,
109 PCOM_SET_FTM_BOOT_COUNT,
110 PCOM_RESERVED0,
111 PCOM_RESERVED1,
112 PCOM_CUSTOMER_CMD1,
113 PCOM_CUSTOMER_CMD2,
114 PCOM_CUSTOMER_CMD3,
115 PCOM_CLK_REGIME_ENTER_APPSBL_CHG_MODE,
116 PCOM_CLK_REGIME_EXIT_APPSBL_CHG_MODE,
117 PCOM_CLK_REGIME_SEC_RAIL_DISABLE,
118 PCOM_CLK_REGIME_SEC_RAIL_ENABLE,
119 PCOM_CLK_REGIME_SEC_RAIL_CONTROL,
120 PCOM_SET_SW_WATCHDOG_STATE,
121 PCOM_PM_MPP_CONFIG_DIGITAL_INPUT,
122 PCOM_PM_MPP_CONFIG_I_SINK,
123 PCOM_RESERVED_101,
124 PCOM_MSM_HSUSB_PHY_RESET,
125 PCOM_GET_BATT_MV_LEVEL,
126 PCOM_CHG_USB_IS_PC_CONNECTED,
127 PCOM_CHG_USB_IS_CHARGER_CONNECTED,
128 PCOM_CHG_USB_IS_DISCONNECTED,
129 PCOM_CHG_USB_IS_AVAILABLE,
130 PCOM_CLK_REGIME_SEC_MSM_SEL_FREQ,
131 PCOM_CLK_REGIME_SEC_SET_PCLK_AXI_POLICY,
132 PCOM_CLKCTL_RPC_RESET_ASSERT,
133 PCOM_CLKCTL_RPC_RESET_DEASSERT,
134 PCOM_CLKCTL_RPC_RAIL_ON,
135 PCOM_CLKCTL_RPC_RAIL_OFF,
136 PCOM_CLKCTL_RPC_RAIL_ENABLE,
137 PCOM_CLKCTL_RPC_RAIL_DISABLE,
138 PCOM_CLKCTL_RPC_RAIL_CONTROL,
139 PCOM_CLKCTL_RPC_MIN_MSMC1,
140 PCOM_NUM_CMDS,
141};
142
143enum {
144 PCOM_INVALID_STATUS = 0x0,
145 PCOM_READY,
146 PCOM_CMD_RUNNING,
147 PCOM_CMD_SUCCESS,
148 PCOM_CMD_FAIL,
149 PCOM_CMD_FAIL_FALSE_RETURNED,
150 PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_SERVER,
151 PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_CLIENT,
152 PCOM_CMD_FAIL_CMD_UNREGISTERED,
153 PCOM_CMD_FAIL_CMD_LOCKED,
154 PCOM_CMD_FAIL_SERVER_NOT_YET_READY,
155 PCOM_CMD_FAIL_BAD_DESTINATION,
156 PCOM_CMD_FAIL_SERVER_RESET,
157 PCOM_CMD_FAIL_SMSM_NOT_INIT,
158 PCOM_CMD_FAIL_PROC_COMM_BUSY,
159 PCOM_CMD_FAIL_PROC_COMM_NOT_INIT,
160
161};
162
163/* List of VREGs that support the Pull Down Resistor setting. */
164enum vreg_pdown_id {
165 PM_VREG_PDOWN_MSMA_ID,
166 PM_VREG_PDOWN_MSMP_ID,
167 PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */
168 PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */
169 PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */
170 PM_VREG_PDOWN_GP3_ID, /* Supported in PM7500 only */
171 PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */
172 PM_VREG_PDOWN_GP4_ID, /* Supported in PM7500 only */
173 PM_VREG_PDOWN_GP1_ID, /* Supported in PM7500 only */
174 PM_VREG_PDOWN_TCXO_ID,
175 PM_VREG_PDOWN_PA_ID,
176 PM_VREG_PDOWN_RFTX_ID,
177 PM_VREG_PDOWN_RFRX1_ID,
178 PM_VREG_PDOWN_RFRX2_ID,
179 PM_VREG_PDOWN_SYNT_ID,
180 PM_VREG_PDOWN_WLAN_ID,
181 PM_VREG_PDOWN_USB_ID,
182 PM_VREG_PDOWN_MMC_ID,
183 PM_VREG_PDOWN_RUIM_ID,
184 PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */
185 PM_VREG_PDOWN_GP2_ID, /* Supported in PM7500 only */
186 PM_VREG_PDOWN_GP5_ID, /* Supported in PM7500 only */
187 PM_VREG_PDOWN_GP6_ID, /* Supported in PM7500 only */
188 PM_VREG_PDOWN_RF_ID,
189 PM_VREG_PDOWN_RF_VCO_ID,
190 PM_VREG_PDOWN_MPLL_ID,
191 PM_VREG_PDOWN_S2_ID,
192 PM_VREG_PDOWN_S3_ID,
193 PM_VREG_PDOWN_RFUBM_ID,
194
195 /* new for HAN */
196 PM_VREG_PDOWN_RF1_ID,
197 PM_VREG_PDOWN_RF2_ID,
198 PM_VREG_PDOWN_RFA_ID,
199 PM_VREG_PDOWN_CDC2_ID,
200 PM_VREG_PDOWN_RFTX2_ID,
201 PM_VREG_PDOWN_USIM_ID,
202 PM_VREG_PDOWN_USB2P6_ID,
203 PM_VREG_PDOWN_USB3P3_ID,
204 PM_VREG_PDOWN_INVALID_ID,
205
206 /* backward compatible enums only */
207 PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID,
208 PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID,
209 PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID,
210 PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID,
211 PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID,
212 PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID,
213
214 PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID,
215 PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID,
216 PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID,
217 PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID,
218 PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID
219};
220
221enum {
222 PCOM_CLKRGM_APPS_RESET_USB_PHY = 34,
223 PCOM_CLKRGM_APPS_RESET_USBH = 37,
224};
225
226/* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */
227
228#define GPIO_ENABLE 0
229#define GPIO_DISABLE 1
230
231#define GPIO_INPUT 0
232#define GPIO_OUTPUT 1
233
234#define GPIO_NO_PULL 0
235#define GPIO_PULL_DOWN 1
236#define GPIO_KEEPER 2
237#define GPIO_PULL_UP 3
238
239#define GPIO_2MA 0
240#define GPIO_4MA 1
241#define GPIO_6MA 2
242#define GPIO_8MA 3
243#define GPIO_10MA 4
244#define GPIO_12MA 5
245#define GPIO_14MA 6
246#define GPIO_16MA 7
247
248#define PCOM_GPIO_CFG(gpio, func, dir, pull, drvstr) \
249 ((((gpio) & 0x3FF) << 4) | \
250 ((func) & 0xf) | \
251 (((dir) & 0x1) << 14) | \
252 (((pull) & 0x3) << 15) | \
253 (((drvstr) & 0xF) << 17))
254
255int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
256void proc_comm_boot_wait(void);
257
258#endif
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
deleted file mode 100644
index 689e78c95f38..000000000000
--- a/arch/arm/mach-msm/sirc.c
+++ /dev/null
@@ -1,172 +0,0 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <asm/irq.h>
23
24static unsigned int int_enable;
25static unsigned int wake_enable;
26
27static struct sirc_regs_t sirc_regs = {
28 .int_enable = SPSS_SIRC_INT_ENABLE,
29 .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
30 .int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
31 .int_type = SPSS_SIRC_INT_TYPE,
32 .int_polarity = SPSS_SIRC_INT_POLARITY,
33 .int_clear = SPSS_SIRC_INT_CLEAR,
34};
35
36static struct sirc_cascade_regs sirc_reg_table[] = {
37 {
38 .int_status = SPSS_SIRC_IRQ_STATUS,
39 .cascade_irq = INT_SIRC_0,
40 }
41};
42
43/* Mask off the given interrupt. Keep the int_enable mask in sync with
44 the enable reg, so it can be restored after power collapse. */
45static void sirc_irq_mask(struct irq_data *d)
46{
47 unsigned int mask;
48
49 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
50 writel(mask, sirc_regs.int_enable_clear);
51 int_enable &= ~mask;
52 return;
53}
54
55/* Unmask the given interrupt. Keep the int_enable mask in sync with
56 the enable reg, so it can be restored after power collapse. */
57static void sirc_irq_unmask(struct irq_data *d)
58{
59 unsigned int mask;
60
61 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
62 writel(mask, sirc_regs.int_enable_set);
63 int_enable |= mask;
64 return;
65}
66
67static void sirc_irq_ack(struct irq_data *d)
68{
69 unsigned int mask;
70
71 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
72 writel(mask, sirc_regs.int_clear);
73 return;
74}
75
76static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
77{
78 unsigned int mask;
79
80 /* Used to set the interrupt enable mask during power collapse. */
81 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
82 if (on)
83 wake_enable |= mask;
84 else
85 wake_enable &= ~mask;
86
87 return 0;
88}
89
90static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
91{
92 unsigned int mask;
93 unsigned int val;
94
95 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
96 val = readl(sirc_regs.int_polarity);
97
98 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
99 val |= mask;
100 else
101 val &= ~mask;
102
103 writel(val, sirc_regs.int_polarity);
104
105 val = readl(sirc_regs.int_type);
106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
107 val |= mask;
108 __irq_set_handler_locked(d->irq, handle_edge_irq);
109 } else {
110 val &= ~mask;
111 __irq_set_handler_locked(d->irq, handle_level_irq);
112 }
113
114 writel(val, sirc_regs.int_type);
115
116 return 0;
117}
118
119/* Finds the pending interrupt on the passed cascade irq and redrives it */
120static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
121{
122 unsigned int reg = 0;
123 unsigned int sirq;
124 unsigned int status;
125
126 while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
127 (sirc_reg_table[reg].cascade_irq != irq))
128 reg++;
129
130 status = readl(sirc_reg_table[reg].int_status);
131 status &= SIRC_MASK;
132 if (status == 0)
133 return;
134
135 for (sirq = 0;
136 (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
137 sirq++)
138 ;
139 generic_handle_irq(sirq+FIRST_SIRC_IRQ);
140
141 desc->irq_data.chip->irq_ack(&desc->irq_data);
142}
143
144static struct irq_chip sirc_irq_chip = {
145 .name = "sirc",
146 .irq_ack = sirc_irq_ack,
147 .irq_mask = sirc_irq_mask,
148 .irq_unmask = sirc_irq_unmask,
149 .irq_set_wake = sirc_irq_set_wake,
150 .irq_set_type = sirc_irq_set_type,
151};
152
153void __init msm_init_sirc(void)
154{
155 int i;
156
157 int_enable = 0;
158 wake_enable = 0;
159
160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
161 irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
162 set_irq_flags(i, IRQF_VALID);
163 }
164
165 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
166 irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
167 sirc_irq_handler);
168 irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
169 }
170 return;
171}
172
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
deleted file mode 100644
index 7550f5a08956..000000000000
--- a/arch/arm/mach-msm/smd.c
+++ /dev/null
@@ -1,1034 +0,0 @@
1/* arch/arm/mach-msm/smd.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/platform_device.h>
20#include <linux/module.h>
21#include <linux/fs.h>
22#include <linux/cdev.h>
23#include <linux/device.h>
24#include <linux/wait.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/list.h>
28#include <linux/slab.h>
29#include <linux/debugfs.h>
30#include <linux/delay.h>
31
32#include <mach/msm_smd.h>
33
34#include "smd_private.h"
35#include "proc_comm.h"
36
37#if defined(CONFIG_ARCH_QSD8X50)
38#define CONFIG_QDSP6 1
39#endif
40
41#define MODULE_NAME "msm_smd"
42
43enum {
44 MSM_SMD_DEBUG = 1U << 0,
45 MSM_SMSM_DEBUG = 1U << 0,
46};
47
48static int msm_smd_debug_mask;
49
50struct shared_info {
51 int ready;
52 void __iomem *state;
53};
54
55static unsigned dummy_state[SMSM_STATE_COUNT];
56
57static struct shared_info smd_info = {
58 /* FIXME: not a real __iomem pointer */
59 .state = &dummy_state,
60};
61
62module_param_named(debug_mask, msm_smd_debug_mask,
63 int, S_IRUGO | S_IWUSR | S_IWGRP);
64
65static unsigned last_heap_free = 0xffffffff;
66
67static inline void notify_other_smsm(void)
68{
69 msm_a2m_int(5);
70#ifdef CONFIG_QDSP6
71 msm_a2m_int(8);
72#endif
73}
74
75static inline void notify_modem_smd(void)
76{
77 msm_a2m_int(0);
78}
79
80static inline void notify_dsp_smd(void)
81{
82 msm_a2m_int(8);
83}
84
85static void smd_diag(void)
86{
87 char *x;
88
89 x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
90 if (x != 0) {
91 x[SZ_DIAG_ERR_MSG - 1] = 0;
92 pr_debug("DIAG '%s'\n", x);
93 }
94}
95
96/* call when SMSM_RESET flag is set in the A9's smsm_state */
97static void handle_modem_crash(void)
98{
99 pr_err("ARM9 has CRASHED\n");
100 smd_diag();
101
102 /* in this case the modem or watchdog should reboot us */
103 for (;;)
104 ;
105}
106
107uint32_t raw_smsm_get_state(enum smsm_state_item item)
108{
109 return readl(smd_info.state + item * 4);
110}
111
112static int check_for_modem_crash(void)
113{
114 if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET) {
115 handle_modem_crash();
116 return -1;
117 }
118 return 0;
119}
120
121/* the spinlock is used to synchronize between the
122 * irq handler and code that mutates the channel
123 * list or fiddles with channel state
124 */
125DEFINE_SPINLOCK(smd_lock);
126DEFINE_SPINLOCK(smem_lock);
127
128/* the mutex is used during open() and close()
129 * operations to avoid races while creating or
130 * destroying smd_channel structures
131 */
132static DEFINE_MUTEX(smd_creation_mutex);
133
134static int smd_initialized;
135
136LIST_HEAD(smd_ch_closed_list);
137LIST_HEAD(smd_ch_list_modem);
138LIST_HEAD(smd_ch_list_dsp);
139
140static unsigned char smd_ch_allocated[64];
141static struct work_struct probe_work;
142
143/* how many bytes are available for reading */
144static int smd_stream_read_avail(struct smd_channel *ch)
145{
146 return (ch->recv->head - ch->recv->tail) & ch->fifo_mask;
147}
148
149/* how many bytes we are free to write */
150static int smd_stream_write_avail(struct smd_channel *ch)
151{
152 return ch->fifo_mask -
153 ((ch->send->head - ch->send->tail) & ch->fifo_mask);
154}
155
156static int smd_packet_read_avail(struct smd_channel *ch)
157{
158 if (ch->current_packet) {
159 int n = smd_stream_read_avail(ch);
160 if (n > ch->current_packet)
161 n = ch->current_packet;
162 return n;
163 } else {
164 return 0;
165 }
166}
167
168static int smd_packet_write_avail(struct smd_channel *ch)
169{
170 int n = smd_stream_write_avail(ch);
171 return n > SMD_HEADER_SIZE ? n - SMD_HEADER_SIZE : 0;
172}
173
174static int ch_is_open(struct smd_channel *ch)
175{
176 return (ch->recv->state == SMD_SS_OPENED) &&
177 (ch->send->state == SMD_SS_OPENED);
178}
179
180/* provide a pointer and length to readable data in the fifo */
181static unsigned ch_read_buffer(struct smd_channel *ch, void **ptr)
182{
183 unsigned head = ch->recv->head;
184 unsigned tail = ch->recv->tail;
185 *ptr = (void *) (ch->recv_data + tail);
186
187 if (tail <= head)
188 return head - tail;
189 else
190 return ch->fifo_size - tail;
191}
192
193/* advance the fifo read pointer after data from ch_read_buffer is consumed */
194static void ch_read_done(struct smd_channel *ch, unsigned count)
195{
196 BUG_ON(count > smd_stream_read_avail(ch));
197 ch->recv->tail = (ch->recv->tail + count) & ch->fifo_mask;
198 ch->send->fTAIL = 1;
199}
200
201/* basic read interface to ch_read_{buffer,done} used
202 * by smd_*_read() and update_packet_state()
203 * will read-and-discard if the _data pointer is null
204 */
205static int ch_read(struct smd_channel *ch, void *_data, int len)
206{
207 void *ptr;
208 unsigned n;
209 unsigned char *data = _data;
210 int orig_len = len;
211
212 while (len > 0) {
213 n = ch_read_buffer(ch, &ptr);
214 if (n == 0)
215 break;
216
217 if (n > len)
218 n = len;
219 if (_data)
220 memcpy(data, ptr, n);
221
222 data += n;
223 len -= n;
224 ch_read_done(ch, n);
225 }
226
227 return orig_len - len;
228}
229
230static void update_stream_state(struct smd_channel *ch)
231{
232 /* streams have no special state requiring updating */
233}
234
235static void update_packet_state(struct smd_channel *ch)
236{
237 unsigned hdr[5];
238 int r;
239
240 /* can't do anything if we're in the middle of a packet */
241 if (ch->current_packet != 0)
242 return;
243
244 /* don't bother unless we can get the full header */
245 if (smd_stream_read_avail(ch) < SMD_HEADER_SIZE)
246 return;
247
248 r = ch_read(ch, hdr, SMD_HEADER_SIZE);
249 BUG_ON(r != SMD_HEADER_SIZE);
250
251 ch->current_packet = hdr[0];
252}
253
254/* provide a pointer and length to next free space in the fifo */
255static unsigned ch_write_buffer(struct smd_channel *ch, void **ptr)
256{
257 unsigned head = ch->send->head;
258 unsigned tail = ch->send->tail;
259 *ptr = (void *) (ch->send_data + head);
260
261 if (head < tail) {
262 return tail - head - 1;
263 } else {
264 if (tail == 0)
265 return ch->fifo_size - head - 1;
266 else
267 return ch->fifo_size - head;
268 }
269}
270
271/* advace the fifo write pointer after freespace
272 * from ch_write_buffer is filled
273 */
274static void ch_write_done(struct smd_channel *ch, unsigned count)
275{
276 BUG_ON(count > smd_stream_write_avail(ch));
277 ch->send->head = (ch->send->head + count) & ch->fifo_mask;
278 ch->send->fHEAD = 1;
279}
280
281static void ch_set_state(struct smd_channel *ch, unsigned n)
282{
283 if (n == SMD_SS_OPENED) {
284 ch->send->fDSR = 1;
285 ch->send->fCTS = 1;
286 ch->send->fCD = 1;
287 } else {
288 ch->send->fDSR = 0;
289 ch->send->fCTS = 0;
290 ch->send->fCD = 0;
291 }
292 ch->send->state = n;
293 ch->send->fSTATE = 1;
294 ch->notify_other_cpu();
295}
296
297static void do_smd_probe(void)
298{
299 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
300 if (shared->heap_info.free_offset != last_heap_free) {
301 last_heap_free = shared->heap_info.free_offset;
302 schedule_work(&probe_work);
303 }
304}
305
306static void smd_state_change(struct smd_channel *ch,
307 unsigned last, unsigned next)
308{
309 ch->last_state = next;
310
311 pr_debug("ch %d %d -> %d\n", ch->n, last, next);
312
313 switch (next) {
314 case SMD_SS_OPENING:
315 ch->recv->tail = 0;
316 case SMD_SS_OPENED:
317 if (ch->send->state != SMD_SS_OPENED)
318 ch_set_state(ch, SMD_SS_OPENED);
319 ch->notify(ch->priv, SMD_EVENT_OPEN);
320 break;
321 case SMD_SS_FLUSHING:
322 case SMD_SS_RESET:
323 /* we should force them to close? */
324 default:
325 ch->notify(ch->priv, SMD_EVENT_CLOSE);
326 }
327}
328
329static void handle_smd_irq(struct list_head *list, void (*notify)(void))
330{
331 unsigned long flags;
332 struct smd_channel *ch;
333 int do_notify = 0;
334 unsigned ch_flags;
335 unsigned tmp;
336
337 spin_lock_irqsave(&smd_lock, flags);
338 list_for_each_entry(ch, list, ch_list) {
339 ch_flags = 0;
340 if (ch_is_open(ch)) {
341 if (ch->recv->fHEAD) {
342 ch->recv->fHEAD = 0;
343 ch_flags |= 1;
344 do_notify |= 1;
345 }
346 if (ch->recv->fTAIL) {
347 ch->recv->fTAIL = 0;
348 ch_flags |= 2;
349 do_notify |= 1;
350 }
351 if (ch->recv->fSTATE) {
352 ch->recv->fSTATE = 0;
353 ch_flags |= 4;
354 do_notify |= 1;
355 }
356 }
357 tmp = ch->recv->state;
358 if (tmp != ch->last_state)
359 smd_state_change(ch, ch->last_state, tmp);
360 if (ch_flags) {
361 ch->update_state(ch);
362 ch->notify(ch->priv, SMD_EVENT_DATA);
363 }
364 }
365 if (do_notify)
366 notify();
367 spin_unlock_irqrestore(&smd_lock, flags);
368 do_smd_probe();
369}
370
371static irqreturn_t smd_modem_irq_handler(int irq, void *data)
372{
373 handle_smd_irq(&smd_ch_list_modem, notify_modem_smd);
374 return IRQ_HANDLED;
375}
376
377#if defined(CONFIG_QDSP6)
378static irqreturn_t smd_dsp_irq_handler(int irq, void *data)
379{
380 handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
381 return IRQ_HANDLED;
382}
383#endif
384
385static void smd_fake_irq_handler(unsigned long arg)
386{
387 handle_smd_irq(&smd_ch_list_modem, notify_modem_smd);
388 handle_smd_irq(&smd_ch_list_dsp, notify_dsp_smd);
389}
390
391static DECLARE_TASKLET(smd_fake_irq_tasklet, smd_fake_irq_handler, 0);
392
393static inline int smd_need_int(struct smd_channel *ch)
394{
395 if (ch_is_open(ch)) {
396 if (ch->recv->fHEAD || ch->recv->fTAIL || ch->recv->fSTATE)
397 return 1;
398 if (ch->recv->state != ch->last_state)
399 return 1;
400 }
401 return 0;
402}
403
404void smd_sleep_exit(void)
405{
406 unsigned long flags;
407 struct smd_channel *ch;
408 int need_int = 0;
409
410 spin_lock_irqsave(&smd_lock, flags);
411 list_for_each_entry(ch, &smd_ch_list_modem, ch_list) {
412 if (smd_need_int(ch)) {
413 need_int = 1;
414 break;
415 }
416 }
417 list_for_each_entry(ch, &smd_ch_list_dsp, ch_list) {
418 if (smd_need_int(ch)) {
419 need_int = 1;
420 break;
421 }
422 }
423 spin_unlock_irqrestore(&smd_lock, flags);
424 do_smd_probe();
425
426 if (need_int) {
427 if (msm_smd_debug_mask & MSM_SMD_DEBUG)
428 pr_info("smd_sleep_exit need interrupt\n");
429 tasklet_schedule(&smd_fake_irq_tasklet);
430 }
431}
432
433
434void smd_kick(smd_channel_t *ch)
435{
436 unsigned long flags;
437 unsigned tmp;
438
439 spin_lock_irqsave(&smd_lock, flags);
440 ch->update_state(ch);
441 tmp = ch->recv->state;
442 if (tmp != ch->last_state) {
443 ch->last_state = tmp;
444 if (tmp == SMD_SS_OPENED)
445 ch->notify(ch->priv, SMD_EVENT_OPEN);
446 else
447 ch->notify(ch->priv, SMD_EVENT_CLOSE);
448 }
449 ch->notify(ch->priv, SMD_EVENT_DATA);
450 ch->notify_other_cpu();
451 spin_unlock_irqrestore(&smd_lock, flags);
452}
453
454static int smd_is_packet(int chn, unsigned type)
455{
456 type &= SMD_KIND_MASK;
457 if (type == SMD_KIND_PACKET)
458 return 1;
459 if (type == SMD_KIND_STREAM)
460 return 0;
461
462 /* older AMSS reports SMD_KIND_UNKNOWN always */
463 if ((chn > 4) || (chn == 1))
464 return 1;
465 else
466 return 0;
467}
468
469static int smd_stream_write(smd_channel_t *ch, const void *_data, int len)
470{
471 void *ptr;
472 const unsigned char *buf = _data;
473 unsigned xfer;
474 int orig_len = len;
475
476 if (len < 0)
477 return -EINVAL;
478
479 while ((xfer = ch_write_buffer(ch, &ptr)) != 0) {
480 if (!ch_is_open(ch))
481 break;
482 if (xfer > len)
483 xfer = len;
484 memcpy(ptr, buf, xfer);
485 ch_write_done(ch, xfer);
486 len -= xfer;
487 buf += xfer;
488 if (len == 0)
489 break;
490 }
491
492 ch->notify_other_cpu();
493
494 return orig_len - len;
495}
496
497static int smd_packet_write(smd_channel_t *ch, const void *_data, int len)
498{
499 unsigned hdr[5];
500
501 if (len < 0)
502 return -EINVAL;
503
504 if (smd_stream_write_avail(ch) < (len + SMD_HEADER_SIZE))
505 return -ENOMEM;
506
507 hdr[0] = len;
508 hdr[1] = hdr[2] = hdr[3] = hdr[4] = 0;
509
510 smd_stream_write(ch, hdr, sizeof(hdr));
511 smd_stream_write(ch, _data, len);
512
513 return len;
514}
515
516static int smd_stream_read(smd_channel_t *ch, void *data, int len)
517{
518 int r;
519
520 if (len < 0)
521 return -EINVAL;
522
523 r = ch_read(ch, data, len);
524 if (r > 0)
525 ch->notify_other_cpu();
526
527 return r;
528}
529
530static int smd_packet_read(smd_channel_t *ch, void *data, int len)
531{
532 unsigned long flags;
533 int r;
534
535 if (len < 0)
536 return -EINVAL;
537
538 if (len > ch->current_packet)
539 len = ch->current_packet;
540
541 r = ch_read(ch, data, len);
542 if (r > 0)
543 ch->notify_other_cpu();
544
545 spin_lock_irqsave(&smd_lock, flags);
546 ch->current_packet -= r;
547 update_packet_state(ch);
548 spin_unlock_irqrestore(&smd_lock, flags);
549
550 return r;
551}
552
553static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
554{
555 struct smd_channel *ch;
556
557 ch = kzalloc(sizeof(struct smd_channel), GFP_KERNEL);
558 if (ch == 0) {
559 pr_err("smd_alloc_channel() out of memory\n");
560 return -1;
561 }
562 ch->n = cid;
563
564 if (_smd_alloc_channel(ch)) {
565 kfree(ch);
566 return -1;
567 }
568
569 ch->fifo_mask = ch->fifo_size - 1;
570 ch->type = type;
571
572 if ((type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
573 ch->notify_other_cpu = notify_modem_smd;
574 else
575 ch->notify_other_cpu = notify_dsp_smd;
576
577 if (smd_is_packet(cid, type)) {
578 ch->read = smd_packet_read;
579 ch->write = smd_packet_write;
580 ch->read_avail = smd_packet_read_avail;
581 ch->write_avail = smd_packet_write_avail;
582 ch->update_state = update_packet_state;
583 } else {
584 ch->read = smd_stream_read;
585 ch->write = smd_stream_write;
586 ch->read_avail = smd_stream_read_avail;
587 ch->write_avail = smd_stream_write_avail;
588 ch->update_state = update_stream_state;
589 }
590
591 if ((type & 0xff) == 0)
592 memcpy(ch->name, "SMD_", 4);
593 else
594 memcpy(ch->name, "DSP_", 4);
595 memcpy(ch->name + 4, name, 20);
596 ch->name[23] = 0;
597 ch->pdev.name = ch->name;
598 ch->pdev.id = -1;
599
600 pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
601 ch->n, ch->fifo_size, ch->name);
602
603 mutex_lock(&smd_creation_mutex);
604 list_add(&ch->ch_list, &smd_ch_closed_list);
605 mutex_unlock(&smd_creation_mutex);
606
607 platform_device_register(&ch->pdev);
608 return 0;
609}
610
611static void smd_channel_probe_worker(struct work_struct *work)
612{
613 struct smd_alloc_elm *shared;
614 unsigned ctype;
615 unsigned type;
616 unsigned n;
617
618 shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
619 if (!shared) {
620 pr_err("cannot find allocation table\n");
621 return;
622 }
623 for (n = 0; n < 64; n++) {
624 if (smd_ch_allocated[n])
625 continue;
626 if (!shared[n].ref_count)
627 continue;
628 if (!shared[n].name[0])
629 continue;
630 ctype = shared[n].ctype;
631 type = ctype & SMD_TYPE_MASK;
632
633 /* DAL channels are stream but neither the modem,
634 * nor the DSP correctly indicate this. Fixup manually.
635 */
636 if (!memcmp(shared[n].name, "DAL", 3))
637 ctype = (ctype & (~SMD_KIND_MASK)) | SMD_KIND_STREAM;
638
639 type = shared[n].ctype & SMD_TYPE_MASK;
640 if ((type == SMD_TYPE_APPS_MODEM) ||
641 (type == SMD_TYPE_APPS_DSP))
642 if (!smd_alloc_channel(shared[n].name, shared[n].cid, ctype))
643 smd_ch_allocated[n] = 1;
644 }
645}
646
647static void do_nothing_notify(void *priv, unsigned flags)
648{
649}
650
651struct smd_channel *smd_get_channel(const char *name)
652{
653 struct smd_channel *ch;
654
655 mutex_lock(&smd_creation_mutex);
656 list_for_each_entry(ch, &smd_ch_closed_list, ch_list) {
657 if (!strcmp(name, ch->name)) {
658 list_del(&ch->ch_list);
659 mutex_unlock(&smd_creation_mutex);
660 return ch;
661 }
662 }
663 mutex_unlock(&smd_creation_mutex);
664
665 return NULL;
666}
667
668int smd_open(const char *name, smd_channel_t **_ch,
669 void *priv, void (*notify)(void *, unsigned))
670{
671 struct smd_channel *ch;
672 unsigned long flags;
673
674 if (smd_initialized == 0) {
675 pr_info("smd_open() before smd_init()\n");
676 return -ENODEV;
677 }
678
679 ch = smd_get_channel(name);
680 if (!ch)
681 return -ENODEV;
682
683 if (notify == 0)
684 notify = do_nothing_notify;
685
686 ch->notify = notify;
687 ch->current_packet = 0;
688 ch->last_state = SMD_SS_CLOSED;
689 ch->priv = priv;
690
691 *_ch = ch;
692
693 spin_lock_irqsave(&smd_lock, flags);
694
695 if ((ch->type & SMD_TYPE_MASK) == SMD_TYPE_APPS_MODEM)
696 list_add(&ch->ch_list, &smd_ch_list_modem);
697 else
698 list_add(&ch->ch_list, &smd_ch_list_dsp);
699
700 /* If the remote side is CLOSING, we need to get it to
701 * move to OPENING (which we'll do by moving from CLOSED to
702 * OPENING) and then get it to move from OPENING to
703 * OPENED (by doing the same state change ourselves).
704 *
705 * Otherwise, it should be OPENING and we can move directly
706 * to OPENED so that it will follow.
707 */
708 if (ch->recv->state == SMD_SS_CLOSING) {
709 ch->send->head = 0;
710 ch_set_state(ch, SMD_SS_OPENING);
711 } else {
712 ch_set_state(ch, SMD_SS_OPENED);
713 }
714 spin_unlock_irqrestore(&smd_lock, flags);
715 smd_kick(ch);
716
717 return 0;
718}
719
720int smd_close(smd_channel_t *ch)
721{
722 unsigned long flags;
723
724 if (ch == 0)
725 return -1;
726
727 spin_lock_irqsave(&smd_lock, flags);
728 ch->notify = do_nothing_notify;
729 list_del(&ch->ch_list);
730 ch_set_state(ch, SMD_SS_CLOSED);
731 spin_unlock_irqrestore(&smd_lock, flags);
732
733 mutex_lock(&smd_creation_mutex);
734 list_add(&ch->ch_list, &smd_ch_closed_list);
735 mutex_unlock(&smd_creation_mutex);
736
737 return 0;
738}
739
740int smd_read(smd_channel_t *ch, void *data, int len)
741{
742 return ch->read(ch, data, len);
743}
744
745int smd_write(smd_channel_t *ch, const void *data, int len)
746{
747 return ch->write(ch, data, len);
748}
749
750int smd_write_atomic(smd_channel_t *ch, const void *data, int len)
751{
752 unsigned long flags;
753 int res;
754 spin_lock_irqsave(&smd_lock, flags);
755 res = ch->write(ch, data, len);
756 spin_unlock_irqrestore(&smd_lock, flags);
757 return res;
758}
759
760int smd_read_avail(smd_channel_t *ch)
761{
762 return ch->read_avail(ch);
763}
764
765int smd_write_avail(smd_channel_t *ch)
766{
767 return ch->write_avail(ch);
768}
769
770int smd_wait_until_readable(smd_channel_t *ch, int bytes)
771{
772 return -1;
773}
774
775int smd_wait_until_writable(smd_channel_t *ch, int bytes)
776{
777 return -1;
778}
779
780int smd_cur_packet_size(smd_channel_t *ch)
781{
782 return ch->current_packet;
783}
784
785
786/* ------------------------------------------------------------------------- */
787
788void *smem_alloc(unsigned id, unsigned size)
789{
790 return smem_find(id, size);
791}
792
793void __iomem *smem_item(unsigned id, unsigned *size)
794{
795 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
796 struct smem_heap_entry *toc = shared->heap_toc;
797
798 if (id >= SMEM_NUM_ITEMS)
799 return NULL;
800
801 if (toc[id].allocated) {
802 *size = toc[id].size;
803 return (MSM_SHARED_RAM_BASE + toc[id].offset);
804 } else {
805 *size = 0;
806 }
807
808 return NULL;
809}
810
811void *smem_find(unsigned id, unsigned size_in)
812{
813 unsigned size;
814 void *ptr;
815
816 ptr = smem_item(id, &size);
817 if (!ptr)
818 return 0;
819
820 size_in = ALIGN(size_in, 8);
821 if (size_in != size) {
822 pr_err("smem_find(%d, %d): wrong size %d\n",
823 id, size_in, size);
824 return 0;
825 }
826
827 return ptr;
828}
829
830static irqreturn_t smsm_irq_handler(int irq, void *data)
831{
832 unsigned long flags;
833 unsigned apps, modm;
834
835 spin_lock_irqsave(&smem_lock, flags);
836
837 apps = raw_smsm_get_state(SMSM_STATE_APPS);
838 modm = raw_smsm_get_state(SMSM_STATE_MODEM);
839
840 if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
841 pr_info("<SM %08x %08x>\n", apps, modm);
842 if (modm & SMSM_RESET)
843 handle_modem_crash();
844
845 do_smd_probe();
846
847 spin_unlock_irqrestore(&smem_lock, flags);
848 return IRQ_HANDLED;
849}
850
851int smsm_change_state(enum smsm_state_item item,
852 uint32_t clear_mask, uint32_t set_mask)
853{
854 void __iomem *addr = smd_info.state + item * 4;
855 unsigned long flags;
856 unsigned state;
857
858 if (!smd_info.ready)
859 return -EIO;
860
861 spin_lock_irqsave(&smem_lock, flags);
862
863 if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET)
864 handle_modem_crash();
865
866 state = (readl(addr) & ~clear_mask) | set_mask;
867 writel(state, addr);
868
869 if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
870 pr_info("smsm_change_state %d %x\n", item, state);
871 notify_other_smsm();
872
873 spin_unlock_irqrestore(&smem_lock, flags);
874
875 return 0;
876}
877
878uint32_t smsm_get_state(enum smsm_state_item item)
879{
880 unsigned long flags;
881 uint32_t rv;
882
883 spin_lock_irqsave(&smem_lock, flags);
884
885 rv = readl(smd_info.state + item * 4);
886
887 if (item == SMSM_STATE_MODEM && (rv & SMSM_RESET))
888 handle_modem_crash();
889
890 spin_unlock_irqrestore(&smem_lock, flags);
891
892 return rv;
893}
894
895#ifdef CONFIG_ARCH_MSM_SCORPION
896
897int smsm_set_sleep_duration(uint32_t delay)
898{
899 struct msm_dem_slave_data *ptr;
900
901 ptr = smem_find(SMEM_APPS_DEM_SLAVE_DATA, sizeof(*ptr));
902 if (ptr == NULL) {
903 pr_err("smsm_set_sleep_duration <SM NO APPS_DEM_SLAVE_DATA>\n");
904 return -EIO;
905 }
906 if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
907 pr_info("smsm_set_sleep_duration %d -> %d\n",
908 ptr->sleep_time, delay);
909 ptr->sleep_time = delay;
910 return 0;
911}
912
913#else
914
915int smsm_set_sleep_duration(uint32_t delay)
916{
917 uint32_t *ptr;
918
919 ptr = smem_find(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
920 if (ptr == NULL) {
921 pr_err("smsm_set_sleep_duration <SM NO SLEEP_DELAY>\n");
922 return -EIO;
923 }
924 if (msm_smd_debug_mask & MSM_SMSM_DEBUG)
925 pr_info("smsm_set_sleep_duration %d -> %d\n",
926 *ptr, delay);
927 *ptr = delay;
928 return 0;
929}
930
931#endif
932
933int smd_core_init(void)
934{
935 int r;
936
937 /* wait for essential items to be initialized */
938 for (;;) {
939 unsigned size;
940 void __iomem *state;
941 state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
942 if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
943 smd_info.state = state;
944 break;
945 }
946 }
947
948 smd_info.ready = 1;
949
950 r = request_irq(INT_A9_M2A_0, smd_modem_irq_handler,
951 IRQF_TRIGGER_RISING, "smd_dev", 0);
952 if (r < 0)
953 return r;
954 r = enable_irq_wake(INT_A9_M2A_0);
955 if (r < 0)
956 pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_0\n");
957
958 r = request_irq(INT_A9_M2A_5, smsm_irq_handler,
959 IRQF_TRIGGER_RISING, "smsm_dev", 0);
960 if (r < 0) {
961 free_irq(INT_A9_M2A_0, 0);
962 return r;
963 }
964 r = enable_irq_wake(INT_A9_M2A_5);
965 if (r < 0)
966 pr_err("smd_core_init: enable_irq_wake failed for A9_M2A_5\n");
967
968#if defined(CONFIG_QDSP6)
969 r = request_irq(INT_ADSP_A11, smd_dsp_irq_handler,
970 IRQF_TRIGGER_RISING, "smd_dsp", 0);
971 if (r < 0) {
972 free_irq(INT_A9_M2A_0, 0);
973 free_irq(INT_A9_M2A_5, 0);
974 return r;
975 }
976#endif
977
978 /* check for any SMD channels that may already exist */
979 do_smd_probe();
980
981 /* indicate that we're up and running */
982 smsm_change_state(SMSM_STATE_APPS,
983 ~0, SMSM_INIT | SMSM_SMDINIT | SMSM_RPCINIT | SMSM_RUN);
984#ifdef CONFIG_ARCH_MSM_SCORPION
985 smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
986#endif
987
988 return 0;
989}
990
991static int msm_smd_probe(struct platform_device *pdev)
992{
993 /*
994 * If we haven't waited for the ARM9 to boot up till now,
995 * then we need to wait here. Otherwise this should just
996 * return immediately.
997 */
998 proc_comm_boot_wait();
999
1000 INIT_WORK(&probe_work, smd_channel_probe_worker);
1001
1002 if (smd_core_init()) {
1003 pr_err("smd_core_init() failed\n");
1004 return -1;
1005 }
1006
1007 do_smd_probe();
1008
1009 msm_check_for_modem_crash = check_for_modem_crash;
1010
1011 msm_init_last_radio_log(THIS_MODULE);
1012
1013 smd_initialized = 1;
1014
1015 return 0;
1016}
1017
1018static struct platform_driver msm_smd_driver = {
1019 .probe = msm_smd_probe,
1020 .driver = {
1021 .name = MODULE_NAME,
1022 },
1023};
1024
1025static int __init msm_smd_init(void)
1026{
1027 return platform_driver_register(&msm_smd_driver);
1028}
1029
1030module_init(msm_smd_init);
1031
1032MODULE_DESCRIPTION("MSM Shared Memory Core");
1033MODULE_AUTHOR("Brian Swetland <swetland@google.com>");
1034MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
deleted file mode 100644
index 8056b3e5590f..000000000000
--- a/arch/arm/mach-msm/smd_debug.c
+++ /dev/null
@@ -1,311 +0,0 @@
1/* arch/arm/mach-msm/smd_debug.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/debugfs.h>
18#include <linux/list.h>
19
20#include <mach/msm_iomap.h>
21
22#include "smd_private.h"
23
24#if defined(CONFIG_DEBUG_FS)
25
26static char *chstate(unsigned n)
27{
28 switch (n) {
29 case SMD_SS_CLOSED:
30 return "CLOSED";
31 case SMD_SS_OPENING:
32 return "OPENING";
33 case SMD_SS_OPENED:
34 return "OPENED";
35 case SMD_SS_FLUSHING:
36 return "FLUSHING";
37 case SMD_SS_CLOSING:
38 return "CLOSING";
39 case SMD_SS_RESET:
40 return "RESET";
41 case SMD_SS_RESET_OPENING:
42 return "ROPENING";
43 default:
44 return "UNKNOWN";
45 }
46}
47
48
49static int dump_ch(char *buf, int max, struct smd_channel *ch)
50{
51 volatile struct smd_half_channel *s = ch->send;
52 volatile struct smd_half_channel *r = ch->recv;
53
54 return scnprintf(
55 buf, max,
56 "ch%02d:"
57 " %8s(%05d/%05d) %c%c%c%c%c%c%c <->"
58 " %8s(%05d/%05d) %c%c%c%c%c%c%c '%s'\n", ch->n,
59 chstate(s->state), s->tail, s->head,
60 s->fDSR ? 'D' : 'd',
61 s->fCTS ? 'C' : 'c',
62 s->fCD ? 'C' : 'c',
63 s->fRI ? 'I' : 'i',
64 s->fHEAD ? 'W' : 'w',
65 s->fTAIL ? 'R' : 'r',
66 s->fSTATE ? 'S' : 's',
67 chstate(r->state), r->tail, r->head,
68 r->fDSR ? 'D' : 'd',
69 r->fCTS ? 'R' : 'r',
70 r->fCD ? 'C' : 'c',
71 r->fRI ? 'I' : 'i',
72 r->fHEAD ? 'W' : 'w',
73 r->fTAIL ? 'R' : 'r',
74 r->fSTATE ? 'S' : 's',
75 ch->name
76 );
77}
78
79static int debug_read_stat(char *buf, int max)
80{
81 char *msg;
82 int i = 0;
83
84 msg = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
85
86 if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET)
87 i += scnprintf(buf + i, max - i,
88 "smsm: ARM9 HAS CRASHED\n");
89
90 i += scnprintf(buf + i, max - i, "smsm: a9: %08x a11: %08x\n",
91 raw_smsm_get_state(SMSM_STATE_MODEM),
92 raw_smsm_get_state(SMSM_STATE_APPS));
93#ifdef CONFIG_ARCH_MSM_SCORPION
94 i += scnprintf(buf + i, max - i, "smsm dem: apps: %08x modem: %08x "
95 "qdsp6: %08x power: %08x time: %08x\n",
96 raw_smsm_get_state(SMSM_STATE_APPS_DEM),
97 raw_smsm_get_state(SMSM_STATE_MODEM_DEM),
98 raw_smsm_get_state(SMSM_STATE_QDSP6_DEM),
99 raw_smsm_get_state(SMSM_STATE_POWER_MASTER_DEM),
100 raw_smsm_get_state(SMSM_STATE_TIME_MASTER_DEM));
101#endif
102 if (msg) {
103 msg[SZ_DIAG_ERR_MSG - 1] = 0;
104 i += scnprintf(buf + i, max - i, "diag: '%s'\n", msg);
105 }
106 return i;
107}
108
109static int debug_read_mem(char *buf, int max)
110{
111 unsigned n;
112 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
113 struct smem_heap_entry *toc = shared->heap_toc;
114 int i = 0;
115
116 i += scnprintf(buf + i, max - i,
117 "heap: init=%d free=%d remain=%d\n",
118 shared->heap_info.initialized,
119 shared->heap_info.free_offset,
120 shared->heap_info.heap_remaining);
121
122 for (n = 0; n < SMEM_NUM_ITEMS; n++) {
123 if (toc[n].allocated == 0)
124 continue;
125 i += scnprintf(buf + i, max - i,
126 "%04d: offset %08x size %08x\n",
127 n, toc[n].offset, toc[n].size);
128 }
129 return i;
130}
131
132static int debug_read_ch(char *buf, int max)
133{
134 struct smd_channel *ch;
135 unsigned long flags;
136 int i = 0;
137
138 spin_lock_irqsave(&smd_lock, flags);
139 list_for_each_entry(ch, &smd_ch_list_dsp, ch_list)
140 i += dump_ch(buf + i, max - i, ch);
141 list_for_each_entry(ch, &smd_ch_list_modem, ch_list)
142 i += dump_ch(buf + i, max - i, ch);
143 list_for_each_entry(ch, &smd_ch_closed_list, ch_list)
144 i += dump_ch(buf + i, max - i, ch);
145 spin_unlock_irqrestore(&smd_lock, flags);
146
147 return i;
148}
149
150static int debug_read_version(char *buf, int max)
151{
152 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
153 unsigned version = shared->version[VERSION_MODEM];
154 return sprintf(buf, "%d.%d\n", version >> 16, version & 0xffff);
155}
156
157static int debug_read_build_id(char *buf, int max)
158{
159 unsigned size;
160 void *data;
161
162 data = smem_item(SMEM_HW_SW_BUILD_ID, &size);
163 if (!data)
164 return 0;
165
166 if (size >= max)
167 size = max;
168 memcpy(buf, data, size);
169
170 return size;
171}
172
173static int debug_read_alloc_tbl(char *buf, int max)
174{
175 struct smd_alloc_elm *shared;
176 int n, i = 0;
177
178 shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
179
180 for (n = 0; n < 64; n++) {
181 if (shared[n].ref_count == 0)
182 continue;
183 i += scnprintf(buf + i, max - i,
184 "%03d: %-20s cid=%02d type=%03d "
185 "kind=%02d ref_count=%d\n",
186 n, shared[n].name, shared[n].cid,
187 shared[n].ctype & 0xff,
188 (shared[n].ctype >> 8) & 0xf,
189 shared[n].ref_count);
190 }
191
192 return i;
193}
194
195#define DEBUG_BUFMAX 4096
196static char debug_buffer[DEBUG_BUFMAX];
197
198static ssize_t debug_read(struct file *file, char __user *buf,
199 size_t count, loff_t *ppos)
200{
201 int (*fill)(char *buf, int max) = file->private_data;
202 int bsize = fill(debug_buffer, DEBUG_BUFMAX);
203 return simple_read_from_buffer(buf, count, ppos, debug_buffer, bsize);
204}
205
206static const struct file_operations debug_ops = {
207 .read = debug_read,
208 .open = simple_open,
209 .llseek = default_llseek,
210};
211
212static void debug_create(const char *name, umode_t mode,
213 struct dentry *dent,
214 int (*fill)(char *buf, int max))
215{
216 debugfs_create_file(name, mode, dent, fill, &debug_ops);
217}
218
219int __init smd_debugfs_init(void)
220{
221 struct dentry *dent;
222
223 dent = debugfs_create_dir("smd", 0);
224 if (IS_ERR(dent))
225 return 1;
226
227 debug_create("ch", 0444, dent, debug_read_ch);
228 debug_create("stat", 0444, dent, debug_read_stat);
229 debug_create("mem", 0444, dent, debug_read_mem);
230 debug_create("version", 0444, dent, debug_read_version);
231 debug_create("tbl", 0444, dent, debug_read_alloc_tbl);
232 debug_create("build", 0444, dent, debug_read_build_id);
233
234 return 0;
235}
236
237#endif
238
239
240#define MAX_NUM_SLEEP_CLIENTS 64
241#define MAX_SLEEP_NAME_LEN 8
242
243#define NUM_GPIO_INT_REGISTERS 6
244#define GPIO_SMEM_NUM_GROUPS 2
245#define GPIO_SMEM_MAX_PC_INTERRUPTS 8
246
247struct tramp_gpio_save {
248 unsigned int enable;
249 unsigned int detect;
250 unsigned int polarity;
251};
252
253struct tramp_gpio_smem {
254 uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
255 uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
256 uint32_t enabled[NUM_GPIO_INT_REGISTERS];
257 uint32_t detection[NUM_GPIO_INT_REGISTERS];
258 uint32_t polarity[NUM_GPIO_INT_REGISTERS];
259};
260
261
262void smsm_print_sleep_info(void)
263{
264 unsigned long flags;
265 uint32_t *ptr;
266#ifndef CONFIG_ARCH_MSM_SCORPION
267 struct tramp_gpio_smem *gpio;
268 struct smsm_interrupt_info *int_info;
269#endif
270
271
272 spin_lock_irqsave(&smem_lock, flags);
273
274 ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
275 if (ptr)
276 pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr);
277
278 ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr));
279 if (ptr)
280 pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr);
281
282 ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr));
283 if (ptr)
284 pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr);
285
286#ifndef CONFIG_ARCH_MSM_SCORPION
287 int_info = smem_alloc(SMEM_SMSM_INT_INFO, sizeof(*int_info));
288 if (int_info)
289 pr_info("SMEM_SMSM_INT_INFO %x %x %x\n",
290 int_info->interrupt_mask,
291 int_info->pending_interrupts,
292 int_info->wakeup_reason);
293
294 gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*gpio));
295 if (gpio) {
296 int i;
297 for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++)
298 pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n",
299 i, gpio->enabled[i], gpio->detection[i],
300 gpio->polarity[i]);
301
302 for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
303 pr_info("SMEM_GPIO_INT: %d: f %d: %d %d...\n",
304 i, gpio->num_fired[i], gpio->fired[i][0],
305 gpio->fired[i][1]);
306 }
307#else
308#endif
309 spin_unlock_irqrestore(&smem_lock, flags);
310}
311
diff --git a/arch/arm/mach-msm/smd_private.h b/arch/arm/mach-msm/smd_private.h
deleted file mode 100644
index 727bfe68aa9b..000000000000
--- a/arch/arm/mach-msm/smd_private.h
+++ /dev/null
@@ -1,403 +0,0 @@
1/* arch/arm/mach-msm/smd_private.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2007 QUALCOMM Incorporated
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
17#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
18
19#include <linux/platform_device.h>
20#include <linux/spinlock.h>
21#include <linux/list.h>
22#include <linux/io.h>
23
24#include <mach/msm_iomap.h>
25
26struct smem_heap_info {
27 unsigned initialized;
28 unsigned free_offset;
29 unsigned heap_remaining;
30 unsigned reserved;
31};
32
33struct smem_heap_entry {
34 unsigned allocated;
35 unsigned offset;
36 unsigned size;
37 unsigned reserved;
38};
39
40struct smem_proc_comm {
41 unsigned command;
42 unsigned status;
43 unsigned data1;
44 unsigned data2;
45};
46
47#define PC_APPS 0
48#define PC_MODEM 1
49
50#define VERSION_SMD 0
51#define VERSION_QDSP6 4
52#define VERSION_APPS_SBL 6
53#define VERSION_MODEM_SBL 7
54#define VERSION_APPS 8
55#define VERSION_MODEM 9
56
57struct smem_shared {
58 struct smem_proc_comm proc_comm[4];
59 unsigned version[32];
60 struct smem_heap_info heap_info;
61 struct smem_heap_entry heap_toc[512];
62};
63
64#define SMSM_V1_SIZE (sizeof(unsigned) * 8)
65#define SMSM_V2_SIZE (sizeof(unsigned) * 4)
66
67#ifdef CONFIG_MSM_SMD_PKG3
68struct smsm_interrupt_info {
69 uint32_t interrupt_mask;
70 uint32_t pending_interrupts;
71 uint32_t wakeup_reason;
72};
73#else
74#define DEM_MAX_PORT_NAME_LEN (20)
75struct msm_dem_slave_data {
76 uint32_t sleep_time;
77 uint32_t interrupt_mask;
78 uint32_t resources_used;
79 uint32_t reserved1;
80
81 uint32_t wakeup_reason;
82 uint32_t pending_interrupts;
83 uint32_t rpc_prog;
84 uint32_t rpc_proc;
85 char smd_port_name[DEM_MAX_PORT_NAME_LEN];
86 uint32_t reserved2;
87};
88#endif
89
90#define SZ_DIAG_ERR_MSG 0xC8
91#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
92#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
93#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
94#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
95
96#define SMSM_INIT 0x00000001
97#define SMSM_SMDINIT 0x00000008
98#define SMSM_RPCINIT 0x00000020
99#define SMSM_RESET 0x00000040
100#define SMSM_RSA 0x00000080
101#define SMSM_RUN 0x00000100
102#define SMSM_PWRC 0x00000200
103#define SMSM_TIMEWAIT 0x00000400
104#define SMSM_TIMEINIT 0x00000800
105#define SMSM_PWRC_EARLY_EXIT 0x00001000
106#define SMSM_WFPI 0x00002000
107#define SMSM_SLEEP 0x00004000
108#define SMSM_SLEEPEXIT 0x00008000
109#define SMSM_APPS_REBOOT 0x00020000
110#define SMSM_SYSTEM_POWER_DOWN 0x00040000
111#define SMSM_SYSTEM_REBOOT 0x00080000
112#define SMSM_SYSTEM_DOWNLOAD 0x00100000
113#define SMSM_PWRC_SUSPEND 0x00200000
114#define SMSM_APPS_SHUTDOWN 0x00400000
115#define SMSM_SMD_LOOPBACK 0x00800000
116#define SMSM_RUN_QUIET 0x01000000
117#define SMSM_MODEM_WAIT 0x02000000
118#define SMSM_MODEM_BREAK 0x04000000
119#define SMSM_MODEM_CONTINUE 0x08000000
120#define SMSM_UNKNOWN 0x80000000
121
122#define SMSM_WKUP_REASON_RPC 0x00000001
123#define SMSM_WKUP_REASON_INT 0x00000002
124#define SMSM_WKUP_REASON_GPIO 0x00000004
125#define SMSM_WKUP_REASON_TIMER 0x00000008
126#define SMSM_WKUP_REASON_ALARM 0x00000010
127#define SMSM_WKUP_REASON_RESET 0x00000020
128
129#ifdef CONFIG_ARCH_MSM7X00A
130enum smsm_state_item {
131 SMSM_STATE_APPS = 1,
132 SMSM_STATE_MODEM = 3,
133 SMSM_STATE_COUNT,
134};
135#else
136enum smsm_state_item {
137 SMSM_STATE_APPS,
138 SMSM_STATE_MODEM,
139 SMSM_STATE_HEXAGON,
140 SMSM_STATE_APPS_DEM,
141 SMSM_STATE_MODEM_DEM,
142 SMSM_STATE_QDSP6_DEM,
143 SMSM_STATE_POWER_MASTER_DEM,
144 SMSM_STATE_TIME_MASTER_DEM,
145 SMSM_STATE_COUNT,
146};
147#endif
148
149void *smem_alloc(unsigned id, unsigned size);
150int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
151uint32_t smsm_get_state(enum smsm_state_item item);
152int smsm_set_sleep_duration(uint32_t delay);
153void smsm_print_sleep_info(void);
154
155#define SMEM_NUM_SMD_CHANNELS 64
156
157typedef enum {
158 /* fixed items */
159 SMEM_PROC_COMM = 0,
160 SMEM_HEAP_INFO,
161 SMEM_ALLOCATION_TABLE,
162 SMEM_VERSION_INFO,
163 SMEM_HW_RESET_DETECT,
164 SMEM_AARM_WARM_BOOT,
165 SMEM_DIAG_ERR_MESSAGE,
166 SMEM_SPINLOCK_ARRAY,
167 SMEM_MEMORY_BARRIER_LOCATION,
168
169 /* dynamic items */
170 SMEM_AARM_PARTITION_TABLE,
171 SMEM_AARM_BAD_BLOCK_TABLE,
172 SMEM_RESERVE_BAD_BLOCKS,
173 SMEM_WM_UUID,
174 SMEM_CHANNEL_ALLOC_TBL,
175 SMEM_SMD_BASE_ID,
176 SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
177 SMEM_SMEM_LOG_EVENTS,
178 SMEM_SMEM_STATIC_LOG_IDX,
179 SMEM_SMEM_STATIC_LOG_EVENTS,
180 SMEM_SMEM_SLOW_CLOCK_SYNC,
181 SMEM_SMEM_SLOW_CLOCK_VALUE,
182 SMEM_BIO_LED_BUF,
183 SMEM_SMSM_SHARED_STATE,
184 SMEM_SMSM_INT_INFO,
185 SMEM_SMSM_SLEEP_DELAY,
186 SMEM_SMSM_LIMIT_SLEEP,
187 SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
188 SMEM_KEYPAD_KEYS_PRESSED,
189 SMEM_KEYPAD_STATE_UPDATED,
190 SMEM_KEYPAD_STATE_IDX,
191 SMEM_GPIO_INT,
192 SMEM_MDDI_LCD_IDX,
193 SMEM_MDDI_HOST_DRIVER_STATE,
194 SMEM_MDDI_LCD_DISP_STATE,
195 SMEM_LCD_CUR_PANEL,
196 SMEM_MARM_BOOT_SEGMENT_INFO,
197 SMEM_AARM_BOOT_SEGMENT_INFO,
198 SMEM_SLEEP_STATIC,
199 SMEM_SCORPION_FREQUENCY,
200 SMEM_SMD_PROFILES,
201 SMEM_TSSC_BUSY,
202 SMEM_HS_SUSPEND_FILTER_INFO,
203 SMEM_BATT_INFO,
204 SMEM_APPS_BOOT_MODE,
205 SMEM_VERSION_FIRST,
206 SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
207 SMEM_OSS_RRCASN1_BUF1,
208 SMEM_OSS_RRCASN1_BUF2,
209 SMEM_ID_VENDOR0,
210 SMEM_ID_VENDOR1,
211 SMEM_ID_VENDOR2,
212 SMEM_HW_SW_BUILD_ID,
213 SMEM_SMD_BLOCK_PORT_BASE_ID,
214 SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
215 SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
216 SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
217 SMEM_SCLK_CONVERSION,
218 SMEM_SMD_SMSM_INTR_MUX,
219 SMEM_SMSM_CPU_INTR_MASK,
220 SMEM_APPS_DEM_SLAVE_DATA,
221 SMEM_QDSP6_DEM_SLAVE_DATA,
222 SMEM_CLKREGIM_BSP,
223 SMEM_CLKREGIM_SOURCES,
224 SMEM_SMD_FIFO_BASE_ID,
225 SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
226 SMEM_POWER_ON_STATUS_INFO,
227 SMEM_DAL_AREA,
228 SMEM_SMEM_LOG_POWER_IDX,
229 SMEM_SMEM_LOG_POWER_WRAP,
230 SMEM_SMEM_LOG_POWER_EVENTS,
231 SMEM_ERR_CRASH_LOG,
232 SMEM_ERR_F3_TRACE_LOG,
233 SMEM_NUM_ITEMS,
234} smem_mem_type;
235
236
237#define SMD_SS_CLOSED 0x00000000
238#define SMD_SS_OPENING 0x00000001
239#define SMD_SS_OPENED 0x00000002
240#define SMD_SS_FLUSHING 0x00000003
241#define SMD_SS_CLOSING 0x00000004
242#define SMD_SS_RESET 0x00000005
243#define SMD_SS_RESET_OPENING 0x00000006
244
245#define SMD_BUF_SIZE 8192
246#define SMD_CHANNELS 64
247
248#define SMD_HEADER_SIZE 20
249
250struct smd_alloc_elm {
251 char name[20];
252 uint32_t cid;
253 uint32_t ctype;
254 uint32_t ref_count;
255};
256
257struct smd_half_channel {
258 unsigned state;
259 unsigned char fDSR;
260 unsigned char fCTS;
261 unsigned char fCD;
262 unsigned char fRI;
263 unsigned char fHEAD;
264 unsigned char fTAIL;
265 unsigned char fSTATE;
266 unsigned char fUNUSED;
267 unsigned tail;
268 unsigned head;
269} __attribute__(( aligned(4), packed ));
270
271/* Only used on SMD package v3 on msm7201a */
272struct smd_shared_v1 {
273 struct smd_half_channel ch0;
274 unsigned char data0[SMD_BUF_SIZE];
275 struct smd_half_channel ch1;
276 unsigned char data1[SMD_BUF_SIZE];
277};
278
279/* Used on SMD package v4 */
280struct smd_shared_v2 {
281 struct smd_half_channel ch0;
282 struct smd_half_channel ch1;
283};
284
285struct smd_channel {
286 volatile struct smd_half_channel *send;
287 volatile struct smd_half_channel *recv;
288 unsigned char *send_data;
289 unsigned char *recv_data;
290
291 unsigned fifo_mask;
292 unsigned fifo_size;
293 unsigned current_packet;
294 unsigned n;
295
296 struct list_head ch_list;
297
298 void *priv;
299 void (*notify)(void *priv, unsigned flags);
300
301 int (*read)(struct smd_channel *ch, void *data, int len);
302 int (*write)(struct smd_channel *ch, const void *data, int len);
303 int (*read_avail)(struct smd_channel *ch);
304 int (*write_avail)(struct smd_channel *ch);
305
306 void (*update_state)(struct smd_channel *ch);
307 unsigned last_state;
308 void (*notify_other_cpu)(void);
309 unsigned type;
310
311 char name[32];
312 struct platform_device pdev;
313};
314
315#define SMD_TYPE_MASK 0x0FF
316#define SMD_TYPE_APPS_MODEM 0x000
317#define SMD_TYPE_APPS_DSP 0x001
318#define SMD_TYPE_MODEM_DSP 0x002
319
320#define SMD_KIND_MASK 0xF00
321#define SMD_KIND_UNKNOWN 0x000
322#define SMD_KIND_STREAM 0x100
323#define SMD_KIND_PACKET 0x200
324
325extern struct list_head smd_ch_closed_list;
326extern struct list_head smd_ch_list_modem;
327extern struct list_head smd_ch_list_dsp;
328
329extern spinlock_t smd_lock;
330extern spinlock_t smem_lock;
331
332void *smem_find(unsigned id, unsigned size);
333void *smem_item(unsigned id, unsigned *size);
334uint32_t raw_smsm_get_state(enum smsm_state_item item);
335
336extern void msm_init_last_radio_log(struct module *);
337
338#ifdef CONFIG_MSM_SMD_PKG3
339/*
340 * This allocator assumes an SMD Package v3 which only exists on
341 * MSM7x00 SoC's.
342 */
343static inline int _smd_alloc_channel(struct smd_channel *ch)
344{
345 struct smd_shared_v1 *shared1;
346
347 shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
348 if (!shared1) {
349 pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
350 return -1;
351 }
352 ch->send = &shared1->ch0;
353 ch->recv = &shared1->ch1;
354 ch->send_data = shared1->data0;
355 ch->recv_data = shared1->data1;
356 ch->fifo_size = SMD_BUF_SIZE;
357 return 0;
358}
359#else
360/*
361 * This allocator assumes an SMD Package v4, the most common
362 * and the default.
363 */
364static inline int _smd_alloc_channel(struct smd_channel *ch)
365{
366 struct smd_shared_v2 *shared2;
367 void *buffer;
368 unsigned buffer_sz;
369
370 shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
371 buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
372
373 if (!buffer)
374 return -1;
375
376 /* buffer must be a power-of-two size */
377 if (buffer_sz & (buffer_sz - 1))
378 return -1;
379
380 buffer_sz /= 2;
381 ch->send = &shared2->ch0;
382 ch->recv = &shared2->ch1;
383 ch->send_data = buffer;
384 ch->recv_data = buffer + buffer_sz;
385 ch->fifo_size = buffer_sz;
386 return 0;
387}
388#endif /* CONFIG_MSM_SMD_PKG3 */
389
390#if defined(CONFIG_ARCH_MSM7X30)
391static inline void msm_a2m_int(uint32_t irq)
392{
393 writel(1 << irq, MSM_GCC_BASE + 0x8);
394}
395#else
396static inline void msm_a2m_int(uint32_t irq)
397{
398 writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
399}
400#endif /* CONFIG_ARCH_MSM7X30 */
401
402
403#endif
diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c
deleted file mode 100644
index bd66ed04d6dc..000000000000
--- a/arch/arm/mach-msm/vreg.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/* arch/arm/mach-msm/vreg.c
2 *
3 * Copyright (C) 2008 Google, Inc.
4 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/init.h>
21#include <linux/debugfs.h>
22#include <linux/module.h>
23#include <linux/string.h>
24#include <mach/vreg.h>
25
26#include "proc_comm.h"
27
28struct vreg {
29 const char *name;
30 unsigned id;
31 int status;
32 unsigned refcnt;
33};
34
35#define VREG(_name, _id, _status, _refcnt) \
36 { .name = _name, .id = _id, .status = _status, .refcnt = _refcnt }
37
38static struct vreg vregs[] = {
39 VREG("msma", 0, 0, 0),
40 VREG("msmp", 1, 0, 0),
41 VREG("msme1", 2, 0, 0),
42 VREG("msmc1", 3, 0, 0),
43 VREG("msmc2", 4, 0, 0),
44 VREG("gp3", 5, 0, 0),
45 VREG("msme2", 6, 0, 0),
46 VREG("gp4", 7, 0, 0),
47 VREG("gp1", 8, 0, 0),
48 VREG("tcxo", 9, 0, 0),
49 VREG("pa", 10, 0, 0),
50 VREG("rftx", 11, 0, 0),
51 VREG("rfrx1", 12, 0, 0),
52 VREG("rfrx2", 13, 0, 0),
53 VREG("synt", 14, 0, 0),
54 VREG("wlan", 15, 0, 0),
55 VREG("usb", 16, 0, 0),
56 VREG("boost", 17, 0, 0),
57 VREG("mmc", 18, 0, 0),
58 VREG("ruim", 19, 0, 0),
59 VREG("msmc0", 20, 0, 0),
60 VREG("gp2", 21, 0, 0),
61 VREG("gp5", 22, 0, 0),
62 VREG("gp6", 23, 0, 0),
63 VREG("rf", 24, 0, 0),
64 VREG("rf_vco", 26, 0, 0),
65 VREG("mpll", 27, 0, 0),
66 VREG("s2", 28, 0, 0),
67 VREG("s3", 29, 0, 0),
68 VREG("rfubm", 30, 0, 0),
69 VREG("ncp", 31, 0, 0),
70 VREG("gp7", 32, 0, 0),
71 VREG("gp8", 33, 0, 0),
72 VREG("gp9", 34, 0, 0),
73 VREG("gp10", 35, 0, 0),
74 VREG("gp11", 36, 0, 0),
75 VREG("gp12", 37, 0, 0),
76 VREG("gp13", 38, 0, 0),
77 VREG("gp14", 39, 0, 0),
78 VREG("gp15", 40, 0, 0),
79 VREG("gp16", 41, 0, 0),
80 VREG("gp17", 42, 0, 0),
81 VREG("s4", 43, 0, 0),
82 VREG("usb2", 44, 0, 0),
83 VREG("wlan2", 45, 0, 0),
84 VREG("xo_out", 46, 0, 0),
85 VREG("lvsw0", 47, 0, 0),
86 VREG("lvsw1", 48, 0, 0),
87};
88
89struct vreg *vreg_get(struct device *dev, const char *id)
90{
91 int n;
92 for (n = 0; n < ARRAY_SIZE(vregs); n++) {
93 if (!strcmp(vregs[n].name, id))
94 return vregs + n;
95 }
96 return ERR_PTR(-ENOENT);
97}
98
99void vreg_put(struct vreg *vreg)
100{
101}
102
103int vreg_enable(struct vreg *vreg)
104{
105 unsigned id = vreg->id;
106 unsigned enable = 1;
107
108 if (vreg->refcnt == 0)
109 vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
110
111 if ((vreg->refcnt < UINT_MAX) && (!vreg->status))
112 vreg->refcnt++;
113
114 return vreg->status;
115}
116
117int vreg_disable(struct vreg *vreg)
118{
119 unsigned id = vreg->id;
120 unsigned enable = 0;
121
122 if (!vreg->refcnt)
123 return 0;
124
125 if (vreg->refcnt == 1)
126 vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
127
128 if (!vreg->status)
129 vreg->refcnt--;
130
131 return vreg->status;
132}
133
134int vreg_set_level(struct vreg *vreg, unsigned mv)
135{
136 unsigned id = vreg->id;
137
138 vreg->status = msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
139 return vreg->status;
140}
141
142#if defined(CONFIG_DEBUG_FS)
143
144static int vreg_debug_set(void *data, u64 val)
145{
146 struct vreg *vreg = data;
147 switch (val) {
148 case 0:
149 vreg_disable(vreg);
150 break;
151 case 1:
152 vreg_enable(vreg);
153 break;
154 default:
155 vreg_set_level(vreg, val);
156 break;
157 }
158 return 0;
159}
160
161static int vreg_debug_get(void *data, u64 *val)
162{
163 struct vreg *vreg = data;
164
165 if (!vreg->status)
166 *val = 0;
167 else
168 *val = 1;
169
170 return 0;
171}
172
173static int vreg_debug_count_set(void *data, u64 val)
174{
175 struct vreg *vreg = data;
176 if (val > UINT_MAX)
177 val = UINT_MAX;
178 vreg->refcnt = val;
179 return 0;
180}
181
182static int vreg_debug_count_get(void *data, u64 *val)
183{
184 struct vreg *vreg = data;
185
186 *val = vreg->refcnt;
187
188 return 0;
189}
190
191DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n");
192DEFINE_SIMPLE_ATTRIBUTE(vreg_count_fops, vreg_debug_count_get,
193 vreg_debug_count_set, "%llu\n");
194
195static int __init vreg_debug_init(void)
196{
197 struct dentry *dent;
198 int n;
199 char name[32];
200 const char *refcnt_name = "_refcnt";
201
202 dent = debugfs_create_dir("vreg", 0);
203 if (IS_ERR(dent))
204 return 0;
205
206 for (n = 0; n < ARRAY_SIZE(vregs); n++) {
207 (void) debugfs_create_file(vregs[n].name, 0644,
208 dent, vregs + n, &vreg_fops);
209
210 strlcpy(name, vregs[n].name, sizeof(name));
211 strlcat(name, refcnt_name, sizeof(name));
212 (void) debugfs_create_file(name, 0644,
213 dent, vregs + n, &vreg_count_fops);
214 }
215
216 return 0;
217}
218
219device_initcall(vreg_debug_init);
220#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 18:27:02 -0500