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authorGavin Shan <gwshan@linux.vnet.ibm.com>2014-10-01 03:07:53 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2014-10-14 20:27:20 -0400
commitb6541db1395298b326ae1bf59fae6fbb2c6e8f77 (patch)
tree5f59a01441a5e8c4abaf58f08dbe208a90f5fbe7 /arch
parent3409eb4e69e1150202bc4ec61801115da32aa380 (diff)
powerpc/eeh: Block PCI config access upon frozen PE
The problem was found when I tried to inject PCI config error by PHB3 PAPR error injection registers into Broadcom Austin 4-ports NIC adapter. The frozen PE was reported successfully and EEH core started to recover it. However, I run into fenced PHB when dumping PCI config space as EEH logs. I was told that PCI config requests should not be progagated to the adapter until PE reset is done successfully. Otherise, we would run out of PHB internal credits and trigger PCT (PCIE Completion Timeout), which leads to the fenced PHB. The patch introduces another PE flag EEH_PE_CFG_RESTRICTED, which is set during PE initialization time if the PE includes the specific PCI devices that need block PCI config access until PE reset is done. When the PE becomes frozen for the first time, EEH_PE_CFG_BLOCKED is set if the PE has flag EEH_PE_CFG_RESTRICTED. Then the PCI config access to the PE will be dropped by platform PCI accessors until PE reset is done successfully. The mechanism is shared by PowerNV platform owned PE or userland owned ones. It's not used on pSeries platform yet. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/eeh.h1
-rw-r--r--arch/powerpc/kernel/eeh_pe.c8
-rw-r--r--arch/powerpc/platforms/powernv/eeh-powernv.c19
3 files changed, 28 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 6a2ad90e6d8c..ca07f9c27335 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -74,6 +74,7 @@ struct device_node;
74#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 74#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
75 75
76#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 76#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
77#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
77 78
78struct eeh_pe { 79struct eeh_pe {
79 int type; /* PE type: PHB/Bus/Device */ 80 int type; /* PE type: PHB/Bus/Device */
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index 37f21284809c..5a63e2b0f65b 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -534,6 +534,10 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
534 pdev->error_state = pci_channel_io_frozen; 534 pdev->error_state = pci_channel_io_frozen;
535 } 535 }
536 536
537 /* Block PCI config access if required */
538 if (pe->state & EEH_PE_CFG_RESTRICTED)
539 pe->state |= EEH_PE_CFG_BLOCKED;
540
537 return NULL; 541 return NULL;
538} 542}
539 543
@@ -611,6 +615,10 @@ static void *__eeh_pe_state_clear(void *data, void *flag)
611 pdev->error_state = pci_channel_io_normal; 615 pdev->error_state = pci_channel_io_normal;
612 } 616 }
613 617
618 /* Unblock PCI config access if required */
619 if (pe->state & EEH_PE_CFG_RESTRICTED)
620 pe->state &= ~EEH_PE_CFG_BLOCKED;
621
614 return NULL; 622 return NULL;
615} 623}
616 624
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 04e42f78a37a..443ce965a5b0 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -169,6 +169,25 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
169 } 169 }
170 170
171 /* 171 /*
172 * If the PE contains any one of following adapters, the
173 * PCI config space can't be accessed when dumping EEH log.
174 * Otherwise, we will run into fenced PHB caused by shortage
175 * of outbound credits in the adapter. The PCI config access
176 * should be blocked until PE reset. MMIO access is dropped
177 * by hardware certainly. In order to drop PCI config requests,
178 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
179 * will be checked in the backend for PE state retrival. If
180 * the PE becomes frozen for the first time and the flag has
181 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
182 * that PE to block its config space.
183 *
184 * Broadcom Austin 4-ports NICs (14e4:1657)
185 */
186 if (dev->vendor == PCI_VENDOR_ID_BROADCOM &&
187 dev->device == 0x1657)
188 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
189
190 /*
172 * Cache the PE primary bus, which can't be fetched when 191 * Cache the PE primary bus, which can't be fetched when
173 * full hotplug is in progress. In that case, all child 192 * full hotplug is in progress. In that case, all child
174 * PCI devices of the PE are expected to be removed prior 193 * PCI devices of the PE are expected to be removed prior