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authorNicolas Pitre <nicolas.pitre@linaro.org>2013-02-18 23:11:30 -0500
committerShawn Guo <shawn.guo@linaro.org>2013-03-03 20:20:09 -0500
commitb4e6153704dda5bef78dd59324205b5e61829499 (patch)
treed35becb2f01f88da2249d07e8e4758f34c07fcfd /arch
parent6dbe51c251a327e012439c4772097a13df43c5b8 (diff)
ARM: mach-imx: move early resume code out of the .data section
Building the kernel with allyesconfig fails because the i.mx early resume code located in the .data section is unable to fixup the bl relocation as the branch target gets too far away. The idea of having code in the .data section allows for easy access to nearby data using relative addressing while the MMU is off. However it is probably best to move the code back to the .text section where it belongs and fixup the data access instead. This solves the bl reloc issue (at least until this becomes a general problem) and simplifies the code as well. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/headsmp.S18
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c15
2 files changed, 9 insertions, 24 deletions
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 921fc1555854..a58c8b0527cc 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -26,16 +26,16 @@ ENDPROC(v7_secondary_startup)
26 26
27#ifdef CONFIG_PM 27#ifdef CONFIG_PM
28/* 28/*
29 * The following code is located into the .data section. This is to 29 * The following code must assume it is running from physical address
30 * allow phys_l2x0_saved_regs to be accessed with a relative load 30 * where absolute virtual addresses to the data section have to be
31 * as we are running on physical address here. 31 * turned into relative ones.
32 */ 32 */
33 .data
34 .align
35 33
36#ifdef CONFIG_CACHE_L2X0 34#ifdef CONFIG_CACHE_L2X0
37 .macro pl310_resume 35 .macro pl310_resume
38 ldr r2, phys_l2x0_saved_regs 36 adr r0, l2x0_saved_regs_offset
37 ldr r2, [r0]
38 add r2, r2, r0
39 ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 39 ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
40 ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value 40 ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
41 str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl 41 str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
@@ -43,9 +43,9 @@ ENDPROC(v7_secondary_startup)
43 str r1, [r0, #L2X0_CTRL] @ re-enable L2 43 str r1, [r0, #L2X0_CTRL] @ re-enable L2
44 .endm 44 .endm
45 45
46 .globl phys_l2x0_saved_regs 46l2x0_saved_regs_offset:
47phys_l2x0_saved_regs: 47 .word l2x0_saved_regs - .
48 .long 0 48
49#else 49#else
50 .macro pl310_resume 50 .macro pl310_resume
51 .endm 51 .endm
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index ee42d20cba19..5faba7a3c95f 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -22,8 +22,6 @@
22#include "common.h" 22#include "common.h"
23#include "hardware.h" 23#include "hardware.h"
24 24
25extern unsigned long phys_l2x0_saved_regs;
26
27static int imx6q_suspend_finish(unsigned long val) 25static int imx6q_suspend_finish(unsigned long val)
28{ 26{
29 cpu_do_idle(); 27 cpu_do_idle();
@@ -57,18 +55,5 @@ static const struct platform_suspend_ops imx6q_pm_ops = {
57 55
58void __init imx6q_pm_init(void) 56void __init imx6q_pm_init(void)
59{ 57{
60 /*
61 * The l2x0 core code provides an infrastucture to save and restore
62 * l2x0 registers across suspend/resume cycle. But because imx6q
63 * retains L2 content during suspend and needs to resume L2 before
64 * MMU is enabled, it can only utilize register saving support and
65 * have to take care of restoring on its own. So we save physical
66 * address of the data structure used by l2x0 core to save registers,
67 * and later restore the necessary ones in imx6q resume entry.
68 */
69#ifdef CONFIG_CACHE_L2X0
70 phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
71#endif
72
73 suspend_set_ops(&imx6q_pm_ops); 58 suspend_set_ops(&imx6q_pm_ops);
74} 59}