diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 16:30:06 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 16:30:06 -0400 |
| commit | b4b50fd78b1e31989940dfc647e64453d0f7176a (patch) | |
| tree | 1a55f110e021c02963b63759f3f18ea7ba3aa228 /arch | |
| parent | dccfd1e439c11422d7aca0d834b0430d24650e85 (diff) | |
| parent | f97c43bbdf8a1ea42477b1a804a48e7e368cb13c (diff) | |
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This branch contains mostly additions and changes to platform
enablement and SoC-level drivers. Since there's sometimes a
dependency on device-tree changes, there's also a fair amount of
those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad
Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving MSI
arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
...
Diffstat (limited to 'arch')
259 files changed, 9599 insertions, 6005 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bf7976439c39..a00f4c1c7d71 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -442,7 +442,6 @@ config ARCH_NETX | |||
| 442 | config ARCH_IOP13XX | 442 | config ARCH_IOP13XX |
| 443 | bool "IOP13xx-based" | 443 | bool "IOP13xx-based" |
| 444 | depends on MMU | 444 | depends on MMU |
| 445 | select ARCH_SUPPORTS_MSI | ||
| 446 | select CPU_XSC3 | 445 | select CPU_XSC3 |
| 447 | select NEED_MACH_MEMORY_H | 446 | select NEED_MACH_MEMORY_H |
| 448 | select NEED_RET_TO_USER | 447 | select NEED_RET_TO_USER |
| @@ -1600,7 +1599,7 @@ config ARM_PSCI | |||
| 1600 | config ARCH_NR_GPIO | 1599 | config ARCH_NR_GPIO |
| 1601 | int | 1600 | int |
| 1602 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA | 1601 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
| 1603 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 | 1602 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX |
| 1604 | default 392 if ARCH_U8500 | 1603 | default 392 if ARCH_U8500 |
| 1605 | default 352 if ARCH_VT8500 | 1604 | default 352 if ARCH_VT8500 |
| 1606 | default 288 if ARCH_SUNXI | 1605 | default 288 if ARCH_SUNXI |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 454288db3180..f9f4c4d9c704 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ | |||
| 91 | kirkwood-ns2max.dtb \ | 91 | kirkwood-ns2max.dtb \ |
| 92 | kirkwood-ns2mini.dtb \ | 92 | kirkwood-ns2mini.dtb \ |
| 93 | kirkwood-nsa310.dtb \ | 93 | kirkwood-nsa310.dtb \ |
| 94 | kirkwood-nsa310a.dtb \ | ||
| 94 | kirkwood-sheevaplug.dtb \ | 95 | kirkwood-sheevaplug.dtb \ |
| 95 | kirkwood-sheevaplug-esata.dtb \ | 96 | kirkwood-sheevaplug-esata.dtb \ |
| 96 | kirkwood-topkick.dtb \ | 97 | kirkwood-topkick.dtb \ |
| @@ -102,7 +103,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ | |||
| 102 | msm8960-cdp.dtb | 103 | msm8960-cdp.dtb |
| 103 | dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ | 104 | dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ |
| 104 | armada-370-mirabox.dtb \ | 105 | armada-370-mirabox.dtb \ |
| 106 | armada-370-netgear-rn102.dtb \ | ||
| 105 | armada-370-rd.dtb \ | 107 | armada-370-rd.dtb \ |
| 108 | armada-xp-axpwifiap.dtb \ | ||
| 106 | armada-xp-db.dtb \ | 109 | armada-xp-db.dtb \ |
| 107 | armada-xp-gp.dtb \ | 110 | armada-xp-gp.dtb \ |
| 108 | armada-xp-openblocks-ax3-4.dtb | 111 | armada-xp-openblocks-ax3-4.dtb |
| @@ -114,6 +117,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 114 | imx27-pdk.dtb \ | 117 | imx27-pdk.dtb \ |
| 115 | imx27-phytec-phycore-som.dtb \ | 118 | imx27-phytec-phycore-som.dtb \ |
| 116 | imx27-phytec-phycore-rdk.dtb \ | 119 | imx27-phytec-phycore-rdk.dtb \ |
| 120 | imx27-phytec-phycard-s-som.dtb \ | ||
| 121 | imx27-phytec-phycard-s-rdk.dtb \ | ||
| 117 | imx31-bug.dtb \ | 122 | imx31-bug.dtb \ |
| 118 | imx51-apf51.dtb \ | 123 | imx51-apf51.dtb \ |
| 119 | imx51-apf51dev.dtb \ | 124 | imx51-apf51dev.dtb \ |
| @@ -133,6 +138,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 133 | imx6q-sabrelite.dtb \ | 138 | imx6q-sabrelite.dtb \ |
| 134 | imx6q-sabresd.dtb \ | 139 | imx6q-sabresd.dtb \ |
| 135 | imx6q-sbc6x.dtb \ | 140 | imx6q-sbc6x.dtb \ |
| 141 | imx6q-wandboard.dtb \ | ||
| 136 | imx6sl-evk.dtb \ | 142 | imx6sl-evk.dtb \ |
| 137 | vf610-twr.dtb | 143 | vf610-twr.dtb |
| 138 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | 144 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ |
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index beee1699d49e..90ce29dbe119 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /dts-v1/; | 16 | /dts-v1/; |
| 17 | /include/ "armada-370.dtsi" | 17 | #include "armada-370.dtsi" |
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "Marvell Armada 370 Evaluation Board"; | 20 | model = "Marvell Armada 370 Evaluation Board"; |
| @@ -30,6 +30,9 @@ | |||
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | soc { | 32 | soc { |
| 33 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 | ||
| 34 | MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; | ||
| 35 | |||
| 33 | internal-regs { | 36 | internal-regs { |
| 34 | serial@12000 { | 37 | serial@12000 { |
| 35 | clock-frequency = <200000000>; | 38 | clock-frequency = <200000000>; |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 45b107763e3b..2471d9da767b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | /include/ "armada-370.dtsi" | 12 | #include "armada-370.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "Globalscale Mirabox"; | 15 | model = "Globalscale Mirabox"; |
| @@ -25,6 +25,25 @@ | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | soc { | 27 | soc { |
| 28 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 | ||
| 29 | MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; | ||
| 30 | |||
| 31 | pcie-controller { | ||
| 32 | status = "okay"; | ||
| 33 | |||
| 34 | /* Internal mini-PCIe connector */ | ||
| 35 | pcie@1,0 { | ||
| 36 | /* Port 0, Lane 0 */ | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* Connected on the PCB to a USB 3.0 XHCI controller */ | ||
| 41 | pcie@2,0 { | ||
| 42 | /* Port 1, Lane 0 */ | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | |||
| 28 | internal-regs { | 47 | internal-regs { |
| 29 | serial@12000 { | 48 | serial@12000 { |
| 30 | clock-frequency = <200000000>; | 49 | clock-frequency = <200000000>; |
| @@ -120,22 +139,6 @@ | |||
| 120 | reg = <0x25>; | 139 | reg = <0x25>; |
| 121 | }; | 140 | }; |
| 122 | }; | 141 | }; |
| 123 | |||
| 124 | pcie-controller { | ||
| 125 | status = "okay"; | ||
| 126 | |||
| 127 | /* Internal mini-PCIe connector */ | ||
| 128 | pcie@1,0 { | ||
| 129 | /* Port 0, Lane 0 */ | ||
| 130 | status = "okay"; | ||
| 131 | }; | ||
| 132 | |||
| 133 | /* Connected on the PCB to a USB 3.0 XHCI controller */ | ||
| 134 | pcie@2,0 { | ||
| 135 | /* Port 1, Lane 0 */ | ||
| 136 | status = "okay"; | ||
| 137 | }; | ||
| 138 | }; | ||
| 139 | }; | 142 | }; |
| 140 | }; | 143 | }; |
| 141 | }; | 144 | }; |
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts new file mode 100644 index 000000000000..05e4485a8225 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts | |||
| @@ -0,0 +1,179 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for NETGEAR ReadyNAS 102 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | |||
| 14 | #include "armada-370.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "NETGEAR ReadyNAS 102"; | ||
| 18 | compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; | ||
| 19 | |||
| 20 | chosen { | ||
| 21 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | memory { | ||
| 25 | device_type = "memory"; | ||
| 26 | reg = <0x00000000 0x20000000>; /* 512 MB */ | ||
| 27 | }; | ||
| 28 | |||
| 29 | soc { | ||
| 30 | internal-regs { | ||
| 31 | serial@12000 { | ||
| 32 | clock-frequency = <200000000>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | sata@a0000 { | ||
| 37 | nr-ports = <2>; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | pinctrl { | ||
| 42 | power_led_pin: power-led-pin { | ||
| 43 | marvell,pins = "mpp57"; | ||
| 44 | marvell,function = "gpio"; | ||
| 45 | }; | ||
| 46 | sata1_led_pin: sata1-led-pin { | ||
| 47 | marvell,pins = "mpp15"; | ||
| 48 | marvell,function = "gpio"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | sata2_led_pin: sata2-led-pin { | ||
| 52 | marvell,pins = "mpp14"; | ||
| 53 | marvell,function = "gpio"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | backup_led_pin: backup-led-pin { | ||
| 57 | marvell,pins = "mpp56"; | ||
| 58 | marvell,function = "gpio"; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | mdio { | ||
| 63 | phy0: ethernet-phy@0 { | ||
| 64 | reg = <0>; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 68 | ethernet@74000 { | ||
| 69 | status = "okay"; | ||
| 70 | phy = <&phy0>; | ||
| 71 | phy-mode = "rgmii-id"; | ||
| 72 | }; | ||
| 73 | |||
| 74 | usb@50000 { | ||
| 75 | status = "okay"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | i2c@11000 { | ||
| 79 | compatible = "marvell,mv64xxx-i2c"; | ||
| 80 | clock-frequency = <100000>; | ||
| 81 | status = "okay"; | ||
| 82 | |||
| 83 | g762: g762@3e { | ||
| 84 | compatible = "gmt,g762"; | ||
| 85 | reg = <0x3e>; | ||
| 86 | clocks = <&g762_clk>; /* input clock */ | ||
| 87 | fan_gear_mode = <0>; | ||
| 88 | fan_startv = <1>; | ||
| 89 | pwm_polarity = <0>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 93 | pcie-controller { | ||
| 94 | status = "okay"; | ||
| 95 | |||
| 96 | /* Connected to Marvell SATA controller */ | ||
| 97 | pcie@1,0 { | ||
| 98 | /* Port 0, Lane 0 */ | ||
| 99 | status = "okay"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | /* Connected to FL1009 USB 3.0 controller */ | ||
| 103 | pcie@2,0 { | ||
| 104 | /* Port 1, Lane 0 */ | ||
| 105 | status = "okay"; | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | }; | ||
| 109 | }; | ||
| 110 | |||
| 111 | clocks { | ||
| 112 | #address-cells = <1>; | ||
| 113 | #size-cells = <0>; | ||
| 114 | |||
| 115 | g762_clk: fixedclk { | ||
| 116 | compatible = "fixed-clock"; | ||
| 117 | #clock-cells = <0>; | ||
| 118 | clock-frequency = <8192>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | |||
| 122 | gpio_leds { | ||
| 123 | compatible = "gpio-leds"; | ||
| 124 | pinctrl-0 = < &power_led_pin | ||
| 125 | &sata1_led_pin | ||
| 126 | &sata2_led_pin | ||
| 127 | &backup_led_pin >; | ||
| 128 | pinctrl-names = "default"; | ||
| 129 | |||
| 130 | blue_power_led { | ||
| 131 | label = "rn102:blue:pwr"; | ||
| 132 | gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */ | ||
| 133 | linux,default-trigger = "heartbeat"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | green_sata1_led { | ||
| 137 | label = "rn102:green:sata1"; | ||
| 138 | gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */ | ||
| 139 | default-state = "on"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | green_sata2_led { | ||
| 143 | label = "rn102:green:sata2"; | ||
| 144 | gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */ | ||
| 145 | default-state = "on"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | green_backup_led { | ||
| 149 | label = "rn102:green:backup"; | ||
| 150 | gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */ | ||
| 151 | default-state = "on"; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 155 | gpio_keys { | ||
| 156 | compatible = "gpio-keys"; | ||
| 157 | #address-cells = <1>; | ||
| 158 | #size-cells = <0>; | ||
| 159 | |||
| 160 | button@1 { | ||
| 161 | label = "Power Button"; | ||
| 162 | linux,code = <116>; /* KEY_POWER */ | ||
| 163 | gpios = <&gpio1 30 1>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | button@2 { | ||
| 167 | label = "Reset Button"; | ||
| 168 | linux,code = <0x198>; /* KEY_RESTART */ | ||
| 169 | gpios = <&gpio0 6 1>; | ||
| 170 | }; | ||
| 171 | |||
| 172 | button@3 { | ||
| 173 | label = "Backup Button"; | ||
| 174 | linux,code = <133>; /* KEY_COPY */ | ||
| 175 | gpios = <&gpio1 26 1>; | ||
| 176 | }; | ||
| 177 | }; | ||
| 178 | |||
| 179 | }; | ||
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index a3a2fedb8726..f81810a59629 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | /include/ "armada-370.dtsi" | 15 | #include "armada-370.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "Marvell Armada 370 Reference Design"; | 18 | model = "Marvell Armada 370 Reference Design"; |
| @@ -28,6 +28,25 @@ | |||
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | soc { | 30 | soc { |
| 31 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 | ||
| 32 | MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; | ||
| 33 | |||
| 34 | pcie-controller { | ||
| 35 | status = "okay"; | ||
| 36 | |||
| 37 | /* Internal mini-PCIe connector */ | ||
| 38 | pcie@1,0 { | ||
| 39 | /* Port 0, Lane 0 */ | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | /* Internal mini-PCIe connector */ | ||
| 44 | pcie@2,0 { | ||
| 45 | /* Port 1, Lane 0 */ | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | |||
| 31 | internal-regs { | 50 | internal-regs { |
| 32 | serial@12000 { | 51 | serial@12000 { |
| 33 | clock-frequency = <200000000>; | 52 | clock-frequency = <200000000>; |
| @@ -85,22 +104,6 @@ | |||
| 85 | gpios = <&gpio0 6 1>; | 104 | gpios = <&gpio0 6 1>; |
| 86 | }; | 105 | }; |
| 87 | }; | 106 | }; |
| 88 | |||
| 89 | pcie-controller { | ||
| 90 | status = "okay"; | ||
| 91 | |||
| 92 | /* Internal mini-PCIe connector */ | ||
| 93 | pcie@1,0 { | ||
| 94 | /* Port 0, Lane 0 */ | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* Internal mini-PCIe connector */ | ||
| 99 | pcie@2,0 { | ||
| 100 | /* Port 1, Lane 0 */ | ||
| 101 | status = "okay"; | ||
| 102 | }; | ||
| 103 | }; | ||
| 104 | }; | 107 | }; |
| 105 | }; | 108 | }; |
| 106 | }; | 109 | }; |
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 90b117624abb..1de2dae0fdae 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -18,6 +18,8 @@ | |||
| 18 | 18 | ||
| 19 | /include/ "skeleton64.dtsi" | 19 | /include/ "skeleton64.dtsi" |
| 20 | 20 | ||
| 21 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | ||
| 22 | |||
| 21 | / { | 23 | / { |
| 22 | model = "Marvell Armada 370 and XP SoC"; | 24 | model = "Marvell Armada 370 and XP SoC"; |
| 23 | compatible = "marvell,armada-370-xp"; | 25 | compatible = "marvell,armada-370-xp"; |
| @@ -38,18 +40,73 @@ | |||
| 38 | }; | 40 | }; |
| 39 | 41 | ||
| 40 | soc { | 42 | soc { |
| 41 | #address-cells = <1>; | 43 | #address-cells = <2>; |
| 42 | #size-cells = <1>; | 44 | #size-cells = <1>; |
| 43 | compatible = "simple-bus"; | 45 | controller = <&mbusc>; |
| 44 | interrupt-parent = <&mpic>; | 46 | interrupt-parent = <&mpic>; |
| 45 | ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ | 47 | pcie-mem-aperture = <0xe0000000 0x8000000>; |
| 46 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; | 48 | pcie-io-aperture = <0xe8000000 0x100000>; |
| 49 | |||
| 50 | devbus-bootcs { | ||
| 51 | compatible = "marvell,mvebu-devbus"; | ||
| 52 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | ||
| 53 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | ||
| 54 | #address-cells = <1>; | ||
| 55 | #size-cells = <1>; | ||
| 56 | clocks = <&coreclk 0>; | ||
| 57 | status = "disabled"; | ||
| 58 | }; | ||
| 59 | |||
| 60 | devbus-cs0 { | ||
| 61 | compatible = "marvell,mvebu-devbus"; | ||
| 62 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | ||
| 63 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | ||
| 64 | #address-cells = <1>; | ||
| 65 | #size-cells = <1>; | ||
| 66 | clocks = <&coreclk 0>; | ||
| 67 | status = "disabled"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | devbus-cs1 { | ||
| 71 | compatible = "marvell,mvebu-devbus"; | ||
| 72 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | ||
| 73 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | ||
| 74 | #address-cells = <1>; | ||
| 75 | #size-cells = <1>; | ||
| 76 | clocks = <&coreclk 0>; | ||
| 77 | status = "disabled"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | devbus-cs2 { | ||
| 81 | compatible = "marvell,mvebu-devbus"; | ||
| 82 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | ||
| 83 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | ||
| 84 | #address-cells = <1>; | ||
| 85 | #size-cells = <1>; | ||
| 86 | clocks = <&coreclk 0>; | ||
| 87 | status = "disabled"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | devbus-cs3 { | ||
| 91 | compatible = "marvell,mvebu-devbus"; | ||
| 92 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | ||
| 93 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | ||
| 94 | #address-cells = <1>; | ||
| 95 | #size-cells = <1>; | ||
| 96 | clocks = <&coreclk 0>; | ||
| 97 | status = "disabled"; | ||
| 98 | }; | ||
| 47 | 99 | ||
| 48 | internal-regs { | 100 | internal-regs { |
| 49 | compatible = "simple-bus"; | 101 | compatible = "simple-bus"; |
| 50 | #address-cells = <1>; | 102 | #address-cells = <1>; |
| 51 | #size-cells = <1>; | 103 | #size-cells = <1>; |
| 52 | ranges; | 104 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
| 105 | |||
| 106 | mbusc: mbus-controller@20000 { | ||
| 107 | compatible = "marvell,mbus-controller"; | ||
| 108 | reg = <0x20000 0x100>, <0x20180 0x20>; | ||
| 109 | }; | ||
| 53 | 110 | ||
| 54 | mpic: interrupt-controller@20000 { | 111 | mpic: interrupt-controller@20000 { |
| 55 | compatible = "marvell,mpic"; | 112 | compatible = "marvell,mpic"; |
| @@ -81,10 +138,8 @@ | |||
| 81 | }; | 138 | }; |
| 82 | 139 | ||
| 83 | timer@20300 { | 140 | timer@20300 { |
| 84 | compatible = "marvell,armada-370-xp-timer"; | ||
| 85 | reg = <0x20300 0x30>, <0x21040 0x30>; | 141 | reg = <0x20300 0x30>, <0x21040 0x30>; |
| 86 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | 142 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; |
| 87 | clocks = <&coreclk 2>; | ||
| 88 | }; | 143 | }; |
| 89 | 144 | ||
| 90 | sata@a0000 { | 145 | sata@a0000 { |
| @@ -195,50 +250,6 @@ | |||
| 195 | status = "disabled"; | 250 | status = "disabled"; |
| 196 | }; | 251 | }; |
| 197 | 252 | ||
| 198 | devbus-bootcs@10400 { | ||
| 199 | compatible = "marvell,mvebu-devbus"; | ||
| 200 | reg = <0x10400 0x8>; | ||
| 201 | #address-cells = <1>; | ||
| 202 | #size-cells = <1>; | ||
| 203 | clocks = <&coreclk 0>; | ||
| 204 | status = "disabled"; | ||
| 205 | }; | ||
| 206 | |||
| 207 | devbus-cs0@10408 { | ||
| 208 | compatible = "marvell,mvebu-devbus"; | ||
| 209 | reg = <0x10408 0x8>; | ||
| 210 | #address-cells = <1>; | ||
| 211 | #size-cells = <1>; | ||
| 212 | clocks = <&coreclk 0>; | ||
| 213 | status = "disabled"; | ||
| 214 | }; | ||
| 215 | |||
| 216 | devbus-cs1@10410 { | ||
| 217 | compatible = "marvell,mvebu-devbus"; | ||
| 218 | reg = <0x10410 0x8>; | ||
| 219 | #address-cells = <1>; | ||
| 220 | #size-cells = <1>; | ||
| 221 | clocks = <&coreclk 0>; | ||
| 222 | status = "disabled"; | ||
| 223 | }; | ||
| 224 | |||
| 225 | devbus-cs2@10418 { | ||
| 226 | compatible = "marvell,mvebu-devbus"; | ||
| 227 | reg = <0x10418 0x8>; | ||
| 228 | #address-cells = <1>; | ||
| 229 | #size-cells = <1>; | ||
| 230 | clocks = <&coreclk 0>; | ||
| 231 | status = "disabled"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | devbus-cs3@10420 { | ||
| 235 | compatible = "marvell,mvebu-devbus"; | ||
| 236 | reg = <0x10420 0x8>; | ||
| 237 | #address-cells = <1>; | ||
| 238 | #size-cells = <1>; | ||
| 239 | clocks = <&coreclk 0>; | ||
| 240 | status = "disabled"; | ||
| 241 | }; | ||
| 242 | }; | 253 | }; |
| 243 | }; | 254 | }; |
| 244 | }; | 255 | }; |
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index fa3dfc6b4c6a..e134d7a90c9a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | * common to all Armada SoCs. | 15 | * common to all Armada SoCs. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | /include/ "armada-370-xp.dtsi" | 18 | #include "armada-370-xp.dtsi" |
| 19 | /include/ "skeleton.dtsi" | 19 | /include/ "skeleton.dtsi" |
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| @@ -29,8 +29,66 @@ | |||
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | soc { | 31 | soc { |
| 32 | ranges = <0 0xd0000000 0x0100000 /* internal registers */ | 32 | compatible = "marvell,armada370-mbus", "simple-bus"; |
| 33 | 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; | 33 | |
| 34 | bootrom { | ||
| 35 | compatible = "marvell,bootrom"; | ||
| 36 | reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | pcie-controller { | ||
| 40 | compatible = "marvell,armada-370-pcie"; | ||
| 41 | status = "disabled"; | ||
| 42 | device_type = "pci"; | ||
| 43 | |||
| 44 | #address-cells = <3>; | ||
| 45 | #size-cells = <2>; | ||
| 46 | |||
| 47 | bus-range = <0x00 0xff>; | ||
| 48 | |||
| 49 | ranges = | ||
| 50 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 51 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | ||
| 52 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 53 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 54 | 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | ||
| 55 | 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; | ||
| 56 | |||
| 57 | pcie@1,0 { | ||
| 58 | device_type = "pci"; | ||
| 59 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 60 | reg = <0x0800 0 0 0 0>; | ||
| 61 | #address-cells = <3>; | ||
| 62 | #size-cells = <2>; | ||
| 63 | #interrupt-cells = <1>; | ||
| 64 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 65 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 66 | interrupt-map-mask = <0 0 0 0>; | ||
| 67 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 68 | marvell,pcie-port = <0>; | ||
| 69 | marvell,pcie-lane = <0>; | ||
| 70 | clocks = <&gateclk 5>; | ||
| 71 | status = "disabled"; | ||
| 72 | }; | ||
| 73 | |||
| 74 | pcie@2,0 { | ||
| 75 | device_type = "pci"; | ||
| 76 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 77 | reg = <0x1000 0 0 0 0>; | ||
| 78 | #address-cells = <3>; | ||
| 79 | #size-cells = <2>; | ||
| 80 | #interrupt-cells = <1>; | ||
| 81 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 82 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 83 | interrupt-map-mask = <0 0 0 0>; | ||
| 84 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 85 | marvell,pcie-port = <1>; | ||
| 86 | marvell,pcie-lane = <0>; | ||
| 87 | clocks = <&gateclk 9>; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 34 | internal-regs { | 92 | internal-regs { |
| 35 | system-controller@18200 { | 93 | system-controller@18200 { |
| 36 | compatible = "marvell,armada-370-xp-system-controller"; | 94 | compatible = "marvell,armada-370-xp-system-controller"; |
| @@ -78,7 +136,7 @@ | |||
| 78 | gpio-controller; | 136 | gpio-controller; |
| 79 | #gpio-cells = <2>; | 137 | #gpio-cells = <2>; |
| 80 | interrupt-controller; | 138 | interrupt-controller; |
| 81 | #interrupts-cells = <2>; | 139 | #interrupt-cells = <2>; |
| 82 | interrupts = <82>, <83>, <84>, <85>; | 140 | interrupts = <82>, <83>, <84>, <85>; |
| 83 | }; | 141 | }; |
| 84 | 142 | ||
| @@ -89,7 +147,7 @@ | |||
| 89 | gpio-controller; | 147 | gpio-controller; |
| 90 | #gpio-cells = <2>; | 148 | #gpio-cells = <2>; |
| 91 | interrupt-controller; | 149 | interrupt-controller; |
| 92 | #interrupts-cells = <2>; | 150 | #interrupt-cells = <2>; |
| 93 | interrupts = <87>, <88>, <89>, <90>; | 151 | interrupts = <87>, <88>, <89>, <90>; |
| 94 | }; | 152 | }; |
| 95 | 153 | ||
| @@ -100,10 +158,15 @@ | |||
| 100 | gpio-controller; | 158 | gpio-controller; |
| 101 | #gpio-cells = <2>; | 159 | #gpio-cells = <2>; |
| 102 | interrupt-controller; | 160 | interrupt-controller; |
| 103 | #interrupts-cells = <2>; | 161 | #interrupt-cells = <2>; |
| 104 | interrupts = <91>; | 162 | interrupts = <91>; |
| 105 | }; | 163 | }; |
| 106 | 164 | ||
| 165 | timer@20300 { | ||
| 166 | compatible = "marvell,armada-370-timer"; | ||
| 167 | clocks = <&coreclk 2>; | ||
| 168 | }; | ||
| 169 | |||
| 107 | coreclk: mvebu-sar@18230 { | 170 | coreclk: mvebu-sar@18230 { |
| 108 | compatible = "marvell,armada-370-core-clock"; | 171 | compatible = "marvell,armada-370-core-clock"; |
| 109 | reg = <0x18230 0x08>; | 172 | reg = <0x18230 0x08>; |
| @@ -169,54 +232,6 @@ | |||
| 169 | 0x18304 0x4>; | 232 | 0x18304 0x4>; |
| 170 | status = "okay"; | 233 | status = "okay"; |
| 171 | }; | 234 | }; |
| 172 | |||
| 173 | pcie-controller { | ||
| 174 | compatible = "marvell,armada-370-pcie"; | ||
| 175 | status = "disabled"; | ||
| 176 | device_type = "pci"; | ||
| 177 | |||
| 178 | #address-cells = <3>; | ||
| 179 | #size-cells = <2>; | ||
| 180 | |||
| 181 | bus-range = <0x00 0xff>; | ||
| 182 | |||
| 183 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 184 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 185 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 186 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 187 | |||
| 188 | pcie@1,0 { | ||
| 189 | device_type = "pci"; | ||
| 190 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 191 | reg = <0x0800 0 0 0 0>; | ||
| 192 | #address-cells = <3>; | ||
| 193 | #size-cells = <2>; | ||
| 194 | #interrupt-cells = <1>; | ||
| 195 | ranges; | ||
| 196 | interrupt-map-mask = <0 0 0 0>; | ||
| 197 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 198 | marvell,pcie-port = <0>; | ||
| 199 | marvell,pcie-lane = <0>; | ||
| 200 | clocks = <&gateclk 5>; | ||
| 201 | status = "disabled"; | ||
| 202 | }; | ||
| 203 | |||
| 204 | pcie@2,0 { | ||
| 205 | device_type = "pci"; | ||
| 206 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 207 | reg = <0x1000 0 0 0 0>; | ||
| 208 | #address-cells = <3>; | ||
| 209 | #size-cells = <2>; | ||
| 210 | #interrupt-cells = <1>; | ||
| 211 | ranges; | ||
| 212 | interrupt-map-mask = <0 0 0 0>; | ||
| 213 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 214 | marvell,pcie-port = <1>; | ||
| 215 | marvell,pcie-lane = <0>; | ||
| 216 | clocks = <&gateclk 9>; | ||
| 217 | status = "disabled"; | ||
| 218 | }; | ||
| 219 | }; | ||
| 220 | }; | 235 | }; |
| 221 | }; | 236 | }; |
| 222 | }; | 237 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts new file mode 100644 index 000000000000..c5fe57269f5a --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts | |||
| @@ -0,0 +1,164 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree file for Marvell RD-AXPWiFiAP. | ||
| 3 | * | ||
| 4 | * Note: this board is shipped with a new generation boot loader that | ||
| 5 | * remaps internal registers at 0xf1000000. Therefore, if earlyprintk | ||
| 6 | * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be | ||
| 7 | * used. | ||
| 8 | * | ||
| 9 | * Copyright (C) 2013 Marvell | ||
| 10 | * | ||
| 11 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | ||
| 12 | * | ||
| 13 | * This file is licensed under the terms of the GNU General Public | ||
| 14 | * License version 2. This program is licensed "as is" without any | ||
| 15 | * warranty of any kind, whether express or implied. | ||
| 16 | */ | ||
| 17 | |||
| 18 | /dts-v1/; | ||
| 19 | #include "armada-xp-mv78230.dtsi" | ||
| 20 | |||
| 21 | / { | ||
| 22 | model = "Marvell RD-AXPWiFiAP"; | ||
| 23 | compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; | ||
| 24 | |||
| 25 | chosen { | ||
| 26 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | memory { | ||
| 30 | device_type = "memory"; | ||
| 31 | reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ | ||
| 32 | }; | ||
| 33 | |||
| 34 | soc { | ||
| 35 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 | ||
| 36 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; | ||
| 37 | |||
| 38 | pcie-controller { | ||
| 39 | status = "okay"; | ||
| 40 | |||
| 41 | /* First mini-PCIe port */ | ||
| 42 | pcie@1,0 { | ||
| 43 | /* Port 0, Lane 0 */ | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* Second mini-PCIe port */ | ||
| 48 | pcie@2,0 { | ||
| 49 | /* Port 0, Lane 1 */ | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* Renesas uPD720202 USB 3.0 controller */ | ||
| 54 | pcie@3,0 { | ||
| 55 | /* Port 0, Lane 3 */ | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | internal-regs { | ||
| 61 | pinctrl { | ||
| 62 | pinctrl-0 = <&pmx_phy_int>; | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | |||
| 65 | pmx_ge0: pmx-ge0 { | ||
| 66 | marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", | ||
| 67 | "mpp4", "mpp5", "mpp6", "mpp7", | ||
| 68 | "mpp8", "mpp9", "mpp10", "mpp11"; | ||
| 69 | marvell,function = "ge0"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | pmx_ge1: pmx-ge1 { | ||
| 73 | marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", | ||
| 74 | "mpp16", "mpp17", "mpp18", "mpp19", | ||
| 75 | "mpp20", "mpp21", "mpp22", "mpp23"; | ||
| 76 | marvell,function = "ge1"; | ||
| 77 | }; | ||
| 78 | |||
| 79 | pmx_keys: pmx-keys { | ||
| 80 | marvell,pins = "mpp33"; | ||
| 81 | marvell,function = "gpio"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | pmx_spi: pmx-spi { | ||
| 85 | marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; | ||
| 86 | marvell,function = "spi"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | pmx_phy_int: pmx-phy-int { | ||
| 90 | marvell,pins = "mpp32"; | ||
| 91 | marvell,function = "gpio"; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | |||
| 95 | serial@12000 { | ||
| 96 | clock-frequency = <250000000>; | ||
| 97 | status = "okay"; | ||
| 98 | }; | ||
| 99 | |||
| 100 | serial@12100 { | ||
| 101 | clock-frequency = <250000000>; | ||
| 102 | status = "okay"; | ||
| 103 | }; | ||
| 104 | |||
| 105 | sata@a0000 { | ||
| 106 | nr-ports = <1>; | ||
| 107 | status = "okay"; | ||
| 108 | }; | ||
| 109 | |||
| 110 | mdio { | ||
| 111 | phy0: ethernet-phy@0 { | ||
| 112 | reg = <0>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | phy1: ethernet-phy@1 { | ||
| 116 | reg = <1>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | ethernet@70000 { | ||
| 121 | pinctrl-0 = <&pmx_ge0>; | ||
| 122 | pinctrl-names = "default"; | ||
| 123 | status = "okay"; | ||
| 124 | phy = <&phy0>; | ||
| 125 | phy-mode = "rgmii-id"; | ||
| 126 | }; | ||
| 127 | ethernet@74000 { | ||
| 128 | pinctrl-0 = <&pmx_ge1>; | ||
| 129 | pinctrl-names = "default"; | ||
| 130 | status = "okay"; | ||
| 131 | phy = <&phy1>; | ||
| 132 | phy-mode = "rgmii-id"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | spi0: spi@10600 { | ||
| 136 | status = "okay"; | ||
| 137 | pinctrl-0 = <&pmx_spi>; | ||
| 138 | pinctrl-names = "default"; | ||
| 139 | |||
| 140 | spi-flash@0 { | ||
| 141 | #address-cells = <1>; | ||
| 142 | #size-cells = <1>; | ||
| 143 | compatible = "n25q128a13"; | ||
| 144 | reg = <0>; /* Chip select 0 */ | ||
| 145 | spi-max-frequency = <108000000>; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | |||
| 151 | gpio_keys { | ||
| 152 | compatible = "gpio-keys"; | ||
| 153 | #address-cells = <1>; | ||
| 154 | #size-cells = <0>; | ||
| 155 | pinctrl-0 = <&pmx_keys>; | ||
| 156 | pinctrl-names = "default"; | ||
| 157 | |||
| 158 | button@1 { | ||
| 159 | label = "Factory Reset Button"; | ||
| 160 | linux,code = <141>; /* KEY_SETUP */ | ||
| 161 | gpios = <&gpio1 1 1>; | ||
| 162 | }; | ||
| 163 | }; | ||
| 164 | }; | ||
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e28e68ff864d..bcf6d79a57ec 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /dts-v1/; | 16 | /dts-v1/; |
| 17 | /include/ "armada-xp-mv78460.dtsi" | 17 | #include "armada-xp-mv78460.dtsi" |
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "Marvell Armada XP Evaluation Board"; | 20 | model = "Marvell Armada XP Evaluation Board"; |
| @@ -30,9 +30,70 @@ | |||
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | soc { | 32 | soc { |
| 33 | ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ | 33 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 |
| 34 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ | 34 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 35 | 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ | 35 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; |
| 36 | |||
| 37 | devbus-bootcs { | ||
| 38 | status = "okay"; | ||
| 39 | |||
| 40 | /* Device Bus parameters are required */ | ||
| 41 | |||
| 42 | /* Read parameters */ | ||
| 43 | devbus,bus-width = <8>; | ||
| 44 | devbus,turn-off-ps = <60000>; | ||
| 45 | devbus,badr-skew-ps = <0>; | ||
| 46 | devbus,acc-first-ps = <124000>; | ||
| 47 | devbus,acc-next-ps = <248000>; | ||
| 48 | devbus,rd-setup-ps = <0>; | ||
| 49 | devbus,rd-hold-ps = <0>; | ||
| 50 | |||
| 51 | /* Write parameters */ | ||
| 52 | devbus,sync-enable = <0>; | ||
| 53 | devbus,wr-high-ps = <60000>; | ||
| 54 | devbus,wr-low-ps = <60000>; | ||
| 55 | devbus,ale-wr-ps = <60000>; | ||
| 56 | |||
| 57 | /* NOR 16 MiB */ | ||
| 58 | nor@0 { | ||
| 59 | compatible = "cfi-flash"; | ||
| 60 | reg = <0 0x1000000>; | ||
| 61 | bank-width = <2>; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | pcie-controller { | ||
| 66 | status = "okay"; | ||
| 67 | |||
| 68 | /* | ||
| 69 | * All 6 slots are physically present as | ||
| 70 | * standard PCIe slots on the board. | ||
| 71 | */ | ||
| 72 | pcie@1,0 { | ||
| 73 | /* Port 0, Lane 0 */ | ||
| 74 | status = "okay"; | ||
| 75 | }; | ||
| 76 | pcie@2,0 { | ||
| 77 | /* Port 0, Lane 1 */ | ||
| 78 | status = "okay"; | ||
| 79 | }; | ||
| 80 | pcie@3,0 { | ||
| 81 | /* Port 0, Lane 2 */ | ||
| 82 | status = "okay"; | ||
| 83 | }; | ||
| 84 | pcie@4,0 { | ||
| 85 | /* Port 0, Lane 3 */ | ||
| 86 | status = "okay"; | ||
| 87 | }; | ||
| 88 | pcie@9,0 { | ||
| 89 | /* Port 2, Lane 0 */ | ||
| 90 | status = "okay"; | ||
| 91 | }; | ||
| 92 | pcie@10,0 { | ||
| 93 | /* Port 3, Lane 0 */ | ||
| 94 | status = "okay"; | ||
| 95 | }; | ||
| 96 | }; | ||
| 36 | 97 | ||
| 37 | internal-regs { | 98 | internal-regs { |
| 38 | serial@12000 { | 99 | serial@12000 { |
| @@ -127,68 +188,6 @@ | |||
| 127 | spi-max-frequency = <20000000>; | 188 | spi-max-frequency = <20000000>; |
| 128 | }; | 189 | }; |
| 129 | }; | 190 | }; |
| 130 | |||
| 131 | pcie-controller { | ||
| 132 | status = "okay"; | ||
| 133 | |||
| 134 | /* | ||
| 135 | * All 6 slots are physically present as | ||
| 136 | * standard PCIe slots on the board. | ||
| 137 | */ | ||
| 138 | pcie@1,0 { | ||
| 139 | /* Port 0, Lane 0 */ | ||
| 140 | status = "okay"; | ||
| 141 | }; | ||
| 142 | pcie@2,0 { | ||
| 143 | /* Port 0, Lane 1 */ | ||
| 144 | status = "okay"; | ||
| 145 | }; | ||
| 146 | pcie@3,0 { | ||
| 147 | /* Port 0, Lane 2 */ | ||
| 148 | status = "okay"; | ||
| 149 | }; | ||
| 150 | pcie@4,0 { | ||
| 151 | /* Port 0, Lane 3 */ | ||
| 152 | status = "okay"; | ||
| 153 | }; | ||
| 154 | pcie@9,0 { | ||
| 155 | /* Port 2, Lane 0 */ | ||
| 156 | status = "okay"; | ||
| 157 | }; | ||
| 158 | pcie@10,0 { | ||
| 159 | /* Port 3, Lane 0 */ | ||
| 160 | status = "okay"; | ||
| 161 | }; | ||
| 162 | }; | ||
| 163 | |||
| 164 | devbus-bootcs@10400 { | ||
| 165 | status = "okay"; | ||
| 166 | ranges = <0 0xf0000000 0x1000000>; | ||
| 167 | |||
| 168 | /* Device Bus parameters are required */ | ||
| 169 | |||
| 170 | /* Read parameters */ | ||
| 171 | devbus,bus-width = <8>; | ||
| 172 | devbus,turn-off-ps = <60000>; | ||
| 173 | devbus,badr-skew-ps = <0>; | ||
| 174 | devbus,acc-first-ps = <124000>; | ||
| 175 | devbus,acc-next-ps = <248000>; | ||
| 176 | devbus,rd-setup-ps = <0>; | ||
| 177 | devbus,rd-hold-ps = <0>; | ||
| 178 | |||
| 179 | /* Write parameters */ | ||
| 180 | devbus,sync-enable = <0>; | ||
| 181 | devbus,wr-high-ps = <60000>; | ||
| 182 | devbus,wr-low-ps = <60000>; | ||
| 183 | devbus,ale-wr-ps = <60000>; | ||
| 184 | |||
| 185 | /* NOR 16 MiB */ | ||
| 186 | nor@0 { | ||
| 187 | compatible = "cfi-flash"; | ||
| 188 | reg = <0 0x1000000>; | ||
| 189 | bank-width = <2>; | ||
| 190 | }; | ||
| 191 | }; | ||
| 192 | }; | 191 | }; |
| 193 | }; | 192 | }; |
| 194 | }; | 193 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index c87b2de29c30..2298e4a910e2 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /dts-v1/; | 16 | /dts-v1/; |
| 17 | /include/ "armada-xp-mv78460.dtsi" | 17 | #include "armada-xp-mv78460.dtsi" |
| 18 | 18 | ||
| 19 | / { | 19 | / { |
| 20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; | 20 | model = "Marvell Armada XP Development Board DB-MV784MP-GP"; |
| @@ -39,9 +39,58 @@ | |||
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | soc { | 41 | soc { |
| 42 | ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ | 42 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 |
| 43 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ | 43 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 44 | 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; | 44 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; |
| 45 | |||
| 46 | devbus-bootcs { | ||
| 47 | status = "okay"; | ||
| 48 | |||
| 49 | /* Device Bus parameters are required */ | ||
| 50 | |||
| 51 | /* Read parameters */ | ||
| 52 | devbus,bus-width = <8>; | ||
| 53 | devbus,turn-off-ps = <60000>; | ||
| 54 | devbus,badr-skew-ps = <0>; | ||
| 55 | devbus,acc-first-ps = <124000>; | ||
| 56 | devbus,acc-next-ps = <248000>; | ||
| 57 | devbus,rd-setup-ps = <0>; | ||
| 58 | devbus,rd-hold-ps = <0>; | ||
| 59 | |||
| 60 | /* Write parameters */ | ||
| 61 | devbus,sync-enable = <0>; | ||
| 62 | devbus,wr-high-ps = <60000>; | ||
| 63 | devbus,wr-low-ps = <60000>; | ||
| 64 | devbus,ale-wr-ps = <60000>; | ||
| 65 | |||
| 66 | /* NOR 16 MiB */ | ||
| 67 | nor@0 { | ||
| 68 | compatible = "cfi-flash"; | ||
| 69 | reg = <0 0x1000000>; | ||
| 70 | bank-width = <2>; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | pcie-controller { | ||
| 75 | status = "okay"; | ||
| 76 | |||
| 77 | /* | ||
| 78 | * The 3 slots are physically present as | ||
| 79 | * standard PCIe slots on the board. | ||
| 80 | */ | ||
| 81 | pcie@1,0 { | ||
| 82 | /* Port 0, Lane 0 */ | ||
| 83 | status = "okay"; | ||
| 84 | }; | ||
| 85 | pcie@9,0 { | ||
| 86 | /* Port 2, Lane 0 */ | ||
| 87 | status = "okay"; | ||
| 88 | }; | ||
| 89 | pcie@10,0 { | ||
| 90 | /* Port 3, Lane 0 */ | ||
| 91 | status = "okay"; | ||
| 92 | }; | ||
| 93 | }; | ||
| 45 | 94 | ||
| 46 | internal-regs { | 95 | internal-regs { |
| 47 | serial@12000 { | 96 | serial@12000 { |
| @@ -126,56 +175,6 @@ | |||
| 126 | spi-max-frequency = <108000000>; | 175 | spi-max-frequency = <108000000>; |
| 127 | }; | 176 | }; |
| 128 | }; | 177 | }; |
| 129 | |||
| 130 | devbus-bootcs@10400 { | ||
| 131 | status = "okay"; | ||
| 132 | ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ | ||
| 133 | |||
| 134 | /* Device Bus parameters are required */ | ||
| 135 | |||
| 136 | /* Read parameters */ | ||
| 137 | devbus,bus-width = <8>; | ||
| 138 | devbus,turn-off-ps = <60000>; | ||
| 139 | devbus,badr-skew-ps = <0>; | ||
| 140 | devbus,acc-first-ps = <124000>; | ||
| 141 | devbus,acc-next-ps = <248000>; | ||
| 142 | devbus,rd-setup-ps = <0>; | ||
| 143 | devbus,rd-hold-ps = <0>; | ||
| 144 | |||
| 145 | /* Write parameters */ | ||
| 146 | devbus,sync-enable = <0>; | ||
| 147 | devbus,wr-high-ps = <60000>; | ||
| 148 | devbus,wr-low-ps = <60000>; | ||
| 149 | devbus,ale-wr-ps = <60000>; | ||
| 150 | |||
| 151 | /* NOR 16 MiB */ | ||
| 152 | nor@0 { | ||
| 153 | compatible = "cfi-flash"; | ||
| 154 | reg = <0 0x1000000>; | ||
| 155 | bank-width = <2>; | ||
| 156 | }; | ||
| 157 | }; | ||
| 158 | |||
| 159 | pcie-controller { | ||
| 160 | status = "okay"; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * The 3 slots are physically present as | ||
| 164 | * standard PCIe slots on the board. | ||
| 165 | */ | ||
| 166 | pcie@1,0 { | ||
| 167 | /* Port 0, Lane 0 */ | ||
| 168 | status = "okay"; | ||
| 169 | }; | ||
| 170 | pcie@9,0 { | ||
| 171 | /* Port 2, Lane 0 */ | ||
| 172 | status = "okay"; | ||
| 173 | }; | ||
| 174 | pcie@10,0 { | ||
| 175 | /* Port 3, Lane 0 */ | ||
| 176 | status = "okay"; | ||
| 177 | }; | ||
| 178 | }; | ||
| 179 | }; | 178 | }; |
| 180 | }; | 179 | }; |
| 181 | }; | 180 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f8eaa383e07f..0358a33cba48 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | * common to all Armada XP SoCs. | 13 | * common to all Armada XP SoCs. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /include/ "armada-xp.dtsi" | 16 | #include "armada-xp.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "Marvell Armada XP MV78230 SoC"; | 19 | model = "Marvell Armada XP MV78230 SoC"; |
| @@ -44,6 +44,124 @@ | |||
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | soc { | 46 | soc { |
| 47 | /* | ||
| 48 | * MV78230 has 2 PCIe units Gen2.0: One unit can be | ||
| 49 | * configured as x4 or quad x1 lanes. One unit is | ||
| 50 | * x4/x1. | ||
| 51 | */ | ||
| 52 | pcie-controller { | ||
| 53 | compatible = "marvell,armada-xp-pcie"; | ||
| 54 | status = "disabled"; | ||
| 55 | device_type = "pci"; | ||
| 56 | |||
| 57 | #address-cells = <3>; | ||
| 58 | #size-cells = <2>; | ||
| 59 | |||
| 60 | bus-range = <0x00 0xff>; | ||
| 61 | |||
| 62 | ranges = | ||
| 63 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 64 | 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 65 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 66 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 67 | 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 68 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 69 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 70 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ | ||
| 71 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ | ||
| 72 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ | ||
| 73 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ | ||
| 74 | 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ | ||
| 75 | 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ | ||
| 76 | 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ | ||
| 77 | 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; | ||
| 78 | |||
| 79 | pcie@1,0 { | ||
| 80 | device_type = "pci"; | ||
| 81 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 82 | reg = <0x0800 0 0 0 0>; | ||
| 83 | #address-cells = <3>; | ||
| 84 | #size-cells = <2>; | ||
| 85 | #interrupt-cells = <1>; | ||
| 86 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 87 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 88 | interrupt-map-mask = <0 0 0 0>; | ||
| 89 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 90 | marvell,pcie-port = <0>; | ||
| 91 | marvell,pcie-lane = <0>; | ||
| 92 | clocks = <&gateclk 5>; | ||
| 93 | status = "disabled"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | pcie@2,0 { | ||
| 97 | device_type = "pci"; | ||
| 98 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 99 | reg = <0x1000 0 0 0 0>; | ||
| 100 | #address-cells = <3>; | ||
| 101 | #size-cells = <2>; | ||
| 102 | #interrupt-cells = <1>; | ||
| 103 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 104 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 105 | interrupt-map-mask = <0 0 0 0>; | ||
| 106 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 107 | marvell,pcie-port = <0>; | ||
| 108 | marvell,pcie-lane = <1>; | ||
| 109 | clocks = <&gateclk 6>; | ||
| 110 | status = "disabled"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | pcie@3,0 { | ||
| 114 | device_type = "pci"; | ||
| 115 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 116 | reg = <0x1800 0 0 0 0>; | ||
| 117 | #address-cells = <3>; | ||
| 118 | #size-cells = <2>; | ||
| 119 | #interrupt-cells = <1>; | ||
| 120 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||
| 121 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||
| 122 | interrupt-map-mask = <0 0 0 0>; | ||
| 123 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 124 | marvell,pcie-port = <0>; | ||
| 125 | marvell,pcie-lane = <2>; | ||
| 126 | clocks = <&gateclk 7>; | ||
| 127 | status = "disabled"; | ||
| 128 | }; | ||
| 129 | |||
| 130 | pcie@4,0 { | ||
| 131 | device_type = "pci"; | ||
| 132 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 133 | reg = <0x2000 0 0 0 0>; | ||
| 134 | #address-cells = <3>; | ||
| 135 | #size-cells = <2>; | ||
| 136 | #interrupt-cells = <1>; | ||
| 137 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | ||
| 138 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | ||
| 139 | interrupt-map-mask = <0 0 0 0>; | ||
| 140 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 141 | marvell,pcie-port = <0>; | ||
| 142 | marvell,pcie-lane = <3>; | ||
| 143 | clocks = <&gateclk 8>; | ||
| 144 | status = "disabled"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | pcie@9,0 { | ||
| 148 | device_type = "pci"; | ||
| 149 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 150 | reg = <0x4800 0 0 0 0>; | ||
| 151 | #address-cells = <3>; | ||
| 152 | #size-cells = <2>; | ||
| 153 | #interrupt-cells = <1>; | ||
| 154 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | ||
| 155 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | ||
| 156 | interrupt-map-mask = <0 0 0 0>; | ||
| 157 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 158 | marvell,pcie-port = <2>; | ||
| 159 | marvell,pcie-lane = <0>; | ||
| 160 | clocks = <&gateclk 26>; | ||
| 161 | status = "disabled"; | ||
| 162 | }; | ||
| 163 | }; | ||
| 164 | |||
| 47 | internal-regs { | 165 | internal-regs { |
| 48 | pinctrl { | 166 | pinctrl { |
| 49 | compatible = "marvell,mv78230-pinctrl"; | 167 | compatible = "marvell,mv78230-pinctrl"; |
| @@ -63,7 +181,7 @@ | |||
| 63 | gpio-controller; | 181 | gpio-controller; |
| 64 | #gpio-cells = <2>; | 182 | #gpio-cells = <2>; |
| 65 | interrupt-controller; | 183 | interrupt-controller; |
| 66 | #interrupts-cells = <2>; | 184 | #interrupt-cells = <2>; |
| 67 | interrupts = <82>, <83>, <84>, <85>; | 185 | interrupts = <82>, <83>, <84>, <85>; |
| 68 | }; | 186 | }; |
| 69 | 187 | ||
| @@ -74,113 +192,9 @@ | |||
| 74 | gpio-controller; | 192 | gpio-controller; |
| 75 | #gpio-cells = <2>; | 193 | #gpio-cells = <2>; |
| 76 | interrupt-controller; | 194 | interrupt-controller; |
| 77 | #interrupts-cells = <2>; | 195 | #interrupt-cells = <2>; |
| 78 | interrupts = <87>, <88>, <89>; | 196 | interrupts = <87>, <88>, <89>; |
| 79 | }; | 197 | }; |
| 80 | |||
| 81 | /* | ||
| 82 | * MV78230 has 2 PCIe units Gen2.0: One unit can be | ||
| 83 | * configured as x4 or quad x1 lanes. One unit is | ||
| 84 | * x4/x1. | ||
| 85 | */ | ||
| 86 | pcie-controller { | ||
| 87 | compatible = "marvell,armada-xp-pcie"; | ||
| 88 | status = "disabled"; | ||
| 89 | device_type = "pci"; | ||
| 90 | |||
| 91 | #address-cells = <3>; | ||
| 92 | #size-cells = <2>; | ||
| 93 | |||
| 94 | bus-range = <0x00 0xff>; | ||
| 95 | |||
| 96 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 97 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 98 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 99 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 100 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 101 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 102 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 103 | |||
| 104 | pcie@1,0 { | ||
| 105 | device_type = "pci"; | ||
| 106 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 107 | reg = <0x0800 0 0 0 0>; | ||
| 108 | #address-cells = <3>; | ||
| 109 | #size-cells = <2>; | ||
| 110 | #interrupt-cells = <1>; | ||
| 111 | ranges; | ||
| 112 | interrupt-map-mask = <0 0 0 0>; | ||
| 113 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 114 | marvell,pcie-port = <0>; | ||
| 115 | marvell,pcie-lane = <0>; | ||
| 116 | clocks = <&gateclk 5>; | ||
| 117 | status = "disabled"; | ||
| 118 | }; | ||
| 119 | |||
| 120 | pcie@2,0 { | ||
| 121 | device_type = "pci"; | ||
| 122 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 123 | reg = <0x1000 0 0 0 0>; | ||
| 124 | #address-cells = <3>; | ||
| 125 | #size-cells = <2>; | ||
| 126 | #interrupt-cells = <1>; | ||
| 127 | ranges; | ||
| 128 | interrupt-map-mask = <0 0 0 0>; | ||
| 129 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 130 | marvell,pcie-port = <0>; | ||
| 131 | marvell,pcie-lane = <1>; | ||
| 132 | clocks = <&gateclk 6>; | ||
| 133 | status = "disabled"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | pcie@3,0 { | ||
| 137 | device_type = "pci"; | ||
| 138 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 139 | reg = <0x1800 0 0 0 0>; | ||
| 140 | #address-cells = <3>; | ||
| 141 | #size-cells = <2>; | ||
| 142 | #interrupt-cells = <1>; | ||
| 143 | ranges; | ||
| 144 | interrupt-map-mask = <0 0 0 0>; | ||
| 145 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 146 | marvell,pcie-port = <0>; | ||
| 147 | marvell,pcie-lane = <2>; | ||
| 148 | clocks = <&gateclk 7>; | ||
| 149 | status = "disabled"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pcie@4,0 { | ||
| 153 | device_type = "pci"; | ||
| 154 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 155 | reg = <0x2000 0 0 0 0>; | ||
| 156 | #address-cells = <3>; | ||
| 157 | #size-cells = <2>; | ||
| 158 | #interrupt-cells = <1>; | ||
| 159 | ranges; | ||
| 160 | interrupt-map-mask = <0 0 0 0>; | ||
| 161 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 162 | marvell,pcie-port = <0>; | ||
| 163 | marvell,pcie-lane = <3>; | ||
| 164 | clocks = <&gateclk 8>; | ||
| 165 | status = "disabled"; | ||
| 166 | }; | ||
| 167 | |||
| 168 | pcie@9,0 { | ||
| 169 | device_type = "pci"; | ||
| 170 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 171 | reg = <0x4800 0 0 0 0>; | ||
| 172 | #address-cells = <3>; | ||
| 173 | #size-cells = <2>; | ||
| 174 | #interrupt-cells = <1>; | ||
| 175 | ranges; | ||
| 176 | interrupt-map-mask = <0 0 0 0>; | ||
| 177 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 178 | marvell,pcie-port = <2>; | ||
| 179 | marvell,pcie-lane = <0>; | ||
| 180 | clocks = <&gateclk 26>; | ||
| 181 | status = "disabled"; | ||
| 182 | }; | ||
| 183 | }; | ||
| 184 | }; | 198 | }; |
| 185 | }; | 199 | }; |
| 186 | }; | 200 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 2d9335da210c..0e82c5062243 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | * common to all Armada XP SoCs. | 13 | * common to all Armada XP SoCs. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /include/ "armada-xp.dtsi" | 16 | #include "armada-xp.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "Marvell Armada XP MV78260 SoC"; | 19 | model = "Marvell Armada XP MV78260 SoC"; |
| @@ -45,6 +45,145 @@ | |||
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | soc { | 47 | soc { |
| 48 | /* | ||
| 49 | * MV78260 has 3 PCIe units Gen2.0: Two units can be | ||
| 50 | * configured as x4 or quad x1 lanes. One unit is | ||
| 51 | * x4/x1. | ||
| 52 | */ | ||
| 53 | pcie-controller { | ||
| 54 | compatible = "marvell,armada-xp-pcie"; | ||
| 55 | status = "disabled"; | ||
| 56 | device_type = "pci"; | ||
| 57 | |||
| 58 | #address-cells = <3>; | ||
| 59 | #size-cells = <2>; | ||
| 60 | |||
| 61 | bus-range = <0x00 0xff>; | ||
| 62 | |||
| 63 | ranges = | ||
| 64 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 65 | 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 66 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 67 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 68 | 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 69 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 70 | 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 71 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 72 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 73 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ | ||
| 74 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ | ||
| 75 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ | ||
| 76 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ | ||
| 77 | 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ | ||
| 78 | 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ | ||
| 79 | 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | ||
| 80 | 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ | ||
| 81 | 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ | ||
| 82 | 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; | ||
| 83 | |||
| 84 | pcie@1,0 { | ||
| 85 | device_type = "pci"; | ||
| 86 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 87 | reg = <0x0800 0 0 0 0>; | ||
| 88 | #address-cells = <3>; | ||
| 89 | #size-cells = <2>; | ||
| 90 | #interrupt-cells = <1>; | ||
| 91 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 92 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 93 | interrupt-map-mask = <0 0 0 0>; | ||
| 94 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 95 | marvell,pcie-port = <0>; | ||
| 96 | marvell,pcie-lane = <0>; | ||
| 97 | clocks = <&gateclk 5>; | ||
| 98 | status = "disabled"; | ||
| 99 | }; | ||
| 100 | |||
| 101 | pcie@2,0 { | ||
| 102 | device_type = "pci"; | ||
| 103 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 104 | reg = <0x1000 0 0 0 0>; | ||
| 105 | #address-cells = <3>; | ||
| 106 | #size-cells = <2>; | ||
| 107 | #interrupt-cells = <1>; | ||
| 108 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 109 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 110 | interrupt-map-mask = <0 0 0 0>; | ||
| 111 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 112 | marvell,pcie-port = <0>; | ||
| 113 | marvell,pcie-lane = <1>; | ||
| 114 | clocks = <&gateclk 6>; | ||
| 115 | status = "disabled"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | pcie@3,0 { | ||
| 119 | device_type = "pci"; | ||
| 120 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 121 | reg = <0x1800 0 0 0 0>; | ||
| 122 | #address-cells = <3>; | ||
| 123 | #size-cells = <2>; | ||
| 124 | #interrupt-cells = <1>; | ||
| 125 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||
| 126 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||
| 127 | interrupt-map-mask = <0 0 0 0>; | ||
| 128 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 129 | marvell,pcie-port = <0>; | ||
| 130 | marvell,pcie-lane = <2>; | ||
| 131 | clocks = <&gateclk 7>; | ||
| 132 | status = "disabled"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | pcie@4,0 { | ||
| 136 | device_type = "pci"; | ||
| 137 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 138 | reg = <0x2000 0 0 0 0>; | ||
| 139 | #address-cells = <3>; | ||
| 140 | #size-cells = <2>; | ||
| 141 | #interrupt-cells = <1>; | ||
| 142 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | ||
| 143 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | ||
| 144 | interrupt-map-mask = <0 0 0 0>; | ||
| 145 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 146 | marvell,pcie-port = <0>; | ||
| 147 | marvell,pcie-lane = <3>; | ||
| 148 | clocks = <&gateclk 8>; | ||
| 149 | status = "disabled"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pcie@9,0 { | ||
| 153 | device_type = "pci"; | ||
| 154 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 155 | reg = <0x4800 0 0 0 0>; | ||
| 156 | #address-cells = <3>; | ||
| 157 | #size-cells = <2>; | ||
| 158 | #interrupt-cells = <1>; | ||
| 159 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | ||
| 160 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | ||
| 161 | interrupt-map-mask = <0 0 0 0>; | ||
| 162 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 163 | marvell,pcie-port = <2>; | ||
| 164 | marvell,pcie-lane = <0>; | ||
| 165 | clocks = <&gateclk 26>; | ||
| 166 | status = "disabled"; | ||
| 167 | }; | ||
| 168 | |||
| 169 | pcie@10,0 { | ||
| 170 | device_type = "pci"; | ||
| 171 | assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; | ||
| 172 | reg = <0x5000 0 0 0 0>; | ||
| 173 | #address-cells = <3>; | ||
| 174 | #size-cells = <2>; | ||
| 175 | #interrupt-cells = <1>; | ||
| 176 | ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 | ||
| 177 | 0x81000000 0 0 0x81000000 0xa 0 1 0>; | ||
| 178 | interrupt-map-mask = <0 0 0 0>; | ||
| 179 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 180 | marvell,pcie-port = <3>; | ||
| 181 | marvell,pcie-lane = <0>; | ||
| 182 | clocks = <&gateclk 27>; | ||
| 183 | status = "disabled"; | ||
| 184 | }; | ||
| 185 | }; | ||
| 186 | |||
| 48 | internal-regs { | 187 | internal-regs { |
| 49 | pinctrl { | 188 | pinctrl { |
| 50 | compatible = "marvell,mv78260-pinctrl"; | 189 | compatible = "marvell,mv78260-pinctrl"; |
| @@ -64,7 +203,7 @@ | |||
| 64 | gpio-controller; | 203 | gpio-controller; |
| 65 | #gpio-cells = <2>; | 204 | #gpio-cells = <2>; |
| 66 | interrupt-controller; | 205 | interrupt-controller; |
| 67 | #interrupts-cells = <2>; | 206 | #interrupt-cells = <2>; |
| 68 | interrupts = <82>, <83>, <84>, <85>; | 207 | interrupts = <82>, <83>, <84>, <85>; |
| 69 | }; | 208 | }; |
| 70 | 209 | ||
| @@ -75,7 +214,7 @@ | |||
| 75 | gpio-controller; | 214 | gpio-controller; |
| 76 | #gpio-cells = <2>; | 215 | #gpio-cells = <2>; |
| 77 | interrupt-controller; | 216 | interrupt-controller; |
| 78 | #interrupts-cells = <2>; | 217 | #interrupt-cells = <2>; |
| 79 | interrupts = <87>, <88>, <89>, <90>; | 218 | interrupts = <87>, <88>, <89>, <90>; |
| 80 | }; | 219 | }; |
| 81 | 220 | ||
| @@ -86,7 +225,7 @@ | |||
| 86 | gpio-controller; | 225 | gpio-controller; |
| 87 | #gpio-cells = <2>; | 226 | #gpio-cells = <2>; |
| 88 | interrupt-controller; | 227 | interrupt-controller; |
| 89 | #interrupts-cells = <2>; | 228 | #interrupt-cells = <2>; |
| 90 | interrupts = <91>; | 229 | interrupts = <91>; |
| 91 | }; | 230 | }; |
| 92 | 231 | ||
| @@ -97,128 +236,6 @@ | |||
| 97 | clocks = <&gateclk 1>; | 236 | clocks = <&gateclk 1>; |
| 98 | status = "disabled"; | 237 | status = "disabled"; |
| 99 | }; | 238 | }; |
| 100 | |||
| 101 | /* | ||
| 102 | * MV78260 has 3 PCIe units Gen2.0: Two units can be | ||
| 103 | * configured as x4 or quad x1 lanes. One unit is | ||
| 104 | * x4/x1. | ||
| 105 | */ | ||
| 106 | pcie-controller { | ||
| 107 | compatible = "marvell,armada-xp-pcie"; | ||
| 108 | status = "disabled"; | ||
| 109 | device_type = "pci"; | ||
| 110 | |||
| 111 | #address-cells = <3>; | ||
| 112 | #size-cells = <2>; | ||
| 113 | |||
| 114 | bus-range = <0x00 0xff>; | ||
| 115 | |||
| 116 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 117 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 118 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 119 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 120 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 121 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 122 | 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 123 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 124 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 125 | |||
| 126 | pcie@1,0 { | ||
| 127 | device_type = "pci"; | ||
| 128 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 129 | reg = <0x0800 0 0 0 0>; | ||
| 130 | #address-cells = <3>; | ||
| 131 | #size-cells = <2>; | ||
| 132 | #interrupt-cells = <1>; | ||
| 133 | ranges; | ||
| 134 | interrupt-map-mask = <0 0 0 0>; | ||
| 135 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 136 | marvell,pcie-port = <0>; | ||
| 137 | marvell,pcie-lane = <0>; | ||
| 138 | clocks = <&gateclk 5>; | ||
| 139 | status = "disabled"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pcie@2,0 { | ||
| 143 | device_type = "pci"; | ||
| 144 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||
| 145 | reg = <0x1000 0 0 0 0>; | ||
| 146 | #address-cells = <3>; | ||
| 147 | #size-cells = <2>; | ||
| 148 | #interrupt-cells = <1>; | ||
| 149 | ranges; | ||
| 150 | interrupt-map-mask = <0 0 0 0>; | ||
| 151 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 152 | marvell,pcie-port = <0>; | ||
| 153 | marvell,pcie-lane = <1>; | ||
| 154 | clocks = <&gateclk 6>; | ||
| 155 | status = "disabled"; | ||
| 156 | }; | ||
| 157 | |||
| 158 | pcie@3,0 { | ||
| 159 | device_type = "pci"; | ||
| 160 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||
| 161 | reg = <0x1800 0 0 0 0>; | ||
| 162 | #address-cells = <3>; | ||
| 163 | #size-cells = <2>; | ||
| 164 | #interrupt-cells = <1>; | ||
| 165 | ranges; | ||
| 166 | interrupt-map-mask = <0 0 0 0>; | ||
| 167 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 168 | marvell,pcie-port = <0>; | ||
| 169 | marvell,pcie-lane = <2>; | ||
| 170 | clocks = <&gateclk 7>; | ||
| 171 | status = "disabled"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | pcie@4,0 { | ||
| 175 | device_type = "pci"; | ||
| 176 | assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; | ||
| 177 | reg = <0x2000 0 0 0 0>; | ||
| 178 | #address-cells = <3>; | ||
| 179 | #size-cells = <2>; | ||
| 180 | #interrupt-cells = <1>; | ||
| 181 | ranges; | ||
| 182 | interrupt-map-mask = <0 0 0 0>; | ||
| 183 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 184 | marvell,pcie-port = <0>; | ||
| 185 | marvell,pcie-lane = <3>; | ||
| 186 | clocks = <&gateclk 8>; | ||
| 187 | status = "disabled"; | ||
| 188 | }; | ||
| 189 | |||
| 190 | pcie@9,0 { | ||
| 191 | device_type = "pci"; | ||
| 192 | assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; | ||
| 193 | reg = <0x4800 0 0 0 0>; | ||
| 194 | #address-cells = <3>; | ||
| 195 | #size-cells = <2>; | ||
| 196 | #interrupt-cells = <1>; | ||
| 197 | ranges; | ||
| 198 | interrupt-map-mask = <0 0 0 0>; | ||
| 199 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 200 | marvell,pcie-port = <2>; | ||
| 201 | marvell,pcie-lane = <0>; | ||
| 202 | clocks = <&gateclk 26>; | ||
| 203 | status = "disabled"; | ||
| 204 | }; | ||
| 205 | |||
| 206 | pcie@10,0 { | ||
| 207 | device_type = "pci"; | ||
| 208 | assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; | ||
| 209 | reg = <0x5000 0 0 0 0>; | ||
| 210 | #address-cells = <3>; | ||
| 211 | #size-cells = <2>; | ||
| 212 | #interrupt-cells = <1>; | ||
| 213 | ranges; | ||
| 214 | interrupt-map-mask = <0 0 0 0>; | ||
| 215 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 216 | marvell,pcie-port = <3>; | ||
| 217 | marvell,pcie-lane = <0>; | ||
| 218 | clocks = <&gateclk 27>; | ||
| 219 | status = "disabled"; | ||
| 220 | }; | ||
| 221 | }; | ||
| 222 | }; | 239 | }; |
| 223 | }; | 240 | }; |
| 224 | }; | 241 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index c7b1f4d5c1c7..e82c1b80af17 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | * common to all Armada XP SoCs. | 13 | * common to all Armada XP SoCs. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /include/ "armada-xp.dtsi" | 16 | #include "armada-xp.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "Marvell Armada XP MV78460 SoC"; | 19 | model = "Marvell Armada XP MV78460 SoC"; |
| @@ -61,6 +61,227 @@ | |||
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | soc { | 63 | soc { |
| 64 | /* | ||
| 65 | * MV78460 has 4 PCIe units Gen2.0: Two units can be | ||
| 66 | * configured as x4 or quad x1 lanes. Two units are | ||
| 67 | * x4/x1. | ||
| 68 | */ | ||
| 69 | pcie-controller { | ||
| 70 | compatible = "marvell,armada-xp-pcie"; | ||
| 71 | status = "disabled"; | ||
| 72 | device_type = "pci"; | ||
| 73 | |||
| 74 | #address-cells = <3>; | ||
| 75 | #size-cells = <2>; | ||
| 76 | |||
| 77 | bus-range = <0x00 0xff>; | ||
| 78 | |||
| 79 | ranges = | ||
| 80 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 81 | 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 82 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 83 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 84 | 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 85 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 86 | 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 87 | 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ | ||
| 88 | 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ | ||
| 89 | 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ | ||
| 90 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 91 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 92 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ | ||
| 93 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ | ||
| 94 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ | ||
| 95 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ | ||
| 96 | 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ | ||
| 97 | 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ | ||
| 98 | |||
| 99 | 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ | ||
| 100 | 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ | ||
| 101 | 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ | ||
| 102 | 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ | ||
| 103 | 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ | ||
| 104 | 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ | ||
| 105 | 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ | ||
| 106 | 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ | ||
| 107 | |||
| 108 | 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ | ||
| 109 | 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ | ||
| 110 | |||
| 111 | 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ | ||
| 112 | 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; | ||
| 113 | |||
| 114 | pcie@1,0 { | ||
| 115 | device_type = "pci"; | ||
| 116 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 117 | reg = <0x0800 0 0 0 0>; | ||
| 118 | #address-cells = <3>; | ||
| 119 | #size-cells = <2>; | ||
| 120 | #interrupt-cells = <1>; | ||
| 121 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 122 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 123 | interrupt-map-mask = <0 0 0 0>; | ||
| 124 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 125 | marvell,pcie-port = <0>; | ||
| 126 | marvell,pcie-lane = <0>; | ||
| 127 | clocks = <&gateclk 5>; | ||
| 128 | status = "disabled"; | ||
| 129 | }; | ||
| 130 | |||
| 131 | pcie@2,0 { | ||
| 132 | device_type = "pci"; | ||
| 133 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; | ||
| 134 | reg = <0x1000 0 0 0 0>; | ||
| 135 | #address-cells = <3>; | ||
| 136 | #size-cells = <2>; | ||
| 137 | #interrupt-cells = <1>; | ||
| 138 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 139 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 140 | interrupt-map-mask = <0 0 0 0>; | ||
| 141 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 142 | marvell,pcie-port = <0>; | ||
| 143 | marvell,pcie-lane = <1>; | ||
| 144 | clocks = <&gateclk 6>; | ||
| 145 | status = "disabled"; | ||
| 146 | }; | ||
| 147 | |||
| 148 | pcie@3,0 { | ||
| 149 | device_type = "pci"; | ||
| 150 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; | ||
| 151 | reg = <0x1800 0 0 0 0>; | ||
| 152 | #address-cells = <3>; | ||
| 153 | #size-cells = <2>; | ||
| 154 | #interrupt-cells = <1>; | ||
| 155 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||
| 156 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||
| 157 | interrupt-map-mask = <0 0 0 0>; | ||
| 158 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 159 | marvell,pcie-port = <0>; | ||
| 160 | marvell,pcie-lane = <2>; | ||
| 161 | clocks = <&gateclk 7>; | ||
| 162 | status = "disabled"; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pcie@4,0 { | ||
| 166 | device_type = "pci"; | ||
| 167 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; | ||
| 168 | reg = <0x2000 0 0 0 0>; | ||
| 169 | #address-cells = <3>; | ||
| 170 | #size-cells = <2>; | ||
| 171 | #interrupt-cells = <1>; | ||
| 172 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | ||
| 173 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | ||
| 174 | interrupt-map-mask = <0 0 0 0>; | ||
| 175 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 176 | marvell,pcie-port = <0>; | ||
| 177 | marvell,pcie-lane = <3>; | ||
| 178 | clocks = <&gateclk 8>; | ||
| 179 | status = "disabled"; | ||
| 180 | }; | ||
| 181 | |||
| 182 | pcie@5,0 { | ||
| 183 | device_type = "pci"; | ||
| 184 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 185 | reg = <0x2800 0 0 0 0>; | ||
| 186 | #address-cells = <3>; | ||
| 187 | #size-cells = <2>; | ||
| 188 | #interrupt-cells = <1>; | ||
| 189 | ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 | ||
| 190 | 0x81000000 0 0 0x81000000 0x5 0 1 0>; | ||
| 191 | interrupt-map-mask = <0 0 0 0>; | ||
| 192 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 193 | marvell,pcie-port = <1>; | ||
| 194 | marvell,pcie-lane = <0>; | ||
| 195 | clocks = <&gateclk 9>; | ||
| 196 | status = "disabled"; | ||
| 197 | }; | ||
| 198 | |||
| 199 | pcie@6,0 { | ||
| 200 | device_type = "pci"; | ||
| 201 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; | ||
| 202 | reg = <0x3000 0 0 0 0>; | ||
| 203 | #address-cells = <3>; | ||
| 204 | #size-cells = <2>; | ||
| 205 | #interrupt-cells = <1>; | ||
| 206 | ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 | ||
| 207 | 0x81000000 0 0 0x81000000 0x6 0 1 0>; | ||
| 208 | interrupt-map-mask = <0 0 0 0>; | ||
| 209 | interrupt-map = <0 0 0 0 &mpic 63>; | ||
| 210 | marvell,pcie-port = <1>; | ||
| 211 | marvell,pcie-lane = <1>; | ||
| 212 | clocks = <&gateclk 10>; | ||
| 213 | status = "disabled"; | ||
| 214 | }; | ||
| 215 | |||
| 216 | pcie@7,0 { | ||
| 217 | device_type = "pci"; | ||
| 218 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; | ||
| 219 | reg = <0x3800 0 0 0 0>; | ||
| 220 | #address-cells = <3>; | ||
| 221 | #size-cells = <2>; | ||
| 222 | #interrupt-cells = <1>; | ||
| 223 | ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 | ||
| 224 | 0x81000000 0 0 0x81000000 0x7 0 1 0>; | ||
| 225 | interrupt-map-mask = <0 0 0 0>; | ||
| 226 | interrupt-map = <0 0 0 0 &mpic 64>; | ||
| 227 | marvell,pcie-port = <1>; | ||
| 228 | marvell,pcie-lane = <2>; | ||
| 229 | clocks = <&gateclk 11>; | ||
| 230 | status = "disabled"; | ||
| 231 | }; | ||
| 232 | |||
| 233 | pcie@8,0 { | ||
| 234 | device_type = "pci"; | ||
| 235 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; | ||
| 236 | reg = <0x4000 0 0 0 0>; | ||
| 237 | #address-cells = <3>; | ||
| 238 | #size-cells = <2>; | ||
| 239 | #interrupt-cells = <1>; | ||
| 240 | ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 | ||
| 241 | 0x81000000 0 0 0x81000000 0x8 0 1 0>; | ||
| 242 | interrupt-map-mask = <0 0 0 0>; | ||
| 243 | interrupt-map = <0 0 0 0 &mpic 65>; | ||
| 244 | marvell,pcie-port = <1>; | ||
| 245 | marvell,pcie-lane = <3>; | ||
| 246 | clocks = <&gateclk 12>; | ||
| 247 | status = "disabled"; | ||
| 248 | }; | ||
| 249 | |||
| 250 | pcie@9,0 { | ||
| 251 | device_type = "pci"; | ||
| 252 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; | ||
| 253 | reg = <0x4800 0 0 0 0>; | ||
| 254 | #address-cells = <3>; | ||
| 255 | #size-cells = <2>; | ||
| 256 | #interrupt-cells = <1>; | ||
| 257 | ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 | ||
| 258 | 0x81000000 0 0 0x81000000 0x9 0 1 0>; | ||
| 259 | interrupt-map-mask = <0 0 0 0>; | ||
| 260 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 261 | marvell,pcie-port = <2>; | ||
| 262 | marvell,pcie-lane = <0>; | ||
| 263 | clocks = <&gateclk 26>; | ||
| 264 | status = "disabled"; | ||
| 265 | }; | ||
| 266 | |||
| 267 | pcie@10,0 { | ||
| 268 | device_type = "pci"; | ||
| 269 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; | ||
| 270 | reg = <0x5000 0 0 0 0>; | ||
| 271 | #address-cells = <3>; | ||
| 272 | #size-cells = <2>; | ||
| 273 | #interrupt-cells = <1>; | ||
| 274 | ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 | ||
| 275 | 0x81000000 0 0 0x81000000 0xa 0 1 0>; | ||
| 276 | interrupt-map-mask = <0 0 0 0>; | ||
| 277 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 278 | marvell,pcie-port = <3>; | ||
| 279 | marvell,pcie-lane = <0>; | ||
| 280 | clocks = <&gateclk 27>; | ||
| 281 | status = "disabled"; | ||
| 282 | }; | ||
| 283 | }; | ||
| 284 | |||
| 64 | internal-regs { | 285 | internal-regs { |
| 65 | pinctrl { | 286 | pinctrl { |
| 66 | compatible = "marvell,mv78460-pinctrl"; | 287 | compatible = "marvell,mv78460-pinctrl"; |
| @@ -80,7 +301,7 @@ | |||
| 80 | gpio-controller; | 301 | gpio-controller; |
| 81 | #gpio-cells = <2>; | 302 | #gpio-cells = <2>; |
| 82 | interrupt-controller; | 303 | interrupt-controller; |
| 83 | #interrupts-cells = <2>; | 304 | #interrupt-cells = <2>; |
| 84 | interrupts = <82>, <83>, <84>, <85>; | 305 | interrupts = <82>, <83>, <84>, <85>; |
| 85 | }; | 306 | }; |
| 86 | 307 | ||
| @@ -91,7 +312,7 @@ | |||
| 91 | gpio-controller; | 312 | gpio-controller; |
| 92 | #gpio-cells = <2>; | 313 | #gpio-cells = <2>; |
| 93 | interrupt-controller; | 314 | interrupt-controller; |
| 94 | #interrupts-cells = <2>; | 315 | #interrupt-cells = <2>; |
| 95 | interrupts = <87>, <88>, <89>, <90>; | 316 | interrupts = <87>, <88>, <89>, <90>; |
| 96 | }; | 317 | }; |
| 97 | 318 | ||
| @@ -102,7 +323,7 @@ | |||
| 102 | gpio-controller; | 323 | gpio-controller; |
| 103 | #gpio-cells = <2>; | 324 | #gpio-cells = <2>; |
| 104 | interrupt-controller; | 325 | interrupt-controller; |
| 105 | #interrupts-cells = <2>; | 326 | #interrupt-cells = <2>; |
| 106 | interrupts = <91>; | 327 | interrupts = <91>; |
| 107 | }; | 328 | }; |
| 108 | 329 | ||
| @@ -113,194 +334,6 @@ | |||
| 113 | clocks = <&gateclk 1>; | 334 | clocks = <&gateclk 1>; |
| 114 | status = "disabled"; | 335 | status = "disabled"; |
| 115 | }; | 336 | }; |
| 116 | |||
| 117 | /* | ||
| 118 | * MV78460 has 4 PCIe units Gen2.0: Two units can be | ||
| 119 | * configured as x4 or quad x1 lanes. Two units are | ||
| 120 | * x4/x1. | ||
| 121 | */ | ||
| 122 | pcie-controller { | ||
| 123 | compatible = "marvell,armada-xp-pcie"; | ||
| 124 | status = "disabled"; | ||
| 125 | device_type = "pci"; | ||
| 126 | |||
| 127 | #address-cells = <3>; | ||
| 128 | #size-cells = <2>; | ||
| 129 | |||
| 130 | bus-range = <0x00 0xff>; | ||
| 131 | |||
| 132 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | ||
| 133 | 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ | ||
| 134 | 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ | ||
| 135 | 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ | ||
| 136 | 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ | ||
| 137 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | ||
| 138 | 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ | ||
| 139 | 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ | ||
| 140 | 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ | ||
| 141 | 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ | ||
| 142 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 143 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 144 | |||
| 145 | pcie@1,0 { | ||
| 146 | device_type = "pci"; | ||
| 147 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||
| 148 | reg = <0x0800 0 0 0 0>; | ||
| 149 | #address-cells = <3>; | ||
| 150 | #size-cells = <2>; | ||
| 151 | #interrupt-cells = <1>; | ||
| 152 | ranges; | ||
| 153 | interrupt-map-mask = <0 0 0 0>; | ||
| 154 | interrupt-map = <0 0 0 0 &mpic 58>; | ||
| 155 | marvell,pcie-port = <0>; | ||
| 156 | marvell,pcie-lane = <0>; | ||
| 157 | clocks = <&gateclk 5>; | ||
| 158 | status = "disabled"; | ||
| 159 | }; | ||
| 160 | |||
| 161 | pcie@2,0 { | ||
| 162 | device_type = "pci"; | ||
| 163 | assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; | ||
| 164 | reg = <0x1000 0 0 0 0>; | ||
| 165 | #address-cells = <3>; | ||
| 166 | #size-cells = <2>; | ||
| 167 | #interrupt-cells = <1>; | ||
| 168 | ranges; | ||
| 169 | interrupt-map-mask = <0 0 0 0>; | ||
| 170 | interrupt-map = <0 0 0 0 &mpic 59>; | ||
| 171 | marvell,pcie-port = <0>; | ||
| 172 | marvell,pcie-lane = <1>; | ||
| 173 | clocks = <&gateclk 6>; | ||
| 174 | status = "disabled"; | ||
| 175 | }; | ||
| 176 | |||
| 177 | pcie@3,0 { | ||
| 178 | device_type = "pci"; | ||
| 179 | assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; | ||
| 180 | reg = <0x1800 0 0 0 0>; | ||
| 181 | #address-cells = <3>; | ||
| 182 | #size-cells = <2>; | ||
| 183 | #interrupt-cells = <1>; | ||
| 184 | ranges; | ||
| 185 | interrupt-map-mask = <0 0 0 0>; | ||
| 186 | interrupt-map = <0 0 0 0 &mpic 60>; | ||
| 187 | marvell,pcie-port = <0>; | ||
| 188 | marvell,pcie-lane = <2>; | ||
| 189 | clocks = <&gateclk 7>; | ||
| 190 | status = "disabled"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | pcie@4,0 { | ||
| 194 | device_type = "pci"; | ||
| 195 | assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; | ||
| 196 | reg = <0x2000 0 0 0 0>; | ||
| 197 | #address-cells = <3>; | ||
| 198 | #size-cells = <2>; | ||
| 199 | #interrupt-cells = <1>; | ||
| 200 | ranges; | ||
| 201 | interrupt-map-mask = <0 0 0 0>; | ||
| 202 | interrupt-map = <0 0 0 0 &mpic 61>; | ||
| 203 | marvell,pcie-port = <0>; | ||
| 204 | marvell,pcie-lane = <3>; | ||
| 205 | clocks = <&gateclk 8>; | ||
| 206 | status = "disabled"; | ||
| 207 | }; | ||
| 208 | |||
| 209 | pcie@5,0 { | ||
| 210 | device_type = "pci"; | ||
| 211 | assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; | ||
| 212 | reg = <0x2800 0 0 0 0>; | ||
| 213 | #address-cells = <3>; | ||
| 214 | #size-cells = <2>; | ||
| 215 | #interrupt-cells = <1>; | ||
| 216 | ranges; | ||
| 217 | interrupt-map-mask = <0 0 0 0>; | ||
| 218 | interrupt-map = <0 0 0 0 &mpic 62>; | ||
| 219 | marvell,pcie-port = <1>; | ||
| 220 | marvell,pcie-lane = <0>; | ||
| 221 | clocks = <&gateclk 9>; | ||
| 222 | status = "disabled"; | ||
| 223 | }; | ||
| 224 | |||
| 225 | pcie@6,0 { | ||
| 226 | device_type = "pci"; | ||
| 227 | assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; | ||
| 228 | reg = <0x3000 0 0 0 0>; | ||
| 229 | #address-cells = <3>; | ||
| 230 | #size-cells = <2>; | ||
| 231 | #interrupt-cells = <1>; | ||
| 232 | ranges; | ||
| 233 | interrupt-map-mask = <0 0 0 0>; | ||
| 234 | interrupt-map = <0 0 0 0 &mpic 63>; | ||
| 235 | marvell,pcie-port = <1>; | ||
| 236 | marvell,pcie-lane = <1>; | ||
| 237 | clocks = <&gateclk 10>; | ||
| 238 | status = "disabled"; | ||
| 239 | }; | ||
| 240 | |||
| 241 | pcie@7,0 { | ||
| 242 | device_type = "pci"; | ||
| 243 | assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; | ||
| 244 | reg = <0x3800 0 0 0 0>; | ||
| 245 | #address-cells = <3>; | ||
| 246 | #size-cells = <2>; | ||
| 247 | #interrupt-cells = <1>; | ||
| 248 | ranges; | ||
| 249 | interrupt-map-mask = <0 0 0 0>; | ||
| 250 | interrupt-map = <0 0 0 0 &mpic 64>; | ||
| 251 | marvell,pcie-port = <1>; | ||
| 252 | marvell,pcie-lane = <2>; | ||
| 253 | clocks = <&gateclk 11>; | ||
| 254 | status = "disabled"; | ||
| 255 | }; | ||
| 256 | |||
| 257 | pcie@8,0 { | ||
| 258 | device_type = "pci"; | ||
| 259 | assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; | ||
| 260 | reg = <0x4000 0 0 0 0>; | ||
| 261 | #address-cells = <3>; | ||
| 262 | #size-cells = <2>; | ||
| 263 | #interrupt-cells = <1>; | ||
| 264 | ranges; | ||
| 265 | interrupt-map-mask = <0 0 0 0>; | ||
| 266 | interrupt-map = <0 0 0 0 &mpic 65>; | ||
| 267 | marvell,pcie-port = <1>; | ||
| 268 | marvell,pcie-lane = <3>; | ||
| 269 | clocks = <&gateclk 12>; | ||
| 270 | status = "disabled"; | ||
| 271 | }; | ||
| 272 | pcie@9,0 { | ||
| 273 | device_type = "pci"; | ||
| 274 | assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; | ||
| 275 | reg = <0x4800 0 0 0 0>; | ||
| 276 | #address-cells = <3>; | ||
| 277 | #size-cells = <2>; | ||
| 278 | #interrupt-cells = <1>; | ||
| 279 | ranges; | ||
| 280 | interrupt-map-mask = <0 0 0 0>; | ||
| 281 | interrupt-map = <0 0 0 0 &mpic 99>; | ||
| 282 | marvell,pcie-port = <2>; | ||
| 283 | marvell,pcie-lane = <0>; | ||
| 284 | clocks = <&gateclk 26>; | ||
| 285 | status = "disabled"; | ||
| 286 | }; | ||
| 287 | |||
| 288 | pcie@10,0 { | ||
| 289 | device_type = "pci"; | ||
| 290 | assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; | ||
| 291 | reg = <0x5000 0 0 0 0>; | ||
| 292 | #address-cells = <3>; | ||
| 293 | #size-cells = <2>; | ||
| 294 | #interrupt-cells = <1>; | ||
| 295 | ranges; | ||
| 296 | interrupt-map-mask = <0 0 0 0>; | ||
| 297 | interrupt-map = <0 0 0 0 &mpic 103>; | ||
| 298 | marvell,pcie-port = <3>; | ||
| 299 | marvell,pcie-lane = <0>; | ||
| 300 | clocks = <&gateclk 27>; | ||
| 301 | status = "disabled"; | ||
| 302 | }; | ||
| 303 | }; | ||
| 304 | }; | 337 | }; |
| 305 | }; | 338 | }; |
| 306 | }; | 339 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 8f510458ea86..5695afcc04bf 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | 13 | /dts-v1/; |
| 14 | /include/ "armada-xp-mv78260.dtsi" | 14 | #include "armada-xp-mv78260.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | model = "PlatHome OpenBlocks AX3-4 board"; | 17 | model = "PlatHome OpenBlocks AX3-4 board"; |
| @@ -27,9 +27,46 @@ | |||
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | soc { | 29 | soc { |
| 30 | ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ | 30 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 |
| 31 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ | 31 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
| 32 | 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; | 32 | MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>; |
| 33 | |||
| 34 | devbus-bootcs { | ||
| 35 | status = "okay"; | ||
| 36 | |||
| 37 | /* Device Bus parameters are required */ | ||
| 38 | |||
| 39 | /* Read parameters */ | ||
| 40 | devbus,bus-width = <8>; | ||
| 41 | devbus,turn-off-ps = <60000>; | ||
| 42 | devbus,badr-skew-ps = <0>; | ||
| 43 | devbus,acc-first-ps = <124000>; | ||
| 44 | devbus,acc-next-ps = <248000>; | ||
| 45 | devbus,rd-setup-ps = <0>; | ||
| 46 | devbus,rd-hold-ps = <0>; | ||
| 47 | |||
| 48 | /* Write parameters */ | ||
| 49 | devbus,sync-enable = <0>; | ||
| 50 | devbus,wr-high-ps = <60000>; | ||
| 51 | devbus,wr-low-ps = <60000>; | ||
| 52 | devbus,ale-wr-ps = <60000>; | ||
| 53 | |||
| 54 | /* NOR 128 MiB */ | ||
| 55 | nor@0 { | ||
| 56 | compatible = "cfi-flash"; | ||
| 57 | reg = <0 0x8000000>; | ||
| 58 | bank-width = <2>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | pcie-controller { | ||
| 63 | status = "okay"; | ||
| 64 | /* Internal mini-PCIe connector */ | ||
| 65 | pcie@1,0 { | ||
| 66 | /* Port 0, Lane 0 */ | ||
| 67 | status = "okay"; | ||
| 68 | }; | ||
| 69 | }; | ||
| 33 | 70 | ||
| 34 | internal-regs { | 71 | internal-regs { |
| 35 | serial@12000 { | 72 | serial@12000 { |
| @@ -148,49 +185,6 @@ | |||
| 148 | usb@51000 { | 185 | usb@51000 { |
| 149 | status = "okay"; | 186 | status = "okay"; |
| 150 | }; | 187 | }; |
| 151 | |||
| 152 | /* USB interface in the mini-PCIe connector */ | ||
| 153 | usb@52000 { | ||
| 154 | status = "okay"; | ||
| 155 | }; | ||
| 156 | |||
| 157 | devbus-bootcs@10400 { | ||
| 158 | status = "okay"; | ||
| 159 | ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ | ||
| 160 | |||
| 161 | /* Device Bus parameters are required */ | ||
| 162 | |||
| 163 | /* Read parameters */ | ||
| 164 | devbus,bus-width = <8>; | ||
| 165 | devbus,turn-off-ps = <60000>; | ||
| 166 | devbus,badr-skew-ps = <0>; | ||
| 167 | devbus,acc-first-ps = <124000>; | ||
| 168 | devbus,acc-next-ps = <248000>; | ||
| 169 | devbus,rd-setup-ps = <0>; | ||
| 170 | devbus,rd-hold-ps = <0>; | ||
| 171 | |||
| 172 | /* Write parameters */ | ||
| 173 | devbus,sync-enable = <0>; | ||
| 174 | devbus,wr-high-ps = <60000>; | ||
| 175 | devbus,wr-low-ps = <60000>; | ||
| 176 | devbus,ale-wr-ps = <60000>; | ||
| 177 | |||
| 178 | /* NOR 128 MiB */ | ||
| 179 | nor@0 { | ||
| 180 | compatible = "cfi-flash"; | ||
| 181 | reg = <0 0x8000000>; | ||
| 182 | bank-width = <2>; | ||
| 183 | }; | ||
| 184 | }; | ||
| 185 | |||
| 186 | pcie-controller { | ||
| 187 | status = "okay"; | ||
| 188 | /* Internal mini-PCIe connector */ | ||
| 189 | pcie@1,0 { | ||
| 190 | /* Port 0, Lane 0 */ | ||
| 191 | status = "okay"; | ||
| 192 | }; | ||
| 193 | }; | ||
| 194 | }; | 188 | }; |
| 195 | }; | 189 | }; |
| 196 | }; | 190 | }; |
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 416eb9481844..def125c0eeaa 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | * common to all Armada SoCs. | 16 | * common to all Armada SoCs. |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | /include/ "armada-370-xp.dtsi" | 19 | #include "armada-370-xp.dtsi" |
| 20 | 20 | ||
| 21 | / { | 21 | / { |
| 22 | model = "Marvell Armada XP family SoC"; | 22 | model = "Marvell Armada XP family SoC"; |
| @@ -27,6 +27,13 @@ | |||
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | soc { | 29 | soc { |
| 30 | compatible = "marvell,armadaxp-mbus", "simple-bus"; | ||
| 31 | |||
| 32 | bootrom { | ||
| 33 | compatible = "marvell,bootrom"; | ||
| 34 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | ||
| 35 | }; | ||
| 36 | |||
| 30 | internal-regs { | 37 | internal-regs { |
| 31 | L2: l2-cache { | 38 | L2: l2-cache { |
| 32 | compatible = "marvell,aurora-system-cache"; | 39 | compatible = "marvell,aurora-system-cache"; |
| @@ -62,7 +69,7 @@ | |||
| 62 | }; | 69 | }; |
| 63 | 70 | ||
| 64 | timer@20300 { | 71 | timer@20300 { |
| 65 | marvell,timer-25Mhz; | 72 | compatible = "marvell,armada-xp-timer"; |
| 66 | }; | 73 | }; |
| 67 | 74 | ||
| 68 | coreclk: mvebu-sar@18230 { | 75 | coreclk: mvebu-sar@18230 { |
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 5bce7cc55cf3..588ce58a2959 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts | |||
| @@ -90,6 +90,17 @@ | |||
| 90 | }; | 90 | }; |
| 91 | }; | 91 | }; |
| 92 | }; | 92 | }; |
| 93 | mdio: mdio@1e24000 { | ||
| 94 | status = "okay"; | ||
| 95 | pinctrl-names = "default"; | ||
| 96 | pinctrl-0 = <&mdio_pins>; | ||
| 97 | bus_freq = <2200000>; | ||
| 98 | }; | ||
| 99 | eth0: ethernet@1e20000 { | ||
| 100 | status = "okay"; | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | pinctrl-0 = <&mii_pins>; | ||
| 103 | }; | ||
| 93 | }; | 104 | }; |
| 94 | nand_cs3@62000000 { | 105 | nand_cs3@62000000 { |
| 95 | status = "okay"; | 106 | status = "okay"; |
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index d70ba5504481..8d17346f9702 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi | |||
| @@ -125,11 +125,33 @@ | |||
| 125 | 0x14 0x00000010 0x000000f0 | 125 | 0x14 0x00000010 0x000000f0 |
| 126 | >; | 126 | >; |
| 127 | }; | 127 | }; |
| 128 | mdio_pins: pinmux_mdio_pins { | ||
| 129 | pinctrl-single,bits = < | ||
| 130 | /* MDIO_CLK, MDIO_D */ | ||
| 131 | 0x10 0x00000088 0x000000ff | ||
| 132 | >; | ||
| 133 | }; | ||
| 134 | mii_pins: pinmux_mii_pins { | ||
| 135 | pinctrl-single,bits = < | ||
| 136 | /* | ||
| 137 | * MII_TXEN, MII_TXCLK, MII_COL | ||
| 138 | * MII_TXD_3, MII_TXD_2, MII_TXD_1 | ||
| 139 | * MII_TXD_0 | ||
| 140 | */ | ||
| 141 | 0x8 0x88888880 0xfffffff0 | ||
| 142 | /* | ||
| 143 | * MII_RXER, MII_CRS, MII_RXCLK | ||
| 144 | * MII_RXDV, MII_RXD_3, MII_RXD_2 | ||
| 145 | * MII_RXD_1, MII_RXD_0 | ||
| 146 | */ | ||
| 147 | 0xc 0x88888888 0xffffffff | ||
| 148 | >; | ||
| 149 | }; | ||
| 150 | |||
| 128 | }; | 151 | }; |
| 129 | serial0: serial@1c42000 { | 152 | serial0: serial@1c42000 { |
| 130 | compatible = "ns16550a"; | 153 | compatible = "ns16550a"; |
| 131 | reg = <0x42000 0x100>; | 154 | reg = <0x42000 0x100>; |
| 132 | clock-frequency = <150000000>; | ||
| 133 | reg-shift = <2>; | 155 | reg-shift = <2>; |
| 134 | interrupts = <25>; | 156 | interrupts = <25>; |
| 135 | status = "disabled"; | 157 | status = "disabled"; |
| @@ -137,7 +159,6 @@ | |||
| 137 | serial1: serial@1d0c000 { | 159 | serial1: serial@1d0c000 { |
| 138 | compatible = "ns16550a"; | 160 | compatible = "ns16550a"; |
| 139 | reg = <0x10c000 0x100>; | 161 | reg = <0x10c000 0x100>; |
| 140 | clock-frequency = <150000000>; | ||
| 141 | reg-shift = <2>; | 162 | reg-shift = <2>; |
| 142 | interrupts = <53>; | 163 | interrupts = <53>; |
| 143 | status = "disabled"; | 164 | status = "disabled"; |
| @@ -145,7 +166,6 @@ | |||
| 145 | serial2: serial@1d0d000 { | 166 | serial2: serial@1d0d000 { |
| 146 | compatible = "ns16550a"; | 167 | compatible = "ns16550a"; |
| 147 | reg = <0x10d000 0x100>; | 168 | reg = <0x10d000 0x100>; |
| 148 | clock-frequency = <150000000>; | ||
| 149 | reg-shift = <2>; | 169 | reg-shift = <2>; |
| 150 | interrupts = <61>; | 170 | interrupts = <61>; |
| 151 | status = "disabled"; | 171 | status = "disabled"; |
| @@ -216,6 +236,26 @@ | |||
| 216 | interrupts = <56>; | 236 | interrupts = <56>; |
| 217 | status = "disabled"; | 237 | status = "disabled"; |
| 218 | }; | 238 | }; |
| 239 | mdio: mdio@1e24000 { | ||
| 240 | compatible = "ti,davinci_mdio"; | ||
| 241 | #address-cells = <1>; | ||
| 242 | #size-cells = <0>; | ||
| 243 | reg = <0x224000 0x1000>; | ||
| 244 | }; | ||
| 245 | eth0: ethernet@1e20000 { | ||
| 246 | compatible = "ti,davinci-dm6467-emac"; | ||
| 247 | reg = <0x220000 0x4000>; | ||
| 248 | ti,davinci-ctrl-reg-offset = <0x3000>; | ||
| 249 | ti,davinci-ctrl-mod-reg-offset = <0x2000>; | ||
| 250 | ti,davinci-ctrl-ram-offset = <0>; | ||
| 251 | ti,davinci-ctrl-ram-size = <0x2000>; | ||
| 252 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 253 | interrupts = <33 | ||
| 254 | 34 | ||
| 255 | 35 | ||
| 256 | 36 | ||
| 257 | >; | ||
| 258 | }; | ||
| 219 | }; | 259 | }; |
| 220 | nand_cs3@62000000 { | 260 | nand_cs3@62000000 { |
| 221 | compatible = "ti,davinci-nand"; | 261 | compatible = "ti,davinci-nand"; |
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 701153992c69..737ed5da8f71 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi | |||
| @@ -13,19 +13,35 @@ | |||
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
| 16 | gpio0 = &gpio1; | ||
| 17 | gpio1 = &gpio2; | ||
| 18 | gpio2 = &gpio3; | ||
| 19 | gpio3 = &gpio4; | ||
| 20 | i2c0 = &i2c1; | ||
| 21 | i2c1 = &i2c2; | ||
| 22 | i2c2 = &i2c3; | ||
| 16 | serial0 = &uart1; | 23 | serial0 = &uart1; |
| 17 | serial1 = &uart2; | 24 | serial1 = &uart2; |
| 18 | serial2 = &uart3; | 25 | serial2 = &uart3; |
| 19 | serial3 = &uart4; | 26 | serial3 = &uart4; |
| 20 | serial4 = &uart5; | 27 | serial4 = &uart5; |
| 21 | gpio0 = &gpio1; | 28 | spi0 = &spi1; |
| 22 | gpio1 = &gpio2; | 29 | spi1 = &spi2; |
| 23 | gpio2 = &gpio3; | 30 | spi2 = &spi3; |
| 24 | gpio3 = &gpio4; | ||
| 25 | usb0 = &usbotg; | 31 | usb0 = &usbotg; |
| 26 | usb1 = &usbhost1; | 32 | usb1 = &usbhost1; |
| 27 | }; | 33 | }; |
| 28 | 34 | ||
| 35 | cpus { | ||
| 36 | #address-cells = <0>; | ||
| 37 | #size-cells = <0>; | ||
| 38 | |||
| 39 | cpu { | ||
| 40 | compatible = "arm,arm926ej-s"; | ||
| 41 | device_type = "cpu"; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 29 | asic: asic-interrupt-controller@68000000 { | 45 | asic: asic-interrupt-controller@68000000 { |
| 30 | compatible = "fsl,imx25-asic", "fsl,avic"; | 46 | compatible = "fsl,imx25-asic", "fsl,avic"; |
| 31 | interrupt-controller; | 47 | interrupt-controller; |
| @@ -377,7 +393,8 @@ | |||
| 377 | status = "disabled"; | 393 | status = "disabled"; |
| 378 | }; | 394 | }; |
| 379 | 395 | ||
| 380 | lcdc@53fbc000 { | 396 | lcdc: lcdc@53fbc000 { |
| 397 | compatible = "fsl,imx25-fb", "fsl,imx21-fb"; | ||
| 381 | reg = <0x53fbc000 0x4000>; | 398 | reg = <0x53fbc000 0x4000>; |
| 382 | interrupts = <39>; | 399 | interrupts = <39>; |
| 383 | clocks = <&clks 103>, <&clks 66>, <&clks 49>; | 400 | clocks = <&clks 103>, <&clks 66>, <&clks 49>; |
| @@ -424,6 +441,7 @@ | |||
| 424 | reg = <0x53fd4000 0x4000>; | 441 | reg = <0x53fd4000 0x4000>; |
| 425 | clocks = <&clks 112>, <&clks 68>; | 442 | clocks = <&clks 112>, <&clks 68>; |
| 426 | clock-names = "ipg", "ahb"; | 443 | clock-names = "ipg", "ahb"; |
| 444 | #dma-cells = <3>; | ||
| 427 | interrupts = <34>; | 445 | interrupts = <34>; |
| 428 | }; | 446 | }; |
| 429 | 447 | ||
| @@ -444,6 +462,13 @@ | |||
| 444 | interrupts = <26>; | 462 | interrupts = <26>; |
| 445 | }; | 463 | }; |
| 446 | 464 | ||
| 465 | iim: iim@53ff0000 { | ||
| 466 | compatible = "fsl,imx25-iim", "fsl,imx27-iim"; | ||
| 467 | reg = <0x53ff0000 0x4000>; | ||
| 468 | interrupts = <19>; | ||
| 469 | clocks = <&clks 99>; | ||
| 470 | }; | ||
| 471 | |||
| 447 | usbphy1: usbphy@1 { | 472 | usbphy1: usbphy@1 { |
| 448 | compatible = "nop-usbphy"; | 473 | compatible = "nop-usbphy"; |
| 449 | status = "disabled"; | 474 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 66b8e1c1b0be..2a377ca1881a 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts | |||
| @@ -53,6 +53,11 @@ | |||
| 53 | &i2c1 { | 53 | &i2c1 { |
| 54 | clock-frequency = <400000>; | 54 | clock-frequency = <400000>; |
| 55 | status = "okay"; | 55 | status = "okay"; |
| 56 | |||
| 57 | rtc@68 { | ||
| 58 | compatible = "dallas,ds1374"; | ||
| 59 | reg = <0x68>; | ||
| 60 | }; | ||
| 56 | }; | 61 | }; |
| 57 | 62 | ||
| 58 | &i2c2 { | 63 | &i2c2 { |
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts new file mode 100644 index 000000000000..5a31c776513f --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Markus Pargmann, Pengutronix | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "imx27-phytec-phycard-s-som.dts" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Phytec pca100 rapid development kit"; | ||
| 16 | compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; | ||
| 17 | |||
| 18 | display: display { | ||
| 19 | model = "Primeview-PD050VL1"; | ||
| 20 | native-mode = <&timing0>; | ||
| 21 | bits-per-pixel = <16>; /* non-standard but required */ | ||
| 22 | fsl,pcr = <0xf0c88080>; /* non-standard but required */ | ||
| 23 | display-timings { | ||
| 24 | timing0: 640x480 { | ||
| 25 | hactive = <640>; | ||
| 26 | vactive = <480>; | ||
| 27 | hback-porch = <112>; | ||
| 28 | hfront-porch = <36>; | ||
| 29 | hsync-len = <32>; | ||
| 30 | vback-porch = <33>; | ||
| 31 | vfront-porch = <33>; | ||
| 32 | vsync-len = <2>; | ||
| 33 | clock-frequency = <25000000>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
| 37 | |||
| 38 | regulators { | ||
| 39 | compatible = "simple-bus"; | ||
| 40 | |||
| 41 | reg_3v3: 3v3 { | ||
| 42 | compatible = "regulator-fixed"; | ||
| 43 | regulator-name = "3V3"; | ||
| 44 | regulator-min-microvolt = <3300000>; | ||
| 45 | regulator-max-microvolt = <3300000>; | ||
| 46 | regulator-always-on; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | &fb { | ||
| 52 | display = <&display>; | ||
| 53 | status = "okay"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | &i2c1 { | ||
| 57 | status = "okay"; | ||
| 58 | |||
| 59 | rtc@51 { | ||
| 60 | compatible = "nxp,pcf8563"; | ||
| 61 | reg = <0x51>; | ||
| 62 | }; | ||
| 63 | |||
| 64 | adc@64 { | ||
| 65 | compatible = "maxim,max1037"; | ||
| 66 | vcc-supply = <®_3v3>; | ||
| 67 | reg = <0x64>; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | &owire { | ||
| 72 | status = "okay"; | ||
| 73 | }; | ||
| 74 | |||
| 75 | &sdhci2 { | ||
| 76 | cd-gpios = <&gpio3 29 0>; | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | &uart1 { | ||
| 81 | fsl,uart-has-rtscts; | ||
| 82 | status = "okay"; | ||
| 83 | }; | ||
| 84 | |||
| 85 | &uart2 { | ||
| 86 | fsl,uart-has-rtscts; | ||
| 87 | status = "okay"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | &uart3 { | ||
| 91 | fsl,uart-has-rtscts; | ||
| 92 | status = "okay"; | ||
| 93 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts new file mode 100644 index 000000000000..c8d57d1d0743 --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar | ||
| 3 | * and Markus Pargmann, Pengutronix | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /dts-v1/; | ||
| 14 | #include "imx27.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "Phytec pca100"; | ||
| 18 | compatible = "phytec,imx27-pca100", "fsl,imx27"; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0xa0000000 0x08000000>; /* 128MB */ | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | &cspi1 { | ||
| 26 | fsl,spi-num-chipselects = <2>; | ||
| 27 | cs-gpios = <&gpio4 28 0>, | ||
| 28 | <&gpio4 27 0>; | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &fec { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &i2c2 { | ||
| 37 | status = "okay"; | ||
| 38 | |||
| 39 | at24@52 { | ||
| 40 | compatible = "at,24c32"; | ||
| 41 | pagesize = <32>; | ||
| 42 | reg = <0x52>; | ||
| 43 | }; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index e7ed9786920a..0fc6551786c6 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | |||
| @@ -35,3 +35,16 @@ | |||
| 35 | fsl,uart-has-rtscts; | 35 | fsl,uart-has-rtscts; |
| 36 | status = "okay"; | 36 | status = "okay"; |
| 37 | }; | 37 | }; |
| 38 | |||
| 39 | &weim { | ||
| 40 | can@d4000000 { | ||
| 41 | compatible = "nxp,sja1000"; | ||
| 42 | reg = <4 0x00000000 0x00000100>; | ||
| 43 | interrupt-parent = <&gpio5>; | ||
| 44 | interrupts = <19 0x2>; | ||
| 45 | nxp,external-clock-frequency = <16000000>; | ||
| 46 | nxp,tx-output-config = <0x16>; | ||
| 47 | nxp,no-comparator-bypass; | ||
| 48 | fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; | ||
| 49 | }; | ||
| 50 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts index f0105651869d..4ec402c38945 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts | |||
| @@ -17,49 +17,22 @@ | |||
| 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; | 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; |
| 18 | 18 | ||
| 19 | memory { | 19 | memory { |
| 20 | reg = <0x0 0x0>; | 20 | reg = <0xa0000000 0x08000000>; |
| 21 | }; | 21 | }; |
| 22 | }; | ||
| 22 | 23 | ||
| 23 | soc { | 24 | &audmux { |
| 24 | aipi@10000000 { /* aipi1 */ | 25 | status = "okay"; |
| 25 | serial@1000a000 { | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | i2c@1001d000 { | ||
| 30 | clock-frequency = <400000>; | ||
| 31 | status = "okay"; | ||
| 32 | at24@52 { | ||
| 33 | compatible = "at,24c32"; | ||
| 34 | pagesize = <32>; | ||
| 35 | reg = <0x52>; | ||
| 36 | }; | ||
| 37 | pcf8563@51 { | ||
| 38 | compatible = "nxp,pcf8563"; | ||
| 39 | reg = <0x51>; | ||
| 40 | }; | ||
| 41 | lm75@4a { | ||
| 42 | compatible = "national,lm75"; | ||
| 43 | reg = <0x4a>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | 26 | ||
| 48 | aipi@10020000 { /* aipi2 */ | 27 | /* SSI0 <=> PINS_4 (MC13783 Audio) */ |
| 49 | ethernet@1002b000 { | 28 | ssi0 { |
| 50 | phy-reset-gpios = <&gpio3 30 0>; | 29 | fsl,audmux-port = <0>; |
| 51 | status = "okay"; | 30 | fsl,port-config = <0xcb205000>; |
| 52 | }; | ||
| 53 | }; | ||
| 54 | }; | 31 | }; |
| 55 | 32 | ||
| 56 | nor_flash@c0000000 { | 33 | pins4 { |
| 57 | compatible = "cfi-flash"; | 34 | fsl,audmux-port = <2>; |
| 58 | bank-width = <2>; | 35 | fsl,port-config = <0x00001000>; |
| 59 | reg = <0xc0000000 0x02000000>; | ||
| 60 | linux,mtd-name = "physmap-flash.0"; | ||
| 61 | #address-cells = <1>; | ||
| 62 | #size-cells = <1>; | ||
| 63 | }; | 36 | }; |
| 64 | }; | 37 | }; |
| 65 | 38 | ||
| @@ -80,28 +53,16 @@ | |||
| 80 | fsl,mc13xxx-uses-rtc; | 53 | fsl,mc13xxx-uses-rtc; |
| 81 | 54 | ||
| 82 | regulators { | 55 | regulators { |
| 83 | sw1a_reg: sw1a { | 56 | /* SW1A and SW1B joined operation */ |
| 57 | sw1_reg: sw1a { | ||
| 84 | regulator-min-microvolt = <1200000>; | 58 | regulator-min-microvolt = <1200000>; |
| 85 | regulator-max-microvolt = <1200000>; | 59 | regulator-max-microvolt = <1520000>; |
| 86 | regulator-always-on; | 60 | regulator-always-on; |
| 87 | regulator-boot-on; | 61 | regulator-boot-on; |
| 88 | }; | 62 | }; |
| 89 | 63 | ||
| 90 | sw1b_reg: sw1b { | 64 | /* SW2A and SW2B joined operation */ |
| 91 | regulator-min-microvolt = <1200000>; | 65 | sw2_reg: sw2a { |
| 92 | regulator-max-microvolt = <1200000>; | ||
| 93 | regulator-always-on; | ||
| 94 | regulator-boot-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | sw2a_reg: sw2a { | ||
| 98 | regulator-min-microvolt = <1800000>; | ||
| 99 | regulator-max-microvolt = <1800000>; | ||
| 100 | regulator-always-on; | ||
| 101 | regulator-boot-on; | ||
| 102 | }; | ||
| 103 | |||
| 104 | sw2b_reg: sw2b { | ||
| 105 | regulator-min-microvolt = <1800000>; | 66 | regulator-min-microvolt = <1800000>; |
| 106 | regulator-max-microvolt = <1800000>; | 67 | regulator-max-microvolt = <1800000>; |
| 107 | regulator-always-on; | 68 | regulator-always-on; |
| @@ -172,8 +133,62 @@ | |||
| 172 | }; | 133 | }; |
| 173 | }; | 134 | }; |
| 174 | 135 | ||
| 136 | &fec { | ||
| 137 | phy-reset-gpios = <&gpio3 30 0>; | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | &i2c2 { | ||
| 142 | clock-frequency = <400000>; | ||
| 143 | status = "okay"; | ||
| 144 | |||
| 145 | at24@52 { | ||
| 146 | compatible = "at,24c32"; | ||
| 147 | pagesize = <32>; | ||
| 148 | reg = <0x52>; | ||
| 149 | }; | ||
| 150 | |||
| 151 | pcf8563@51 { | ||
| 152 | compatible = "nxp,pcf8563"; | ||
| 153 | reg = <0x51>; | ||
| 154 | }; | ||
| 155 | |||
| 156 | lm75@4a { | ||
| 157 | compatible = "national,lm75"; | ||
| 158 | reg = <0x4a>; | ||
| 159 | }; | ||
| 160 | }; | ||
| 161 | |||
| 175 | &nfc { | 162 | &nfc { |
| 176 | nand-bus-width = <8>; | 163 | nand-bus-width = <8>; |
| 177 | nand-ecc-mode = "hw"; | 164 | nand-ecc-mode = "hw"; |
| 178 | status = "okay"; | 165 | status = "okay"; |
| 179 | }; | 166 | }; |
| 167 | |||
| 168 | &uart1 { | ||
| 169 | status = "okay"; | ||
| 170 | }; | ||
| 171 | |||
| 172 | &weim { | ||
| 173 | status = "okay"; | ||
| 174 | |||
| 175 | nor: nor@c0000000 { | ||
| 176 | compatible = "cfi-flash"; | ||
| 177 | reg = <0 0x00000000 0x02000000>; | ||
| 178 | bank-width = <2>; | ||
| 179 | linux,mtd-name = "physmap-flash.0"; | ||
| 180 | fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; | ||
| 181 | #address-cells = <1>; | ||
| 182 | #size-cells = <1>; | ||
| 183 | }; | ||
| 184 | |||
| 185 | sram: sram@c8000000 { | ||
| 186 | compatible = "mtd-ram"; | ||
| 187 | reg = <1 0x00000000 0x00800000>; | ||
| 188 | bank-width = <2>; | ||
| 189 | linux,mtd-name = "mtd-ram.0"; | ||
| 190 | fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; | ||
| 191 | #address-cells = <1>; | ||
| 192 | #size-cells = <1>; | ||
| 193 | }; | ||
| 194 | }; | ||
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 0695264ddf1b..c037c223619a 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -13,25 +13,27 @@ | |||
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | aliases { | 15 | aliases { |
| 16 | serial0 = &uart1; | ||
| 17 | serial1 = &uart2; | ||
| 18 | serial2 = &uart3; | ||
| 19 | serial3 = &uart4; | ||
| 20 | serial4 = &uart5; | ||
| 21 | serial5 = &uart6; | ||
| 22 | gpio0 = &gpio1; | 16 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | 17 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; | 18 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; | 19 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; | 20 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; | 21 | gpio5 = &gpio6; |
| 22 | i2c0 = &i2c1; | ||
| 23 | i2c1 = &i2c2; | ||
| 24 | serial0 = &uart1; | ||
| 25 | serial1 = &uart2; | ||
| 26 | serial2 = &uart3; | ||
| 27 | serial3 = &uart4; | ||
| 28 | serial4 = &uart5; | ||
| 29 | serial5 = &uart6; | ||
| 28 | spi0 = &cspi1; | 30 | spi0 = &cspi1; |
| 29 | spi1 = &cspi2; | 31 | spi1 = &cspi2; |
| 30 | spi2 = &cspi3; | 32 | spi2 = &cspi3; |
| 31 | }; | 33 | }; |
| 32 | 34 | ||
| 33 | avic: avic-interrupt-controller@e0000000 { | 35 | aitc: aitc-interrupt-controller@e0000000 { |
| 34 | compatible = "fsl,imx27-avic", "fsl,avic"; | 36 | compatible = "fsl,imx27-aitc", "fsl,avic"; |
| 35 | interrupt-controller; | 37 | interrupt-controller; |
| 36 | #interrupt-cells = <1>; | 38 | #interrupt-cells = <1>; |
| 37 | reg = <0x10040000 0x1000>; | 39 | reg = <0x10040000 0x1000>; |
| @@ -47,11 +49,29 @@ | |||
| 47 | }; | 49 | }; |
| 48 | }; | 50 | }; |
| 49 | 51 | ||
| 52 | cpus { | ||
| 53 | #size-cells = <0>; | ||
| 54 | #address-cells = <1>; | ||
| 55 | |||
| 56 | cpu: cpu@0 { | ||
| 57 | device_type = "cpu"; | ||
| 58 | compatible = "arm,arm926ej-s"; | ||
| 59 | operating-points = < | ||
| 60 | /* kHz uV */ | ||
| 61 | 266000 1300000 | ||
| 62 | 399000 1450000 | ||
| 63 | >; | ||
| 64 | clock-latency = <62500>; | ||
| 65 | clocks = <&clks 18>; | ||
| 66 | voltage-tolerance = <5>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 50 | soc { | 70 | soc { |
| 51 | #address-cells = <1>; | 71 | #address-cells = <1>; |
| 52 | #size-cells = <1>; | 72 | #size-cells = <1>; |
| 53 | compatible = "simple-bus"; | 73 | compatible = "simple-bus"; |
| 54 | interrupt-parent = <&avic>; | 74 | interrupt-parent = <&aitc>; |
| 55 | ranges; | 75 | ranges; |
| 56 | 76 | ||
| 57 | aipi@10000000 { /* AIPI1 */ | 77 | aipi@10000000 { /* AIPI1 */ |
| @@ -75,7 +95,7 @@ | |||
| 75 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; | 95 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 76 | reg = <0x10002000 0x1000>; | 96 | reg = <0x10002000 0x1000>; |
| 77 | interrupts = <27>; | 97 | interrupts = <27>; |
| 78 | clocks = <&clks 0>; | 98 | clocks = <&clks 74>; |
| 79 | }; | 99 | }; |
| 80 | 100 | ||
| 81 | gpt1: timer@10003000 { | 101 | gpt1: timer@10003000 { |
| @@ -102,7 +122,7 @@ | |||
| 102 | clock-names = "ipg", "per"; | 122 | clock-names = "ipg", "per"; |
| 103 | }; | 123 | }; |
| 104 | 124 | ||
| 105 | pwm0: pwm@10006000 { | 125 | pwm: pwm@10006000 { |
| 106 | compatible = "fsl,imx27-pwm"; | 126 | compatible = "fsl,imx27-pwm"; |
| 107 | reg = <0x10006000 0x1000>; | 127 | reg = <0x10006000 0x1000>; |
| 108 | interrupts = <23>; | 128 | interrupts = <23>; |
| @@ -110,6 +130,21 @@ | |||
| 110 | clock-names = "ipg", "per"; | 130 | clock-names = "ipg", "per"; |
| 111 | }; | 131 | }; |
| 112 | 132 | ||
| 133 | kpp: kpp@10008000 { | ||
| 134 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; | ||
| 135 | reg = <0x10008000 0x1000>; | ||
| 136 | interrupts = <21>; | ||
| 137 | clocks = <&clks 37>; | ||
| 138 | status = "disabled"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | owire: owire@10009000 { | ||
| 142 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; | ||
| 143 | reg = <0x10009000 0x1000>; | ||
| 144 | clocks = <&clks 35>; | ||
| 145 | status = "disabled"; | ||
| 146 | }; | ||
| 147 | |||
| 113 | uart1: serial@1000a000 { | 148 | uart1: serial@1000a000 { |
| 114 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 149 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 115 | reg = <0x1000a000 0x1000>; | 150 | reg = <0x1000a000 0x1000>; |
| @@ -260,6 +295,14 @@ | |||
| 260 | #interrupt-cells = <2>; | 295 | #interrupt-cells = <2>; |
| 261 | }; | 296 | }; |
| 262 | 297 | ||
| 298 | audmux: audmux@10016000 { | ||
| 299 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; | ||
| 300 | reg = <0x10016000 0x1000>; | ||
| 301 | clocks = <&clks 0>; | ||
| 302 | clock-names = "audmux"; | ||
| 303 | status = "disabled"; | ||
| 304 | }; | ||
| 305 | |||
| 263 | cspi3: cspi@10017000 { | 306 | cspi3: cspi@10017000 { |
| 264 | #address-cells = <1>; | 307 | #address-cells = <1>; |
| 265 | #size-cells = <0>; | 308 | #size-cells = <0>; |
| @@ -342,6 +385,15 @@ | |||
| 342 | reg = <0x10020000 0x20000>; | 385 | reg = <0x10020000 0x20000>; |
| 343 | ranges; | 386 | ranges; |
| 344 | 387 | ||
| 388 | fb: fb@10021000 { | ||
| 389 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; | ||
| 390 | interrupts = <61>; | ||
| 391 | reg = <0x10021000 0x1000>; | ||
| 392 | clocks = <&clks 36>, <&clks 65>, <&clks 59>; | ||
| 393 | clock-names = "ipg", "ahb", "per"; | ||
| 394 | status = "disabled"; | ||
| 395 | }; | ||
| 396 | |||
| 345 | coda: coda@10023000 { | 397 | coda: coda@10023000 { |
| 346 | compatible = "fsl,imx27-vpu"; | 398 | compatible = "fsl,imx27-vpu"; |
| 347 | reg = <0x10023000 0x0200>; | 399 | reg = <0x10023000 0x0200>; |
| @@ -351,27 +403,37 @@ | |||
| 351 | iram = <&iram>; | 403 | iram = <&iram>; |
| 352 | }; | 404 | }; |
| 353 | 405 | ||
| 406 | sahara2: sahara@10025000 { | ||
| 407 | compatible = "fsl,imx27-sahara"; | ||
| 408 | reg = <0x10025000 0x1000>; | ||
| 409 | interrupts = <59>; | ||
| 410 | clocks = <&clks 32>, <&clks 64>; | ||
| 411 | clock-names = "ipg", "ahb"; | ||
| 412 | }; | ||
| 413 | |||
| 354 | clks: ccm@10027000{ | 414 | clks: ccm@10027000{ |
| 355 | compatible = "fsl,imx27-ccm"; | 415 | compatible = "fsl,imx27-ccm"; |
| 356 | reg = <0x10027000 0x1000>; | 416 | reg = <0x10027000 0x1000>; |
| 357 | #clock-cells = <1>; | 417 | #clock-cells = <1>; |
| 358 | }; | 418 | }; |
| 359 | 419 | ||
| 420 | iim: iim@10028000 { | ||
| 421 | compatible = "fsl,imx27-iim"; | ||
| 422 | reg = <0x10028000 0x1000>; | ||
| 423 | interrupts = <62>; | ||
| 424 | clocks = <&clks 38>; | ||
| 425 | }; | ||
| 426 | |||
| 360 | fec: ethernet@1002b000 { | 427 | fec: ethernet@1002b000 { |
| 361 | compatible = "fsl,imx27-fec"; | 428 | compatible = "fsl,imx27-fec"; |
| 362 | reg = <0x1002b000 0x4000>; | 429 | reg = <0x1002b000 0x4000>; |
| 363 | interrupts = <50>; | 430 | interrupts = <50>; |
| 364 | clocks = <&clks 48>, <&clks 67>, <&clks 0>; | 431 | clocks = <&clks 48>, <&clks 67>; |
| 365 | clock-names = "ipg", "ahb", "ptp"; | 432 | clock-names = "ipg", "ahb"; |
| 366 | status = "disabled"; | 433 | status = "disabled"; |
| 367 | }; | 434 | }; |
| 368 | }; | 435 | }; |
| 369 | 436 | ||
| 370 | iram: iram@ffff4c00 { | ||
| 371 | compatible = "mmio-sram"; | ||
| 372 | reg = <0xffff4c00 0xb400>; | ||
| 373 | }; | ||
| 374 | |||
| 375 | nfc: nand@d8000000 { | 437 | nfc: nand@d8000000 { |
| 376 | #address-cells = <1>; | 438 | #address-cells = <1>; |
| 377 | #size-cells = <1>; | 439 | #size-cells = <1>; |
| @@ -381,5 +443,27 @@ | |||
| 381 | clocks = <&clks 54>; | 443 | clocks = <&clks 54>; |
| 382 | status = "disabled"; | 444 | status = "disabled"; |
| 383 | }; | 445 | }; |
| 446 | |||
| 447 | weim: weim@d8002000 { | ||
| 448 | #address-cells = <2>; | ||
| 449 | #size-cells = <1>; | ||
| 450 | compatible = "fsl,imx27-weim"; | ||
| 451 | reg = <0xd8002000 0x1000>; | ||
| 452 | clocks = <&clks 0>; | ||
| 453 | ranges = < | ||
| 454 | 0 0 0xc0000000 0x08000000 | ||
| 455 | 1 0 0xc8000000 0x08000000 | ||
| 456 | 2 0 0xd0000000 0x02000000 | ||
| 457 | 3 0 0xd2000000 0x02000000 | ||
| 458 | 4 0 0xd4000000 0x02000000 | ||
| 459 | 5 0 0xd6000000 0x02000000 | ||
| 460 | >; | ||
| 461 | status = "disabled"; | ||
| 462 | }; | ||
| 463 | |||
| 464 | iram: iram@ffff4c00 { | ||
| 465 | compatible = "mmio-sram"; | ||
| 466 | reg = <0xffff4c00 0xb400>; | ||
| 467 | }; | ||
| 384 | }; | 468 | }; |
| 385 | }; | 469 | }; |
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index c5449257ad9a..c34f82581248 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi | |||
| @@ -20,6 +20,16 @@ | |||
| 20 | serial4 = &uart5; | 20 | serial4 = &uart5; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | cpus { | ||
| 24 | #address-cells = <0>; | ||
| 25 | #size-cells = <0>; | ||
| 26 | |||
| 27 | cpu { | ||
| 28 | compatible = "arm,arm1136"; | ||
| 29 | device_type = "cpu"; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 23 | avic: avic-interrupt-controller@60000000 { | 33 | avic: avic-interrupt-controller@60000000 { |
| 24 | compatible = "fsl,imx31-avic", "fsl,avic"; | 34 | compatible = "fsl,imx31-avic", "fsl,avic"; |
| 25 | interrupt-controller; | 35 | interrupt-controller; |
| @@ -94,6 +104,13 @@ | |||
| 94 | status = "disabled"; | 104 | status = "disabled"; |
| 95 | }; | 105 | }; |
| 96 | 106 | ||
| 107 | iim: iim@5001c000 { | ||
| 108 | compatible = "fsl,imx31-iim", "fsl,imx27-iim"; | ||
| 109 | reg = <0x5001c000 0x1000>; | ||
| 110 | interrupts = <19>; | ||
| 111 | clocks = <&clks 25>; | ||
| 112 | }; | ||
| 113 | |||
| 97 | clks: ccm@53f80000{ | 114 | clks: ccm@53f80000{ |
| 98 | compatible = "fsl,imx31-ccm"; | 115 | compatible = "fsl,imx31-ccm"; |
| 99 | reg = <0x53f80000 0x4000>; | 116 | reg = <0x53f80000 0x4000>; |
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 8f7f9ac0b989..b3606993f2e8 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts | |||
| @@ -26,10 +26,6 @@ | |||
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | clocks { | 28 | clocks { |
| 29 | ckih1 { | ||
| 30 | clock-frequency = <0>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | osc { | 29 | osc { |
| 34 | clock-frequency = <33554432>; | 30 | clock-frequency = <33554432>; |
| 35 | }; | 31 | }; |
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ad3471ca17c7..1d337d99ecd5 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts | |||
| @@ -63,6 +63,10 @@ | |||
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | clocks { | 65 | clocks { |
| 66 | ckih1 { | ||
| 67 | clock-frequency = <22579200>; | ||
| 68 | }; | ||
| 69 | |||
| 66 | clk_26M: codec_clock { | 70 | clk_26M: codec_clock { |
| 67 | compatible = "fixed-clock"; | 71 | compatible = "fixed-clock"; |
| 68 | reg=<0>; | 72 | reg=<0>; |
| @@ -108,6 +112,7 @@ | |||
| 108 | #size-cells = <0>; | 112 | #size-cells = <0>; |
| 109 | compatible = "fsl,mc13892"; | 113 | compatible = "fsl,mc13892"; |
| 110 | spi-max-frequency = <6000000>; | 114 | spi-max-frequency = <6000000>; |
| 115 | spi-cs-high; | ||
| 111 | reg = <0>; | 116 | reg = <0>; |
| 112 | interrupt-parent = <&gpio1>; | 117 | interrupt-parent = <&gpio1>; |
| 113 | interrupts = <8 0x4>; | 118 | interrupts = <8 0x4>; |
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 25764b505a61..a85abb424c34 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -15,13 +15,18 @@ | |||
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | aliases { | 17 | aliases { |
| 18 | serial0 = &uart1; | ||
| 19 | serial1 = &uart2; | ||
| 20 | serial2 = &uart3; | ||
| 21 | gpio0 = &gpio1; | 18 | gpio0 = &gpio1; |
| 22 | gpio1 = &gpio2; | 19 | gpio1 = &gpio2; |
| 23 | gpio2 = &gpio3; | 20 | gpio2 = &gpio3; |
| 24 | gpio3 = &gpio4; | 21 | gpio3 = &gpio4; |
| 22 | i2c0 = &i2c1; | ||
| 23 | i2c1 = &i2c2; | ||
| 24 | serial0 = &uart1; | ||
| 25 | serial1 = &uart2; | ||
| 26 | serial2 = &uart3; | ||
| 27 | spi0 = &ecspi1; | ||
| 28 | spi1 = &ecspi2; | ||
| 29 | spi2 = &cspi; | ||
| 25 | }; | 30 | }; |
| 26 | 31 | ||
| 27 | tzic: tz-interrupt-controller@e0000000 { | 32 | tzic: tz-interrupt-controller@e0000000 { |
| @@ -42,7 +47,7 @@ | |||
| 42 | 47 | ||
| 43 | ckih1 { | 48 | ckih1 { |
| 44 | compatible = "fsl,imx-ckih1", "fixed-clock"; | 49 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 45 | clock-frequency = <22579200>; | 50 | clock-frequency = <0>; |
| 46 | }; | 51 | }; |
| 47 | 52 | ||
| 48 | ckih2 { | 53 | ckih2 { |
| @@ -149,6 +154,9 @@ | |||
| 149 | reg = <0x70014000 0x4000>; | 154 | reg = <0x70014000 0x4000>; |
| 150 | interrupts = <30>; | 155 | interrupts = <30>; |
| 151 | clocks = <&clks 49>; | 156 | clocks = <&clks 49>; |
| 157 | dmas = <&sdma 24 1 0>, | ||
| 158 | <&sdma 25 1 0>; | ||
| 159 | dma-names = "rx", "tx"; | ||
| 152 | fsl,fifo-depth = <15>; | 160 | fsl,fifo-depth = <15>; |
| 153 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | 161 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ |
| 154 | status = "disabled"; | 162 | status = "disabled"; |
| @@ -300,275 +308,6 @@ | |||
| 300 | iomuxc: iomuxc@73fa8000 { | 308 | iomuxc: iomuxc@73fa8000 { |
| 301 | compatible = "fsl,imx51-iomuxc"; | 309 | compatible = "fsl,imx51-iomuxc"; |
| 302 | reg = <0x73fa8000 0x4000>; | 310 | reg = <0x73fa8000 0x4000>; |
| 303 | |||
| 304 | audmux { | ||
| 305 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 306 | fsl,pins = < | ||
| 307 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 308 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 309 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 310 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 311 | >; | ||
| 312 | }; | ||
| 313 | }; | ||
| 314 | |||
| 315 | fec { | ||
| 316 | pinctrl_fec_1: fecgrp-1 { | ||
| 317 | fsl,pins = < | ||
| 318 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 319 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 320 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 321 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 322 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 323 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 324 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 325 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 326 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 327 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 328 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 329 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 330 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 331 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 332 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 333 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 334 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 335 | >; | ||
| 336 | }; | ||
| 337 | |||
| 338 | pinctrl_fec_2: fecgrp-2 { | ||
| 339 | fsl,pins = < | ||
| 340 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 341 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 342 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 343 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 344 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 345 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 346 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 347 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 348 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 349 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 350 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 351 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 352 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 353 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 354 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 355 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 356 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 357 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 358 | >; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | |||
| 362 | ecspi1 { | ||
| 363 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 364 | fsl,pins = < | ||
| 365 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 366 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 367 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 368 | >; | ||
| 369 | }; | ||
| 370 | }; | ||
| 371 | |||
| 372 | ecspi2 { | ||
| 373 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 374 | fsl,pins = < | ||
| 375 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 376 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 377 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 378 | >; | ||
| 379 | }; | ||
| 380 | }; | ||
| 381 | |||
| 382 | esdhc1 { | ||
| 383 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 384 | fsl,pins = < | ||
| 385 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 386 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 387 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 388 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 389 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 390 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 391 | >; | ||
| 392 | }; | ||
| 393 | }; | ||
| 394 | |||
| 395 | esdhc2 { | ||
| 396 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 397 | fsl,pins = < | ||
| 398 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 399 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 400 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 401 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 402 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 403 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 404 | >; | ||
| 405 | }; | ||
| 406 | }; | ||
| 407 | |||
| 408 | i2c2 { | ||
| 409 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 410 | fsl,pins = < | ||
| 411 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 412 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 413 | >; | ||
| 414 | }; | ||
| 415 | |||
| 416 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 417 | fsl,pins = < | ||
| 418 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 419 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 420 | >; | ||
| 421 | }; | ||
| 422 | }; | ||
| 423 | |||
| 424 | ipu_disp1 { | ||
| 425 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 426 | fsl,pins = < | ||
| 427 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 428 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 429 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 430 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 431 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 432 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 433 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 434 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 435 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 436 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 437 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 438 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 439 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 440 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 441 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 442 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 443 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 444 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 445 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 446 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 447 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 448 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 449 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 450 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 451 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | ||
| 452 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | ||
| 453 | >; | ||
| 454 | }; | ||
| 455 | }; | ||
| 456 | |||
| 457 | ipu_disp2 { | ||
| 458 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 459 | fsl,pins = < | ||
| 460 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 461 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 462 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 463 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 464 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 465 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 466 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 467 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 468 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 469 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 470 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 471 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 472 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 473 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 474 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 475 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 476 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | ||
| 477 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | ||
| 478 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | ||
| 479 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | ||
| 480 | >; | ||
| 481 | }; | ||
| 482 | }; | ||
| 483 | |||
| 484 | pata { | ||
| 485 | pinctrl_pata_1: patagrp-1 { | ||
| 486 | fsl,pins = < | ||
| 487 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 488 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 489 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 490 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 491 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 492 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 493 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 494 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 495 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 496 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 497 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 498 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 499 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 500 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 501 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 502 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 503 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 504 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 505 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 506 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 507 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 508 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 509 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 510 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 511 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 512 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 513 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 514 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 515 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 516 | >; | ||
| 517 | }; | ||
| 518 | }; | ||
| 519 | |||
| 520 | uart1 { | ||
| 521 | pinctrl_uart1_1: uart1grp-1 { | ||
| 522 | fsl,pins = < | ||
| 523 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 524 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 525 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 526 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 527 | >; | ||
| 528 | }; | ||
| 529 | }; | ||
| 530 | |||
| 531 | uart2 { | ||
| 532 | pinctrl_uart2_1: uart2grp-1 { | ||
| 533 | fsl,pins = < | ||
| 534 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 535 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 536 | >; | ||
| 537 | }; | ||
| 538 | }; | ||
| 539 | |||
| 540 | uart3 { | ||
| 541 | pinctrl_uart3_1: uart3grp-1 { | ||
| 542 | fsl,pins = < | ||
| 543 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 544 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 545 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 546 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 547 | >; | ||
| 548 | }; | ||
| 549 | |||
| 550 | pinctrl_uart3_2: uart3grp-2 { | ||
| 551 | fsl,pins = < | ||
| 552 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 553 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 554 | >; | ||
| 555 | }; | ||
| 556 | }; | ||
| 557 | |||
| 558 | kpp { | ||
| 559 | pinctrl_kpp_1: kppgrp-1 { | ||
| 560 | fsl,pins = < | ||
| 561 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 562 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 563 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 564 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 565 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 566 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 567 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 568 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 569 | >; | ||
| 570 | }; | ||
| 571 | }; | ||
| 572 | }; | 311 | }; |
| 573 | 312 | ||
| 574 | pwm1: pwm@73fb4000 { | 313 | pwm1: pwm@73fb4000 { |
| @@ -628,6 +367,13 @@ | |||
| 628 | reg = <0x80000000 0x10000000>; | 367 | reg = <0x80000000 0x10000000>; |
| 629 | ranges; | 368 | ranges; |
| 630 | 369 | ||
| 370 | iim: iim@83f98000 { | ||
| 371 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; | ||
| 372 | reg = <0x83f98000 0x4000>; | ||
| 373 | interrupts = <69>; | ||
| 374 | clocks = <&clks 107>; | ||
| 375 | }; | ||
| 376 | |||
| 631 | ecspi2: ecspi@83fac000 { | 377 | ecspi2: ecspi@83fac000 { |
| 632 | #address-cells = <1>; | 378 | #address-cells = <1>; |
| 633 | #size-cells = <0>; | 379 | #size-cells = <0>; |
| @@ -645,6 +391,7 @@ | |||
| 645 | interrupts = <6>; | 391 | interrupts = <6>; |
| 646 | clocks = <&clks 56>, <&clks 56>; | 392 | clocks = <&clks 56>, <&clks 56>; |
| 647 | clock-names = "ipg", "ahb"; | 393 | clock-names = "ipg", "ahb"; |
| 394 | #dma-cells = <3>; | ||
| 648 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; | 395 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
| 649 | }; | 396 | }; |
| 650 | 397 | ||
| @@ -684,6 +431,9 @@ | |||
| 684 | reg = <0x83fcc000 0x4000>; | 431 | reg = <0x83fcc000 0x4000>; |
| 685 | interrupts = <29>; | 432 | interrupts = <29>; |
| 686 | clocks = <&clks 48>; | 433 | clocks = <&clks 48>; |
| 434 | dmas = <&sdma 28 0 0>, | ||
| 435 | <&sdma 29 0 0>; | ||
| 436 | dma-names = "rx", "tx"; | ||
| 687 | fsl,fifo-depth = <15>; | 437 | fsl,fifo-depth = <15>; |
| 688 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | 438 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ |
| 689 | status = "disabled"; | 439 | status = "disabled"; |
| @@ -695,6 +445,23 @@ | |||
| 695 | status = "disabled"; | 445 | status = "disabled"; |
| 696 | }; | 446 | }; |
| 697 | 447 | ||
| 448 | weim: weim@83fda000 { | ||
| 449 | #address-cells = <2>; | ||
| 450 | #size-cells = <1>; | ||
| 451 | compatible = "fsl,imx51-weim"; | ||
| 452 | reg = <0x83fda000 0x1000>; | ||
| 453 | clocks = <&clks 57>; | ||
| 454 | ranges = < | ||
| 455 | 0 0 0xb0000000 0x08000000 | ||
| 456 | 1 0 0xb8000000 0x08000000 | ||
| 457 | 2 0 0xc0000000 0x08000000 | ||
| 458 | 3 0 0xc8000000 0x04000000 | ||
| 459 | 4 0 0xcc000000 0x02000000 | ||
| 460 | 5 0 0xce000000 0x02000000 | ||
| 461 | >; | ||
| 462 | status = "disabled"; | ||
| 463 | }; | ||
| 464 | |||
| 698 | nfc: nand@83fdb000 { | 465 | nfc: nand@83fdb000 { |
| 699 | compatible = "fsl,imx51-nand"; | 466 | compatible = "fsl,imx51-nand"; |
| 700 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | 467 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; |
| @@ -716,6 +483,9 @@ | |||
| 716 | reg = <0x83fe8000 0x4000>; | 483 | reg = <0x83fe8000 0x4000>; |
| 717 | interrupts = <96>; | 484 | interrupts = <96>; |
| 718 | clocks = <&clks 50>; | 485 | clocks = <&clks 50>; |
| 486 | dmas = <&sdma 46 0 0>, | ||
| 487 | <&sdma 47 0 0>; | ||
| 488 | dma-names = "rx", "tx"; | ||
| 719 | fsl,fifo-depth = <15>; | 489 | fsl,fifo-depth = <15>; |
| 720 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ | 490 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ |
| 721 | status = "disabled"; | 491 | status = "disabled"; |
| @@ -732,3 +502,319 @@ | |||
| 732 | }; | 502 | }; |
| 733 | }; | 503 | }; |
| 734 | }; | 504 | }; |
| 505 | |||
| 506 | &iomuxc { | ||
| 507 | audmux { | ||
| 508 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 509 | fsl,pins = < | ||
| 510 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 511 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 512 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 513 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 514 | >; | ||
| 515 | }; | ||
| 516 | }; | ||
| 517 | |||
| 518 | fec { | ||
| 519 | pinctrl_fec_1: fecgrp-1 { | ||
| 520 | fsl,pins = < | ||
| 521 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 522 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 523 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 524 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 525 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 526 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 527 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 528 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 529 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 530 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 531 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 532 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 533 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 534 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 535 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 536 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 537 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 538 | >; | ||
| 539 | }; | ||
| 540 | |||
| 541 | pinctrl_fec_2: fecgrp-2 { | ||
| 542 | fsl,pins = < | ||
| 543 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 544 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 545 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 546 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 547 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 548 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 549 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 550 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 551 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 552 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 553 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 554 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 555 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 556 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 557 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 558 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 559 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 560 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 561 | >; | ||
| 562 | }; | ||
| 563 | }; | ||
| 564 | |||
| 565 | ecspi1 { | ||
| 566 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 567 | fsl,pins = < | ||
| 568 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 569 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 570 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 571 | >; | ||
| 572 | }; | ||
| 573 | }; | ||
| 574 | |||
| 575 | ecspi2 { | ||
| 576 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 577 | fsl,pins = < | ||
| 578 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 579 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 580 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 581 | >; | ||
| 582 | }; | ||
| 583 | }; | ||
| 584 | |||
| 585 | esdhc1 { | ||
| 586 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 587 | fsl,pins = < | ||
| 588 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 589 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 590 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 591 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 592 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 593 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 594 | >; | ||
| 595 | }; | ||
| 596 | }; | ||
| 597 | |||
| 598 | esdhc2 { | ||
| 599 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 600 | fsl,pins = < | ||
| 601 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 602 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 603 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 604 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 605 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 606 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 607 | >; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 611 | i2c2 { | ||
| 612 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 613 | fsl,pins = < | ||
| 614 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 615 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 616 | >; | ||
| 617 | }; | ||
| 618 | |||
| 619 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 620 | fsl,pins = < | ||
| 621 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 622 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 623 | >; | ||
| 624 | }; | ||
| 625 | |||
| 626 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 627 | fsl,pins = < | ||
| 628 | MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed | ||
| 629 | MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed | ||
| 630 | >; | ||
| 631 | }; | ||
| 632 | }; | ||
| 633 | |||
| 634 | ipu_disp1 { | ||
| 635 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 636 | fsl,pins = < | ||
| 637 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 638 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 639 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 640 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 641 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 642 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 643 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 644 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 645 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 646 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 647 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 648 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 649 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 650 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 651 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 652 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 653 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 654 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 655 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 656 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 657 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 658 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 659 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 660 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 661 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | ||
| 662 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | ||
| 663 | >; | ||
| 664 | }; | ||
| 665 | }; | ||
| 666 | |||
| 667 | ipu_disp2 { | ||
| 668 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 669 | fsl,pins = < | ||
| 670 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 671 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 672 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 673 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 674 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 675 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 676 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 677 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 678 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 679 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 680 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 681 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 682 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 683 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 684 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 685 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 686 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | ||
| 687 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | ||
| 688 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ | ||
| 689 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ | ||
| 690 | >; | ||
| 691 | }; | ||
| 692 | }; | ||
| 693 | |||
| 694 | kpp { | ||
| 695 | pinctrl_kpp_1: kppgrp-1 { | ||
| 696 | fsl,pins = < | ||
| 697 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 698 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 699 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 700 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 701 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 702 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 703 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 704 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 705 | >; | ||
| 706 | }; | ||
| 707 | }; | ||
| 708 | |||
| 709 | pata { | ||
| 710 | pinctrl_pata_1: patagrp-1 { | ||
| 711 | fsl,pins = < | ||
| 712 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 713 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 714 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 715 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 716 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 717 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 718 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 719 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 720 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 721 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 722 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 723 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 724 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 725 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 726 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 727 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 728 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 729 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 730 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 731 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 732 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 733 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 734 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 735 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 736 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 737 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 738 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 739 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 740 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 741 | >; | ||
| 742 | }; | ||
| 743 | }; | ||
| 744 | |||
| 745 | uart1 { | ||
| 746 | pinctrl_uart1_1: uart1grp-1 { | ||
| 747 | fsl,pins = < | ||
| 748 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 749 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 750 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 751 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 752 | >; | ||
| 753 | }; | ||
| 754 | }; | ||
| 755 | |||
| 756 | uart2 { | ||
| 757 | pinctrl_uart2_1: uart2grp-1 { | ||
| 758 | fsl,pins = < | ||
| 759 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 760 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 761 | >; | ||
| 762 | }; | ||
| 763 | }; | ||
| 764 | |||
| 765 | uart3 { | ||
| 766 | pinctrl_uart3_1: uart3grp-1 { | ||
| 767 | fsl,pins = < | ||
| 768 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 769 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 770 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 771 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 772 | >; | ||
| 773 | }; | ||
| 774 | |||
| 775 | pinctrl_uart3_2: uart3grp-2 { | ||
| 776 | fsl,pins = < | ||
| 777 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 778 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 779 | >; | ||
| 780 | }; | ||
| 781 | }; | ||
| 782 | |||
| 783 | usbh1 { | ||
| 784 | pinctrl_usbh1_1: usbh1grp-1 { | ||
| 785 | fsl,pins = < | ||
| 786 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 787 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 788 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 789 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 790 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 791 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 792 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 793 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 794 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 795 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 796 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 797 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 798 | >; | ||
| 799 | }; | ||
| 800 | }; | ||
| 801 | |||
| 802 | usbh2 { | ||
| 803 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 804 | fsl,pins = < | ||
| 805 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 | ||
| 806 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 | ||
| 807 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 | ||
| 808 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 | ||
| 809 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 | ||
| 810 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 | ||
| 811 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 | ||
| 812 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 | ||
| 813 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 | ||
| 814 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 | ||
| 815 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 | ||
| 816 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 | ||
| 817 | >; | ||
| 818 | }; | ||
| 819 | }; | ||
| 820 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 512a1f608253..e97ddae09d74 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -93,6 +93,15 @@ | |||
| 93 | regulator-max-microvolt = <3200000>; | 93 | regulator-max-microvolt = <3200000>; |
| 94 | regulator-always-on; | 94 | regulator-always-on; |
| 95 | }; | 95 | }; |
| 96 | |||
| 97 | reg_usb_vbus: usb_vbus { | ||
| 98 | compatible = "regulator-fixed"; | ||
| 99 | regulator-name = "usb_vbus"; | ||
| 100 | regulator-min-microvolt = <5000000>; | ||
| 101 | regulator-max-microvolt = <5000000>; | ||
| 102 | gpio = <&gpio7 8 0>; | ||
| 103 | enable-active-high; | ||
| 104 | }; | ||
| 96 | }; | 105 | }; |
| 97 | 106 | ||
| 98 | sound { | 107 | sound { |
| @@ -145,6 +154,7 @@ | |||
| 145 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 | 154 | MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 |
| 146 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 | 155 | MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 |
| 147 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | 156 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
| 157 | MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 | ||
| 148 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 | 158 | MX53_PAD_GPIO_16__GPIO7_11 0x80000000 |
| 149 | >; | 159 | >; |
| 150 | }; | 160 | }; |
| @@ -297,8 +307,14 @@ | |||
| 297 | status = "okay"; | 307 | status = "okay"; |
| 298 | }; | 308 | }; |
| 299 | 309 | ||
| 310 | &vpu { | ||
| 311 | status = "okay"; | ||
| 312 | }; | ||
| 313 | |||
| 300 | &usbh1 { | 314 | &usbh1 { |
| 301 | status = "okay"; | 315 | vbus-supply = <®_usb_vbus>; |
| 316 | phy_type = "utmi"; | ||
| 317 | status = "okay"; | ||
| 302 | }; | 318 | }; |
| 303 | 319 | ||
| 304 | &usbotg { | 320 | &usbotg { |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 569aa9f2c4ed..4307e80b2d2e 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -15,11 +15,6 @@ | |||
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | aliases { | 17 | aliases { |
| 18 | serial0 = &uart1; | ||
| 19 | serial1 = &uart2; | ||
| 20 | serial2 = &uart3; | ||
| 21 | serial3 = &uart4; | ||
| 22 | serial4 = &uart5; | ||
| 23 | gpio0 = &gpio1; | 18 | gpio0 = &gpio1; |
| 24 | gpio1 = &gpio2; | 19 | gpio1 = &gpio2; |
| 25 | gpio2 = &gpio3; | 20 | gpio2 = &gpio3; |
| @@ -30,6 +25,24 @@ | |||
| 30 | i2c0 = &i2c1; | 25 | i2c0 = &i2c1; |
| 31 | i2c1 = &i2c2; | 26 | i2c1 = &i2c2; |
| 32 | i2c2 = &i2c3; | 27 | i2c2 = &i2c3; |
| 28 | serial0 = &uart1; | ||
| 29 | serial1 = &uart2; | ||
| 30 | serial2 = &uart3; | ||
| 31 | serial3 = &uart4; | ||
| 32 | serial4 = &uart5; | ||
| 33 | spi0 = &ecspi1; | ||
| 34 | spi1 = &ecspi2; | ||
| 35 | spi2 = &cspi; | ||
| 36 | }; | ||
| 37 | |||
| 38 | cpus { | ||
| 39 | #address-cells = <1>; | ||
| 40 | #size-cells = <0>; | ||
| 41 | cpu@0 { | ||
| 42 | device_type = "cpu"; | ||
| 43 | compatible = "arm,cortex-a8"; | ||
| 44 | reg = <0x0>; | ||
| 45 | }; | ||
| 33 | }; | 46 | }; |
| 34 | 47 | ||
| 35 | tzic: tz-interrupt-controller@0fffc000 { | 48 | tzic: tz-interrupt-controller@0fffc000 { |
| @@ -140,6 +153,9 @@ | |||
| 140 | reg = <0x50014000 0x4000>; | 153 | reg = <0x50014000 0x4000>; |
| 141 | interrupts = <30>; | 154 | interrupts = <30>; |
| 142 | clocks = <&clks 49>; | 155 | clocks = <&clks 49>; |
| 156 | dmas = <&sdma 24 1 0>, | ||
| 157 | <&sdma 25 1 0>; | ||
| 158 | dma-names = "rx", "tx"; | ||
| 143 | fsl,fifo-depth = <15>; | 159 | fsl,fifo-depth = <15>; |
| 144 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | 160 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ |
| 145 | status = "disabled"; | 161 | status = "disabled"; |
| @@ -957,6 +973,13 @@ | |||
| 957 | reg = <0x60000000 0x10000000>; | 973 | reg = <0x60000000 0x10000000>; |
| 958 | ranges; | 974 | ranges; |
| 959 | 975 | ||
| 976 | iim: iim@63f98000 { | ||
| 977 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | ||
| 978 | reg = <0x63f98000 0x4000>; | ||
| 979 | interrupts = <69>; | ||
| 980 | clocks = <&clks 107>; | ||
| 981 | }; | ||
| 982 | |||
| 960 | uart5: serial@63f90000 { | 983 | uart5: serial@63f90000 { |
| 961 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; | 984 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 962 | reg = <0x63f90000 0x4000>; | 985 | reg = <0x63f90000 0x4000>; |
| @@ -990,6 +1013,7 @@ | |||
| 990 | interrupts = <6>; | 1013 | interrupts = <6>; |
| 991 | clocks = <&clks 56>, <&clks 56>; | 1014 | clocks = <&clks 56>, <&clks 56>; |
| 992 | clock-names = "ipg", "ahb"; | 1015 | clock-names = "ipg", "ahb"; |
| 1016 | #dma-cells = <3>; | ||
| 993 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; | 1017 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 994 | }; | 1018 | }; |
| 995 | 1019 | ||
| @@ -1029,6 +1053,9 @@ | |||
| 1029 | reg = <0x63fcc000 0x4000>; | 1053 | reg = <0x63fcc000 0x4000>; |
| 1030 | interrupts = <29>; | 1054 | interrupts = <29>; |
| 1031 | clocks = <&clks 48>; | 1055 | clocks = <&clks 48>; |
| 1056 | dmas = <&sdma 28 0 0>, | ||
| 1057 | <&sdma 29 0 0>; | ||
| 1058 | dma-names = "rx", "tx"; | ||
| 1032 | fsl,fifo-depth = <15>; | 1059 | fsl,fifo-depth = <15>; |
| 1033 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | 1060 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ |
| 1034 | status = "disabled"; | 1061 | status = "disabled"; |
| @@ -1053,6 +1080,9 @@ | |||
| 1053 | reg = <0x63fe8000 0x4000>; | 1080 | reg = <0x63fe8000 0x4000>; |
| 1054 | interrupts = <96>; | 1081 | interrupts = <96>; |
| 1055 | clocks = <&clks 50>; | 1082 | clocks = <&clks 50>; |
| 1083 | dmas = <&sdma 46 0 0>, | ||
| 1084 | <&sdma 47 0 0>; | ||
| 1085 | dma-names = "rx", "tx"; | ||
| 1056 | fsl,fifo-depth = <15>; | 1086 | fsl,fifo-depth = <15>; |
| 1057 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ | 1087 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ |
| 1058 | status = "disabled"; | 1088 | status = "disabled"; |
| @@ -1076,6 +1106,22 @@ | |||
| 1076 | crtcs = <&ipu 1>; | 1106 | crtcs = <&ipu 1>; |
| 1077 | status = "disabled"; | 1107 | status = "disabled"; |
| 1078 | }; | 1108 | }; |
| 1109 | |||
| 1110 | vpu: vpu@63ff4000 { | ||
| 1111 | compatible = "fsl,imx53-vpu"; | ||
| 1112 | reg = <0x63ff4000 0x1000>; | ||
| 1113 | interrupts = <9>; | ||
| 1114 | clocks = <&clks 63>, <&clks 63>; | ||
| 1115 | clock-names = "per", "ahb"; | ||
| 1116 | iram = <&ocram>; | ||
| 1117 | status = "disabled"; | ||
| 1118 | }; | ||
| 1119 | }; | ||
| 1120 | |||
| 1121 | ocram: sram@f8000000 { | ||
| 1122 | compatible = "mmio-sram"; | ||
| 1123 | reg = <0xf8000000 0x20000>; | ||
| 1124 | clocks = <&clks 186>; | ||
| 1079 | }; | 1125 | }; |
| 1080 | }; | 1126 | }; |
| 1081 | }; | 1127 | }; |
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index 9aab950ec269..b81a7a4ebab6 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h | |||
| @@ -14,1072 +14,1076 @@ | |||
| 14 | * The pin function ID is a tuple of | 14 | * The pin function ID is a tuple of |
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | 15 | * <mux_reg conf_reg input_reg mux_mode input_val> |
| 16 | */ | 16 | */ |
| 17 | #define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 | 17 | #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 |
| 18 | #define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 | 18 | #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 |
| 19 | #define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 | 19 | #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 |
| 20 | #define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 | 20 | #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 |
| 21 | #define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 | 21 | #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 |
| 22 | #define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 | 22 | #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 |
| 23 | #define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 | 23 | #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 |
| 24 | #define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 | 24 | #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 |
| 25 | #define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 | 25 | #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 |
| 26 | #define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 | 26 | #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 |
| 27 | #define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 | 27 | #define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 |
| 28 | #define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 | 28 | #define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 |
| 29 | #define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 | 29 | #define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 |
| 30 | #define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 | 30 | #define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 |
| 31 | #define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 | 31 | #define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 |
| 32 | #define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 | 32 | #define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 |
| 33 | #define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 | 33 | #define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 |
| 34 | #define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 | 34 | #define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 |
| 35 | #define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 | 35 | #define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 |
| 36 | #define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 | 36 | #define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 |
| 37 | #define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 | 37 | #define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 |
| 38 | #define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 | 38 | #define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 |
| 39 | #define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 | 39 | #define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 |
| 40 | #define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 | 40 | #define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 |
| 41 | #define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 | 41 | #define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 |
| 42 | #define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 | 42 | #define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 |
| 43 | #define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 | 43 | #define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 |
| 44 | #define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 | 44 | #define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 |
| 45 | #define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 | 45 | #define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 |
| 46 | #define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 | 46 | #define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 |
| 47 | #define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 | 47 | #define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 |
| 48 | #define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 | 48 | #define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 |
| 49 | #define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 | 49 | #define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 |
| 50 | #define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 | 50 | #define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 |
| 51 | #define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 | 51 | #define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 |
| 52 | #define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 | 52 | #define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 |
| 53 | #define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 | 53 | #define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 |
| 54 | #define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 | 54 | #define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 |
| 55 | #define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 | 55 | #define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 |
| 56 | #define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 | 56 | #define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 |
| 57 | #define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 | 57 | #define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 |
| 58 | #define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 | 58 | #define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 |
| 59 | #define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 | 59 | #define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 |
| 60 | #define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 | 60 | #define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 |
| 61 | #define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 | 61 | #define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 |
| 62 | #define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 | 62 | #define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 |
| 63 | #define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 | 63 | #define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 |
| 64 | #define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 | 64 | #define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 |
| 65 | #define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 | 65 | #define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 |
| 66 | #define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 | 66 | #define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 |
| 67 | #define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 | 67 | #define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 |
| 68 | #define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 | 68 | #define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 |
| 69 | #define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 | 69 | #define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 |
| 70 | #define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 | 70 | #define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 |
| 71 | #define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 | 71 | #define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 |
| 72 | #define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 | 72 | #define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 |
| 73 | #define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 | 73 | #define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 |
| 74 | #define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 | 74 | #define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 |
| 75 | #define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 | 75 | #define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 |
| 76 | #define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 | 76 | #define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 |
| 77 | #define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 | 77 | #define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 |
| 78 | #define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 | 78 | #define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 |
| 79 | #define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 | 79 | #define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 |
| 80 | #define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 | 80 | #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 |
| 81 | #define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 | 81 | #define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 |
| 82 | #define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 | 82 | #define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 |
| 83 | #define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 | 83 | #define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 |
| 84 | #define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 | 84 | #define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 |
| 85 | #define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 | 85 | #define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 |
| 86 | #define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 | 86 | #define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 |
| 87 | #define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 | 87 | #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 |
| 88 | #define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 | 88 | #define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 |
| 89 | #define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 | 89 | #define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 |
| 90 | #define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 | 90 | #define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 |
| 91 | #define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 | 91 | #define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 |
| 92 | #define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 | 92 | #define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 |
| 93 | #define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 | 93 | #define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 |
| 94 | #define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 | 94 | #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 |
| 95 | #define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 | 95 | #define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 |
| 96 | #define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 | 96 | #define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 |
| 97 | #define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 | 97 | #define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 |
| 98 | #define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 | 98 | #define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 |
| 99 | #define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 | 99 | #define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 |
| 100 | #define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 | 100 | #define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 |
| 101 | #define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 | 101 | #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 |
| 102 | #define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 | 102 | #define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 |
| 103 | #define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 | 103 | #define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 |
| 104 | #define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 | 104 | #define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 |
| 105 | #define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 | 105 | #define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 |
| 106 | #define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 | 106 | #define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 |
| 107 | #define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 | 107 | #define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 |
| 108 | #define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 | 108 | #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 |
| 109 | #define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 | 109 | #define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 |
| 110 | #define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 | 110 | #define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 |
| 111 | #define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 | 111 | #define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 |
| 112 | #define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 | 112 | #define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 |
| 113 | #define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 | 113 | #define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 |
| 114 | #define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 | 114 | #define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 |
| 115 | #define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 | 115 | #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 |
| 116 | #define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 | 116 | #define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 |
| 117 | #define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 | 117 | #define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 |
| 118 | #define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 | 118 | #define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 |
| 119 | #define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 | 119 | #define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 |
| 120 | #define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 | 120 | #define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 |
| 121 | #define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 | 121 | #define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 |
| 122 | #define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 | 122 | #define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 |
| 123 | #define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 | 123 | #define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 |
| 124 | #define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 | 124 | #define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 |
| 125 | #define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 | 125 | #define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 |
| 126 | #define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 | 126 | #define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 |
| 127 | #define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 | 127 | #define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 |
| 128 | #define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 | 128 | #define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 |
| 129 | #define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 | 129 | #define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 |
| 130 | #define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 | 130 | #define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 |
| 131 | #define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 | 131 | #define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 |
| 132 | #define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 | 132 | #define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 |
| 133 | #define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 | 133 | #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 |
| 134 | #define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 | 134 | #define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 |
| 135 | #define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 | 135 | #define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 |
| 136 | #define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 | 136 | #define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 |
| 137 | #define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 | 137 | #define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 |
| 138 | #define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 | 138 | #define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 |
| 139 | #define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 | 139 | #define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 |
| 140 | #define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 | 140 | #define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 |
| 141 | #define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 | 141 | #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 |
| 142 | #define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 | 142 | #define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 |
| 143 | #define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 | 143 | #define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 |
| 144 | #define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 | 144 | #define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 |
| 145 | #define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 | 145 | #define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 |
| 146 | #define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 | 146 | #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 |
| 147 | #define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 | 147 | #define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 |
| 148 | #define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 | 148 | #define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 |
| 149 | #define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 | 149 | #define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 |
| 150 | #define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 | 150 | #define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 |
| 151 | #define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 | 151 | #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 |
| 152 | #define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 | 152 | #define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 |
| 153 | #define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 | 153 | #define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 |
| 154 | #define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 | 154 | #define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 |
| 155 | #define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 | 155 | #define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 |
| 156 | #define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 | 156 | #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 |
| 157 | #define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 | 157 | #define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 |
| 158 | #define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 | 158 | #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 |
| 159 | #define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 | 159 | #define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 |
| 160 | #define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 | 160 | #define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 |
| 161 | #define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 | 161 | #define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 |
| 162 | #define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 | 162 | #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 |
| 163 | #define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 | 163 | #define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 |
| 164 | #define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 | 164 | #define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 |
| 165 | #define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 | 165 | #define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 |
| 166 | #define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 | 166 | #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 |
| 167 | #define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 | 167 | #define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 |
| 168 | #define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 | 168 | #define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 |
| 169 | #define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 | 169 | #define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 |
| 170 | #define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 | 170 | #define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 |
| 171 | #define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 | 171 | #define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 |
| 172 | #define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 | 172 | #define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 |
| 173 | #define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 | 173 | #define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 |
| 174 | #define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 | 174 | #define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 |
| 175 | #define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 | 175 | #define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 |
| 176 | #define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 | 176 | #define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 |
| 177 | #define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 | 177 | #define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 |
| 178 | #define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 | 178 | #define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 |
| 179 | #define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 | 179 | #define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 |
| 180 | #define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 | 180 | #define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 |
| 181 | #define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 | 181 | #define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 |
| 182 | #define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 | 182 | #define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 |
| 183 | #define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 | 183 | #define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 |
| 184 | #define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 | 184 | #define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 |
| 185 | #define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 | 185 | #define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 |
| 186 | #define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 | 186 | #define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 |
| 187 | #define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 | 187 | #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 |
| 188 | #define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 | 188 | #define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 |
| 189 | #define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 | 189 | #define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 |
| 190 | #define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 | 190 | #define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 |
| 191 | #define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 | 191 | #define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 |
| 192 | #define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 | 192 | #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 |
| 193 | #define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 | 193 | #define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 |
| 194 | #define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 | 194 | #define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 |
| 195 | #define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 | 195 | #define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 |
| 196 | #define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 | 196 | #define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 |
| 197 | #define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 | 197 | #define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 |
| 198 | #define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 | 198 | #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 |
| 199 | #define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 | 199 | #define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 |
| 200 | #define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 | 200 | #define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 |
| 201 | #define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 | 201 | #define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 |
| 202 | #define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 | 202 | #define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 |
| 203 | #define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 | 203 | #define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 |
| 204 | #define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 | 204 | #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 |
| 205 | #define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 | 205 | #define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 |
| 206 | #define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 | 206 | #define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 |
| 207 | #define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 | 207 | #define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 |
| 208 | #define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 | 208 | #define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 |
| 209 | #define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 | 209 | #define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 |
| 210 | #define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 | 210 | #define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 |
| 211 | #define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 | 211 | #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 |
| 212 | #define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 | 212 | #define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 |
| 213 | #define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 | 213 | #define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 |
| 214 | #define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 | 214 | #define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 |
| 215 | #define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 | 215 | #define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 |
| 216 | #define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 | 216 | #define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 |
| 217 | #define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 | 217 | #define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 |
| 218 | #define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 | 218 | #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 |
| 219 | #define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 | 219 | #define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 |
| 220 | #define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 | 220 | #define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 |
| 221 | #define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 | 221 | #define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 |
| 222 | #define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 | 222 | #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 |
| 223 | #define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 | 223 | #define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 |
| 224 | #define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 | 224 | #define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 |
| 225 | #define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 | 225 | #define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 |
| 226 | #define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 | 226 | #define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 |
| 227 | #define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 | 227 | #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 |
| 228 | #define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 | 228 | #define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 |
| 229 | #define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 | 229 | #define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 |
| 230 | #define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 | 230 | #define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 |
| 231 | #define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 | 231 | #define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 |
| 232 | #define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 | 232 | #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 |
| 233 | #define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 | 233 | #define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 |
| 234 | #define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 | 234 | #define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 |
| 235 | #define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 | 235 | #define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 |
| 236 | #define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 | 236 | #define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 |
| 237 | #define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 | 237 | #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 |
| 238 | #define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 | 238 | #define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 |
| 239 | #define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 | 239 | #define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 |
| 240 | #define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 | 240 | #define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 |
| 241 | #define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 | 241 | #define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 |
| 242 | #define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 | 242 | #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 |
| 243 | #define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 | 243 | #define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 |
| 244 | #define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 | 244 | #define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 |
| 245 | #define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 | 245 | #define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 |
| 246 | #define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 | 246 | #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 |
| 247 | #define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 | 247 | #define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 |
| 248 | #define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 | 248 | #define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 |
| 249 | #define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 | 249 | #define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 |
| 250 | #define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 | 250 | #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 |
| 251 | #define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 | 251 | #define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 |
| 252 | #define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 | 252 | #define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 |
| 253 | #define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 | 253 | #define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 |
| 254 | #define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 | 254 | #define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 |
| 255 | #define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 | 255 | #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 |
| 256 | #define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 | 256 | #define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 |
| 257 | #define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 | 257 | #define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 |
| 258 | #define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 | 258 | #define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 |
| 259 | #define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 | 259 | #define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 |
| 260 | #define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 | 260 | #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 |
| 261 | #define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 | 261 | #define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 |
| 262 | #define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 | 262 | #define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 |
| 263 | #define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 | 263 | #define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 |
| 264 | #define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 | 264 | #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 |
| 265 | #define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 | 265 | #define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 |
| 266 | #define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 | 266 | #define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 |
| 267 | #define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 | 267 | #define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 |
| 268 | #define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 | 268 | #define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 |
| 269 | #define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 | 269 | #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 |
| 270 | #define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 | 270 | #define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 |
| 271 | #define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 | 271 | #define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 |
| 272 | #define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 | 272 | #define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 |
| 273 | #define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 | 273 | #define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 |
| 274 | #define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 | 274 | #define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 |
| 275 | #define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 | 275 | #define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 |
| 276 | #define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 | 276 | #define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 |
| 277 | #define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 | 277 | #define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 |
| 278 | #define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 | 278 | #define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 |
| 279 | #define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 | 279 | #define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 |
| 280 | #define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 | 280 | #define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 |
| 281 | #define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 | 281 | #define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 |
| 282 | #define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 | 282 | #define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 |
| 283 | #define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 | 283 | #define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 |
| 284 | #define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 | 284 | #define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 |
| 285 | #define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 | 285 | #define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 |
| 286 | #define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 | 286 | #define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 |
| 287 | #define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 | 287 | #define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 |
| 288 | #define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 | 288 | #define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 |
| 289 | #define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 | 289 | #define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 |
| 290 | #define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 | 290 | #define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 |
| 291 | #define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 | 291 | #define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 |
| 292 | #define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 | 292 | #define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 |
| 293 | #define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 | 293 | #define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 |
| 294 | #define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 | 294 | #define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 |
| 295 | #define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 | 295 | #define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 |
| 296 | #define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 | 296 | #define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 |
| 297 | #define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 | 297 | #define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 |
| 298 | #define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 | 298 | #define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 |
| 299 | #define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 | 299 | #define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 |
| 300 | #define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 | 300 | #define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 |
| 301 | #define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 | 301 | #define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 |
| 302 | #define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 | 302 | #define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 |
| 303 | #define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 | 303 | #define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 |
| 304 | #define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 | 304 | #define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 |
| 305 | #define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 | 305 | #define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 |
| 306 | #define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 | 306 | #define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 |
| 307 | #define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 | 307 | #define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 |
| 308 | #define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 | 308 | #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 |
| 309 | #define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 | 309 | #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 |
| 310 | #define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 | 310 | #define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 |
| 311 | #define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 | 311 | #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 |
| 312 | #define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 | 312 | #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 |
| 313 | #define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 | 313 | #define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 |
| 314 | #define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 | 314 | #define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 |
| 315 | #define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 | 315 | #define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 |
| 316 | #define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 | 316 | #define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 |
| 317 | #define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 | 317 | #define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 |
| 318 | #define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 | 318 | #define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 |
| 319 | #define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 | 319 | #define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 |
| 320 | #define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 | 320 | #define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 |
| 321 | #define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 | 321 | #define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 |
| 322 | #define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 | 322 | #define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 |
| 323 | #define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 | 323 | #define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 |
| 324 | #define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 | 324 | #define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 |
| 325 | #define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 | 325 | #define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 |
| 326 | #define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 | 326 | #define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 |
| 327 | #define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 | 327 | #define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 |
| 328 | #define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 | 328 | #define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 |
| 329 | #define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 | 329 | #define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 |
| 330 | #define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 | 330 | #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 |
| 331 | #define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 | 331 | #define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 |
| 332 | #define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 | 332 | #define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 |
| 333 | #define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 | 333 | #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 |
| 334 | #define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 | 334 | #define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 |
| 335 | #define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 | 335 | #define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 |
| 336 | #define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 | 336 | #define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 |
| 337 | #define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 | 337 | #define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 |
| 338 | #define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 | 338 | #define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 |
| 339 | #define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 | 339 | #define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 |
| 340 | #define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 | 340 | #define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 |
| 341 | #define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 | 341 | #define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 |
| 342 | #define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 | 342 | #define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 |
| 343 | #define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 | 343 | #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 |
| 344 | #define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 | 344 | #define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 |
| 345 | #define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 | 345 | #define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 |
| 346 | #define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 | 346 | #define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 |
| 347 | #define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 | 347 | #define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 |
| 348 | #define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 | 348 | #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 |
| 349 | #define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 | 349 | #define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 |
| 350 | #define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 | 350 | #define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 |
| 351 | #define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 | 351 | #define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 |
| 352 | #define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 | 352 | #define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 |
| 353 | #define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 | 353 | #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 |
| 354 | #define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 | 354 | #define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 |
| 355 | #define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 | 355 | #define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 |
| 356 | #define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 | 356 | #define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 |
| 357 | #define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 | 357 | #define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 |
| 358 | #define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 | 358 | #define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 |
| 359 | #define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 | 359 | #define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 |
| 360 | #define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 | 360 | #define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 |
| 361 | #define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 | 361 | #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 |
| 362 | #define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 | 362 | #define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 |
| 363 | #define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 | 363 | #define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 |
| 364 | #define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 | 364 | #define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 |
| 365 | #define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 | 365 | #define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 |
| 366 | #define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 | 366 | #define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 |
| 367 | #define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 | 367 | #define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 |
| 368 | #define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 | 368 | #define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 |
| 369 | #define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 | 369 | #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 |
| 370 | #define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 | 370 | #define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 |
| 371 | #define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 | 371 | #define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 |
| 372 | #define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 | 372 | #define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 |
| 373 | #define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 | 373 | #define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 |
| 374 | #define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 | 374 | #define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 |
| 375 | #define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 | 375 | #define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 |
| 376 | #define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 | 376 | #define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 |
| 377 | #define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 | 377 | #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 |
| 378 | #define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 | 378 | #define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 |
| 379 | #define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 | 379 | #define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 |
| 380 | #define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 | 380 | #define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 |
| 381 | #define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 | 381 | #define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 |
| 382 | #define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 | 382 | #define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 |
| 383 | #define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 | 383 | #define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 |
| 384 | #define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 | 384 | #define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 |
| 385 | #define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 | 385 | #define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 |
| 386 | #define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 | 386 | #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 |
| 387 | #define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 | 387 | #define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 |
| 388 | #define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 | 388 | #define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 |
| 389 | #define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 | 389 | #define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 |
| 390 | #define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 | 390 | #define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 |
| 391 | #define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 | 391 | #define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 |
| 392 | #define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 | 392 | #define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 |
| 393 | #define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 | 393 | #define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 |
| 394 | #define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 | 394 | #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 |
| 395 | #define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 | 395 | #define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 |
| 396 | #define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 | 396 | #define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 |
| 397 | #define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 | 397 | #define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 |
| 398 | #define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 | 398 | #define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 |
| 399 | #define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 | 399 | #define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 |
| 400 | #define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 | 400 | #define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 |
| 401 | #define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 | 401 | #define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 |
| 402 | #define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 | 402 | #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 |
| 403 | #define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 | 403 | #define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 |
| 404 | #define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 | 404 | #define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 |
| 405 | #define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 | 405 | #define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 |
| 406 | #define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 | 406 | #define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 |
| 407 | #define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 | 407 | #define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 |
| 408 | #define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 | 408 | #define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 |
| 409 | #define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 | 409 | #define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 |
| 410 | #define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 | 410 | #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 |
| 411 | #define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 | 411 | #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 |
| 412 | #define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 | 412 | #define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 |
| 413 | #define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 | 413 | #define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 |
| 414 | #define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 | 414 | #define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 |
| 415 | #define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 | 415 | #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 |
| 416 | #define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 | 416 | #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 |
| 417 | #define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 | 417 | #define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 |
| 418 | #define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 | 418 | #define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 |
| 419 | #define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 | 419 | #define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 |
| 420 | #define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 | 420 | #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 |
| 421 | #define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 | 421 | #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 |
| 422 | #define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 | 422 | #define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 |
| 423 | #define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 | 423 | #define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 |
| 424 | #define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 | 424 | #define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 |
| 425 | #define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 | 425 | #define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 |
| 426 | #define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 | 426 | #define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 |
| 427 | #define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 | 427 | #define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 |
| 428 | #define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 | 428 | #define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 |
| 429 | #define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 | 429 | #define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 |
| 430 | #define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 | 430 | #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 |
| 431 | #define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 | 431 | #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 |
| 432 | #define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 | 432 | #define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 |
| 433 | #define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 | 433 | #define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 |
| 434 | #define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 | 434 | #define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 |
| 435 | #define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 | 435 | #define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 |
| 436 | #define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 | 436 | #define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 |
| 437 | #define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 | 437 | #define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 |
| 438 | #define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 | 438 | #define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 |
| 439 | #define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 | 439 | #define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 |
| 440 | #define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 | 440 | #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 |
| 441 | #define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 | 441 | #define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 |
| 442 | #define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 | 442 | #define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 |
| 443 | #define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 | 443 | #define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 |
| 444 | #define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 | 444 | #define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 |
| 445 | #define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 | 445 | #define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 |
| 446 | #define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 | 446 | #define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 |
| 447 | #define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 | 447 | #define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 |
| 448 | #define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 | 448 | #define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 |
| 449 | #define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 | 449 | #define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 |
| 450 | #define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 | 450 | #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 |
| 451 | #define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 | 451 | #define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 |
| 452 | #define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 | 452 | #define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 |
| 453 | #define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 | 453 | #define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 |
| 454 | #define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 | 454 | #define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 |
| 455 | #define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 | 455 | #define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 |
| 456 | #define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 | 456 | #define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 |
| 457 | #define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 | 457 | #define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 |
| 458 | #define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 | 458 | #define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 |
| 459 | #define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 | 459 | #define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 |
| 460 | #define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 | 460 | #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 |
| 461 | #define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 | 461 | #define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 |
| 462 | #define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 | 462 | #define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 |
| 463 | #define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 | 463 | #define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 |
| 464 | #define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 | 464 | #define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 |
| 465 | #define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 | 465 | #define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 |
| 466 | #define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 | 466 | #define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 |
| 467 | #define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 | 467 | #define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 |
| 468 | #define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 | 468 | #define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 |
| 469 | #define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 | 469 | #define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 |
| 470 | #define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 | 470 | #define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 |
| 471 | #define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 | 471 | #define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 |
| 472 | #define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 | 472 | #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 |
| 473 | #define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 | 473 | #define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 |
| 474 | #define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 | 474 | #define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 |
| 475 | #define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 | 475 | #define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 |
| 476 | #define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 | 476 | #define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 |
| 477 | #define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 | 477 | #define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 |
| 478 | #define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 | 478 | #define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 |
| 479 | #define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 | 479 | #define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 |
| 480 | #define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 | 480 | #define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 |
| 481 | #define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 | 481 | #define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 |
| 482 | #define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 | 482 | #define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 |
| 483 | #define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 | 483 | #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 |
| 484 | #define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 | 484 | #define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 |
| 485 | #define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 | 485 | #define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 |
| 486 | #define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 | 486 | #define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 |
| 487 | #define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 | 487 | #define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 |
| 488 | #define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 | 488 | #define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 |
| 489 | #define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 | 489 | #define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 |
| 490 | #define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 | 490 | #define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 |
| 491 | #define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 | 491 | #define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 |
| 492 | #define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 | 492 | #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 |
| 493 | #define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 | 493 | #define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 |
| 494 | #define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 | 494 | #define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 |
| 495 | #define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 | 495 | #define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 |
| 496 | #define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 | 496 | #define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 |
| 497 | #define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 | 497 | #define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 |
| 498 | #define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 | 498 | #define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 |
| 499 | #define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 | 499 | #define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 |
| 500 | #define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 | 500 | #define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 |
| 501 | #define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 | 501 | #define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 |
| 502 | #define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 | 502 | #define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 |
| 503 | #define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 | 503 | #define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 |
| 504 | #define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 | 504 | #define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 |
| 505 | #define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 | 505 | #define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 |
| 506 | #define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 | 506 | #define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 |
| 507 | #define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 | 507 | #define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 |
| 508 | #define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 | 508 | #define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 |
| 509 | #define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 | 509 | #define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 |
| 510 | #define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 | 510 | #define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 |
| 511 | #define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 | 511 | #define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 |
| 512 | #define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 | 512 | #define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 |
| 513 | #define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 | 513 | #define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 |
| 514 | #define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 | 514 | #define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 |
| 515 | #define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 | 515 | #define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 |
| 516 | #define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 | 516 | #define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 |
| 517 | #define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 | 517 | #define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 |
| 518 | #define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 | 518 | #define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 |
| 519 | #define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 | 519 | #define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 |
| 520 | #define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 | 520 | #define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 |
| 521 | #define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 | 521 | #define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 |
| 522 | #define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 | 522 | #define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 |
| 523 | #define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 | 523 | #define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 |
| 524 | #define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 | 524 | #define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 |
| 525 | #define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 | 525 | #define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 |
| 526 | #define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 | 526 | #define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 |
| 527 | #define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 | 527 | #define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 |
| 528 | #define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 | 528 | #define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 |
| 529 | #define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 | 529 | #define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 |
| 530 | #define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 | 530 | #define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 |
| 531 | #define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 | 531 | #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 |
| 532 | #define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 | 532 | #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 |
| 533 | #define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 | 533 | #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 |
| 534 | #define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 | 534 | #define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 |
| 535 | #define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 | 535 | #define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 |
| 536 | #define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 | 536 | #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 |
| 537 | #define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 | 537 | #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 |
| 538 | #define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 | 538 | #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 |
| 539 | #define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 | 539 | #define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 |
| 540 | #define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 | 540 | #define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 |
| 541 | #define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 | 541 | #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 |
| 542 | #define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 | 542 | #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 |
| 543 | #define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 | 543 | #define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 |
| 544 | #define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 | 544 | #define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 |
| 545 | #define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 | 545 | #define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 |
| 546 | #define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 | 546 | #define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 |
| 547 | #define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 | 547 | #define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 |
| 548 | #define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 | 548 | #define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 |
| 549 | #define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 | 549 | #define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 |
| 550 | #define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 | 550 | #define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 |
| 551 | #define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 | 551 | #define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 |
| 552 | #define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 | 552 | #define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 |
| 553 | #define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 | 553 | #define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 |
| 554 | #define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 | 554 | #define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 |
| 555 | #define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 | 555 | #define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 |
| 556 | #define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 | 556 | #define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 |
| 557 | #define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 | 557 | #define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 |
| 558 | #define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 | 558 | #define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 |
| 559 | #define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 | 559 | #define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 |
| 560 | #define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 | 560 | #define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 |
| 561 | #define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 | 561 | #define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 |
| 562 | #define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 | 562 | #define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 |
| 563 | #define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 | 563 | #define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 |
| 564 | #define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 | 564 | #define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 |
| 565 | #define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 | 565 | #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 |
| 566 | #define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 | 566 | #define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 |
| 567 | #define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 | 567 | #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 |
| 568 | #define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 | 568 | #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 |
| 569 | #define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 | 569 | #define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 |
| 570 | #define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 | 570 | #define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 |
| 571 | #define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 | 571 | #define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 |
| 572 | #define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 | 572 | #define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 |
| 573 | #define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 | 573 | #define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 |
| 574 | #define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 | 574 | #define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 |
| 575 | #define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 | 575 | #define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 |
| 576 | #define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 | 576 | #define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 |
| 577 | #define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 | 577 | #define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 |
| 578 | #define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 | 578 | #define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 |
| 579 | #define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 | 579 | #define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 |
| 580 | #define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 | 580 | #define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 |
| 581 | #define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 | 581 | #define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 |
| 582 | #define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 | 582 | #define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 |
| 583 | #define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 | 583 | #define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 |
| 584 | #define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 | 584 | #define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 |
| 585 | #define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 | 585 | #define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 |
| 586 | #define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 | 586 | #define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 |
| 587 | #define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 | 587 | #define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 |
| 588 | #define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 | 588 | #define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 |
| 589 | #define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 | 589 | #define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 |
| 590 | #define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 | 590 | #define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 |
| 591 | #define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 | 591 | #define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 |
| 592 | #define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 | 592 | #define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 |
| 593 | #define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 | 593 | #define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 |
| 594 | #define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 | 594 | #define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 |
| 595 | #define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 | 595 | #define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 |
| 596 | #define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 | 596 | #define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 |
| 597 | #define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 | 597 | #define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 |
| 598 | #define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 | 598 | #define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 |
| 599 | #define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 | 599 | #define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 |
| 600 | #define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 | 600 | #define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 |
| 601 | #define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 | 601 | #define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 |
| 602 | #define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 | 602 | #define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 |
| 603 | #define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 | 603 | #define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 |
| 604 | #define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 | 604 | #define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 |
| 605 | #define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 | 605 | #define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 |
| 606 | #define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 | 606 | #define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 |
| 607 | #define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 | 607 | #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 |
| 608 | #define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 | 608 | #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 |
| 609 | #define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 | 609 | #define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 |
| 610 | #define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 | 610 | #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 |
| 611 | #define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 | 611 | #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 |
| 612 | #define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 | 612 | #define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 |
| 613 | #define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 | 613 | #define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 |
| 614 | #define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 | 614 | #define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 |
| 615 | #define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 | 615 | #define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 |
| 616 | #define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 | 616 | #define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 |
| 617 | #define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 | 617 | #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 |
| 618 | #define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 | 618 | #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 |
| 619 | #define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 | 619 | #define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 |
| 620 | #define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 | 620 | #define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 |
| 621 | #define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 | 621 | #define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 |
| 622 | #define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 | 622 | #define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 |
| 623 | #define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 | 623 | #define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 |
| 624 | #define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 | 624 | #define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 |
| 625 | #define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 | 625 | #define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 |
| 626 | #define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 | 626 | #define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 |
| 627 | #define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 | 627 | #define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 |
| 628 | #define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 | 628 | #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 |
| 629 | #define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 | 629 | #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 |
| 630 | #define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 | 630 | #define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 |
| 631 | #define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 | 631 | #define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 |
| 632 | #define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 | 632 | #define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 |
| 633 | #define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 | 633 | #define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 |
| 634 | #define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 | 634 | #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 |
| 635 | #define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 | 635 | #define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 |
| 636 | #define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 | 636 | #define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 |
| 637 | #define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 | 637 | #define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 |
| 638 | #define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 | 638 | #define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 |
| 639 | #define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 | 639 | #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 |
| 640 | #define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 | 640 | #define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 |
| 641 | #define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 | 641 | #define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 |
| 642 | #define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 | 642 | #define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 |
| 643 | #define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 | 643 | #define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 |
| 644 | #define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 | 644 | #define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 |
| 645 | #define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 | 645 | #define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 |
| 646 | #define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 | 646 | #define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 |
| 647 | #define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 | 647 | #define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 |
| 648 | #define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 | 648 | #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 |
| 649 | #define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 | 649 | #define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 |
| 650 | #define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 | 650 | #define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 |
| 651 | #define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 | 651 | #define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 |
| 652 | #define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 | 652 | #define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 |
| 653 | #define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 | 653 | #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 |
| 654 | #define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 | 654 | #define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 |
| 655 | #define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 | 655 | #define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 |
| 656 | #define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 | 656 | #define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 |
| 657 | #define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 | 657 | #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 |
| 658 | #define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 | 658 | #define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 |
| 659 | #define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 | 659 | #define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 |
| 660 | #define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 | 660 | #define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 |
| 661 | #define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 | 661 | #define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 |
| 662 | #define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 | 662 | #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 |
| 663 | #define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 | 663 | #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 |
| 664 | #define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 | 664 | #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 |
| 665 | #define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 | 665 | #define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 |
| 666 | #define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 | 666 | #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 |
| 667 | #define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 | 667 | #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 |
| 668 | #define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 | 668 | #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 |
| 669 | #define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 | 669 | #define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 |
| 670 | #define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 | 670 | #define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 |
| 671 | #define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 | 671 | #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 |
| 672 | #define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 | 672 | #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 |
| 673 | #define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 | 673 | #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 |
| 674 | #define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 | 674 | #define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 |
| 675 | #define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 | 675 | #define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 |
| 676 | #define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 | 676 | #define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 |
| 677 | #define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 | 677 | #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 |
| 678 | #define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 | 678 | #define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 |
| 679 | #define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 | 679 | #define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 |
| 680 | #define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 | 680 | #define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 |
| 681 | #define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 | 681 | #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 |
| 682 | #define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 | 682 | #define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 |
| 683 | #define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 | 683 | #define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 |
| 684 | #define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 | 684 | #define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 |
| 685 | #define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 | 685 | #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 |
| 686 | #define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 | 686 | #define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 |
| 687 | #define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 | 687 | #define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 |
| 688 | #define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 | 688 | #define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 |
| 689 | #define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 | 689 | #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 |
| 690 | #define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 | 690 | #define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 |
| 691 | #define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 | 691 | #define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 |
| 692 | #define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 | 692 | #define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 |
| 693 | #define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 | 693 | #define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 |
| 694 | #define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 | 694 | #define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 |
| 695 | #define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 | 695 | #define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 |
| 696 | #define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 | 696 | #define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 |
| 697 | #define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 | 697 | #define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 |
| 698 | #define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 | 698 | #define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 |
| 699 | #define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 | 699 | #define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 |
| 700 | #define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 | 700 | #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 |
| 701 | #define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 | 701 | #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 |
| 702 | #define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 | 702 | #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 |
| 703 | #define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 | 703 | #define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 |
| 704 | #define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 | 704 | #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 |
| 705 | #define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 | 705 | #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 |
| 706 | #define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 | 706 | #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 |
| 707 | #define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 | 707 | #define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 |
| 708 | #define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 | 708 | #define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 |
| 709 | #define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 | 709 | #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 |
| 710 | #define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 | 710 | #define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 |
| 711 | #define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 | 711 | #define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 |
| 712 | #define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 | 712 | #define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 |
| 713 | #define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 | 713 | #define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 |
| 714 | #define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 | 714 | #define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 |
| 715 | #define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 | 715 | #define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 |
| 716 | #define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 | 716 | #define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 |
| 717 | #define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 | 717 | #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 |
| 718 | #define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 | 718 | #define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 |
| 719 | #define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 | 719 | #define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 |
| 720 | #define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 | 720 | #define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 |
| 721 | #define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 | 721 | #define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 |
| 722 | #define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 | 722 | #define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 |
| 723 | #define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 | 723 | #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 |
| 724 | #define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 | 724 | #define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 |
| 725 | #define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 | 725 | #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 |
| 726 | #define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 | 726 | #define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 |
| 727 | #define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 | 727 | #define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 |
| 728 | #define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 | 728 | #define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 |
| 729 | #define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 | 729 | #define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 |
| 730 | #define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 | 730 | #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 |
| 731 | #define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 | 731 | #define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 |
| 732 | #define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 | 732 | #define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 |
| 733 | #define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 | 733 | #define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 |
| 734 | #define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 | 734 | #define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 |
| 735 | #define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 | 735 | #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 |
| 736 | #define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 | 736 | #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 |
| 737 | #define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 | 737 | #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 |
| 738 | #define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 | 738 | #define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 |
| 739 | #define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 | 739 | #define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 |
| 740 | #define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 | 740 | #define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 |
| 741 | #define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 | 741 | #define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 |
| 742 | #define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 | 742 | #define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 |
| 743 | #define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 | 743 | #define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 |
| 744 | #define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 | 744 | #define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 |
| 745 | #define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 | 745 | #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 |
| 746 | #define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 | 746 | #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 |
| 747 | #define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 | 747 | #define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 |
| 748 | #define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 | 748 | #define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 |
| 749 | #define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 | 749 | #define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 |
| 750 | #define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 | 750 | #define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 |
| 751 | #define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 | 751 | #define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 |
| 752 | #define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 | 752 | #define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 |
| 753 | #define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 | 753 | #define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 |
| 754 | #define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 | 754 | #define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 |
| 755 | #define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 | 755 | #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 |
| 756 | #define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 | 756 | #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 |
| 757 | #define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 | 757 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 |
| 758 | #define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 | 758 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 |
| 759 | #define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 | 759 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 |
| 760 | #define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 | 760 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 |
| 761 | #define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 | 761 | #define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 |
| 762 | #define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 | 762 | #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 |
| 763 | #define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 | 763 | #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 |
| 764 | #define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 | 764 | #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 |
| 765 | #define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 | 765 | #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 |
| 766 | #define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 | 766 | #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 |
| 767 | #define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 | 767 | #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 |
| 768 | #define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 | 768 | #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 |
| 769 | #define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 | 769 | #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 |
| 770 | #define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 | 770 | #define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 |
| 771 | #define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 | 771 | #define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 |
| 772 | #define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 | 772 | #define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 |
| 773 | #define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 | 773 | #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 |
| 774 | #define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 | 774 | #define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 |
| 775 | #define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 | 775 | #define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 |
| 776 | #define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 | 776 | #define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 |
| 777 | #define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 | 777 | #define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 |
| 778 | #define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 | 778 | #define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 |
| 779 | #define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 | 779 | #define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 |
| 780 | #define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 | 780 | #define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 |
| 781 | #define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 | 781 | #define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 |
| 782 | #define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 | 782 | #define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 |
| 783 | #define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 | 783 | #define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 |
| 784 | #define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 | 784 | #define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 |
| 785 | #define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 | 785 | #define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 |
| 786 | #define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 | 786 | #define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 |
| 787 | #define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 | 787 | #define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 |
| 788 | #define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 | 788 | #define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 |
| 789 | #define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 | 789 | #define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 |
| 790 | #define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 | 790 | #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 |
| 791 | #define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 | 791 | #define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 |
| 792 | #define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 | 792 | #define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 |
| 793 | #define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 | 793 | #define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 |
| 794 | #define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 | 794 | #define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 |
| 795 | #define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 | 795 | #define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 |
| 796 | #define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 | 796 | #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 |
| 797 | #define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 | 797 | #define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 |
| 798 | #define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 | 798 | #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 |
| 799 | #define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 | 799 | #define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 |
| 800 | #define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 | 800 | #define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 |
| 801 | #define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 | 801 | #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 |
| 802 | #define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 | 802 | #define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 |
| 803 | #define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 | 803 | #define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 |
| 804 | #define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 | 804 | #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 |
| 805 | #define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 | 805 | #define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 |
| 806 | #define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 | 806 | #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 |
| 807 | #define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 | 807 | #define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 |
| 808 | #define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 | 808 | #define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 |
| 809 | #define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 | 809 | #define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 |
| 810 | #define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 | 810 | #define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 |
| 811 | #define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 | 811 | #define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 |
| 812 | #define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 | 812 | #define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 |
| 813 | #define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 | 813 | #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 |
| 814 | #define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 | 814 | #define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 |
| 815 | #define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 | 815 | #define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 |
| 816 | #define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 | 816 | #define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 |
| 817 | #define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 | 817 | #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 |
| 818 | #define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 | 818 | #define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 |
| 819 | #define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 | 819 | #define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 |
| 820 | #define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 | 820 | #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 |
| 821 | #define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 | 821 | #define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 |
| 822 | #define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 | 822 | #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 |
| 823 | #define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 | 823 | #define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 |
| 824 | #define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 | 824 | #define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 |
| 825 | #define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 | 825 | #define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 |
| 826 | #define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 | 826 | #define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 |
| 827 | #define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 | 827 | #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 |
| 828 | #define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 | 828 | #define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 |
| 829 | #define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 | 829 | #define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 |
| 830 | #define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 | 830 | #define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 |
| 831 | #define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 | 831 | #define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 |
| 832 | #define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 | 832 | #define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 |
| 833 | #define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 | 833 | #define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 |
| 834 | #define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 | 834 | #define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 |
| 835 | #define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 | 835 | #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 |
| 836 | #define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 | 836 | #define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 |
| 837 | #define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 | 837 | #define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 |
| 838 | #define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 | 838 | #define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 |
| 839 | #define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 | 839 | #define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 |
| 840 | #define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 | 840 | #define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 |
| 841 | #define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 | 841 | #define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 |
| 842 | #define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 | 842 | #define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 |
| 843 | #define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 | 843 | #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 |
| 844 | #define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 | 844 | #define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 |
| 845 | #define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 | 845 | #define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 |
| 846 | #define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 | 846 | #define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 |
| 847 | #define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 | 847 | #define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 |
| 848 | #define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 | 848 | #define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 |
| 849 | #define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 | 849 | #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 |
| 850 | #define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 | 850 | #define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 |
| 851 | #define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 | 851 | #define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 |
| 852 | #define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 | 852 | #define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 |
| 853 | #define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 | 853 | #define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 |
| 854 | #define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 | 854 | #define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 |
| 855 | #define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 | 855 | #define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 |
| 856 | #define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 | 856 | #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 |
| 857 | #define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 | 857 | #define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 |
| 858 | #define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 | 858 | #define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 |
| 859 | #define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 | 859 | #define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 |
| 860 | #define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 | 860 | #define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 |
| 861 | #define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 | 861 | #define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 |
| 862 | #define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 | 862 | #define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 |
| 863 | #define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 | 863 | #define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 |
| 864 | #define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 | 864 | #define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 |
| 865 | #define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 | 865 | #define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 |
| 866 | #define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 | 866 | #define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 |
| 867 | #define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 | 867 | #define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 |
| 868 | #define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 | 868 | #define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 |
| 869 | #define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 | 869 | #define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 |
| 870 | #define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 | 870 | #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 |
| 871 | #define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 | 871 | #define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 |
| 872 | #define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 | 872 | #define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 |
| 873 | #define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 | 873 | #define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 |
| 874 | #define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 | 874 | #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 |
| 875 | #define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 | 875 | #define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 |
| 876 | #define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 | 876 | #define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 |
| 877 | #define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 | 877 | #define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 |
| 878 | #define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 | 878 | #define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 |
| 879 | #define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 | 879 | #define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 |
| 880 | #define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 | 880 | #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 |
| 881 | #define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 | 881 | #define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 |
| 882 | #define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 | 882 | #define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 |
| 883 | #define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 | 883 | #define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 |
| 884 | #define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 | 884 | #define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 |
| 885 | #define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 | 885 | #define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 |
| 886 | #define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 | 886 | #define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 |
| 887 | #define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 | 887 | #define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 |
| 888 | #define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 | 888 | #define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 |
| 889 | #define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 | 889 | #define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 |
| 890 | #define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 | 890 | #define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 |
| 891 | #define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 | 891 | #define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 |
| 892 | #define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 | 892 | #define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 |
| 893 | #define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 | 893 | #define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 |
| 894 | #define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 | 894 | #define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 |
| 895 | #define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 | 895 | #define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 |
| 896 | #define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 | 896 | #define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 |
| 897 | #define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 | 897 | #define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 |
| 898 | #define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 | 898 | #define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 |
| 899 | #define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 | 899 | #define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 |
| 900 | #define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 | 900 | #define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 |
| 901 | #define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 | 901 | #define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 |
| 902 | #define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 | 902 | #define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 |
| 903 | #define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 | 903 | #define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 |
| 904 | #define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 | 904 | #define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 |
| 905 | #define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 | 905 | #define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 |
| 906 | #define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 | 906 | #define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 |
| 907 | #define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 | 907 | #define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 |
| 908 | #define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 | 908 | #define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 |
| 909 | #define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 | 909 | #define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 |
| 910 | #define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 | 910 | #define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 |
| 911 | #define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 | 911 | #define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 |
| 912 | #define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 | 912 | #define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 |
| 913 | #define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 | 913 | #define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 |
| 914 | #define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 | 914 | #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 |
| 915 | #define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 | 915 | #define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 |
| 916 | #define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 | 916 | #define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 |
| 917 | #define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 | 917 | #define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 |
| 918 | #define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 | 918 | #define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 |
| 919 | #define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 | 919 | #define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 |
| 920 | #define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 | 920 | #define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 |
| 921 | #define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 | 921 | #define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 |
| 922 | #define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 | 922 | #define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 |
| 923 | #define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 | 923 | #define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 |
| 924 | #define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 | 924 | #define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 |
| 925 | #define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 | 925 | #define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 |
| 926 | #define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 | 926 | #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 |
| 927 | #define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 | 927 | #define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 |
| 928 | #define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 | 928 | #define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 |
| 929 | #define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 | 929 | #define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 |
| 930 | #define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 | 930 | #define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 |
| 931 | #define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 | 931 | #define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 |
| 932 | #define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 | 932 | #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 |
| 933 | #define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 | 933 | #define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 |
| 934 | #define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 | 934 | #define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 |
| 935 | #define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 | 935 | #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 |
| 936 | #define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 | 936 | #define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 |
| 937 | #define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 | 937 | #define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 |
| 938 | #define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 | 938 | #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 |
| 939 | #define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 | 939 | #define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 |
| 940 | #define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 | 940 | #define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 |
| 941 | #define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 | 941 | #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 |
| 942 | #define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 | 942 | #define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 |
| 943 | #define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 | 943 | #define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 |
| 944 | #define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 | 944 | #define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 |
| 945 | #define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 | 945 | #define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 |
| 946 | #define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 | 946 | #define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 |
| 947 | #define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 | 947 | #define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 |
| 948 | #define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 | 948 | #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 |
| 949 | #define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 | 949 | #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 |
| 950 | #define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 | 950 | #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 |
| 951 | #define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 | 951 | #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 |
| 952 | #define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 | 952 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 |
| 953 | #define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 | 953 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 |
| 954 | #define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 | 954 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 |
| 955 | #define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 | 955 | #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 |
| 956 | #define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 | 956 | #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 |
| 957 | #define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 | 957 | #define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 |
| 958 | #define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 | 958 | #define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 |
| 959 | #define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 | 959 | #define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 |
| 960 | #define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 | 960 | #define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 |
| 961 | #define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 | 961 | #define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 |
| 962 | #define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 | 962 | #define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 |
| 963 | #define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 | 963 | #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 |
| 964 | #define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 | 964 | #define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 |
| 965 | #define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 | 965 | #define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 |
| 966 | #define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 | 966 | #define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 |
| 967 | #define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 | 967 | #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 |
| 968 | #define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 | 968 | #define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 |
| 969 | #define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 | 969 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 |
| 970 | #define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 | 970 | #define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 |
| 971 | #define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 | 971 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 |
| 972 | #define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 | 972 | #define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 |
| 973 | #define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 | 973 | #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 |
| 974 | #define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 | 974 | #define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 |
| 975 | #define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 | 975 | #define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 |
| 976 | #define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 | 976 | #define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 |
| 977 | #define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 | 977 | #define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 |
| 978 | #define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 | 978 | #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 |
| 979 | #define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 | 979 | #define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 |
| 980 | #define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 | 980 | #define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 |
| 981 | #define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 | 981 | #define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 |
| 982 | #define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 | 982 | #define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 |
| 983 | #define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 | 983 | #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 |
| 984 | #define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 | 984 | #define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 |
| 985 | #define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 | 985 | #define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 |
| 986 | #define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 | 986 | #define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 |
| 987 | #define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 | 987 | #define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 |
| 988 | #define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 | 988 | #define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 |
| 989 | #define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 | 989 | #define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 |
| 990 | #define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 | 990 | #define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 |
| 991 | #define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 | 991 | #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 |
| 992 | #define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 | 992 | #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 |
| 993 | #define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 | 993 | #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 |
| 994 | #define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 | 994 | #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 |
| 995 | #define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 | 995 | #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 |
| 996 | #define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 | 996 | #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 |
| 997 | #define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 | 997 | #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 |
| 998 | #define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 | 998 | #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 |
| 999 | #define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 | 999 | #define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 |
| 1000 | #define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 | 1000 | #define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 |
| 1001 | #define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 | 1001 | #define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 |
| 1002 | #define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 | 1002 | #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 |
| 1003 | #define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 | 1003 | #define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 |
| 1004 | #define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 | 1004 | #define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 |
| 1005 | #define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 | 1005 | #define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 |
| 1006 | #define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 | 1006 | #define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 |
| 1007 | #define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 | 1007 | #define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 |
| 1008 | #define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 | 1008 | #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 |
| 1009 | #define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 | 1009 | #define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 |
| 1010 | #define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 | 1010 | #define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 |
| 1011 | #define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 | 1011 | #define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 |
| 1012 | #define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 | 1012 | #define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 |
| 1013 | #define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 | 1013 | #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 |
| 1014 | #define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 | 1014 | #define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 |
| 1015 | #define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 | 1015 | #define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 |
| 1016 | #define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 | 1016 | #define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 |
| 1017 | #define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 | 1017 | #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 |
| 1018 | #define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 | 1018 | #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 |
| 1019 | #define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 | 1019 | #define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 |
| 1020 | #define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 | 1020 | #define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 |
| 1021 | #define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 | 1021 | #define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 |
| 1022 | #define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 | 1022 | #define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 |
| 1023 | #define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 | 1023 | #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 |
| 1024 | #define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 | 1024 | #define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 |
| 1025 | #define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 | 1025 | #define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 |
| 1026 | #define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 | 1026 | #define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 |
| 1027 | #define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 | 1027 | #define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 |
| 1028 | #define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 | 1028 | #define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 |
| 1029 | #define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 | 1029 | #define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 |
| 1030 | #define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 | 1030 | #define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 |
| 1031 | #define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 | 1031 | #define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 |
| 1032 | #define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 | 1032 | #define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 |
| 1033 | #define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 | 1033 | #define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 |
| 1034 | #define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 | 1034 | #define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 |
| 1035 | #define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 | 1035 | #define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 |
| 1036 | #define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 | 1036 | #define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 |
| 1037 | #define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 | 1037 | #define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 |
| 1038 | #define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 | 1038 | #define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 |
| 1039 | #define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 | 1039 | #define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 |
| 1040 | #define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 | 1040 | #define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 |
| 1041 | #define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 | 1041 | #define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 |
| 1042 | #define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 | 1042 | #define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 |
| 1043 | #define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 | 1043 | #define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 |
| 1044 | #define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 | 1044 | #define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 |
| 1045 | #define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 | 1045 | #define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 |
| 1046 | #define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 | 1046 | #define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 |
| 1047 | #define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 | 1047 | #define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 |
| 1048 | #define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 | 1048 | #define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 |
| 1049 | #define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 | 1049 | #define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 |
| 1050 | #define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 | 1050 | #define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 |
| 1051 | #define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 | 1051 | #define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 |
| 1052 | #define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 | 1052 | #define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 |
| 1053 | #define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 | 1053 | #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 |
| 1054 | #define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 | 1054 | #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 |
| 1055 | #define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 | 1055 | #define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 |
| 1056 | #define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 | 1056 | #define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 |
| 1057 | #define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 | 1057 | #define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 |
| 1058 | #define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 | 1058 | #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 |
| 1059 | #define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 | 1059 | #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 |
| 1060 | #define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 | 1060 | #define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 |
| 1061 | #define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 | 1061 | #define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 |
| 1062 | #define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 | 1062 | #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 |
| 1063 | #define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 | 1063 | #define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 |
| 1064 | #define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 | 1064 | #define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 |
| 1065 | #define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 | 1065 | #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 |
| 1066 | #define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 | 1066 | #define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 |
| 1067 | #define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 | 1067 | #define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 |
| 1068 | #define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 | 1068 | #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 |
| 1069 | #define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 | 1069 | #define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 |
| 1070 | #define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 | 1070 | #define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 |
| 1071 | #define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 | 1071 | #define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 |
| 1072 | #define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 | 1072 | #define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 |
| 1073 | #define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 | 1073 | #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 |
| 1074 | #define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 | 1074 | #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 |
| 1075 | #define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 | 1075 | #define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 |
| 1076 | #define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 | 1076 | #define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 |
| 1077 | #define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 | 1077 | #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 |
| 1078 | #define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 | 1078 | #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 |
| 1079 | #define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 | 1079 | #define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 |
| 1080 | #define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 | 1080 | #define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 |
| 1081 | #define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 | 1081 | #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 |
| 1082 | #define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 | 1082 | #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 |
| 1083 | #define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 | 1083 | #define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 |
| 1084 | #define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 | ||
| 1085 | #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 | ||
| 1086 | #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 | ||
| 1087 | #define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 | ||
| 1084 | 1088 | ||
| 1085 | #endif /* __DTS_IMX6DL_PINFUNC_H */ | 1089 | #endif /* __DTS_IMX6DL_PINFUNC_H */ |
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 95da71185a4a..a6ce7b487ad7 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts | |||
| @@ -15,25 +15,3 @@ | |||
| 15 | model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; | 15 | model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; |
| 16 | compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; | 16 | compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; |
| 17 | }; | 17 | }; |
| 18 | |||
| 19 | &iomuxc { | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | pinctrl-0 = <&pinctrl_hog>; | ||
| 22 | |||
| 23 | hog { | ||
| 24 | pinctrl_hog: hoggrp { | ||
| 25 | fsl,pins = < | ||
| 26 | MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 | ||
| 27 | MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 | ||
| 28 | >; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | ecspi1 { | ||
| 33 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | ||
| 34 | fsl,pins = < | ||
| 35 | MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 36 | >; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 8989df2b89e5..1e45f2f9d0b6 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts | |||
| @@ -15,22 +15,3 @@ | |||
| 15 | model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; | 15 | model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; |
| 16 | compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; | 16 | compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; |
| 17 | }; | 17 | }; |
| 18 | |||
| 19 | &iomuxc { | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | pinctrl-0 = <&pinctrl_hog>; | ||
| 22 | |||
| 23 | hog { | ||
| 24 | pinctrl_hog: hoggrp { | ||
| 25 | fsl,pins = < | ||
| 26 | MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 27 | MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 28 | MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 | ||
| 29 | MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | ||
| 30 | MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | ||
| 31 | MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | ||
| 32 | MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 33 | >; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts index bfc59c3566a4..e672891c1626 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard.dts | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | #include "imx6dl.dtsi" | 12 | #include "imx6dl.dtsi" |
| 13 | #include "imx6qdl-wandboard.dtsi" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | model = "Wandboard i.MX6 Dual Lite Board"; | 16 | model = "Wandboard i.MX6 Dual Lite Board"; |
| @@ -19,26 +20,3 @@ | |||
| 19 | reg = <0x10000000 0x40000000>; | 20 | reg = <0x10000000 0x40000000>; |
| 20 | }; | 21 | }; |
| 21 | }; | 22 | }; |
| 22 | |||
| 23 | &fec { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 26 | phy-mode = "rgmii"; | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &uart1 { | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | &usbh1 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | &usdhc3 { | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 2b3ecd679350..9e8ae118fdd4 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -8,8 +8,8 @@ | |||
| 8 | * | 8 | * |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include "imx6qdl.dtsi" | ||
| 12 | #include "imx6dl-pinfunc.h" | 11 | #include "imx6dl-pinfunc.h" |
| 12 | #include "imx6qdl.dtsi" | ||
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | cpus { | 15 | cpus { |
| @@ -32,238 +32,15 @@ | |||
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | soc { | 34 | soc { |
| 35 | ocram: sram@00900000 { | ||
| 36 | compatible = "mmio-sram"; | ||
| 37 | reg = <0x00900000 0x20000>; | ||
| 38 | clocks = <&clks 142>; | ||
| 39 | }; | ||
| 40 | |||
| 35 | aips1: aips-bus@02000000 { | 41 | aips1: aips-bus@02000000 { |
| 36 | iomuxc: iomuxc@020e0000 { | 42 | iomuxc: iomuxc@020e0000 { |
| 37 | compatible = "fsl,imx6dl-iomuxc"; | 43 | compatible = "fsl,imx6dl-iomuxc"; |
| 38 | reg = <0x020e0000 0x4000>; | ||
| 39 | |||
| 40 | audmux { | ||
| 41 | pinctrl_audmux_2: audmux-2 { | ||
| 42 | fsl,pins = < | ||
| 43 | MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 44 | MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 45 | MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 46 | MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 47 | >; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ecspi1 { | ||
| 52 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 53 | fsl,pins = < | ||
| 54 | MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 55 | MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 56 | MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | enet { | ||
| 62 | pinctrl_enet_1: enetgrp-1 { | ||
| 63 | fsl,pins = < | ||
| 64 | MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 65 | MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 66 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 67 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 68 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 69 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 70 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 71 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 72 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 73 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 74 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 75 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 76 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 77 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 78 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 79 | MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 80 | >; | ||
| 81 | }; | ||
| 82 | |||
| 83 | pinctrl_enet_2: enetgrp-2 { | ||
| 84 | fsl,pins = < | ||
| 85 | MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 86 | MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 87 | MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 88 | MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 89 | MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 90 | MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 91 | MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 92 | MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 93 | MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 94 | MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 95 | MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 96 | MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 97 | MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 98 | MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 99 | MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 100 | >; | ||
| 101 | }; | ||
| 102 | }; | ||
| 103 | |||
| 104 | gpmi-nand { | ||
| 105 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 106 | fsl,pins = < | ||
| 107 | MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 108 | MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 109 | MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 110 | MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 111 | MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 112 | MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 113 | MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 114 | MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 115 | MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 116 | MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 117 | MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 118 | MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 119 | MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 120 | MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 121 | MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 122 | MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 123 | MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | i2c1 { | ||
| 129 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 130 | fsl,pins = < | ||
| 131 | MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 132 | MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 137 | uart1 { | ||
| 138 | pinctrl_uart1_1: uart1grp-1 { | ||
| 139 | fsl,pins = < | ||
| 140 | MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 141 | MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | |||
| 146 | uart4 { | ||
| 147 | pinctrl_uart4_1: uart4grp-1 { | ||
| 148 | fsl,pins = < | ||
| 149 | MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 150 | MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 151 | >; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 155 | usbotg { | ||
| 156 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 157 | fsl,pins = < | ||
| 158 | MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 159 | >; | ||
| 160 | }; | ||
| 161 | }; | ||
| 162 | |||
| 163 | usdhc2 { | ||
| 164 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 165 | fsl,pins = < | ||
| 166 | MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 167 | MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 168 | MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 169 | MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 170 | MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 171 | MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 172 | MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 173 | MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 174 | MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 175 | MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 176 | >; | ||
| 177 | }; | ||
| 178 | }; | ||
| 179 | |||
| 180 | usdhc3 { | ||
| 181 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 182 | fsl,pins = < | ||
| 183 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 184 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 185 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 186 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 187 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 188 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 189 | MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 190 | MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 191 | MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 192 | MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 193 | >; | ||
| 194 | }; | ||
| 195 | |||
| 196 | pinctrl_usdhc3_2: usdhc3grp_2 { | ||
| 197 | fsl,pins = < | ||
| 198 | MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 199 | MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 200 | MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 201 | MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 202 | MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 203 | MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 204 | >; | ||
| 205 | }; | ||
| 206 | }; | ||
| 207 | |||
| 208 | weim { | ||
| 209 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 210 | fsl,pins = < | ||
| 211 | MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 216 | fsl,pins = < | ||
| 217 | MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 218 | MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 219 | MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 220 | /* data */ | ||
| 221 | MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 222 | MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 223 | MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 224 | MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 225 | MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 226 | MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 227 | MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 228 | MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 229 | MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 230 | MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 231 | MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 232 | MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 233 | MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 234 | MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 235 | MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 236 | MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 237 | /* address */ | ||
| 238 | MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 239 | MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 240 | MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 241 | MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 242 | MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 243 | MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 244 | MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 245 | MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 246 | MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 247 | MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 248 | MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 249 | MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 250 | MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 251 | MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 252 | MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 253 | MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 254 | MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 255 | MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 256 | MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 257 | MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 258 | MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 259 | MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 260 | MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 261 | MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | }; | ||
| 266 | |||
| 267 | }; | 44 | }; |
| 268 | 45 | ||
| 269 | pxp: pxp@020f0000 { | 46 | pxp: pxp@020f0000 { |
| @@ -294,3 +71,20 @@ | |||
| 294 | }; | 71 | }; |
| 295 | }; | 72 | }; |
| 296 | }; | 73 | }; |
| 74 | |||
| 75 | &ldb { | ||
| 76 | clocks = <&clks 33>, <&clks 34>, | ||
| 77 | <&clks 39>, <&clks 40>, | ||
| 78 | <&clks 135>, <&clks 136>; | ||
| 79 | clock-names = "di0_pll", "di1_pll", | ||
| 80 | "di0_sel", "di1_sel", | ||
| 81 | "di0", "di1"; | ||
| 82 | |||
| 83 | lvds-channel@0 { | ||
| 84 | crtcs = <&ipu1 0>, <&ipu1 1>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | lvds-channel@1 { | ||
| 88 | crtcs = <&ipu1 0>, <&ipu1 1>; | ||
| 89 | }; | ||
| 90 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 4e54fde591bd..edf1bd967164 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
| @@ -57,7 +57,7 @@ | |||
| 57 | hog { | 57 | hog { |
| 58 | pinctrl_hog: hoggrp { | 58 | pinctrl_hog: hoggrp { |
| 59 | fsl,pins = < | 59 | fsl,pins = < |
| 60 | MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 | 60 | MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 |
| 61 | >; | 61 | >; |
| 62 | }; | 62 | }; |
| 63 | }; | 63 | }; |
| @@ -65,8 +65,8 @@ | |||
| 65 | arm2 { | 65 | arm2 { |
| 66 | pinctrl_usdhc3_arm2: usdhc3grp-arm2 { | 66 | pinctrl_usdhc3_arm2: usdhc3grp-arm2 { |
| 67 | fsl,pins = < | 67 | fsl,pins = < |
| 68 | MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 | 68 | MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 |
| 69 | MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 | 69 | MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 |
| 70 | >; | 70 | >; |
| 71 | }; | 71 | }; |
| 72 | }; | 72 | }; |
| @@ -97,6 +97,14 @@ | |||
| 97 | status = "okay"; | 97 | status = "okay"; |
| 98 | }; | 98 | }; |
| 99 | 99 | ||
| 100 | &uart2 { | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | pinctrl-0 = <&pinctrl_uart2_2>; | ||
| 103 | fsl,dte-mode; | ||
| 104 | fsl,uart-has-rtscts; | ||
| 105 | status = "okay"; | ||
| 106 | }; | ||
| 107 | |||
| 100 | &uart4 { | 108 | &uart4 { |
| 101 | pinctrl-names = "default"; | 109 | pinctrl-names = "default"; |
| 102 | pinctrl-0 = <&pinctrl_uart4_1>; | 110 | pinctrl-0 = <&pinctrl_uart4_1>; |
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index f5e1981025ed..1a3b50d4d8fa 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | |||
| @@ -20,6 +20,110 @@ | |||
| 20 | }; | 20 | }; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | &ecspi3 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&pinctrl_ecspi3_1>; | ||
| 26 | status = "okay"; | ||
| 27 | fsl,spi-num-chipselects = <1>; | ||
| 28 | cs-gpios = <&gpio4 24 0>; | ||
| 29 | |||
| 30 | flash@0 { | ||
| 31 | compatible = "m25p80"; | ||
| 32 | spi-max-frequency = <20000000>; | ||
| 33 | reg = <0>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | &i2c1 { | ||
| 38 | pinctrl-names = "default"; | ||
| 39 | pinctrl-0 = <&pinctrl_i2c1_1>; | ||
| 40 | status = "okay"; | ||
| 41 | |||
| 42 | eeprom@50 { | ||
| 43 | compatible = "atmel,24c32"; | ||
| 44 | reg = <0x50>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | pmic@58 { | ||
| 48 | compatible = "dialog,da9063"; | ||
| 49 | reg = <0x58>; | ||
| 50 | interrupt-parent = <&gpio4>; | ||
| 51 | interrupts = <17 0x8>; /* active-low GPIO4_17 */ | ||
| 52 | |||
| 53 | regulators { | ||
| 54 | vddcore_reg: bcore1 { | ||
| 55 | regulator-min-microvolt = <730000>; | ||
| 56 | regulator-max-microvolt = <1380000>; | ||
| 57 | regulator-always-on; | ||
| 58 | }; | ||
| 59 | |||
| 60 | vddsoc_reg: bcore2 { | ||
| 61 | regulator-min-microvolt = <730000>; | ||
| 62 | regulator-max-microvolt = <1380000>; | ||
| 63 | regulator-always-on; | ||
| 64 | }; | ||
| 65 | |||
| 66 | vdd_ddr3_reg: bpro { | ||
| 67 | regulator-min-microvolt = <1500000>; | ||
| 68 | regulator-max-microvolt = <1500000>; | ||
| 69 | regulator-always-on; | ||
| 70 | }; | ||
| 71 | |||
| 72 | vdd_3v3_reg: bperi { | ||
| 73 | regulator-min-microvolt = <3300000>; | ||
| 74 | regulator-max-microvolt = <3300000>; | ||
| 75 | regulator-always-on; | ||
| 76 | }; | ||
| 77 | |||
| 78 | vdd_buckmem_reg: bmem { | ||
| 79 | regulator-min-microvolt = <3300000>; | ||
| 80 | regulator-max-microvolt = <3300000>; | ||
| 81 | regulator-always-on; | ||
| 82 | }; | ||
| 83 | |||
| 84 | vdd_eth_reg: bio { | ||
| 85 | regulator-min-microvolt = <1200000>; | ||
| 86 | regulator-max-microvolt = <1200000>; | ||
| 87 | regulator-always-on; | ||
| 88 | }; | ||
| 89 | |||
| 90 | vdd_eth_io_reg: ldo4 { | ||
| 91 | regulator-min-microvolt = <2500000>; | ||
| 92 | regulator-max-microvolt = <2500000>; | ||
| 93 | regulator-always-on; | ||
| 94 | }; | ||
| 95 | |||
| 96 | vdd_mx6_snvs_reg: ldo5 { | ||
| 97 | regulator-min-microvolt = <3000000>; | ||
| 98 | regulator-max-microvolt = <3000000>; | ||
| 99 | regulator-always-on; | ||
| 100 | }; | ||
| 101 | |||
| 102 | vdd_3v3_pmic_io_reg: ldo6 { | ||
| 103 | regulator-min-microvolt = <3300000>; | ||
| 104 | regulator-max-microvolt = <3300000>; | ||
| 105 | regulator-always-on; | ||
| 106 | }; | ||
| 107 | |||
| 108 | vdd_sd0_reg: ldo9 { | ||
| 109 | regulator-min-microvolt = <3300000>; | ||
| 110 | regulator-max-microvolt = <3300000>; | ||
| 111 | }; | ||
| 112 | |||
| 113 | vdd_sd1_reg: ldo10 { | ||
| 114 | regulator-min-microvolt = <3300000>; | ||
| 115 | regulator-max-microvolt = <3300000>; | ||
| 116 | }; | ||
| 117 | |||
| 118 | vdd_mx6_high_reg: ldo11 { | ||
| 119 | regulator-min-microvolt = <3000000>; | ||
| 120 | regulator-max-microvolt = <3000000>; | ||
| 121 | regulator-always-on; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | |||
| 23 | &iomuxc { | 127 | &iomuxc { |
| 24 | pinctrl-names = "default"; | 128 | pinctrl-names = "default"; |
| 25 | pinctrl-0 = <&pinctrl_hog>; | 129 | pinctrl-0 = <&pinctrl_hog>; |
| @@ -27,7 +131,9 @@ | |||
| 27 | hog { | 131 | hog { |
| 28 | pinctrl_hog: hoggrp { | 132 | pinctrl_hog: hoggrp { |
| 29 | fsl,pins = < | 133 | fsl,pins = < |
| 30 | MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 | 134 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| 135 | MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ | ||
| 136 | MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ | ||
| 31 | >; | 137 | >; |
| 32 | }; | 138 | }; |
| 33 | }; | 139 | }; |
| @@ -35,8 +141,8 @@ | |||
| 35 | pfla02 { | 141 | pfla02 { |
| 36 | pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { | 142 | pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { |
| 37 | fsl,pins = < | 143 | fsl,pins = < |
| 38 | MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | 144 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 |
| 39 | MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | 145 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 |
| 40 | >; | 146 | >; |
| 41 | }; | 147 | }; |
| 42 | }; | 148 | }; |
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index faea6e1ada00..c0e38a45e4bb 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h | |||
| @@ -14,1028 +14,1032 @@ | |||
| 14 | * The pin function ID is a tuple of | 14 | * The pin function ID is a tuple of |
| 15 | * <mux_reg conf_reg input_reg mux_mode input_val> | 15 | * <mux_reg conf_reg input_reg mux_mode input_val> |
| 16 | */ | 16 | */ |
| 17 | #define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 | 17 | #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 |
| 18 | #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 | 18 | #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 |
| 19 | #define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 | 19 | #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 |
| 20 | #define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 | 20 | #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 |
| 21 | #define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 | 21 | #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 |
| 22 | #define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 | 22 | #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 |
| 23 | #define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 | 23 | #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 |
| 24 | #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 | 24 | #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 |
| 25 | #define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 | 25 | #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 |
| 26 | #define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 | 26 | #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 |
| 27 | #define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 | 27 | #define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 |
| 28 | #define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 | 28 | #define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 |
| 29 | #define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 | 29 | #define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 |
| 30 | #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 | 30 | #define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 |
| 31 | #define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 | 31 | #define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 |
| 32 | #define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 | 32 | #define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 |
| 33 | #define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 | 33 | #define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 |
| 34 | #define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 | 34 | #define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 |
| 35 | #define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 | 35 | #define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 |
| 36 | #define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 | 36 | #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 |
| 37 | #define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 | 37 | #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 |
| 38 | #define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 | 38 | #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 |
| 39 | #define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 | 39 | #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 |
| 40 | #define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 | 40 | #define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 |
| 41 | #define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 | 41 | #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 |
| 42 | #define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 | 42 | #define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 |
| 43 | #define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 | 43 | #define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 |
| 44 | #define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 | 44 | #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 |
| 45 | #define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 | 45 | #define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 |
| 46 | #define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 | 46 | #define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 |
| 47 | #define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 | 47 | #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 |
| 48 | #define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 | 48 | #define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 |
| 49 | #define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 | 49 | #define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 |
| 50 | #define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 | 50 | #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 |
| 51 | #define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 | 51 | #define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 |
| 52 | #define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 | 52 | #define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 |
| 53 | #define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 | 53 | #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 |
| 54 | #define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 | 54 | #define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 |
| 55 | #define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 | 55 | #define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 |
| 56 | #define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 | 56 | #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 |
| 57 | #define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 | 57 | #define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 |
| 58 | #define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 | 58 | #define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 |
| 59 | #define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 | 59 | #define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 |
| 60 | #define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 | 60 | #define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 |
| 61 | #define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 | 61 | #define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 |
| 62 | #define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 | 62 | #define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 |
| 63 | #define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 | 63 | #define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 |
| 64 | #define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 | 64 | #define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 |
| 65 | #define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 | 65 | #define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 |
| 66 | #define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 | 66 | #define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 |
| 67 | #define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 | 67 | #define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 |
| 68 | #define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 | 68 | #define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 |
| 69 | #define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 | 69 | #define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 |
| 70 | #define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 | 70 | #define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 |
| 71 | #define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 | 71 | #define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 |
| 72 | #define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 | 72 | #define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 |
| 73 | #define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 | 73 | #define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 |
| 74 | #define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 | 74 | #define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 |
| 75 | #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 | 75 | #define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 |
| 76 | #define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 | 76 | #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 |
| 77 | #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 | 77 | #define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 |
| 78 | #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 | 78 | #define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 |
| 79 | #define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 | 79 | #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 |
| 80 | #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 | 80 | #define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 |
| 81 | #define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 | 81 | #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 |
| 82 | #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 | 82 | #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 |
| 83 | #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 | 83 | #define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 |
| 84 | #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 | 84 | #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 |
| 85 | #define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 | 85 | #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 |
| 86 | #define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 | 86 | #define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 |
| 87 | #define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 | 87 | #define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 |
| 88 | #define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 | 88 | #define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 |
| 89 | #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 | 89 | #define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 |
| 90 | #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 | 90 | #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 |
| 91 | #define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 | 91 | #define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 |
| 92 | #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 | 92 | #define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 |
| 93 | #define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 | 93 | #define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 |
| 94 | #define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 | 94 | #define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 |
| 95 | #define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 | 95 | #define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 |
| 96 | #define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 | 96 | #define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 |
| 97 | #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 | 97 | #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 |
| 98 | #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 | 98 | #define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 |
| 99 | #define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 | 99 | #define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 |
| 100 | #define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 | 100 | #define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 |
| 101 | #define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 | 101 | #define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 |
| 102 | #define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 | 102 | #define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 |
| 103 | #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 | 103 | #define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 |
| 104 | #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 | 104 | #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 |
| 105 | #define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 | 105 | #define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 |
| 106 | #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 | 106 | #define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 |
| 107 | #define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 | 107 | #define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 |
| 108 | #define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 | 108 | #define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 |
| 109 | #define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 | 109 | #define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 |
| 110 | #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 | 110 | #define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 |
| 111 | #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 | 111 | #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 |
| 112 | #define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 | 112 | #define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 |
| 113 | #define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 | 113 | #define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 |
| 114 | #define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 | 114 | #define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 |
| 115 | #define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 | 115 | #define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 |
| 116 | #define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 | 116 | #define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 |
| 117 | #define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 | 117 | #define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 |
| 118 | #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 | 118 | #define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 |
| 119 | #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 | 119 | #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 |
| 120 | #define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 | 120 | #define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 |
| 121 | #define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 | 121 | #define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 |
| 122 | #define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 | 122 | #define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 |
| 123 | #define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 | 123 | #define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 |
| 124 | #define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 | 124 | #define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 |
| 125 | #define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 | 125 | #define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 |
| 126 | #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 | 126 | #define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 |
| 127 | #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 | 127 | #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 |
| 128 | #define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 | 128 | #define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 |
| 129 | #define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 | 129 | #define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 |
| 130 | #define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 | 130 | #define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 |
| 131 | #define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 | 131 | #define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 |
| 132 | #define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 | 132 | #define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 |
| 133 | #define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 | 133 | #define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 |
| 134 | #define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 | 134 | #define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 |
| 135 | #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 | 135 | #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 |
| 136 | #define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 | 136 | #define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 |
| 137 | #define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 | 137 | #define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 |
| 138 | #define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 | 138 | #define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 |
| 139 | #define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 | 139 | #define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 |
| 140 | #define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 | 140 | #define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 |
| 141 | #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 | 141 | #define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 |
| 142 | #define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 | 142 | #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 |
| 143 | #define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 | 143 | #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 |
| 144 | #define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 | 144 | #define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 |
| 145 | #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 | 145 | #define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 |
| 146 | #define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 | 146 | #define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 |
| 147 | #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 | 147 | #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 |
| 148 | #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 | 148 | #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 |
| 149 | #define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 | 149 | #define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 |
| 150 | #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 | 150 | #define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 |
| 151 | #define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 | 151 | #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 |
| 152 | #define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 | 152 | #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 |
| 153 | #define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 | 153 | #define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 |
| 154 | #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 | 154 | #define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 |
| 155 | #define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 | 155 | #define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 |
| 156 | #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 | 156 | #define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 |
| 157 | #define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 | 157 | #define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 |
| 158 | #define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 | 158 | #define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 |
| 159 | #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 | 159 | #define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 |
| 160 | #define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 | 160 | #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 |
| 161 | #define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 | 161 | #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 |
| 162 | #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 | 162 | #define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 |
| 163 | #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 | 163 | #define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 |
| 164 | #define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 | 164 | #define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 |
| 165 | #define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 | 165 | #define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 |
| 166 | #define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 | 166 | #define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 |
| 167 | #define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 | 167 | #define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 |
| 168 | #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 | 168 | #define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 |
| 169 | #define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 | 169 | #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 |
| 170 | #define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 | 170 | #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 |
| 171 | #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 | 171 | #define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 |
| 172 | #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 | 172 | #define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 |
| 173 | #define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 | 173 | #define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 |
| 174 | #define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 | 174 | #define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 |
| 175 | #define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 | 175 | #define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 |
| 176 | #define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 | 176 | #define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 |
| 177 | #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 | 177 | #define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 |
| 178 | #define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 | 178 | #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 |
| 179 | #define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 | 179 | #define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 |
| 180 | #define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 | 180 | #define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 |
| 181 | #define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 | 181 | #define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 |
| 182 | #define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 | 182 | #define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 |
| 183 | #define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 | 183 | #define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 |
| 184 | #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 | 184 | #define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 |
| 185 | #define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 | 185 | #define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 |
| 186 | #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 | 186 | #define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 |
| 187 | #define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 | 187 | #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 |
| 188 | #define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 | 188 | #define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 |
| 189 | #define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 | 189 | #define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 |
| 190 | #define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 | 190 | #define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 |
| 191 | #define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 | 191 | #define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 |
| 192 | #define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 | 192 | #define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 |
| 193 | #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 | 193 | #define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 |
| 194 | #define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 | 194 | #define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 |
| 195 | #define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 | 195 | #define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 |
| 196 | #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 | 196 | #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 |
| 197 | #define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 | 197 | #define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 |
| 198 | #define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 | 198 | #define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 |
| 199 | #define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 | 199 | #define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 |
| 200 | #define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 | 200 | #define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 |
| 201 | #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 | 201 | #define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 |
| 202 | #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 | 202 | #define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 |
| 203 | #define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 | 203 | #define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 |
| 204 | #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 | 204 | #define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 |
| 205 | #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 | 205 | #define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 |
| 206 | #define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 | 206 | #define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 |
| 207 | #define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 | 207 | #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 |
| 208 | #define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 | 208 | #define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 |
| 209 | #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 | 209 | #define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 |
| 210 | #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 | 210 | #define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0 |
| 211 | #define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 | 211 | #define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1 |
| 212 | #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 | 212 | #define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 |
| 213 | #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 | 213 | #define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 |
| 214 | #define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 | 214 | #define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 |
| 215 | #define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 | 215 | #define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 |
| 216 | #define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 | 216 | #define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 |
| 217 | #define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 | 217 | #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 |
| 218 | #define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 | 218 | #define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 |
| 219 | #define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 | 219 | #define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 |
| 220 | #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 | 220 | #define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 |
| 221 | #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 | 221 | #define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 |
| 222 | #define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 | 222 | #define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 |
| 223 | #define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 | 223 | #define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 |
| 224 | #define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 | 224 | #define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 |
| 225 | #define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 | 225 | #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 |
| 226 | #define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 | 226 | #define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 |
| 227 | #define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 | 227 | #define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 |
| 228 | #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 | 228 | #define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 |
| 229 | #define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 | 229 | #define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 |
| 230 | #define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 | 230 | #define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 |
| 231 | #define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 | 231 | #define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 |
| 232 | #define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 | 232 | #define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 |
| 233 | #define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 | 233 | #define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 |
| 234 | #define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 | 234 | #define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 |
| 235 | #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 | 235 | #define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 |
| 236 | #define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 | 236 | #define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 |
| 237 | #define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 | 237 | #define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 |
| 238 | #define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 | 238 | #define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 |
| 239 | #define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 | 239 | #define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 |
| 240 | #define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 | 240 | #define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 |
| 241 | #define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 | 241 | #define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 |
| 242 | #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 | 242 | #define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 |
| 243 | #define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 | 243 | #define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 |
| 244 | #define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 | 244 | #define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 |
| 245 | #define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 | 245 | #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 |
| 246 | #define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 | 246 | #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 |
| 247 | #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 | 247 | #define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 |
| 248 | #define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 | 248 | #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 |
| 249 | #define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 | 249 | #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 |
| 250 | #define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 | 250 | #define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 |
| 251 | #define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 | 251 | #define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 |
| 252 | #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 | 252 | #define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 |
| 253 | #define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 | 253 | #define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 |
| 254 | #define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 | 254 | #define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 |
| 255 | #define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 | 255 | #define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 |
| 256 | #define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 | 256 | #define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 |
| 257 | #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 | 257 | #define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 |
| 258 | #define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 | 258 | #define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 |
| 259 | #define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 | 259 | #define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 |
| 260 | #define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 | 260 | #define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 |
| 261 | #define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 | 261 | #define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 |
| 262 | #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 | 262 | #define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 |
| 263 | #define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 | 263 | #define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 |
| 264 | #define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 | 264 | #define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 |
| 265 | #define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 | 265 | #define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 |
| 266 | #define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 | 266 | #define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 |
| 267 | #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 | 267 | #define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 |
| 268 | #define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 | 268 | #define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 |
| 269 | #define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 | 269 | #define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 |
| 270 | #define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 | 270 | #define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 |
| 271 | #define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 | 271 | #define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 |
| 272 | #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 | 272 | #define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 |
| 273 | #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 | 273 | #define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 |
| 274 | #define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 | 274 | #define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 |
| 275 | #define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 | 275 | #define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 |
| 276 | #define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 | 276 | #define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 |
| 277 | #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 | 277 | #define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 |
| 278 | #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 | 278 | #define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 |
| 279 | #define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 | 279 | #define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 |
| 280 | #define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 | 280 | #define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 |
| 281 | #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 | 281 | #define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 |
| 282 | #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 | 282 | #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 |
| 283 | #define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 | 283 | #define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 |
| 284 | #define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 | 284 | #define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 |
| 285 | #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 | 285 | #define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 |
| 286 | #define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 | 286 | #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 |
| 287 | #define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 | 287 | #define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 |
| 288 | #define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 | 288 | #define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 |
| 289 | #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 | 289 | #define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 |
| 290 | #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 | 290 | #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 |
| 291 | #define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 | 291 | #define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 |
| 292 | #define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 | 292 | #define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 |
| 293 | #define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 | 293 | #define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 |
| 294 | #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 | 294 | #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 |
| 295 | #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 | 295 | #define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 |
| 296 | #define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 | 296 | #define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 |
| 297 | #define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 | 297 | #define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 |
| 298 | #define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 | 298 | #define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 |
| 299 | #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 | 299 | #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 |
| 300 | #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 | 300 | #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 |
| 301 | #define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 | 301 | #define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 |
| 302 | #define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 | 302 | #define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 |
| 303 | #define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 | 303 | #define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 |
| 304 | #define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 | 304 | #define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 |
| 305 | #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 | 305 | #define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 |
| 306 | #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 | 306 | #define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 |
| 307 | #define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 | 307 | #define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 |
| 308 | #define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 | 308 | #define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 |
| 309 | #define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 | 309 | #define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 |
| 310 | #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 | 310 | #define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 |
| 311 | #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 | 311 | #define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 |
| 312 | #define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 | 312 | #define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 |
| 313 | #define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 | 313 | #define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 |
| 314 | #define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 | 314 | #define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 |
| 315 | #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 | 315 | #define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 |
| 316 | #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 | 316 | #define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 |
| 317 | #define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 | 317 | #define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 |
| 318 | #define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 | 318 | #define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 |
| 319 | #define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 | 319 | #define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 |
| 320 | #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 | 320 | #define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 |
| 321 | #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 | 321 | #define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 |
| 322 | #define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 | 322 | #define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 |
| 323 | #define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 | 323 | #define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 |
| 324 | #define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 | 324 | #define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 |
| 325 | #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 | 325 | #define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 |
| 326 | #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 | 326 | #define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 |
| 327 | #define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 | 327 | #define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 |
| 328 | #define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 | 328 | #define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 |
| 329 | #define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 | 329 | #define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 |
| 330 | #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 | 330 | #define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 |
| 331 | #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 | 331 | #define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 |
| 332 | #define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 | 332 | #define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 |
| 333 | #define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 | 333 | #define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 |
| 334 | #define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 | 334 | #define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 |
| 335 | #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 | 335 | #define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 |
| 336 | #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 | 336 | #define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 |
| 337 | #define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 | 337 | #define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 |
| 338 | #define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 | 338 | #define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 |
| 339 | #define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 | 339 | #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 |
| 340 | #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 | 340 | #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 |
| 341 | #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 | 341 | #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 |
| 342 | #define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 | 342 | #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 |
| 343 | #define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 | 343 | #define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 |
| 344 | #define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 | 344 | #define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 |
| 345 | #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 | 345 | #define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 |
| 346 | #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 | 346 | #define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 |
| 347 | #define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 | 347 | #define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 |
| 348 | #define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 | 348 | #define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 |
| 349 | #define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 | 349 | #define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 |
| 350 | #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 | 350 | #define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 |
| 351 | #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 | 351 | #define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 |
| 352 | #define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 | 352 | #define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 |
| 353 | #define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 | 353 | #define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 |
| 354 | #define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 | 354 | #define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 |
| 355 | #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 | 355 | #define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 |
| 356 | #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 | 356 | #define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 |
| 357 | #define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 | 357 | #define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 |
| 358 | #define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 | 358 | #define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 |
| 359 | #define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 | 359 | #define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 |
| 360 | #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 | 360 | #define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 |
| 361 | #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 | 361 | #define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 |
| 362 | #define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 | 362 | #define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 |
| 363 | #define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 | 363 | #define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 |
| 364 | #define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 | 364 | #define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 |
| 365 | #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 | 365 | #define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 |
| 366 | #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 | 366 | #define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 |
| 367 | #define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 | 367 | #define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 |
| 368 | #define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 | 368 | #define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 |
| 369 | #define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 | 369 | #define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 |
| 370 | #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 | 370 | #define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 |
| 371 | #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 | 371 | #define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 |
| 372 | #define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 | 372 | #define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 |
| 373 | #define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 | 373 | #define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 |
| 374 | #define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 | 374 | #define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 |
| 375 | #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 | 375 | #define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 |
| 376 | #define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 | 376 | #define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 |
| 377 | #define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 | 377 | #define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 |
| 378 | #define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 | 378 | #define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 |
| 379 | #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 | 379 | #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 |
| 380 | #define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 | 380 | #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 |
| 381 | #define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 | 381 | #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 |
| 382 | #define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 | 382 | #define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 |
| 383 | #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 | 383 | #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 |
| 384 | #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 | 384 | #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 |
| 385 | #define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 | 385 | #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 |
| 386 | #define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 | 386 | #define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 |
| 387 | #define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 | 387 | #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 |
| 388 | #define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 | 388 | #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 |
| 389 | #define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 | 389 | #define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 |
| 390 | #define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 | 390 | #define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 |
| 391 | #define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 | 391 | #define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 |
| 392 | #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 | 392 | #define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 |
| 393 | #define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 | 393 | #define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 |
| 394 | #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 | 394 | #define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 |
| 395 | #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 | 395 | #define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 |
| 396 | #define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 | 396 | #define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 |
| 397 | #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 | 397 | #define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 |
| 398 | #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 | 398 | #define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 |
| 399 | #define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 | 399 | #define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 |
| 400 | #define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 | 400 | #define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 |
| 401 | #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 | 401 | #define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 |
| 402 | #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 | 402 | #define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 |
| 403 | #define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 | 403 | #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 |
| 404 | #define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 | 404 | #define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 |
| 405 | #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 | 405 | #define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 |
| 406 | #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 | 406 | #define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 |
| 407 | #define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 | 407 | #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 |
| 408 | #define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 | 408 | #define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 |
| 409 | #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 | 409 | #define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 |
| 410 | #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 | 410 | #define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 |
| 411 | #define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 | 411 | #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 |
| 412 | #define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 | 412 | #define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 |
| 413 | #define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 | 413 | #define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 |
| 414 | #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 | 414 | #define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 |
| 415 | #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 | 415 | #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 |
| 416 | #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 | 416 | #define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 |
| 417 | #define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 | 417 | #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 |
| 418 | #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 | 418 | #define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 |
| 419 | #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 | 419 | #define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 |
| 420 | #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 | 420 | #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 |
| 421 | #define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 | 421 | #define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 |
| 422 | #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 | 422 | #define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 |
| 423 | #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 | 423 | #define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 |
| 424 | #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 | 424 | #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 |
| 425 | #define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 | 425 | #define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 |
| 426 | #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 | 426 | #define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 |
| 427 | #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 | 427 | #define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 |
| 428 | #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 | 428 | #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 |
| 429 | #define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 | 429 | #define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 |
| 430 | #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 | 430 | #define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 |
| 431 | #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 | 431 | #define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 |
| 432 | #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 | 432 | #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 |
| 433 | #define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 | 433 | #define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 |
| 434 | #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 | 434 | #define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 |
| 435 | #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 | 435 | #define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 |
| 436 | #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 | 436 | #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 |
| 437 | #define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 | 437 | #define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 |
| 438 | #define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 | 438 | #define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 |
| 439 | #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 | 439 | #define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 |
| 440 | #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 | 440 | #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 |
| 441 | #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 | 441 | #define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 |
| 442 | #define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 | 442 | #define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 |
| 443 | #define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 | 443 | #define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 |
| 444 | #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 | 444 | #define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 |
| 445 | #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 | 445 | #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 |
| 446 | #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 | 446 | #define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 |
| 447 | #define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 | 447 | #define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 |
| 448 | #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 | 448 | #define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 |
| 449 | #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 | 449 | #define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 |
| 450 | #define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 | 450 | #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 |
| 451 | #define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 | 451 | #define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 |
| 452 | #define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 | 452 | #define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 |
| 453 | #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 | 453 | #define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 |
| 454 | #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 | 454 | #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 |
| 455 | #define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 | 455 | #define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 |
| 456 | #define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 | 456 | #define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 |
| 457 | #define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 | 457 | #define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 |
| 458 | #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 | 458 | #define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 |
| 459 | #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 | 459 | #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 |
| 460 | #define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 | 460 | #define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 |
| 461 | #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 | 461 | #define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 |
| 462 | #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 | 462 | #define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 |
| 463 | #define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 | 463 | #define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 |
| 464 | #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 | 464 | #define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 |
| 465 | #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 | 465 | #define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 |
| 466 | #define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 | 466 | #define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 |
| 467 | #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 | 467 | #define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 |
| 468 | #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 | 468 | #define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 |
| 469 | #define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 | 469 | #define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 |
| 470 | #define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 | 470 | #define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 |
| 471 | #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 | 471 | #define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 |
| 472 | #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 | 472 | #define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 |
| 473 | #define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 | 473 | #define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 |
| 474 | #define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 | 474 | #define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 |
| 475 | #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 | 475 | #define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 |
| 476 | #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 | 476 | #define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 |
| 477 | #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 | 477 | #define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 |
| 478 | #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 | 478 | #define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 |
| 479 | #define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 | 479 | #define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 |
| 480 | #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 | 480 | #define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 |
| 481 | #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 | 481 | #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 |
| 482 | #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 | 482 | #define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 |
| 483 | #define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 | 483 | #define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 |
| 484 | #define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 | 484 | #define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 |
| 485 | #define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 | 485 | #define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 |
| 486 | #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 | 486 | #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 |
| 487 | #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 | 487 | #define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 |
| 488 | #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 | 488 | #define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 |
| 489 | #define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 | 489 | #define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 |
| 490 | #define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 | 490 | #define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 |
| 491 | #define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 | 491 | #define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 |
| 492 | #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 | 492 | #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 |
| 493 | #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 | 493 | #define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 |
| 494 | #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 | 494 | #define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 |
| 495 | #define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 | 495 | #define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 |
| 496 | #define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 | 496 | #define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 |
| 497 | #define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 | 497 | #define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 |
| 498 | #define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 | 498 | #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 |
| 499 | #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 | 499 | #define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 |
| 500 | #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 | 500 | #define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 |
| 501 | #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 | 501 | #define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 |
| 502 | #define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 | 502 | #define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 |
| 503 | #define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 | 503 | #define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 |
| 504 | #define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 | 504 | #define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 |
| 505 | #define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 | 505 | #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 |
| 506 | #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 | 506 | #define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 |
| 507 | #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 | 507 | #define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 |
| 508 | #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 | 508 | #define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 |
| 509 | #define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 | 509 | #define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 |
| 510 | #define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 | 510 | #define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 |
| 511 | #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 | 511 | #define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 |
| 512 | #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 | 512 | #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 |
| 513 | #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 | 513 | #define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 |
| 514 | #define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 | 514 | #define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 |
| 515 | #define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 | 515 | #define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 |
| 516 | #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 | 516 | #define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 |
| 517 | #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 | 517 | #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 |
| 518 | #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 | 518 | #define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 |
| 519 | #define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 | 519 | #define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 |
| 520 | #define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 | 520 | #define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 |
| 521 | #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 | 521 | #define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 |
| 522 | #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 | 522 | #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 |
| 523 | #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 | 523 | #define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 |
| 524 | #define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 | 524 | #define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 |
| 525 | #define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 | 525 | #define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 |
| 526 | #define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 | 526 | #define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 |
| 527 | #define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 | 527 | #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 |
| 528 | #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 | 528 | #define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 |
| 529 | #define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 | 529 | #define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 |
| 530 | #define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 | 530 | #define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 |
| 531 | #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 | 531 | #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 |
| 532 | #define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 | 532 | #define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 |
| 533 | #define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 | 533 | #define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 |
| 534 | #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 | 534 | #define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 |
| 535 | #define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 | 535 | #define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 |
| 536 | #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 | 536 | #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 |
| 537 | #define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 | 537 | #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 |
| 538 | #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 | 538 | #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 |
| 539 | #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 | 539 | #define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 |
| 540 | #define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 | 540 | #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 |
| 541 | #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 | 541 | #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 |
| 542 | #define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 | 542 | #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 |
| 543 | #define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 | 543 | #define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 |
| 544 | #define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 | 544 | #define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 |
| 545 | #define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 | 545 | #define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 |
| 546 | #define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 | 546 | #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 |
| 547 | #define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 | 547 | #define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 |
| 548 | #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 | 548 | #define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 |
| 549 | #define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 | 549 | #define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 |
| 550 | #define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 | 550 | #define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 |
| 551 | #define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 | 551 | #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 |
| 552 | #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 | 552 | #define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 |
| 553 | #define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 | 553 | #define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 |
| 554 | #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 | 554 | #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 |
| 555 | #define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 | 555 | #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 |
| 556 | #define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 | 556 | #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 |
| 557 | #define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 | 557 | #define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 |
| 558 | #define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 | 558 | #define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 |
| 559 | #define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 | 559 | #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 |
| 560 | #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 | 560 | #define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 |
| 561 | #define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 | 561 | #define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 |
| 562 | #define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 | 562 | #define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 |
| 563 | #define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 | 563 | #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 |
| 564 | #define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 | 564 | #define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 |
| 565 | #define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 | 565 | #define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 |
| 566 | #define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 | 566 | #define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 |
| 567 | #define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 | 567 | #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 |
| 568 | #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 | 568 | #define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 |
| 569 | #define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 | 569 | #define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 |
| 570 | #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 | 570 | #define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 |
| 571 | #define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 | 571 | #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 |
| 572 | #define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 | 572 | #define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 |
| 573 | #define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 | 573 | #define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 |
| 574 | #define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 | 574 | #define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 |
| 575 | #define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 | 575 | #define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 |
| 576 | #define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 | 576 | #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 |
| 577 | #define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 | 577 | #define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 |
| 578 | #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 | 578 | #define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 |
| 579 | #define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 | 579 | #define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 |
| 580 | #define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 | 580 | #define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 |
| 581 | #define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 | 581 | #define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 |
| 582 | #define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 | 582 | #define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 |
| 583 | #define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 | 583 | #define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 |
| 584 | #define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 | 584 | #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 |
| 585 | #define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 | 585 | #define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 |
| 586 | #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 | 586 | #define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 |
| 587 | #define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 | 587 | #define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 |
| 588 | #define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 | 588 | #define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 |
| 589 | #define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 | 589 | #define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 |
| 590 | #define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 | 590 | #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 |
| 591 | #define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 | 591 | #define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 |
| 592 | #define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 | 592 | #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 |
| 593 | #define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 | 593 | #define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 |
| 594 | #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 | 594 | #define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 |
| 595 | #define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 | 595 | #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 |
| 596 | #define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 | 596 | #define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 |
| 597 | #define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 | 597 | #define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 |
| 598 | #define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 | 598 | #define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 |
| 599 | #define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 | 599 | #define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 |
| 600 | #define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 | 600 | #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 |
| 601 | #define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 | 601 | #define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 |
| 602 | #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 | 602 | #define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 |
| 603 | #define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 | 603 | #define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 |
| 604 | #define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 | 604 | #define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 |
| 605 | #define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 | 605 | #define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 |
| 606 | #define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 | 606 | #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 |
| 607 | #define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 | 607 | #define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 |
| 608 | #define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 | 608 | #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 |
| 609 | #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 | 609 | #define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 |
| 610 | #define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 | 610 | #define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 |
| 611 | #define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 | 611 | #define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 |
| 612 | #define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 | 612 | #define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 |
| 613 | #define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 | 613 | #define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 |
| 614 | #define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 | 614 | #define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 |
| 615 | #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 | 615 | #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 |
| 616 | #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 | 616 | #define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 |
| 617 | #define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 | 617 | #define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 |
| 618 | #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 | 618 | #define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 |
| 619 | #define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 | 619 | #define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 |
| 620 | #define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 | 620 | #define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 |
| 621 | #define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 | 621 | #define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 |
| 622 | #define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 | 622 | #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 |
| 623 | #define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 | 623 | #define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 |
| 624 | #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 | 624 | #define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 |
| 625 | #define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 | 625 | #define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 |
| 626 | #define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 | 626 | #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 |
| 627 | #define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 | 627 | #define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 |
| 628 | #define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 | 628 | #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 |
| 629 | #define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 | 629 | #define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 |
| 630 | #define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 | 630 | #define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 |
| 631 | #define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 | 631 | #define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 |
| 632 | #define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 | 632 | #define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 |
| 633 | #define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 | 633 | #define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 |
| 634 | #define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 | 634 | #define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 |
| 635 | #define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 | 635 | #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 |
| 636 | #define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 | 636 | #define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 |
| 637 | #define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 | 637 | #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 |
| 638 | #define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 | 638 | #define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 |
| 639 | #define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 | 639 | #define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 |
| 640 | #define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 | 640 | #define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 |
| 641 | #define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 | 641 | #define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 |
| 642 | #define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 | 642 | #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 |
| 643 | #define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 | 643 | #define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 |
| 644 | #define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 | 644 | #define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 |
| 645 | #define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 | 645 | #define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 |
| 646 | #define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 | 646 | #define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 |
| 647 | #define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 | 647 | #define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 |
| 648 | #define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 | 648 | #define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 |
| 649 | #define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 | 649 | #define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 |
| 650 | #define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 | 650 | #define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 |
| 651 | #define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 | 651 | #define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 |
| 652 | #define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 | 652 | #define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 |
| 653 | #define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 | 653 | #define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 |
| 654 | #define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 | 654 | #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 |
| 655 | #define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 | 655 | #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 |
| 656 | #define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 | 656 | #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 |
| 657 | #define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 | 657 | #define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 |
| 658 | #define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 | 658 | #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 |
| 659 | #define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 | 659 | #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 |
| 660 | #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 | 660 | #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 |
| 661 | #define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 | 661 | #define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 |
| 662 | #define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 | 662 | #define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 |
| 663 | #define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 | 663 | #define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 |
| 664 | #define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 | 664 | #define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 |
| 665 | #define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 | 665 | #define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 |
| 666 | #define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 | 666 | #define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 |
| 667 | #define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 | 667 | #define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 |
| 668 | #define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 | 668 | #define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 |
| 669 | #define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 | 669 | #define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 |
| 670 | #define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 | 670 | #define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 |
| 671 | #define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 | 671 | #define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 |
| 672 | #define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 | 672 | #define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 |
| 673 | #define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 | 673 | #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 |
| 674 | #define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 | 674 | #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 |
| 675 | #define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 | 675 | #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 |
| 676 | #define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 | 676 | #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 |
| 677 | #define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 | 677 | #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 |
| 678 | #define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 | 678 | #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 |
| 679 | #define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 | 679 | #define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 |
| 680 | #define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 | 680 | #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 |
| 681 | #define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 | 681 | #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 |
| 682 | #define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 | 682 | #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 |
| 683 | #define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 | 683 | #define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 |
| 684 | #define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 | 684 | #define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 |
| 685 | #define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 | 685 | #define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 |
| 686 | #define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 | 686 | #define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 |
| 687 | #define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 | 687 | #define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 |
| 688 | #define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 | 688 | #define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 |
| 689 | #define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 | 689 | #define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 |
| 690 | #define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 | 690 | #define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 |
| 691 | #define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 | 691 | #define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 |
| 692 | #define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 | 692 | #define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 |
| 693 | #define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 | 693 | #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 |
| 694 | #define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 | 694 | #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 |
| 695 | #define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 | 695 | #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 |
| 696 | #define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 | 696 | #define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 |
| 697 | #define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 | 697 | #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 |
| 698 | #define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 | 698 | #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 |
| 699 | #define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 | 699 | #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 |
| 700 | #define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 | 700 | #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 |
| 701 | #define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 | 701 | #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 |
| 702 | #define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 | 702 | #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 |
| 703 | #define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 | 703 | #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 |
| 704 | #define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 | 704 | #define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 |
| 705 | #define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 | 705 | #define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 |
| 706 | #define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 | 706 | #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 |
| 707 | #define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 | 707 | #define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 |
| 708 | #define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 | 708 | #define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 |
| 709 | #define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 | 709 | #define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 |
| 710 | #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 | 710 | #define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 |
| 711 | #define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 | 711 | #define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 |
| 712 | #define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 | 712 | #define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 |
| 713 | #define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 | 713 | #define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 |
| 714 | #define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 | 714 | #define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 |
| 715 | #define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 | 715 | #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 |
| 716 | #define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 | 716 | #define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 |
| 717 | #define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 | 717 | #define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 |
| 718 | #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 | 718 | #define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 |
| 719 | #define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 | 719 | #define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 |
| 720 | #define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 | 720 | #define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 |
| 721 | #define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 | 721 | #define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 |
| 722 | #define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 | 722 | #define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 |
| 723 | #define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 | 723 | #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 |
| 724 | #define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 | 724 | #define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 |
| 725 | #define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 | 725 | #define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 |
| 726 | #define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 | 726 | #define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 |
| 727 | #define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 | 727 | #define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 |
| 728 | #define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 | 728 | #define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 |
| 729 | #define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 | 729 | #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 |
| 730 | #define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 | 730 | #define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 |
| 731 | #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 | 731 | #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 |
| 732 | #define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 | 732 | #define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 |
| 733 | #define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 | 733 | #define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 |
| 734 | #define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 | 734 | #define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 |
| 735 | #define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 | 735 | #define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 |
| 736 | #define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 | 736 | #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 |
| 737 | #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 | 737 | #define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 |
| 738 | #define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 | 738 | #define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 |
| 739 | #define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 | 739 | #define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 |
| 740 | #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 | 740 | #define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 |
| 741 | #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 | 741 | #define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 |
| 742 | #define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 | 742 | #define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 |
| 743 | #define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 | 743 | #define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 |
| 744 | #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 | 744 | #define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 |
| 745 | #define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 | 745 | #define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 |
| 746 | #define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 | 746 | #define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 |
| 747 | #define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 | 747 | #define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 |
| 748 | #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 | 748 | #define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 |
| 749 | #define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 | 749 | #define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 |
| 750 | #define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 | 750 | #define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 |
| 751 | #define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 | 751 | #define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 |
| 752 | #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 | 752 | #define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 |
| 753 | #define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 | 753 | #define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 |
| 754 | #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 | 754 | #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 |
| 755 | #define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 | 755 | #define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 |
| 756 | #define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 | 756 | #define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 |
| 757 | #define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 | 757 | #define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 |
| 758 | #define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 | 758 | #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 |
| 759 | #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 | 759 | #define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 |
| 760 | #define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 | 760 | #define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 |
| 761 | #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 | 761 | #define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 |
| 762 | #define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 | 762 | #define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 |
| 763 | #define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 | 763 | #define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 |
| 764 | #define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 | 764 | #define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 |
| 765 | #define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 | 765 | #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 |
| 766 | #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 | 766 | #define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 |
| 767 | #define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 | 767 | #define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 |
| 768 | #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 | 768 | #define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 |
| 769 | #define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 | 769 | #define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 |
| 770 | #define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 | 770 | #define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 |
| 771 | #define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 | 771 | #define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 |
| 772 | #define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 | 772 | #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 |
| 773 | #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 | 773 | #define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 |
| 774 | #define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 | 774 | #define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 |
| 775 | #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 | 775 | #define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 |
| 776 | #define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 | 776 | #define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 |
| 777 | #define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 | 777 | #define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 |
| 778 | #define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 | 778 | #define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 |
| 779 | #define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 | 779 | #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 |
| 780 | #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 | 780 | #define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 |
| 781 | #define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 | 781 | #define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 |
| 782 | #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 | 782 | #define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 |
| 783 | #define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 | 783 | #define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 |
| 784 | #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 | 784 | #define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 |
| 785 | #define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 | 785 | #define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 |
| 786 | #define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 | 786 | #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 |
| 787 | #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 | 787 | #define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 |
| 788 | #define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 | 788 | #define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 |
| 789 | #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 | 789 | #define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 |
| 790 | #define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 | 790 | #define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 |
| 791 | #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 | 791 | #define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 |
| 792 | #define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 | 792 | #define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 |
| 793 | #define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 | 793 | #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 |
| 794 | #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 | 794 | #define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 |
| 795 | #define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 | 795 | #define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 |
| 796 | #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 | 796 | #define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 |
| 797 | #define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 | 797 | #define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 |
| 798 | #define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 | 798 | #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 |
| 799 | #define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 | 799 | #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 |
| 800 | #define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 | 800 | #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 |
| 801 | #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 | 801 | #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 |
| 802 | #define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 | 802 | #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 |
| 803 | #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 | 803 | #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 |
| 804 | #define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 | 804 | #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 |
| 805 | #define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 | 805 | #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 |
| 806 | #define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 | 806 | #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 |
| 807 | #define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 | 807 | #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 |
| 808 | #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 | 808 | #define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 |
| 809 | #define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 | 809 | #define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 |
| 810 | #define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 | 810 | #define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 |
| 811 | #define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 | 811 | #define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 |
| 812 | #define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 | 812 | #define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 |
| 813 | #define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 | 813 | #define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 |
| 814 | #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 | 814 | #define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 |
| 815 | #define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 | 815 | #define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 |
| 816 | #define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 | 816 | #define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 |
| 817 | #define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 | 817 | #define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 |
| 818 | #define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 | 818 | #define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 |
| 819 | #define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 | 819 | #define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 |
| 820 | #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 | 820 | #define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 |
| 821 | #define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 | 821 | #define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 |
| 822 | #define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 | 822 | #define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 |
| 823 | #define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 | 823 | #define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 |
| 824 | #define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 | 824 | #define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 |
| 825 | #define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 | 825 | #define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 |
| 826 | #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 | 826 | #define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 |
| 827 | #define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 | 827 | #define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 |
| 828 | #define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 | 828 | #define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 |
| 829 | #define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 | 829 | #define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 |
| 830 | #define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 | 830 | #define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 |
| 831 | #define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 | 831 | #define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 |
| 832 | #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 | 832 | #define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 |
| 833 | #define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 | 833 | #define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 |
| 834 | #define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 | 834 | #define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 |
| 835 | #define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 | 835 | #define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 |
| 836 | #define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 | 836 | #define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 |
| 837 | #define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 | 837 | #define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 |
| 838 | #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 | 838 | #define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 |
| 839 | #define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 | 839 | #define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 |
| 840 | #define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 | 840 | #define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 |
| 841 | #define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 | 841 | #define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 |
| 842 | #define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 | 842 | #define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 |
| 843 | #define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 | 843 | #define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 |
| 844 | #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 | 844 | #define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 |
| 845 | #define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 | 845 | #define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 |
| 846 | #define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 | 846 | #define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 |
| 847 | #define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 | 847 | #define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 |
| 848 | #define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 | 848 | #define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 |
| 849 | #define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 | 849 | #define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 |
| 850 | #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 | 850 | #define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 |
| 851 | #define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 | 851 | #define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 |
| 852 | #define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 | 852 | #define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 |
| 853 | #define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 | 853 | #define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 |
| 854 | #define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 | 854 | #define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 |
| 855 | #define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 | 855 | #define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 |
| 856 | #define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 | 856 | #define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 |
| 857 | #define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 | 857 | #define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 |
| 858 | #define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 | 858 | #define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 |
| 859 | #define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 | 859 | #define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 |
| 860 | #define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 | 860 | #define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 |
| 861 | #define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 | 861 | #define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 |
| 862 | #define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 | 862 | #define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 |
| 863 | #define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 | 863 | #define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 |
| 864 | #define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 | 864 | #define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 |
| 865 | #define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 | 865 | #define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 |
| 866 | #define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 | 866 | #define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 |
| 867 | #define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 | 867 | #define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 |
| 868 | #define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 | 868 | #define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 |
| 869 | #define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 | 869 | #define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 |
| 870 | #define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 | 870 | #define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 |
| 871 | #define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 | 871 | #define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 |
| 872 | #define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 | 872 | #define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 |
| 873 | #define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 | 873 | #define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 |
| 874 | #define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 | 874 | #define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 |
| 875 | #define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 | 875 | #define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 |
| 876 | #define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 | 876 | #define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 |
| 877 | #define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 | 877 | #define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 |
| 878 | #define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 | 878 | #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 |
| 879 | #define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 | 879 | #define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 |
| 880 | #define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 | 880 | #define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 |
| 881 | #define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 | 881 | #define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 |
| 882 | #define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 | 882 | #define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 |
| 883 | #define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 | 883 | #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 |
| 884 | #define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 | 884 | #define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 |
| 885 | #define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 | 885 | #define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 |
| 886 | #define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 | 886 | #define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 |
| 887 | #define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 | 887 | #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 |
| 888 | #define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 | 888 | #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 |
| 889 | #define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 | 889 | #define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 |
| 890 | #define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 | 890 | #define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 |
| 891 | #define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 | 891 | #define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 |
| 892 | #define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 | 892 | #define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 |
| 893 | #define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 | 893 | #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 |
| 894 | #define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 | 894 | #define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 |
| 895 | #define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 | 895 | #define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 |
| 896 | #define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 | 896 | #define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 |
| 897 | #define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 | 897 | #define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 |
| 898 | #define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 | 898 | #define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 |
| 899 | #define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 | 899 | #define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 |
| 900 | #define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 | 900 | #define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 |
| 901 | #define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 | 901 | #define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 |
| 902 | #define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 | 902 | #define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 |
| 903 | #define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 | 903 | #define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 |
| 904 | #define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 | 904 | #define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 |
| 905 | #define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 | 905 | #define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 |
| 906 | #define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 | 906 | #define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 |
| 907 | #define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 | 907 | #define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 |
| 908 | #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 | 908 | #define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 |
| 909 | #define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 | 909 | #define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 |
| 910 | #define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 | 910 | #define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 |
| 911 | #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 | 911 | #define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 |
| 912 | #define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 | 912 | #define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 |
| 913 | #define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 | 913 | #define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 |
| 914 | #define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 | 914 | #define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 |
| 915 | #define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 | 915 | #define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 |
| 916 | #define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 | 916 | #define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 |
| 917 | #define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 | 917 | #define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 |
| 918 | #define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 | 918 | #define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 |
| 919 | #define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 | 919 | #define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 |
| 920 | #define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 | 920 | #define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 |
| 921 | #define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 | 921 | #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 |
| 922 | #define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 | 922 | #define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 |
| 923 | #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 | 923 | #define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 |
| 924 | #define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 | 924 | #define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 |
| 925 | #define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 | 925 | #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 |
| 926 | #define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 | 926 | #define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 |
| 927 | #define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 | 927 | #define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 |
| 928 | #define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 | 928 | #define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 |
| 929 | #define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 | 929 | #define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 |
| 930 | #define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 | 930 | #define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 |
| 931 | #define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 | 931 | #define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 |
| 932 | #define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 | 932 | #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 |
| 933 | #define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 | 933 | #define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 |
| 934 | #define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 | 934 | #define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 |
| 935 | #define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 | 935 | #define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 |
| 936 | #define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 | 936 | #define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 |
| 937 | #define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 | 937 | #define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 |
| 938 | #define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 | 938 | #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 |
| 939 | #define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 | 939 | #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 |
| 940 | #define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 | 940 | #define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 |
| 941 | #define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 | 941 | #define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 |
| 942 | #define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 | 942 | #define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 |
| 943 | #define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 | 943 | #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 |
| 944 | #define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 | 944 | #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 |
| 945 | #define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 | 945 | #define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 |
| 946 | #define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 | 946 | #define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 |
| 947 | #define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 | 947 | #define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 |
| 948 | #define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 | 948 | #define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 |
| 949 | #define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 | 949 | #define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 |
| 950 | #define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 | 950 | #define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 |
| 951 | #define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 | 951 | #define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 |
| 952 | #define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 | 952 | #define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 |
| 953 | #define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 | 953 | #define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 |
| 954 | #define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 | 954 | #define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 |
| 955 | #define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 | 955 | #define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 |
| 956 | #define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 | 956 | #define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 |
| 957 | #define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 | 957 | #define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 |
| 958 | #define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 | 958 | #define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 |
| 959 | #define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 | 959 | #define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 |
| 960 | #define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 | 960 | #define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 |
| 961 | #define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 | 961 | #define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 |
| 962 | #define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 | 962 | #define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 |
| 963 | #define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 | 963 | #define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 |
| 964 | #define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 | 964 | #define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 |
| 965 | #define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 | 965 | #define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 |
| 966 | #define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 | 966 | #define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 |
| 967 | #define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 | 967 | #define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 |
| 968 | #define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 | 968 | #define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 |
| 969 | #define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 | 969 | #define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 |
| 970 | #define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 | 970 | #define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 |
| 971 | #define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 | 971 | #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 |
| 972 | #define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 | 972 | #define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 |
| 973 | #define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 | 973 | #define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 |
| 974 | #define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 | 974 | #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 |
| 975 | #define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 | 975 | #define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 |
| 976 | #define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 | 976 | #define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 |
| 977 | #define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 | 977 | #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 |
| 978 | #define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 | 978 | #define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 |
| 979 | #define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 | 979 | #define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 |
| 980 | #define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 | 980 | #define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 |
| 981 | #define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 | 981 | #define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 |
| 982 | #define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 | 982 | #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 |
| 983 | #define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 | 983 | #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 |
| 984 | #define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 | 984 | #define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 |
| 985 | #define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 | 985 | #define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 |
| 986 | #define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 | 986 | #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 |
| 987 | #define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 | 987 | #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 |
| 988 | #define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 | 988 | #define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 |
| 989 | #define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 | 989 | #define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 |
| 990 | #define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 | 990 | #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 |
| 991 | #define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 | 991 | #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 |
| 992 | #define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 | 992 | #define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 |
| 993 | #define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 | 993 | #define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 |
| 994 | #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 | 994 | #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 |
| 995 | #define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 | 995 | #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 |
| 996 | #define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 | 996 | #define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 |
| 997 | #define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 | 997 | #define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 |
| 998 | #define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 | 998 | #define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 |
| 999 | #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 | 999 | #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 |
| 1000 | #define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 | 1000 | #define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 |
| 1001 | #define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 | 1001 | #define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 |
| 1002 | #define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 | 1002 | #define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 |
| 1003 | #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 | 1003 | #define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 |
| 1004 | #define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 | 1004 | #define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 |
| 1005 | #define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 | 1005 | #define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 |
| 1006 | #define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 | 1006 | #define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 |
| 1007 | #define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 | 1007 | #define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 |
| 1008 | #define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 | 1008 | #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 |
| 1009 | #define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 | 1009 | #define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 |
| 1010 | #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 | 1010 | #define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 |
| 1011 | #define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 | 1011 | #define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 |
| 1012 | #define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 | 1012 | #define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 |
| 1013 | #define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 | 1013 | #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 |
| 1014 | #define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 | 1014 | #define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 |
| 1015 | #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 | 1015 | #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 |
| 1016 | #define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 | 1016 | #define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 |
| 1017 | #define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 | 1017 | #define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 |
| 1018 | #define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 | 1018 | #define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 |
| 1019 | #define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 | 1019 | #define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 |
| 1020 | #define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 | 1020 | #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 |
| 1021 | #define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 | 1021 | #define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 |
| 1022 | #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 | 1022 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 |
| 1023 | #define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 | 1023 | #define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 |
| 1024 | #define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 | 1024 | #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 |
| 1025 | #define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 | 1025 | #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 |
| 1026 | #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 | 1026 | #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 |
| 1027 | #define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 | 1027 | #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 |
| 1028 | #define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 | 1028 | #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 |
| 1029 | #define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 | 1029 | #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 |
| 1030 | #define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 | 1030 | #define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 |
| 1031 | #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 | 1031 | #define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 |
| 1032 | #define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 | 1032 | #define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 |
| 1033 | #define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 | 1033 | #define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 |
| 1034 | #define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 | 1034 | #define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 |
| 1035 | #define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 | 1035 | #define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 |
| 1036 | #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 | 1036 | #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 |
| 1037 | #define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 | 1037 | #define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 |
| 1038 | #define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 | 1038 | #define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 |
| 1039 | #define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 | 1039 | #define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 |
| 1040 | #define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 | ||
| 1041 | #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 | ||
| 1042 | #define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 | ||
| 1043 | #define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 | ||
| 1040 | 1044 | ||
| 1041 | #endif /* __DTS_IMX6Q_PINFUNC_H */ | 1045 | #endif /* __DTS_IMX6Q_PINFUNC_H */ |
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 09a75807bc6d..334b9247e78c 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts | |||
| @@ -20,24 +20,6 @@ | |||
| 20 | compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; | 20 | compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | &iomuxc { | 23 | &sata { |
| 24 | pinctrl-names = "default"; | 24 | status = "okay"; |
| 25 | pinctrl-0 = <&pinctrl_hog>; | ||
| 26 | |||
| 27 | hog { | ||
| 28 | pinctrl_hog: hoggrp { | ||
| 29 | fsl,pins = < | ||
| 30 | MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 | ||
| 31 | MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 | ||
| 32 | >; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | ecspi1 { | ||
| 37 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | ||
| 38 | fsl,pins = < | ||
| 39 | MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 40 | >; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | 25 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 6a000666c147..3530280f5150 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
| @@ -65,6 +65,10 @@ | |||
| 65 | }; | 65 | }; |
| 66 | }; | 66 | }; |
| 67 | 67 | ||
| 68 | &sata { | ||
| 69 | status = "okay"; | ||
| 70 | }; | ||
| 71 | |||
| 68 | &ecspi1 { | 72 | &ecspi1 { |
| 69 | fsl,spi-num-chipselects = <1>; | 73 | fsl,spi-num-chipselects = <1>; |
| 70 | cs-gpios = <&gpio3 19 0>; | 74 | cs-gpios = <&gpio3 19 0>; |
| @@ -91,14 +95,14 @@ | |||
| 91 | hog { | 95 | hog { |
| 92 | pinctrl_hog: hoggrp { | 96 | pinctrl_hog: hoggrp { |
| 93 | fsl,pins = < | 97 | fsl,pins = < |
| 94 | MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 | 98 | MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 |
| 95 | MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 | 99 | MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 |
| 96 | MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 | 100 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 |
| 97 | MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 | 101 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 |
| 98 | MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 | 102 | MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| 99 | MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 | 103 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 |
| 100 | MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 | 104 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 |
| 101 | MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 | 105 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 |
| 102 | >; | 106 | >; |
| 103 | }; | 107 | }; |
| 104 | }; | 108 | }; |
| @@ -163,7 +167,7 @@ | |||
| 163 | codec: sgtl5000@0a { | 167 | codec: sgtl5000@0a { |
| 164 | compatible = "fsl,sgtl5000"; | 168 | compatible = "fsl,sgtl5000"; |
| 165 | reg = <0x0a>; | 169 | reg = <0x0a>; |
| 166 | clocks = <&clks 169>; | 170 | clocks = <&clks 201>; |
| 167 | VDDA-supply = <®_2p5v>; | 171 | VDDA-supply = <®_2p5v>; |
| 168 | VDDIO-supply = <®_3p3v>; | 172 | VDDIO-supply = <®_3p3v>; |
| 169 | }; | 173 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 0038228c508c..9cbdfe7a0931 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts | |||
| @@ -20,21 +20,6 @@ | |||
| 20 | compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; | 20 | compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | &iomuxc { | 23 | &sata { |
| 24 | pinctrl-names = "default"; | 24 | status = "okay"; |
| 25 | pinctrl-0 = <&pinctrl_hog>; | ||
| 26 | |||
| 27 | hog { | ||
| 28 | pinctrl_hog: hoggrp { | ||
| 29 | fsl,pins = < | ||
| 30 | MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 31 | MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 32 | MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000 | ||
| 33 | MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | ||
| 34 | MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | ||
| 35 | MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | ||
| 36 | MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 37 | >; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | }; | 25 | }; |
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts new file mode 100644 index 000000000000..36be17f207b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-wandboard.dts | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | /dts-v1/; | ||
| 12 | #include "imx6q.dtsi" | ||
| 13 | #include "imx6qdl-wandboard.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Wandboard i.MX6 Quad Board"; | ||
| 17 | compatible = "wand,imx6q-wandboard", "fsl,imx6q"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x10000000 0x80000000>; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &sata { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index ba09dc32324e..f024ef28b34b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -8,8 +8,8 @@ | |||
| 8 | * | 8 | * |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include "imx6qdl.dtsi" | ||
| 12 | #include "imx6q-pinfunc.h" | 11 | #include "imx6q-pinfunc.h" |
| 12 | #include "imx6qdl.dtsi" | ||
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | cpus { | 15 | cpus { |
| @@ -61,6 +61,12 @@ | |||
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | soc { | 63 | soc { |
| 64 | ocram: sram@00900000 { | ||
| 65 | compatible = "mmio-sram"; | ||
| 66 | reg = <0x00900000 0x40000>; | ||
| 67 | clocks = <&clks 142>; | ||
| 68 | }; | ||
| 69 | |||
| 64 | aips-bus@02000000 { /* AIPS1 */ | 70 | aips-bus@02000000 { /* AIPS1 */ |
| 65 | spba-bus@02000000 { | 71 | spba-bus@02000000 { |
| 66 | ecspi5: ecspi@02018000 { | 72 | ecspi5: ecspi@02018000 { |
| @@ -77,357 +83,54 @@ | |||
| 77 | 83 | ||
| 78 | iomuxc: iomuxc@020e0000 { | 84 | iomuxc: iomuxc@020e0000 { |
| 79 | compatible = "fsl,imx6q-iomuxc"; | 85 | compatible = "fsl,imx6q-iomuxc"; |
| 80 | reg = <0x020e0000 0x4000>; | ||
| 81 | |||
| 82 | /* shared pinctrl settings */ | ||
| 83 | audmux { | ||
| 84 | pinctrl_audmux_1: audmux-1 { | ||
| 85 | fsl,pins = < | ||
| 86 | MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | ||
| 87 | MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | ||
| 88 | MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | ||
| 89 | MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | ||
| 90 | >; | ||
| 91 | }; | ||
| 92 | |||
| 93 | pinctrl_audmux_2: audmux-2 { | ||
| 94 | fsl,pins = < | ||
| 95 | MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 96 | MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 97 | MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 98 | MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 99 | >; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | ecspi1 { | ||
| 104 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 105 | fsl,pins = < | ||
| 106 | MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 107 | MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 108 | MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 109 | >; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | |||
| 113 | ecspi3 { | ||
| 114 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 115 | fsl,pins = < | ||
| 116 | MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 117 | MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 118 | MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 119 | >; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | enet { | ||
| 124 | pinctrl_enet_1: enetgrp-1 { | ||
| 125 | fsl,pins = < | ||
| 126 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 127 | MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 128 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 129 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 130 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 131 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 132 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 133 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 134 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 135 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 136 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 137 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 138 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 139 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 140 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 141 | MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | pinctrl_enet_2: enetgrp-2 { | ||
| 146 | fsl,pins = < | ||
| 147 | MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 148 | MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 149 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 150 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 151 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 152 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 153 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 154 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 155 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 156 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 157 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 158 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 159 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 160 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 161 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 162 | >; | ||
| 163 | }; | ||
| 164 | |||
| 165 | pinctrl_enet_3: enetgrp-3 { | ||
| 166 | fsl,pins = < | ||
| 167 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 168 | MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 169 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 170 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 171 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 172 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 173 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 174 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 175 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 176 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 177 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 178 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 179 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 180 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 181 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 182 | MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 183 | >; | ||
| 184 | }; | ||
| 185 | }; | ||
| 186 | |||
| 187 | gpmi-nand { | ||
| 188 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 189 | fsl,pins = < | ||
| 190 | MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 191 | MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 192 | MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 193 | MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 194 | MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 195 | MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 196 | MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 197 | MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 198 | MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 199 | MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 200 | MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 201 | MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 202 | MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 203 | MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 204 | MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 205 | MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 206 | MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 207 | >; | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | |||
| 211 | i2c1 { | ||
| 212 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 213 | fsl,pins = < | ||
| 214 | MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 215 | MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 216 | >; | ||
| 217 | }; | ||
| 218 | 86 | ||
| 219 | pinctrl_i2c1_2: i2c1grp-2 { | 87 | ipu2 { |
| 220 | fsl,pins = < | 88 | pinctrl_ipu2_1: ipu2grp-1 { |
| 221 | MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | 89 | fsl,pins = < |
| 222 | MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | 90 | MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 |
| 223 | >; | 91 | MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 |
| 224 | }; | 92 | MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 |
| 225 | }; | 93 | MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 |
| 226 | 94 | MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 | |
| 227 | i2c2 { | 95 | MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 |
| 228 | pinctrl_i2c2_1: i2c2grp-1 { | 96 | MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 |
| 229 | fsl,pins = < | 97 | MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 |
| 230 | MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | 98 | MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 |
| 231 | MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | 99 | MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 |
| 100 | MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 | ||
| 101 | MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 | ||
| 102 | MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 | ||
| 103 | MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 | ||
| 104 | MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 | ||
| 105 | MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 | ||
| 106 | MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 | ||
| 107 | MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 | ||
| 108 | MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 | ||
| 109 | MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 | ||
| 110 | MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 | ||
| 111 | MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 | ||
| 112 | MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 | ||
| 113 | MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 | ||
| 114 | MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 | ||
| 115 | MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 | ||
| 116 | MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 | ||
| 117 | MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 | ||
| 118 | MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 | ||
| 232 | >; | 119 | >; |
| 233 | }; | 120 | }; |
| 234 | }; | 121 | }; |
| 235 | |||
| 236 | i2c3 { | ||
| 237 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 238 | fsl,pins = < | ||
| 239 | MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 240 | MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 241 | >; | ||
| 242 | }; | ||
| 243 | }; | ||
| 244 | |||
| 245 | uart1 { | ||
| 246 | pinctrl_uart1_1: uart1grp-1 { | ||
| 247 | fsl,pins = < | ||
| 248 | MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 249 | MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 250 | >; | ||
| 251 | }; | ||
| 252 | }; | ||
| 253 | |||
| 254 | uart2 { | ||
| 255 | pinctrl_uart2_1: uart2grp-1 { | ||
| 256 | fsl,pins = < | ||
| 257 | MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 258 | MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 259 | >; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | |||
| 263 | uart4 { | ||
| 264 | pinctrl_uart4_1: uart4grp-1 { | ||
| 265 | fsl,pins = < | ||
| 266 | MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 267 | MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 268 | >; | ||
| 269 | }; | ||
| 270 | }; | ||
| 271 | |||
| 272 | usbotg { | ||
| 273 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 274 | fsl,pins = < | ||
| 275 | MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 276 | >; | ||
| 277 | }; | ||
| 278 | |||
| 279 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 280 | fsl,pins = < | ||
| 281 | MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 282 | >; | ||
| 283 | }; | ||
| 284 | }; | ||
| 285 | |||
| 286 | usdhc2 { | ||
| 287 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 288 | fsl,pins = < | ||
| 289 | MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 290 | MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 291 | MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 292 | MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 293 | MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 294 | MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 295 | MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 296 | MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 297 | MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 298 | MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 299 | >; | ||
| 300 | }; | ||
| 301 | |||
| 302 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 303 | fsl,pins = < | ||
| 304 | MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 305 | MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 306 | MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 307 | MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 308 | MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 309 | MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 310 | >; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | |||
| 314 | usdhc3 { | ||
| 315 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 316 | fsl,pins = < | ||
| 317 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 318 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 319 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 320 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 321 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 322 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 323 | MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 324 | MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 325 | MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 326 | MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 327 | >; | ||
| 328 | }; | ||
| 329 | |||
| 330 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 331 | fsl,pins = < | ||
| 332 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 333 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 334 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 335 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 336 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 337 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 338 | >; | ||
| 339 | }; | ||
| 340 | }; | ||
| 341 | |||
| 342 | usdhc4 { | ||
| 343 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| 344 | fsl,pins = < | ||
| 345 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 346 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 347 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 348 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 349 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 350 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 351 | MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 352 | MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 353 | MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 354 | MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 355 | >; | ||
| 356 | }; | ||
| 357 | |||
| 358 | pinctrl_usdhc4_2: usdhc4grp-2 { | ||
| 359 | fsl,pins = < | ||
| 360 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 361 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 362 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 363 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 364 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 365 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 366 | >; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 370 | weim { | ||
| 371 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 372 | fsl,pins = < | ||
| 373 | MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 374 | >; | ||
| 375 | }; | ||
| 376 | |||
| 377 | pinctrl_weim_nor_1: weimnorgrp-1 { | ||
| 378 | fsl,pins = < | ||
| 379 | MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 380 | MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 381 | MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 382 | /* data */ | ||
| 383 | MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 384 | MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 385 | MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 386 | MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 387 | MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 388 | MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 389 | MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 390 | MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 391 | MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 392 | MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 393 | MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 394 | MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 395 | MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 396 | MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 397 | MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 398 | MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 399 | /* address */ | ||
| 400 | MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 401 | MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 402 | MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 403 | MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 404 | MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 405 | MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 406 | MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 407 | MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 408 | MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 409 | MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 410 | MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 411 | MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 412 | MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 413 | MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 414 | MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 415 | MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 416 | MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 417 | MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 418 | MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 419 | MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 420 | MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 421 | MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 422 | MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 423 | MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 424 | >; | ||
| 425 | }; | ||
| 426 | |||
| 427 | }; | ||
| 428 | }; | 122 | }; |
| 429 | }; | 123 | }; |
| 430 | 124 | ||
| 125 | sata: sata@02200000 { | ||
| 126 | compatible = "fsl,imx6q-ahci"; | ||
| 127 | reg = <0x02200000 0x4000>; | ||
| 128 | interrupts = <0 39 0x04>; | ||
| 129 | clocks = <&clks 154>, <&clks 187>, <&clks 105>; | ||
| 130 | clock-names = "sata", "sata_ref", "ahb"; | ||
| 131 | status = "disabled"; | ||
| 132 | }; | ||
| 133 | |||
| 431 | ipu2: ipu@02800000 { | 134 | ipu2: ipu@02800000 { |
| 432 | #crtc-cells = <1>; | 135 | #crtc-cells = <1>; |
| 433 | compatible = "fsl,imx6q-ipu"; | 136 | compatible = "fsl,imx6q-ipu"; |
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e994011220e7..1cbbc5160d27 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |||
| @@ -45,6 +45,28 @@ | |||
| 45 | status = "okay"; | 45 | status = "okay"; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | &iomuxc { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&pinctrl_hog>; | ||
| 51 | |||
| 52 | hog { | ||
| 53 | pinctrl_hog: hoggrp { | ||
| 54 | fsl,pins = < | ||
| 55 | MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 | ||
| 56 | MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 61 | ecspi1 { | ||
| 62 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | ||
| 63 | fsl,pins = < | ||
| 64 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 65 | >; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | |||
| 48 | &uart4 { | 70 | &uart4 { |
| 49 | pinctrl-names = "default"; | 71 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&pinctrl_uart4_1>; | 72 | pinctrl-0 = <&pinctrl_uart4_1>; |
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 6e5dfdb32416..39eafc222a2e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |||
| @@ -27,6 +27,15 @@ | |||
| 27 | enable-active-high; | 27 | enable-active-high; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | reg_usb_h1_vbus: usb_h1_vbus { | ||
| 31 | compatible = "regulator-fixed"; | ||
| 32 | regulator-name = "usb_h1_vbus"; | ||
| 33 | regulator-min-microvolt = <5000000>; | ||
| 34 | regulator-max-microvolt = <5000000>; | ||
| 35 | gpio = <&gpio1 29 0>; | ||
| 36 | enable-active-high; | ||
| 37 | }; | ||
| 38 | |||
| 30 | reg_audio: wm8962_supply { | 39 | reg_audio: wm8962_supply { |
| 31 | compatible = "regulator-fixed"; | 40 | compatible = "regulator-fixed"; |
| 32 | regulator-name = "wm8962-supply"; | 41 | regulator-name = "wm8962-supply"; |
| @@ -41,12 +50,14 @@ | |||
| 41 | volume-up { | 50 | volume-up { |
| 42 | label = "Volume Up"; | 51 | label = "Volume Up"; |
| 43 | gpios = <&gpio1 4 0>; | 52 | gpios = <&gpio1 4 0>; |
| 53 | gpio-key,wakeup; | ||
| 44 | linux,code = <115>; /* KEY_VOLUMEUP */ | 54 | linux,code = <115>; /* KEY_VOLUMEUP */ |
| 45 | }; | 55 | }; |
| 46 | 56 | ||
| 47 | volume-down { | 57 | volume-down { |
| 48 | label = "Volume Down"; | 58 | label = "Volume Down"; |
| 49 | gpios = <&gpio1 5 0>; | 59 | gpios = <&gpio1 5 0>; |
| 60 | gpio-key,wakeup; | ||
| 50 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | 61 | linux,code = <114>; /* KEY_VOLUMEDOWN */ |
| 51 | }; | 62 | }; |
| 52 | }; | 63 | }; |
| @@ -77,6 +88,22 @@ | |||
| 77 | status = "okay"; | 88 | status = "okay"; |
| 78 | }; | 89 | }; |
| 79 | 90 | ||
| 91 | &ecspi1 { | ||
| 92 | fsl,spi-num-chipselects = <1>; | ||
| 93 | cs-gpios = <&gpio4 9 0>; | ||
| 94 | pinctrl-names = "default"; | ||
| 95 | pinctrl-0 = <&pinctrl_ecspi1_2>; | ||
| 96 | status = "okay"; | ||
| 97 | |||
| 98 | flash: m25p80@0 { | ||
| 99 | #address-cells = <1>; | ||
| 100 | #size-cells = <1>; | ||
| 101 | compatible = "st,m25p32"; | ||
| 102 | spi-max-frequency = <20000000>; | ||
| 103 | reg = <0>; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | |||
| 80 | &fec { | 107 | &fec { |
| 81 | pinctrl-names = "default"; | 108 | pinctrl-names = "default"; |
| 82 | pinctrl-0 = <&pinctrl_enet_1>; | 109 | pinctrl-0 = <&pinctrl_enet_1>; |
| @@ -93,7 +120,7 @@ | |||
| 93 | codec: wm8962@1a { | 120 | codec: wm8962@1a { |
| 94 | compatible = "wlf,wm8962"; | 121 | compatible = "wlf,wm8962"; |
| 95 | reg = <0x1a>; | 122 | reg = <0x1a>; |
| 96 | clocks = <&clks 169>; | 123 | clocks = <&clks 201>; |
| 97 | DCVDD-supply = <®_audio>; | 124 | DCVDD-supply = <®_audio>; |
| 98 | DBVDD-supply = <®_audio>; | 125 | DBVDD-supply = <®_audio>; |
| 99 | AVDD-supply = <®_audio>; | 126 | AVDD-supply = <®_audio>; |
| @@ -113,6 +140,68 @@ | |||
| 113 | }; | 140 | }; |
| 114 | }; | 141 | }; |
| 115 | 142 | ||
| 143 | &i2c3 { | ||
| 144 | clock-frequency = <100000>; | ||
| 145 | pinctrl-names = "default"; | ||
| 146 | pinctrl-0 = <&pinctrl_i2c3_2>; | ||
| 147 | status = "okay"; | ||
| 148 | |||
| 149 | egalax_ts@04 { | ||
| 150 | compatible = "eeti,egalax_ts"; | ||
| 151 | reg = <0x04>; | ||
| 152 | interrupt-parent = <&gpio6>; | ||
| 153 | interrupts = <7 2>; | ||
| 154 | wakeup-gpios = <&gpio6 7 0>; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | |||
| 158 | &iomuxc { | ||
| 159 | pinctrl-names = "default"; | ||
| 160 | pinctrl-0 = <&pinctrl_hog>; | ||
| 161 | |||
| 162 | hog { | ||
| 163 | pinctrl_hog: hoggrp { | ||
| 164 | fsl,pins = < | ||
| 165 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 | ||
| 166 | MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 | ||
| 167 | MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 | ||
| 168 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | ||
| 169 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | ||
| 170 | MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | ||
| 171 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 172 | MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 | ||
| 173 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | ||
| 174 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 | ||
| 175 | >; | ||
| 176 | }; | ||
| 177 | }; | ||
| 178 | }; | ||
| 179 | |||
| 180 | &ldb { | ||
| 181 | status = "okay"; | ||
| 182 | |||
| 183 | lvds-channel@1 { | ||
| 184 | fsl,data-mapping = "spwg"; | ||
| 185 | fsl,data-width = <18>; | ||
| 186 | status = "okay"; | ||
| 187 | |||
| 188 | display-timings { | ||
| 189 | native-mode = <&timing0>; | ||
| 190 | timing0: hsd100pxn1 { | ||
| 191 | clock-frequency = <65000000>; | ||
| 192 | hactive = <1024>; | ||
| 193 | vactive = <768>; | ||
| 194 | hback-porch = <220>; | ||
| 195 | hfront-porch = <40>; | ||
| 196 | vback-porch = <21>; | ||
| 197 | vfront-porch = <7>; | ||
| 198 | hsync-len = <60>; | ||
| 199 | vsync-len = <10>; | ||
| 200 | }; | ||
| 201 | }; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
| 116 | &ssi2 { | 205 | &ssi2 { |
| 117 | fsl,mode = "i2s-slave"; | 206 | fsl,mode = "i2s-slave"; |
| 118 | status = "okay"; | 207 | status = "okay"; |
| @@ -125,6 +214,7 @@ | |||
| 125 | }; | 214 | }; |
| 126 | 215 | ||
| 127 | &usbh1 { | 216 | &usbh1 { |
| 217 | vbus-supply = <®_usb_h1_vbus>; | ||
| 128 | status = "okay"; | 218 | status = "okay"; |
| 129 | }; | 219 | }; |
| 130 | 220 | ||
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi new file mode 100644 index 000000000000..a55113e65bcb --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | / { | ||
| 13 | regulators { | ||
| 14 | compatible = "simple-bus"; | ||
| 15 | |||
| 16 | reg_2p5v: 2p5v { | ||
| 17 | compatible = "regulator-fixed"; | ||
| 18 | regulator-name = "2P5V"; | ||
| 19 | regulator-min-microvolt = <2500000>; | ||
| 20 | regulator-max-microvolt = <2500000>; | ||
| 21 | regulator-always-on; | ||
| 22 | }; | ||
| 23 | |||
| 24 | reg_3p3v: 3p3v { | ||
| 25 | compatible = "regulator-fixed"; | ||
| 26 | regulator-name = "3P3V"; | ||
| 27 | regulator-min-microvolt = <3300000>; | ||
| 28 | regulator-max-microvolt = <3300000>; | ||
| 29 | regulator-always-on; | ||
| 30 | }; | ||
| 31 | }; | ||
| 32 | |||
| 33 | sound { | ||
| 34 | compatible = "fsl,imx6-wandboard-sgtl5000", | ||
| 35 | "fsl,imx-audio-sgtl5000"; | ||
| 36 | model = "imx6-wandboard-sgtl5000"; | ||
| 37 | ssi-controller = <&ssi1>; | ||
| 38 | audio-codec = <&codec>; | ||
| 39 | audio-routing = | ||
| 40 | "MIC_IN", "Mic Jack", | ||
| 41 | "Mic Jack", "Mic Bias", | ||
| 42 | "Headphone Jack", "HP_OUT"; | ||
| 43 | mux-int-port = <1>; | ||
| 44 | mux-ext-port = <3>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | &audmux { | ||
| 49 | pinctrl-names = "default"; | ||
| 50 | pinctrl-0 = <&pinctrl_audmux_2>; | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | &i2c2 { | ||
| 55 | clock-frequency = <100000>; | ||
| 56 | pinctrl-names = "default"; | ||
| 57 | pinctrl-0 = <&pinctrl_i2c2_2>; | ||
| 58 | status = "okay"; | ||
| 59 | |||
| 60 | codec: sgtl5000@0a { | ||
| 61 | compatible = "fsl,sgtl5000"; | ||
| 62 | reg = <0x0a>; | ||
| 63 | clocks = <&clks 201>; | ||
| 64 | VDDA-supply = <®_2p5v>; | ||
| 65 | VDDIO-supply = <®_3p3v>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | &iomuxc { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_hog>; | ||
| 72 | |||
| 73 | hog { | ||
| 74 | pinctrl_hog: hoggrp { | ||
| 75 | fsl,pins = < | ||
| 76 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 77 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 | ||
| 78 | MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 | ||
| 79 | MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */ | ||
| 80 | MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */ | ||
| 81 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ | ||
| 82 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ | ||
| 83 | MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ | ||
| 84 | >; | ||
| 85 | }; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | |||
| 89 | &fec { | ||
| 90 | pinctrl-names = "default"; | ||
| 91 | pinctrl-0 = <&pinctrl_enet_1>; | ||
| 92 | phy-mode = "rgmii"; | ||
| 93 | status = "okay"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &ssi1 { | ||
| 97 | fsl,mode = "i2s-slave"; | ||
| 98 | status = "okay"; | ||
| 99 | }; | ||
| 100 | |||
| 101 | &uart1 { | ||
| 102 | pinctrl-names = "default"; | ||
| 103 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 104 | status = "okay"; | ||
| 105 | }; | ||
| 106 | |||
| 107 | &uart3 { | ||
| 108 | pinctrl-names = "default"; | ||
| 109 | pinctrl-0 = <&pinctrl_uart3_2>; | ||
| 110 | fsl,uart-has-rtscts; | ||
| 111 | status = "okay"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | &usbh1 { | ||
| 115 | status = "okay"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | &usdhc1 { | ||
| 119 | pinctrl-names = "default"; | ||
| 120 | pinctrl-0 = <&pinctrl_usdhc1_2>; | ||
| 121 | cd-gpios = <&gpio1 2 0>; | ||
| 122 | status = "okay"; | ||
| 123 | }; | ||
| 124 | |||
| 125 | &usdhc2 { | ||
| 126 | pinctrl-names = "default"; | ||
| 127 | pinctrl-0 = <&pinctrl_usdhc2_2>; | ||
| 128 | non-removable; | ||
| 129 | status = "okay"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | &usdhc3 { | ||
| 133 | pinctrl-names = "default"; | ||
| 134 | pinctrl-0 = <&pinctrl_usdhc3_2>; | ||
| 135 | cd-gpios = <&gpio3 9 0>; | ||
| 136 | status = "okay"; | ||
| 137 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f21d259080fd..ccd55c2fdb67 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -14,11 +14,6 @@ | |||
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | aliases { | 16 | aliases { |
| 17 | serial0 = &uart1; | ||
| 18 | serial1 = &uart2; | ||
| 19 | serial2 = &uart3; | ||
| 20 | serial3 = &uart4; | ||
| 21 | serial4 = &uart5; | ||
| 22 | gpio0 = &gpio1; | 17 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | 18 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; | 19 | gpio2 = &gpio3; |
| @@ -26,6 +21,18 @@ | |||
| 26 | gpio4 = &gpio5; | 21 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; | 22 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; | 23 | gpio6 = &gpio7; |
| 24 | i2c0 = &i2c1; | ||
| 25 | i2c1 = &i2c2; | ||
| 26 | i2c2 = &i2c3; | ||
| 27 | serial0 = &uart1; | ||
| 28 | serial1 = &uart2; | ||
| 29 | serial2 = &uart3; | ||
| 30 | serial3 = &uart4; | ||
| 31 | serial4 = &uart5; | ||
| 32 | spi0 = &ecspi1; | ||
| 33 | spi1 = &ecspi2; | ||
| 34 | spi2 = &ecspi3; | ||
| 35 | spi3 = &ecspi4; | ||
| 29 | }; | 36 | }; |
| 30 | 37 | ||
| 31 | intc: interrupt-controller@00a01000 { | 38 | intc: interrupt-controller@00a01000 { |
| @@ -81,15 +88,14 @@ | |||
| 81 | #size-cells = <1>; | 88 | #size-cells = <1>; |
| 82 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | 89 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 83 | reg-names = "gpmi-nand", "bch"; | 90 | reg-names = "gpmi-nand", "bch"; |
| 84 | interrupts = <0 13 0x04>, <0 15 0x04>; | 91 | interrupts = <0 15 0x04>; |
| 85 | interrupt-names = "gpmi-dma", "bch"; | 92 | interrupt-names = "bch"; |
| 86 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, | 93 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 87 | <&clks 150>, <&clks 149>; | 94 | <&clks 150>, <&clks 149>; |
| 88 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | 95 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 89 | "gpmi_bch_apb", "per1_bch"; | 96 | "gpmi_bch_apb", "per1_bch"; |
| 90 | dmas = <&dma_apbh 0>; | 97 | dmas = <&dma_apbh 0>; |
| 91 | dma-names = "rx-tx"; | 98 | dma-names = "rx-tx"; |
| 92 | fsl,gpmi-dma-channel = <0>; | ||
| 93 | status = "disabled"; | 99 | status = "disabled"; |
| 94 | }; | 100 | }; |
| 95 | 101 | ||
| @@ -184,6 +190,8 @@ | |||
| 184 | interrupts = <0 26 0x04>; | 190 | interrupts = <0 26 0x04>; |
| 185 | clocks = <&clks 160>, <&clks 161>; | 191 | clocks = <&clks 160>, <&clks 161>; |
| 186 | clock-names = "ipg", "per"; | 192 | clock-names = "ipg", "per"; |
| 193 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | ||
| 194 | dma-names = "rx", "tx"; | ||
| 187 | status = "disabled"; | 195 | status = "disabled"; |
| 188 | }; | 196 | }; |
| 189 | 197 | ||
| @@ -197,6 +205,9 @@ | |||
| 197 | reg = <0x02028000 0x4000>; | 205 | reg = <0x02028000 0x4000>; |
| 198 | interrupts = <0 46 0x04>; | 206 | interrupts = <0 46 0x04>; |
| 199 | clocks = <&clks 178>; | 207 | clocks = <&clks 178>; |
| 208 | dmas = <&sdma 37 1 0>, | ||
| 209 | <&sdma 38 1 0>; | ||
| 210 | dma-names = "rx", "tx"; | ||
| 200 | fsl,fifo-depth = <15>; | 211 | fsl,fifo-depth = <15>; |
| 201 | fsl,ssi-dma-events = <38 37>; | 212 | fsl,ssi-dma-events = <38 37>; |
| 202 | status = "disabled"; | 213 | status = "disabled"; |
| @@ -207,6 +218,9 @@ | |||
| 207 | reg = <0x0202c000 0x4000>; | 218 | reg = <0x0202c000 0x4000>; |
| 208 | interrupts = <0 47 0x04>; | 219 | interrupts = <0 47 0x04>; |
| 209 | clocks = <&clks 179>; | 220 | clocks = <&clks 179>; |
| 221 | dmas = <&sdma 41 1 0>, | ||
| 222 | <&sdma 42 1 0>; | ||
| 223 | dma-names = "rx", "tx"; | ||
| 210 | fsl,fifo-depth = <15>; | 224 | fsl,fifo-depth = <15>; |
| 211 | fsl,ssi-dma-events = <42 41>; | 225 | fsl,ssi-dma-events = <42 41>; |
| 212 | status = "disabled"; | 226 | status = "disabled"; |
| @@ -217,6 +231,9 @@ | |||
| 217 | reg = <0x02030000 0x4000>; | 231 | reg = <0x02030000 0x4000>; |
| 218 | interrupts = <0 48 0x04>; | 232 | interrupts = <0 48 0x04>; |
| 219 | clocks = <&clks 180>; | 233 | clocks = <&clks 180>; |
| 234 | dmas = <&sdma 45 1 0>, | ||
| 235 | <&sdma 46 1 0>; | ||
| 236 | dma-names = "rx", "tx"; | ||
| 220 | fsl,fifo-depth = <15>; | 237 | fsl,fifo-depth = <15>; |
| 221 | fsl,ssi-dma-events = <46 45>; | 238 | fsl,ssi-dma-events = <46 45>; |
| 222 | status = "disabled"; | 239 | status = "disabled"; |
| @@ -278,17 +295,23 @@ | |||
| 278 | }; | 295 | }; |
| 279 | 296 | ||
| 280 | can1: flexcan@02090000 { | 297 | can1: flexcan@02090000 { |
| 298 | compatible = "fsl,imx6q-flexcan"; | ||
| 281 | reg = <0x02090000 0x4000>; | 299 | reg = <0x02090000 0x4000>; |
| 282 | interrupts = <0 110 0x04>; | 300 | interrupts = <0 110 0x04>; |
| 301 | clocks = <&clks 108>, <&clks 109>; | ||
| 302 | clock-names = "ipg", "per"; | ||
| 283 | }; | 303 | }; |
| 284 | 304 | ||
| 285 | can2: flexcan@02094000 { | 305 | can2: flexcan@02094000 { |
| 306 | compatible = "fsl,imx6q-flexcan"; | ||
| 286 | reg = <0x02094000 0x4000>; | 307 | reg = <0x02094000 0x4000>; |
| 287 | interrupts = <0 111 0x04>; | 308 | interrupts = <0 111 0x04>; |
| 309 | clocks = <&clks 110>, <&clks 111>; | ||
| 310 | clock-names = "ipg", "per"; | ||
| 288 | }; | 311 | }; |
| 289 | 312 | ||
| 290 | gpt: gpt@02098000 { | 313 | gpt: gpt@02098000 { |
| 291 | compatible = "fsl,imx6q-gpt"; | 314 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
| 292 | reg = <0x02098000 0x4000>; | 315 | reg = <0x02098000 0x4000>; |
| 293 | interrupts = <0 55 0x04>; | 316 | interrupts = <0 55 0x04>; |
| 294 | clocks = <&clks 119>, <&clks 120>; | 317 | clocks = <&clks 119>, <&clks 120>; |
| @@ -491,6 +514,13 @@ | |||
| 491 | }; | 514 | }; |
| 492 | }; | 515 | }; |
| 493 | 516 | ||
| 517 | tempmon: tempmon { | ||
| 518 | compatible = "fsl,imx6q-tempmon"; | ||
| 519 | interrupts = <0 49 0x04>; | ||
| 520 | fsl,tempmon = <&anatop>; | ||
| 521 | fsl,tempmon-data = <&ocotp>; | ||
| 522 | }; | ||
| 523 | |||
| 494 | usbphy1: usbphy@020c9000 { | 524 | usbphy1: usbphy@020c9000 { |
| 495 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | 525 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| 496 | reg = <0x020c9000 0x1000>; | 526 | reg = <0x020c9000 0x1000>; |
| @@ -546,6 +576,713 @@ | |||
| 546 | reg = <0x020e0000 0x38>; | 576 | reg = <0x020e0000 0x38>; |
| 547 | }; | 577 | }; |
| 548 | 578 | ||
| 579 | iomuxc: iomuxc@020e0000 { | ||
| 580 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | ||
| 581 | reg = <0x020e0000 0x4000>; | ||
| 582 | |||
| 583 | audmux { | ||
| 584 | pinctrl_audmux_1: audmux-1 { | ||
| 585 | fsl,pins = < | ||
| 586 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 | ||
| 587 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 | ||
| 588 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 | ||
| 589 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 | ||
| 590 | >; | ||
| 591 | }; | ||
| 592 | |||
| 593 | pinctrl_audmux_2: audmux-2 { | ||
| 594 | fsl,pins = < | ||
| 595 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 596 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 597 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 598 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 599 | >; | ||
| 600 | }; | ||
| 601 | |||
| 602 | pinctrl_audmux_3: audmux-3 { | ||
| 603 | fsl,pins = < | ||
| 604 | MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 | ||
| 605 | MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 | ||
| 606 | MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 | ||
| 607 | >; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 611 | ecspi1 { | ||
| 612 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 613 | fsl,pins = < | ||
| 614 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 615 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 616 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 617 | >; | ||
| 618 | }; | ||
| 619 | |||
| 620 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 621 | fsl,pins = < | ||
| 622 | MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 | ||
| 623 | MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 | ||
| 624 | MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 | ||
| 625 | >; | ||
| 626 | }; | ||
| 627 | }; | ||
| 628 | |||
| 629 | ecspi3 { | ||
| 630 | pinctrl_ecspi3_1: ecspi3grp-1 { | ||
| 631 | fsl,pins = < | ||
| 632 | MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 | ||
| 633 | MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 | ||
| 634 | MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 | ||
| 635 | >; | ||
| 636 | }; | ||
| 637 | }; | ||
| 638 | |||
| 639 | enet { | ||
| 640 | pinctrl_enet_1: enetgrp-1 { | ||
| 641 | fsl,pins = < | ||
| 642 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 643 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 644 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 645 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 646 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 647 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 648 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 649 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 650 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 651 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 652 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 653 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 654 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 655 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 656 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 657 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | ||
| 658 | >; | ||
| 659 | }; | ||
| 660 | |||
| 661 | pinctrl_enet_2: enetgrp-2 { | ||
| 662 | fsl,pins = < | ||
| 663 | MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 | ||
| 664 | MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 | ||
| 665 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 666 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 667 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 668 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 669 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 670 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 671 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 672 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 673 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 674 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 675 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 676 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 677 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 678 | >; | ||
| 679 | }; | ||
| 680 | |||
| 681 | pinctrl_enet_3: enetgrp-3 { | ||
| 682 | fsl,pins = < | ||
| 683 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 684 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 685 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 686 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 687 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 688 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 689 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 690 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 691 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 692 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 693 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 694 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 695 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 696 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 697 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 698 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 699 | >; | ||
| 700 | }; | ||
| 701 | }; | ||
| 702 | |||
| 703 | esai { | ||
| 704 | pinctrl_esai_1: esaigrp-1 { | ||
| 705 | fsl,pins = < | ||
| 706 | MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 | ||
| 707 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 708 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 709 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 710 | MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 | ||
| 711 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 712 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 713 | MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 | ||
| 714 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 715 | >; | ||
| 716 | }; | ||
| 717 | |||
| 718 | pinctrl_esai_2: esaigrp-2 { | ||
| 719 | fsl,pins = < | ||
| 720 | MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 | ||
| 721 | MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 | ||
| 722 | MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 | ||
| 723 | MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 | ||
| 724 | MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 | ||
| 725 | MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 | ||
| 726 | MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 | ||
| 727 | MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 | ||
| 728 | MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 | ||
| 729 | MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 | ||
| 730 | >; | ||
| 731 | }; | ||
| 732 | }; | ||
| 733 | |||
| 734 | flexcan1 { | ||
| 735 | pinctrl_flexcan1_1: flexcan1grp-1 { | ||
| 736 | fsl,pins = < | ||
| 737 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 738 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 | ||
| 739 | >; | ||
| 740 | }; | ||
| 741 | |||
| 742 | pinctrl_flexcan1_2: flexcan1grp-2 { | ||
| 743 | fsl,pins = < | ||
| 744 | MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 | ||
| 745 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 | ||
| 746 | >; | ||
| 747 | }; | ||
| 748 | }; | ||
| 749 | |||
| 750 | flexcan2 { | ||
| 751 | pinctrl_flexcan2_1: flexcan2grp-1 { | ||
| 752 | fsl,pins = < | ||
| 753 | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 | ||
| 754 | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 | ||
| 755 | >; | ||
| 756 | }; | ||
| 757 | }; | ||
| 758 | |||
| 759 | gpmi-nand { | ||
| 760 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 761 | fsl,pins = < | ||
| 762 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 763 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 764 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 765 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 766 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 767 | MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 768 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 769 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 770 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 771 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 772 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 773 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 774 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 775 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 776 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 777 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 778 | MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 779 | >; | ||
| 780 | }; | ||
| 781 | }; | ||
| 782 | |||
| 783 | hdmi_hdcp { | ||
| 784 | pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { | ||
| 785 | fsl,pins = < | ||
| 786 | MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 787 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 788 | >; | ||
| 789 | }; | ||
| 790 | |||
| 791 | pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { | ||
| 792 | fsl,pins = < | ||
| 793 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 794 | MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 795 | >; | ||
| 796 | }; | ||
| 797 | |||
| 798 | pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { | ||
| 799 | fsl,pins = < | ||
| 800 | MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 | ||
| 801 | MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 | ||
| 802 | >; | ||
| 803 | }; | ||
| 804 | }; | ||
| 805 | |||
| 806 | hdmi_cec { | ||
| 807 | pinctrl_hdmi_cec_1: hdmicecgrp-1 { | ||
| 808 | fsl,pins = < | ||
| 809 | MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 810 | >; | ||
| 811 | }; | ||
| 812 | |||
| 813 | pinctrl_hdmi_cec_2: hdmicecgrp-2 { | ||
| 814 | fsl,pins = < | ||
| 815 | MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | ||
| 816 | >; | ||
| 817 | }; | ||
| 818 | }; | ||
| 819 | |||
| 820 | i2c1 { | ||
| 821 | pinctrl_i2c1_1: i2c1grp-1 { | ||
| 822 | fsl,pins = < | ||
| 823 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | ||
| 824 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | ||
| 825 | >; | ||
| 826 | }; | ||
| 827 | |||
| 828 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 829 | fsl,pins = < | ||
| 830 | MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 831 | MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 832 | >; | ||
| 833 | }; | ||
| 834 | }; | ||
| 835 | |||
| 836 | i2c2 { | ||
| 837 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 838 | fsl,pins = < | ||
| 839 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 840 | MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 | ||
| 841 | >; | ||
| 842 | }; | ||
| 843 | |||
| 844 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 845 | fsl,pins = < | ||
| 846 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | ||
| 847 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 848 | >; | ||
| 849 | }; | ||
| 850 | |||
| 851 | pinctrl_i2c2_3: i2c2grp-3 { | ||
| 852 | fsl,pins = < | ||
| 853 | MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 | ||
| 854 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | ||
| 855 | >; | ||
| 856 | }; | ||
| 857 | }; | ||
| 858 | |||
| 859 | i2c3 { | ||
| 860 | pinctrl_i2c3_1: i2c3grp-1 { | ||
| 861 | fsl,pins = < | ||
| 862 | MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 | ||
| 863 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 864 | >; | ||
| 865 | }; | ||
| 866 | |||
| 867 | pinctrl_i2c3_2: i2c3grp-2 { | ||
| 868 | fsl,pins = < | ||
| 869 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 870 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | ||
| 871 | >; | ||
| 872 | }; | ||
| 873 | |||
| 874 | pinctrl_i2c3_3: i2c3grp-3 { | ||
| 875 | fsl,pins = < | ||
| 876 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | ||
| 877 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 | ||
| 878 | >; | ||
| 879 | }; | ||
| 880 | |||
| 881 | pinctrl_i2c3_4: i2c3grp-4 { | ||
| 882 | fsl,pins = < | ||
| 883 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | ||
| 884 | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | ||
| 885 | >; | ||
| 886 | }; | ||
| 887 | }; | ||
| 888 | |||
| 889 | ipu1 { | ||
| 890 | pinctrl_ipu1_1: ipu1grp-1 { | ||
| 891 | fsl,pins = < | ||
| 892 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 | ||
| 893 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 | ||
| 894 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 | ||
| 895 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 | ||
| 896 | MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 | ||
| 897 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 | ||
| 898 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 | ||
| 899 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 | ||
| 900 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 | ||
| 901 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 | ||
| 902 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 | ||
| 903 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 | ||
| 904 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 | ||
| 905 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 | ||
| 906 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 | ||
| 907 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 | ||
| 908 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 | ||
| 909 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 | ||
| 910 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 | ||
| 911 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 | ||
| 912 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 | ||
| 913 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 | ||
| 914 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 | ||
| 915 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 | ||
| 916 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 | ||
| 917 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 | ||
| 918 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 | ||
| 919 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 | ||
| 920 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 | ||
| 921 | >; | ||
| 922 | }; | ||
| 923 | |||
| 924 | pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ | ||
| 925 | fsl,pins = < | ||
| 926 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 927 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 928 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 929 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 930 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 931 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 932 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 933 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 934 | MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 | ||
| 935 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 936 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 937 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 938 | >; | ||
| 939 | }; | ||
| 940 | |||
| 941 | pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ | ||
| 942 | fsl,pins = < | ||
| 943 | MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 | ||
| 944 | MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 | ||
| 945 | MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 | ||
| 946 | MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 | ||
| 947 | MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 | ||
| 948 | MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 | ||
| 949 | MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 | ||
| 950 | MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 | ||
| 951 | MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 | ||
| 952 | MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 | ||
| 953 | MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 | ||
| 954 | MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 | ||
| 955 | MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 | ||
| 956 | MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 | ||
| 957 | MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 | ||
| 958 | MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 | ||
| 959 | MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 | ||
| 960 | MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 | ||
| 961 | MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 | ||
| 962 | >; | ||
| 963 | }; | ||
| 964 | }; | ||
| 965 | |||
| 966 | mlb { | ||
| 967 | pinctrl_mlb_1: mlbgrp-1 { | ||
| 968 | fsl,pins = < | ||
| 969 | MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 | ||
| 970 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 971 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 972 | >; | ||
| 973 | }; | ||
| 974 | |||
| 975 | pinctrl_mlb_2: mlbgrp-2 { | ||
| 976 | fsl,pins = < | ||
| 977 | MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 | ||
| 978 | MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 | ||
| 979 | MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 | ||
| 980 | >; | ||
| 981 | }; | ||
| 982 | }; | ||
| 983 | |||
| 984 | pwm0 { | ||
| 985 | pinctrl_pwm0_1: pwm0grp-1 { | ||
| 986 | fsl,pins = < | ||
| 987 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 | ||
| 988 | >; | ||
| 989 | }; | ||
| 990 | }; | ||
| 991 | |||
| 992 | pwm3 { | ||
| 993 | pinctrl_pwm3_1: pwm3grp-1 { | ||
| 994 | fsl,pins = < | ||
| 995 | MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 | ||
| 996 | >; | ||
| 997 | }; | ||
| 998 | }; | ||
| 999 | |||
| 1000 | spdif { | ||
| 1001 | pinctrl_spdif_1: spdifgrp-1 { | ||
| 1002 | fsl,pins = < | ||
| 1003 | MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 | ||
| 1004 | >; | ||
| 1005 | }; | ||
| 1006 | |||
| 1007 | pinctrl_spdif_2: spdifgrp-2 { | ||
| 1008 | fsl,pins = < | ||
| 1009 | MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 | ||
| 1010 | MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 | ||
| 1011 | >; | ||
| 1012 | }; | ||
| 1013 | }; | ||
| 1014 | |||
| 1015 | uart1 { | ||
| 1016 | pinctrl_uart1_1: uart1grp-1 { | ||
| 1017 | fsl,pins = < | ||
| 1018 | MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | ||
| 1019 | MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | ||
| 1020 | >; | ||
| 1021 | }; | ||
| 1022 | }; | ||
| 1023 | |||
| 1024 | uart2 { | ||
| 1025 | pinctrl_uart2_1: uart2grp-1 { | ||
| 1026 | fsl,pins = < | ||
| 1027 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | ||
| 1028 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | ||
| 1029 | >; | ||
| 1030 | }; | ||
| 1031 | |||
| 1032 | pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ | ||
| 1033 | fsl,pins = < | ||
| 1034 | MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 | ||
| 1035 | MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 | ||
| 1036 | MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 | ||
| 1037 | MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 | ||
| 1038 | >; | ||
| 1039 | }; | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | uart3 { | ||
| 1043 | pinctrl_uart3_1: uart3grp-1 { | ||
| 1044 | fsl,pins = < | ||
| 1045 | MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 | ||
| 1046 | MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 | ||
| 1047 | MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 | ||
| 1048 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1049 | >; | ||
| 1050 | }; | ||
| 1051 | |||
| 1052 | pinctrl_uart3_2: uart3grp-2 { | ||
| 1053 | fsl,pins = < | ||
| 1054 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | ||
| 1055 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | ||
| 1056 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | ||
| 1057 | MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | ||
| 1058 | >; | ||
| 1059 | }; | ||
| 1060 | }; | ||
| 1061 | |||
| 1062 | uart4 { | ||
| 1063 | pinctrl_uart4_1: uart4grp-1 { | ||
| 1064 | fsl,pins = < | ||
| 1065 | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | ||
| 1066 | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | ||
| 1067 | >; | ||
| 1068 | }; | ||
| 1069 | }; | ||
| 1070 | |||
| 1071 | usbotg { | ||
| 1072 | pinctrl_usbotg_1: usbotggrp-1 { | ||
| 1073 | fsl,pins = < | ||
| 1074 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | ||
| 1075 | >; | ||
| 1076 | }; | ||
| 1077 | |||
| 1078 | pinctrl_usbotg_2: usbotggrp-2 { | ||
| 1079 | fsl,pins = < | ||
| 1080 | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | ||
| 1081 | >; | ||
| 1082 | }; | ||
| 1083 | }; | ||
| 1084 | |||
| 1085 | usbh2 { | ||
| 1086 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 1087 | fsl,pins = < | ||
| 1088 | MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 | ||
| 1089 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 | ||
| 1090 | >; | ||
| 1091 | }; | ||
| 1092 | |||
| 1093 | pinctrl_usbh2_2: usbh2grp-2 { | ||
| 1094 | fsl,pins = < | ||
| 1095 | MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 | ||
| 1096 | >; | ||
| 1097 | }; | ||
| 1098 | }; | ||
| 1099 | |||
| 1100 | usbh3 { | ||
| 1101 | pinctrl_usbh3_1: usbh3grp-1 { | ||
| 1102 | fsl,pins = < | ||
| 1103 | MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 | ||
| 1104 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 | ||
| 1105 | >; | ||
| 1106 | }; | ||
| 1107 | |||
| 1108 | pinctrl_usbh3_2: usbh3grp-2 { | ||
| 1109 | fsl,pins = < | ||
| 1110 | MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 | ||
| 1111 | >; | ||
| 1112 | }; | ||
| 1113 | }; | ||
| 1114 | |||
| 1115 | usdhc1 { | ||
| 1116 | pinctrl_usdhc1_1: usdhc1grp-1 { | ||
| 1117 | fsl,pins = < | ||
| 1118 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 1119 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 1120 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 1121 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 1122 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 1123 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 1124 | MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 | ||
| 1125 | MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 | ||
| 1126 | MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 | ||
| 1127 | MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 | ||
| 1128 | >; | ||
| 1129 | }; | ||
| 1130 | |||
| 1131 | pinctrl_usdhc1_2: usdhc1grp-2 { | ||
| 1132 | fsl,pins = < | ||
| 1133 | MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 1134 | MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 1135 | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 1136 | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 1137 | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 1138 | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 1139 | >; | ||
| 1140 | }; | ||
| 1141 | }; | ||
| 1142 | |||
| 1143 | usdhc2 { | ||
| 1144 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 1145 | fsl,pins = < | ||
| 1146 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1147 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1148 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1149 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1150 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1151 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1152 | MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 | ||
| 1153 | MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 | ||
| 1154 | MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 | ||
| 1155 | MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 | ||
| 1156 | >; | ||
| 1157 | }; | ||
| 1158 | |||
| 1159 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 1160 | fsl,pins = < | ||
| 1161 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 1162 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 1163 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 1164 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 1165 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 1166 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 1167 | >; | ||
| 1168 | }; | ||
| 1169 | }; | ||
| 1170 | |||
| 1171 | usdhc3 { | ||
| 1172 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 1173 | fsl,pins = < | ||
| 1174 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1175 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1176 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1177 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1178 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1179 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1180 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 | ||
| 1181 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 | ||
| 1182 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 | ||
| 1183 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 | ||
| 1184 | >; | ||
| 1185 | }; | ||
| 1186 | |||
| 1187 | pinctrl_usdhc3_2: usdhc3grp-2 { | ||
| 1188 | fsl,pins = < | ||
| 1189 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 1190 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 1191 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 1192 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 1193 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 1194 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 1195 | >; | ||
| 1196 | }; | ||
| 1197 | }; | ||
| 1198 | |||
| 1199 | usdhc4 { | ||
| 1200 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
| 1201 | fsl,pins = < | ||
| 1202 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1203 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1204 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1205 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1206 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1207 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1208 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | ||
| 1209 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | ||
| 1210 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | ||
| 1211 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | ||
| 1212 | >; | ||
| 1213 | }; | ||
| 1214 | |||
| 1215 | pinctrl_usdhc4_2: usdhc4grp-2 { | ||
| 1216 | fsl,pins = < | ||
| 1217 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | ||
| 1218 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | ||
| 1219 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | ||
| 1220 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | ||
| 1221 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | ||
| 1222 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | ||
| 1223 | >; | ||
| 1224 | }; | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | weim { | ||
| 1228 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 1229 | fsl,pins = < | ||
| 1230 | MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 1231 | >; | ||
| 1232 | }; | ||
| 1233 | |||
| 1234 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 1235 | fsl,pins = < | ||
| 1236 | MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 1237 | MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 1238 | MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 1239 | /* data */ | ||
| 1240 | MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 1241 | MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 1242 | MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 1243 | MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 1244 | MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 1245 | MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 1246 | MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 1247 | MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 1248 | MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 1249 | MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 1250 | MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 1251 | MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 1252 | MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 1253 | MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 1254 | MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 1255 | MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 1256 | /* address */ | ||
| 1257 | MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 1258 | MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 1259 | MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 1260 | MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 1261 | MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 1262 | MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 1263 | MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 1264 | MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 1265 | MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 1266 | MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 1267 | MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 1268 | MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 1269 | MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 1270 | MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 1271 | MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 1272 | MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 1273 | MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 1274 | MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 1275 | MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 1276 | MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 1277 | MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 1278 | MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 1279 | MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 1280 | MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 1281 | >; | ||
| 1282 | }; | ||
| 1283 | }; | ||
| 1284 | }; | ||
| 1285 | |||
| 549 | ldb: ldb@020e0008 { | 1286 | ldb: ldb@020e0008 { |
| 550 | #address-cells = <1>; | 1287 | #address-cells = <1>; |
| 551 | #size-cells = <0>; | 1288 | #size-cells = <0>; |
| @@ -555,13 +1292,11 @@ | |||
| 555 | 1292 | ||
| 556 | lvds-channel@0 { | 1293 | lvds-channel@0 { |
| 557 | reg = <0>; | 1294 | reg = <0>; |
| 558 | crtcs = <&ipu1 0>; | ||
| 559 | status = "disabled"; | 1295 | status = "disabled"; |
| 560 | }; | 1296 | }; |
| 561 | 1297 | ||
| 562 | lvds-channel@1 { | 1298 | lvds-channel@1 { |
| 563 | reg = <1>; | 1299 | reg = <1>; |
| 564 | crtcs = <&ipu1 1>; | ||
| 565 | status = "disabled"; | 1300 | status = "disabled"; |
| 566 | }; | 1301 | }; |
| 567 | }; | 1302 | }; |
| @@ -582,6 +1317,7 @@ | |||
| 582 | interrupts = <0 2 0x04>; | 1317 | interrupts = <0 2 0x04>; |
| 583 | clocks = <&clks 155>, <&clks 155>; | 1318 | clocks = <&clks 155>, <&clks 155>; |
| 584 | clock-names = "ipg", "ahb"; | 1319 | clock-names = "ipg", "ahb"; |
| 1320 | #dma-cells = <3>; | ||
| 585 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | 1321 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| 586 | }; | 1322 | }; |
| 587 | }; | 1323 | }; |
| @@ -751,8 +1487,8 @@ | |||
| 751 | clocks = <&clks 196>; | 1487 | clocks = <&clks 196>; |
| 752 | }; | 1488 | }; |
| 753 | 1489 | ||
| 754 | ocotp@021bc000 { | 1490 | ocotp: ocotp@021bc000 { |
| 755 | compatible = "fsl,imx6q-ocotp"; | 1491 | compatible = "fsl,imx6q-ocotp", "syscon"; |
| 756 | reg = <0x021bc000 0x4000>; | 1492 | reg = <0x021bc000 0x4000>; |
| 757 | }; | 1493 | }; |
| 758 | 1494 | ||
| @@ -791,6 +1527,8 @@ | |||
| 791 | interrupts = <0 27 0x04>; | 1527 | interrupts = <0 27 0x04>; |
| 792 | clocks = <&clks 160>, <&clks 161>; | 1528 | clocks = <&clks 160>, <&clks 161>; |
| 793 | clock-names = "ipg", "per"; | 1529 | clock-names = "ipg", "per"; |
| 1530 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | ||
| 1531 | dma-names = "rx", "tx"; | ||
| 794 | status = "disabled"; | 1532 | status = "disabled"; |
| 795 | }; | 1533 | }; |
| 796 | 1534 | ||
| @@ -800,6 +1538,8 @@ | |||
| 800 | interrupts = <0 28 0x04>; | 1538 | interrupts = <0 28 0x04>; |
| 801 | clocks = <&clks 160>, <&clks 161>; | 1539 | clocks = <&clks 160>, <&clks 161>; |
| 802 | clock-names = "ipg", "per"; | 1540 | clock-names = "ipg", "per"; |
| 1541 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | ||
| 1542 | dma-names = "rx", "tx"; | ||
| 803 | status = "disabled"; | 1543 | status = "disabled"; |
| 804 | }; | 1544 | }; |
| 805 | 1545 | ||
| @@ -809,6 +1549,8 @@ | |||
| 809 | interrupts = <0 29 0x04>; | 1549 | interrupts = <0 29 0x04>; |
| 810 | clocks = <&clks 160>, <&clks 161>; | 1550 | clocks = <&clks 160>, <&clks 161>; |
| 811 | clock-names = "ipg", "per"; | 1551 | clock-names = "ipg", "per"; |
| 1552 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | ||
| 1553 | dma-names = "rx", "tx"; | ||
| 812 | status = "disabled"; | 1554 | status = "disabled"; |
| 813 | }; | 1555 | }; |
| 814 | 1556 | ||
| @@ -818,6 +1560,8 @@ | |||
| 818 | interrupts = <0 30 0x04>; | 1560 | interrupts = <0 30 0x04>; |
| 819 | clocks = <&clks 160>, <&clks 161>; | 1561 | clocks = <&clks 160>, <&clks 161>; |
| 820 | clock-names = "ipg", "per"; | 1562 | clock-names = "ipg", "per"; |
| 1563 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | ||
| 1564 | dma-names = "rx", "tx"; | ||
| 821 | status = "disabled"; | 1565 | status = "disabled"; |
| 822 | }; | 1566 | }; |
| 823 | }; | 1567 | }; |
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c5e5da02d7e3..c46651e4d966 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
| @@ -152,32 +152,41 @@ | |||
| 152 | }; | 152 | }; |
| 153 | 153 | ||
| 154 | uart5: serial@02018000 { | 154 | uart5: serial@02018000 { |
| 155 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 155 | compatible = "fsl,imx6sl-uart", |
| 156 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 156 | reg = <0x02018000 0x4000>; | 157 | reg = <0x02018000 0x4000>; |
| 157 | interrupts = <0 30 0x04>; | 158 | interrupts = <0 30 0x04>; |
| 158 | clocks = <&clks IMX6SL_CLK_UART>, | 159 | clocks = <&clks IMX6SL_CLK_UART>, |
| 159 | <&clks IMX6SL_CLK_UART_SERIAL>; | 160 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 160 | clock-names = "ipg", "per"; | 161 | clock-names = "ipg", "per"; |
| 162 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | ||
| 163 | dma-names = "rx", "tx"; | ||
| 161 | status = "disabled"; | 164 | status = "disabled"; |
| 162 | }; | 165 | }; |
| 163 | 166 | ||
| 164 | uart1: serial@02020000 { | 167 | uart1: serial@02020000 { |
| 165 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 168 | compatible = "fsl,imx6sl-uart", |
| 169 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 166 | reg = <0x02020000 0x4000>; | 170 | reg = <0x02020000 0x4000>; |
| 167 | interrupts = <0 26 0x04>; | 171 | interrupts = <0 26 0x04>; |
| 168 | clocks = <&clks IMX6SL_CLK_UART>, | 172 | clocks = <&clks IMX6SL_CLK_UART>, |
| 169 | <&clks IMX6SL_CLK_UART_SERIAL>; | 173 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 170 | clock-names = "ipg", "per"; | 174 | clock-names = "ipg", "per"; |
| 175 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | ||
| 176 | dma-names = "rx", "tx"; | ||
| 171 | status = "disabled"; | 177 | status = "disabled"; |
| 172 | }; | 178 | }; |
| 173 | 179 | ||
| 174 | uart2: serial@02024000 { | 180 | uart2: serial@02024000 { |
| 175 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 181 | compatible = "fsl,imx6sl-uart", |
| 182 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 176 | reg = <0x02024000 0x4000>; | 183 | reg = <0x02024000 0x4000>; |
| 177 | interrupts = <0 27 0x04>; | 184 | interrupts = <0 27 0x04>; |
| 178 | clocks = <&clks IMX6SL_CLK_UART>, | 185 | clocks = <&clks IMX6SL_CLK_UART>, |
| 179 | <&clks IMX6SL_CLK_UART_SERIAL>; | 186 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 180 | clock-names = "ipg", "per"; | 187 | clock-names = "ipg", "per"; |
| 188 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | ||
| 189 | dma-names = "rx", "tx"; | ||
| 181 | status = "disabled"; | 190 | status = "disabled"; |
| 182 | }; | 191 | }; |
| 183 | 192 | ||
| @@ -186,6 +195,9 @@ | |||
| 186 | reg = <0x02028000 0x4000>; | 195 | reg = <0x02028000 0x4000>; |
| 187 | interrupts = <0 46 0x04>; | 196 | interrupts = <0 46 0x04>; |
| 188 | clocks = <&clks IMX6SL_CLK_SSI1>; | 197 | clocks = <&clks IMX6SL_CLK_SSI1>; |
| 198 | dmas = <&sdma 37 1 0>, | ||
| 199 | <&sdma 38 1 0>; | ||
| 200 | dma-names = "rx", "tx"; | ||
| 189 | fsl,fifo-depth = <15>; | 201 | fsl,fifo-depth = <15>; |
| 190 | status = "disabled"; | 202 | status = "disabled"; |
| 191 | }; | 203 | }; |
| @@ -195,6 +207,9 @@ | |||
| 195 | reg = <0x0202c000 0x4000>; | 207 | reg = <0x0202c000 0x4000>; |
| 196 | interrupts = <0 47 0x04>; | 208 | interrupts = <0 47 0x04>; |
| 197 | clocks = <&clks IMX6SL_CLK_SSI2>; | 209 | clocks = <&clks IMX6SL_CLK_SSI2>; |
| 210 | dmas = <&sdma 41 1 0>, | ||
| 211 | <&sdma 42 1 0>; | ||
| 212 | dma-names = "rx", "tx"; | ||
| 198 | fsl,fifo-depth = <15>; | 213 | fsl,fifo-depth = <15>; |
| 199 | status = "disabled"; | 214 | status = "disabled"; |
| 200 | }; | 215 | }; |
| @@ -204,27 +219,36 @@ | |||
| 204 | reg = <0x02030000 0x4000>; | 219 | reg = <0x02030000 0x4000>; |
| 205 | interrupts = <0 48 0x04>; | 220 | interrupts = <0 48 0x04>; |
| 206 | clocks = <&clks IMX6SL_CLK_SSI3>; | 221 | clocks = <&clks IMX6SL_CLK_SSI3>; |
| 222 | dmas = <&sdma 45 1 0>, | ||
| 223 | <&sdma 46 1 0>; | ||
| 224 | dma-names = "rx", "tx"; | ||
| 207 | fsl,fifo-depth = <15>; | 225 | fsl,fifo-depth = <15>; |
| 208 | status = "disabled"; | 226 | status = "disabled"; |
| 209 | }; | 227 | }; |
| 210 | 228 | ||
| 211 | uart3: serial@02034000 { | 229 | uart3: serial@02034000 { |
| 212 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 230 | compatible = "fsl,imx6sl-uart", |
| 231 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 213 | reg = <0x02034000 0x4000>; | 232 | reg = <0x02034000 0x4000>; |
| 214 | interrupts = <0 28 0x04>; | 233 | interrupts = <0 28 0x04>; |
| 215 | clocks = <&clks IMX6SL_CLK_UART>, | 234 | clocks = <&clks IMX6SL_CLK_UART>, |
| 216 | <&clks IMX6SL_CLK_UART_SERIAL>; | 235 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 217 | clock-names = "ipg", "per"; | 236 | clock-names = "ipg", "per"; |
| 237 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | ||
| 238 | dma-names = "rx", "tx"; | ||
| 218 | status = "disabled"; | 239 | status = "disabled"; |
| 219 | }; | 240 | }; |
| 220 | 241 | ||
| 221 | uart4: serial@02038000 { | 242 | uart4: serial@02038000 { |
| 222 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 243 | compatible = "fsl,imx6sl-uart", |
| 244 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 223 | reg = <0x02038000 0x4000>; | 245 | reg = <0x02038000 0x4000>; |
| 224 | interrupts = <0 29 0x04>; | 246 | interrupts = <0 29 0x04>; |
| 225 | clocks = <&clks IMX6SL_CLK_UART>, | 247 | clocks = <&clks IMX6SL_CLK_UART>, |
| 226 | <&clks IMX6SL_CLK_UART_SERIAL>; | 248 | <&clks IMX6SL_CLK_UART_SERIAL>; |
| 227 | clock-names = "ipg", "per"; | 249 | clock-names = "ipg", "per"; |
| 250 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | ||
| 251 | dma-names = "rx", "tx"; | ||
| 228 | status = "disabled"; | 252 | status = "disabled"; |
| 229 | }; | 253 | }; |
| 230 | }; | 254 | }; |
| @@ -594,6 +618,7 @@ | |||
| 594 | clocks = <&clks IMX6SL_CLK_SDMA>, | 618 | clocks = <&clks IMX6SL_CLK_SDMA>, |
| 595 | <&clks IMX6SL_CLK_SDMA>; | 619 | <&clks IMX6SL_CLK_SDMA>; |
| 596 | clock-names = "ipg", "ahb"; | 620 | clock-names = "ipg", "ahb"; |
| 621 | #dma-cells = <3>; | ||
| 597 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; | 622 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; |
| 598 | }; | 623 | }; |
| 599 | 624 | ||
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 1e5bef0bead7..650ef30e1856 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi | |||
| @@ -1,4 +1,39 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | ||
| 3 | pcie-controller { | ||
| 4 | compatible = "marvell,kirkwood-pcie"; | ||
| 5 | status = "disabled"; | ||
| 6 | device_type = "pci"; | ||
| 7 | |||
| 8 | #address-cells = <3>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | |||
| 11 | bus-range = <0x00 0xff>; | ||
| 12 | |||
| 13 | ranges = | ||
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; | ||
| 17 | |||
| 18 | pcie@1,0 { | ||
| 19 | device_type = "pci"; | ||
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 21 | reg = <0x0800 0 0 0 0>; | ||
| 22 | #address-cells = <3>; | ||
| 23 | #size-cells = <2>; | ||
| 24 | #interrupt-cells = <1>; | ||
| 25 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 26 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 27 | interrupt-map-mask = <0 0 0 0>; | ||
| 28 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 29 | marvell,pcie-port = <0>; | ||
| 30 | marvell,pcie-lane = <0>; | ||
| 31 | clocks = <&gate_clk 2>; | ||
| 32 | status = "disabled"; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 2 | ocp@f1000000 { | 37 | ocp@f1000000 { |
| 3 | pinctrl: pinctrl@10000 { | 38 | pinctrl: pinctrl@10000 { |
| 4 | compatible = "marvell,88f6281-pinctrl"; | 39 | compatible = "marvell,88f6281-pinctrl"; |
| @@ -41,37 +76,6 @@ | |||
| 41 | }; | 76 | }; |
| 42 | }; | 77 | }; |
| 43 | 78 | ||
| 44 | pcie-controller { | ||
| 45 | compatible = "marvell,kirkwood-pcie"; | ||
| 46 | status = "disabled"; | ||
| 47 | device_type = "pci"; | ||
| 48 | |||
| 49 | #address-cells = <3>; | ||
| 50 | #size-cells = <2>; | ||
| 51 | |||
| 52 | bus-range = <0x00 0xff>; | ||
| 53 | |||
| 54 | ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 55 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 56 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 57 | |||
| 58 | pcie@1,0 { | ||
| 59 | device_type = "pci"; | ||
| 60 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 61 | reg = <0x0800 0 0 0 0>; | ||
| 62 | #address-cells = <3>; | ||
| 63 | #size-cells = <2>; | ||
| 64 | #interrupt-cells = <1>; | ||
| 65 | ranges; | ||
| 66 | interrupt-map-mask = <0 0 0 0>; | ||
| 67 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 68 | marvell,pcie-port = <0>; | ||
| 69 | marvell,pcie-lane = <0>; | ||
| 70 | clocks = <&gate_clk 2>; | ||
| 71 | status = "disabled"; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | rtc@10300 { | 79 | rtc@10300 { |
| 76 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | 80 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
| 77 | reg = <0x10300 0x20>; | 81 | reg = <0x10300 0x20>; |
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index a63a11137262..3933a331ddc2 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -1,4 +1,59 @@ | |||
| 1 | / { | 1 | / { |
| 2 | mbus { | ||
| 3 | pcie-controller { | ||
| 4 | compatible = "marvell,kirkwood-pcie"; | ||
| 5 | status = "disabled"; | ||
| 6 | device_type = "pci"; | ||
| 7 | |||
| 8 | #address-cells = <3>; | ||
| 9 | #size-cells = <2>; | ||
| 10 | |||
| 11 | bus-range = <0x00 0xff>; | ||
| 12 | |||
| 13 | ranges = | ||
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | ||
| 15 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | ||
| 16 | 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 | ||
| 17 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ | ||
| 18 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ | ||
| 19 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ | ||
| 20 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; | ||
| 21 | |||
| 22 | pcie@1,0 { | ||
| 23 | device_type = "pci"; | ||
| 24 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 25 | reg = <0x0800 0 0 0 0>; | ||
| 26 | #address-cells = <3>; | ||
| 27 | #size-cells = <2>; | ||
| 28 | #interrupt-cells = <1>; | ||
| 29 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||
| 30 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||
| 31 | interrupt-map-mask = <0 0 0 0>; | ||
| 32 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 33 | marvell,pcie-port = <0>; | ||
| 34 | marvell,pcie-lane = <0>; | ||
| 35 | clocks = <&gate_clk 2>; | ||
| 36 | status = "disabled"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | pcie@2,0 { | ||
| 40 | device_type = "pci"; | ||
| 41 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; | ||
| 42 | reg = <0x1000 0 0 0 0>; | ||
| 43 | #address-cells = <3>; | ||
| 44 | #size-cells = <2>; | ||
| 45 | #interrupt-cells = <1>; | ||
| 46 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||
| 47 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||
| 48 | interrupt-map-mask = <0 0 0 0>; | ||
| 49 | interrupt-map = <0 0 0 0 &intc 10>; | ||
| 50 | marvell,pcie-port = <1>; | ||
| 51 | marvell,pcie-lane = <0>; | ||
| 52 | clocks = <&gate_clk 18>; | ||
| 53 | status = "disabled"; | ||
| 54 | }; | ||
| 55 | }; | ||
| 56 | }; | ||
| 2 | ocp@f1000000 { | 57 | ocp@f1000000 { |
| 3 | 58 | ||
| 4 | pinctrl: pinctrl@10000 { | 59 | pinctrl: pinctrl@10000 { |
| @@ -94,52 +149,5 @@ | |||
| 94 | status = "disabled"; | 149 | status = "disabled"; |
| 95 | }; | 150 | }; |
| 96 | 151 | ||
| 97 | pcie-controller { | ||
| 98 | compatible = "marvell,kirkwood-pcie"; | ||
| 99 | status = "disabled"; | ||
| 100 | device_type = "pci"; | ||
| 101 | |||
| 102 | #address-cells = <3>; | ||
| 103 | #size-cells = <2>; | ||
| 104 | |||
| 105 | bus-range = <0x00 0xff>; | ||
| 106 | |||
| 107 | ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ | ||
| 108 | 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ | ||
| 109 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | ||
| 110 | 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ | ||
| 111 | |||
| 112 | pcie@1,0 { | ||
| 113 | device_type = "pci"; | ||
| 114 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; | ||
| 115 | reg = <0x0800 0 0 0 0>; | ||
| 116 | #address-cells = <3>; | ||
| 117 | #size-cells = <2>; | ||
| 118 | #interrupt-cells = <1>; | ||
| 119 | ranges; | ||
| 120 | interrupt-map-mask = <0 0 0 0>; | ||
| 121 | interrupt-map = <0 0 0 0 &intc 9>; | ||
| 122 | marvell,pcie-port = <0>; | ||
| 123 | marvell,pcie-lane = <0>; | ||
| 124 | clocks = <&gate_clk 2>; | ||
| 125 | status = "disabled"; | ||
| 126 | }; | ||
| 127 | |||
| 128 | pcie@2,0 { | ||
| 129 | device_type = "pci"; | ||
| 130 | assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; | ||
| 131 | reg = <0x1000 0 0 0 0>; | ||
| 132 | #address-cells = <3>; | ||
| 133 | #size-cells = <2>; | ||
| 134 | #interrupt-cells = <1>; | ||
| 135 | ranges; | ||
| 136 | interrupt-map-mask = <0 0 0 0>; | ||
| 137 | interrupt-map = <0 0 0 0 &intc 10>; | ||
| 138 | marvell,pcie-port = <1>; | ||
| 139 | marvell,pcie-lane = <0>; | ||
| 140 | clocks = <&gate_clk 18>; | ||
| 141 | status = "disabled"; | ||
| 142 | }; | ||
| 143 | }; | ||
| 144 | }; | 152 | }; |
| 145 | }; | 153 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 00c48d26de68..9bf139c5a34d 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "LaCie CloudBox"; | 7 | model = "LaCie CloudBox"; |
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index 9d777edd1f36..72c4b0a0366f 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts | |||
| @@ -11,14 +11,15 @@ | |||
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | 13 | ||
| 14 | /include/ "kirkwood-db.dtsi" | 14 | #include "kirkwood-db.dtsi" |
| 15 | /include/ "kirkwood-6281.dtsi" | 15 | #include "kirkwood-6281.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "Marvell DB-88F6281-BP Development Board"; | 18 | model = "Marvell DB-88F6281-BP Development Board"; |
| 19 | compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | 19 | compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; |
| 20 | 20 | ||
| 21 | ocp@f1000000 { | 21 | mbus { |
| 22 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 22 | pcie-controller { | 23 | pcie-controller { |
| 23 | status = "okay"; | 24 | status = "okay"; |
| 24 | 25 | ||
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index f4c852886d23..36c411d34926 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts | |||
| @@ -11,14 +11,15 @@ | |||
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | 13 | ||
| 14 | /include/ "kirkwood-db.dtsi" | 14 | #include "kirkwood-db.dtsi" |
| 15 | /include/ "kirkwood-6282.dtsi" | 15 | #include "kirkwood-6282.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "Marvell DB-88F6282-BP Development Board"; | 18 | model = "Marvell DB-88F6282-BP Development Board"; |
| 19 | compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; | 19 | compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; |
| 20 | 20 | ||
| 21 | ocp@f1000000 { | 21 | mbus { |
| 22 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 22 | pcie-controller { | 23 | pcie-controller { |
| 23 | status = "okay"; | 24 | status = "okay"; |
| 24 | 25 | ||
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index c87cfb816120..45c1bf74ac00 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | * and 6282 variants of the Marvell Kirkwood Development Board. | 12 | * and 6282 variants of the Marvell Kirkwood Development Board. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | /include/ "kirkwood.dtsi" | 15 | #include "kirkwood.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | memory { | 18 | memory { |
| @@ -77,13 +77,5 @@ | |||
| 77 | cd-gpios = <&gpio1 6 0>; | 77 | cd-gpios = <&gpio1 6 0>; |
| 78 | status = "okay"; | 78 | status = "okay"; |
| 79 | }; | 79 | }; |
| 80 | |||
| 81 | pcie-controller { | ||
| 82 | status = "okay"; | ||
| 83 | |||
| 84 | pcie@1,0 { | ||
| 85 | status = "okay"; | ||
| 86 | }; | ||
| 87 | }; | ||
| 88 | }; | 80 | }; |
| 89 | }; | 81 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index 14d4ceea3057..e112ca62d978 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-dnskw.dtsi" | 3 | #include "kirkwood-dnskw.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "D-Link DNS-320 NAS (Rev A1)"; | 6 | model = "D-Link DNS-320 NAS (Rev A1)"; |
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index 63872570e6ce..5119fb8a8eb6 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-dnskw.dtsi" | 3 | #include "kirkwood-dnskw.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "D-Link DNS-325 NAS (Rev A1)"; | 6 | model = "D-Link DNS-325 NAS (Rev A1)"; |
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 0afe1d07c803..2e04284846a0 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /include/ "kirkwood.dtsi" | 1 | #include "kirkwood.dtsi" |
| 2 | /include/ "kirkwood-6281.dtsi" | 2 | #include "kirkwood-6281.dtsi" |
| 3 | 3 | ||
| 4 | / { | 4 | / { |
| 5 | model = "D-Link DNS NASes (kirkwood-based)"; | 5 | model = "D-Link DNS NASes (kirkwood-based)"; |
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 7714742bb8d8..4387ae8e93fe 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Seagate FreeAgent Dockstar"; | 7 | model = "Seagate FreeAgent Dockstar"; |
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 36c7ba38d500..c62837837246 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Globalscale Technologies Dreamplug"; | 7 | model = "Globalscale Technologies Dreamplug"; |
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 31caa6405065..e57118039277 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Seagate GoFlex Net"; | 7 | model = "Seagate GoFlex Net"; |
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 1e642f39b154..2c5673adb4bd 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Globalscale Technologies Guruplug Server Plus"; | 7 | model = "Globalscale Technologies Guruplug Server Plus"; |
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 20c4b081f420..158161ff6826 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; | 7 | model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; |
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 441204e8abc6..8314118b6b8a 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Iomega Iconnect"; | 7 | model = "Iomega Iconnect"; |
| @@ -18,6 +18,17 @@ | |||
| 18 | linux,initrd-end = <0x4800000>; | 18 | linux,initrd-end = <0x4800000>; |
| 19 | }; | 19 | }; |
| 20 | 20 | ||
| 21 | mbus { | ||
| 22 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 23 | pcie-controller { | ||
| 24 | status = "okay"; | ||
| 25 | |||
| 26 | pcie@1,0 { | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 21 | ocp@f1000000 { | 32 | ocp@f1000000 { |
| 22 | pinctrl: pinctrl@10000 { | 33 | pinctrl: pinctrl@10000 { |
| 23 | pmx_button_reset: pmx-button-reset { | 34 | pmx_button_reset: pmx-button-reset { |
| @@ -101,14 +112,6 @@ | |||
| 101 | reg = <0x980000 0x1f400000>; | 112 | reg = <0x980000 0x1f400000>; |
| 102 | }; | 113 | }; |
| 103 | }; | 114 | }; |
| 104 | |||
| 105 | pcie-controller { | ||
| 106 | status = "okay"; | ||
| 107 | |||
| 108 | pcie@1,0 { | ||
| 109 | status = "okay"; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | }; | 115 | }; |
| 113 | 116 | ||
| 114 | gpio-leds { | 117 | gpio-leds { |
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 00a7bfe5e83b..fd7f053e9c96 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Iomega StorCenter ix2-200"; | 7 | model = "Iomega StorCenter ix2-200"; |
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index c3f036b86cca..bd88a236f729 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-ns2-common.dtsi" | 3 | #include "kirkwood-ns2-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "LaCie Internet Space v2"; | 6 | model = "LaCie Internet Space v2"; |
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5d9f5ea78700..b071d37cc291 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-98dx4122.dtsi" | 4 | #include "kirkwood-98dx4122.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Keymile Kirkwood Reference Design"; | 7 | model = "Keymile Kirkwood Reference Design"; |
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts index 9f55d95f35f5..e2fa368aef25 100644 --- a/arch/arm/boot/dts/kirkwood-lschlv2.dts +++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-lsxl.dtsi" | 3 | #include "kirkwood-lsxl.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Buffalo Linkstation LS-CHLv2"; | 6 | model = "Buffalo Linkstation LS-CHLv2"; |
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts index 5c84c118ed8d..8d89cdf8d6bf 100644 --- a/arch/arm/boot/dts/kirkwood-lsxhl.dts +++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-lsxl.dtsi" | 3 | #include "kirkwood-lsxl.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Buffalo Linkstation LS-XHL"; | 6 | model = "Buffalo Linkstation LS-XHL"; |
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 31b17f5b9d28..f7e247cc925a 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /include/ "kirkwood.dtsi" | 1 | #include "kirkwood.dtsi" |
| 2 | /include/ "kirkwood-6281.dtsi" | 2 | #include "kirkwood-6281.dtsi" |
| 3 | 3 | ||
| 4 | / { | 4 | / { |
| 5 | chosen { | 5 | chosen { |
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 6179333fd71f..21f1954c9e54 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "MPL CEC4"; | 7 | model = "MPL CEC4"; |
| @@ -16,6 +16,17 @@ | |||
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | mbus { | ||
| 20 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 21 | pcie-controller { | ||
| 22 | status = "okay"; | ||
| 23 | |||
| 24 | pcie@1,0 { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 19 | ocp@f1000000 { | 30 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 31 | pinctrl: pinctrl@10000 { |
| 21 | pmx_led_health: pmx-led-health { | 32 | pmx_led_health: pmx-led-health { |
| @@ -134,14 +145,6 @@ | |||
| 134 | cd-gpios = <&gpio1 15 1>; | 145 | cd-gpios = <&gpio1 15 1>; |
| 135 | /* No WP GPIO */ | 146 | /* No WP GPIO */ |
| 136 | }; | 147 | }; |
| 137 | |||
| 138 | pcie-controller { | ||
| 139 | status = "okay"; | ||
| 140 | |||
| 141 | pcie@1,0 { | ||
| 142 | status = "okay"; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | }; | 148 | }; |
| 146 | 149 | ||
| 147 | gpio-leds { | 150 | gpio-leds { |
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index ad6ade7d9191..cc40f19ae3fc 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6282.dtsi" | 4 | #include "kirkwood-6282.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "NETGEAR ReadyNAS Duo v2"; | 7 | model = "NETGEAR ReadyNAS Duo v2"; |
| @@ -16,6 +16,17 @@ | |||
| 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | 16 | bootargs = "console=ttyS0,115200n8 earlyprintk"; |
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | mbus { | ||
| 20 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 21 | pcie-controller { | ||
| 22 | status = "okay"; | ||
| 23 | |||
| 24 | pcie@1,0 { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 19 | ocp@f1000000 { | 30 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 31 | pinctrl: pinctrl@10000 { |
| 21 | pmx_button_power: pmx-button-power { | 32 | pmx_button_power: pmx-button-power { |
| @@ -52,6 +63,17 @@ | |||
| 52 | }; | 63 | }; |
| 53 | }; | 64 | }; |
| 54 | 65 | ||
| 66 | clocks { | ||
| 67 | #address-cells = <1>; | ||
| 68 | #size-cells = <0>; | ||
| 69 | |||
| 70 | g762_clk: fixedclk { | ||
| 71 | compatible = "fixed-clock"; | ||
| 72 | #clock-cells = <0>; | ||
| 73 | clock-frequency = <8192>; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | |||
| 55 | i2c@11000 { | 77 | i2c@11000 { |
| 56 | status = "okay"; | 78 | status = "okay"; |
| 57 | 79 | ||
| @@ -59,6 +81,15 @@ | |||
| 59 | compatible = "ricoh,rs5c372a"; | 81 | compatible = "ricoh,rs5c372a"; |
| 60 | reg = <0x32>; | 82 | reg = <0x32>; |
| 61 | }; | 83 | }; |
| 84 | |||
| 85 | g762: g762@3e { | ||
| 86 | compatible = "gmt,g762"; | ||
| 87 | reg = <0x3e>; | ||
| 88 | clocks = <&g762_clk>; /* input clock */ | ||
| 89 | fan_gear_mode = <0>; | ||
| 90 | fan_startv = <1>; | ||
| 91 | pwm_polarity = <0>; | ||
| 92 | }; | ||
| 62 | }; | 93 | }; |
| 63 | 94 | ||
| 64 | serial@12000 { | 95 | serial@12000 { |
| @@ -101,14 +132,6 @@ | |||
| 101 | status = "okay"; | 132 | status = "okay"; |
| 102 | nr-ports = <2>; | 133 | nr-ports = <2>; |
| 103 | }; | 134 | }; |
| 104 | |||
| 105 | pcie-controller { | ||
| 106 | status = "okay"; | ||
| 107 | |||
| 108 | pcie@1,0 { | ||
| 109 | status = "okay"; | ||
| 110 | }; | ||
| 111 | }; | ||
| 112 | }; | 135 | }; |
| 113 | 136 | ||
| 114 | gpio-leds { | 137 | gpio-leds { |
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 2afac0405816..d0fb34dc1667 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /include/ "kirkwood.dtsi" | 1 | #include "kirkwood.dtsi" |
| 2 | /include/ "kirkwood-6281.dtsi" | 2 | #include "kirkwood-6281.dtsi" |
| 3 | 3 | ||
| 4 | / { | 4 | / { |
| 5 | chosen { | 5 | chosen { |
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index b50e93d7796c..0599f3cb844e 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-ns2-common.dtsi" | 3 | #include "kirkwood-ns2-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "LaCie Network Space v2"; | 6 | model = "LaCie Network Space v2"; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index af8259fe8955..b0e17984aea0 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-ns2-common.dtsi" | 3 | #include "kirkwood-ns2-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "LaCie Network Space Lite v2"; | 6 | model = "LaCie Network Space Lite v2"; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index 85f24d227e17..d4f6a586d553 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-ns2-common.dtsi" | 3 | #include "kirkwood-ns2-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "LaCie Network Space Max v2"; | 6 | model = "LaCie Network Space Max v2"; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index 329e530bffe7..f30e05af6473 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood-ns2-common.dtsi" | 3 | #include "kirkwood-ns2-common.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | /* This machine is embedded in the first LaCie CloudBox product. */ | 6 | /* This machine is embedded in the first LaCie CloudBox product. */ |
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi new file mode 100644 index 000000000000..06267a91de38 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | #include "kirkwood.dtsi" | ||
| 2 | #include "kirkwood-6281.dtsi" | ||
| 3 | |||
| 4 | / { | ||
| 5 | model = "ZyXEL NSA310"; | ||
| 6 | |||
| 7 | ocp@f1000000 { | ||
| 8 | pinctrl: pinctrl@10000 { | ||
| 9 | |||
| 10 | pmx_usb_power_off: pmx-usb-power-off { | ||
| 11 | marvell,pins = "mpp21"; | ||
| 12 | marvell,function = "gpio"; | ||
| 13 | }; | ||
| 14 | pmx_pwr_off: pmx-pwr-off { | ||
| 15 | marvell,pins = "mpp48"; | ||
| 16 | marvell,function = "gpio"; | ||
| 17 | }; | ||
| 18 | |||
| 19 | }; | ||
| 20 | |||
| 21 | serial@12000 { | ||
| 22 | status = "ok"; | ||
| 23 | }; | ||
| 24 | |||
| 25 | sata@80000 { | ||
| 26 | status = "okay"; | ||
| 27 | nr-ports = <2>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | nand@3000000 { | ||
| 31 | status = "okay"; | ||
| 32 | chip-delay = <35>; | ||
| 33 | |||
| 34 | partition@0 { | ||
| 35 | label = "uboot"; | ||
| 36 | reg = <0x0000000 0x0100000>; | ||
| 37 | read-only; | ||
| 38 | }; | ||
| 39 | partition@100000 { | ||
| 40 | label = "uboot_env"; | ||
| 41 | reg = <0x0100000 0x0080000>; | ||
| 42 | }; | ||
| 43 | partition@180000 { | ||
| 44 | label = "key_store"; | ||
| 45 | reg = <0x0180000 0x0080000>; | ||
| 46 | }; | ||
| 47 | partition@200000 { | ||
| 48 | label = "info"; | ||
| 49 | reg = <0x0200000 0x0080000>; | ||
| 50 | }; | ||
| 51 | partition@280000 { | ||
| 52 | label = "etc"; | ||
| 53 | reg = <0x0280000 0x0a00000>; | ||
| 54 | }; | ||
| 55 | partition@c80000 { | ||
| 56 | label = "kernel_1"; | ||
| 57 | reg = <0x0c80000 0x0a00000>; | ||
| 58 | }; | ||
| 59 | partition@1680000 { | ||
| 60 | label = "rootfs1"; | ||
| 61 | reg = <0x1680000 0x2fc0000>; | ||
| 62 | }; | ||
| 63 | partition@4640000 { | ||
| 64 | label = "kernel_2"; | ||
| 65 | reg = <0x4640000 0x0a00000>; | ||
| 66 | }; | ||
| 67 | partition@5040000 { | ||
| 68 | label = "rootfs2"; | ||
| 69 | reg = <0x5040000 0x2fc0000>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | |||
| 73 | pcie-controller { | ||
| 74 | status = "okay"; | ||
| 75 | |||
| 76 | pcie@1,0 { | ||
| 77 | status = "okay"; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | gpio_poweroff { | ||
| 83 | compatible = "gpio-poweroff"; | ||
| 84 | pinctrl-0 = <&pmx_pwr_off>; | ||
| 85 | pinctrl-names = "default"; | ||
| 86 | gpios = <&gpio1 16 0>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | regulators { | ||
| 90 | compatible = "simple-bus"; | ||
| 91 | #address-cells = <1>; | ||
| 92 | #size-cells = <0>; | ||
| 93 | pinctrl-0 = <&pmx_usb_power_off>; | ||
| 94 | pinctrl-names = "default"; | ||
| 95 | |||
| 96 | usb0_power_off: regulator@1 { | ||
| 97 | compatible = "regulator-fixed"; | ||
| 98 | reg = <1>; | ||
| 99 | regulator-name = "USB Power Off"; | ||
| 100 | regulator-min-microvolt = <5000000>; | ||
| 101 | regulator-max-microvolt = <5000000>; | ||
| 102 | regulator-always-on; | ||
| 103 | regulator-boot-on; | ||
| 104 | gpio = <&gpio0 21 0>; | ||
| 105 | }; | ||
| 106 | }; | ||
| 107 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 69003598f5fa..7aeae0c2c1f4 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts | |||
| @@ -1,10 +1,8 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood-nsa310-common.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | ||
| 5 | 4 | ||
| 6 | / { | 5 | / { |
| 7 | model = "ZyXEL NSA310"; | ||
| 8 | compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | 6 | compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; |
| 9 | 7 | ||
| 10 | memory { | 8 | memory { |
| @@ -16,6 +14,17 @@ | |||
| 16 | bootargs = "console=ttyS0,115200"; | 14 | bootargs = "console=ttyS0,115200"; |
| 17 | }; | 15 | }; |
| 18 | 16 | ||
| 17 | mbus { | ||
| 18 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 19 | pcie-controller { | ||
| 20 | status = "okay"; | ||
| 21 | |||
| 22 | pcie@1,0 { | ||
| 23 | status = "okay"; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | |||
| 19 | ocp@f1000000 { | 28 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 29 | pinctrl: pinctrl@10000 { |
| 21 | pinctrl-0 = <&pmx_unknown>; | 30 | pinctrl-0 = <&pmx_unknown>; |
| @@ -41,11 +50,6 @@ | |||
| 41 | marvell,function = "gpio"; | 50 | marvell,function = "gpio"; |
| 42 | }; | 51 | }; |
| 43 | 52 | ||
| 44 | pmx_usb_power_off: pmx-usb-power-off { | ||
| 45 | marvell,pins = "mpp21"; | ||
| 46 | marvell,function = "gpio"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | pmx_led_sys_green: pmx-led-sys-green { | 53 | pmx_led_sys_green: pmx-led-sys-green { |
| 50 | marvell,pins = "mpp28"; | 54 | marvell,pins = "mpp28"; |
| 51 | marvell,function = "gpio"; | 55 | marvell,function = "gpio"; |
| @@ -95,20 +99,6 @@ | |||
| 95 | marvell,pins = "mpp46"; | 99 | marvell,pins = "mpp46"; |
| 96 | marvell,function = "gpio"; | 100 | marvell,function = "gpio"; |
| 97 | }; | 101 | }; |
| 98 | |||
| 99 | pmx_pwr_off: pmx-pwr-off { | ||
| 100 | marvell,pins = "mpp48"; | ||
| 101 | marvell,function = "gpio"; | ||
| 102 | }; | ||
| 103 | }; | ||
| 104 | |||
| 105 | serial@12000 { | ||
| 106 | status = "ok"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | sata@80000 { | ||
| 110 | status = "okay"; | ||
| 111 | nr-ports = <2>; | ||
| 112 | }; | 102 | }; |
| 113 | 103 | ||
| 114 | i2c@11000 { | 104 | i2c@11000 { |
| @@ -119,57 +109,6 @@ | |||
| 119 | reg = <0x2e>; | 109 | reg = <0x2e>; |
| 120 | }; | 110 | }; |
| 121 | }; | 111 | }; |
| 122 | |||
| 123 | nand@3000000 { | ||
| 124 | status = "okay"; | ||
| 125 | chip-delay = <35>; | ||
| 126 | |||
| 127 | partition@0 { | ||
| 128 | label = "uboot"; | ||
| 129 | reg = <0x0000000 0x0100000>; | ||
| 130 | read-only; | ||
| 131 | }; | ||
| 132 | partition@100000 { | ||
| 133 | label = "uboot_env"; | ||
| 134 | reg = <0x0100000 0x0080000>; | ||
| 135 | }; | ||
| 136 | partition@180000 { | ||
| 137 | label = "key_store"; | ||
| 138 | reg = <0x0180000 0x0080000>; | ||
| 139 | }; | ||
| 140 | partition@200000 { | ||
| 141 | label = "info"; | ||
| 142 | reg = <0x0200000 0x0080000>; | ||
| 143 | }; | ||
| 144 | partition@280000 { | ||
| 145 | label = "etc"; | ||
| 146 | reg = <0x0280000 0x0a00000>; | ||
| 147 | }; | ||
| 148 | partition@c80000 { | ||
| 149 | label = "kernel_1"; | ||
| 150 | reg = <0x0c80000 0x0a00000>; | ||
| 151 | }; | ||
| 152 | partition@1680000 { | ||
| 153 | label = "rootfs1"; | ||
| 154 | reg = <0x1680000 0x2fc0000>; | ||
| 155 | }; | ||
| 156 | partition@4640000 { | ||
| 157 | label = "kernel_2"; | ||
| 158 | reg = <0x4640000 0x0a00000>; | ||
| 159 | }; | ||
| 160 | partition@5040000 { | ||
| 161 | label = "rootfs2"; | ||
| 162 | reg = <0x5040000 0x2fc0000>; | ||
| 163 | }; | ||
| 164 | }; | ||
| 165 | |||
| 166 | pcie-controller { | ||
| 167 | status = "okay"; | ||
| 168 | |||
| 169 | pcie@1,0 { | ||
| 170 | status = "okay"; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | }; | 112 | }; |
| 174 | 113 | ||
| 175 | gpio_keys { | 114 | gpio_keys { |
| @@ -246,30 +185,4 @@ | |||
| 246 | gpios = <&gpio1 8 0>; | 185 | gpios = <&gpio1 8 0>; |
| 247 | }; | 186 | }; |
| 248 | }; | 187 | }; |
| 249 | |||
| 250 | gpio_poweroff { | ||
| 251 | compatible = "gpio-poweroff"; | ||
| 252 | pinctrl-0 = <&pmx_pwr_off>; | ||
| 253 | pinctrl-names = "default"; | ||
| 254 | gpios = <&gpio1 16 0>; | ||
| 255 | }; | ||
| 256 | |||
| 257 | regulators { | ||
| 258 | compatible = "simple-bus"; | ||
| 259 | #address-cells = <1>; | ||
| 260 | #size-cells = <0>; | ||
| 261 | pinctrl-0 = <&pmx_usb_power_off>; | ||
| 262 | pinctrl-names = "default"; | ||
| 263 | |||
| 264 | usb0_power_off: regulator@1 { | ||
| 265 | compatible = "regulator-fixed"; | ||
| 266 | reg = <1>; | ||
| 267 | regulator-name = "USB Power Off"; | ||
| 268 | regulator-min-microvolt = <5000000>; | ||
| 269 | regulator-max-microvolt = <5000000>; | ||
| 270 | regulator-always-on; | ||
| 271 | regulator-boot-on; | ||
| 272 | gpio = <&gpio0 21 0>; | ||
| 273 | }; | ||
| 274 | }; | ||
| 275 | }; | 188 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts new file mode 100644 index 000000000000..ab0212b0e6f5 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts | |||
| @@ -0,0 +1,165 @@ | |||
| 1 | /dts-v1/; | ||
| 2 | |||
| 3 | #include "kirkwood-nsa310-common.dtsi" | ||
| 4 | |||
| 5 | /* | ||
| 6 | * There are at least two different NSA310 designs. This variant does | ||
| 7 | * not have the red USB Led. | ||
| 8 | */ | ||
| 9 | |||
| 10 | / { | ||
| 11 | compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 12 | |||
| 13 | memory { | ||
| 14 | device_type = "memory"; | ||
| 15 | reg = <0x00000000 0x10000000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | chosen { | ||
| 19 | bootargs = "console=ttyS0,115200"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | ocp@f1000000 { | ||
| 23 | pinctrl: pinctrl@10000 { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | |||
| 26 | pmx_led_esata_green: pmx-led-esata-green { | ||
| 27 | marvell,pins = "mpp12"; | ||
| 28 | marvell,function = "gpio"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pmx_led_esata_red: pmx-led-esata-red { | ||
| 32 | marvell,pins = "mpp13"; | ||
| 33 | marvell,function = "gpio"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | pmx_led_usb_green: pmx-led-usb-green { | ||
| 37 | marvell,pins = "mpp15"; | ||
| 38 | marvell,function = "gpio"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | pmx_usb_power_off: pmx-usb-power-off { | ||
| 42 | marvell,pins = "mpp21"; | ||
| 43 | marvell,function = "gpio"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | pmx_led_sys_green: pmx-led-sys-green { | ||
| 47 | marvell,pins = "mpp28"; | ||
| 48 | marvell,function = "gpio"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | pmx_led_sys_red: pmx-led-sys-red { | ||
| 52 | marvell,pins = "mpp29"; | ||
| 53 | marvell,function = "gpio"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | pmx_btn_reset: pmx-btn-reset { | ||
| 57 | marvell,pins = "mpp36"; | ||
| 58 | marvell,function = "gpio"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | pmx_btn_copy: pmx-btn-copy { | ||
| 62 | marvell,pins = "mpp37"; | ||
| 63 | marvell,function = "gpio"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | pmx_led_copy_green: pmx-led-copy-green { | ||
| 67 | marvell,pins = "mpp39"; | ||
| 68 | marvell,function = "gpio"; | ||
| 69 | }; | ||
| 70 | |||
| 71 | pmx_led_copy_red: pmx-led-copy-red { | ||
| 72 | marvell,pins = "mpp40"; | ||
| 73 | marvell,function = "gpio"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | pmx_led_hdd_green: pmx-led-hdd-green { | ||
| 77 | marvell,pins = "mpp41"; | ||
| 78 | marvell,function = "gpio"; | ||
| 79 | }; | ||
| 80 | |||
| 81 | pmx_led_hdd_red: pmx-led-hdd-red { | ||
| 82 | marvell,pins = "mpp42"; | ||
| 83 | marvell,function = "gpio"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | pmx_btn_power: pmx-btn-power { | ||
| 87 | marvell,pins = "mpp46"; | ||
| 88 | marvell,function = "gpio"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | }; | ||
| 92 | |||
| 93 | i2c@11000 { | ||
| 94 | status = "okay"; | ||
| 95 | |||
| 96 | lm85: lm85@2e { | ||
| 97 | compatible = "lm85"; | ||
| 98 | reg = <0x2e>; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | gpio_keys { | ||
| 104 | compatible = "gpio-keys"; | ||
| 105 | #address-cells = <1>; | ||
| 106 | #size-cells = <0>; | ||
| 107 | |||
| 108 | button@1 { | ||
| 109 | label = "Power Button"; | ||
| 110 | linux,code = <116>; | ||
| 111 | gpios = <&gpio1 14 0>; | ||
| 112 | }; | ||
| 113 | button@2 { | ||
| 114 | label = "Copy Button"; | ||
| 115 | linux,code = <133>; | ||
| 116 | gpios = <&gpio1 5 1>; | ||
| 117 | }; | ||
| 118 | button@3 { | ||
| 119 | label = "Reset Button"; | ||
| 120 | linux,code = <0x198>; | ||
| 121 | gpios = <&gpio1 4 1>; | ||
| 122 | }; | ||
| 123 | }; | ||
| 124 | |||
| 125 | gpio-leds { | ||
| 126 | compatible = "gpio-leds"; | ||
| 127 | |||
| 128 | green-sys { | ||
| 129 | label = "nsa310:green:sys"; | ||
| 130 | gpios = <&gpio0 28 0>; | ||
| 131 | }; | ||
| 132 | red-sys { | ||
| 133 | label = "nsa310:red:sys"; | ||
| 134 | gpios = <&gpio0 29 0>; | ||
| 135 | }; | ||
| 136 | green-hdd { | ||
| 137 | label = "nsa310:green:hdd"; | ||
| 138 | gpios = <&gpio1 9 0>; | ||
| 139 | }; | ||
| 140 | red-hdd { | ||
| 141 | label = "nsa310:red:hdd"; | ||
| 142 | gpios = <&gpio1 10 0>; | ||
| 143 | }; | ||
| 144 | green-esata { | ||
| 145 | label = "nsa310:green:esata"; | ||
| 146 | gpios = <&gpio0 12 0>; | ||
| 147 | }; | ||
| 148 | red-esata { | ||
| 149 | label = "nsa310:red:esata"; | ||
| 150 | gpios = <&gpio0 13 0>; | ||
| 151 | }; | ||
| 152 | green-usb { | ||
| 153 | label = "nsa310:green:usb"; | ||
| 154 | gpios = <&gpio0 15 0>; | ||
| 155 | }; | ||
| 156 | green-copy { | ||
| 157 | label = "nsa310:green:copy"; | ||
| 158 | gpios = <&gpio1 7 0>; | ||
| 159 | }; | ||
| 160 | red-copy { | ||
| 161 | label = "nsa310:red:copy"; | ||
| 162 | gpios = <&gpio1 8 0>; | ||
| 163 | }; | ||
| 164 | }; | ||
| 165 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 38dc8517d777..365b792b23a7 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6282.dtsi" | 4 | #include "kirkwood-6282.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Plat'Home OpenBlocksA6"; | 7 | model = "Plat'Home OpenBlocksA6"; |
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index f7143f128504..0cc5f26bbbb6 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | |||
| @@ -6,8 +6,8 @@ | |||
| 6 | * Licensed under GPLv2 | 6 | * Licensed under GPLv2 |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /include/ "kirkwood.dtsi" | 9 | #include "kirkwood.dtsi" |
| 10 | /include/ "kirkwood-6281.dtsi" | 10 | #include "kirkwood-6281.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | memory { | 13 | memory { |
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts index f620ce48de97..eac6a21f3b1f 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | 8 | ||
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | 10 | ||
| 11 | /include/ "kirkwood-sheevaplug-common.dtsi" | 11 | #include "kirkwood-sheevaplug-common.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Globalscale Technologies eSATA SheevaPlug"; | 14 | model = "Globalscale Technologies eSATA SheevaPlug"; |
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index bf1dff251432..bb61918313db 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | 8 | ||
| 9 | /dts-v1/; | 9 | /dts-v1/; |
| 10 | 10 | ||
| 11 | /include/ "kirkwood-sheevaplug-common.dtsi" | 11 | #include "kirkwood-sheevaplug-common.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "Globalscale Technologies SheevaPlug"; | 14 | model = "Globalscale Technologies SheevaPlug"; |
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index f2052d7bc10f..974f1e0f09b2 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6282.dtsi" | 4 | #include "kirkwood-6282.dtsi" |
| 5 | 5 | ||
| 6 | / { | 6 | / { |
| 7 | model = "Univeral Scientific Industrial Co. Topkick-1281P2"; | 7 | model = "Univeral Scientific Industrial Co. Topkick-1281P2"; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 6dd1038e4de4..3867ae3030be 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | 4 | #include "kirkwood-6281.dtsi" |
| 5 | /include/ "kirkwood-ts219.dtsi" | 5 | #include "kirkwood-ts219.dtsi" |
| 6 | 6 | ||
| 7 | / { | 7 | / { |
| 8 | ocp@f1000000 { | 8 | ocp@f1000000 { |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 6fdc5ffcaae5..04f6fe106bb5 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts | |||
| @@ -1,10 +1,21 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | #include "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6282.dtsi" | 4 | #include "kirkwood-6282.dtsi" |
| 5 | /include/ "kirkwood-ts219.dtsi" | 5 | #include "kirkwood-ts219.dtsi" |
| 6 | 6 | ||
| 7 | / { | 7 | / { |
| 8 | mbus { | ||
| 9 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; | ||
| 10 | pcie-controller { | ||
| 11 | status = "okay"; | ||
| 12 | |||
| 13 | pcie@2,0 { | ||
| 14 | status = "okay"; | ||
| 15 | }; | ||
| 16 | }; | ||
| 17 | }; | ||
| 18 | |||
| 8 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 9 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 10 | 21 | ||
| @@ -30,14 +41,6 @@ | |||
| 30 | marvell,function = "gpio"; | 41 | marvell,function = "gpio"; |
| 31 | }; | 42 | }; |
| 32 | }; | 43 | }; |
| 33 | pcie-controller { | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | pcie@2,0 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | }; | 44 | }; |
| 42 | 45 | ||
| 43 | gpio_keys { | 46 | gpio_keys { |
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 0c9a94cd666c..7019cf675df2 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi | |||
| @@ -11,6 +11,16 @@ | |||
| 11 | bootargs = "console=ttyS0,115200n8"; | 11 | bootargs = "console=ttyS0,115200n8"; |
| 12 | }; | 12 | }; |
| 13 | 13 | ||
| 14 | mbus { | ||
| 15 | pcie-controller { | ||
| 16 | status = "okay"; | ||
| 17 | |||
| 18 | pcie@1,0 { | ||
| 19 | status = "okay"; | ||
| 20 | }; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 14 | ocp@f1000000 { | 24 | ocp@f1000000 { |
| 15 | i2c@11000 { | 25 | i2c@11000 { |
| 16 | status = "okay"; | 26 | status = "okay"; |
| @@ -87,12 +97,5 @@ | |||
| 87 | status = "okay"; | 97 | status = "okay"; |
| 88 | nr-ports = <2>; | 98 | nr-ports = <2>; |
| 89 | }; | 99 | }; |
| 90 | pcie-controller { | ||
| 91 | status = "okay"; | ||
| 92 | |||
| 93 | pcie@1,0 { | ||
| 94 | status = "okay"; | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | }; | 100 | }; |
| 98 | }; | 101 | }; |
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 9809fc1f105c..70f414d9bd9a 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | /include/ "skeleton.dtsi" | 1 | /include/ "skeleton.dtsi" |
| 2 | 2 | ||
| 3 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | ||
| 4 | |||
| 3 | / { | 5 | / { |
| 4 | compatible = "marvell,kirkwood"; | 6 | compatible = "marvell,kirkwood"; |
| 5 | interrupt-parent = <&intc>; | 7 | interrupt-parent = <&intc>; |
| @@ -28,15 +30,28 @@ | |||
| 28 | <0xf1020214 0x04>; | 30 | <0xf1020214 0x04>; |
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 33 | mbus { | ||
| 34 | compatible = "marvell,kirkwood-mbus", "simple-bus"; | ||
| 35 | #address-cells = <2>; | ||
| 36 | #size-cells = <1>; | ||
| 37 | controller = <&mbusc>; | ||
| 38 | pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ | ||
| 39 | pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ | ||
| 40 | }; | ||
| 41 | |||
| 31 | ocp@f1000000 { | 42 | ocp@f1000000 { |
| 32 | compatible = "simple-bus"; | 43 | compatible = "simple-bus"; |
| 33 | ranges = <0x00000000 0xf1000000 0x0100000 | 44 | ranges = <0x00000000 0xf1000000 0x0100000 |
| 34 | 0xe0000000 0xe0000000 0x8100000 /* PCIE */ | ||
| 35 | 0xf4000000 0xf4000000 0x0000400 | 45 | 0xf4000000 0xf4000000 0x0000400 |
| 36 | 0xf5000000 0xf5000000 0x0000400>; | 46 | 0xf5000000 0xf5000000 0x0000400>; |
| 37 | #address-cells = <1>; | 47 | #address-cells = <1>; |
| 38 | #size-cells = <1>; | 48 | #size-cells = <1>; |
| 39 | 49 | ||
| 50 | mbusc: mbus-controller@20000 { | ||
| 51 | compatible = "marvell,mbus-controller"; | ||
| 52 | reg = <0x20000 0x80>, <0x1500 0x20>; | ||
| 53 | }; | ||
| 54 | |||
| 40 | core_clk: core-clocks@10030 { | 55 | core_clk: core-clocks@10030 { |
| 41 | compatible = "marvell,kirkwood-core-clock"; | 56 | compatible = "marvell,kirkwood-core-clock"; |
| 42 | reg = <0x10030 0x4>; | 57 | reg = <0x10030 0x4>; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index d2803be4e1a8..759b0cd20013 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |||
| @@ -125,6 +125,12 @@ | |||
| 125 | clock-names = "apb_pclk"; | 125 | clock-names = "apb_pclk"; |
| 126 | }; | 126 | }; |
| 127 | 127 | ||
| 128 | scc@7fff0000 { | ||
| 129 | compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; | ||
| 130 | reg = <0 0x7fff0000 0 0x1000>; | ||
| 131 | interrupts = <0 95 4>; | ||
| 132 | }; | ||
| 133 | |||
| 128 | timer { | 134 | timer { |
| 129 | compatible = "arm,armv7-timer"; | 135 | compatible = "arm,armv7-timer"; |
| 130 | interrupts = <1 13 0xf08>, | 136 | interrupts = <1 13 0xf08>, |
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index b3905f5bcaf9..1a58678b93fa 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts | |||
| @@ -50,6 +50,13 @@ | |||
| 50 | status = "okay"; | 50 | status = "okay"; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | &i2c0 { | ||
| 54 | clock-frequency = <100000>; | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&pinctrl_i2c0_1>; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 53 | &uart1 { | 60 | &uart1 { |
| 54 | pinctrl-names = "default"; | 61 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&pinctrl_uart1_1>; | 62 | pinctrl-0 = <&pinctrl_uart1_1>; |
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index f07a847b00c9..e958ebe79779 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_SWAP is not set | 1 | # CONFIG_SWAP is not set |
| 3 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_POSIX_MQUEUE=y | 3 | CONFIG_POSIX_MQUEUE=y |
| @@ -17,16 +16,18 @@ CONFIG_MODULE_UNLOAD=y | |||
| 17 | # CONFIG_BLK_DEV_BSG is not set | 16 | # CONFIG_BLK_DEV_BSG is not set |
| 18 | # CONFIG_IOSCHED_DEADLINE is not set | 17 | # CONFIG_IOSCHED_DEADLINE is not set |
| 19 | # CONFIG_IOSCHED_CFQ is not set | 18 | # CONFIG_IOSCHED_CFQ is not set |
| 20 | CONFIG_ARCH_MXC=y | ||
| 21 | CONFIG_ARCH_MULTI_V4T=y | 19 | CONFIG_ARCH_MULTI_V4T=y |
| 22 | CONFIG_ARCH_MULTI_V5=y | 20 | CONFIG_ARCH_MULTI_V5=y |
| 23 | # CONFIG_ARCH_MULTI_V7 is not set | 21 | # CONFIG_ARCH_MULTI_V7 is not set |
| 22 | CONFIG_ARCH_MXC=y | ||
| 23 | CONFIG_MXC_IRQ_PRIOR=y | ||
| 24 | CONFIG_ARCH_MX1ADS=y | 24 | CONFIG_ARCH_MX1ADS=y |
| 25 | CONFIG_MACH_SCB9328=y | 25 | CONFIG_MACH_SCB9328=y |
| 26 | CONFIG_MACH_APF9328=y | 26 | CONFIG_MACH_APF9328=y |
| 27 | CONFIG_MACH_MX21ADS=y | 27 | CONFIG_MACH_MX21ADS=y |
| 28 | CONFIG_MACH_MX25_3DS=y | 28 | CONFIG_MACH_MX25_3DS=y |
| 29 | CONFIG_MACH_EUKREA_CPUIMX25SD=y | 29 | CONFIG_MACH_EUKREA_CPUIMX25SD=y |
| 30 | CONFIG_MACH_IMX25_DT=y | ||
| 30 | CONFIG_MACH_MX27ADS=y | 31 | CONFIG_MACH_MX27ADS=y |
| 31 | CONFIG_MACH_PCM038=y | 32 | CONFIG_MACH_PCM038=y |
| 32 | CONFIG_MACH_CPUIMX27=y | 33 | CONFIG_MACH_CPUIMX27=y |
| @@ -39,8 +40,6 @@ CONFIG_MACH_PCA100=y | |||
| 39 | CONFIG_MACH_MXT_TD60=y | 40 | CONFIG_MACH_MXT_TD60=y |
| 40 | CONFIG_MACH_IMX27IPCAM=y | 41 | CONFIG_MACH_IMX27IPCAM=y |
| 41 | CONFIG_MACH_IMX27_DT=y | 42 | CONFIG_MACH_IMX27_DT=y |
| 42 | CONFIG_MXC_IRQ_PRIOR=y | ||
| 43 | CONFIG_MXC_PWM=y | ||
| 44 | CONFIG_PREEMPT=y | 43 | CONFIG_PREEMPT=y |
| 45 | CONFIG_AEABI=y | 44 | CONFIG_AEABI=y |
| 46 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 45 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| @@ -67,7 +66,6 @@ CONFIG_DEVTMPFS=y | |||
| 67 | CONFIG_DEVTMPFS_MOUNT=y | 66 | CONFIG_DEVTMPFS_MOUNT=y |
| 68 | CONFIG_MTD=y | 67 | CONFIG_MTD=y |
| 69 | CONFIG_MTD_CMDLINE_PARTS=y | 68 | CONFIG_MTD_CMDLINE_PARTS=y |
| 70 | CONFIG_MTD_CHAR=y | ||
| 71 | CONFIG_MTD_BLOCK=y | 69 | CONFIG_MTD_BLOCK=y |
| 72 | CONFIG_MTD_CFI=y | 70 | CONFIG_MTD_CFI=y |
| 73 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 71 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| @@ -123,24 +121,20 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y | |||
| 123 | CONFIG_REGULATOR_MC13783=y | 121 | CONFIG_REGULATOR_MC13783=y |
| 124 | CONFIG_REGULATOR_MC13892=y | 122 | CONFIG_REGULATOR_MC13892=y |
| 125 | CONFIG_MEDIA_SUPPORT=y | 123 | CONFIG_MEDIA_SUPPORT=y |
| 126 | CONFIG_VIDEO_DEV=y | ||
| 127 | CONFIG_V4L_PLATFORM_DRIVERS=y | ||
| 128 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 124 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 125 | CONFIG_V4L_PLATFORM_DRIVERS=y | ||
| 129 | CONFIG_SOC_CAMERA=y | 126 | CONFIG_SOC_CAMERA=y |
| 130 | CONFIG_SOC_CAMERA_OV2640=y | ||
| 131 | CONFIG_VIDEO_MX2=y | 127 | CONFIG_VIDEO_MX2=y |
| 132 | CONFIG_V4L_MEM2MEM_DRIVERS=y | 128 | CONFIG_V4L_MEM2MEM_DRIVERS=y |
| 133 | CONFIG_VIDEO_CODA=y | 129 | CONFIG_VIDEO_CODA=y |
| 130 | CONFIG_SOC_CAMERA_OV2640=y | ||
| 134 | CONFIG_FB=y | 131 | CONFIG_FB=y |
| 135 | CONFIG_FB_IMX=y | 132 | CONFIG_FB_IMX=y |
| 136 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 133 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 137 | CONFIG_LCD_CLASS_DEVICE=y | 134 | CONFIG_LCD_CLASS_DEVICE=y |
| 138 | CONFIG_LCD_L4F00242T03=y | 135 | CONFIG_LCD_L4F00242T03=y |
| 139 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 136 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 140 | CONFIG_BACKLIGHT_PWM=y | ||
| 141 | CONFIG_FRAMEBUFFER_CONSOLE=y | 137 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 142 | CONFIG_FONTS=y | ||
| 143 | CONFIG_FONT_8x8=y | ||
| 144 | CONFIG_LOGO=y | 138 | CONFIG_LOGO=y |
| 145 | CONFIG_SOUND=y | 139 | CONFIG_SOUND=y |
| 146 | CONFIG_SND=y | 140 | CONFIG_SND=y |
| @@ -157,7 +151,6 @@ CONFIG_USB_HID=m | |||
| 157 | CONFIG_USB=y | 151 | CONFIG_USB=y |
| 158 | CONFIG_USB_EHCI_HCD=y | 152 | CONFIG_USB_EHCI_HCD=y |
| 159 | CONFIG_USB_EHCI_MXC=y | 153 | CONFIG_USB_EHCI_MXC=y |
| 160 | CONFIG_USB_ULPI=y | ||
| 161 | CONFIG_MMC=y | 154 | CONFIG_MMC=y |
| 162 | CONFIG_MMC_SDHCI=y | 155 | CONFIG_MMC_SDHCI=y |
| 163 | CONFIG_MMC_SDHCI_PLTFM=y | 156 | CONFIG_MMC_SDHCI_PLTFM=y |
| @@ -198,3 +191,5 @@ CONFIG_NLS_CODEPAGE_850=m | |||
| 198 | CONFIG_NLS_ISO8859_1=y | 191 | CONFIG_NLS_ISO8859_1=y |
| 199 | CONFIG_NLS_ISO8859_15=m | 192 | CONFIG_NLS_ISO8859_15=m |
| 200 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 193 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 194 | CONFIG_FONTS=y | ||
| 195 | CONFIG_FONT_8x8=y | ||
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 06686e7303a9..5d488c24b132 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | CONFIG_KERNEL_LZO=y | 2 | CONFIG_KERNEL_LZO=y |
| 4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| @@ -17,10 +16,8 @@ CONFIG_MODULE_UNLOAD=y | |||
| 17 | CONFIG_MODVERSIONS=y | 16 | CONFIG_MODVERSIONS=y |
| 18 | CONFIG_MODULE_SRCVERSION_ALL=y | 17 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 19 | # CONFIG_BLK_DEV_BSG is not set | 18 | # CONFIG_BLK_DEV_BSG is not set |
| 20 | CONFIG_ARCH_MXC=y | ||
| 21 | CONFIG_ARCH_MULTI_V6=y | 19 | CONFIG_ARCH_MULTI_V6=y |
| 22 | CONFIG_ARCH_MULTI_V7=y | 20 | CONFIG_ARCH_MXC=y |
| 23 | CONFIG_MACH_IMX31_DT=y | ||
| 24 | CONFIG_MACH_MX31LILLY=y | 21 | CONFIG_MACH_MX31LILLY=y |
| 25 | CONFIG_MACH_MX31LITE=y | 22 | CONFIG_MACH_MX31LITE=y |
| 26 | CONFIG_MACH_PCM037=y | 23 | CONFIG_MACH_PCM037=y |
| @@ -30,6 +27,7 @@ CONFIG_MACH_MX31MOBOARD=y | |||
| 30 | CONFIG_MACH_QONG=y | 27 | CONFIG_MACH_QONG=y |
| 31 | CONFIG_MACH_ARMADILLO5X0=y | 28 | CONFIG_MACH_ARMADILLO5X0=y |
| 32 | CONFIG_MACH_KZM_ARM11_01=y | 29 | CONFIG_MACH_KZM_ARM11_01=y |
| 30 | CONFIG_MACH_IMX31_DT=y | ||
| 33 | CONFIG_MACH_PCM043=y | 31 | CONFIG_MACH_PCM043=y |
| 34 | CONFIG_MACH_MX35_3DS=y | 32 | CONFIG_MACH_MX35_3DS=y |
| 35 | CONFIG_MACH_VPR200=y | 33 | CONFIG_MACH_VPR200=y |
| @@ -39,7 +37,6 @@ CONFIG_SOC_IMX53=y | |||
| 39 | CONFIG_SOC_IMX6Q=y | 37 | CONFIG_SOC_IMX6Q=y |
| 40 | CONFIG_SOC_IMX6SL=y | 38 | CONFIG_SOC_IMX6SL=y |
| 41 | CONFIG_SOC_VF610=y | 39 | CONFIG_SOC_VF610=y |
| 42 | CONFIG_MXC_PWM=y | ||
| 43 | CONFIG_SMP=y | 40 | CONFIG_SMP=y |
| 44 | CONFIG_VMSPLIT_2G=y | 41 | CONFIG_VMSPLIT_2G=y |
| 45 | CONFIG_PREEMPT_VOLUNTARY=y | 42 | CONFIG_PREEMPT_VOLUNTARY=y |
| @@ -64,20 +61,24 @@ CONFIG_IP_PNP_DHCP=y | |||
| 64 | # CONFIG_INET_LRO is not set | 61 | # CONFIG_INET_LRO is not set |
| 65 | CONFIG_IPV6=y | 62 | CONFIG_IPV6=y |
| 66 | CONFIG_NETFILTER=y | 63 | CONFIG_NETFILTER=y |
| 67 | # CONFIG_WIRELESS is not set | 64 | CONFIG_CFG80211=y |
| 65 | CONFIG_MAC80211=y | ||
| 66 | CONFIG_RFKILL=y | ||
| 67 | CONFIG_RFKILL_INPUT=y | ||
| 68 | CONFIG_DEVTMPFS=y | 68 | CONFIG_DEVTMPFS=y |
| 69 | CONFIG_DEVTMPFS_MOUNT=y | 69 | CONFIG_DEVTMPFS_MOUNT=y |
| 70 | # CONFIG_STANDALONE is not set | 70 | # CONFIG_STANDALONE is not set |
| 71 | CONFIG_IMX_WEIM=y | ||
| 71 | CONFIG_CONNECTOR=y | 72 | CONFIG_CONNECTOR=y |
| 72 | CONFIG_MTD=y | 73 | CONFIG_MTD=y |
| 73 | CONFIG_MTD_CMDLINE_PARTS=y | 74 | CONFIG_MTD_CMDLINE_PARTS=y |
| 74 | CONFIG_MTD_CHAR=y | ||
| 75 | CONFIG_MTD_BLOCK=y | 75 | CONFIG_MTD_BLOCK=y |
| 76 | CONFIG_MTD_CFI=y | 76 | CONFIG_MTD_CFI=y |
| 77 | CONFIG_MTD_JEDECPROBE=y | 77 | CONFIG_MTD_JEDECPROBE=y |
| 78 | CONFIG_MTD_CFI_INTELEXT=y | 78 | CONFIG_MTD_CFI_INTELEXT=y |
| 79 | CONFIG_MTD_CFI_AMDSTD=y | 79 | CONFIG_MTD_CFI_AMDSTD=y |
| 80 | CONFIG_MTD_CFI_STAA=y | 80 | CONFIG_MTD_CFI_STAA=y |
| 81 | CONFIG_MTD_PHYSMAP_OF=y | ||
| 81 | CONFIG_MTD_DATAFLASH=y | 82 | CONFIG_MTD_DATAFLASH=y |
| 82 | CONFIG_MTD_M25P80=y | 83 | CONFIG_MTD_M25P80=y |
| 83 | CONFIG_MTD_SST25L=y | 84 | CONFIG_MTD_SST25L=y |
| @@ -88,6 +89,7 @@ CONFIG_MTD_UBI=y | |||
| 88 | CONFIG_BLK_DEV_LOOP=y | 89 | CONFIG_BLK_DEV_LOOP=y |
| 89 | CONFIG_BLK_DEV_RAM=y | 90 | CONFIG_BLK_DEV_RAM=y |
| 90 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 91 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 92 | CONFIG_SRAM=y | ||
| 91 | CONFIG_EEPROM_AT24=y | 93 | CONFIG_EEPROM_AT24=y |
| 92 | CONFIG_EEPROM_AT25=y | 94 | CONFIG_EEPROM_AT25=y |
| 93 | # CONFIG_SCSI_PROC_FS is not set | 95 | # CONFIG_SCSI_PROC_FS is not set |
| @@ -98,10 +100,11 @@ CONFIG_SCSI_LOGGING=y | |||
| 98 | CONFIG_SCSI_SCAN_ASYNC=y | 100 | CONFIG_SCSI_SCAN_ASYNC=y |
| 99 | # CONFIG_SCSI_LOWLEVEL is not set | 101 | # CONFIG_SCSI_LOWLEVEL is not set |
| 100 | CONFIG_ATA=y | 102 | CONFIG_ATA=y |
| 103 | CONFIG_SATA_AHCI_PLATFORM=y | ||
| 104 | CONFIG_AHCI_IMX=y | ||
| 101 | CONFIG_PATA_IMX=y | 105 | CONFIG_PATA_IMX=y |
| 102 | CONFIG_NETDEVICES=y | 106 | CONFIG_NETDEVICES=y |
| 103 | # CONFIG_NET_VENDOR_BROADCOM is not set | 107 | # CONFIG_NET_VENDOR_BROADCOM is not set |
| 104 | # CONFIG_NET_VENDOR_CHELSIO is not set | ||
| 105 | CONFIG_CS89x0=y | 108 | CONFIG_CS89x0=y |
| 106 | CONFIG_CS89x0_PLATFORM=y | 109 | CONFIG_CS89x0_PLATFORM=y |
| 107 | # CONFIG_NET_VENDOR_FARADAY is not set | 110 | # CONFIG_NET_VENDOR_FARADAY is not set |
| @@ -115,7 +118,7 @@ CONFIG_SMC91X=y | |||
| 115 | CONFIG_SMC911X=y | 118 | CONFIG_SMC911X=y |
| 116 | CONFIG_SMSC911X=y | 119 | CONFIG_SMSC911X=y |
| 117 | # CONFIG_NET_VENDOR_STMICRO is not set | 120 | # CONFIG_NET_VENDOR_STMICRO is not set |
| 118 | # CONFIG_WLAN is not set | 121 | CONFIG_BRCMFMAC=m |
| 119 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 122 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 120 | CONFIG_INPUT_EVDEV=y | 123 | CONFIG_INPUT_EVDEV=y |
| 121 | CONFIG_INPUT_EVBUG=m | 124 | CONFIG_INPUT_EVBUG=m |
| @@ -124,6 +127,7 @@ CONFIG_KEYBOARD_IMX=y | |||
| 124 | CONFIG_MOUSE_PS2=m | 127 | CONFIG_MOUSE_PS2=m |
| 125 | CONFIG_MOUSE_PS2_ELANTECH=y | 128 | CONFIG_MOUSE_PS2_ELANTECH=y |
| 126 | CONFIG_INPUT_TOUCHSCREEN=y | 129 | CONFIG_INPUT_TOUCHSCREEN=y |
| 130 | CONFIG_TOUCHSCREEN_EGALAX=y | ||
| 127 | CONFIG_TOUCHSCREEN_MC13783=y | 131 | CONFIG_TOUCHSCREEN_MC13783=y |
| 128 | CONFIG_INPUT_MISC=y | 132 | CONFIG_INPUT_MISC=y |
| 129 | CONFIG_INPUT_MMA8450=y | 133 | CONFIG_INPUT_MMA8450=y |
| @@ -133,13 +137,13 @@ CONFIG_VT_HW_CONSOLE_BINDING=y | |||
| 133 | # CONFIG_DEVKMEM is not set | 137 | # CONFIG_DEVKMEM is not set |
| 134 | CONFIG_SERIAL_IMX=y | 138 | CONFIG_SERIAL_IMX=y |
| 135 | CONFIG_SERIAL_IMX_CONSOLE=y | 139 | CONFIG_SERIAL_IMX_CONSOLE=y |
| 140 | CONFIG_SERIAL_FSL_LPUART=y | ||
| 141 | CONFIG_SERIAL_FSL_LPUART_CONSOLE=y | ||
| 136 | CONFIG_HW_RANDOM=y | 142 | CONFIG_HW_RANDOM=y |
| 137 | CONFIG_HW_RANDOM_MXC_RNGA=y | 143 | CONFIG_HW_RANDOM_MXC_RNGA=y |
| 138 | CONFIG_I2C=y | ||
| 139 | # CONFIG_I2C_COMPAT is not set | 144 | # CONFIG_I2C_COMPAT is not set |
| 140 | CONFIG_I2C_CHARDEV=y | 145 | CONFIG_I2C_CHARDEV=y |
| 141 | # CONFIG_I2C_HELPER_AUTO is not set | 146 | # CONFIG_I2C_HELPER_AUTO is not set |
| 142 | CONFIG_I2C_ALGOBIT=m | ||
| 143 | CONFIG_I2C_ALGOPCF=m | 147 | CONFIG_I2C_ALGOPCF=m |
| 144 | CONFIG_I2C_ALGOPCA=m | 148 | CONFIG_I2C_ALGOPCA=m |
| 145 | CONFIG_I2C_IMX=y | 149 | CONFIG_I2C_IMX=y |
| @@ -155,30 +159,26 @@ CONFIG_MFD_MC13XXX_SPI=y | |||
| 155 | CONFIG_MFD_MC13XXX_I2C=y | 159 | CONFIG_MFD_MC13XXX_I2C=y |
| 156 | CONFIG_REGULATOR=y | 160 | CONFIG_REGULATOR=y |
| 157 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | 161 | CONFIG_REGULATOR_FIXED_VOLTAGE=y |
| 158 | CONFIG_REGULATOR_DA9052=y | ||
| 159 | CONFIG_REGULATOR_ANATOP=y | 162 | CONFIG_REGULATOR_ANATOP=y |
| 163 | CONFIG_REGULATOR_DA9052=y | ||
| 160 | CONFIG_REGULATOR_MC13783=y | 164 | CONFIG_REGULATOR_MC13783=y |
| 161 | CONFIG_REGULATOR_MC13892=y | 165 | CONFIG_REGULATOR_MC13892=y |
| 162 | CONFIG_MEDIA_SUPPORT=y | 166 | CONFIG_MEDIA_SUPPORT=y |
| 163 | CONFIG_VIDEO_DEV=y | ||
| 164 | CONFIG_V4L_PLATFORM_DRIVERS=y | ||
| 165 | CONFIG_MEDIA_CAMERA_SUPPORT=y | 167 | CONFIG_MEDIA_CAMERA_SUPPORT=y |
| 168 | CONFIG_V4L_PLATFORM_DRIVERS=y | ||
| 166 | CONFIG_SOC_CAMERA=y | 169 | CONFIG_SOC_CAMERA=y |
| 170 | CONFIG_VIDEO_MX3=y | ||
| 171 | CONFIG_V4L_MEM2MEM_DRIVERS=y | ||
| 172 | CONFIG_VIDEO_CODA=y | ||
| 167 | CONFIG_SOC_CAMERA_OV2640=y | 173 | CONFIG_SOC_CAMERA_OV2640=y |
| 168 | CONFIG_DRM=y | 174 | CONFIG_DRM=y |
| 169 | CONFIG_VIDEO_MX3=y | ||
| 170 | CONFIG_FB=y | ||
| 171 | CONFIG_LCD_PLATFORM=y | ||
| 172 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 175 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 173 | CONFIG_LCD_CLASS_DEVICE=y | 176 | CONFIG_LCD_CLASS_DEVICE=y |
| 174 | CONFIG_LCD_L4F00242T03=y | 177 | CONFIG_LCD_L4F00242T03=y |
| 178 | CONFIG_LCD_PLATFORM=y | ||
| 175 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 179 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 176 | CONFIG_BACKLIGHT_PWM=y | 180 | CONFIG_BACKLIGHT_PWM=y |
| 177 | CONFIG_FRAMEBUFFER_CONSOLE=y | 181 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 178 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 179 | CONFIG_FONTS=y | ||
| 180 | CONFIG_FONT_8x8=y | ||
| 181 | CONFIG_FONT_8x16=y | ||
| 182 | CONFIG_LOGO=y | 182 | CONFIG_LOGO=y |
| 183 | CONFIG_SOUND=y | 183 | CONFIG_SOUND=y |
| 184 | CONFIG_SND=y | 184 | CONFIG_SND=y |
| @@ -192,11 +192,12 @@ CONFIG_SND_SOC_IMX_MC13783=y | |||
| 192 | CONFIG_USB=y | 192 | CONFIG_USB=y |
| 193 | CONFIG_USB_EHCI_HCD=y | 193 | CONFIG_USB_EHCI_HCD=y |
| 194 | CONFIG_USB_EHCI_MXC=y | 194 | CONFIG_USB_EHCI_MXC=y |
| 195 | CONFIG_USB_STORAGE=y | ||
| 195 | CONFIG_USB_CHIPIDEA=y | 196 | CONFIG_USB_CHIPIDEA=y |
| 196 | CONFIG_USB_CHIPIDEA_HOST=y | 197 | CONFIG_USB_CHIPIDEA_HOST=y |
| 197 | CONFIG_USB_PHY=y | 198 | CONFIG_USB_PHY=y |
| 199 | CONFIG_NOP_USB_XCEIV=y | ||
| 198 | CONFIG_USB_MXS_PHY=y | 200 | CONFIG_USB_MXS_PHY=y |
| 199 | CONFIG_USB_STORAGE=y | ||
| 200 | CONFIG_MMC=y | 201 | CONFIG_MMC=y |
| 201 | CONFIG_MMC_SDHCI=y | 202 | CONFIG_MMC_SDHCI=y |
| 202 | CONFIG_MMC_SDHCI_PLTFM=y | 203 | CONFIG_MMC_SDHCI_PLTFM=y |
| @@ -213,9 +214,10 @@ CONFIG_IMX_SDMA=y | |||
| 213 | CONFIG_MXS_DMA=y | 214 | CONFIG_MXS_DMA=y |
| 214 | CONFIG_STAGING=y | 215 | CONFIG_STAGING=y |
| 215 | CONFIG_DRM_IMX=y | 216 | CONFIG_DRM_IMX=y |
| 216 | CONFIG_DRM_IMX_TVE=y | ||
| 217 | CONFIG_DRM_IMX_FB_HELPER=y | 217 | CONFIG_DRM_IMX_FB_HELPER=y |
| 218 | CONFIG_DRM_IMX_PARALLEL_DISPLAY=y | 218 | CONFIG_DRM_IMX_PARALLEL_DISPLAY=y |
| 219 | CONFIG_DRM_IMX_TVE=y | ||
| 220 | CONFIG_DRM_IMX_LDB=y | ||
| 219 | CONFIG_DRM_IMX_IPUV3_CORE=y | 221 | CONFIG_DRM_IMX_IPUV3_CORE=y |
| 220 | CONFIG_DRM_IMX_IPUV3=y | 222 | CONFIG_DRM_IMX_IPUV3=y |
| 221 | CONFIG_COMMON_CLK_DEBUG=y | 223 | CONFIG_COMMON_CLK_DEBUG=y |
| @@ -269,3 +271,6 @@ CONFIG_CRC_CCITT=m | |||
| 269 | CONFIG_CRC_T10DIF=y | 271 | CONFIG_CRC_T10DIF=y |
| 270 | CONFIG_CRC7=m | 272 | CONFIG_CRC7=m |
| 271 | CONFIG_LIBCRC32C=m | 273 | CONFIG_LIBCRC32C=m |
| 274 | CONFIG_FONTS=y | ||
| 275 | CONFIG_FONT_8x8=y | ||
| 276 | CONFIG_FONT_8x16=y | ||
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 1d6d8fb7f4a1..4555c025629a 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
| 3 | CONFIG_NO_HZ=y | 2 | CONFIG_NO_HZ=y |
| 4 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -27,7 +26,6 @@ CONFIG_ARCH_MXS=y | |||
| 27 | # CONFIG_ARM_THUMB is not set | 26 | # CONFIG_ARM_THUMB is not set |
| 28 | CONFIG_PREEMPT_VOLUNTARY=y | 27 | CONFIG_PREEMPT_VOLUNTARY=y |
| 29 | CONFIG_AEABI=y | 28 | CONFIG_AEABI=y |
| 30 | CONFIG_AUTO_ZRELADDR=y | ||
| 31 | CONFIG_FPE_NWFPE=y | 29 | CONFIG_FPE_NWFPE=y |
| 32 | CONFIG_NET=y | 30 | CONFIG_NET=y |
| 33 | CONFIG_PACKET=y | 31 | CONFIG_PACKET=y |
| @@ -43,8 +41,6 @@ CONFIG_SYN_COOKIES=y | |||
| 43 | # CONFIG_INET_DIAG is not set | 41 | # CONFIG_INET_DIAG is not set |
| 44 | # CONFIG_IPV6 is not set | 42 | # CONFIG_IPV6 is not set |
| 45 | CONFIG_CAN=m | 43 | CONFIG_CAN=m |
| 46 | CONFIG_CAN_RAW=m | ||
| 47 | CONFIG_CAN_BCM=m | ||
| 48 | CONFIG_CAN_FLEXCAN=m | 44 | CONFIG_CAN_FLEXCAN=m |
| 49 | # CONFIG_WIRELESS is not set | 45 | # CONFIG_WIRELESS is not set |
| 50 | CONFIG_DEVTMPFS=y | 46 | CONFIG_DEVTMPFS=y |
| @@ -52,7 +48,6 @@ CONFIG_DEVTMPFS_MOUNT=y | |||
| 52 | # CONFIG_FIRMWARE_IN_KERNEL is not set | 48 | # CONFIG_FIRMWARE_IN_KERNEL is not set |
| 53 | CONFIG_MTD=y | 49 | CONFIG_MTD=y |
| 54 | CONFIG_MTD_CMDLINE_PARTS=y | 50 | CONFIG_MTD_CMDLINE_PARTS=y |
| 55 | CONFIG_MTD_CHAR=y | ||
| 56 | CONFIG_MTD_BLOCK=y | 51 | CONFIG_MTD_BLOCK=y |
| 57 | CONFIG_MTD_DATAFLASH=y | 52 | CONFIG_MTD_DATAFLASH=y |
| 58 | CONFIG_MTD_M25P80=y | 53 | CONFIG_MTD_M25P80=y |
| @@ -67,12 +62,12 @@ CONFIG_SCSI=y | |||
| 67 | CONFIG_BLK_DEV_SD=y | 62 | CONFIG_BLK_DEV_SD=y |
| 68 | CONFIG_NETDEVICES=y | 63 | CONFIG_NETDEVICES=y |
| 69 | CONFIG_ENC28J60=y | 64 | CONFIG_ENC28J60=y |
| 70 | CONFIG_USB_USBNET=y | ||
| 71 | CONFIG_USB_NET_SMSC95XX=y | ||
| 72 | CONFIG_SMSC_PHY=y | 65 | CONFIG_SMSC_PHY=y |
| 73 | CONFIG_ICPLUS_PHY=y | 66 | CONFIG_ICPLUS_PHY=y |
| 74 | CONFIG_REALTEK_PHY=y | 67 | CONFIG_REALTEK_PHY=y |
| 75 | CONFIG_MICREL_PHY=y | 68 | CONFIG_MICREL_PHY=y |
| 69 | CONFIG_USB_USBNET=y | ||
| 70 | CONFIG_USB_NET_SMSC95XX=y | ||
| 76 | # CONFIG_WLAN is not set | 71 | # CONFIG_WLAN is not set |
| 77 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 72 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 78 | CONFIG_INPUT_EVDEV=y | 73 | CONFIG_INPUT_EVDEV=y |
| @@ -110,7 +105,6 @@ CONFIG_LCD_CLASS_DEVICE=y | |||
| 110 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 105 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 111 | CONFIG_BACKLIGHT_PWM=y | 106 | CONFIG_BACKLIGHT_PWM=y |
| 112 | CONFIG_FRAMEBUFFER_CONSOLE=y | 107 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 113 | CONFIG_FONTS=y | ||
| 114 | CONFIG_LOGO=y | 108 | CONFIG_LOGO=y |
| 115 | CONFIG_SOUND=y | 109 | CONFIG_SOUND=y |
| 116 | CONFIG_SND=y | 110 | CONFIG_SND=y |
| @@ -119,9 +113,9 @@ CONFIG_SND_MXS_SOC=y | |||
| 119 | CONFIG_SND_SOC_MXS_SGTL5000=y | 113 | CONFIG_SND_SOC_MXS_SGTL5000=y |
| 120 | CONFIG_USB=y | 114 | CONFIG_USB=y |
| 121 | CONFIG_USB_EHCI_HCD=y | 115 | CONFIG_USB_EHCI_HCD=y |
| 116 | CONFIG_USB_STORAGE=y | ||
| 122 | CONFIG_USB_CHIPIDEA=y | 117 | CONFIG_USB_CHIPIDEA=y |
| 123 | CONFIG_USB_CHIPIDEA_HOST=y | 118 | CONFIG_USB_CHIPIDEA_HOST=y |
| 124 | CONFIG_USB_STORAGE=y | ||
| 125 | CONFIG_USB_PHY=y | 119 | CONFIG_USB_PHY=y |
| 126 | CONFIG_USB_MXS_PHY=y | 120 | CONFIG_USB_MXS_PHY=y |
| 127 | CONFIG_MMC=y | 121 | CONFIG_MMC=y |
| @@ -143,9 +137,9 @@ CONFIG_DMADEVICES=y | |||
| 143 | CONFIG_MXS_DMA=y | 137 | CONFIG_MXS_DMA=y |
| 144 | CONFIG_STAGING=y | 138 | CONFIG_STAGING=y |
| 145 | CONFIG_MXS_LRADC=y | 139 | CONFIG_MXS_LRADC=y |
| 146 | CONFIG_IIO_SYSFS_TRIGGER=y | ||
| 147 | CONFIG_COMMON_CLK_DEBUG=y | 140 | CONFIG_COMMON_CLK_DEBUG=y |
| 148 | CONFIG_IIO=y | 141 | CONFIG_IIO=y |
| 142 | CONFIG_IIO_SYSFS_TRIGGER=y | ||
| 149 | CONFIG_PWM=y | 143 | CONFIG_PWM=y |
| 150 | CONFIG_PWM_MXS=y | 144 | CONFIG_PWM_MXS=y |
| 151 | CONFIG_EXT2_FS=y | 145 | CONFIG_EXT2_FS=y |
| @@ -173,14 +167,14 @@ CONFIG_NLS_CODEPAGE_850=y | |||
| 173 | CONFIG_NLS_ISO8859_1=y | 167 | CONFIG_NLS_ISO8859_1=y |
| 174 | CONFIG_NLS_ISO8859_15=y | 168 | CONFIG_NLS_ISO8859_15=y |
| 175 | CONFIG_PRINTK_TIME=y | 169 | CONFIG_PRINTK_TIME=y |
| 170 | CONFIG_DEBUG_INFO=y | ||
| 176 | CONFIG_FRAME_WARN=2048 | 171 | CONFIG_FRAME_WARN=2048 |
| 177 | CONFIG_MAGIC_SYSRQ=y | ||
| 178 | CONFIG_UNUSED_SYMBOLS=y | 172 | CONFIG_UNUSED_SYMBOLS=y |
| 173 | CONFIG_MAGIC_SYSRQ=y | ||
| 179 | CONFIG_DEBUG_KERNEL=y | 174 | CONFIG_DEBUG_KERNEL=y |
| 180 | CONFIG_LOCKUP_DETECTOR=y | 175 | CONFIG_LOCKUP_DETECTOR=y |
| 181 | CONFIG_TIMER_STATS=y | 176 | CONFIG_TIMER_STATS=y |
| 182 | CONFIG_PROVE_LOCKING=y | 177 | CONFIG_PROVE_LOCKING=y |
| 183 | CONFIG_DEBUG_INFO=y | ||
| 184 | CONFIG_BLK_DEV_IO_TRACE=y | 178 | CONFIG_BLK_DEV_IO_TRACE=y |
| 185 | CONFIG_STRICT_DEVMEM=y | 179 | CONFIG_STRICT_DEVMEM=y |
| 186 | CONFIG_DEBUG_USER=y | 180 | CONFIG_DEBUG_USER=y |
| @@ -188,3 +182,4 @@ CONFIG_DEBUG_USER=y | |||
| 188 | # CONFIG_CRYPTO_HW is not set | 182 | # CONFIG_CRYPTO_HW is not set |
| 189 | CONFIG_CRC_ITU_T=m | 183 | CONFIG_CRC_ITU_T=m |
| 190 | CONFIG_CRC7=m | 184 | CONFIG_CRC7=m |
| 185 | CONFIG_FONTS=y | ||
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 056b27aafbe6..254cf0539439 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
| @@ -305,3 +305,4 @@ CONFIG_TI_DAVINCI_MDIO=y | |||
| 305 | CONFIG_TI_DAVINCI_CPDMA=y | 305 | CONFIG_TI_DAVINCI_CPDMA=y |
| 306 | CONFIG_TI_CPSW=y | 306 | CONFIG_TI_CPSW=y |
| 307 | CONFIG_AT803X_PHY=y | 307 | CONFIG_AT803X_PHY=y |
| 308 | CONFIG_SOC_DRA7XX=y | ||
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index a1c90d7feb0e..454d642a4070 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h | |||
| @@ -36,6 +36,8 @@ struct hw_pci { | |||
| 36 | resource_size_t start, | 36 | resource_size_t start, |
| 37 | resource_size_t size, | 37 | resource_size_t size, |
| 38 | resource_size_t align); | 38 | resource_size_t align); |
| 39 | void (*add_bus)(struct pci_bus *bus); | ||
| 40 | void (*remove_bus)(struct pci_bus *bus); | ||
| 39 | }; | 41 | }; |
| 40 | 42 | ||
| 41 | /* | 43 | /* |
| @@ -63,6 +65,8 @@ struct pci_sys_data { | |||
| 63 | resource_size_t start, | 65 | resource_size_t start, |
| 64 | resource_size_t size, | 66 | resource_size_t size, |
| 65 | resource_size_t align); | 67 | resource_size_t align); |
| 68 | void (*add_bus)(struct pci_bus *bus); | ||
| 69 | void (*remove_bus)(struct pci_bus *bus); | ||
| 66 | void *private_data; /* platform controller private data */ | 70 | void *private_data; /* platform controller private data */ |
| 67 | }; | 71 | }; |
| 68 | 72 | ||
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 88e14d74b6de..317da88ae65b 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c | |||
| @@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus) | |||
| 363 | } | 363 | } |
| 364 | EXPORT_SYMBOL(pcibios_fixup_bus); | 364 | EXPORT_SYMBOL(pcibios_fixup_bus); |
| 365 | 365 | ||
| 366 | void pcibios_add_bus(struct pci_bus *bus) | ||
| 367 | { | ||
| 368 | struct pci_sys_data *sys = bus->sysdata; | ||
| 369 | if (sys->add_bus) | ||
| 370 | sys->add_bus(bus); | ||
| 371 | } | ||
| 372 | |||
| 373 | void pcibios_remove_bus(struct pci_bus *bus) | ||
| 374 | { | ||
| 375 | struct pci_sys_data *sys = bus->sysdata; | ||
| 376 | if (sys->remove_bus) | ||
| 377 | sys->remove_bus(bus); | ||
| 378 | } | ||
| 379 | |||
| 366 | /* | 380 | /* |
| 367 | * Swizzle the device pin each time we cross a bridge. If a platform does | 381 | * Swizzle the device pin each time we cross a bridge. If a platform does |
| 368 | * not provide a swizzle function, we perform the standard PCI swizzling. | 382 | * not provide a swizzle function, we perform the standard PCI swizzling. |
| @@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, | |||
| 464 | sys->swizzle = hw->swizzle; | 478 | sys->swizzle = hw->swizzle; |
| 465 | sys->map_irq = hw->map_irq; | 479 | sys->map_irq = hw->map_irq; |
| 466 | sys->align_resource = hw->align_resource; | 480 | sys->align_resource = hw->align_resource; |
| 481 | sys->add_bus = hw->add_bus; | ||
| 482 | sys->remove_bus = hw->remove_bus; | ||
| 467 | INIT_LIST_HEAD(&sys->resources); | 483 | INIT_LIST_HEAD(&sys->resources); |
| 468 | 484 | ||
| 469 | if (hw->private_data) | 485 | if (hw->private_data) |
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index ad95f6a23a28..bf00d15d954d 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c | |||
| @@ -42,20 +42,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy) | |||
| 42 | { | 42 | { |
| 43 | int value; | 43 | int value; |
| 44 | 44 | ||
| 45 | #define GMII_RCCPSR 260 | ||
| 46 | #define GMII_RRDPSR 261 | ||
| 47 | #define GMII_ERCR 11 | ||
| 48 | #define GMII_ERDWR 12 | ||
| 49 | |||
| 50 | /* Set delay values */ | 45 | /* Set delay values */ |
| 51 | value = GMII_RCCPSR | 0x8000; | 46 | value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000; |
| 52 | phy_write(phy, GMII_ERCR, value); | 47 | phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); |
| 53 | value = 0xF2F4; | 48 | value = 0xF2F4; |
| 54 | phy_write(phy, GMII_ERDWR, value); | 49 | phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); |
| 55 | value = GMII_RRDPSR | 0x8000; | 50 | value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000; |
| 56 | phy_write(phy, GMII_ERCR, value); | 51 | phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); |
| 57 | value = 0x2222; | 52 | value = 0x2222; |
| 58 | phy_write(phy, GMII_ERDWR, value); | 53 | phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); |
| 59 | 54 | ||
| 60 | return 0; | 55 | return 0; |
| 61 | } | 56 | } |
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 1332de8c52c9..c4bdc0a1c36e 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c | |||
| @@ -185,10 +185,6 @@ static __init void da830_evm_usb_init(void) | |||
| 185 | __func__, ret); | 185 | __func__, ret); |
| 186 | } | 186 | } |
| 187 | 187 | ||
| 188 | static struct davinci_uart_config da830_evm_uart_config __initdata = { | ||
| 189 | .enabled_uarts = 0x7, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static const short da830_evm_mcasp1_pins[] = { | 188 | static const short da830_evm_mcasp1_pins[] = { |
| 193 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, | 189 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, |
| 194 | DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, | 190 | DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, |
| @@ -630,7 +626,7 @@ static __init void da830_evm_init(void) | |||
| 630 | pr_warning("da830_evm_init: watchdog registration failed: %d\n", | 626 | pr_warning("da830_evm_init: watchdog registration failed: %d\n", |
| 631 | ret); | 627 | ret); |
| 632 | 628 | ||
| 633 | davinci_serial_init(&da830_evm_uart_config); | 629 | davinci_serial_init(da8xx_serial_device); |
| 634 | i2c_register_board_info(1, da830_evm_i2c_devices, | 630 | i2c_register_board_info(1, da830_evm_i2c_devices, |
| 635 | ARRAY_SIZE(da830_evm_i2c_devices)); | 631 | ARRAY_SIZE(da830_evm_i2c_devices)); |
| 636 | 632 | ||
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index f5c228190fdd..dd1fb24521aa 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -746,10 +746,6 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { | |||
| 746 | .bus_delay = 0, /* usec */ | 746 | .bus_delay = 0, /* usec */ |
| 747 | }; | 747 | }; |
| 748 | 748 | ||
| 749 | static struct davinci_uart_config da850_evm_uart_config __initdata = { | ||
| 750 | .enabled_uarts = 0x7, | ||
| 751 | }; | ||
| 752 | |||
| 753 | /* davinci da850 evm audio machine driver */ | 749 | /* davinci da850 evm audio machine driver */ |
| 754 | static u8 da850_iis_serializer_direction[] = { | 750 | static u8 da850_iis_serializer_direction[] = { |
| 755 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | 751 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, |
| @@ -1492,7 +1488,7 @@ static __init void da850_evm_init(void) | |||
| 1492 | __func__, ret); | 1488 | __func__, ret); |
| 1493 | } | 1489 | } |
| 1494 | 1490 | ||
| 1495 | davinci_serial_init(&da850_evm_uart_config); | 1491 | davinci_serial_init(da8xx_serial_device); |
| 1496 | 1492 | ||
| 1497 | i2c_register_board_info(1, da850_evm_i2c_devices, | 1493 | i2c_register_board_info(1, da850_evm_i2c_devices, |
| 1498 | ARRAY_SIZE(da850_evm_i2c_devices)); | 1494 | ARRAY_SIZE(da850_evm_i2c_devices)); |
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index c2a0a67d09e0..42b23a3194a0 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c | |||
| @@ -314,10 +314,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = { | |||
| 314 | &davinci_nand_device, | 314 | &davinci_nand_device, |
| 315 | }; | 315 | }; |
| 316 | 316 | ||
| 317 | static struct davinci_uart_config uart_config __initdata = { | ||
| 318 | .enabled_uarts = (1 << 0), | ||
| 319 | }; | ||
| 320 | |||
| 321 | static void __init dm355_evm_map_io(void) | 317 | static void __init dm355_evm_map_io(void) |
| 322 | { | 318 | { |
| 323 | dm355_init(); | 319 | dm355_init(); |
| @@ -393,7 +389,7 @@ static __init void dm355_evm_init(void) | |||
| 393 | platform_add_devices(davinci_evm_devices, | 389 | platform_add_devices(davinci_evm_devices, |
| 394 | ARRAY_SIZE(davinci_evm_devices)); | 390 | ARRAY_SIZE(davinci_evm_devices)); |
| 395 | evm_init_i2c(); | 391 | evm_init_i2c(); |
| 396 | davinci_serial_init(&uart_config); | 392 | davinci_serial_init(dm355_serial_device); |
| 397 | 393 | ||
| 398 | /* NOTE: NAND flash timings set by the UBL are slower than | 394 | /* NOTE: NAND flash timings set by the UBL are slower than |
| 399 | * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 | 395 | * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 |
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 139e42da25f0..65a984c52df6 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c | |||
| @@ -173,10 +173,6 @@ static struct platform_device *davinci_leopard_devices[] __initdata = { | |||
| 173 | &davinci_nand_device, | 173 | &davinci_nand_device, |
| 174 | }; | 174 | }; |
| 175 | 175 | ||
| 176 | static struct davinci_uart_config uart_config __initdata = { | ||
| 177 | .enabled_uarts = (1 << 0), | ||
| 178 | }; | ||
| 179 | |||
| 180 | static void __init dm355_leopard_map_io(void) | 176 | static void __init dm355_leopard_map_io(void) |
| 181 | { | 177 | { |
| 182 | dm355_init(); | 178 | dm355_init(); |
| @@ -252,7 +248,7 @@ static __init void dm355_leopard_init(void) | |||
| 252 | platform_add_devices(davinci_leopard_devices, | 248 | platform_add_devices(davinci_leopard_devices, |
| 253 | ARRAY_SIZE(davinci_leopard_devices)); | 249 | ARRAY_SIZE(davinci_leopard_devices)); |
| 254 | leopard_init_i2c(); | 250 | leopard_init_i2c(); |
| 255 | davinci_serial_init(&uart_config); | 251 | davinci_serial_init(dm355_serial_device); |
| 256 | 252 | ||
| 257 | /* NOTE: NAND flash timings set by the UBL are slower than | 253 | /* NOTE: NAND flash timings set by the UBL are slower than |
| 258 | * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 | 254 | * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 |
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 4cdb61c54459..92b7f770615a 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c | |||
| @@ -718,10 +718,6 @@ fail: | |||
| 718 | /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ | 718 | /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ |
| 719 | } | 719 | } |
| 720 | 720 | ||
| 721 | static struct davinci_uart_config uart_config __initdata = { | ||
| 722 | .enabled_uarts = (1 << 0), | ||
| 723 | }; | ||
| 724 | |||
| 725 | static void __init dm365_evm_map_io(void) | 721 | static void __init dm365_evm_map_io(void) |
| 726 | { | 722 | { |
| 727 | dm365_init(); | 723 | dm365_init(); |
| @@ -748,7 +744,7 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = { | |||
| 748 | static __init void dm365_evm_init(void) | 744 | static __init void dm365_evm_init(void) |
| 749 | { | 745 | { |
| 750 | evm_init_i2c(); | 746 | evm_init_i2c(); |
| 751 | davinci_serial_init(&uart_config); | 747 | davinci_serial_init(dm365_serial_device); |
| 752 | 748 | ||
| 753 | dm365evm_emac_configure(); | 749 | dm365evm_emac_configure(); |
| 754 | dm365evm_mmc_configure(); | 750 | dm365evm_mmc_configure(); |
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index fa4bfaf952d8..40bb9b5b87e8 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c | |||
| @@ -727,10 +727,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = { | |||
| 727 | &rtc_dev, | 727 | &rtc_dev, |
| 728 | }; | 728 | }; |
| 729 | 729 | ||
| 730 | static struct davinci_uart_config uart_config __initdata = { | ||
| 731 | .enabled_uarts = (1 << 0), | ||
| 732 | }; | ||
| 733 | |||
| 734 | static void __init | 730 | static void __init |
| 735 | davinci_evm_map_io(void) | 731 | davinci_evm_map_io(void) |
| 736 | { | 732 | { |
| @@ -792,7 +788,7 @@ static __init void davinci_evm_init(void) | |||
| 792 | davinci_setup_mmc(0, &dm6446evm_mmc_config); | 788 | davinci_setup_mmc(0, &dm6446evm_mmc_config); |
| 793 | dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); | 789 | dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); |
| 794 | 790 | ||
| 795 | davinci_serial_init(&uart_config); | 791 | davinci_serial_init(dm644x_serial_device); |
| 796 | dm644x_init_asp(&dm644x_evm_snd_data); | 792 | dm644x_init_asp(&dm644x_evm_snd_data); |
| 797 | 793 | ||
| 798 | /* irlml6401 switches over 1A, in under 8 msec */ | 794 | /* irlml6401 switches over 1A, in under 8 msec */ |
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 0c005e876cac..2bc3651d56cc 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c | |||
| @@ -750,10 +750,6 @@ static void __init davinci_map_io(void) | |||
| 750 | cdce_clk_init(); | 750 | cdce_clk_init(); |
| 751 | } | 751 | } |
| 752 | 752 | ||
| 753 | static struct davinci_uart_config uart_config __initdata = { | ||
| 754 | .enabled_uarts = (1 << 0), | ||
| 755 | }; | ||
| 756 | |||
| 757 | #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" | 753 | #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" |
| 758 | /* | 754 | /* |
| 759 | * The following EDMA channels/slots are not being used by drivers (for | 755 | * The following EDMA channels/slots are not being used by drivers (for |
| @@ -793,7 +789,7 @@ static __init void evm_init(void) | |||
| 793 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 789 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 794 | 790 | ||
| 795 | evm_init_i2c(); | 791 | evm_init_i2c(); |
| 796 | davinci_serial_init(&uart_config); | 792 | davinci_serial_init(dm646x_serial_device); |
| 797 | dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); | 793 | dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); |
| 798 | dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); | 794 | dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); |
| 799 | 795 | ||
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 9549d53aa63f..cd0f58730c2b 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c | |||
| @@ -434,10 +434,6 @@ static void __init mityomapl138_setup_nand(void) | |||
| 434 | ARRAY_SIZE(mityomapl138_devices)); | 434 | ARRAY_SIZE(mityomapl138_devices)); |
| 435 | } | 435 | } |
| 436 | 436 | ||
| 437 | static struct davinci_uart_config mityomapl138_uart_config __initdata = { | ||
| 438 | .enabled_uarts = 0x7, | ||
| 439 | }; | ||
| 440 | |||
| 441 | static const short mityomap_mii_pins[] = { | 437 | static const short mityomap_mii_pins[] = { |
| 442 | DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, | 438 | DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, |
| 443 | DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, | 439 | DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, |
| @@ -517,7 +513,7 @@ static void __init mityomapl138_init(void) | |||
| 517 | if (ret) | 513 | if (ret) |
| 518 | pr_warning("watchdog registration failed: %d\n", ret); | 514 | pr_warning("watchdog registration failed: %d\n", ret); |
| 519 | 515 | ||
| 520 | davinci_serial_init(&mityomapl138_uart_config); | 516 | davinci_serial_init(da8xx_serial_device); |
| 521 | 517 | ||
| 522 | ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); | 518 | ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); |
| 523 | if (ret) | 519 | if (ret) |
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 808233b60e3d..46f336fca803 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c | |||
| @@ -154,10 +154,6 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = { | |||
| 154 | &ntosd2_leds_dev, | 154 | &ntosd2_leds_dev, |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | static struct davinci_uart_config uart_config __initdata = { | ||
| 158 | .enabled_uarts = (1 << 0), | ||
| 159 | }; | ||
| 160 | |||
| 161 | static void __init davinci_ntosd2_map_io(void) | 157 | static void __init davinci_ntosd2_map_io(void) |
| 162 | { | 158 | { |
| 163 | dm644x_init(); | 159 | dm644x_init(); |
| @@ -198,7 +194,7 @@ static __init void davinci_ntosd2_init(void) | |||
| 198 | platform_add_devices(davinci_ntosd2_devices, | 194 | platform_add_devices(davinci_ntosd2_devices, |
| 199 | ARRAY_SIZE(davinci_ntosd2_devices)); | 195 | ARRAY_SIZE(davinci_ntosd2_devices)); |
| 200 | 196 | ||
| 201 | davinci_serial_init(&uart_config); | 197 | davinci_serial_init(dm644x_serial_device); |
| 202 | dm644x_init_asp(&dm644x_ntosd2_snd_data); | 198 | dm644x_init_asp(&dm644x_ntosd2_snd_data); |
| 203 | 199 | ||
| 204 | soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; | 200 | soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; |
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index b8c20de10ca2..ab98c75cabb4 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c | |||
| @@ -286,15 +286,11 @@ usb11_setup_oc_fail: | |||
| 286 | gpio_free(DA850_USB1_VBUS_PIN); | 286 | gpio_free(DA850_USB1_VBUS_PIN); |
| 287 | } | 287 | } |
| 288 | 288 | ||
| 289 | static struct davinci_uart_config omapl138_hawk_uart_config __initdata = { | ||
| 290 | .enabled_uarts = 0x7, | ||
| 291 | }; | ||
| 292 | |||
| 293 | static __init void omapl138_hawk_init(void) | 289 | static __init void omapl138_hawk_init(void) |
| 294 | { | 290 | { |
| 295 | int ret; | 291 | int ret; |
| 296 | 292 | ||
| 297 | davinci_serial_init(&omapl138_hawk_uart_config); | 293 | davinci_serial_init(da8xx_serial_device); |
| 298 | 294 | ||
| 299 | omapl138_hawk_config_emac(); | 295 | omapl138_hawk_config_emac(); |
| 300 | 296 | ||
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 513eee14f77d..d84360148100 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c | |||
| @@ -125,10 +125,6 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = { | |||
| 125 | &davinci_sffsdr_nandflash_device, | 125 | &davinci_sffsdr_nandflash_device, |
| 126 | }; | 126 | }; |
| 127 | 127 | ||
| 128 | static struct davinci_uart_config uart_config __initdata = { | ||
| 129 | .enabled_uarts = (1 << 0), | ||
| 130 | }; | ||
| 131 | |||
| 132 | static void __init davinci_sffsdr_map_io(void) | 128 | static void __init davinci_sffsdr_map_io(void) |
| 133 | { | 129 | { |
| 134 | dm644x_init(); | 130 | dm644x_init(); |
| @@ -141,7 +137,7 @@ static __init void davinci_sffsdr_init(void) | |||
| 141 | platform_add_devices(davinci_sffsdr_devices, | 137 | platform_add_devices(davinci_sffsdr_devices, |
| 142 | ARRAY_SIZE(davinci_sffsdr_devices)); | 138 | ARRAY_SIZE(davinci_sffsdr_devices)); |
| 143 | sffsdr_init_i2c(); | 139 | sffsdr_init_i2c(); |
| 144 | davinci_serial_init(&uart_config); | 140 | davinci_serial_init(dm644x_serial_device); |
| 145 | soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; | 141 | soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; |
| 146 | davinci_setup_usb(0, 0); /* We support only peripheral mode. */ | 142 | davinci_setup_usb(0, 0); /* We support only peripheral mode. */ |
| 147 | 143 | ||
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index abbaf0270be6..d6c746e35ad9 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c | |||
| @@ -395,9 +395,9 @@ static struct clk_lookup da830_clks[] = { | |||
| 395 | CLK(NULL, "tptc0", &tptc0_clk), | 395 | CLK(NULL, "tptc0", &tptc0_clk), |
| 396 | CLK(NULL, "tptc1", &tptc1_clk), | 396 | CLK(NULL, "tptc1", &tptc1_clk), |
| 397 | CLK("da830-mmc.0", NULL, &mmcsd_clk), | 397 | CLK("da830-mmc.0", NULL, &mmcsd_clk), |
| 398 | CLK(NULL, "uart0", &uart0_clk), | 398 | CLK("serial8250.0", NULL, &uart0_clk), |
| 399 | CLK(NULL, "uart1", &uart1_clk), | 399 | CLK("serial8250.1", NULL, &uart1_clk), |
| 400 | CLK(NULL, "uart2", &uart2_clk), | 400 | CLK("serial8250.2", NULL, &uart2_clk), |
| 401 | CLK("spi_davinci.0", NULL, &spi0_clk), | 401 | CLK("spi_davinci.0", NULL, &spi0_clk), |
| 402 | CLK("spi_davinci.1", NULL, &spi1_clk), | 402 | CLK("spi_davinci.1", NULL, &spi1_clk), |
| 403 | CLK(NULL, "ecap0", &ecap0_clk), | 403 | CLK(NULL, "ecap0", &ecap0_clk), |
| @@ -417,6 +417,7 @@ static struct clk_lookup da830_clks[] = { | |||
| 417 | CLK(NULL, "aintc", &aintc_clk), | 417 | CLK(NULL, "aintc", &aintc_clk), |
| 418 | CLK(NULL, "secu_mgr", &secu_mgr_clk), | 418 | CLK(NULL, "secu_mgr", &secu_mgr_clk), |
| 419 | CLK("davinci_emac.1", NULL, &emac_clk), | 419 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 420 | CLK("davinci_mdio.0", "fck", &emac_clk), | ||
| 420 | CLK(NULL, "gpio", &gpio_clk), | 421 | CLK(NULL, "gpio", &gpio_clk), |
| 421 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | 422 | CLK("i2c_davinci.2", NULL, &i2c1_clk), |
| 422 | CLK(NULL, "usb11", &usb11_clk), | 423 | CLK(NULL, "usb11", &usb11_clk), |
| @@ -1199,7 +1200,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = { | |||
| 1199 | .gpio_base = DA8XX_GPIO_BASE, | 1200 | .gpio_base = DA8XX_GPIO_BASE, |
| 1200 | .gpio_num = 128, | 1201 | .gpio_num = 128, |
| 1201 | .gpio_irq = IRQ_DA8XX_GPIO0, | 1202 | .gpio_irq = IRQ_DA8XX_GPIO0, |
| 1202 | .serial_dev = &da8xx_serial_device, | ||
| 1203 | .emac_pdata = &da8xx_emac_pdata, | 1203 | .emac_pdata = &da8xx_emac_pdata, |
| 1204 | }; | 1204 | }; |
| 1205 | 1205 | ||
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index a0d4f6038b60..f56e5fbfa2fd 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
| @@ -451,9 +451,9 @@ static struct clk_lookup da850_clks[] = { | |||
| 451 | CLK(NULL, "tpcc1", &tpcc1_clk), | 451 | CLK(NULL, "tpcc1", &tpcc1_clk), |
| 452 | CLK(NULL, "tptc2", &tptc2_clk), | 452 | CLK(NULL, "tptc2", &tptc2_clk), |
| 453 | CLK("pruss_uio", "pruss", &pruss_clk), | 453 | CLK("pruss_uio", "pruss", &pruss_clk), |
| 454 | CLK(NULL, "uart0", &uart0_clk), | 454 | CLK("serial8250.0", NULL, &uart0_clk), |
| 455 | CLK(NULL, "uart1", &uart1_clk), | 455 | CLK("serial8250.1", NULL, &uart1_clk), |
| 456 | CLK(NULL, "uart2", &uart2_clk), | 456 | CLK("serial8250.2", NULL, &uart2_clk), |
| 457 | CLK(NULL, "aintc", &aintc_clk), | 457 | CLK(NULL, "aintc", &aintc_clk), |
| 458 | CLK(NULL, "gpio", &gpio_clk), | 458 | CLK(NULL, "gpio", &gpio_clk), |
| 459 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | 459 | CLK("i2c_davinci.2", NULL, &i2c1_clk), |
| @@ -461,6 +461,7 @@ static struct clk_lookup da850_clks[] = { | |||
| 461 | CLK(NULL, "arm", &arm_clk), | 461 | CLK(NULL, "arm", &arm_clk), |
| 462 | CLK(NULL, "rmii", &rmii_clk), | 462 | CLK(NULL, "rmii", &rmii_clk), |
| 463 | CLK("davinci_emac.1", NULL, &emac_clk), | 463 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 464 | CLK("davinci_mdio.0", "fck", &emac_clk), | ||
| 464 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), | 465 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), |
| 465 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), | 466 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), |
| 466 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), | 467 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), |
| @@ -1301,7 +1302,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = { | |||
| 1301 | .gpio_base = DA8XX_GPIO_BASE, | 1302 | .gpio_base = DA8XX_GPIO_BASE, |
| 1302 | .gpio_num = 144, | 1303 | .gpio_num = 144, |
| 1303 | .gpio_irq = IRQ_DA8XX_GPIO0, | 1304 | .gpio_irq = IRQ_DA8XX_GPIO0, |
| 1304 | .serial_dev = &da8xx_serial_device, | ||
| 1305 | .emac_pdata = &da8xx_emac_pdata, | 1305 | .emac_pdata = &da8xx_emac_pdata, |
| 1306 | .sram_dma = DA8XX_SHARED_RAM_BASE, | 1306 | .sram_dma = DA8XX_SHARED_RAM_BASE, |
| 1307 | .sram_len = SZ_128K, | 1307 | .sram_len = SZ_128K, |
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 961aea8bbad5..d2bc574ae172 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c | |||
| @@ -20,13 +20,6 @@ | |||
| 20 | 20 | ||
| 21 | #define DA8XX_NUM_UARTS 3 | 21 | #define DA8XX_NUM_UARTS 3 |
| 22 | 22 | ||
| 23 | static void __init da8xx_uart_clk_enable(void) | ||
| 24 | { | ||
| 25 | int i; | ||
| 26 | for (i = 0; i < DA8XX_NUM_UARTS; i++) | ||
| 27 | davinci_serial_setup_clk(i, NULL); | ||
| 28 | } | ||
| 29 | |||
| 30 | static struct of_device_id da8xx_irq_match[] __initdata = { | 23 | static struct of_device_id da8xx_irq_match[] __initdata = { |
| 31 | { .compatible = "ti,cp-intc", .data = cp_intc_of_init, }, | 24 | { .compatible = "ti,cp-intc", .data = cp_intc_of_init, }, |
| 32 | { } | 25 | { } |
| @@ -47,6 +40,12 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { | |||
| 47 | OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), | 40 | OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), |
| 48 | OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), | 41 | OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), |
| 49 | OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), | 42 | OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), |
| 43 | OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL), | ||
| 44 | OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL), | ||
| 45 | OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL), | ||
| 46 | OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL), | ||
| 47 | OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1", | ||
| 48 | NULL), | ||
| 50 | {} | 49 | {} |
| 51 | }; | 50 | }; |
| 52 | 51 | ||
| @@ -57,7 +56,6 @@ static void __init da850_init_machine(void) | |||
| 57 | of_platform_populate(NULL, of_default_bus_match_table, | 56 | of_platform_populate(NULL, of_default_bus_match_table, |
| 58 | da850_auxdata_lookup, NULL); | 57 | da850_auxdata_lookup, NULL); |
| 59 | 58 | ||
| 60 | da8xx_uart_clk_enable(); | ||
| 61 | } | 59 | } |
| 62 | 60 | ||
| 63 | static const char *da850_boards_compat[] __initdata = { | 61 | static const char *da850_boards_compat[] __initdata = { |
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index a883043d0820..2ab5d577186f 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h | |||
| @@ -106,4 +106,9 @@ int dm646x_init_edma(struct edma_rsv_info *rsv); | |||
| 106 | void dm646x_video_init(void); | 106 | void dm646x_video_init(void); |
| 107 | void dm646x_setup_vpif(struct vpif_display_config *, | 107 | void dm646x_setup_vpif(struct vpif_display_config *, |
| 108 | struct vpif_capture_config *); | 108 | struct vpif_capture_config *); |
| 109 | |||
| 110 | extern struct platform_device dm365_serial_device[]; | ||
| 111 | extern struct platform_device dm355_serial_device[]; | ||
| 112 | extern struct platform_device dm644x_serial_device[]; | ||
| 113 | extern struct platform_device dm646x_serial_device[]; | ||
| 109 | #endif /*__DAVINCI_H */ | 114 | #endif /*__DAVINCI_H */ |
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 71a46a348761..2e473fefd71e 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c | |||
| @@ -68,7 +68,7 @@ | |||
| 68 | void __iomem *da8xx_syscfg0_base; | 68 | void __iomem *da8xx_syscfg0_base; |
| 69 | void __iomem *da8xx_syscfg1_base; | 69 | void __iomem *da8xx_syscfg1_base; |
| 70 | 70 | ||
| 71 | static struct plat_serial8250_port da8xx_serial_pdata[] = { | 71 | static struct plat_serial8250_port da8xx_serial0_pdata[] = { |
| 72 | { | 72 | { |
| 73 | .mapbase = DA8XX_UART0_BASE, | 73 | .mapbase = DA8XX_UART0_BASE, |
| 74 | .irq = IRQ_DA8XX_UARTINT0, | 74 | .irq = IRQ_DA8XX_UARTINT0, |
| @@ -78,6 +78,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { | |||
| 78 | .regshift = 2, | 78 | .regshift = 2, |
| 79 | }, | 79 | }, |
| 80 | { | 80 | { |
| 81 | .flags = 0, | ||
| 82 | } | ||
| 83 | }; | ||
| 84 | static struct plat_serial8250_port da8xx_serial1_pdata[] = { | ||
| 85 | { | ||
| 81 | .mapbase = DA8XX_UART1_BASE, | 86 | .mapbase = DA8XX_UART1_BASE, |
| 82 | .irq = IRQ_DA8XX_UARTINT1, | 87 | .irq = IRQ_DA8XX_UARTINT1, |
| 83 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 88 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -86,6 +91,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { | |||
| 86 | .regshift = 2, | 91 | .regshift = 2, |
| 87 | }, | 92 | }, |
| 88 | { | 93 | { |
| 94 | .flags = 0, | ||
| 95 | } | ||
| 96 | }; | ||
| 97 | static struct plat_serial8250_port da8xx_serial2_pdata[] = { | ||
| 98 | { | ||
| 89 | .mapbase = DA8XX_UART2_BASE, | 99 | .mapbase = DA8XX_UART2_BASE, |
| 90 | .irq = IRQ_DA8XX_UARTINT2, | 100 | .irq = IRQ_DA8XX_UARTINT2, |
| 91 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 101 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -95,15 +105,33 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { | |||
| 95 | }, | 105 | }, |
| 96 | { | 106 | { |
| 97 | .flags = 0, | 107 | .flags = 0, |
| 98 | }, | 108 | } |
| 99 | }; | 109 | }; |
| 100 | 110 | ||
| 101 | struct platform_device da8xx_serial_device = { | 111 | struct platform_device da8xx_serial_device[] = { |
| 102 | .name = "serial8250", | 112 | { |
| 103 | .id = PLAT8250_DEV_PLATFORM, | 113 | .name = "serial8250", |
| 104 | .dev = { | 114 | .id = PLAT8250_DEV_PLATFORM, |
| 105 | .platform_data = da8xx_serial_pdata, | 115 | .dev = { |
| 116 | .platform_data = da8xx_serial0_pdata, | ||
| 117 | } | ||
| 118 | }, | ||
| 119 | { | ||
| 120 | .name = "serial8250", | ||
| 121 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 122 | .dev = { | ||
| 123 | .platform_data = da8xx_serial1_pdata, | ||
| 124 | } | ||
| 125 | }, | ||
| 126 | { | ||
| 127 | .name = "serial8250", | ||
| 128 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 129 | .dev = { | ||
| 130 | .platform_data = da8xx_serial2_pdata, | ||
| 131 | } | ||
| 106 | }, | 132 | }, |
| 133 | { | ||
| 134 | } | ||
| 107 | }; | 135 | }; |
| 108 | 136 | ||
| 109 | static s8 da8xx_queue_tc_mapping[][2] = { | 137 | static s8 da8xx_queue_tc_mapping[][2] = { |
| @@ -453,12 +481,8 @@ int __init da8xx_register_emac(void) | |||
| 453 | ret = platform_device_register(&da8xx_mdio_device); | 481 | ret = platform_device_register(&da8xx_mdio_device); |
| 454 | if (ret < 0) | 482 | if (ret < 0) |
| 455 | return ret; | 483 | return ret; |
| 456 | ret = platform_device_register(&da8xx_emac_device); | 484 | |
| 457 | if (ret < 0) | 485 | return platform_device_register(&da8xx_emac_device); |
| 458 | return ret; | ||
| 459 | ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), | ||
| 460 | NULL, &da8xx_emac_device.dev); | ||
| 461 | return ret; | ||
| 462 | } | 486 | } |
| 463 | 487 | ||
| 464 | static struct resource da830_mcasp1_resources[] = { | 488 | static struct resource da830_mcasp1_resources[] = { |
| @@ -828,14 +852,7 @@ static struct platform_device da8xx_rtc_device = { | |||
| 828 | 852 | ||
| 829 | int da8xx_register_rtc(void) | 853 | int da8xx_register_rtc(void) |
| 830 | { | 854 | { |
| 831 | int ret; | 855 | return platform_device_register(&da8xx_rtc_device); |
| 832 | |||
| 833 | ret = platform_device_register(&da8xx_rtc_device); | ||
| 834 | if (!ret) | ||
| 835 | /* Atleast on DA850, RTC is a wakeup source */ | ||
| 836 | device_init_wakeup(&da8xx_rtc_device.dev, true); | ||
| 837 | |||
| 838 | return ret; | ||
| 839 | } | 856 | } |
| 840 | 857 | ||
| 841 | static void __iomem *da8xx_ddr2_ctlr_base; | 858 | static void __iomem *da8xx_ddr2_ctlr_base; |
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 128cb9ae80f4..01d8686e553c 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c | |||
| @@ -126,7 +126,7 @@ static struct platform_device edma_device = { | |||
| 126 | .dev.platform_data = tnetv107x_edma_info, | 126 | .dev.platform_data = tnetv107x_edma_info, |
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | static struct plat_serial8250_port serial_data[] = { | 129 | static struct plat_serial8250_port serial0_platform_data[] = { |
| 130 | { | 130 | { |
| 131 | .mapbase = TNETV107X_UART0_BASE, | 131 | .mapbase = TNETV107X_UART0_BASE, |
| 132 | .irq = IRQ_TNETV107X_UART0, | 132 | .irq = IRQ_TNETV107X_UART0, |
| @@ -137,6 +137,11 @@ static struct plat_serial8250_port serial_data[] = { | |||
| 137 | .regshift = 2, | 137 | .regshift = 2, |
| 138 | }, | 138 | }, |
| 139 | { | 139 | { |
| 140 | .flags = 0, | ||
| 141 | } | ||
| 142 | }; | ||
| 143 | static struct plat_serial8250_port serial1_platform_data[] = { | ||
| 144 | { | ||
| 140 | .mapbase = TNETV107X_UART1_BASE, | 145 | .mapbase = TNETV107X_UART1_BASE, |
| 141 | .irq = IRQ_TNETV107X_UART1, | 146 | .irq = IRQ_TNETV107X_UART1, |
| 142 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 147 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -146,6 +151,11 @@ static struct plat_serial8250_port serial_data[] = { | |||
| 146 | .regshift = 2, | 151 | .regshift = 2, |
| 147 | }, | 152 | }, |
| 148 | { | 153 | { |
| 154 | .flags = 0, | ||
| 155 | } | ||
| 156 | }; | ||
| 157 | static struct plat_serial8250_port serial2_platform_data[] = { | ||
| 158 | { | ||
| 149 | .mapbase = TNETV107X_UART2_BASE, | 159 | .mapbase = TNETV107X_UART2_BASE, |
| 150 | .irq = IRQ_TNETV107X_UART2, | 160 | .irq = IRQ_TNETV107X_UART2, |
| 151 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 161 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -156,13 +166,28 @@ static struct plat_serial8250_port serial_data[] = { | |||
| 156 | }, | 166 | }, |
| 157 | { | 167 | { |
| 158 | .flags = 0, | 168 | .flags = 0, |
| 159 | }, | 169 | } |
| 160 | }; | 170 | }; |
| 161 | 171 | ||
| 162 | struct platform_device tnetv107x_serial_device = { | 172 | |
| 163 | .name = "serial8250", | 173 | struct platform_device tnetv107x_serial_device[] = { |
| 164 | .id = PLAT8250_DEV_PLATFORM, | 174 | { |
| 165 | .dev.platform_data = serial_data, | 175 | .name = "serial8250", |
| 176 | .id = PLAT8250_DEV_PLATFORM, | ||
| 177 | .dev.platform_data = serial0_platform_data, | ||
| 178 | }, | ||
| 179 | { | ||
| 180 | .name = "serial8250", | ||
| 181 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 182 | .dev.platform_data = serial1_platform_data, | ||
| 183 | }, | ||
| 184 | { | ||
| 185 | .name = "serial8250", | ||
| 186 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 187 | .dev.platform_data = serial2_platform_data, | ||
| 188 | }, | ||
| 189 | { | ||
| 190 | } | ||
| 166 | }; | 191 | }; |
| 167 | 192 | ||
| 168 | static struct resource mmc0_resources[] = { | 193 | static struct resource mmc0_resources[] = { |
| @@ -385,7 +410,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) | |||
| 385 | platform_device_register(&tsc_device); | 410 | platform_device_register(&tsc_device); |
| 386 | 411 | ||
| 387 | if (info->serial_config) | 412 | if (info->serial_config) |
| 388 | davinci_serial_init(info->serial_config); | 413 | davinci_serial_init(tnetv107x_serial_device); |
| 389 | 414 | ||
| 390 | for (i = 0; i < 2; i++) | 415 | for (i = 0; i < 2; i++) |
| 391 | if (info->mmc_config[i]) { | 416 | if (info->mmc_config[i]) { |
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 86100d179694..3eaa5f6b2160 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c | |||
| @@ -357,9 +357,9 @@ static struct clk_lookup dm355_clks[] = { | |||
| 357 | CLK(NULL, "clkout3", &clkout3_clk), | 357 | CLK(NULL, "clkout3", &clkout3_clk), |
| 358 | CLK(NULL, "arm", &arm_clk), | 358 | CLK(NULL, "arm", &arm_clk), |
| 359 | CLK(NULL, "mjcp", &mjcp_clk), | 359 | CLK(NULL, "mjcp", &mjcp_clk), |
| 360 | CLK(NULL, "uart0", &uart0_clk), | 360 | CLK("serial8250.0", NULL, &uart0_clk), |
| 361 | CLK(NULL, "uart1", &uart1_clk), | 361 | CLK("serial8250.1", NULL, &uart1_clk), |
| 362 | CLK(NULL, "uart2", &uart2_clk), | 362 | CLK("serial8250.2", NULL, &uart2_clk), |
| 363 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 363 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 364 | CLK("davinci-mcbsp.0", NULL, &asp0_clk), | 364 | CLK("davinci-mcbsp.0", NULL, &asp0_clk), |
| 365 | CLK("davinci-mcbsp.1", NULL, &asp1_clk), | 365 | CLK("davinci-mcbsp.1", NULL, &asp1_clk), |
| @@ -922,7 +922,7 @@ static struct davinci_timer_info dm355_timer_info = { | |||
| 922 | .clocksource_id = T0_TOP, | 922 | .clocksource_id = T0_TOP, |
| 923 | }; | 923 | }; |
| 924 | 924 | ||
| 925 | static struct plat_serial8250_port dm355_serial_platform_data[] = { | 925 | static struct plat_serial8250_port dm355_serial0_platform_data[] = { |
| 926 | { | 926 | { |
| 927 | .mapbase = DAVINCI_UART0_BASE, | 927 | .mapbase = DAVINCI_UART0_BASE, |
| 928 | .irq = IRQ_UARTINT0, | 928 | .irq = IRQ_UARTINT0, |
| @@ -932,6 +932,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { | |||
| 932 | .regshift = 2, | 932 | .regshift = 2, |
| 933 | }, | 933 | }, |
| 934 | { | 934 | { |
| 935 | .flags = 0, | ||
| 936 | } | ||
| 937 | }; | ||
| 938 | static struct plat_serial8250_port dm355_serial1_platform_data[] = { | ||
| 939 | { | ||
| 935 | .mapbase = DAVINCI_UART1_BASE, | 940 | .mapbase = DAVINCI_UART1_BASE, |
| 936 | .irq = IRQ_UARTINT1, | 941 | .irq = IRQ_UARTINT1, |
| 937 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 942 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -940,6 +945,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { | |||
| 940 | .regshift = 2, | 945 | .regshift = 2, |
| 941 | }, | 946 | }, |
| 942 | { | 947 | { |
| 948 | .flags = 0, | ||
| 949 | } | ||
| 950 | }; | ||
| 951 | static struct plat_serial8250_port dm355_serial2_platform_data[] = { | ||
| 952 | { | ||
| 943 | .mapbase = DM355_UART2_BASE, | 953 | .mapbase = DM355_UART2_BASE, |
| 944 | .irq = IRQ_DM355_UARTINT2, | 954 | .irq = IRQ_DM355_UARTINT2, |
| 945 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 955 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -948,16 +958,34 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { | |||
| 948 | .regshift = 2, | 958 | .regshift = 2, |
| 949 | }, | 959 | }, |
| 950 | { | 960 | { |
| 951 | .flags = 0 | 961 | .flags = 0, |
| 952 | }, | 962 | } |
| 953 | }; | 963 | }; |
| 954 | 964 | ||
| 955 | static struct platform_device dm355_serial_device = { | 965 | struct platform_device dm355_serial_device[] = { |
| 956 | .name = "serial8250", | 966 | { |
| 957 | .id = PLAT8250_DEV_PLATFORM, | 967 | .name = "serial8250", |
| 958 | .dev = { | 968 | .id = PLAT8250_DEV_PLATFORM, |
| 959 | .platform_data = dm355_serial_platform_data, | 969 | .dev = { |
| 970 | .platform_data = dm355_serial0_platform_data, | ||
| 971 | } | ||
| 972 | }, | ||
| 973 | { | ||
| 974 | .name = "serial8250", | ||
| 975 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 976 | .dev = { | ||
| 977 | .platform_data = dm355_serial1_platform_data, | ||
| 978 | } | ||
| 960 | }, | 979 | }, |
| 980 | { | ||
| 981 | .name = "serial8250", | ||
| 982 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 983 | .dev = { | ||
| 984 | .platform_data = dm355_serial2_platform_data, | ||
| 985 | } | ||
| 986 | }, | ||
| 987 | { | ||
| 988 | } | ||
| 961 | }; | 989 | }; |
| 962 | 990 | ||
| 963 | static struct davinci_soc_info davinci_soc_info_dm355 = { | 991 | static struct davinci_soc_info davinci_soc_info_dm355 = { |
| @@ -981,7 +1009,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { | |||
| 981 | .gpio_base = DAVINCI_GPIO_BASE, | 1009 | .gpio_base = DAVINCI_GPIO_BASE, |
| 982 | .gpio_num = 104, | 1010 | .gpio_num = 104, |
| 983 | .gpio_irq = IRQ_DM355_GPIOBNK0, | 1011 | .gpio_irq = IRQ_DM355_GPIOBNK0, |
| 984 | .serial_dev = &dm355_serial_device, | ||
| 985 | .sram_dma = 0x00010000, | 1012 | .sram_dma = 0x00010000, |
| 986 | .sram_len = SZ_32K, | 1013 | .sram_len = SZ_32K, |
| 987 | }; | 1014 | }; |
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index dad28029ba9b..c29e324eb0bb 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c | |||
| @@ -455,8 +455,8 @@ static struct clk_lookup dm365_clks[] = { | |||
| 455 | CLK("vpss", "master", &vpss_master_clk), | 455 | CLK("vpss", "master", &vpss_master_clk), |
| 456 | CLK("vpss", "slave", &vpss_slave_clk), | 456 | CLK("vpss", "slave", &vpss_slave_clk), |
| 457 | CLK(NULL, "arm", &arm_clk), | 457 | CLK(NULL, "arm", &arm_clk), |
| 458 | CLK(NULL, "uart0", &uart0_clk), | 458 | CLK("serial8250.0", NULL, &uart0_clk), |
| 459 | CLK(NULL, "uart1", &uart1_clk), | 459 | CLK("serial8250.1", NULL, &uart1_clk), |
| 460 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 460 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 461 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), | 461 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), |
| 462 | CLK("da830-mmc.1", NULL, &mmcsd1_clk), | 462 | CLK("da830-mmc.1", NULL, &mmcsd1_clk), |
| @@ -477,6 +477,7 @@ static struct clk_lookup dm365_clks[] = { | |||
| 477 | CLK(NULL, "timer3", &timer3_clk), | 477 | CLK(NULL, "timer3", &timer3_clk), |
| 478 | CLK(NULL, "usb", &usb_clk), | 478 | CLK(NULL, "usb", &usb_clk), |
| 479 | CLK("davinci_emac.1", NULL, &emac_clk), | 479 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 480 | CLK("davinci_mdio.0", "fck", &emac_clk), | ||
| 480 | CLK("davinci_voicecodec", NULL, &voicecodec_clk), | 481 | CLK("davinci_voicecodec", NULL, &voicecodec_clk), |
| 481 | CLK("davinci-mcbsp", NULL, &asp0_clk), | 482 | CLK("davinci-mcbsp", NULL, &asp0_clk), |
| 482 | CLK(NULL, "rto", &rto_clk), | 483 | CLK(NULL, "rto", &rto_clk), |
| @@ -1041,7 +1042,7 @@ static struct davinci_timer_info dm365_timer_info = { | |||
| 1041 | 1042 | ||
| 1042 | #define DM365_UART1_BASE (IO_PHYS + 0x106000) | 1043 | #define DM365_UART1_BASE (IO_PHYS + 0x106000) |
| 1043 | 1044 | ||
| 1044 | static struct plat_serial8250_port dm365_serial_platform_data[] = { | 1045 | static struct plat_serial8250_port dm365_serial0_platform_data[] = { |
| 1045 | { | 1046 | { |
| 1046 | .mapbase = DAVINCI_UART0_BASE, | 1047 | .mapbase = DAVINCI_UART0_BASE, |
| 1047 | .irq = IRQ_UARTINT0, | 1048 | .irq = IRQ_UARTINT0, |
| @@ -1051,6 +1052,11 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { | |||
| 1051 | .regshift = 2, | 1052 | .regshift = 2, |
| 1052 | }, | 1053 | }, |
| 1053 | { | 1054 | { |
| 1055 | .flags = 0, | ||
| 1056 | } | ||
| 1057 | }; | ||
| 1058 | static struct plat_serial8250_port dm365_serial1_platform_data[] = { | ||
| 1059 | { | ||
| 1054 | .mapbase = DM365_UART1_BASE, | 1060 | .mapbase = DM365_UART1_BASE, |
| 1055 | .irq = IRQ_UARTINT1, | 1061 | .irq = IRQ_UARTINT1, |
| 1056 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 1062 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -1059,16 +1065,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { | |||
| 1059 | .regshift = 2, | 1065 | .regshift = 2, |
| 1060 | }, | 1066 | }, |
| 1061 | { | 1067 | { |
| 1062 | .flags = 0 | 1068 | .flags = 0, |
| 1063 | }, | 1069 | } |
| 1064 | }; | 1070 | }; |
| 1065 | 1071 | ||
| 1066 | static struct platform_device dm365_serial_device = { | 1072 | struct platform_device dm365_serial_device[] = { |
| 1067 | .name = "serial8250", | 1073 | { |
| 1068 | .id = PLAT8250_DEV_PLATFORM, | 1074 | .name = "serial8250", |
| 1069 | .dev = { | 1075 | .id = PLAT8250_DEV_PLATFORM, |
| 1070 | .platform_data = dm365_serial_platform_data, | 1076 | .dev = { |
| 1077 | .platform_data = dm365_serial0_platform_data, | ||
| 1078 | } | ||
| 1079 | }, | ||
| 1080 | { | ||
| 1081 | .name = "serial8250", | ||
| 1082 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 1083 | .dev = { | ||
| 1084 | .platform_data = dm365_serial1_platform_data, | ||
| 1085 | } | ||
| 1071 | }, | 1086 | }, |
| 1087 | { | ||
| 1088 | } | ||
| 1072 | }; | 1089 | }; |
| 1073 | 1090 | ||
| 1074 | static struct davinci_soc_info davinci_soc_info_dm365 = { | 1091 | static struct davinci_soc_info davinci_soc_info_dm365 = { |
| @@ -1093,7 +1110,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { | |||
| 1093 | .gpio_num = 104, | 1110 | .gpio_num = 104, |
| 1094 | .gpio_irq = IRQ_DM365_GPIO0, | 1111 | .gpio_irq = IRQ_DM365_GPIO0, |
| 1095 | .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ | 1112 | .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ |
| 1096 | .serial_dev = &dm365_serial_device, | ||
| 1097 | .emac_pdata = &dm365_emac_pdata, | 1113 | .emac_pdata = &dm365_emac_pdata, |
| 1098 | .sram_dma = 0x00010000, | 1114 | .sram_dma = 0x00010000, |
| 1099 | .sram_len = SZ_32K, | 1115 | .sram_len = SZ_32K, |
| @@ -1407,8 +1423,6 @@ static int __init dm365_init_devices(void) | |||
| 1407 | 1423 | ||
| 1408 | platform_device_register(&dm365_mdio_device); | 1424 | platform_device_register(&dm365_mdio_device); |
| 1409 | platform_device_register(&dm365_emac_device); | 1425 | platform_device_register(&dm365_emac_device); |
| 1410 | clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), | ||
| 1411 | NULL, &dm365_emac_device.dev); | ||
| 1412 | 1426 | ||
| 1413 | return 0; | 1427 | return 0; |
| 1414 | } | 1428 | } |
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index a49d18246fe9..4f74682293d6 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c | |||
| @@ -303,10 +303,11 @@ static struct clk_lookup dm644x_clks[] = { | |||
| 303 | CLK("vpss", "master", &vpss_master_clk), | 303 | CLK("vpss", "master", &vpss_master_clk), |
| 304 | CLK("vpss", "slave", &vpss_slave_clk), | 304 | CLK("vpss", "slave", &vpss_slave_clk), |
| 305 | CLK(NULL, "arm", &arm_clk), | 305 | CLK(NULL, "arm", &arm_clk), |
| 306 | CLK(NULL, "uart0", &uart0_clk), | 306 | CLK("serial8250.0", NULL, &uart0_clk), |
| 307 | CLK(NULL, "uart1", &uart1_clk), | 307 | CLK("serial8250.1", NULL, &uart1_clk), |
| 308 | CLK(NULL, "uart2", &uart2_clk), | 308 | CLK("serial8250.2", NULL, &uart2_clk), |
| 309 | CLK("davinci_emac.1", NULL, &emac_clk), | 309 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 310 | CLK("davinci_mdio.0", "fck", &emac_clk), | ||
| 310 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 311 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 311 | CLK("palm_bk3710", NULL, &ide_clk), | 312 | CLK("palm_bk3710", NULL, &ide_clk), |
| 312 | CLK("davinci-mcbsp", NULL, &asp_clk), | 313 | CLK("davinci-mcbsp", NULL, &asp_clk), |
| @@ -813,7 +814,7 @@ static struct davinci_timer_info dm644x_timer_info = { | |||
| 813 | .clocksource_id = T0_TOP, | 814 | .clocksource_id = T0_TOP, |
| 814 | }; | 815 | }; |
| 815 | 816 | ||
| 816 | static struct plat_serial8250_port dm644x_serial_platform_data[] = { | 817 | static struct plat_serial8250_port dm644x_serial0_platform_data[] = { |
| 817 | { | 818 | { |
| 818 | .mapbase = DAVINCI_UART0_BASE, | 819 | .mapbase = DAVINCI_UART0_BASE, |
| 819 | .irq = IRQ_UARTINT0, | 820 | .irq = IRQ_UARTINT0, |
| @@ -823,6 +824,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { | |||
| 823 | .regshift = 2, | 824 | .regshift = 2, |
| 824 | }, | 825 | }, |
| 825 | { | 826 | { |
| 827 | .flags = 0, | ||
| 828 | } | ||
| 829 | }; | ||
| 830 | static struct plat_serial8250_port dm644x_serial1_platform_data[] = { | ||
| 831 | { | ||
| 826 | .mapbase = DAVINCI_UART1_BASE, | 832 | .mapbase = DAVINCI_UART1_BASE, |
| 827 | .irq = IRQ_UARTINT1, | 833 | .irq = IRQ_UARTINT1, |
| 828 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 834 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -831,6 +837,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { | |||
| 831 | .regshift = 2, | 837 | .regshift = 2, |
| 832 | }, | 838 | }, |
| 833 | { | 839 | { |
| 840 | .flags = 0, | ||
| 841 | } | ||
| 842 | }; | ||
| 843 | static struct plat_serial8250_port dm644x_serial2_platform_data[] = { | ||
| 844 | { | ||
| 834 | .mapbase = DAVINCI_UART2_BASE, | 845 | .mapbase = DAVINCI_UART2_BASE, |
| 835 | .irq = IRQ_UARTINT2, | 846 | .irq = IRQ_UARTINT2, |
| 836 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 847 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -839,16 +850,34 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { | |||
| 839 | .regshift = 2, | 850 | .regshift = 2, |
| 840 | }, | 851 | }, |
| 841 | { | 852 | { |
| 842 | .flags = 0 | 853 | .flags = 0, |
| 843 | }, | 854 | } |
| 844 | }; | 855 | }; |
| 845 | 856 | ||
| 846 | static struct platform_device dm644x_serial_device = { | 857 | struct platform_device dm644x_serial_device[] = { |
| 847 | .name = "serial8250", | 858 | { |
| 848 | .id = PLAT8250_DEV_PLATFORM, | 859 | .name = "serial8250", |
| 849 | .dev = { | 860 | .id = PLAT8250_DEV_PLATFORM, |
| 850 | .platform_data = dm644x_serial_platform_data, | 861 | .dev = { |
| 862 | .platform_data = dm644x_serial0_platform_data, | ||
| 863 | } | ||
| 851 | }, | 864 | }, |
| 865 | { | ||
| 866 | .name = "serial8250", | ||
| 867 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 868 | .dev = { | ||
| 869 | .platform_data = dm644x_serial1_platform_data, | ||
| 870 | } | ||
| 871 | }, | ||
| 872 | { | ||
| 873 | .name = "serial8250", | ||
| 874 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 875 | .dev = { | ||
| 876 | .platform_data = dm644x_serial2_platform_data, | ||
| 877 | } | ||
| 878 | }, | ||
| 879 | { | ||
| 880 | } | ||
| 852 | }; | 881 | }; |
| 853 | 882 | ||
| 854 | static struct davinci_soc_info davinci_soc_info_dm644x = { | 883 | static struct davinci_soc_info davinci_soc_info_dm644x = { |
| @@ -872,7 +901,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { | |||
| 872 | .gpio_base = DAVINCI_GPIO_BASE, | 901 | .gpio_base = DAVINCI_GPIO_BASE, |
| 873 | .gpio_num = 71, | 902 | .gpio_num = 71, |
| 874 | .gpio_irq = IRQ_GPIOBNK0, | 903 | .gpio_irq = IRQ_GPIOBNK0, |
| 875 | .serial_dev = &dm644x_serial_device, | ||
| 876 | .emac_pdata = &dm644x_emac_pdata, | 904 | .emac_pdata = &dm644x_emac_pdata, |
| 877 | .sram_dma = 0x00008000, | 905 | .sram_dma = 0x00008000, |
| 878 | .sram_len = SZ_16K, | 906 | .sram_len = SZ_16K, |
| @@ -923,8 +951,6 @@ static int __init dm644x_init_devices(void) | |||
| 923 | 951 | ||
| 924 | platform_device_register(&dm644x_mdio_device); | 952 | platform_device_register(&dm644x_mdio_device); |
| 925 | platform_device_register(&dm644x_emac_device); | 953 | platform_device_register(&dm644x_emac_device); |
| 926 | clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev), | ||
| 927 | NULL, &dm644x_emac_device.dev); | ||
| 928 | 954 | ||
| 929 | return 0; | 955 | return 0; |
| 930 | } | 956 | } |
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index d1259e80141b..68f8d1f1aca1 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c | |||
| @@ -342,15 +342,16 @@ static struct clk_lookup dm646x_clks[] = { | |||
| 342 | CLK(NULL, "edma_tc1", &edma_tc1_clk), | 342 | CLK(NULL, "edma_tc1", &edma_tc1_clk), |
| 343 | CLK(NULL, "edma_tc2", &edma_tc2_clk), | 343 | CLK(NULL, "edma_tc2", &edma_tc2_clk), |
| 344 | CLK(NULL, "edma_tc3", &edma_tc3_clk), | 344 | CLK(NULL, "edma_tc3", &edma_tc3_clk), |
| 345 | CLK(NULL, "uart0", &uart0_clk), | 345 | CLK("serial8250.0", NULL, &uart0_clk), |
| 346 | CLK(NULL, "uart1", &uart1_clk), | 346 | CLK("serial8250.1", NULL, &uart1_clk), |
| 347 | CLK(NULL, "uart2", &uart2_clk), | 347 | CLK("serial8250.2", NULL, &uart2_clk), |
| 348 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 348 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 349 | CLK(NULL, "gpio", &gpio_clk), | 349 | CLK(NULL, "gpio", &gpio_clk), |
| 350 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), | 350 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), |
| 351 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | 351 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), |
| 352 | CLK(NULL, "aemif", &aemif_clk), | 352 | CLK(NULL, "aemif", &aemif_clk), |
| 353 | CLK("davinci_emac.1", NULL, &emac_clk), | 353 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 354 | CLK("davinci_mdio.0", "fck", &emac_clk), | ||
| 354 | CLK(NULL, "pwm0", &pwm0_clk), | 355 | CLK(NULL, "pwm0", &pwm0_clk), |
| 355 | CLK(NULL, "pwm1", &pwm1_clk), | 356 | CLK(NULL, "pwm1", &pwm1_clk), |
| 356 | CLK(NULL, "timer0", &timer0_clk), | 357 | CLK(NULL, "timer0", &timer0_clk), |
| @@ -790,7 +791,7 @@ static struct davinci_timer_info dm646x_timer_info = { | |||
| 790 | .clocksource_id = T0_TOP, | 791 | .clocksource_id = T0_TOP, |
| 791 | }; | 792 | }; |
| 792 | 793 | ||
| 793 | static struct plat_serial8250_port dm646x_serial_platform_data[] = { | 794 | static struct plat_serial8250_port dm646x_serial0_platform_data[] = { |
| 794 | { | 795 | { |
| 795 | .mapbase = DAVINCI_UART0_BASE, | 796 | .mapbase = DAVINCI_UART0_BASE, |
| 796 | .irq = IRQ_UARTINT0, | 797 | .irq = IRQ_UARTINT0, |
| @@ -800,6 +801,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { | |||
| 800 | .regshift = 2, | 801 | .regshift = 2, |
| 801 | }, | 802 | }, |
| 802 | { | 803 | { |
| 804 | .flags = 0, | ||
| 805 | } | ||
| 806 | }; | ||
| 807 | static struct plat_serial8250_port dm646x_serial1_platform_data[] = { | ||
| 808 | { | ||
| 803 | .mapbase = DAVINCI_UART1_BASE, | 809 | .mapbase = DAVINCI_UART1_BASE, |
| 804 | .irq = IRQ_UARTINT1, | 810 | .irq = IRQ_UARTINT1, |
| 805 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 811 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -808,6 +814,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { | |||
| 808 | .regshift = 2, | 814 | .regshift = 2, |
| 809 | }, | 815 | }, |
| 810 | { | 816 | { |
| 817 | .flags = 0, | ||
| 818 | } | ||
| 819 | }; | ||
| 820 | static struct plat_serial8250_port dm646x_serial2_platform_data[] = { | ||
| 821 | { | ||
| 811 | .mapbase = DAVINCI_UART2_BASE, | 822 | .mapbase = DAVINCI_UART2_BASE, |
| 812 | .irq = IRQ_DM646X_UARTINT2, | 823 | .irq = IRQ_DM646X_UARTINT2, |
| 813 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | 824 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
| @@ -816,16 +827,34 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { | |||
| 816 | .regshift = 2, | 827 | .regshift = 2, |
| 817 | }, | 828 | }, |
| 818 | { | 829 | { |
| 819 | .flags = 0 | 830 | .flags = 0, |
| 820 | }, | 831 | } |
| 821 | }; | 832 | }; |
| 822 | 833 | ||
| 823 | static struct platform_device dm646x_serial_device = { | 834 | struct platform_device dm646x_serial_device[] = { |
| 824 | .name = "serial8250", | 835 | { |
| 825 | .id = PLAT8250_DEV_PLATFORM, | 836 | .name = "serial8250", |
| 826 | .dev = { | 837 | .id = PLAT8250_DEV_PLATFORM, |
| 827 | .platform_data = dm646x_serial_platform_data, | 838 | .dev = { |
| 839 | .platform_data = dm646x_serial0_platform_data, | ||
| 840 | } | ||
| 841 | }, | ||
| 842 | { | ||
| 843 | .name = "serial8250", | ||
| 844 | .id = PLAT8250_DEV_PLATFORM1, | ||
| 845 | .dev = { | ||
| 846 | .platform_data = dm646x_serial1_platform_data, | ||
| 847 | } | ||
| 828 | }, | 848 | }, |
| 849 | { | ||
| 850 | .name = "serial8250", | ||
| 851 | .id = PLAT8250_DEV_PLATFORM2, | ||
| 852 | .dev = { | ||
| 853 | .platform_data = dm646x_serial2_platform_data, | ||
| 854 | } | ||
| 855 | }, | ||
| 856 | { | ||
| 857 | } | ||
| 829 | }; | 858 | }; |
| 830 | 859 | ||
| 831 | static struct davinci_soc_info davinci_soc_info_dm646x = { | 860 | static struct davinci_soc_info davinci_soc_info_dm646x = { |
| @@ -849,7 +878,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { | |||
| 849 | .gpio_base = DAVINCI_GPIO_BASE, | 878 | .gpio_base = DAVINCI_GPIO_BASE, |
| 850 | .gpio_num = 43, /* Only 33 usable */ | 879 | .gpio_num = 43, /* Only 33 usable */ |
| 851 | .gpio_irq = IRQ_DM646X_GPIOBNK0, | 880 | .gpio_irq = IRQ_DM646X_GPIOBNK0, |
| 852 | .serial_dev = &dm646x_serial_device, | ||
| 853 | .emac_pdata = &dm646x_emac_pdata, | 881 | .emac_pdata = &dm646x_emac_pdata, |
| 854 | .sram_dma = 0x10010000, | 882 | .sram_dma = 0x10010000, |
| 855 | .sram_len = SZ_32K, | 883 | .sram_len = SZ_32K, |
| @@ -913,8 +941,6 @@ static int __init dm646x_init_devices(void) | |||
| 913 | 941 | ||
| 914 | platform_device_register(&dm646x_mdio_device); | 942 | platform_device_register(&dm646x_mdio_device); |
| 915 | platform_device_register(&dm646x_emac_device); | 943 | platform_device_register(&dm646x_emac_device); |
| 916 | clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev), | ||
| 917 | NULL, &dm646x_emac_device.dev); | ||
| 918 | 944 | ||
| 919 | return 0; | 945 | return 0; |
| 920 | } | 946 | } |
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index cce316b92c06..0b3c169758ed 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h | |||
| @@ -72,7 +72,6 @@ struct davinci_soc_info { | |||
| 72 | unsigned gpio_unbanked; | 72 | unsigned gpio_unbanked; |
| 73 | struct davinci_gpio_controller *gpio_ctlrs; | 73 | struct davinci_gpio_controller *gpio_ctlrs; |
| 74 | int gpio_ctlrs_num; | 74 | int gpio_ctlrs_num; |
| 75 | struct platform_device *serial_dev; | ||
| 76 | struct emac_platform_data *emac_pdata; | 75 | struct emac_platform_data *emac_pdata; |
| 77 | dma_addr_t sram_dma; | 76 | dma_addr_t sram_dma; |
| 78 | unsigned sram_len; | 77 | unsigned sram_len; |
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 7b41a5e9bc31..aae53072c0eb 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
| @@ -111,7 +111,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd); | |||
| 111 | void da8xx_rproc_reserve_cma(void); | 111 | void da8xx_rproc_reserve_cma(void); |
| 112 | int da8xx_register_rproc(void); | 112 | int da8xx_register_rproc(void); |
| 113 | 113 | ||
| 114 | extern struct platform_device da8xx_serial_device; | 114 | extern struct platform_device da8xx_serial_device[]; |
| 115 | extern struct emac_platform_data da8xx_emac_pdata; | 115 | extern struct emac_platform_data da8xx_emac_pdata; |
| 116 | extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; | 116 | extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; |
| 117 | extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; | 117 | extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; |
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 62ad300440f5..52b8571b2e70 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h | |||
| @@ -15,6 +15,8 @@ | |||
| 15 | 15 | ||
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | 17 | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | |||
| 18 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) | 20 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) |
| 19 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) | 21 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) |
| 20 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) | 22 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) |
| @@ -37,13 +39,7 @@ | |||
| 37 | #define UART_DM646X_SCR_TX_WATERMARK 0x08 | 39 | #define UART_DM646X_SCR_TX_WATERMARK 0x08 |
| 38 | 40 | ||
| 39 | #ifndef __ASSEMBLY__ | 41 | #ifndef __ASSEMBLY__ |
| 40 | struct davinci_uart_config { | 42 | extern int davinci_serial_init(struct platform_device *); |
| 41 | /* Bit field of UARTs present; bit 0 --> UART0 */ | ||
| 42 | unsigned int enabled_uarts; | ||
| 43 | }; | ||
| 44 | |||
| 45 | extern int davinci_serial_init(struct davinci_uart_config *); | ||
| 46 | extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate); | ||
| 47 | #endif | 43 | #endif |
| 48 | 44 | ||
| 49 | #endif /* __ASM_ARCH_SERIAL_H */ | 45 | #endif /* __ASM_ARCH_SERIAL_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index 16314c64f755..494fcf5ccfe1 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h | |||
| @@ -42,7 +42,6 @@ | |||
| 42 | #include <mach/serial.h> | 42 | #include <mach/serial.h> |
| 43 | 43 | ||
| 44 | struct tnetv107x_device_info { | 44 | struct tnetv107x_device_info { |
| 45 | struct davinci_uart_config *serial_config; | ||
| 46 | struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ | 45 | struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ |
| 47 | struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ | 46 | struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ |
| 48 | struct matrix_keypad_platform_data *keypad_config; | 47 | struct matrix_keypad_platform_data *keypad_config; |
| @@ -50,7 +49,7 @@ struct tnetv107x_device_info { | |||
| 50 | }; | 49 | }; |
| 51 | 50 | ||
| 52 | extern struct platform_device tnetv107x_wdt_device; | 51 | extern struct platform_device tnetv107x_wdt_device; |
| 53 | extern struct platform_device tnetv107x_serial_device; | 52 | extern struct platform_device tnetv107x_serial_device[]; |
| 54 | 53 | ||
| 55 | extern void tnetv107x_init(void); | 54 | extern void tnetv107x_init(void); |
| 56 | extern void tnetv107x_devices_init(struct tnetv107x_device_info *); | 55 | extern void tnetv107x_devices_init(struct tnetv107x_device_info *); |
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index f2625814c3c9..5e93a734c858 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c | |||
| @@ -70,49 +70,36 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p) | |||
| 70 | UART_DM646X_SCR_TX_WATERMARK); | 70 | UART_DM646X_SCR_TX_WATERMARK); |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | /* Enable UART clock and obtain its rate */ | 73 | int __init davinci_serial_init(struct platform_device *serial_dev) |
| 74 | int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate) | ||
| 75 | { | 74 | { |
| 76 | char name[16]; | 75 | int i, ret = 0; |
| 76 | struct device *dev; | ||
| 77 | struct plat_serial8250_port *p; | ||
| 77 | struct clk *clk; | 78 | struct clk *clk; |
| 78 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 79 | struct device *dev = &soc_info->serial_dev->dev; | ||
| 80 | |||
| 81 | sprintf(name, "uart%d", instance); | ||
| 82 | clk = clk_get(dev, name); | ||
| 83 | if (IS_ERR(clk)) { | ||
| 84 | pr_err("%s:%d: failed to get UART%d clock\n", | ||
| 85 | __func__, __LINE__, instance); | ||
| 86 | return PTR_ERR(clk); | ||
| 87 | } | ||
| 88 | |||
| 89 | clk_prepare_enable(clk); | ||
| 90 | |||
| 91 | if (rate) | ||
| 92 | *rate = clk_get_rate(clk); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | int __init davinci_serial_init(struct davinci_uart_config *info) | ||
| 98 | { | ||
| 99 | int i, ret; | ||
| 100 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 101 | struct device *dev = &soc_info->serial_dev->dev; | ||
| 102 | struct plat_serial8250_port *p = dev->platform_data; | ||
| 103 | 79 | ||
| 104 | /* | 80 | /* |
| 105 | * Make sure the serial ports are muxed on at this point. | 81 | * Make sure the serial ports are muxed on at this point. |
| 106 | * You have to mux them off in device drivers later on if not needed. | 82 | * You have to mux them off in device drivers later on if not needed. |
| 107 | */ | 83 | */ |
| 108 | for (i = 0; p->flags; i++, p++) { | 84 | for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) { |
| 109 | if (!(info->enabled_uarts & (1 << i))) | 85 | dev = &serial_dev[i].dev; |
| 110 | continue; | 86 | p = dev->platform_data; |
| 111 | 87 | ||
| 112 | ret = davinci_serial_setup_clk(i, &p->uartclk); | 88 | ret = platform_device_register(&serial_dev[i]); |
| 113 | if (ret) | 89 | if (ret) |
| 114 | continue; | 90 | continue; |
| 115 | 91 | ||
| 92 | clk = clk_get(dev, NULL); | ||
| 93 | if (IS_ERR(clk)) { | ||
| 94 | pr_err("%s:%d: failed to get UART%d clock\n", | ||
| 95 | __func__, __LINE__, i); | ||
| 96 | continue; | ||
| 97 | } | ||
| 98 | |||
| 99 | clk_prepare_enable(clk); | ||
| 100 | |||
| 101 | p->uartclk = clk_get_rate(clk); | ||
| 102 | |||
| 116 | if (!p->membase && p->mapbase) { | 103 | if (!p->membase && p->mapbase) { |
| 117 | p->membase = ioremap(p->mapbase, SZ_4K); | 104 | p->membase = ioremap(p->mapbase, SZ_4K); |
| 118 | 105 | ||
| @@ -125,6 +112,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info) | |||
| 125 | if (p->membase && p->type != PORT_AR7) | 112 | if (p->membase && p->type != PORT_AR7) |
| 126 | davinci_serial_reset(p); | 113 | davinci_serial_reset(p); |
| 127 | } | 114 | } |
| 128 | 115 | return ret; | |
| 129 | return platform_device_register(soc_info->serial_dev); | ||
| 130 | } | 116 | } |
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 4545667ecd3c..f4d7fbb24b3b 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c | |||
| @@ -264,7 +264,7 @@ static struct clk_lookup clks[] = { | |||
| 264 | CLK(NULL, "clk_chipcfg", &clk_chipcfg), | 264 | CLK(NULL, "clk_chipcfg", &clk_chipcfg), |
| 265 | CLK("tnetv107x-ts.0", NULL, &clk_tsc), | 265 | CLK("tnetv107x-ts.0", NULL, &clk_tsc), |
| 266 | CLK(NULL, "clk_rom", &clk_rom), | 266 | CLK(NULL, "clk_rom", &clk_rom), |
| 267 | CLK(NULL, "uart2", &clk_uart2), | 267 | CLK("serial8250.2", NULL, &clk_uart2), |
| 268 | CLK(NULL, "clk_pktsec", &clk_pktsec), | 268 | CLK(NULL, "clk_pktsec", &clk_pktsec), |
| 269 | CLK("tnetv107x-rng.0", NULL, &clk_rng), | 269 | CLK("tnetv107x-rng.0", NULL, &clk_rng), |
| 270 | CLK("tnetv107x-pka.0", NULL, &clk_pka), | 270 | CLK("tnetv107x-pka.0", NULL, &clk_pka), |
| @@ -274,8 +274,8 @@ static struct clk_lookup clks[] = { | |||
| 274 | CLK(NULL, "clk_gpio", &clk_gpio), | 274 | CLK(NULL, "clk_gpio", &clk_gpio), |
| 275 | CLK(NULL, "clk_mdio", &clk_mdio), | 275 | CLK(NULL, "clk_mdio", &clk_mdio), |
| 276 | CLK("dm6441-mmc.0", NULL, &clk_sdio0), | 276 | CLK("dm6441-mmc.0", NULL, &clk_sdio0), |
| 277 | CLK(NULL, "uart0", &clk_uart0), | 277 | CLK("serial8250.0", NULL, &clk_uart0), |
| 278 | CLK(NULL, "uart1", &clk_uart1), | 278 | CLK("serial8250.1", NULL, &clk_uart1), |
| 279 | CLK(NULL, "timer0", &clk_timer0), | 279 | CLK(NULL, "timer0", &clk_timer0), |
| 280 | CLK(NULL, "timer1", &clk_timer1), | 280 | CLK(NULL, "timer1", &clk_timer1), |
| 281 | CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), | 281 | CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), |
| @@ -757,7 +757,7 @@ static struct davinci_soc_info tnetv107x_soc_info = { | |||
| 757 | .gpio_type = GPIO_TYPE_TNETV107X, | 757 | .gpio_type = GPIO_TYPE_TNETV107X, |
| 758 | .gpio_num = TNETV107X_N_GPIO, | 758 | .gpio_num = TNETV107X_N_GPIO, |
| 759 | .timer_info = &timer_info, | 759 | .timer_info = &timer_info, |
| 760 | .serial_dev = &tnetv107x_serial_device, | 760 | .serial_dev = tnetv107x_serial_device, |
| 761 | }; | 761 | }; |
| 762 | 762 | ||
| 763 | void __init tnetv107x_init(void) | 763 | void __init tnetv107x_init(void) |
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 304f069ebf50..c122bcff9f7c 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
| @@ -27,6 +27,22 @@ | |||
| 27 | #include <plat/time.h> | 27 | #include <plat/time.h> |
| 28 | #include "common.h" | 28 | #include "common.h" |
| 29 | 29 | ||
| 30 | /* These can go away once Dove uses the mvebu-mbus DT binding */ | ||
| 31 | #define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 | ||
| 32 | #define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 | ||
| 33 | #define DOVE_MBUS_PCIE0_IO_TARGET 0x4 | ||
| 34 | #define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 | ||
| 35 | #define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 | ||
| 36 | #define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 | ||
| 37 | #define DOVE_MBUS_PCIE1_IO_TARGET 0x8 | ||
| 38 | #define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 | ||
| 39 | #define DOVE_MBUS_CESA_TARGET 0x3 | ||
| 40 | #define DOVE_MBUS_CESA_ATTR 0x1 | ||
| 41 | #define DOVE_MBUS_BOOTROM_TARGET 0x1 | ||
| 42 | #define DOVE_MBUS_BOOTROM_ATTR 0xfd | ||
| 43 | #define DOVE_MBUS_SCRATCHPAD_TARGET 0xd | ||
| 44 | #define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 | ||
| 45 | |||
| 30 | /***************************************************************************** | 46 | /***************************************************************************** |
| 31 | * I/O Address Mapping | 47 | * I/O Address Mapping |
| 32 | ****************************************************************************/ | 48 | ****************************************************************************/ |
| @@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void) | |||
| 332 | { | 348 | { |
| 333 | /* | 349 | /* |
| 334 | * The PCIe windows will no longer be statically allocated | 350 | * The PCIe windows will no longer be statically allocated |
| 335 | * here once Dove is migrated to the pci-mvebu driver. | 351 | * here once Dove is migrated to the pci-mvebu driver. The |
| 352 | * non-PCIe windows will no longer be created here once Dove | ||
| 353 | * fully moves to DT. | ||
| 336 | */ | 354 | */ |
| 337 | mvebu_mbus_add_window_remap_flags("pcie0.0", | 355 | mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, |
| 356 | DOVE_MBUS_PCIE0_IO_ATTR, | ||
| 338 | DOVE_PCIE0_IO_PHYS_BASE, | 357 | DOVE_PCIE0_IO_PHYS_BASE, |
| 339 | DOVE_PCIE0_IO_SIZE, | 358 | DOVE_PCIE0_IO_SIZE, |
| 340 | DOVE_PCIE0_IO_BUS_BASE, | 359 | DOVE_PCIE0_IO_BUS_BASE); |
| 341 | MVEBU_MBUS_PCI_IO); | 360 | mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, |
| 342 | mvebu_mbus_add_window_remap_flags("pcie1.0", | 361 | DOVE_MBUS_PCIE1_IO_ATTR, |
| 343 | DOVE_PCIE1_IO_PHYS_BASE, | 362 | DOVE_PCIE1_IO_PHYS_BASE, |
| 344 | DOVE_PCIE1_IO_SIZE, | 363 | DOVE_PCIE1_IO_SIZE, |
| 345 | DOVE_PCIE1_IO_BUS_BASE, | 364 | DOVE_PCIE1_IO_BUS_BASE); |
| 346 | MVEBU_MBUS_PCI_IO); | 365 | mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, |
| 347 | mvebu_mbus_add_window_remap_flags("pcie0.0", | 366 | DOVE_MBUS_PCIE0_MEM_ATTR, |
| 348 | DOVE_PCIE0_MEM_PHYS_BASE, | 367 | DOVE_PCIE0_MEM_PHYS_BASE, |
| 349 | DOVE_PCIE0_MEM_SIZE, | 368 | DOVE_PCIE0_MEM_SIZE); |
| 350 | MVEBU_MBUS_NO_REMAP, | 369 | mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, |
| 351 | MVEBU_MBUS_PCI_MEM); | 370 | DOVE_MBUS_PCIE1_MEM_ATTR, |
| 352 | mvebu_mbus_add_window_remap_flags("pcie1.0", | 371 | DOVE_PCIE1_MEM_PHYS_BASE, |
| 353 | DOVE_PCIE1_MEM_PHYS_BASE, | 372 | DOVE_PCIE1_MEM_SIZE); |
| 354 | DOVE_PCIE1_MEM_SIZE, | 373 | mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, |
| 355 | MVEBU_MBUS_NO_REMAP, | 374 | DOVE_MBUS_CESA_ATTR, |
| 356 | MVEBU_MBUS_PCI_MEM); | 375 | DOVE_CESA_PHYS_BASE, |
| 357 | mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, | 376 | DOVE_CESA_SIZE); |
| 358 | DOVE_CESA_SIZE); | 377 | mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, |
| 359 | mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, | 378 | DOVE_MBUS_BOOTROM_ATTR, |
| 360 | DOVE_BOOTROM_SIZE); | 379 | DOVE_BOOTROM_PHYS_BASE, |
| 361 | mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, | 380 | DOVE_BOOTROM_SIZE); |
| 362 | DOVE_SCRATCHPAD_SIZE); | 381 | mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, |
| 382 | DOVE_MBUS_SCRATCHPAD_ATTR, | ||
| 383 | DOVE_SCRATCHPAD_PHYS_BASE, | ||
| 384 | DOVE_SCRATCHPAD_SIZE); | ||
| 363 | } | 385 | } |
| 364 | 386 | ||
| 365 | void __init dove_init(void) | 387 | void __init dove_init(void) |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1303e334c343..29a8af6922a8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | config ARCH_MXC | 1 | config ARCH_MXC |
| 2 | bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 | 2 | bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 |
| 3 | select ARCH_REQUIRE_GPIOLIB | 3 | select ARCH_REQUIRE_GPIOLIB |
| 4 | select ARM_CPU_SUSPEND if PM | ||
| 4 | select ARM_PATCH_PHYS_VIRT | 5 | select ARM_PATCH_PHYS_VIRT |
| 5 | select AUTO_ZRELADDR if !ZBOOT_ROM | 6 | select AUTO_ZRELADDR if !ZBOOT_ROM |
| 6 | select CLKDEV_LOOKUP | 7 | select CLKDEV_LOOKUP |
| @@ -8,6 +9,7 @@ config ARCH_MXC | |||
| 8 | select GENERIC_ALLOCATOR | 9 | select GENERIC_ALLOCATOR |
| 9 | select GENERIC_CLOCKEVENTS | 10 | select GENERIC_CLOCKEVENTS |
| 10 | select GENERIC_IRQ_CHIP | 11 | select GENERIC_IRQ_CHIP |
| 12 | select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 | ||
| 11 | select MULTI_IRQ_HANDLER | 13 | select MULTI_IRQ_HANDLER |
| 12 | select SPARSE_IRQ | 14 | select SPARSE_IRQ |
| 13 | select USE_OF | 15 | select USE_OF |
| @@ -785,7 +787,6 @@ config SOC_IMX6Q | |||
| 785 | bool "i.MX6 Quad/DualLite support" | 787 | bool "i.MX6 Quad/DualLite support" |
| 786 | select ARCH_HAS_CPUFREQ | 788 | select ARCH_HAS_CPUFREQ |
| 787 | select ARCH_HAS_OPP | 789 | select ARCH_HAS_OPP |
| 788 | select ARM_CPU_SUSPEND if PM | ||
| 789 | select ARM_ERRATA_754322 | 790 | select ARM_ERRATA_754322 |
| 790 | select ARM_ERRATA_764369 if SMP | 791 | select ARM_ERRATA_764369 if SMP |
| 791 | select ARM_ERRATA_775420 | 792 | select ARM_ERRATA_775420 |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e20f22d58fd8..5383c589ad71 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -15,7 +15,8 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o | |||
| 15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) | 15 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) |
| 16 | 16 | ||
| 17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ | 17 | obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ |
| 18 | clk-pfd.o clk-busy.o clk.o | 18 | clk-pfd.o clk-busy.o clk.o \ |
| 19 | clk-fixup-div.o clk-fixup-mux.o | ||
| 19 | 20 | ||
| 20 | obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o | 21 | obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o |
| 21 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o | 22 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o |
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 0cfa07dd9aa4..ad3b755abb78 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c | |||
| @@ -66,7 +66,7 @@ void imx_anatop_post_resume(void) | |||
| 66 | imx_anatop_enable_weak2p5(false); | 66 | imx_anatop_enable_weak2p5(false); |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | void imx_anatop_usb_chrg_detect_disable(void) | 69 | static void imx_anatop_usb_chrg_detect_disable(void) |
| 70 | { | 70 | { |
| 71 | regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, | 71 | regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, |
| 72 | BM_ANADIG_USB_CHRG_DETECT_EN_B | 72 | BM_ANADIG_USB_CHRG_DETECT_EN_B |
| @@ -100,4 +100,6 @@ void __init imx_anatop_init(void) | |||
| 100 | pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); | 100 | pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); |
| 101 | return; | 101 | return; |
| 102 | } | 102 | } |
| 103 | |||
| 104 | imx_anatop_usb_chrg_detect_disable(); | ||
| 103 | } | 105 | } |
diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c new file mode 100644 index 000000000000..21db020b1f2d --- /dev/null +++ b/arch/arm/mach-imx/clk-fixup-div.c | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/slab.h> | ||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | #define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw) | ||
| 19 | #define div_mask(d) ((1 << (d->width)) - 1) | ||
| 20 | |||
| 21 | /** | ||
| 22 | * struct clk_fixup_div - imx integer fixup divider clock | ||
| 23 | * @divider: the parent class | ||
| 24 | * @ops: pointer to clk_ops of parent class | ||
| 25 | * @fixup: a hook to fixup the write value | ||
| 26 | * | ||
| 27 | * The imx fixup divider clock is a subclass of basic clk_divider | ||
| 28 | * with an addtional fixup hook. | ||
| 29 | */ | ||
| 30 | struct clk_fixup_div { | ||
| 31 | struct clk_divider divider; | ||
| 32 | const struct clk_ops *ops; | ||
| 33 | void (*fixup)(u32 *val); | ||
| 34 | }; | ||
| 35 | |||
| 36 | static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw) | ||
| 37 | { | ||
| 38 | struct clk_divider *divider = to_clk_div(hw); | ||
| 39 | |||
| 40 | return container_of(divider, struct clk_fixup_div, divider); | ||
| 41 | } | ||
| 42 | |||
| 43 | static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw, | ||
| 44 | unsigned long parent_rate) | ||
| 45 | { | ||
| 46 | struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); | ||
| 47 | |||
| 48 | return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); | ||
| 49 | } | ||
| 50 | |||
| 51 | static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 52 | unsigned long *prate) | ||
| 53 | { | ||
| 54 | struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); | ||
| 55 | |||
| 56 | return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); | ||
| 57 | } | ||
| 58 | |||
| 59 | static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 60 | unsigned long parent_rate) | ||
| 61 | { | ||
| 62 | struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); | ||
| 63 | struct clk_divider *div = to_clk_div(hw); | ||
| 64 | unsigned int divider, value; | ||
| 65 | unsigned long flags = 0; | ||
| 66 | u32 val; | ||
| 67 | |||
| 68 | divider = parent_rate / rate; | ||
| 69 | |||
| 70 | /* Zero based divider */ | ||
| 71 | value = divider - 1; | ||
| 72 | |||
| 73 | if (value > div_mask(div)) | ||
| 74 | value = div_mask(div); | ||
| 75 | |||
| 76 | spin_lock_irqsave(div->lock, flags); | ||
| 77 | |||
| 78 | val = readl(div->reg); | ||
| 79 | val &= ~(div_mask(div) << div->shift); | ||
| 80 | val |= value << div->shift; | ||
| 81 | fixup_div->fixup(&val); | ||
| 82 | writel(val, div->reg); | ||
| 83 | |||
| 84 | spin_unlock_irqrestore(div->lock, flags); | ||
| 85 | |||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | |||
| 89 | static const struct clk_ops clk_fixup_div_ops = { | ||
| 90 | .recalc_rate = clk_fixup_div_recalc_rate, | ||
| 91 | .round_rate = clk_fixup_div_round_rate, | ||
| 92 | .set_rate = clk_fixup_div_set_rate, | ||
| 93 | }; | ||
| 94 | |||
| 95 | struct clk *imx_clk_fixup_divider(const char *name, const char *parent, | ||
| 96 | void __iomem *reg, u8 shift, u8 width, | ||
| 97 | void (*fixup)(u32 *val)) | ||
| 98 | { | ||
| 99 | struct clk_fixup_div *fixup_div; | ||
| 100 | struct clk *clk; | ||
| 101 | struct clk_init_data init; | ||
| 102 | |||
| 103 | if (!fixup) | ||
| 104 | return ERR_PTR(-EINVAL); | ||
| 105 | |||
| 106 | fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL); | ||
| 107 | if (!fixup_div) | ||
| 108 | return ERR_PTR(-ENOMEM); | ||
| 109 | |||
| 110 | init.name = name; | ||
| 111 | init.ops = &clk_fixup_div_ops; | ||
| 112 | init.flags = CLK_SET_RATE_PARENT; | ||
| 113 | init.parent_names = parent ? &parent : NULL; | ||
| 114 | init.num_parents = parent ? 1 : 0; | ||
| 115 | |||
| 116 | fixup_div->divider.reg = reg; | ||
| 117 | fixup_div->divider.shift = shift; | ||
| 118 | fixup_div->divider.width = width; | ||
| 119 | fixup_div->divider.lock = &imx_ccm_lock; | ||
| 120 | fixup_div->divider.hw.init = &init; | ||
| 121 | fixup_div->ops = &clk_divider_ops; | ||
| 122 | fixup_div->fixup = fixup; | ||
| 123 | |||
| 124 | clk = clk_register(NULL, &fixup_div->divider.hw); | ||
| 125 | if (IS_ERR(clk)) | ||
| 126 | kfree(fixup_div); | ||
| 127 | |||
| 128 | return clk; | ||
| 129 | } | ||
diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c new file mode 100644 index 000000000000..deb4b8093b30 --- /dev/null +++ b/arch/arm/mach-imx/clk-fixup-mux.c | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/clk-provider.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <linux/slab.h> | ||
| 16 | #include "clk.h" | ||
| 17 | |||
| 18 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) | ||
| 19 | |||
| 20 | /** | ||
| 21 | * struct clk_fixup_mux - imx integer fixup multiplexer clock | ||
| 22 | * @mux: the parent class | ||
| 23 | * @ops: pointer to clk_ops of parent class | ||
| 24 | * @fixup: a hook to fixup the write value | ||
| 25 | * | ||
| 26 | * The imx fixup multiplexer clock is a subclass of basic clk_mux | ||
| 27 | * with an addtional fixup hook. | ||
| 28 | */ | ||
| 29 | struct clk_fixup_mux { | ||
| 30 | struct clk_mux mux; | ||
| 31 | const struct clk_ops *ops; | ||
| 32 | void (*fixup)(u32 *val); | ||
| 33 | }; | ||
| 34 | |||
| 35 | static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw) | ||
| 36 | { | ||
| 37 | struct clk_mux *mux = to_clk_mux(hw); | ||
| 38 | |||
| 39 | return container_of(mux, struct clk_fixup_mux, mux); | ||
| 40 | } | ||
| 41 | |||
| 42 | static u8 clk_fixup_mux_get_parent(struct clk_hw *hw) | ||
| 43 | { | ||
| 44 | struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); | ||
| 45 | |||
| 46 | return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); | ||
| 47 | } | ||
| 48 | |||
| 49 | static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index) | ||
| 50 | { | ||
| 51 | struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); | ||
| 52 | struct clk_mux *mux = to_clk_mux(hw); | ||
| 53 | unsigned long flags = 0; | ||
| 54 | u32 val; | ||
| 55 | |||
| 56 | spin_lock_irqsave(mux->lock, flags); | ||
| 57 | |||
| 58 | val = readl(mux->reg); | ||
| 59 | val &= ~(mux->mask << mux->shift); | ||
| 60 | val |= index << mux->shift; | ||
| 61 | fixup_mux->fixup(&val); | ||
| 62 | writel(val, mux->reg); | ||
| 63 | |||
| 64 | spin_unlock_irqrestore(mux->lock, flags); | ||
| 65 | |||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | static const struct clk_ops clk_fixup_mux_ops = { | ||
| 70 | .get_parent = clk_fixup_mux_get_parent, | ||
| 71 | .set_parent = clk_fixup_mux_set_parent, | ||
| 72 | }; | ||
| 73 | |||
| 74 | struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, | ||
| 75 | u8 shift, u8 width, const char **parents, | ||
| 76 | int num_parents, void (*fixup)(u32 *val)) | ||
| 77 | { | ||
| 78 | struct clk_fixup_mux *fixup_mux; | ||
| 79 | struct clk *clk; | ||
| 80 | struct clk_init_data init; | ||
| 81 | |||
| 82 | if (!fixup) | ||
| 83 | return ERR_PTR(-EINVAL); | ||
| 84 | |||
| 85 | fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL); | ||
| 86 | if (!fixup_mux) | ||
| 87 | return ERR_PTR(-ENOMEM); | ||
| 88 | |||
| 89 | init.name = name; | ||
| 90 | init.ops = &clk_fixup_mux_ops; | ||
| 91 | init.parent_names = parents; | ||
| 92 | init.num_parents = num_parents; | ||
| 93 | |||
| 94 | fixup_mux->mux.reg = reg; | ||
| 95 | fixup_mux->mux.shift = shift; | ||
| 96 | fixup_mux->mux.mask = BIT(width) - 1; | ||
| 97 | fixup_mux->mux.lock = &imx_ccm_lock; | ||
| 98 | fixup_mux->mux.hw.init = &init; | ||
| 99 | fixup_mux->ops = &clk_mux_ops; | ||
| 100 | fixup_mux->fixup = fixup; | ||
| 101 | |||
| 102 | clk = clk_register(NULL, &fixup_mux->mux.hw); | ||
| 103 | if (IS_ERR(clk)) | ||
| 104 | kfree(fixup_mux); | ||
| 105 | |||
| 106 | return clk; | ||
| 107 | } | ||
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 9afac26fa1cc..1a56a3319997 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
| @@ -119,7 +119,7 @@ enum imx5_clks { | |||
| 119 | srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, | 119 | srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, |
| 120 | spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, | 120 | spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, |
| 121 | spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, | 121 | spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, |
| 122 | clk_max | 122 | ocram, clk_max |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | static struct clk *clk[clk_max]; | 125 | static struct clk *clk[clk_max]; |
| @@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 506 | mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); | 506 | mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); |
| 507 | clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); | 507 | clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); |
| 508 | clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); | 508 | clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); |
| 509 | clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); | ||
| 509 | clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); | 510 | clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); |
| 510 | clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); | 511 | clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); |
| 511 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); | 512 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 86567d980b07..9181a241d3a8 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -206,6 +206,17 @@ static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", | |||
| 206 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", | 206 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
| 207 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", | 207 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", |
| 208 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; | 208 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; |
| 209 | static const char *cko2_sels[] = { | ||
| 210 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", | ||
| 211 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", | ||
| 212 | "usdhc3", "dummy", "arm", "ipu1", | ||
| 213 | "ipu2", "vdo_axi", "osc", "gpu2d_core", | ||
| 214 | "gpu3d_core", "usdhc2", "ssi1", "ssi2", | ||
| 215 | "ssi3", "gpu3d_shader", "vpu_axi", "can_root", | ||
| 216 | "ldb_di0", "ldb_di1", "esai", "eim_slow", | ||
| 217 | "uart_serial", "spdif", "asrc", "hsi_tx", | ||
| 218 | }; | ||
| 219 | static const char *cko_sels[] = { "cko1", "cko2", }; | ||
| 209 | 220 | ||
| 210 | enum mx6q_clks { | 221 | enum mx6q_clks { |
| 211 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | 222 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, |
| @@ -239,7 +250,8 @@ enum mx6q_clks { | |||
| 239 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, | 250 | pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, |
| 240 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, | 251 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, |
| 241 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, | 252 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, |
| 242 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max | 253 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, |
| 254 | spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max | ||
| 243 | }; | 255 | }; |
| 244 | 256 | ||
| 245 | static struct clk *clk[clk_max]; | 257 | static struct clk *clk[clk_max]; |
| @@ -276,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 276 | struct device_node *np; | 288 | struct device_node *np; |
| 277 | void __iomem *base; | 289 | void __iomem *base; |
| 278 | int i, irq; | 290 | int i, irq; |
| 291 | int ret; | ||
| 279 | 292 | ||
| 280 | clk[dummy] = imx_clk_fixed("dummy", 0); | 293 | clk[dummy] = imx_clk_fixed("dummy", 0); |
| 281 | clk[ckil] = imx_obtain_fixed_clock("ckil", 0); | 294 | clk[ckil] = imx_obtain_fixed_clock("ckil", 0); |
| @@ -384,19 +397,21 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 384 | clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); | 397 | clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); |
| 385 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); | 398 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
| 386 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | 399 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); |
| 387 | clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 400 | clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 388 | clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 401 | clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 389 | clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 402 | clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 390 | clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 403 | clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 391 | clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 404 | clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 392 | clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 405 | clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 393 | clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 406 | clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 394 | clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); | 407 | clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); |
| 395 | clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); | 408 | clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); |
| 396 | clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels)); | 409 | clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); |
| 397 | clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); | 410 | clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
| 398 | clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | 411 | clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); |
| 399 | clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | 412 | clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); |
| 413 | clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); | ||
| 414 | clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); | ||
| 400 | 415 | ||
| 401 | /* name reg shift width busy: reg, shift parent_names num_parents */ | 416 | /* name reg shift width busy: reg, shift parent_names num_parents */ |
| 402 | clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | 417 | clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); |
| @@ -406,7 +421,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 406 | clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); | 421 | clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); |
| 407 | clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | 422 | clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); |
| 408 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | 423 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); |
| 409 | clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); | 424 | clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
| 410 | clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); | 425 | clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); |
| 411 | clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | 426 | clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); |
| 412 | clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | 427 | clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); |
| @@ -442,10 +457,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 442 | clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | 457 | clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); |
| 443 | clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | 458 | clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); |
| 444 | clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | 459 | clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); |
| 445 | clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); | 460 | clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
| 446 | clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); | 461 | clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); |
| 447 | clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); | 462 | clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); |
| 448 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | 463 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); |
| 464 | clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); | ||
| 449 | 465 | ||
| 450 | /* name parent_name reg shift width busy: reg, shift */ | 466 | /* name parent_name reg shift width busy: reg, shift */ |
| 451 | clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); | 467 | clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); |
| @@ -486,6 +502,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 486 | clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); | 502 | clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); |
| 487 | clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); | 503 | clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); |
| 488 | clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); | 504 | clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); |
| 505 | clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); | ||
| 489 | clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); | 506 | clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); |
| 490 | clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | 507 | clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); |
| 491 | clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | 508 | clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); |
| @@ -521,6 +538,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 521 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); | 538 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); |
| 522 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); | 539 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); |
| 523 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | 540 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
| 541 | clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); | ||
| 524 | clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); | 542 | clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); |
| 525 | clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); | 543 | clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); |
| 526 | clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); | 544 | clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); |
| @@ -535,6 +553,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 535 | clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); | 553 | clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); |
| 536 | clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | 554 | clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); |
| 537 | clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); | 555 | clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); |
| 556 | clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); | ||
| 538 | 557 | ||
| 539 | for (i = 0; i < ARRAY_SIZE(clk); i++) | 558 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
| 540 | if (IS_ERR(clk[i])) | 559 | if (IS_ERR(clk[i])) |
| @@ -554,7 +573,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 554 | clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); | 573 | clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); |
| 555 | clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); | 574 | clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); |
| 556 | 575 | ||
| 557 | if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { | 576 | if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { |
| 558 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); | 577 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); |
| 559 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); | 578 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); |
| 560 | } | 579 | } |
| @@ -574,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 574 | clk_prepare_enable(clk[usbphy2_gate]); | 593 | clk_prepare_enable(clk[usbphy2_gate]); |
| 575 | } | 594 | } |
| 576 | 595 | ||
| 596 | /* | ||
| 597 | * Let's initially set up CLKO with OSC24M, since this configuration | ||
| 598 | * is widely used by imx6q board designs to clock audio codec. | ||
| 599 | */ | ||
| 600 | ret = clk_set_parent(clk[cko2_sel], clk[osc]); | ||
| 601 | if (!ret) | ||
| 602 | ret = clk_set_parent(clk[cko], clk[cko2]); | ||
| 603 | if (ret) | ||
| 604 | pr_warn("failed to set up CLKO: %d\n", ret); | ||
| 605 | |||
| 577 | /* Set initial power mode */ | 606 | /* Set initial power mode */ |
| 578 | imx6q_set_lpm(WAIT_CLOCKED); | 607 | imx6q_set_lpm(WAIT_CLOCKED); |
| 579 | 608 | ||
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index a307ac22dffe..a5c3c5d21aee 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c | |||
| @@ -138,14 +138,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
| 138 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | 138 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
| 139 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); | 139 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); |
| 140 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); | 140 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); |
| 141 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 141 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 142 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 142 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 143 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 143 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 144 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | 144 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 145 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 145 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 146 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 146 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 147 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | 147 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 148 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); | 148 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); |
| 149 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); | 149 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); |
| 150 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); | 150 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); |
| 151 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); | 151 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); |
| @@ -179,14 +179,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
| 179 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | 179 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); |
| 180 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | 180 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); |
| 181 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | 181 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); |
| 182 | clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); | 182 | clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
| 183 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); | 183 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); |
| 184 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); | 184 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); |
| 185 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); | 185 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); |
| 186 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); | 186 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); |
| 187 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); | 187 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); |
| 188 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); | 188 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); |
| 189 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); | 189 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
| 190 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); | 190 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); |
| 191 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); | 191 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); |
| 192 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); | 192 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); |
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index a9fad5f8d340..f6640b6a7b31 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c | |||
| @@ -48,7 +48,7 @@ struct clk_pllv3 { | |||
| 48 | static int clk_pllv3_prepare(struct clk_hw *hw) | 48 | static int clk_pllv3_prepare(struct clk_hw *hw) |
| 49 | { | 49 | { |
| 50 | struct clk_pllv3 *pll = to_clk_pllv3(hw); | 50 | struct clk_pllv3 *pll = to_clk_pllv3(hw); |
| 51 | unsigned long timeout = jiffies + msecs_to_jiffies(10); | 51 | unsigned long timeout; |
| 52 | u32 val; | 52 | u32 val; |
| 53 | 53 | ||
| 54 | val = readl_relaxed(pll->base); | 54 | val = readl_relaxed(pll->base); |
| @@ -59,12 +59,19 @@ static int clk_pllv3_prepare(struct clk_hw *hw) | |||
| 59 | val &= ~BM_PLL_POWER; | 59 | val &= ~BM_PLL_POWER; |
| 60 | writel_relaxed(val, pll->base); | 60 | writel_relaxed(val, pll->base); |
| 61 | 61 | ||
| 62 | timeout = jiffies + msecs_to_jiffies(10); | ||
| 62 | /* Wait for PLL to lock */ | 63 | /* Wait for PLL to lock */ |
| 63 | while (!(readl_relaxed(pll->base) & BM_PLL_LOCK)) | 64 | do { |
| 65 | if (readl_relaxed(pll->base) & BM_PLL_LOCK) | ||
| 66 | break; | ||
| 64 | if (time_after(jiffies, timeout)) | 67 | if (time_after(jiffies, timeout)) |
| 65 | return -ETIMEDOUT; | 68 | break; |
| 69 | } while (1); | ||
| 66 | 70 | ||
| 67 | return 0; | 71 | if (readl_relaxed(pll->base) & BM_PLL_LOCK) |
| 72 | return 0; | ||
| 73 | else | ||
| 74 | return -ETIMEDOUT; | ||
| 68 | } | 75 | } |
| 69 | 76 | ||
| 70 | static void clk_pllv3_unprepare(struct clk_hw *hw) | 77 | static void clk_pllv3_unprepare(struct clk_hw *hw) |
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index 55bc80a00666..edc35df7bed4 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c | |||
| @@ -37,3 +37,29 @@ struct clk * __init imx_obtain_fixed_clock( | |||
| 37 | clk = imx_clk_fixed(name, rate); | 37 | clk = imx_clk_fixed(name, rate); |
| 38 | return clk; | 38 | return clk; |
| 39 | } | 39 | } |
| 40 | |||
| 41 | /* | ||
| 42 | * This fixups the register CCM_CSCMR1 write value. | ||
| 43 | * The write/read/divider values of the aclk_podf field | ||
| 44 | * of that register have the relationship described by | ||
| 45 | * the following table: | ||
| 46 | * | ||
| 47 | * write value read value divider | ||
| 48 | * 3b'000 3b'110 7 | ||
| 49 | * 3b'001 3b'111 8 | ||
| 50 | * 3b'010 3b'100 5 | ||
| 51 | * 3b'011 3b'101 6 | ||
| 52 | * 3b'100 3b'010 3 | ||
| 53 | * 3b'101 3b'011 4 | ||
| 54 | * 3b'110 3b'000 1 | ||
| 55 | * 3b'111 3b'001 2(default) | ||
| 56 | * | ||
| 57 | * That's why we do the xor operation below. | ||
| 58 | */ | ||
| 59 | #define CSCMR1_FIXUP 0x00600000 | ||
| 60 | |||
| 61 | void imx_cscmr1_fixup(u32 *val) | ||
| 62 | { | ||
| 63 | *val ^= CSCMR1_FIXUP; | ||
| 64 | return; | ||
| 65 | } | ||
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 0e4e8bb261b9..3451f1f8ba1f 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h | |||
| @@ -6,6 +6,8 @@ | |||
| 6 | 6 | ||
| 7 | extern spinlock_t imx_ccm_lock; | 7 | extern spinlock_t imx_ccm_lock; |
| 8 | 8 | ||
| 9 | extern void imx_cscmr1_fixup(u32 *val); | ||
| 10 | |||
| 9 | struct clk *imx_clk_pllv1(const char *name, const char *parent, | 11 | struct clk *imx_clk_pllv1(const char *name, const char *parent, |
| 10 | void __iomem *base); | 12 | void __iomem *base); |
| 11 | 13 | ||
| @@ -49,6 +51,14 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, | |||
| 49 | u8 width, void __iomem *busy_reg, u8 busy_shift, | 51 | u8 width, void __iomem *busy_reg, u8 busy_shift, |
| 50 | const char **parent_names, int num_parents); | 52 | const char **parent_names, int num_parents); |
| 51 | 53 | ||
| 54 | struct clk *imx_clk_fixup_divider(const char *name, const char *parent, | ||
| 55 | void __iomem *reg, u8 shift, u8 width, | ||
| 56 | void (*fixup)(u32 *val)); | ||
| 57 | |||
| 58 | struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, | ||
| 59 | u8 shift, u8 width, const char **parents, | ||
| 60 | int num_parents, void (*fixup)(u32 *val)); | ||
| 61 | |||
| 52 | static inline struct clk *imx_clk_fixed(const char *name, int rate) | 62 | static inline struct clk *imx_clk_fixed(const char *name, int rate) |
| 53 | { | 63 | { |
| 54 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | 64 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); |
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index cb6c838b63ed..4517fd760bfc 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h | |||
| @@ -137,7 +137,6 @@ extern void imx_gpc_restore_all(void); | |||
| 137 | extern void imx_anatop_init(void); | 137 | extern void imx_anatop_init(void); |
| 138 | extern void imx_anatop_pre_suspend(void); | 138 | extern void imx_anatop_pre_suspend(void); |
| 139 | extern void imx_anatop_post_resume(void); | 139 | extern void imx_anatop_post_resume(void); |
| 140 | extern void imx_anatop_usb_chrg_detect_disable(void); | ||
| 141 | extern u32 imx_anatop_get_digprog(void); | 140 | extern u32 imx_anatop_get_digprog(void); |
| 142 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | 141 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); |
| 143 | extern void imx6q_set_chicken_bit(void); | 142 | extern void imx6q_set_chicken_bit(void); |
| @@ -147,12 +146,10 @@ extern int imx_cpu_kill(unsigned int cpu); | |||
| 147 | 146 | ||
| 148 | #ifdef CONFIG_PM | 147 | #ifdef CONFIG_PM |
| 149 | extern void imx6q_pm_init(void); | 148 | extern void imx6q_pm_init(void); |
| 150 | extern void imx51_pm_init(void); | 149 | extern void imx5_pm_init(void); |
| 151 | extern void imx53_pm_init(void); | ||
| 152 | #else | 150 | #else |
| 153 | static inline void imx6q_pm_init(void) {} | 151 | static inline void imx6q_pm_init(void) {} |
| 154 | static inline void imx51_pm_init(void) {} | 152 | static inline void imx5_pm_init(void) {} |
| 155 | static inline void imx53_pm_init(void) {} | ||
| 156 | #endif | 153 | #endif |
| 157 | 154 | ||
| 158 | #ifdef CONFIG_NEON | 155 | #ifdef CONFIG_NEON |
| @@ -161,6 +158,12 @@ extern int mx51_neon_fixup(void); | |||
| 161 | static inline int mx51_neon_fixup(void) { return 0; } | 158 | static inline int mx51_neon_fixup(void) { return 0; } |
| 162 | #endif | 159 | #endif |
| 163 | 160 | ||
| 161 | #ifdef CONFIG_CACHE_L2X0 | ||
| 162 | extern void imx_init_l2cache(void); | ||
| 163 | #else | ||
| 164 | static inline void imx_init_l2cache(void) {} | ||
| 165 | #endif | ||
| 166 | |||
| 164 | extern struct smp_operations imx_smp_ops; | 167 | extern struct smp_operations imx_smp_ops; |
| 165 | 168 | ||
| 166 | #endif | 169 | #endif |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index a02f275a198d..85a1b51346c8 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <linux/regmap.h> | 31 | #include <linux/regmap.h> |
| 32 | #include <linux/micrel_phy.h> | 32 | #include <linux/micrel_phy.h> |
| 33 | #include <linux/mfd/syscon.h> | 33 | #include <linux/mfd/syscon.h> |
| 34 | #include <asm/hardware/cache-l2x0.h> | 34 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
| 35 | #include <asm/mach/arch.h> | 35 | #include <asm/mach/arch.h> |
| 36 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
| 37 | #include <asm/system_misc.h> | 37 | #include <asm/system_misc.h> |
| @@ -103,87 +103,77 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev) | |||
| 103 | { | 103 | { |
| 104 | if (IS_BUILTIN(CONFIG_PHYLIB)) { | 104 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
| 105 | /* min rx data delay */ | 105 | /* min rx data delay */ |
| 106 | phy_write(phydev, 0x0b, 0x8105); | 106 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
| 107 | phy_write(phydev, 0x0c, 0x0000); | 107 | 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); |
| 108 | phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); | ||
| 108 | 109 | ||
| 109 | /* max rx/tx clock delay, min rx/tx control delay */ | 110 | /* max rx/tx clock delay, min rx/tx control delay */ |
| 110 | phy_write(phydev, 0x0b, 0x8104); | 111 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
| 111 | phy_write(phydev, 0x0c, 0xf0f0); | 112 | 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); |
| 112 | phy_write(phydev, 0x0b, 0x104); | 113 | phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); |
| 114 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, | ||
| 115 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); | ||
| 113 | } | 116 | } |
| 114 | 117 | ||
| 115 | return 0; | 118 | return 0; |
| 116 | } | 119 | } |
| 117 | 120 | ||
| 118 | static void __init imx6q_sabrelite_cko1_setup(void) | 121 | static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) |
| 119 | { | 122 | { |
| 120 | struct clk *cko1_sel, *ahb, *cko1; | 123 | phy_write(dev, 0x0d, device); |
| 121 | unsigned long rate; | 124 | phy_write(dev, 0x0e, reg); |
| 122 | 125 | phy_write(dev, 0x0d, (1 << 14) | device); | |
| 123 | cko1_sel = clk_get_sys(NULL, "cko1_sel"); | 126 | phy_write(dev, 0x0e, val); |
| 124 | ahb = clk_get_sys(NULL, "ahb"); | ||
| 125 | cko1 = clk_get_sys(NULL, "cko1"); | ||
| 126 | if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) { | ||
| 127 | pr_err("cko1 setup failed!\n"); | ||
| 128 | goto put_clk; | ||
| 129 | } | ||
| 130 | clk_set_parent(cko1_sel, ahb); | ||
| 131 | rate = clk_round_rate(cko1, 16000000); | ||
| 132 | clk_set_rate(cko1, rate); | ||
| 133 | put_clk: | ||
| 134 | if (!IS_ERR(cko1_sel)) | ||
| 135 | clk_put(cko1_sel); | ||
| 136 | if (!IS_ERR(ahb)) | ||
| 137 | clk_put(ahb); | ||
| 138 | if (!IS_ERR(cko1)) | ||
| 139 | clk_put(cko1); | ||
| 140 | } | 127 | } |
| 141 | 128 | ||
| 142 | static void __init imx6q_sabrelite_init(void) | 129 | static int ksz9031rn_phy_fixup(struct phy_device *dev) |
| 143 | { | 130 | { |
| 144 | if (IS_BUILTIN(CONFIG_PHYLIB)) | 131 | /* |
| 145 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, | 132 | * min rx data delay, max rx/tx clock delay, |
| 146 | ksz9021rn_phy_fixup); | 133 | * min rx/tx control delay |
| 147 | imx6q_sabrelite_cko1_setup(); | 134 | */ |
| 135 | mmd_write_reg(dev, 2, 4, 0); | ||
| 136 | mmd_write_reg(dev, 2, 5, 0); | ||
| 137 | mmd_write_reg(dev, 2, 8, 0x003ff); | ||
| 138 | |||
| 139 | return 0; | ||
| 148 | } | 140 | } |
| 149 | 141 | ||
| 150 | static void __init imx6q_sabresd_cko1_setup(void) | 142 | static int ar8031_phy_fixup(struct phy_device *dev) |
| 151 | { | 143 | { |
| 152 | struct clk *cko1_sel, *pll4, *pll4_post, *cko1; | 144 | u16 val; |
| 153 | unsigned long rate; | 145 | |
| 154 | 146 | /* To enable AR8031 output a 125MHz clk from CLK_25M */ | |
| 155 | cko1_sel = clk_get_sys(NULL, "cko1_sel"); | 147 | phy_write(dev, 0xd, 0x7); |
| 156 | pll4 = clk_get_sys(NULL, "pll4_audio"); | 148 | phy_write(dev, 0xe, 0x8016); |
| 157 | pll4_post = clk_get_sys(NULL, "pll4_post_div"); | 149 | phy_write(dev, 0xd, 0x4007); |
| 158 | cko1 = clk_get_sys(NULL, "cko1"); | 150 | |
| 159 | if (IS_ERR(cko1_sel) || IS_ERR(pll4) | 151 | val = phy_read(dev, 0xe); |
| 160 | || IS_ERR(pll4_post) || IS_ERR(cko1)) { | 152 | val &= 0xffe3; |
| 161 | pr_err("cko1 setup failed!\n"); | 153 | val |= 0x18; |
| 162 | goto put_clk; | 154 | phy_write(dev, 0xe, val); |
| 163 | } | 155 | |
| 164 | /* | 156 | /* introduce tx clock delay */ |
| 165 | * Setting pll4 at 768MHz (24MHz * 32) | 157 | phy_write(dev, 0x1d, 0x5); |
| 166 | * So its child clock can get 24MHz easily | 158 | val = phy_read(dev, 0x1e); |
| 167 | */ | 159 | val |= 0x0100; |
| 168 | clk_set_rate(pll4, 768000000); | 160 | phy_write(dev, 0x1e, val); |
| 169 | 161 | ||
| 170 | clk_set_parent(cko1_sel, pll4_post); | 162 | return 0; |
| 171 | rate = clk_round_rate(cko1, 24000000); | ||
| 172 | clk_set_rate(cko1, rate); | ||
| 173 | put_clk: | ||
| 174 | if (!IS_ERR(cko1_sel)) | ||
| 175 | clk_put(cko1_sel); | ||
| 176 | if (!IS_ERR(pll4_post)) | ||
| 177 | clk_put(pll4_post); | ||
| 178 | if (!IS_ERR(pll4)) | ||
| 179 | clk_put(pll4); | ||
| 180 | if (!IS_ERR(cko1)) | ||
| 181 | clk_put(cko1); | ||
| 182 | } | 163 | } |
| 183 | 164 | ||
| 184 | static void __init imx6q_sabresd_init(void) | 165 | #define PHY_ID_AR8031 0x004dd074 |
| 166 | |||
| 167 | static void __init imx6q_enet_phy_init(void) | ||
| 185 | { | 168 | { |
| 186 | imx6q_sabresd_cko1_setup(); | 169 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
| 170 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, | ||
| 171 | ksz9021rn_phy_fixup); | ||
| 172 | phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, | ||
| 173 | ksz9031rn_phy_fixup); | ||
| 174 | phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, | ||
| 175 | ar8031_phy_fixup); | ||
| 176 | } | ||
| 187 | } | 177 | } |
| 188 | 178 | ||
| 189 | static void __init imx6q_1588_init(void) | 179 | static void __init imx6q_1588_init(void) |
| @@ -192,29 +182,22 @@ static void __init imx6q_1588_init(void) | |||
| 192 | 182 | ||
| 193 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | 183 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
| 194 | if (!IS_ERR(gpr)) | 184 | if (!IS_ERR(gpr)) |
| 195 | regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); | 185 | regmap_update_bits(gpr, IOMUXC_GPR1, |
| 186 | IMX6Q_GPR1_ENET_CLK_SEL_MASK, | ||
| 187 | IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); | ||
| 196 | else | 188 | else |
| 197 | pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); | 189 | pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); |
| 198 | 190 | ||
| 199 | } | 191 | } |
| 200 | static void __init imx6q_usb_init(void) | ||
| 201 | { | ||
| 202 | imx_anatop_usb_chrg_detect_disable(); | ||
| 203 | } | ||
| 204 | 192 | ||
| 205 | static void __init imx6q_init_machine(void) | 193 | static void __init imx6q_init_machine(void) |
| 206 | { | 194 | { |
| 207 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) | 195 | imx6q_enet_phy_init(); |
| 208 | imx6q_sabrelite_init(); | ||
| 209 | else if (of_machine_is_compatible("fsl,imx6q-sabresd") || | ||
| 210 | of_machine_is_compatible("fsl,imx6dl-sabresd")) | ||
| 211 | imx6q_sabresd_init(); | ||
| 212 | 196 | ||
| 213 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 197 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 214 | 198 | ||
| 215 | imx_anatop_init(); | 199 | imx_anatop_init(); |
| 216 | imx6q_pm_init(); | 200 | imx6q_pm_init(); |
| 217 | imx6q_usb_init(); | ||
| 218 | imx6q_1588_init(); | 201 | imx6q_1588_init(); |
| 219 | } | 202 | } |
| 220 | 203 | ||
| @@ -296,44 +279,10 @@ static void __init imx6q_map_io(void) | |||
| 296 | imx_scu_map_io(); | 279 | imx_scu_map_io(); |
| 297 | } | 280 | } |
| 298 | 281 | ||
| 299 | #ifdef CONFIG_CACHE_L2X0 | ||
| 300 | static void __init imx6q_init_l2cache(void) | ||
| 301 | { | ||
| 302 | void __iomem *l2x0_base; | ||
| 303 | struct device_node *np; | ||
| 304 | unsigned int val; | ||
| 305 | |||
| 306 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); | ||
| 307 | if (!np) | ||
| 308 | goto out; | ||
| 309 | |||
| 310 | l2x0_base = of_iomap(np, 0); | ||
| 311 | if (!l2x0_base) { | ||
| 312 | of_node_put(np); | ||
| 313 | goto out; | ||
| 314 | } | ||
| 315 | |||
| 316 | /* Configure the L2 PREFETCH and POWER registers */ | ||
| 317 | val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); | ||
| 318 | val |= 0x70800000; | ||
| 319 | writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); | ||
| 320 | val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; | ||
| 321 | writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); | ||
| 322 | |||
| 323 | iounmap(l2x0_base); | ||
| 324 | of_node_put(np); | ||
| 325 | |||
| 326 | out: | ||
| 327 | l2x0_of_init(0, ~0UL); | ||
| 328 | } | ||
| 329 | #else | ||
| 330 | static inline void imx6q_init_l2cache(void) {} | ||
| 331 | #endif | ||
| 332 | |||
| 333 | static void __init imx6q_init_irq(void) | 282 | static void __init imx6q_init_irq(void) |
| 334 | { | 283 | { |
| 335 | imx6q_init_revision(); | 284 | imx6q_init_revision(); |
| 336 | imx6q_init_l2cache(); | 285 | imx_init_l2cache(); |
| 337 | imx_src_init(); | 286 | imx_src_init(); |
| 338 | imx_gpc_init(); | 287 | imx_gpc_init(); |
| 339 | irqchip_init(); | 288 | irqchip_init(); |
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 132db2609507..0d75dc54f715 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | #include <linux/irqchip.h> | 11 | #include <linux/irqchip.h> |
| 12 | #include <linux/of.h> | 12 | #include <linux/of.h> |
| 13 | #include <linux/of_platform.h> | 13 | #include <linux/of_platform.h> |
| 14 | #include <asm/hardware/cache-l2x0.h> | ||
| 15 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
| 17 | 16 | ||
| @@ -26,7 +25,7 @@ static void __init imx6sl_init_machine(void) | |||
| 26 | 25 | ||
| 27 | static void __init imx6sl_init_irq(void) | 26 | static void __init imx6sl_init_irq(void) |
| 28 | { | 27 | { |
| 29 | l2x0_of_init(0, ~0UL); | 28 | imx_init_l2cache(); |
| 30 | imx_src_init(); | 29 | imx_src_init(); |
| 31 | imx_gpc_init(); | 30 | imx_gpc_init(); |
| 32 | irqchip_init(); | 31 | irqchip_init(); |
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index cf193d87274a..a8229b7f10bf 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
| @@ -153,10 +153,10 @@ void __init imx51_soc_init(void) | |||
| 153 | void __init imx51_init_late(void) | 153 | void __init imx51_init_late(void) |
| 154 | { | 154 | { |
| 155 | mx51_neon_fixup(); | 155 | mx51_neon_fixup(); |
| 156 | imx51_pm_init(); | 156 | imx5_pm_init(); |
| 157 | } | 157 | } |
| 158 | 158 | ||
| 159 | void __init imx53_init_late(void) | 159 | void __init imx53_init_late(void) |
| 160 | { | 160 | { |
| 161 | imx53_pm_init(); | 161 | imx5_pm_init(); |
| 162 | } | 162 | } |
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 82e79c658eb2..58aeaf5baaf6 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c | |||
| @@ -169,14 +169,9 @@ static int __init imx5_pm_common_init(void) | |||
| 169 | return imx5_cpuidle_init(); | 169 | return imx5_cpuidle_init(); |
| 170 | } | 170 | } |
| 171 | 171 | ||
| 172 | void __init imx51_pm_init(void) | 172 | void __init imx5_pm_init(void) |
| 173 | { | 173 | { |
| 174 | int ret = imx5_pm_common_init(); | 174 | int ret = imx5_pm_common_init(); |
| 175 | if (!ret) | 175 | if (!ret) |
| 176 | suspend_set_ops(&mx5_suspend_ops); | 176 | suspend_set_ops(&mx5_suspend_ops); |
| 177 | } | 177 | } |
| 178 | |||
| 179 | void __init imx53_pm_init(void) | ||
| 180 | { | ||
| 181 | imx5_pm_common_init(); | ||
| 182 | } | ||
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 6fe81bb4d3c9..64ff37ea72b1 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/system_misc.h> | 27 | #include <asm/system_misc.h> |
| 28 | #include <asm/proc-fns.h> | 28 | #include <asm/proc-fns.h> |
| 29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 30 | #include <asm/hardware/cache-l2x0.h> | ||
| 30 | 31 | ||
| 31 | #include "common.h" | 32 | #include "common.h" |
| 32 | #include "hardware.h" | 33 | #include "hardware.h" |
| @@ -95,3 +96,35 @@ void __init mxc_arch_reset_init_dt(void) | |||
| 95 | 96 | ||
| 96 | clk_prepare(wdog_clk); | 97 | clk_prepare(wdog_clk); |
| 97 | } | 98 | } |
| 99 | |||
| 100 | #ifdef CONFIG_CACHE_L2X0 | ||
| 101 | void __init imx_init_l2cache(void) | ||
| 102 | { | ||
| 103 | void __iomem *l2x0_base; | ||
| 104 | struct device_node *np; | ||
| 105 | unsigned int val; | ||
| 106 | |||
| 107 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); | ||
| 108 | if (!np) | ||
| 109 | goto out; | ||
| 110 | |||
| 111 | l2x0_base = of_iomap(np, 0); | ||
| 112 | if (!l2x0_base) { | ||
| 113 | of_node_put(np); | ||
| 114 | goto out; | ||
| 115 | } | ||
| 116 | |||
| 117 | /* Configure the L2 PREFETCH and POWER registers */ | ||
| 118 | val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); | ||
| 119 | val |= 0x70800000; | ||
| 120 | writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); | ||
| 121 | val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; | ||
| 122 | writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); | ||
| 123 | |||
| 124 | iounmap(l2x0_base); | ||
| 125 | of_node_put(np); | ||
| 126 | |||
| 127 | out: | ||
| 128 | l2x0_of_init(0, ~0UL); | ||
| 129 | } | ||
| 130 | #endif | ||
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 6e122ed3282f..682b7ac8deb8 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c | |||
| @@ -87,6 +87,7 @@ static void __init kirkwood_dt_init(void) | |||
| 87 | */ | 87 | */ |
| 88 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | 88 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); |
| 89 | 89 | ||
| 90 | BUG_ON(mvebu_mbus_dt_init()); | ||
| 90 | kirkwood_setup_wins(); | 91 | kirkwood_setup_wins(); |
| 91 | 92 | ||
| 92 | kirkwood_l2_init(); | 93 | kirkwood_l2_init(); |
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 1663de090984..176761134a66 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -37,6 +37,12 @@ | |||
| 37 | #include <linux/platform_data/dma-mv_xor.h> | 37 | #include <linux/platform_data/dma-mv_xor.h> |
| 38 | #include "common.h" | 38 | #include "common.h" |
| 39 | 39 | ||
| 40 | /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ | ||
| 41 | #define KIRKWOOD_MBUS_NAND_TARGET 0x01 | ||
| 42 | #define KIRKWOOD_MBUS_NAND_ATTR 0x2f | ||
| 43 | #define KIRKWOOD_MBUS_SRAM_TARGET 0x03 | ||
| 44 | #define KIRKWOOD_MBUS_SRAM_ATTR 0x01 | ||
| 45 | |||
| 40 | /***************************************************************************** | 46 | /***************************************************************************** |
| 41 | * I/O Address Mapping | 47 | * I/O Address Mapping |
| 42 | ****************************************************************************/ | 48 | ****************************************************************************/ |
| @@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void) | |||
| 528 | void __init kirkwood_init_early(void) | 534 | void __init kirkwood_init_early(void) |
| 529 | { | 535 | { |
| 530 | orion_time_set_base(TIMER_VIRT_BASE); | 536 | orion_time_set_base(TIMER_VIRT_BASE); |
| 531 | |||
| 532 | mvebu_mbus_init("marvell,kirkwood-mbus", | ||
| 533 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, | ||
| 534 | DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); | ||
| 535 | } | 537 | } |
| 536 | 538 | ||
| 537 | int kirkwood_tclk; | 539 | int kirkwood_tclk; |
| @@ -666,10 +668,14 @@ char * __init kirkwood_id(void) | |||
| 666 | 668 | ||
| 667 | void __init kirkwood_setup_wins(void) | 669 | void __init kirkwood_setup_wins(void) |
| 668 | { | 670 | { |
| 669 | mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, | 671 | mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET, |
| 670 | KIRKWOOD_NAND_MEM_SIZE); | 672 | KIRKWOOD_MBUS_NAND_ATTR, |
| 671 | mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, | 673 | KIRKWOOD_NAND_MEM_PHYS_BASE, |
| 672 | KIRKWOOD_SRAM_SIZE); | 674 | KIRKWOOD_NAND_MEM_SIZE); |
| 675 | mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET, | ||
| 676 | KIRKWOOD_MBUS_SRAM_ATTR, | ||
| 677 | KIRKWOOD_SRAM_PHYS_BASE, | ||
| 678 | KIRKWOOD_SRAM_SIZE); | ||
| 673 | } | 679 | } |
| 674 | 680 | ||
| 675 | void __init kirkwood_l2_init(void) | 681 | void __init kirkwood_l2_init(void) |
| @@ -697,6 +703,10 @@ void __init kirkwood_init(void) | |||
| 697 | */ | 703 | */ |
| 698 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | 704 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); |
| 699 | 705 | ||
| 706 | BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus", | ||
| 707 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, | ||
| 708 | DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ)); | ||
| 709 | |||
| 700 | kirkwood_setup_wins(); | 710 | kirkwood_setup_wins(); |
| 701 | 711 | ||
| 702 | kirkwood_l2_init(); | 712 | kirkwood_l2_init(); |
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index ddcb09f5bdd3..12d86f39f380 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c | |||
| @@ -20,6 +20,16 @@ | |||
| 20 | #include <mach/bridge-regs.h> | 20 | #include <mach/bridge-regs.h> |
| 21 | #include "common.h" | 21 | #include "common.h" |
| 22 | 22 | ||
| 23 | /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ | ||
| 24 | #define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4 | ||
| 25 | #define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8 | ||
| 26 | #define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4 | ||
| 27 | #define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0 | ||
| 28 | #define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4 | ||
| 29 | #define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8 | ||
| 30 | #define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4 | ||
| 31 | #define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0 | ||
| 32 | |||
| 23 | static void kirkwood_enable_pcie_clk(const char *port) | 33 | static void kirkwood_enable_pcie_clk(const char *port) |
| 24 | { | 34 | { |
| 25 | struct clk *clk; | 35 | struct clk *clk; |
| @@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base) | |||
| 254 | 264 | ||
| 255 | void __init kirkwood_pcie_init(unsigned int portmask) | 265 | void __init kirkwood_pcie_init(unsigned int portmask) |
| 256 | { | 266 | { |
| 257 | mvebu_mbus_add_window_remap_flags("pcie0.0", | 267 | mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET, |
| 268 | KIRKWOOD_MBUS_PCIE0_IO_ATTR, | ||
| 258 | KIRKWOOD_PCIE_IO_PHYS_BASE, | 269 | KIRKWOOD_PCIE_IO_PHYS_BASE, |
| 259 | KIRKWOOD_PCIE_IO_SIZE, | 270 | KIRKWOOD_PCIE_IO_SIZE, |
| 260 | KIRKWOOD_PCIE_IO_BUS_BASE, | 271 | KIRKWOOD_PCIE_IO_BUS_BASE); |
| 261 | MVEBU_MBUS_PCI_IO); | 272 | mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET, |
| 262 | mvebu_mbus_add_window_remap_flags("pcie0.0", | 273 | KIRKWOOD_MBUS_PCIE0_MEM_ATTR, |
| 263 | KIRKWOOD_PCIE_MEM_PHYS_BASE, | 274 | KIRKWOOD_PCIE_MEM_PHYS_BASE, |
| 264 | KIRKWOOD_PCIE_MEM_SIZE, | 275 | KIRKWOOD_PCIE_MEM_SIZE); |
| 265 | MVEBU_MBUS_NO_REMAP, | 276 | mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET, |
| 266 | MVEBU_MBUS_PCI_MEM); | 277 | KIRKWOOD_MBUS_PCIE1_IO_ATTR, |
| 267 | mvebu_mbus_add_window_remap_flags("pcie1.0", | ||
| 268 | KIRKWOOD_PCIE1_IO_PHYS_BASE, | 278 | KIRKWOOD_PCIE1_IO_PHYS_BASE, |
| 269 | KIRKWOOD_PCIE1_IO_SIZE, | 279 | KIRKWOOD_PCIE1_IO_SIZE, |
| 270 | KIRKWOOD_PCIE1_IO_BUS_BASE, | 280 | KIRKWOOD_PCIE1_IO_BUS_BASE); |
| 271 | MVEBU_MBUS_PCI_IO); | 281 | mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET, |
| 272 | mvebu_mbus_add_window_remap_flags("pcie1.0", | 282 | KIRKWOOD_MBUS_PCIE1_MEM_ATTR, |
| 273 | KIRKWOOD_PCIE1_MEM_PHYS_BASE, | 283 | KIRKWOOD_PCIE1_MEM_PHYS_BASE, |
| 274 | KIRKWOOD_PCIE1_MEM_SIZE, | 284 | KIRKWOOD_PCIE1_MEM_SIZE); |
| 275 | MVEBU_MBUS_NO_REMAP, | ||
| 276 | MVEBU_MBUS_PCI_MEM); | ||
| 277 | 285 | ||
| 278 | vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; | 286 | vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; |
| 279 | 287 | ||
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index dc26a654c496..445e553f4a28 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c | |||
| @@ -18,6 +18,11 @@ | |||
| 18 | #include <mach/mv78xx0.h> | 18 | #include <mach/mv78xx0.h> |
| 19 | #include "common.h" | 19 | #include "common.h" |
| 20 | 20 | ||
| 21 | #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) | ||
| 22 | #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) | ||
| 23 | #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) | ||
| 24 | #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) | ||
| 25 | |||
| 21 | struct pcie_port { | 26 | struct pcie_port { |
| 22 | u8 maj; | 27 | u8 maj; |
| 23 | u8 min; | 28 | u8 min; |
| @@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void) | |||
| 71 | start = MV78XX0_PCIE_MEM_PHYS_BASE; | 76 | start = MV78XX0_PCIE_MEM_PHYS_BASE; |
| 72 | for (i = 0; i < num_pcie_ports; i++) { | 77 | for (i = 0; i < num_pcie_ports; i++) { |
| 73 | struct pcie_port *pp = pcie_port + i; | 78 | struct pcie_port *pp = pcie_port + i; |
| 74 | char winname[MVEBU_MBUS_MAX_WINNAME_SZ]; | ||
| 75 | 79 | ||
| 76 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | 80 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), |
| 77 | "PCIe %d.%d MEM", pp->maj, pp->min); | 81 | "PCIe %d.%d MEM", pp->maj, pp->min); |
| @@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void) | |||
| 85 | if (request_resource(&iomem_resource, &pp->res)) | 89 | if (request_resource(&iomem_resource, &pp->res)) |
| 86 | panic("can't allocate PCIe MEM sub-space"); | 90 | panic("can't allocate PCIe MEM sub-space"); |
| 87 | 91 | ||
| 88 | snprintf(winname, sizeof(winname), "pcie%d.%d", | 92 | mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min), |
| 89 | pp->maj, pp->min); | 93 | MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min), |
| 90 | 94 | pp->res.start, resource_size(&pp->res)); | |
| 91 | mvebu_mbus_add_window_remap_flags(winname, | 95 | mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min), |
| 92 | pp->res.start, | 96 | MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min), |
| 93 | resource_size(&pp->res), | 97 | i * SZ_64K, SZ_64K, 0); |
| 94 | MVEBU_MBUS_NO_REMAP, | ||
| 95 | MVEBU_MBUS_PCI_MEM); | ||
| 96 | mvebu_mbus_add_window_remap_flags(winname, | ||
| 97 | i * SZ_64K, SZ_64K, | ||
| 98 | 0, MVEBU_MBUS_PCI_IO); | ||
| 99 | } | 98 | } |
| 100 | } | 99 | } |
| 101 | 100 | ||
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 97cbb8021919..829b57306328 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c | |||
| @@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void) | |||
| 34 | debug_ll_io_init(); | 34 | debug_ll_io_init(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | /* | ||
| 38 | * This initialization will be replaced by a DT-based | ||
| 39 | * initialization once the mvebu-mbus driver gains DT support. | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000 | ||
| 43 | #define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 | ||
| 44 | #define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180 | ||
| 45 | #define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 | ||
| 46 | |||
| 47 | static void __init armada_370_xp_mbus_init(void) | ||
| 48 | { | ||
| 49 | char *mbus_soc_name; | ||
| 50 | struct device_node *dn; | ||
| 51 | const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS); | ||
| 52 | const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS); | ||
| 53 | |||
| 54 | if (of_machine_is_compatible("marvell,armada370")) | ||
| 55 | mbus_soc_name = "marvell,armada370-mbus"; | ||
| 56 | else | ||
| 57 | mbus_soc_name = "marvell,armadaxp-mbus"; | ||
| 58 | |||
| 59 | dn = of_find_node_by_name(NULL, "internal-regs"); | ||
| 60 | BUG_ON(!dn); | ||
| 61 | |||
| 62 | mvebu_mbus_init(mbus_soc_name, | ||
| 63 | of_translate_address(dn, &mbus_wins_offs), | ||
| 64 | ARMADA_370_XP_MBUS_WINS_SIZE, | ||
| 65 | of_translate_address(dn, &sdram_wins_offs), | ||
| 66 | ARMADA_370_XP_SDRAM_WINS_SIZE); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void __init armada_370_xp_timer_and_clk_init(void) | 37 | static void __init armada_370_xp_timer_and_clk_init(void) |
| 70 | { | 38 | { |
| 71 | of_clk_init(NULL); | 39 | of_clk_init(NULL); |
| 72 | armada_370_xp_timer_init(); | 40 | armada_370_xp_timer_init(); |
| 73 | coherency_init(); | 41 | coherency_init(); |
| 74 | armada_370_xp_mbus_init(); | 42 | BUG_ON(mvebu_mbus_dt_init()); |
| 75 | #ifdef CONFIG_CACHE_L2X0 | 43 | #ifdef CONFIG_CACHE_L2X0 |
| 76 | l2x0_of_init(0, ~0UL); | 44 | l2x0_of_init(0, ~0UL); |
| 77 | #endif | 45 | #endif |
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index f9c09b75d4d7..ff69c2df298b 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/smp.h> | 21 | #include <linux/smp.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
| 24 | #include <linux/of_address.h> | ||
| 24 | #include <linux/mbus.h> | 25 | #include <linux/mbus.h> |
| 25 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
| 26 | #include <asm/smp_plat.h> | 27 | #include <asm/smp_plat.h> |
| @@ -29,6 +30,9 @@ | |||
| 29 | #include "pmsu.h" | 30 | #include "pmsu.h" |
| 30 | #include "coherency.h" | 31 | #include "coherency.h" |
| 31 | 32 | ||
| 33 | #define AXP_BOOTROM_BASE 0xfff00000 | ||
| 34 | #define AXP_BOOTROM_SIZE 0x100000 | ||
| 35 | |||
| 32 | static struct clk *__init get_cpu_clk(int cpu) | 36 | static struct clk *__init get_cpu_clk(int cpu) |
| 33 | { | 37 | { |
| 34 | struct clk *cpu_clk; | 38 | struct clk *cpu_clk; |
| @@ -92,10 +96,29 @@ static void __init armada_xp_smp_init_cpus(void) | |||
| 92 | 96 | ||
| 93 | void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) | 97 | void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) |
| 94 | { | 98 | { |
| 99 | struct device_node *node; | ||
| 100 | struct resource res; | ||
| 101 | int err; | ||
| 102 | |||
| 95 | set_secondary_cpus_clock(); | 103 | set_secondary_cpus_clock(); |
| 96 | flush_cache_all(); | 104 | flush_cache_all(); |
| 97 | set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); | 105 | set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); |
| 98 | mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); | 106 | |
| 107 | /* | ||
| 108 | * In order to boot the secondary CPUs we need to ensure | ||
| 109 | * the bootROM is mapped at the correct address. | ||
| 110 | */ | ||
| 111 | node = of_find_compatible_node(NULL, NULL, "marvell,bootrom"); | ||
| 112 | if (!node) | ||
| 113 | panic("Cannot find 'marvell,bootrom' compatible node"); | ||
| 114 | |||
| 115 | err = of_address_to_resource(node, 0, &res); | ||
| 116 | if (err < 0) | ||
| 117 | panic("Cannot get 'bootrom' node address"); | ||
| 118 | |||
| 119 | if (res.start != AXP_BOOTROM_BASE || | ||
| 120 | resource_size(&res) != AXP_BOOTROM_SIZE) | ||
| 121 | panic("The address for the BootROM is incorrect"); | ||
| 99 | } | 122 | } |
| 100 | 123 | ||
| 101 | struct smp_operations armada_xp_smp_ops __initdata = { | 124 | struct smp_operations armada_xp_smp_ops __initdata = { |
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 4ce27b536dc9..98f6e2adb53e 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/clk/mxs.h> | 14 | #include <linux/clk/mxs.h> |
| 15 | #include <linux/clkdev.h> | 15 | #include <linux/clkdev.h> |
| 16 | #include <linux/clocksource.h> | 16 | #include <linux/clocksource.h> |
| 17 | #include <linux/clk-provider.h> | ||
| 17 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
| 18 | #include <linux/err.h> | 19 | #include <linux/err.h> |
| 19 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| @@ -61,6 +62,8 @@ | |||
| 61 | static u32 chipid; | 62 | static u32 chipid; |
| 62 | static u32 socid; | 63 | static u32 socid; |
| 63 | 64 | ||
| 65 | static void __iomem *reset_addr; | ||
| 66 | |||
| 64 | static inline void __mxs_setl(u32 mask, void __iomem *reg) | 67 | static inline void __mxs_setl(u32 mask, void __iomem *reg) |
| 65 | { | 68 | { |
| 66 | __raw_writel(mask, reg + MXS_SET_ADDR); | 69 | __raw_writel(mask, reg + MXS_SET_ADDR); |
| @@ -393,12 +396,33 @@ static const char __init *mxs_get_revision(void) | |||
| 393 | u32 rev = mxs_get_cpu_rev(); | 396 | u32 rev = mxs_get_cpu_rev(); |
| 394 | 397 | ||
| 395 | if (rev != MXS_CHIP_REV_UNKNOWN) | 398 | if (rev != MXS_CHIP_REV_UNKNOWN) |
| 396 | return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf, | 399 | return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf, |
| 397 | rev & 0xf); | 400 | rev & 0xf); |
| 398 | else | 401 | else |
| 399 | return kasprintf(GFP_KERNEL, "%s", "Unknown"); | 402 | return kasprintf(GFP_KERNEL, "%s", "Unknown"); |
| 400 | } | 403 | } |
| 401 | 404 | ||
| 405 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 | ||
| 406 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 | ||
| 407 | |||
| 408 | static int __init mxs_restart_init(void) | ||
| 409 | { | ||
| 410 | struct device_node *np; | ||
| 411 | |||
| 412 | np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); | ||
| 413 | reset_addr = of_iomap(np, 0); | ||
| 414 | if (!reset_addr) | ||
| 415 | return -ENODEV; | ||
| 416 | |||
| 417 | if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) | ||
| 418 | reset_addr += MX23_CLKCTRL_RESET_OFFSET; | ||
| 419 | else | ||
| 420 | reset_addr += MX28_CLKCTRL_RESET_OFFSET; | ||
| 421 | of_node_put(np); | ||
| 422 | |||
| 423 | return 0; | ||
| 424 | } | ||
| 425 | |||
| 402 | static void __init mxs_machine_init(void) | 426 | static void __init mxs_machine_init(void) |
| 403 | { | 427 | { |
| 404 | struct device_node *root; | 428 | struct device_node *root; |
| @@ -433,21 +457,18 @@ static void __init mxs_machine_init(void) | |||
| 433 | imx28_evk_init(); | 457 | imx28_evk_init(); |
| 434 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) | 458 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) |
| 435 | apx4devkit_init(); | 459 | apx4devkit_init(); |
| 436 | else if (of_machine_is_compatible("crystalfontz,cfa10037") || | 460 | else if (of_machine_is_compatible("crystalfontz,cfa10036")) |
| 437 | of_machine_is_compatible("crystalfontz,cfa10049") || | ||
| 438 | of_machine_is_compatible("crystalfontz,cfa10055") || | ||
| 439 | of_machine_is_compatible("crystalfontz,cfa10057")) | ||
| 440 | crystalfontz_init(); | 461 | crystalfontz_init(); |
| 441 | 462 | ||
| 442 | of_platform_populate(NULL, of_default_bus_match_table, | 463 | of_platform_populate(NULL, of_default_bus_match_table, |
| 443 | NULL, parent); | 464 | NULL, parent); |
| 444 | 465 | ||
| 466 | mxs_restart_init(); | ||
| 467 | |||
| 445 | if (of_machine_is_compatible("karo,tx28")) | 468 | if (of_machine_is_compatible("karo,tx28")) |
| 446 | tx28_post_init(); | 469 | tx28_post_init(); |
| 447 | } | 470 | } |
| 448 | 471 | ||
| 449 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 | ||
| 450 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 | ||
| 451 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) | 472 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) |
| 452 | 473 | ||
| 453 | /* | 474 | /* |
| @@ -455,28 +476,16 @@ static void __init mxs_machine_init(void) | |||
| 455 | */ | 476 | */ |
| 456 | static void mxs_restart(enum reboot_mode mode, const char *cmd) | 477 | static void mxs_restart(enum reboot_mode mode, const char *cmd) |
| 457 | { | 478 | { |
| 458 | struct device_node *np; | 479 | if (reset_addr) { |
| 459 | void __iomem *reset_addr; | 480 | /* reset the chip */ |
| 481 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); | ||
| 460 | 482 | ||
| 461 | np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); | 483 | pr_err("Failed to assert the chip reset\n"); |
| 462 | reset_addr = of_iomap(np, 0); | ||
| 463 | if (!reset_addr) | ||
| 464 | goto soft; | ||
| 465 | 484 | ||
| 466 | if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) | 485 | /* Delay to allow the serial port to show the message */ |
| 467 | reset_addr += MX23_CLKCTRL_RESET_OFFSET; | 486 | mdelay(50); |
| 468 | else | 487 | } |
| 469 | reset_addr += MX28_CLKCTRL_RESET_OFFSET; | ||
| 470 | |||
| 471 | /* reset the chip */ | ||
| 472 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); | ||
| 473 | |||
| 474 | pr_err("Failed to assert the chip reset\n"); | ||
| 475 | |||
| 476 | /* Delay to allow the serial port to show the message */ | ||
| 477 | mdelay(50); | ||
| 478 | 488 | ||
| 479 | soft: | ||
| 480 | /* We'll take a jump through zero as a poor second */ | 489 | /* We'll take a jump through zero as a poor second */ |
| 481 | soft_restart(0); | 490 | soft_restart(0); |
| 482 | } | 491 | } |
| @@ -487,6 +496,7 @@ static void __init mxs_timer_init(void) | |||
| 487 | mx23_clocks_init(); | 496 | mx23_clocks_init(); |
| 488 | else | 497 | else |
| 489 | mx28_clocks_init(); | 498 | mx28_clocks_init(); |
| 499 | of_clk_init(NULL); | ||
| 490 | clocksource_of_init(); | 500 | clocksource_of_init(); |
| 491 | } | 501 | } |
| 492 | 502 | ||
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c index b2494d2db2c4..0170e99fd70f 100644 --- a/arch/arm/mach-mxs/pm.c +++ b/arch/arm/mach-mxs/pm.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/suspend.h> | 16 | #include <linux/suspend.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include "pm.h" | ||
| 18 | 19 | ||
| 19 | static int mxs_suspend_enter(suspend_state_t state) | 20 | static int mxs_suspend_enter(suspend_state_t state) |
| 20 | { | 21 | { |
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h index 6cf9c1cc2bef..612bd1cc257c 100644 --- a/arch/arm/mach-omap1/include/mach/soc.h +++ b/arch/arm/mach-omap1/include/mach/soc.h | |||
| @@ -195,6 +195,7 @@ IS_OMAP_TYPE(1710, 0x1710) | |||
| 195 | #define cpu_is_omap34xx() 0 | 195 | #define cpu_is_omap34xx() 0 |
| 196 | #define cpu_is_omap44xx() 0 | 196 | #define cpu_is_omap44xx() 0 |
| 197 | #define soc_is_omap54xx() 0 | 197 | #define soc_is_omap54xx() 0 |
| 198 | #define soc_is_dra7xx() 0 | ||
| 198 | #define soc_is_am33xx() 0 | 199 | #define soc_is_am33xx() 0 |
| 199 | #define cpu_class_is_omap1() 1 | 200 | #define cpu_class_is_omap1() 1 |
| 200 | #define cpu_class_is_omap2() 0 | 201 | #define cpu_class_is_omap2() 0 |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 56021c67c89c..b5fb5f7992df 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -117,7 +117,7 @@ config ARCH_OMAP2PLUS_TYPICAL | |||
| 117 | select I2C | 117 | select I2C |
| 118 | select I2C_OMAP | 118 | select I2C_OMAP |
| 119 | select MENELAUS if ARCH_OMAP2 | 119 | select MENELAUS if ARCH_OMAP2 |
| 120 | select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 | 120 | select NEON if CPU_V7 |
| 121 | select PM_RUNTIME | 121 | select PM_RUNTIME |
| 122 | select REGULATOR | 122 | select REGULATOR |
| 123 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 | 123 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
| @@ -131,9 +131,17 @@ config SOC_HAS_OMAP2_SDRC | |||
| 131 | 131 | ||
| 132 | config SOC_HAS_REALTIME_COUNTER | 132 | config SOC_HAS_REALTIME_COUNTER |
| 133 | bool "Real time free running counter" | 133 | bool "Real time free running counter" |
| 134 | depends on SOC_OMAP5 | 134 | depends on SOC_OMAP5 || SOC_DRA7XX |
| 135 | default y | 135 | default y |
| 136 | 136 | ||
| 137 | config SOC_DRA7XX | ||
| 138 | bool "TI DRA7XX" | ||
| 139 | select ARM_ARCH_TIMER | ||
| 140 | select CPU_V7 | ||
| 141 | select ARM_GIC | ||
| 142 | select HAVE_SMP | ||
| 143 | select COMMON_CLK | ||
| 144 | |||
| 137 | comment "OMAP Core Type" | 145 | comment "OMAP Core Type" |
| 138 | depends on ARCH_OMAP2 | 146 | depends on ARCH_OMAP2 |
| 139 | 147 | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d4f671547c37..cc36bfe104fe 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) | |||
| 23 | obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) | 23 | obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) |
| 24 | obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) | 24 | obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) |
| 25 | obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) | 25 | obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) |
| 26 | obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) | ||
| 26 | 27 | ||
| 27 | ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) | 28 | ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) |
| 28 | obj-y += mcbsp.o | 29 | obj-y += mcbsp.o |
| @@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o | |||
| 39 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o | 40 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o |
| 40 | obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o | 41 | obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o |
| 41 | obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) | 42 | obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) |
| 43 | obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) | ||
| 42 | 44 | ||
| 43 | plus_sec := $(call as-instr,.arch_extension sec,+sec) | 45 | plus_sec := $(call as-instr,.arch_extension sec,+sec) |
| 44 | AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) | 46 | AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) |
| @@ -87,6 +89,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o | |||
| 87 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | 89 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o |
| 88 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o | 90 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o |
| 89 | obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o | 91 | obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o |
| 92 | obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o | ||
| 90 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 93 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
| 91 | 94 | ||
| 92 | obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o | 95 | obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o |
| @@ -114,6 +117,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ | |||
| 114 | vc44xx_data.o vp44xx_data.o | 117 | vc44xx_data.o vp44xx_data.o |
| 115 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) | 118 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) |
| 116 | obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) | 119 | obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) |
| 120 | obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) | ||
| 117 | 121 | ||
| 118 | # OMAP voltage domains | 122 | # OMAP voltage domains |
| 119 | voltagedomain-common := voltage.o vc.o vp.o | 123 | voltagedomain-common := voltage.o vc.o vp.o |
| @@ -143,6 +147,7 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o | |||
| 143 | obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) | 147 | obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) |
| 144 | obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) | 148 | obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) |
| 145 | obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o | 149 | obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o |
| 150 | obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) | ||
| 146 | 151 | ||
| 147 | # PRCM clockdomain control | 152 | # PRCM clockdomain control |
| 148 | clockdomain-common += clockdomain.o | 153 | clockdomain-common += clockdomain.o |
| @@ -160,6 +165,7 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o | |||
| 160 | obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) | 165 | obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) |
| 161 | obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) | 166 | obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) |
| 162 | obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o | 167 | obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o |
| 168 | obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) | ||
| 163 | 169 | ||
| 164 | # Clock framework | 170 | # Clock framework |
| 165 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o | 171 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index be5d005ebad2..b89e55ba2c13 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -222,3 +222,21 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") | |||
| 222 | .dt_compat = am43_boards_compat, | 222 | .dt_compat = am43_boards_compat, |
| 223 | MACHINE_END | 223 | MACHINE_END |
| 224 | #endif | 224 | #endif |
| 225 | |||
| 226 | #ifdef CONFIG_SOC_DRA7XX | ||
| 227 | static const char *dra7xx_boards_compat[] __initdata = { | ||
| 228 | "ti,dra7", | ||
| 229 | NULL, | ||
| 230 | }; | ||
| 231 | |||
| 232 | DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") | ||
| 233 | .reserve = omap_reserve, | ||
| 234 | .smp = smp_ops(omap4_smp_ops), | ||
| 235 | .map_io = omap5_map_io, | ||
| 236 | .init_early = dra7xx_init_early, | ||
| 237 | .init_irq = omap_gic_of_init, | ||
| 238 | .init_machine = omap_generic_init, | ||
| 239 | .init_time = omap5_realtime_timer_init, | ||
| 240 | .dt_compat = dra7xx_boards_compat, | ||
| 241 | MACHINE_END | ||
| 242 | #endif | ||
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index dfcc182ecff9..4a5684b96492 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
| @@ -110,6 +110,7 @@ void omap3630_init_late(void); | |||
| 110 | void am35xx_init_late(void); | 110 | void am35xx_init_late(void); |
| 111 | void ti81xx_init_late(void); | 111 | void ti81xx_init_late(void); |
| 112 | int omap2_common_pm_late_init(void); | 112 | int omap2_common_pm_late_init(void); |
| 113 | void dra7xx_init_early(void); | ||
| 113 | 114 | ||
| 114 | #ifdef CONFIG_SOC_BUS | 115 | #ifdef CONFIG_SOC_BUS |
| 115 | void omap_soc_device_init(void); | 116 | void omap_soc_device_init(void); |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 2dc62a25f2c3..0289adcb6efb 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -61,7 +61,7 @@ int omap_type(void) | |||
| 61 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); | 61 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
| 62 | } else if (cpu_is_omap44xx()) { | 62 | } else if (cpu_is_omap44xx()) { |
| 63 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); | 63 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
| 64 | } else if (soc_is_omap54xx()) { | 64 | } else if (soc_is_omap54xx() || soc_is_dra7xx()) { |
| 65 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); | 65 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); |
| 66 | val &= OMAP5_DEVICETYPE_MASK; | 66 | val &= OMAP5_DEVICETYPE_MASK; |
| 67 | val >>= 6; | 67 | val >>= 6; |
| @@ -116,7 +116,7 @@ static u16 tap_prod_id; | |||
| 116 | 116 | ||
| 117 | void omap_get_die_id(struct omap_die_id *odi) | 117 | void omap_get_die_id(struct omap_die_id *odi) |
| 118 | { | 118 | { |
| 119 | if (cpu_is_omap44xx() || soc_is_omap54xx()) { | 119 | if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
| 120 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); | 120 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
| 121 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | 121 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); |
| 122 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | 122 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4a3f06f02859..3656b8009a1c 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { | |||
| 251 | }; | 251 | }; |
| 252 | #endif | 252 | #endif |
| 253 | 253 | ||
| 254 | #ifdef CONFIG_SOC_OMAP5 | 254 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
| 255 | static struct map_desc omap54xx_io_desc[] __initdata = { | 255 | static struct map_desc omap54xx_io_desc[] __initdata = { |
| 256 | { | 256 | { |
| 257 | .virtual = L3_54XX_VIRT, | 257 | .virtual = L3_54XX_VIRT, |
| @@ -333,7 +333,7 @@ void __init omap4_map_io(void) | |||
| 333 | } | 333 | } |
| 334 | #endif | 334 | #endif |
| 335 | 335 | ||
| 336 | #ifdef CONFIG_SOC_OMAP5 | 336 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
| 337 | void __init omap5_map_io(void) | 337 | void __init omap5_map_io(void) |
| 338 | { | 338 | { |
| 339 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | 339 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); |
| @@ -653,6 +653,22 @@ void __init omap5_init_early(void) | |||
| 653 | } | 653 | } |
| 654 | #endif | 654 | #endif |
| 655 | 655 | ||
| 656 | #ifdef CONFIG_SOC_DRA7XX | ||
| 657 | void __init dra7xx_init_early(void) | ||
| 658 | { | ||
| 659 | omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); | ||
| 660 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | ||
| 661 | OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); | ||
| 662 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); | ||
| 663 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), | ||
| 664 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | ||
| 665 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | ||
| 666 | omap_prm_base_init(); | ||
| 667 | omap_cm_base_init(); | ||
| 668 | } | ||
| 669 | #endif | ||
| 670 | |||
| 671 | |||
| 656 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | 672 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
| 657 | struct omap_sdrc_params *sdrc_cs1) | 673 | struct omap_sdrc_params *sdrc_cs1) |
| 658 | { | 674 | { |
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a086ba15868b..2d35c5709408 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h | |||
| @@ -30,4 +30,8 @@ | |||
| 30 | #define OMAP54XX_CTRL_BASE 0x4a002800 | 30 | #define OMAP54XX_CTRL_BASE 0x4a002800 |
| 31 | #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 | 31 | #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 |
| 32 | 32 | ||
| 33 | #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 | ||
| 34 | #define DRA7XX_CTRL_BASE 0x4a003400 | ||
| 35 | #define DRA7XX_TAP_BASE 0x4ae0c000 | ||
| 36 | |||
| 33 | #endif /* __ASM_SOC_OMAP555554XX_H */ | 37 | #endif /* __ASM_SOC_OMAP555554XX_H */ |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 7f4db12b1459..b4ecd2c7db8e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -4113,7 +4113,7 @@ void __init omap_hwmod_init(void) | |||
| 4113 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | 4113 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
| 4114 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | 4114 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; |
| 4115 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | 4115 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; |
| 4116 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { | 4116 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
| 4117 | soc_ops.enable_module = _omap4_enable_module; | 4117 | soc_ops.enable_module = _omap4_enable_module; |
| 4118 | soc_ops.disable_module = _omap4_disable_module; | 4118 | soc_ops.disable_module = _omap4_disable_module; |
| 4119 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | 4119 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 8c616e436bc7..4588df1447ed 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> |
| 9 | * | 9 | * |
| 10 | * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> | 10 | * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> |
| 11 | * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com> | ||
| 11 | * | 12 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 13 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by | 14 | * it under the terms of the GNU General Public License as published by |
| @@ -35,6 +36,7 @@ | |||
| 35 | #ifndef __ASSEMBLY__ | 36 | #ifndef __ASSEMBLY__ |
| 36 | 37 | ||
| 37 | #include <linux/bitops.h> | 38 | #include <linux/bitops.h> |
| 39 | #include <linux/of.h> | ||
| 38 | 40 | ||
| 39 | /* | 41 | /* |
| 40 | * Test if multicore OMAP support is needed | 42 | * Test if multicore OMAP support is needed |
| @@ -105,6 +107,15 @@ | |||
| 105 | # endif | 107 | # endif |
| 106 | #endif | 108 | #endif |
| 107 | 109 | ||
| 110 | #ifdef CONFIG_SOC_DRA7XX | ||
| 111 | # ifdef OMAP_NAME | ||
| 112 | # undef MULTI_OMAP2 | ||
| 113 | # define MULTI_OMAP2 | ||
| 114 | # else | ||
| 115 | # define OMAP_NAME DRA7XX | ||
| 116 | # endif | ||
| 117 | #endif | ||
| 118 | |||
| 108 | /* | 119 | /* |
| 109 | * Omap device type i.e. EMU/HS/TST/GP/BAD | 120 | * Omap device type i.e. EMU/HS/TST/GP/BAD |
| 110 | */ | 121 | */ |
| @@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437) | |||
| 233 | #define cpu_is_omap447x() 0 | 244 | #define cpu_is_omap447x() 0 |
| 234 | #define soc_is_omap54xx() 0 | 245 | #define soc_is_omap54xx() 0 |
| 235 | #define soc_is_omap543x() 0 | 246 | #define soc_is_omap543x() 0 |
| 247 | #define soc_is_dra7xx() 0 | ||
| 236 | 248 | ||
| 237 | #if defined(MULTI_OMAP2) | 249 | #if defined(MULTI_OMAP2) |
| 238 | # if defined(CONFIG_ARCH_OMAP2) | 250 | # if defined(CONFIG_ARCH_OMAP2) |
| @@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 379 | # define soc_is_omap543x() is_omap543x() | 391 | # define soc_is_omap543x() is_omap543x() |
| 380 | #endif | 392 | #endif |
| 381 | 393 | ||
| 394 | #if defined(CONFIG_SOC_DRA7XX) | ||
| 395 | #undef soc_is_dra7xx | ||
| 396 | #define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) | ||
| 397 | #endif | ||
| 398 | |||
| 382 | /* Various silicon revisions for omap2 */ | 399 | /* Various silicon revisions for omap2 */ |
| 383 | #define OMAP242X_CLASS 0x24200024 | 400 | #define OMAP242X_CLASS 0x24200024 |
| 384 | #define OMAP2420_REV_ES1_0 OMAP242X_CLASS | 401 | #define OMAP2420_REV_ES1_0 OMAP242X_CLASS |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 801287ee4d98..fa74a0625da1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -594,7 +594,8 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, | |||
| 594 | 1, "timer_sys_ck", "ti,timer-alwon"); | 594 | 1, "timer_sys_ck", "ti,timer-alwon"); |
| 595 | #endif | 595 | #endif |
| 596 | 596 | ||
| 597 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) | 597 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
| 598 | defined(CONFIG_SOC_DRA7XX) | ||
| 598 | static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", | 599 | static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", |
| 599 | 2, "sys_clkin_ck", NULL); | 600 | 2, "sys_clkin_ck", NULL); |
| 600 | #endif | 601 | #endif |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index b41599f98a8e..91a5852b44f3 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -174,8 +174,10 @@ void __init orion5x_xor_init(void) | |||
| 174 | ****************************************************************************/ | 174 | ****************************************************************************/ |
| 175 | static void __init orion5x_crypto_init(void) | 175 | static void __init orion5x_crypto_init(void) |
| 176 | { | 176 | { |
| 177 | mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE, | 177 | mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, |
| 178 | ORION5X_SRAM_SIZE); | 178 | ORION_MBUS_SRAM_ATTR, |
| 179 | ORION5X_SRAM_PHYS_BASE, | ||
| 180 | ORION5X_SRAM_SIZE); | ||
| 179 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, | 181 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
| 180 | SZ_8K, IRQ_ORION5X_CESA); | 182 | SZ_8K, IRQ_ORION5X_CESA); |
| 181 | } | 183 | } |
| @@ -222,22 +224,24 @@ void orion5x_setup_wins(void) | |||
| 222 | * The PCIe windows will no longer be statically allocated | 224 | * The PCIe windows will no longer be statically allocated |
| 223 | * here once Orion5x is migrated to the pci-mvebu driver. | 225 | * here once Orion5x is migrated to the pci-mvebu driver. |
| 224 | */ | 226 | */ |
| 225 | mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE, | 227 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, |
| 228 | ORION_MBUS_PCIE_IO_ATTR, | ||
| 229 | ORION5X_PCIE_IO_PHYS_BASE, | ||
| 226 | ORION5X_PCIE_IO_SIZE, | 230 | ORION5X_PCIE_IO_SIZE, |
| 227 | ORION5X_PCIE_IO_BUS_BASE, | 231 | ORION5X_PCIE_IO_BUS_BASE); |
| 228 | MVEBU_MBUS_PCI_IO); | 232 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, |
| 229 | mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE, | 233 | ORION_MBUS_PCIE_MEM_ATTR, |
| 230 | ORION5X_PCIE_MEM_SIZE, | 234 | ORION5X_PCIE_MEM_PHYS_BASE, |
| 231 | MVEBU_MBUS_NO_REMAP, | 235 | ORION5X_PCIE_MEM_SIZE); |
| 232 | MVEBU_MBUS_PCI_MEM); | 236 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, |
| 233 | mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE, | 237 | ORION_MBUS_PCI_IO_ATTR, |
| 238 | ORION5X_PCI_IO_PHYS_BASE, | ||
| 234 | ORION5X_PCI_IO_SIZE, | 239 | ORION5X_PCI_IO_SIZE, |
| 235 | ORION5X_PCI_IO_BUS_BASE, | 240 | ORION5X_PCI_IO_BUS_BASE); |
| 236 | MVEBU_MBUS_PCI_IO); | 241 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, |
| 237 | mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE, | 242 | ORION_MBUS_PCI_MEM_ATTR, |
| 238 | ORION5X_PCI_MEM_SIZE, | 243 | ORION5X_PCI_MEM_PHYS_BASE, |
| 239 | MVEBU_MBUS_NO_REMAP, | 244 | ORION5X_PCI_MEM_SIZE); |
| 240 | MVEBU_MBUS_PCI_MEM); | ||
| 241 | } | 245 | } |
| 242 | 246 | ||
| 243 | int orion5x_tclk; | 247 | int orion5x_tclk; |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index a909afb384fb..f565f9944af2 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h | |||
| @@ -7,6 +7,23 @@ struct dsa_platform_data; | |||
| 7 | struct mv643xx_eth_platform_data; | 7 | struct mv643xx_eth_platform_data; |
| 8 | struct mv_sata_platform_data; | 8 | struct mv_sata_platform_data; |
| 9 | 9 | ||
| 10 | #define ORION_MBUS_PCIE_MEM_TARGET 0x04 | ||
| 11 | #define ORION_MBUS_PCIE_MEM_ATTR 0x59 | ||
| 12 | #define ORION_MBUS_PCIE_IO_TARGET 0x04 | ||
| 13 | #define ORION_MBUS_PCIE_IO_ATTR 0x51 | ||
| 14 | #define ORION_MBUS_PCIE_WA_TARGET 0x04 | ||
| 15 | #define ORION_MBUS_PCIE_WA_ATTR 0x79 | ||
| 16 | #define ORION_MBUS_PCI_MEM_TARGET 0x03 | ||
| 17 | #define ORION_MBUS_PCI_MEM_ATTR 0x59 | ||
| 18 | #define ORION_MBUS_PCI_IO_TARGET 0x03 | ||
| 19 | #define ORION_MBUS_PCI_IO_ATTR 0x51 | ||
| 20 | #define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01 | ||
| 21 | #define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f | ||
| 22 | #define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 | ||
| 23 | #define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) | ||
| 24 | #define ORION_MBUS_SRAM_TARGET 0x00 | ||
| 25 | #define ORION_MBUS_SRAM_ATTR 0x00 | ||
| 26 | |||
| 10 | /* | 27 | /* |
| 11 | * Basic Orion init functions used early by machine-setup. | 28 | * Basic Orion init functions used early by machine-setup. |
| 12 | */ | 29 | */ |
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 16c88bbabc98..8f68b745c1d5 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c | |||
| @@ -317,8 +317,10 @@ static void __init d2net_init(void) | |||
| 317 | d2net_sata_power_init(); | 317 | d2net_sata_power_init(); |
| 318 | orion5x_sata_init(&d2net_sata_data); | 318 | orion5x_sata_init(&d2net_sata_data); |
| 319 | 319 | ||
| 320 | mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE, | 320 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 321 | D2NET_NOR_BOOT_SIZE); | 321 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 322 | D2NET_NOR_BOOT_BASE, | ||
| 323 | D2NET_NOR_BOOT_SIZE); | ||
| 322 | platform_device_register(&d2net_nor_flash); | 324 | platform_device_register(&d2net_nor_flash); |
| 323 | 325 | ||
| 324 | platform_device_register(&d2net_gpio_buttons); | 326 | platform_device_register(&d2net_gpio_buttons); |
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 4e1263da38bb..4b2aefd1d961 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
| @@ -340,19 +340,27 @@ static void __init db88f5281_init(void) | |||
| 340 | orion5x_uart0_init(); | 340 | orion5x_uart0_init(); |
| 341 | orion5x_uart1_init(); | 341 | orion5x_uart1_init(); |
| 342 | 342 | ||
| 343 | mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE, | 343 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 344 | DB88F5281_NOR_BOOT_SIZE); | 344 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 345 | DB88F5281_NOR_BOOT_BASE, | ||
| 346 | DB88F5281_NOR_BOOT_SIZE); | ||
| 345 | platform_device_register(&db88f5281_boot_flash); | 347 | platform_device_register(&db88f5281_boot_flash); |
| 346 | 348 | ||
| 347 | mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE, | 349 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), |
| 348 | DB88F5281_7SEG_SIZE); | 350 | ORION_MBUS_DEVBUS_ATTR(0), |
| 351 | DB88F5281_7SEG_BASE, | ||
| 352 | DB88F5281_7SEG_SIZE); | ||
| 349 | 353 | ||
| 350 | mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE, | 354 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), |
| 351 | DB88F5281_NOR_SIZE); | 355 | ORION_MBUS_DEVBUS_ATTR(1), |
| 356 | DB88F5281_NOR_BASE, | ||
| 357 | DB88F5281_NOR_SIZE); | ||
| 352 | platform_device_register(&db88f5281_nor_flash); | 358 | platform_device_register(&db88f5281_nor_flash); |
| 353 | 359 | ||
| 354 | mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE, | 360 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), |
| 355 | DB88F5281_NAND_SIZE); | 361 | ORION_MBUS_DEVBUS_ATTR(2), |
| 362 | DB88F5281_NAND_BASE, | ||
| 363 | DB88F5281_NAND_SIZE); | ||
| 356 | platform_device_register(&db88f5281_nand_flash); | 364 | platform_device_register(&db88f5281_nand_flash); |
| 357 | 365 | ||
| 358 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | 366 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 9e6baf581ed3..70974732cbf0 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -611,8 +611,10 @@ static void __init dns323_init(void) | |||
| 611 | /* setup flash mapping | 611 | /* setup flash mapping |
| 612 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 612 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
| 613 | */ | 613 | */ |
| 614 | mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE, | 614 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 615 | DNS323_NOR_BOOT_SIZE); | 615 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 616 | DNS323_NOR_BOOT_BASE, | ||
| 617 | DNS323_NOR_BOOT_SIZE); | ||
| 616 | platform_device_register(&dns323_nor_flash); | 618 | platform_device_register(&dns323_nor_flash); |
| 617 | 619 | ||
| 618 | /* Sort out LEDs, Buttons and i2c devices */ | 620 | /* Sort out LEDs, Buttons and i2c devices */ |
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index 147615510dd0..0fc33c56cbb7 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c | |||
| @@ -154,8 +154,10 @@ void __init edmini_v2_init(void) | |||
| 154 | orion5x_ehci0_init(); | 154 | orion5x_ehci0_init(); |
| 155 | orion5x_eth_init(&edmini_v2_eth_data); | 155 | orion5x_eth_init(&edmini_v2_eth_data); |
| 156 | 156 | ||
| 157 | mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE, | 157 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 158 | EDMINI_V2_NOR_BOOT_SIZE); | 158 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 159 | EDMINI_V2_NOR_BOOT_BASE, | ||
| 160 | EDMINI_V2_NOR_BOOT_SIZE); | ||
| 159 | platform_device_register(&edmini_v2_nor_flash); | 161 | platform_device_register(&edmini_v2_nor_flash); |
| 160 | 162 | ||
| 161 | pr_notice("edmini_v2: USB device port, flash write and power-off " | 163 | pr_notice("edmini_v2: USB device port, flash write and power-off " |
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index aae10e4a917c..fe6a48a325e8 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c | |||
| @@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void) | |||
| 359 | orion5x_uart1_init(); | 359 | orion5x_uart1_init(); |
| 360 | orion5x_xor_init(); | 360 | orion5x_xor_init(); |
| 361 | 361 | ||
| 362 | mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE, | 362 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 363 | KUROBOX_PRO_NOR_BOOT_SIZE); | 363 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 364 | KUROBOX_PRO_NOR_BOOT_BASE, | ||
| 365 | KUROBOX_PRO_NOR_BOOT_SIZE); | ||
| 364 | platform_device_register(&kurobox_pro_nor_flash); | 366 | platform_device_register(&kurobox_pro_nor_flash); |
| 365 | 367 | ||
| 366 | if (machine_is_kurobox_pro()) { | 368 | if (machine_is_kurobox_pro()) { |
| 367 | mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE, | 369 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), |
| 368 | KUROBOX_PRO_NAND_SIZE); | 370 | ORION_MBUS_DEVBUS_ATTR(0), |
| 371 | KUROBOX_PRO_NAND_BASE, | ||
| 372 | KUROBOX_PRO_NAND_SIZE); | ||
| 369 | platform_device_register(&kurobox_pro_nand_flash); | 373 | platform_device_register(&kurobox_pro_nand_flash); |
| 370 | } | 374 | } |
| 371 | 375 | ||
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 6234977b5aea..028ea038d404 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c | |||
| @@ -294,8 +294,10 @@ static void __init lschl_init(void) | |||
| 294 | orion5x_uart0_init(); | 294 | orion5x_uart0_init(); |
| 295 | orion5x_xor_init(); | 295 | orion5x_xor_init(); |
| 296 | 296 | ||
| 297 | mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE, | 297 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 298 | LSCHL_NOR_BOOT_SIZE); | 298 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 299 | LSCHL_NOR_BOOT_BASE, | ||
| 300 | LSCHL_NOR_BOOT_SIZE); | ||
| 299 | platform_device_register(&lschl_nor_flash); | 301 | platform_device_register(&lschl_nor_flash); |
| 300 | 302 | ||
| 301 | platform_device_register(&lschl_leds); | 303 | platform_device_register(&lschl_leds); |
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index fe04c4b64569..32b7129b767d 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c | |||
| @@ -243,8 +243,10 @@ static void __init ls_hgl_init(void) | |||
| 243 | orion5x_uart0_init(); | 243 | orion5x_uart0_init(); |
| 244 | orion5x_xor_init(); | 244 | orion5x_xor_init(); |
| 245 | 245 | ||
| 246 | mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE, | 246 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 247 | LS_HGL_NOR_BOOT_SIZE); | 247 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 248 | LS_HGL_NOR_BOOT_BASE, | ||
| 249 | LS_HGL_NOR_BOOT_SIZE); | ||
| 248 | platform_device_register(&ls_hgl_nor_flash); | 250 | platform_device_register(&ls_hgl_nor_flash); |
| 249 | 251 | ||
| 250 | platform_device_register(&ls_hgl_button_device); | 252 | platform_device_register(&ls_hgl_button_device); |
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index ca4dbe973daf..a6493e76f96d 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c | |||
| @@ -244,8 +244,10 @@ static void __init lsmini_init(void) | |||
| 244 | orion5x_uart0_init(); | 244 | orion5x_uart0_init(); |
| 245 | orion5x_xor_init(); | 245 | orion5x_xor_init(); |
| 246 | 246 | ||
| 247 | mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE, | 247 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 248 | LSMINI_NOR_BOOT_SIZE); | 248 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 249 | LSMINI_NOR_BOOT_BASE, | ||
| 250 | LSMINI_NOR_BOOT_SIZE); | ||
| 249 | platform_device_register(&lsmini_nor_flash); | 251 | platform_device_register(&lsmini_nor_flash); |
| 250 | 252 | ||
| 251 | platform_device_register(&lsmini_button_device); | 253 | platform_device_register(&lsmini_button_device); |
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 827acbafc9dc..e105130ba51c 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c | |||
| @@ -241,8 +241,10 @@ static void __init mss2_init(void) | |||
| 241 | orion5x_uart0_init(); | 241 | orion5x_uart0_init(); |
| 242 | orion5x_xor_init(); | 242 | orion5x_xor_init(); |
| 243 | 243 | ||
| 244 | mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE, | 244 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 245 | MSS2_NOR_BOOT_SIZE); | 245 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 246 | MSS2_NOR_BOOT_BASE, | ||
| 247 | MSS2_NOR_BOOT_SIZE); | ||
| 246 | platform_device_register(&mss2_nor_flash); | 248 | platform_device_register(&mss2_nor_flash); |
| 247 | 249 | ||
| 248 | platform_device_register(&mss2_button_device); | 250 | platform_device_register(&mss2_button_device); |
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 92600ae2b4b6..e032f01da49e 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c | |||
| @@ -204,8 +204,10 @@ static void __init mv2120_init(void) | |||
| 204 | orion5x_uart0_init(); | 204 | orion5x_uart0_init(); |
| 205 | orion5x_xor_init(); | 205 | orion5x_xor_init(); |
| 206 | 206 | ||
| 207 | mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE, | 207 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 208 | MV2120_NOR_BOOT_SIZE); | 208 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 209 | MV2120_NOR_BOOT_BASE, | ||
| 210 | MV2120_NOR_BOOT_SIZE); | ||
| 209 | platform_device_register(&mv2120_nor_flash); | 211 | platform_device_register(&mv2120_nor_flash); |
| 210 | 212 | ||
| 211 | platform_device_register(&mv2120_button_device); | 213 | platform_device_register(&mv2120_button_device); |
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index dd0641a0d074..ba73dc7ffb9e 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c | |||
| @@ -397,8 +397,10 @@ static void __init net2big_init(void) | |||
| 397 | net2big_sata_power_init(); | 397 | net2big_sata_power_init(); |
| 398 | orion5x_sata_init(&net2big_sata_data); | 398 | orion5x_sata_init(&net2big_sata_data); |
| 399 | 399 | ||
| 400 | mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE, | 400 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 401 | NET2BIG_NOR_BOOT_SIZE); | 401 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 402 | NET2BIG_NOR_BOOT_BASE, | ||
| 403 | NET2BIG_NOR_BOOT_SIZE); | ||
| 402 | platform_device_register(&net2big_nor_flash); | 404 | platform_device_register(&net2big_nor_flash); |
| 403 | 405 | ||
| 404 | platform_device_register(&net2big_gpio_buttons); | 406 | platform_device_register(&net2big_gpio_buttons); |
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 503368023bb1..7fab67053030 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
| @@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { |
| 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | 158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " |
| 159 | "read transaction workaround\n"); | 159 | "read transaction workaround\n"); |
| 160 | mvebu_mbus_add_window_remap_flags("pcie0.0", | 160 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET, |
| 161 | ORION5X_PCIE_WA_PHYS_BASE, | 161 | ORION_MBUS_PCIE_WA_ATTR, |
| 162 | ORION5X_PCIE_WA_SIZE, | 162 | ORION5X_PCIE_WA_PHYS_BASE, |
| 163 | MVEBU_MBUS_NO_REMAP, | 163 | ORION5X_PCIE_WA_SIZE); |
| 164 | MVEBU_MBUS_PCI_WA); | ||
| 165 | pcie_ops.read = pcie_rd_conf_wa; | 164 | pcie_ops.read = pcie_rd_conf_wa; |
| 166 | } | 165 | } |
| 167 | 166 | ||
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 1c4498bf650a..213b3e143c57 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | |||
| @@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void) | |||
| 123 | orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); | 123 | orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); |
| 124 | orion5x_uart0_init(); | 124 | orion5x_uart0_init(); |
| 125 | 125 | ||
| 126 | mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE, | 126 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 127 | RD88F5181L_FXO_NOR_BOOT_SIZE); | 127 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 128 | RD88F5181L_FXO_NOR_BOOT_BASE, | ||
| 129 | RD88F5181L_FXO_NOR_BOOT_SIZE); | ||
| 128 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); | 130 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); |
| 129 | } | 131 | } |
| 130 | 132 | ||
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index adabe34c4fc6..594800e1d691 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | |||
| @@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void) | |||
| 130 | orion5x_i2c_init(); | 130 | orion5x_i2c_init(); |
| 131 | orion5x_uart0_init(); | 131 | orion5x_uart0_init(); |
| 132 | 132 | ||
| 133 | mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE, | 133 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 134 | RD88F5181L_GE_NOR_BOOT_SIZE); | 134 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 135 | RD88F5181L_GE_NOR_BOOT_BASE, | ||
| 136 | RD88F5181L_GE_NOR_BOOT_SIZE); | ||
| 135 | platform_device_register(&rd88f5181l_ge_nor_boot_flash); | 137 | platform_device_register(&rd88f5181l_ge_nor_boot_flash); |
| 136 | 138 | ||
| 137 | i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); | 139 | i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); |
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 66e77ec91532..b1cf68493ffc 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
| @@ -264,11 +264,14 @@ static void __init rd88f5182_init(void) | |||
| 264 | orion5x_uart0_init(); | 264 | orion5x_uart0_init(); |
| 265 | orion5x_xor_init(); | 265 | orion5x_xor_init(); |
| 266 | 266 | ||
| 267 | mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE, | 267 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 268 | RD88F5182_NOR_BOOT_SIZE); | 268 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 269 | 269 | RD88F5182_NOR_BOOT_BASE, | |
| 270 | mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE, | 270 | RD88F5182_NOR_BOOT_SIZE); |
| 271 | RD88F5182_NOR_SIZE); | 271 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), |
| 272 | ORION_MBUS_DEVBUS_ATTR(1), | ||
| 273 | RD88F5182_NOR_BASE, | ||
| 274 | RD88F5182_NOR_SIZE); | ||
| 272 | platform_device_register(&rd88f5182_nor_flash); | 275 | platform_device_register(&rd88f5182_nor_flash); |
| 273 | platform_device_register(&rd88f5182_gpio_leds); | 276 | platform_device_register(&rd88f5182_gpio_leds); |
| 274 | 277 | ||
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index a0bfa53e7556..7e9064844698 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c | |||
| @@ -329,8 +329,10 @@ static void __init tsp2_init(void) | |||
| 329 | /* | 329 | /* |
| 330 | * Configure peripherals. | 330 | * Configure peripherals. |
| 331 | */ | 331 | */ |
| 332 | mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE, | 332 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 333 | TSP2_NOR_BOOT_SIZE); | 333 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 334 | TSP2_NOR_BOOT_BASE, | ||
| 335 | TSP2_NOR_BOOT_SIZE); | ||
| 334 | platform_device_register(&tsp2_nor_flash); | 336 | platform_device_register(&tsp2_nor_flash); |
| 335 | 337 | ||
| 336 | orion5x_ehci0_init(); | 338 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 80174f0f168e..e90c0618fdad 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
| @@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void) | |||
| 286 | /* | 286 | /* |
| 287 | * Configure peripherals. | 287 | * Configure peripherals. |
| 288 | */ | 288 | */ |
| 289 | mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE, | 289 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 290 | QNAP_TS209_NOR_BOOT_SIZE); | 290 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 291 | QNAP_TS209_NOR_BOOT_BASE, | ||
| 292 | QNAP_TS209_NOR_BOOT_SIZE); | ||
| 291 | platform_device_register(&qnap_ts209_nor_flash); | 293 | platform_device_register(&qnap_ts209_nor_flash); |
| 292 | 294 | ||
| 293 | orion5x_ehci0_init(); | 295 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 92592790d6da..5c079d312015 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c | |||
| @@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void) | |||
| 277 | /* | 277 | /* |
| 278 | * Configure peripherals. | 278 | * Configure peripherals. |
| 279 | */ | 279 | */ |
| 280 | mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE, | 280 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 281 | QNAP_TS409_NOR_BOOT_SIZE); | 281 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 282 | QNAP_TS409_NOR_BOOT_BASE, | ||
| 283 | QNAP_TS409_NOR_BOOT_SIZE); | ||
| 282 | platform_device_register(&qnap_ts409_nor_flash); | 284 | platform_device_register(&qnap_ts409_nor_flash); |
| 283 | 285 | ||
| 284 | orion5x_ehci0_init(); | 286 | orion5x_ehci0_init(); |
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 6b84863c018d..80a56ee245b3 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c | |||
| @@ -127,8 +127,10 @@ static void __init wnr854t_init(void) | |||
| 127 | orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); | 127 | orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); |
| 128 | orion5x_uart0_init(); | 128 | orion5x_uart0_init(); |
| 129 | 129 | ||
| 130 | mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE, | 130 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 131 | WNR854T_NOR_BOOT_SIZE); | 131 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 132 | WNR854T_NOR_BOOT_BASE, | ||
| 133 | WNR854T_NOR_BOOT_SIZE); | ||
| 132 | platform_device_register(&wnr854t_nor_flash); | 134 | platform_device_register(&wnr854t_nor_flash); |
| 133 | } | 135 | } |
| 134 | 136 | ||
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index fae684bc54f2..670e30dc0d1b 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c | |||
| @@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void) | |||
| 213 | orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); | 213 | orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); |
| 214 | orion5x_uart0_init(); | 214 | orion5x_uart0_init(); |
| 215 | 215 | ||
| 216 | mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE, | 216 | mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
| 217 | WRT350N_V2_NOR_BOOT_SIZE); | 217 | ORION_MBUS_DEVBUS_BOOT_ATTR, |
| 218 | WRT350N_V2_NOR_BOOT_BASE, | ||
| 219 | WRT350N_V2_NOR_BOOT_SIZE); | ||
| 218 | platform_device_register(&wrt350n_v2_nor_flash); | 220 | platform_device_register(&wrt350n_v2_nor_flash); |
| 219 | platform_device_register(&wrt350n_v2_leds); | 221 | platform_device_register(&wrt350n_v2_leds); |
| 220 | platform_device_register(&wrt350n_v2_button_device); | 222 | platform_device_register(&wrt350n_v2_button_device); |
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index 02cc34388b05..c4525a88e5da 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c | |||
| @@ -34,7 +34,10 @@ static void sirfsoc_set_wakeup_source(void) | |||
| 34 | pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + | 34 | pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + |
| 35 | SIRFSOC_PWRC_TRIGGER_EN); | 35 | SIRFSOC_PWRC_TRIGGER_EN); |
| 36 | #define X_ON_KEY_B (1 << 0) | 36 | #define X_ON_KEY_B (1 << 0) |
| 37 | sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B, | 37 | #define RTC_ALARM0_B (1 << 2) |
| 38 | #define RTC_ALARM1_B (1 << 3) | ||
| 39 | sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B | | ||
| 40 | RTC_ALARM0_B | RTC_ALARM1_B, | ||
| 38 | sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); | 41 | sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); |
| 39 | } | 42 | } |
| 40 | 43 | ||
| @@ -85,12 +88,6 @@ static const struct platform_suspend_ops sirfsoc_pm_ops = { | |||
| 85 | .valid = suspend_valid_only_mem, | 88 | .valid = suspend_valid_only_mem, |
| 86 | }; | 89 | }; |
| 87 | 90 | ||
| 88 | int __init sirfsoc_pm_init(void) | ||
| 89 | { | ||
| 90 | suspend_set_ops(&sirfsoc_pm_ops); | ||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | static const struct of_device_id pwrc_ids[] = { | 91 | static const struct of_device_id pwrc_ids[] = { |
| 95 | { .compatible = "sirf,prima2-pwrc" }, | 92 | { .compatible = "sirf,prima2-pwrc" }, |
| 96 | {} | 93 | {} |
| @@ -118,7 +115,6 @@ static int __init sirfsoc_of_pwrc_init(void) | |||
| 118 | 115 | ||
| 119 | return 0; | 116 | return 0; |
| 120 | } | 117 | } |
| 121 | postcore_initcall(sirfsoc_of_pwrc_init); | ||
| 122 | 118 | ||
| 123 | static const struct of_device_id memc_ids[] = { | 119 | static const struct of_device_id memc_ids[] = { |
| 124 | { .compatible = "sirf,prima2-memc" }, | 120 | { .compatible = "sirf,prima2-memc" }, |
| @@ -149,4 +145,11 @@ static int __init sirfsoc_memc_init(void) | |||
| 149 | { | 145 | { |
| 150 | return platform_driver_register(&sirfsoc_memc_driver); | 146 | return platform_driver_register(&sirfsoc_memc_driver); |
| 151 | } | 147 | } |
| 152 | postcore_initcall(sirfsoc_memc_init); | 148 | |
| 149 | int __init sirfsoc_pm_init(void) | ||
| 150 | { | ||
| 151 | sirfsoc_of_pwrc_init(); | ||
| 152 | sirfsoc_memc_init(); | ||
| 153 | suspend_set_ops(&sirfsoc_pm_ops); | ||
| 154 | return 0; | ||
| 155 | } | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index cdefd7dcca79..403c939ddf99 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
| @@ -61,9 +61,10 @@ config ARCH_R8A73A4 | |||
| 61 | select ARCH_WANT_OPTIONAL_GPIOLIB | 61 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 62 | select ARM_GIC | 62 | select ARM_GIC |
| 63 | select CPU_V7 | 63 | select CPU_V7 |
| 64 | select HAVE_ARM_ARCH_TIMER | ||
| 65 | select SH_CLK_CPG | 64 | select SH_CLK_CPG |
| 66 | select RENESAS_IRQC | 65 | select RENESAS_IRQC |
| 66 | select ARCH_HAS_CPUFREQ | ||
| 67 | select ARCH_HAS_OPP | ||
| 67 | 68 | ||
| 68 | config ARCH_R8A7740 | 69 | config ARCH_R8A7740 |
| 69 | bool "R-Mobile A1 (R8A77400)" | 70 | bool "R-Mobile A1 (R8A77400)" |
| @@ -97,7 +98,6 @@ config ARCH_R8A7790 | |||
| 97 | select ARCH_WANT_OPTIONAL_GPIOLIB | 98 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 98 | select ARM_GIC | 99 | select ARM_GIC |
| 99 | select CPU_V7 | 100 | select CPU_V7 |
| 100 | select HAVE_ARM_ARCH_TIMER | ||
| 101 | select SH_CLK_CPG | 101 | select SH_CLK_CPG |
| 102 | select RENESAS_IRQC | 102 | select RENESAS_IRQC |
| 103 | 103 | ||
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 1fbc39a14e25..af6dd39d3758 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c | |||
| @@ -101,6 +101,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { | |||
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | DT_MACHINE_START(APE6EVM_DT, "ape6evm") | 103 | DT_MACHINE_START(APE6EVM_DT, "ape6evm") |
| 104 | .init_early = r8a73a4_init_delay, | ||
| 104 | .init_time = shmobile_timer_init, | 105 | .init_time = shmobile_timer_init, |
| 105 | .init_machine = ape6evm_add_standard_devices, | 106 | .init_machine = ape6evm_add_standard_devices, |
| 106 | .dt_compat = ape6evm_boards_compat_dt, | 107 | .dt_compat = ape6evm_boards_compat_dt, |
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 78d92d34665d..f89f16650731 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c | |||
| @@ -102,6 +102,7 @@ static const char *lager_boards_compat_dt[] __initdata = { | |||
| 102 | }; | 102 | }; |
| 103 | 103 | ||
| 104 | DT_MACHINE_START(LAGER_DT, "lager") | 104 | DT_MACHINE_START(LAGER_DT, "lager") |
| 105 | .init_early = r8a7790_init_delay, | ||
| 105 | .init_time = r8a7790_timer_init, | 106 | .init_time = r8a7790_timer_init, |
| 106 | .init_machine = lager_add_standard_devices, | 107 | .init_machine = lager_add_standard_devices, |
| 107 | .dt_compat = lager_boards_compat_dt, | 108 | .dt_compat = lager_boards_compat_dt, |
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c index 56dd0cfcddc7..5ac13ba71d54 100644 --- a/arch/arm/mach-shmobile/clock-emev2.c +++ b/arch/arm/mach-shmobile/clock-emev2.c | |||
| @@ -40,7 +40,6 @@ | |||
| 40 | #define USIB2SCLKDIV 0x65c | 40 | #define USIB2SCLKDIV 0x65c |
| 41 | #define USIB3SCLKDIV 0x660 | 41 | #define USIB3SCLKDIV 0x660 |
| 42 | #define STI_CLKSEL 0x688 | 42 | #define STI_CLKSEL 0x688 |
| 43 | #define SMU_GENERAL_REG0 0x7c0 | ||
| 44 | 43 | ||
| 45 | /* not pretty, but hey */ | 44 | /* not pretty, but hey */ |
| 46 | static void __iomem *smu_base; | 45 | static void __iomem *smu_base; |
| @@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs) | |||
| 51 | iowrite32(value, smu_base + offs); | 50 | iowrite32(value, smu_base + offs); |
| 52 | } | 51 | } |
| 53 | 52 | ||
| 54 | void emev2_set_boot_vector(unsigned long value) | ||
| 55 | { | ||
| 56 | emev2_smu_write(value, SMU_GENERAL_REG0); | ||
| 57 | } | ||
| 58 | |||
| 59 | static struct clk_mapping smu_mapping = { | 53 | static struct clk_mapping smu_mapping = { |
| 60 | .phys = EMEV2_SMU_BASE, | 54 | .phys = EMEV2_SMU_BASE, |
| 61 | .len = PAGE_SIZE, | 55 | .len = PAGE_SIZE, |
| @@ -205,18 +199,6 @@ static struct clk_lookup lookups[] = { | |||
| 205 | void __init emev2_clock_init(void) | 199 | void __init emev2_clock_init(void) |
| 206 | { | 200 | { |
| 207 | int k, ret = 0; | 201 | int k, ret = 0; |
| 208 | static int is_setup; | ||
| 209 | |||
| 210 | /* yuck, this is ugly as hell, but the non-smp case of clocks | ||
| 211 | * code is now designed to rely on ioremap() instead of static | ||
| 212 | * entity maps. in the case of smp we need access to the SMU | ||
| 213 | * register earlier than ioremap() is actually working without | ||
| 214 | * any static maps. to enable SMP in ugly but with dynamic | ||
| 215 | * mappings we have to call emev2_clock_init() from different | ||
| 216 | * places depending on UP and SMP... | ||
| 217 | */ | ||
| 218 | if (is_setup++) | ||
| 219 | return; | ||
| 220 | 202 | ||
| 221 | smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); | 203 | smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); |
| 222 | BUG_ON(!smu_base); | 204 | BUG_ON(!smu_base); |
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 5f7fe628b8a1..8ea5ef6c79cc 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c | |||
| @@ -30,10 +30,12 @@ | |||
| 30 | 30 | ||
| 31 | #define SMSTPCR2 0xe6150138 | 31 | #define SMSTPCR2 0xe6150138 |
| 32 | #define SMSTPCR3 0xe615013c | 32 | #define SMSTPCR3 0xe615013c |
| 33 | #define SMSTPCR4 0xe6150140 | ||
| 33 | #define SMSTPCR5 0xe6150144 | 34 | #define SMSTPCR5 0xe6150144 |
| 34 | 35 | ||
| 35 | #define FRQCRA 0xE6150000 | 36 | #define FRQCRA 0xE6150000 |
| 36 | #define FRQCRB 0xE6150004 | 37 | #define FRQCRB 0xE6150004 |
| 38 | #define FRQCRC 0xE61500E0 | ||
| 37 | #define VCLKCR1 0xE6150008 | 39 | #define VCLKCR1 0xE6150008 |
| 38 | #define VCLKCR2 0xE615000C | 40 | #define VCLKCR2 0xE615000C |
| 39 | #define VCLKCR3 0xE615001C | 41 | #define VCLKCR3 0xE615001C |
| @@ -52,6 +54,7 @@ | |||
| 52 | #define HSICKCR 0xE615026C | 54 | #define HSICKCR 0xE615026C |
| 53 | #define M4CKCR 0xE6150098 | 55 | #define M4CKCR 0xE6150098 |
| 54 | #define PLLECR 0xE61500D0 | 56 | #define PLLECR 0xE61500D0 |
| 57 | #define PLL0CR 0xE61500D8 | ||
| 55 | #define PLL1CR 0xE6150028 | 58 | #define PLL1CR 0xE6150028 |
| 56 | #define PLL2CR 0xE615002C | 59 | #define PLL2CR 0xE615002C |
| 57 | #define PLL2SCR 0xE61501F4 | 60 | #define PLL2SCR 0xE61501F4 |
| @@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = { | |||
| 177 | .mapping = &cpg_mapping, \ | 180 | .mapping = &cpg_mapping, \ |
| 178 | } | 181 | } |
| 179 | 182 | ||
| 183 | PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0); | ||
| 180 | PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); | 184 | PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); |
| 181 | PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); | 185 | PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); |
| 182 | PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); | 186 | PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); |
| @@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); | |||
| 184 | 188 | ||
| 185 | SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); | 189 | SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); |
| 186 | 190 | ||
| 191 | static atomic_t frqcr_lock; | ||
| 192 | |||
| 193 | /* Several clocks need to access FRQCRB, have to lock */ | ||
| 194 | static bool frqcr_kick_check(struct clk *clk) | ||
| 195 | { | ||
| 196 | return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31)); | ||
| 197 | } | ||
| 198 | |||
| 199 | static int frqcr_kick_do(struct clk *clk) | ||
| 200 | { | ||
| 201 | int i; | ||
| 202 | |||
| 203 | /* set KICK bit in FRQCRB to update hardware setting, check success */ | ||
| 204 | iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB)); | ||
| 205 | for (i = 1000; i; i--) | ||
| 206 | if (ioread32(CPG_MAP(FRQCRB)) & BIT(31)) | ||
| 207 | cpu_relax(); | ||
| 208 | else | ||
| 209 | return 0; | ||
| 210 | |||
| 211 | return -ETIMEDOUT; | ||
| 212 | } | ||
| 213 | |||
| 214 | static int zclk_set_rate(struct clk *clk, unsigned long rate) | ||
| 215 | { | ||
| 216 | void __iomem *frqcrc; | ||
| 217 | int ret; | ||
| 218 | unsigned long step, p_rate; | ||
| 219 | u32 val; | ||
| 220 | |||
| 221 | if (!clk->parent || !__clk_get(clk->parent)) | ||
| 222 | return -ENODEV; | ||
| 223 | |||
| 224 | if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) { | ||
| 225 | ret = -EBUSY; | ||
| 226 | goto done; | ||
| 227 | } | ||
| 228 | |||
| 229 | /* | ||
| 230 | * Users are supposed to first call clk_set_rate() only with | ||
| 231 | * clk_round_rate() results. So, we don't fix wrong rates here, but | ||
| 232 | * guard against them anyway | ||
| 233 | */ | ||
| 234 | |||
| 235 | p_rate = clk_get_rate(clk->parent); | ||
| 236 | if (rate == p_rate) { | ||
| 237 | val = 0; | ||
| 238 | } else { | ||
| 239 | step = DIV_ROUND_CLOSEST(p_rate, 32); | ||
| 240 | |||
| 241 | if (rate > p_rate || rate < step) { | ||
| 242 | ret = -EINVAL; | ||
| 243 | goto done; | ||
| 244 | } | ||
| 245 | |||
| 246 | val = 32 - rate / step; | ||
| 247 | } | ||
| 248 | |||
| 249 | frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); | ||
| 250 | |||
| 251 | iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) | | ||
| 252 | (val << clk->enable_bit), frqcrc); | ||
| 253 | |||
| 254 | ret = frqcr_kick_do(clk); | ||
| 255 | |||
| 256 | done: | ||
| 257 | atomic_dec(&frqcr_lock); | ||
| 258 | __clk_put(clk->parent); | ||
| 259 | return ret; | ||
| 260 | } | ||
| 261 | |||
| 262 | static long zclk_round_rate(struct clk *clk, unsigned long rate) | ||
| 263 | { | ||
| 264 | /* | ||
| 265 | * theoretical rate = parent rate * multiplier / 32, | ||
| 266 | * where 1 <= multiplier <= 32. Therefore we should do | ||
| 267 | * multiplier = rate * 32 / parent rate | ||
| 268 | * rounded rate = parent rate * multiplier / 32. | ||
| 269 | * However, multiplication before division won't fit in 32 bits, so | ||
| 270 | * we sacrifice some precision by first dividing and then multiplying. | ||
| 271 | * To find the nearest divisor we calculate both and pick up the best | ||
| 272 | * one. This avoids 64-bit arithmetics. | ||
| 273 | */ | ||
| 274 | unsigned long step, mul_min, mul_max, rate_min, rate_max; | ||
| 275 | |||
| 276 | rate_max = clk_get_rate(clk->parent); | ||
| 277 | |||
| 278 | /* output freq <= parent */ | ||
| 279 | if (rate >= rate_max) | ||
| 280 | return rate_max; | ||
| 281 | |||
| 282 | step = DIV_ROUND_CLOSEST(rate_max, 32); | ||
| 283 | /* output freq >= parent / 32 */ | ||
| 284 | if (step >= rate) | ||
| 285 | return step; | ||
| 286 | |||
| 287 | mul_min = rate / step; | ||
| 288 | mul_max = DIV_ROUND_UP(rate, step); | ||
| 289 | rate_min = step * mul_min; | ||
| 290 | if (mul_max == mul_min) | ||
| 291 | return rate_min; | ||
| 292 | |||
| 293 | rate_max = step * mul_max; | ||
| 294 | |||
| 295 | if (rate_max - rate < rate - rate_min) | ||
| 296 | return rate_max; | ||
| 297 | |||
| 298 | return rate_min; | ||
| 299 | } | ||
| 300 | |||
| 301 | static unsigned long zclk_recalc(struct clk *clk) | ||
| 302 | { | ||
| 303 | void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg; | ||
| 304 | unsigned int max = clk->div_mask + 1; | ||
| 305 | unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) & | ||
| 306 | clk->div_mask); | ||
| 307 | |||
| 308 | return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) * | ||
| 309 | (max - val); | ||
| 310 | } | ||
| 311 | |||
| 312 | static struct sh_clk_ops zclk_ops = { | ||
| 313 | .recalc = zclk_recalc, | ||
| 314 | .set_rate = zclk_set_rate, | ||
| 315 | .round_rate = zclk_round_rate, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct clk z_clk = { | ||
| 319 | .parent = &pll0_clk, | ||
| 320 | .div_mask = 0x1f, | ||
| 321 | .enable_bit = 8, | ||
| 322 | /* We'll need to access FRQCRB and FRQCRC */ | ||
| 323 | .enable_reg = (void __iomem *)FRQCRB, | ||
| 324 | .ops = &zclk_ops, | ||
| 325 | }; | ||
| 326 | |||
| 327 | /* | ||
| 328 | * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3 | ||
| 329 | * switching is only available in auto-DVFS mode | ||
| 330 | */ | ||
| 331 | SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2); | ||
| 332 | |||
| 333 | static struct clk z2_clk = { | ||
| 334 | .parent = &pll0_div2_clk, | ||
| 335 | .div_mask = 0x1f, | ||
| 336 | .enable_bit = 0, | ||
| 337 | /* We'll need to access FRQCRB and FRQCRC */ | ||
| 338 | .enable_reg = (void __iomem *)FRQCRB, | ||
| 339 | .ops = &zclk_ops, | ||
| 340 | }; | ||
| 341 | |||
| 187 | static struct clk *main_clks[] = { | 342 | static struct clk *main_clks[] = { |
| 188 | &extalr_clk, | 343 | &extalr_clk, |
| 189 | &extal1_clk, | 344 | &extal1_clk, |
| @@ -195,22 +350,23 @@ static struct clk *main_clks[] = { | |||
| 195 | &main_div2_clk, | 350 | &main_div2_clk, |
| 196 | &fsiack_clk, | 351 | &fsiack_clk, |
| 197 | &fsibck_clk, | 352 | &fsibck_clk, |
| 353 | &pll0_clk, | ||
| 198 | &pll1_clk, | 354 | &pll1_clk, |
| 199 | &pll1_div2_clk, | 355 | &pll1_div2_clk, |
| 200 | &pll2_clk, | 356 | &pll2_clk, |
| 201 | &pll2s_clk, | 357 | &pll2s_clk, |
| 202 | &pll2h_clk, | 358 | &pll2h_clk, |
| 359 | &z_clk, | ||
| 360 | &pll0_div2_clk, | ||
| 361 | &z2_clk, | ||
| 203 | }; | 362 | }; |
| 204 | 363 | ||
| 205 | /* DIV4 */ | 364 | /* DIV4 */ |
| 206 | static void div4_kick(struct clk *clk) | 365 | static void div4_kick(struct clk *clk) |
| 207 | { | 366 | { |
| 208 | unsigned long value; | 367 | if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n")) |
| 209 | 368 | frqcr_kick_do(clk); | |
| 210 | /* set KICK bit in FRQCRB to update hardware setting */ | 369 | atomic_dec(&frqcr_lock); |
| 211 | value = ioread32(CPG_MAP(FRQCRB)); | ||
| 212 | value |= (1 << 31); | ||
| 213 | iowrite32(value, CPG_MAP(FRQCRB)); | ||
| 214 | } | 370 | } |
| 215 | 371 | ||
| 216 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; | 372 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; |
| @@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = { | |||
| 349 | /* MSTP */ | 505 | /* MSTP */ |
| 350 | enum { | 506 | enum { |
| 351 | MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, | 507 | MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, |
| 352 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, | 508 | MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, |
| 353 | MSTP522, | 509 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, |
| 510 | MSTP411, MSTP410, MSTP409, | ||
| 511 | MSTP522, MSTP515, | ||
| 354 | MSTP_NR | 512 | MSTP_NR |
| 355 | }; | 513 | }; |
| 356 | 514 | ||
| @@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 361 | [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ | 519 | [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ |
| 362 | [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ | 520 | [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ |
| 363 | [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ | 521 | [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ |
| 522 | [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ | ||
| 364 | [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ | 523 | [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ |
| 365 | [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ | 524 | [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ |
| 366 | [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ | 525 | [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ |
| 367 | [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ | 526 | [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ |
| 368 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ | 527 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ |
| 528 | [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */ | ||
| 529 | [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ | ||
| 530 | [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ | ||
| 531 | [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ | ||
| 532 | [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */ | ||
| 533 | [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ | ||
| 534 | [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ | ||
| 535 | [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ | ||
| 369 | [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ | 536 | [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ |
| 537 | [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */ | ||
| 370 | }; | 538 | }; |
| 371 | 539 | ||
| 372 | static struct clk_lookup lookups[] = { | 540 | static struct clk_lookup lookups[] = { |
| @@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = { | |||
| 386 | CLKDEV_CON_ID("pll2s", &pll2s_clk), | 554 | CLKDEV_CON_ID("pll2s", &pll2s_clk), |
| 387 | CLKDEV_CON_ID("pll2h", &pll2h_clk), | 555 | CLKDEV_CON_ID("pll2h", &pll2h_clk), |
| 388 | 556 | ||
| 557 | /* CPU clock */ | ||
| 558 | CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk), | ||
| 559 | |||
| 389 | /* DIV6 */ | 560 | /* DIV6 */ |
| 390 | CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), | 561 | CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), |
| 391 | CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), | 562 | CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), |
| @@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = { | |||
| 408 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), | 579 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), |
| 409 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), | 580 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), |
| 410 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 581 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
| 582 | CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), | ||
| 411 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), | 583 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), |
| 412 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), | 584 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), |
| 413 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), | 585 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), |
| @@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = { | |||
| 418 | CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), | 590 | CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), |
| 419 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), | 591 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), |
| 420 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), | 592 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), |
| 593 | CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), | ||
| 594 | CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), | ||
| 595 | CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), | ||
| 596 | CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), | ||
| 597 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), | ||
| 598 | CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), | ||
| 599 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), | ||
| 600 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), | ||
| 601 | CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]), | ||
| 421 | 602 | ||
| 422 | /* for DT */ | 603 | /* for DT */ |
| 423 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), | 604 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), |
| @@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void) | |||
| 429 | int k, ret = 0; | 610 | int k, ret = 0; |
| 430 | u32 ckscr; | 611 | u32 ckscr; |
| 431 | 612 | ||
| 613 | atomic_set(&frqcr_lock, -1); | ||
| 614 | |||
| 432 | reg = ioremap_nocache(CKSCR, PAGE_SIZE); | 615 | reg = ioremap_nocache(CKSCR, PAGE_SIZE); |
| 433 | BUG_ON(!reg); | 616 | BUG_ON(!reg); |
| 434 | ckscr = ioread32(reg); | 617 | ckscr = ioread32(reg); |
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index f4265e52432c..c826bca4024e 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
| @@ -597,6 +597,7 @@ static struct clk_lookup lookups[] = { | |||
| 597 | CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), | 597 | CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), |
| 598 | CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), | 598 | CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), |
| 599 | CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), | 599 | CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), |
| 600 | CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), | ||
| 600 | 601 | ||
| 601 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), | 602 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), |
| 602 | CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), | 603 | CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), |
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 5d71313df52d..fc36d3db0b4d 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <linux/clkdev.h> | 24 | #include <linux/clkdev.h> |
| 25 | #include <mach/clock.h> | 25 | #include <mach/clock.h> |
| 26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 27 | #include <mach/r8a7790.h> | ||
| 27 | 28 | ||
| 28 | /* | 29 | /* |
| 29 | * MD EXTAL PLL0 PLL1 PLL3 | 30 | * MD EXTAL PLL0 PLL1 PLL3 |
| @@ -42,16 +43,16 @@ | |||
| 42 | * see "p1 / 2" on R8A7790_CLOCK_ROOT() below | 43 | * see "p1 / 2" on R8A7790_CLOCK_ROOT() below |
| 43 | */ | 44 | */ |
| 44 | 45 | ||
| 45 | #define MD(nr) (1 << nr) | ||
| 46 | |||
| 47 | #define CPG_BASE 0xe6150000 | 46 | #define CPG_BASE 0xe6150000 |
| 48 | #define CPG_LEN 0x1000 | 47 | #define CPG_LEN 0x1000 |
| 49 | 48 | ||
| 49 | #define SMSTPCR1 0xe6150134 | ||
| 50 | #define SMSTPCR2 0xe6150138 | 50 | #define SMSTPCR2 0xe6150138 |
| 51 | #define SMSTPCR3 0xe615013c | 51 | #define SMSTPCR3 0xe615013c |
| 52 | #define SMSTPCR5 0xe6150144 | ||
| 52 | #define SMSTPCR7 0xe615014c | 53 | #define SMSTPCR7 0xe615014c |
| 54 | #define SMSTPCR8 0xe6150990 | ||
| 53 | 55 | ||
| 54 | #define MODEMR 0xE6160060 | ||
| 55 | #define SDCKCR 0xE6150074 | 56 | #define SDCKCR 0xE6150074 |
| 56 | #define SD2CKCR 0xE6150078 | 57 | #define SD2CKCR 0xE6150078 |
| 57 | #define SD3CKCR 0xE615007C | 58 | #define SD3CKCR 0xE615007C |
| @@ -180,16 +181,23 @@ static struct clk div6_clks[DIV6_NR] = { | |||
| 180 | 181 | ||
| 181 | /* MSTP */ | 182 | /* MSTP */ |
| 182 | enum { | 183 | enum { |
| 184 | MSTP813, | ||
| 183 | MSTP721, MSTP720, | 185 | MSTP721, MSTP720, |
| 184 | MSTP717, MSTP716, | 186 | MSTP717, MSTP716, |
| 187 | MSTP522, | ||
| 185 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, | 188 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, |
| 186 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, | 189 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, |
| 190 | MSTP124, | ||
| 187 | MSTP_NR | 191 | MSTP_NR |
| 188 | }; | 192 | }; |
| 189 | 193 | ||
| 190 | static struct clk mstp_clks[MSTP_NR] = { | 194 | static struct clk mstp_clks[MSTP_NR] = { |
| 195 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | ||
| 191 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | 196 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ |
| 192 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 197 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
| 198 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ | ||
| 199 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ | ||
| 200 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ | ||
| 193 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ | 201 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ |
| 194 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ | 202 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ |
| 195 | [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ | 203 | [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ |
| @@ -203,8 +211,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 203 | [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ | 211 | [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ |
| 204 | [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ | 212 | [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ |
| 205 | [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ | 213 | [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ |
| 206 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ | 214 | [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ |
| 207 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ | ||
| 208 | }; | 215 | }; |
| 209 | 216 | ||
| 210 | static struct clk_lookup lookups[] = { | 217 | static struct clk_lookup lookups[] = { |
| @@ -254,6 +261,8 @@ static struct clk_lookup lookups[] = { | |||
| 254 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), | 261 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), |
| 255 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), | 262 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), |
| 256 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), | 263 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), |
| 264 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), | ||
| 265 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | ||
| 257 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), | 266 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), |
| 258 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), | 267 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), |
| 259 | CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), | 268 | CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), |
| @@ -266,6 +275,7 @@ static struct clk_lookup lookups[] = { | |||
| 266 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), | 275 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), |
| 267 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), | 276 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), |
| 268 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), | 277 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), |
| 278 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | ||
| 269 | }; | 279 | }; |
| 270 | 280 | ||
| 271 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | 281 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
| @@ -280,14 +290,9 @@ static struct clk_lookup lookups[] = { | |||
| 280 | 290 | ||
| 281 | void __init r8a7790_clock_init(void) | 291 | void __init r8a7790_clock_init(void) |
| 282 | { | 292 | { |
| 283 | void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); | 293 | u32 mode = r8a7790_read_mode_pins(); |
| 284 | u32 mode; | ||
| 285 | int k, ret = 0; | 294 | int k, ret = 0; |
| 286 | 295 | ||
| 287 | BUG_ON(!modemr); | ||
| 288 | mode = ioread32(modemr); | ||
| 289 | iounmap(modemr); | ||
| 290 | |||
| 291 | switch (mode & (MD(14) | MD(13))) { | 296 | switch (mode & (MD(14) | MD(13))) { |
| 292 | case 0: | 297 | case 0: |
| 293 | R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); | 298 | R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); |
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h index b0ab4b72770a..c2eb7568d9be 100644 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ b/arch/arm/mach-shmobile/include/mach/emev2.h | |||
| @@ -5,7 +5,6 @@ extern void emev2_map_io(void); | |||
| 5 | extern void emev2_init_delay(void); | 5 | extern void emev2_init_delay(void); |
| 6 | extern void emev2_add_standard_devices(void); | 6 | extern void emev2_add_standard_devices(void); |
| 7 | extern void emev2_clock_init(void); | 7 | extern void emev2_clock_init(void); |
| 8 | extern void emev2_set_boot_vector(unsigned long value); | ||
| 9 | 8 | ||
| 10 | #define EMEV2_GPIO_BASE 200 | 9 | #define EMEV2_GPIO_BASE 200 |
| 11 | #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) | 10 | #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index f043103e32c9..144a85e29245 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h | |||
| @@ -4,5 +4,6 @@ | |||
| 4 | void r8a73a4_add_standard_devices(void); | 4 | void r8a73a4_add_standard_devices(void); |
| 5 | void r8a73a4_clock_init(void); | 5 | void r8a73a4_clock_init(void); |
| 6 | void r8a73a4_pinmux_init(void); | 6 | void r8a73a4_pinmux_init(void); |
| 7 | void r8a73a4_init_delay(void); | ||
| 7 | 8 | ||
| 8 | #endif /* __ASM_R8A73A4_H__ */ | 9 | #endif /* __ASM_R8A73A4_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index b34d19b5ca5c..56f375005fcd 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h | |||
| @@ -42,6 +42,8 @@ enum { | |||
| 42 | SHDMA_SLAVE_FSIB_TX, | 42 | SHDMA_SLAVE_FSIB_TX, |
| 43 | SHDMA_SLAVE_USBHS_TX, | 43 | SHDMA_SLAVE_USBHS_TX, |
| 44 | SHDMA_SLAVE_USBHS_RX, | 44 | SHDMA_SLAVE_USBHS_RX, |
| 45 | SHDMA_SLAVE_MMCIF_TX, | ||
| 46 | SHDMA_SLAVE_MMCIF_RX, | ||
| 45 | }; | 47 | }; |
| 46 | 48 | ||
| 47 | extern void r8a7740_meram_workaround(void); | 49 | extern void r8a7740_meram_workaround(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 2e919e61fa0d..7aaef409a059 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h | |||
| @@ -4,6 +4,10 @@ | |||
| 4 | void r8a7790_add_standard_devices(void); | 4 | void r8a7790_add_standard_devices(void); |
| 5 | void r8a7790_clock_init(void); | 5 | void r8a7790_clock_init(void); |
| 6 | void r8a7790_pinmux_init(void); | 6 | void r8a7790_pinmux_init(void); |
| 7 | void r8a7790_init_delay(void); | ||
| 7 | void r8a7790_timer_init(void); | 8 | void r8a7790_timer_init(void); |
| 8 | 9 | ||
| 10 | #define MD(nr) BIT(nr) | ||
| 11 | u32 r8a7790_read_mode_pins(void); | ||
| 12 | |||
| 9 | #endif /* __ASM_R8A7790_H__ */ | 13 | #endif /* __ASM_R8A7790_H__ */ |
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index a8c4e41bf27a..d533bd23865c 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
| 23 | #include <linux/platform_data/irq-renesas-irqc.h> | 23 | #include <linux/platform_data/irq-renesas-irqc.h> |
| 24 | #include <linux/serial_sci.h> | 24 | #include <linux/serial_sci.h> |
| 25 | #include <linux/sh_timer.h> | ||
| 25 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 26 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
| 27 | #include <mach/r8a73a4.h> | 28 | #include <mach/r8a73a4.h> |
| @@ -168,6 +169,25 @@ static const struct resource thermal0_resources[] = { | |||
| 168 | thermal0_resources, \ | 169 | thermal0_resources, \ |
| 169 | ARRAY_SIZE(thermal0_resources)) | 170 | ARRAY_SIZE(thermal0_resources)) |
| 170 | 171 | ||
| 172 | static struct sh_timer_config cmt10_platform_data = { | ||
| 173 | .name = "CMT10", | ||
| 174 | .timer_bit = 0, | ||
| 175 | .clockevent_rating = 80, | ||
| 176 | }; | ||
| 177 | |||
| 178 | static struct resource cmt10_resources[] = { | ||
| 179 | DEFINE_RES_MEM(0xe6130010, 0x0c), | ||
| 180 | DEFINE_RES_MEM(0xe6130000, 0x04), | ||
| 181 | DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */ | ||
| 182 | }; | ||
| 183 | |||
| 184 | #define r8a7790_register_cmt(idx) \ | ||
| 185 | platform_device_register_resndata(&platform_bus, "sh_cmt", \ | ||
| 186 | idx, cmt##idx##_resources, \ | ||
| 187 | ARRAY_SIZE(cmt##idx##_resources), \ | ||
| 188 | &cmt##idx##_platform_data, \ | ||
| 189 | sizeof(struct sh_timer_config)) | ||
| 190 | |||
| 171 | void __init r8a73a4_add_standard_devices(void) | 191 | void __init r8a73a4_add_standard_devices(void) |
| 172 | { | 192 | { |
| 173 | r8a73a4_register_scif(SCIFA0); | 193 | r8a73a4_register_scif(SCIFA0); |
| @@ -179,11 +199,20 @@ void __init r8a73a4_add_standard_devices(void) | |||
| 179 | r8a73a4_register_irqc(0); | 199 | r8a73a4_register_irqc(0); |
| 180 | r8a73a4_register_irqc(1); | 200 | r8a73a4_register_irqc(1); |
| 181 | r8a73a4_register_thermal(); | 201 | r8a73a4_register_thermal(); |
| 202 | r8a7790_register_cmt(10); | ||
| 203 | } | ||
| 204 | |||
| 205 | void __init r8a73a4_init_delay(void) | ||
| 206 | { | ||
| 207 | #ifndef CONFIG_ARM_ARCH_TIMER | ||
| 208 | shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ | ||
| 209 | #endif | ||
| 182 | } | 210 | } |
| 183 | 211 | ||
| 184 | #ifdef CONFIG_USE_OF | 212 | #ifdef CONFIG_USE_OF |
| 185 | void __init r8a73a4_add_standard_devices_dt(void) | 213 | void __init r8a73a4_add_standard_devices_dt(void) |
| 186 | { | 214 | { |
| 215 | platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0); | ||
| 187 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 216 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 188 | } | 217 | } |
| 189 | 218 | ||
| @@ -193,6 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { | |||
| 193 | }; | 222 | }; |
| 194 | 223 | ||
| 195 | DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") | 224 | DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") |
| 225 | .init_early = r8a73a4_init_delay, | ||
| 196 | .init_machine = r8a73a4_add_standard_devices_dt, | 226 | .init_machine = r8a73a4_add_standard_devices_dt, |
| 197 | .init_time = shmobile_timer_init, | 227 | .init_time = shmobile_timer_init, |
| 198 | .dt_compat = r8a73a4_boards_compat_dt, | 228 | .dt_compat = r8a73a4_boards_compat_dt, |
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index ac29c2ee011f..84c5bb6d9725 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
| @@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { | |||
| 588 | .addr = 0xfe1f0064, | 588 | .addr = 0xfe1f0064, |
| 589 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | 589 | .chcr = CHCR_TX(XMIT_SZ_32BIT), |
| 590 | .mid_rid = 0xb5, | 590 | .mid_rid = 0xb5, |
| 591 | }, { | ||
| 592 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
| 593 | .addr = 0xe6bd0034, | ||
| 594 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | ||
| 595 | .mid_rid = 0xd1, | ||
| 596 | }, { | ||
| 597 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
| 598 | .addr = 0xe6bd0034, | ||
| 599 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | ||
| 600 | .mid_rid = 0xd2, | ||
| 591 | }, | 601 | }, |
| 592 | }; | 602 | }; |
| 593 | 603 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index b7e78b9a7fdf..4c96dad21195 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
| @@ -21,9 +21,10 @@ | |||
| 21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
| 22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
| 24 | #include <linux/serial_sci.h> | ||
| 25 | #include <linux/platform_data/gpio-rcar.h> | 24 | #include <linux/platform_data/gpio-rcar.h> |
| 26 | #include <linux/platform_data/irq-renesas-irqc.h> | 25 | #include <linux/platform_data/irq-renesas-irqc.h> |
| 26 | #include <linux/serial_sci.h> | ||
| 27 | #include <linux/sh_timer.h> | ||
| 27 | #include <mach/common.h> | 28 | #include <mach/common.h> |
| 28 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
| 29 | #include <mach/r8a7790.h> | 30 | #include <mach/r8a7790.h> |
| @@ -148,6 +149,36 @@ static struct resource irqc0_resources[] __initdata = { | |||
| 148 | &irqc##idx##_data, \ | 149 | &irqc##idx##_data, \ |
| 149 | sizeof(struct renesas_irqc_config)) | 150 | sizeof(struct renesas_irqc_config)) |
| 150 | 151 | ||
| 152 | static struct resource thermal_resources[] __initdata = { | ||
| 153 | DEFINE_RES_MEM(0xe61f0000, 0x14), | ||
| 154 | DEFINE_RES_MEM(0xe61f0100, 0x38), | ||
| 155 | DEFINE_RES_IRQ(gic_spi(69)), | ||
| 156 | }; | ||
| 157 | |||
| 158 | #define r8a7790_register_thermal() \ | ||
| 159 | platform_device_register_simple("rcar_thermal", -1, \ | ||
| 160 | thermal_resources, \ | ||
| 161 | ARRAY_SIZE(thermal_resources)) | ||
| 162 | |||
| 163 | static struct sh_timer_config cmt00_platform_data = { | ||
| 164 | .name = "CMT00", | ||
| 165 | .timer_bit = 0, | ||
| 166 | .clockevent_rating = 80, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct resource cmt00_resources[] = { | ||
| 170 | DEFINE_RES_MEM(0xffca0510, 0x0c), | ||
| 171 | DEFINE_RES_MEM(0xffca0500, 0x04), | ||
| 172 | DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ | ||
| 173 | }; | ||
| 174 | |||
| 175 | #define r8a7790_register_cmt(idx) \ | ||
| 176 | platform_device_register_resndata(&platform_bus, "sh_cmt", \ | ||
| 177 | idx, cmt##idx##_resources, \ | ||
| 178 | ARRAY_SIZE(cmt##idx##_resources), \ | ||
| 179 | &cmt##idx##_platform_data, \ | ||
| 180 | sizeof(struct sh_timer_config)) | ||
| 181 | |||
| 151 | void __init r8a7790_add_standard_devices(void) | 182 | void __init r8a7790_add_standard_devices(void) |
| 152 | { | 183 | { |
| 153 | r8a7790_register_scif(SCIFA0); | 184 | r8a7790_register_scif(SCIFA0); |
| @@ -161,20 +192,82 @@ void __init r8a7790_add_standard_devices(void) | |||
| 161 | r8a7790_register_scif(HSCIF0); | 192 | r8a7790_register_scif(HSCIF0); |
| 162 | r8a7790_register_scif(HSCIF1); | 193 | r8a7790_register_scif(HSCIF1); |
| 163 | r8a7790_register_irqc(0); | 194 | r8a7790_register_irqc(0); |
| 195 | r8a7790_register_thermal(); | ||
| 196 | r8a7790_register_cmt(00); | ||
| 164 | } | 197 | } |
| 165 | 198 | ||
| 199 | #define MODEMR 0xe6160060 | ||
| 200 | |||
| 201 | u32 __init r8a7790_read_mode_pins(void) | ||
| 202 | { | ||
| 203 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | ||
| 204 | u32 mode; | ||
| 205 | |||
| 206 | BUG_ON(!modemr); | ||
| 207 | mode = ioread32(modemr); | ||
| 208 | iounmap(modemr); | ||
| 209 | |||
| 210 | return mode; | ||
| 211 | } | ||
| 212 | |||
| 213 | #define CNTCR 0 | ||
| 214 | #define CNTFID0 0x20 | ||
| 215 | |||
| 166 | void __init r8a7790_timer_init(void) | 216 | void __init r8a7790_timer_init(void) |
| 167 | { | 217 | { |
| 168 | void __iomem *cntcr; | 218 | #ifdef CONFIG_ARM_ARCH_TIMER |
| 219 | u32 mode = r8a7790_read_mode_pins(); | ||
| 220 | void __iomem *base; | ||
| 221 | int extal_mhz = 0; | ||
| 222 | u32 freq; | ||
| 223 | |||
| 224 | /* At Linux boot time the r8a7790 arch timer comes up | ||
| 225 | * with the counter disabled. Moreover, it may also report | ||
| 226 | * a potentially incorrect fixed 13 MHz frequency. To be | ||
| 227 | * correct these registers need to be updated to use the | ||
| 228 | * frequency EXTAL / 2 which can be determined by the MD pins. | ||
| 229 | */ | ||
| 230 | |||
| 231 | switch (mode & (MD(14) | MD(13))) { | ||
| 232 | case 0: | ||
| 233 | extal_mhz = 15; | ||
| 234 | break; | ||
| 235 | case MD(13): | ||
| 236 | extal_mhz = 20; | ||
| 237 | break; | ||
| 238 | case MD(14): | ||
| 239 | extal_mhz = 26; | ||
| 240 | break; | ||
| 241 | case MD(13) | MD(14): | ||
| 242 | extal_mhz = 30; | ||
| 243 | break; | ||
| 244 | } | ||
| 169 | 245 | ||
| 170 | /* make sure arch timer is started by setting bit 0 of CNTCT */ | 246 | /* The arch timer frequency equals EXTAL / 2 */ |
| 171 | cntcr = ioremap(0xe6080000, PAGE_SIZE); | 247 | freq = extal_mhz * (1000000 / 2); |
| 172 | iowrite32(1, cntcr); | 248 | |
| 173 | iounmap(cntcr); | 249 | /* Remap "armgcnt address map" space */ |
| 250 | base = ioremap(0xe6080000, PAGE_SIZE); | ||
| 251 | |||
| 252 | /* Update registers with correct frequency */ | ||
| 253 | iowrite32(freq, base + CNTFID0); | ||
| 254 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | ||
| 255 | |||
| 256 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
| 257 | iowrite32(1, base + CNTCR); | ||
| 258 | iounmap(base); | ||
| 259 | #endif /* CONFIG_ARM_ARCH_TIMER */ | ||
| 174 | 260 | ||
| 175 | shmobile_timer_init(); | 261 | shmobile_timer_init(); |
| 176 | } | 262 | } |
| 177 | 263 | ||
| 264 | void __init r8a7790_init_delay(void) | ||
| 265 | { | ||
| 266 | #ifndef CONFIG_ARM_ARCH_TIMER | ||
| 267 | shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ | ||
| 268 | #endif | ||
| 269 | } | ||
| 270 | |||
| 178 | #ifdef CONFIG_USE_OF | 271 | #ifdef CONFIG_USE_OF |
| 179 | 272 | ||
| 180 | static const char *r8a7790_boards_compat_dt[] __initdata = { | 273 | static const char *r8a7790_boards_compat_dt[] __initdata = { |
| @@ -183,6 +276,7 @@ static const char *r8a7790_boards_compat_dt[] __initdata = { | |||
| 183 | }; | 276 | }; |
| 184 | 277 | ||
| 185 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") | 278 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") |
| 279 | .init_early = r8a7790_init_delay, | ||
| 186 | .init_time = r8a7790_timer_init, | 280 | .init_time = r8a7790_timer_init, |
| 187 | .dt_compat = r8a7790_boards_compat_dt, | 281 | .dt_compat = r8a7790_boards_compat_dt, |
| 188 | MACHINE_END | 282 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 1fcd607d64ad..78e84c582453 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c | |||
| @@ -29,6 +29,8 @@ | |||
| 29 | #include <asm/smp_scu.h> | 29 | #include <asm/smp_scu.h> |
| 30 | 30 | ||
| 31 | #define EMEV2_SCU_BASE 0x1e000000 | 31 | #define EMEV2_SCU_BASE 0x1e000000 |
| 32 | #define EMEV2_SMU_BASE 0xe0110000 | ||
| 33 | #define SMU_GENERAL_REG0 0x7c0 | ||
| 32 | 34 | ||
| 33 | static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) | 35 | static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 34 | { | 36 | { |
| @@ -38,13 +40,18 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 38 | 40 | ||
| 39 | static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) | 41 | static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) |
| 40 | { | 42 | { |
| 43 | void __iomem *smu; | ||
| 44 | |||
| 41 | /* setup EMEV2 specific SCU base, enable */ | 45 | /* setup EMEV2 specific SCU base, enable */ |
| 42 | shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); | 46 | shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); |
| 43 | scu_enable(shmobile_scu_base); | 47 | scu_enable(shmobile_scu_base); |
| 44 | 48 | ||
| 45 | /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ | 49 | /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ |
| 46 | emev2_clock_init(); /* need ioremapped SMU */ | 50 | smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); |
| 47 | emev2_set_boot_vector(__pa(shmobile_boot_vector)); | 51 | if (smu) { |
| 52 | iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0); | ||
| 53 | iounmap(smu); | ||
| 54 | } | ||
| 48 | shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); | 55 | shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); |
| 49 | shmobile_boot_arg = (unsigned long)shmobile_scu_base; | 56 | shmobile_boot_arg = (unsigned long)shmobile_scu_base; |
| 50 | 57 | ||
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 5b045e302b43..3ab2f65f8a50 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig | |||
| @@ -10,3 +10,5 @@ config ARCH_SUNXI | |||
| 10 | select SPARSE_IRQ | 10 | select SPARSE_IRQ |
| 11 | select SUN4I_TIMER | 11 | select SUN4I_TIMER |
| 12 | select PINCTRL_SUNXI | 12 | select PINCTRL_SUNXI |
| 13 | select ARM_GIC | ||
| 14 | select HAVE_SMP | ||
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot deleted file mode 100644 index 46d4cf0841c0..000000000000 --- a/arch/arm/mach-sunxi/Makefile.boot +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000 | ||
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 38a3c55527c8..e79fb3469341 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c | |||
| @@ -27,10 +27,19 @@ | |||
| 27 | #include <asm/system_misc.h> | 27 | #include <asm/system_misc.h> |
| 28 | 28 | ||
| 29 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 | 29 | #define SUN4I_WATCHDOG_CTRL_REG 0x00 |
| 30 | #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) | 30 | #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) |
| 31 | #define SUN4I_WATCHDOG_MODE_REG 0x04 | 31 | #define SUN4I_WATCHDOG_MODE_REG 0x04 |
| 32 | #define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) | 32 | #define SUN4I_WATCHDOG_MODE_ENABLE BIT(0) |
| 33 | #define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) | 33 | #define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1) |
| 34 | |||
| 35 | #define SUN6I_WATCHDOG1_IRQ_REG 0x00 | ||
| 36 | #define SUN6I_WATCHDOG1_CTRL_REG 0x10 | ||
| 37 | #define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0) | ||
| 38 | #define SUN6I_WATCHDOG1_CONFIG_REG 0x14 | ||
| 39 | #define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0) | ||
| 40 | #define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1) | ||
| 41 | #define SUN6I_WATCHDOG1_MODE_REG 0x18 | ||
| 42 | #define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0) | ||
| 34 | 43 | ||
| 35 | static void __iomem *wdt_base; | 44 | static void __iomem *wdt_base; |
| 36 | 45 | ||
| @@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd) | |||
| 56 | } | 65 | } |
| 57 | } | 66 | } |
| 58 | 67 | ||
| 68 | static void sun6i_restart(enum reboot_mode mode, const char *cmd) | ||
| 69 | { | ||
| 70 | if (!wdt_base) | ||
| 71 | return; | ||
| 72 | |||
| 73 | /* Disable interrupts */ | ||
| 74 | writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG); | ||
| 75 | |||
| 76 | /* We want to disable the IRQ and just reset the whole system */ | ||
| 77 | writel(SUN6I_WATCHDOG1_CONFIG_RESTART, | ||
| 78 | wdt_base + SUN6I_WATCHDOG1_CONFIG_REG); | ||
| 79 | |||
| 80 | /* Enable timer. The default and lowest interval value is 0.5s */ | ||
| 81 | writel(SUN6I_WATCHDOG1_MODE_ENABLE, | ||
| 82 | wdt_base + SUN6I_WATCHDOG1_MODE_REG); | ||
| 83 | |||
| 84 | /* Restart the watchdog. */ | ||
| 85 | writel(SUN6I_WATCHDOG1_CTRL_RESTART, | ||
| 86 | wdt_base + SUN6I_WATCHDOG1_CTRL_REG); | ||
| 87 | |||
| 88 | while (1) { | ||
| 89 | mdelay(5); | ||
| 90 | writel(SUN6I_WATCHDOG1_MODE_ENABLE, | ||
| 91 | wdt_base + SUN6I_WATCHDOG1_MODE_REG); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 59 | static struct of_device_id sunxi_restart_ids[] = { | 95 | static struct of_device_id sunxi_restart_ids[] = { |
| 60 | { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, | 96 | { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, |
| 97 | { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, | ||
| 61 | { /*sentinel*/ } | 98 | { /*sentinel*/ } |
| 62 | }; | 99 | }; |
| 63 | 100 | ||
| @@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = { | |||
| 96 | "allwinner,sun4i-a10", | 133 | "allwinner,sun4i-a10", |
| 97 | "allwinner,sun5i-a10s", | 134 | "allwinner,sun5i-a10s", |
| 98 | "allwinner,sun5i-a13", | 135 | "allwinner,sun5i-a13", |
| 136 | "allwinner,sun6i-a31", | ||
| 137 | "allwinner,sun7i-a20", | ||
| 99 | NULL, | 138 | NULL, |
| 100 | }; | 139 | }; |
| 101 | 140 | ||
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 59925cc896fb..67a76f2dfb9f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
| @@ -2,18 +2,25 @@ config ARCH_TEGRA | |||
| 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 | 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
| 3 | select ARCH_HAS_CPUFREQ | 3 | select ARCH_HAS_CPUFREQ |
| 4 | select ARCH_REQUIRE_GPIOLIB | 4 | select ARCH_REQUIRE_GPIOLIB |
| 5 | select ARM_GIC | ||
| 5 | select CLKDEV_LOOKUP | 6 | select CLKDEV_LOOKUP |
| 6 | select CLKSRC_MMIO | 7 | select CLKSRC_MMIO |
| 7 | select CLKSRC_OF | 8 | select CLKSRC_OF |
| 8 | select COMMON_CLK | 9 | select COMMON_CLK |
| 10 | select CPU_V7 | ||
| 9 | select GENERIC_CLOCKEVENTS | 11 | select GENERIC_CLOCKEVENTS |
| 10 | select HAVE_ARM_SCU if SMP | 12 | select HAVE_ARM_SCU if SMP |
| 11 | select HAVE_ARM_TWD if SMP | 13 | select HAVE_ARM_TWD if SMP |
| 12 | select HAVE_CLK | 14 | select HAVE_CLK |
| 13 | select HAVE_SMP | 15 | select HAVE_SMP |
| 14 | select MIGHT_HAVE_CACHE_L2X0 | 16 | select MIGHT_HAVE_CACHE_L2X0 |
| 17 | select MIGHT_HAVE_PCI | ||
| 18 | select PINCTRL | ||
| 15 | select SOC_BUS | 19 | select SOC_BUS |
| 16 | select SPARSE_IRQ | 20 | select SPARSE_IRQ |
| 21 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | ||
| 22 | select USB_ULPI if USB_PHY | ||
| 23 | select USB_ULPI_VIEWPORT if USB_PHY | ||
| 17 | select USE_OF | 24 | select USE_OF |
| 18 | help | 25 | help |
| 19 | This enables support for NVIDIA Tegra based systems. | 26 | This enables support for NVIDIA Tegra based systems. |
| @@ -27,15 +34,9 @@ config ARCH_TEGRA_2x_SOC | |||
| 27 | select ARM_ERRATA_720789 | 34 | select ARM_ERRATA_720789 |
| 28 | select ARM_ERRATA_754327 if SMP | 35 | select ARM_ERRATA_754327 if SMP |
| 29 | select ARM_ERRATA_764369 if SMP | 36 | select ARM_ERRATA_764369 if SMP |
| 30 | select ARM_GIC | ||
| 31 | select CPU_V7 | ||
| 32 | select PINCTRL | ||
| 33 | select PINCTRL_TEGRA20 | 37 | select PINCTRL_TEGRA20 |
| 34 | select PL310_ERRATA_727915 if CACHE_L2X0 | 38 | select PL310_ERRATA_727915 if CACHE_L2X0 |
| 35 | select PL310_ERRATA_769419 if CACHE_L2X0 | 39 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 36 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | ||
| 37 | select USB_ULPI if USB_PHY | ||
| 38 | select USB_ULPI_VIEWPORT if USB_PHY | ||
| 39 | help | 40 | help |
| 40 | Support for NVIDIA Tegra AP20 and T20 processors, based on the | 41 | Support for NVIDIA Tegra AP20 and T20 processors, based on the |
| 41 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 42 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| @@ -44,14 +45,8 @@ config ARCH_TEGRA_3x_SOC | |||
| 44 | bool "Enable support for Tegra30 family" | 45 | bool "Enable support for Tegra30 family" |
| 45 | select ARM_ERRATA_754322 | 46 | select ARM_ERRATA_754322 |
| 46 | select ARM_ERRATA_764369 if SMP | 47 | select ARM_ERRATA_764369 if SMP |
| 47 | select ARM_GIC | ||
| 48 | select CPU_V7 | ||
| 49 | select PINCTRL | ||
| 50 | select PINCTRL_TEGRA30 | 48 | select PINCTRL_TEGRA30 |
| 51 | select PL310_ERRATA_769419 if CACHE_L2X0 | 49 | select PL310_ERRATA_769419 if CACHE_L2X0 |
| 52 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | ||
| 53 | select USB_ULPI if USB_PHY | ||
| 54 | select USB_ULPI_VIEWPORT if USB_PHY | ||
| 55 | help | 50 | help |
| 56 | Support for NVIDIA Tegra T30 processor family, based on the | 51 | Support for NVIDIA Tegra T30 processor family, based on the |
| 57 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller | 52 | ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| @@ -59,20 +54,13 @@ config ARCH_TEGRA_3x_SOC | |||
| 59 | config ARCH_TEGRA_114_SOC | 54 | config ARCH_TEGRA_114_SOC |
| 60 | bool "Enable support for Tegra114 family" | 55 | bool "Enable support for Tegra114 family" |
| 61 | select HAVE_ARM_ARCH_TIMER | 56 | select HAVE_ARM_ARCH_TIMER |
| 62 | select ARM_GIC | 57 | select ARM_ERRATA_798181 |
| 63 | select ARM_L1_CACHE_SHIFT_6 | 58 | select ARM_L1_CACHE_SHIFT_6 |
| 64 | select CPU_V7 | ||
| 65 | select PINCTRL | ||
| 66 | select PINCTRL_TEGRA114 | 59 | select PINCTRL_TEGRA114 |
| 67 | help | 60 | help |
| 68 | Support for NVIDIA Tegra T114 processor family, based on the | 61 | Support for NVIDIA Tegra T114 processor family, based on the |
| 69 | ARM CortexA15MP CPU | 62 | ARM CortexA15MP CPU |
| 70 | 63 | ||
| 71 | config TEGRA_PCI | ||
| 72 | bool "PCI Express support" | ||
| 73 | depends on ARCH_TEGRA_2x_SOC | ||
| 74 | select PCI | ||
| 75 | |||
| 76 | config TEGRA_AHB | 64 | config TEGRA_AHB |
| 77 | bool "Enable AHB driver for NVIDIA Tegra SoCs" | 65 | bool "Enable AHB driver for NVIDIA Tegra SoCs" |
| 78 | default y | 66 | default y |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 98b184efc110..e7e5f45c6558 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
| @@ -17,24 +17,24 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o | |||
| 17 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o | 17 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o |
| 18 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o | 18 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o |
| 19 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o | 19 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o |
| 20 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o | ||
| 20 | ifeq ($(CONFIG_CPU_IDLE),y) | 21 | ifeq ($(CONFIG_CPU_IDLE),y) |
| 21 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o | 22 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o |
| 22 | endif | 23 | endif |
| 23 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o | 24 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o |
| 24 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o | 25 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o |
| 26 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o | ||
| 25 | ifeq ($(CONFIG_CPU_IDLE),y) | 27 | ifeq ($(CONFIG_CPU_IDLE),y) |
| 26 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o | 28 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o |
| 27 | endif | 29 | endif |
| 28 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 30 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 29 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 31 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 30 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | ||
| 31 | 32 | ||
| 32 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o | 33 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o |
| 33 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o | 34 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o |
| 35 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o | ||
| 34 | ifeq ($(CONFIG_CPU_IDLE),y) | 36 | ifeq ($(CONFIG_CPU_IDLE),y) |
| 35 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o | 37 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o |
| 36 | endif | 38 | endif |
| 37 | 39 | ||
| 38 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o | ||
| 39 | |||
| 40 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o | 40 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o |
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c deleted file mode 100644 index 035b240b9e15..000000000000 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ /dev/null | |||
| @@ -1,89 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-tegra/board-harmony-pcie.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 CompuLab, Ltd. | ||
| 5 | * Mike Rapoport <mike@compulab.co.il> | ||
| 6 | * | ||
| 7 | * This software is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2, as published by the Free Software Foundation, and | ||
| 9 | * may be copied, distributed, and modified under those terms. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/gpio.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/of_gpio.h> | ||
| 22 | #include <linux/regulator/consumer.h> | ||
| 23 | |||
| 24 | #include <asm/mach-types.h> | ||
| 25 | |||
| 26 | #include "board.h" | ||
| 27 | |||
| 28 | #ifdef CONFIG_TEGRA_PCI | ||
| 29 | |||
| 30 | int __init harmony_pcie_init(void) | ||
| 31 | { | ||
| 32 | struct device_node *np; | ||
| 33 | int en_vdd_1v05; | ||
| 34 | struct regulator *regulator = NULL; | ||
| 35 | int err; | ||
| 36 | |||
| 37 | np = of_find_node_by_path("/regulators/regulator@3"); | ||
| 38 | if (!np) { | ||
| 39 | pr_err("%s: of_find_node_by_path failed\n", __func__); | ||
| 40 | return -ENODEV; | ||
| 41 | } | ||
| 42 | |||
| 43 | en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0); | ||
| 44 | if (en_vdd_1v05 < 0) { | ||
| 45 | pr_err("%s: of_get_named_gpio failed: %d\n", __func__, | ||
| 46 | en_vdd_1v05); | ||
| 47 | return en_vdd_1v05; | ||
| 48 | } | ||
| 49 | |||
| 50 | err = gpio_request(en_vdd_1v05, "EN_VDD_1V05"); | ||
| 51 | if (err) { | ||
| 52 | pr_err("%s: gpio_request failed: %d\n", __func__, err); | ||
| 53 | return err; | ||
| 54 | } | ||
| 55 | |||
| 56 | gpio_direction_output(en_vdd_1v05, 1); | ||
| 57 | |||
| 58 | regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk"); | ||
| 59 | if (IS_ERR(regulator)) { | ||
| 60 | err = PTR_ERR(regulator); | ||
| 61 | pr_err("%s: regulator_get failed: %d\n", __func__, err); | ||
| 62 | goto err_reg; | ||
| 63 | } | ||
| 64 | |||
| 65 | err = regulator_enable(regulator); | ||
| 66 | if (err) { | ||
| 67 | pr_err("%s: regulator_enable failed: %d\n", __func__, err); | ||
| 68 | goto err_en; | ||
| 69 | } | ||
| 70 | |||
| 71 | err = tegra_pcie_init(true, true); | ||
| 72 | if (err) { | ||
| 73 | pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err); | ||
| 74 | goto err_pcie; | ||
| 75 | } | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | |||
| 79 | err_pcie: | ||
| 80 | regulator_disable(regulator); | ||
| 81 | err_en: | ||
| 82 | regulator_put(regulator); | ||
| 83 | err_reg: | ||
| 84 | gpio_free(en_vdd_1v05); | ||
| 85 | |||
| 86 | return err; | ||
| 87 | } | ||
| 88 | |||
| 89 | #endif | ||
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 9a6659fe2dc2..db6810dc0b3d 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h | |||
| @@ -31,7 +31,6 @@ void __init tegra_init_early(void); | |||
| 31 | void __init tegra_map_common_io(void); | 31 | void __init tegra_map_common_io(void); |
| 32 | void __init tegra_init_irq(void); | 32 | void __init tegra_init_irq(void); |
| 33 | void __init tegra_dt_init_irq(void); | 33 | void __init tegra_dt_init_irq(void); |
| 34 | int __init tegra_pcie_init(bool init_port0, bool init_port1); | ||
| 35 | 34 | ||
| 36 | void tegra_init_late(void); | 35 | void tegra_init_late(void); |
| 37 | 36 | ||
| @@ -48,13 +47,6 @@ int __init tegra_powergate_debugfs_init(void); | |||
| 48 | static inline int tegra_powergate_debugfs_init(void) { return 0; } | 47 | static inline int tegra_powergate_debugfs_init(void) { return 0; } |
| 49 | #endif | 48 | #endif |
| 50 | 49 | ||
| 51 | int __init harmony_regulator_init(void); | ||
| 52 | #ifdef CONFIG_TEGRA_PCI | ||
| 53 | int __init harmony_pcie_init(void); | ||
| 54 | #else | ||
| 55 | static inline int harmony_pcie_init(void) { return 0; } | ||
| 56 | #endif | ||
| 57 | |||
| 58 | void __init tegra_paz00_wifikill_init(void); | 50 | void __init tegra_paz00_wifikill_init(void); |
| 59 | 51 | ||
| 60 | #endif | 52 | #endif |
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 32f8eb3fe344..5900cc44f780 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h | |||
| @@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops; | |||
| 2 | 2 | ||
| 3 | extern int tegra_cpu_kill(unsigned int cpu); | 3 | extern int tegra_cpu_kill(unsigned int cpu); |
| 4 | extern void tegra_cpu_die(unsigned int cpu); | 4 | extern void tegra_cpu_die(unsigned int cpu); |
| 5 | extern int tegra_cpu_disable(unsigned int cpu); | ||
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 1d1c6023f4a2..e0b87300243d 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c | |||
| @@ -17,15 +17,64 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> | 18 | #include <linux/module.h> |
| 19 | #include <linux/cpuidle.h> | 19 | #include <linux/cpuidle.h> |
| 20 | #include <linux/cpu_pm.h> | ||
| 21 | #include <linux/clockchips.h> | ||
| 20 | 22 | ||
| 21 | #include <asm/cpuidle.h> | 23 | #include <asm/cpuidle.h> |
| 24 | #include <asm/suspend.h> | ||
| 25 | #include <asm/smp_plat.h> | ||
| 26 | |||
| 27 | #include "pm.h" | ||
| 28 | #include "sleep.h" | ||
| 29 | |||
| 30 | #ifdef CONFIG_PM_SLEEP | ||
| 31 | #define TEGRA114_MAX_STATES 2 | ||
| 32 | #else | ||
| 33 | #define TEGRA114_MAX_STATES 1 | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifdef CONFIG_PM_SLEEP | ||
| 37 | static int tegra114_idle_power_down(struct cpuidle_device *dev, | ||
| 38 | struct cpuidle_driver *drv, | ||
| 39 | int index) | ||
| 40 | { | ||
| 41 | local_fiq_disable(); | ||
| 42 | |||
| 43 | tegra_set_cpu_in_lp2(); | ||
| 44 | cpu_pm_enter(); | ||
| 45 | |||
| 46 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); | ||
| 47 | |||
| 48 | cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); | ||
| 49 | |||
| 50 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | ||
| 51 | |||
| 52 | cpu_pm_exit(); | ||
| 53 | tegra_clear_cpu_in_lp2(); | ||
| 54 | |||
| 55 | local_fiq_enable(); | ||
| 56 | |||
| 57 | return index; | ||
| 58 | } | ||
| 59 | #endif | ||
| 22 | 60 | ||
| 23 | static struct cpuidle_driver tegra_idle_driver = { | 61 | static struct cpuidle_driver tegra_idle_driver = { |
| 24 | .name = "tegra_idle", | 62 | .name = "tegra_idle", |
| 25 | .owner = THIS_MODULE, | 63 | .owner = THIS_MODULE, |
| 26 | .state_count = 1, | 64 | .state_count = TEGRA114_MAX_STATES, |
| 27 | .states = { | 65 | .states = { |
| 28 | [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), | 66 | [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), |
| 67 | #ifdef CONFIG_PM_SLEEP | ||
| 68 | [1] = { | ||
| 69 | .enter = tegra114_idle_power_down, | ||
| 70 | .exit_latency = 500, | ||
| 71 | .target_residency = 1000, | ||
| 72 | .power_usage = 0, | ||
| 73 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
| 74 | .name = "powered-down", | ||
| 75 | .desc = "CPU power gated", | ||
| 76 | }, | ||
| 77 | #endif | ||
| 29 | }, | 78 | }, |
| 30 | }; | 79 | }; |
| 31 | 80 | ||
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 706aa4215c36..b82dcaee2ef4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c | |||
| @@ -211,6 +211,18 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, | |||
| 211 | } | 211 | } |
| 212 | #endif | 212 | #endif |
| 213 | 213 | ||
| 214 | /* | ||
| 215 | * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether | ||
| 216 | * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around | ||
| 217 | * this, simply disable LP2 if the PCI driver and DT node are both enabled. | ||
| 218 | */ | ||
| 219 | void tegra20_cpuidle_pcie_irqs_in_use(void) | ||
| 220 | { | ||
| 221 | pr_info_once( | ||
| 222 | "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); | ||
| 223 | tegra_idle_driver.states[1].disabled = true; | ||
| 224 | } | ||
| 225 | |||
| 214 | int __init tegra20_cpuidle_init(void) | 226 | int __init tegra20_cpuidle_init(void) |
| 215 | { | 227 | { |
| 216 | return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); | 228 | return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); |
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index e85973cef037..0961dfcf83a4 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c | |||
| @@ -44,3 +44,13 @@ void __init tegra_cpuidle_init(void) | |||
| 44 | break; | 44 | break; |
| 45 | } | 45 | } |
| 46 | } | 46 | } |
| 47 | |||
| 48 | void tegra_cpuidle_pcie_irqs_in_use(void) | ||
| 49 | { | ||
| 50 | switch (tegra_chip_id) { | ||
| 51 | case TEGRA20: | ||
| 52 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | ||
| 53 | tegra20_cpuidle_pcie_irqs_in_use(); | ||
| 54 | break; | ||
| 55 | } | ||
| 56 | } | ||
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 9ec2c1ab0fa4..c017dab60ffa 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | #ifdef CONFIG_CPU_IDLE | 20 | #ifdef CONFIG_CPU_IDLE |
| 21 | int tegra20_cpuidle_init(void); | 21 | int tegra20_cpuidle_init(void); |
| 22 | void tegra20_cpuidle_pcie_irqs_in_use(void); | ||
| 22 | int tegra30_cpuidle_init(void); | 23 | int tegra30_cpuidle_init(void); |
| 23 | int tegra114_cpuidle_init(void); | 24 | int tegra114_cpuidle_init(void); |
| 24 | void tegra_cpuidle_init(void); | 25 | void tegra_cpuidle_init(void); |
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index b477ef310dcd..5348543382bf 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
| @@ -86,6 +86,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) | |||
| 86 | reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; | 86 | reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; |
| 87 | break; | 87 | break; |
| 88 | case TEGRA30: | 88 | case TEGRA30: |
| 89 | case TEGRA114: | ||
| 89 | /* clear wfe bitmap */ | 90 | /* clear wfe bitmap */ |
| 90 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | 91 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; |
| 91 | /* clear wfi bitmap */ | 92 | /* clear wfi bitmap */ |
| @@ -123,6 +124,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) | |||
| 123 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; | 124 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; |
| 124 | break; | 125 | break; |
| 125 | case TEGRA30: | 126 | case TEGRA30: |
| 127 | case TEGRA114: | ||
| 126 | /* clear wfe bitmap */ | 128 | /* clear wfe bitmap */ |
| 127 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | 129 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; |
| 128 | /* clear wfi bitmap */ | 130 | /* clear wfi bitmap */ |
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 7a29bae799a7..c89aac60a143 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h | |||
| @@ -28,9 +28,18 @@ | |||
| 28 | #define FLOW_CTRL_SCLK_RESUME (1 << 27) | 28 | #define FLOW_CTRL_SCLK_RESUME (1 << 27) |
| 29 | #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) | 29 | #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) |
| 30 | #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) | 30 | #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) |
| 31 | #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) | ||
| 32 | #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) | ||
| 33 | #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) | ||
| 34 | #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) | ||
| 31 | #define FLOW_CTRL_CPU0_CSR 0x8 | 35 | #define FLOW_CTRL_CPU0_CSR 0x8 |
| 32 | #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) | 36 | #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) |
| 33 | #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) | 37 | #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) |
| 38 | #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) | ||
| 39 | #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) | ||
| 40 | #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ | ||
| 41 | FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ | ||
| 42 | FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) | ||
| 34 | #define FLOW_CTRL_CSR_ENABLE (1 << 0) | 43 | #define FLOW_CTRL_CSR_ENABLE (1 << 0) |
| 35 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 | 44 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 |
| 36 | #define FLOW_CTRL_CPU1_CSR 0x18 | 45 | #define FLOW_CTRL_CPU1_CSR 0x18 |
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 045c16f2dd51..2072e7322c39 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | .section ".text.head", "ax" | 6 | .section ".text.head", "ax" |
| 7 | 7 | ||
| 8 | ENTRY(tegra_secondary_startup) | 8 | ENTRY(tegra_secondary_startup) |
| 9 | bl v7_invalidate_l1 | 9 | check_cpu_part_num 0xc09, r8, r9 |
| 10 | bleq v7_invalidate_l1 | ||
| 10 | b secondary_startup | 11 | b secondary_startup |
| 11 | ENDPROC(tegra_secondary_startup) | 12 | ENDPROC(tegra_secondary_startup) |
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index a52c10e0a857..04de2e860923 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
| @@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu) | |||
| 37 | void __ref tegra_cpu_die(unsigned int cpu) | 37 | void __ref tegra_cpu_die(unsigned int cpu) |
| 38 | { | 38 | { |
| 39 | /* Clean L1 data cache */ | 39 | /* Clean L1 data cache */ |
| 40 | tegra_disable_clean_inv_dcache(); | 40 | tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); |
| 41 | 41 | ||
| 42 | /* Shut down the current CPU. */ | 42 | /* Shut down the current CPU. */ |
| 43 | tegra_hotplug_shutdown(); | 43 | tegra_hotplug_shutdown(); |
| @@ -46,17 +46,6 @@ void __ref tegra_cpu_die(unsigned int cpu) | |||
| 46 | BUG(); | 46 | BUG(); |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | int tegra_cpu_disable(unsigned int cpu) | ||
| 50 | { | ||
| 51 | switch (tegra_chip_id) { | ||
| 52 | case TEGRA20: | ||
| 53 | case TEGRA30: | ||
| 54 | return cpu == 0 ? -EPERM : 0; | ||
| 55 | default: | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | } | ||
| 59 | |||
| 60 | void __init tegra_hotplug_init(void) | 49 | void __init tegra_hotplug_init(void) |
| 61 | { | 50 | { |
| 62 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) | 51 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 399fbca27102..3f5fa0749bde 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h | |||
| @@ -24,6 +24,8 @@ | |||
| 24 | #define TEGRA_IRAM_BASE 0x40000000 | 24 | #define TEGRA_IRAM_BASE 0x40000000 |
| 25 | #define TEGRA_IRAM_SIZE SZ_256K | 25 | #define TEGRA_IRAM_SIZE SZ_256K |
| 26 | 26 | ||
| 27 | #define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) | ||
| 28 | |||
| 27 | #define TEGRA_HOST1X_BASE 0x50000000 | 29 | #define TEGRA_HOST1X_BASE 0x50000000 |
| 28 | #define TEGRA_HOST1X_SIZE 0x24000 | 30 | #define TEGRA_HOST1X_SIZE 0x24000 |
| 29 | 31 | ||
| @@ -237,6 +239,12 @@ | |||
| 237 | #define TEGRA_KFUSE_BASE 0x7000FC00 | 239 | #define TEGRA_KFUSE_BASE 0x7000FC00 |
| 238 | #define TEGRA_KFUSE_SIZE SZ_1K | 240 | #define TEGRA_KFUSE_SIZE SZ_1K |
| 239 | 241 | ||
| 242 | #define TEGRA_EMC0_BASE 0x7001A000 | ||
| 243 | #define TEGRA_EMC0_SIZE SZ_2K | ||
| 244 | |||
| 245 | #define TEGRA_EMC1_BASE 0x7001A800 | ||
| 246 | #define TEGRA_EMC1_SIZE SZ_2K | ||
| 247 | |||
| 240 | #define TEGRA_CSITE_BASE 0x70040000 | 248 | #define TEGRA_CSITE_BASE 0x70040000 |
| 241 | #define TEGRA_CSITE_SIZE SZ_256K | 249 | #define TEGRA_CSITE_SIZE SZ_256K |
| 242 | 250 | ||
| @@ -278,9 +286,6 @@ | |||
| 278 | #define IO_APB_VIRT IOMEM(0xFE300000) | 286 | #define IO_APB_VIRT IOMEM(0xFE300000) |
| 279 | #define IO_APB_SIZE SZ_1M | 287 | #define IO_APB_SIZE SZ_1M |
| 280 | 288 | ||
| 281 | #define TEGRA_PCIE_BASE 0x80000000 | ||
| 282 | #define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) | ||
| 283 | |||
| 284 | #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) | 289 | #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) |
| 285 | #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) | 290 | #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) |
| 286 | 291 | ||
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 0de4eed1493d..1a74d562dca1 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
| @@ -18,10 +18,12 @@ | |||
| 18 | */ | 18 | */ |
| 19 | 19 | ||
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/cpu_pm.h> | ||
| 21 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 22 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 23 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 24 | #include <linux/of.h> | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_address.h> | ||
| 25 | #include <linux/irqchip/arm-gic.h> | 27 | #include <linux/irqchip/arm-gic.h> |
| 26 | #include <linux/syscore_ops.h> | 28 | #include <linux/syscore_ops.h> |
| 27 | 29 | ||
| @@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS]; | |||
| 65 | static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; | 67 | static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; |
| 66 | 68 | ||
| 67 | static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; | 69 | static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; |
| 70 | static void __iomem *tegra_gic_cpu_base; | ||
| 68 | #endif | 71 | #endif |
| 69 | 72 | ||
| 70 | bool tegra_pending_sgi(void) | 73 | bool tegra_pending_sgi(void) |
| @@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void) | |||
| 213 | 216 | ||
| 214 | return 0; | 217 | return 0; |
| 215 | } | 218 | } |
| 219 | |||
| 220 | static int tegra_gic_notifier(struct notifier_block *self, | ||
| 221 | unsigned long cmd, void *v) | ||
| 222 | { | ||
| 223 | switch (cmd) { | ||
| 224 | case CPU_PM_ENTER: | ||
| 225 | writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); | ||
| 226 | break; | ||
| 227 | } | ||
| 228 | |||
| 229 | return NOTIFY_OK; | ||
| 230 | } | ||
| 231 | |||
| 232 | static struct notifier_block tegra_gic_notifier_block = { | ||
| 233 | .notifier_call = tegra_gic_notifier, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static const struct of_device_id tegra114_dt_gic_match[] __initconst = { | ||
| 237 | { .compatible = "arm,cortex-a15-gic" }, | ||
| 238 | { } | ||
| 239 | }; | ||
| 240 | |||
| 241 | static void tegra114_gic_cpu_pm_registration(void) | ||
| 242 | { | ||
| 243 | struct device_node *dn; | ||
| 244 | |||
| 245 | dn = of_find_matching_node(NULL, tegra114_dt_gic_match); | ||
| 246 | if (!dn) | ||
| 247 | return; | ||
| 248 | |||
| 249 | tegra_gic_cpu_base = of_iomap(dn, 1); | ||
| 250 | |||
| 251 | cpu_pm_register_notifier(&tegra_gic_notifier_block); | ||
| 252 | } | ||
| 216 | #else | 253 | #else |
| 217 | #define tegra_set_wake NULL | 254 | #define tegra_set_wake NULL |
| 255 | static void tegra114_gic_cpu_pm_registration(void) { } | ||
| 218 | #endif | 256 | #endif |
| 219 | 257 | ||
| 220 | void __init tegra_init_irq(void) | 258 | void __init tegra_init_irq(void) |
| @@ -252,4 +290,6 @@ void __init tegra_init_irq(void) | |||
| 252 | if (!of_have_populated_dt()) | 290 | if (!of_have_populated_dt()) |
| 253 | gic_init(0, 29, distbase, | 291 | gic_init(0, 29, distbase, |
| 254 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); | 292 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); |
| 293 | |||
| 294 | tegra114_gic_cpu_pm_registration(); | ||
| 255 | } | 295 | } |
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c deleted file mode 100644 index 46144a19a7e7..000000000000 --- a/arch/arm/mach-tegra/pcie.c +++ /dev/null | |||
| @@ -1,886 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-tegra/pci.c | ||
| 3 | * | ||
| 4 | * PCIe host controller driver for TEGRA(2) SOCs | ||
| 5 | * | ||
| 6 | * Copyright (c) 2010, CompuLab, Ltd. | ||
| 7 | * Author: Mike Rapoport <mike@compulab.co.il> | ||
| 8 | * | ||
| 9 | * Based on NVIDIA PCIe driver | ||
| 10 | * Copyright (c) 2008-2009, NVIDIA Corporation. | ||
| 11 | * | ||
| 12 | * Bits taken from arch/arm/mach-dove/pcie.c | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 20 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 22 | * more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/kernel.h> | ||
| 30 | #include <linux/pci.h> | ||
| 31 | #include <linux/interrupt.h> | ||
| 32 | #include <linux/irq.h> | ||
| 33 | #include <linux/clk.h> | ||
| 34 | #include <linux/delay.h> | ||
| 35 | #include <linux/export.h> | ||
| 36 | #include <linux/clk/tegra.h> | ||
| 37 | #include <linux/tegra-powergate.h> | ||
| 38 | |||
| 39 | #include <asm/sizes.h> | ||
| 40 | #include <asm/mach/pci.h> | ||
| 41 | |||
| 42 | #include "board.h" | ||
| 43 | #include "iomap.h" | ||
| 44 | |||
| 45 | /* Hack - need to parse this from DT */ | ||
| 46 | #define INT_PCIE_INTR 130 | ||
| 47 | |||
| 48 | /* register definitions */ | ||
| 49 | #define AFI_OFFSET 0x3800 | ||
| 50 | #define PADS_OFFSET 0x3000 | ||
| 51 | #define RP0_OFFSET 0x0000 | ||
| 52 | #define RP1_OFFSET 0x1000 | ||
| 53 | |||
| 54 | #define AFI_AXI_BAR0_SZ 0x00 | ||
| 55 | #define AFI_AXI_BAR1_SZ 0x04 | ||
| 56 | #define AFI_AXI_BAR2_SZ 0x08 | ||
| 57 | #define AFI_AXI_BAR3_SZ 0x0c | ||
| 58 | #define AFI_AXI_BAR4_SZ 0x10 | ||
| 59 | #define AFI_AXI_BAR5_SZ 0x14 | ||
| 60 | |||
| 61 | #define AFI_AXI_BAR0_START 0x18 | ||
| 62 | #define AFI_AXI_BAR1_START 0x1c | ||
| 63 | #define AFI_AXI_BAR2_START 0x20 | ||
| 64 | #define AFI_AXI_BAR3_START 0x24 | ||
| 65 | #define AFI_AXI_BAR4_START 0x28 | ||
| 66 | #define AFI_AXI_BAR5_START 0x2c | ||
| 67 | |||
| 68 | #define AFI_FPCI_BAR0 0x30 | ||
| 69 | #define AFI_FPCI_BAR1 0x34 | ||
| 70 | #define AFI_FPCI_BAR2 0x38 | ||
| 71 | #define AFI_FPCI_BAR3 0x3c | ||
| 72 | #define AFI_FPCI_BAR4 0x40 | ||
| 73 | #define AFI_FPCI_BAR5 0x44 | ||
| 74 | |||
| 75 | #define AFI_CACHE_BAR0_SZ 0x48 | ||
| 76 | #define AFI_CACHE_BAR0_ST 0x4c | ||
| 77 | #define AFI_CACHE_BAR1_SZ 0x50 | ||
| 78 | #define AFI_CACHE_BAR1_ST 0x54 | ||
| 79 | |||
| 80 | #define AFI_MSI_BAR_SZ 0x60 | ||
| 81 | #define AFI_MSI_FPCI_BAR_ST 0x64 | ||
| 82 | #define AFI_MSI_AXI_BAR_ST 0x68 | ||
| 83 | |||
| 84 | #define AFI_CONFIGURATION 0xac | ||
| 85 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | ||
| 86 | |||
| 87 | #define AFI_FPCI_ERROR_MASKS 0xb0 | ||
| 88 | |||
| 89 | #define AFI_INTR_MASK 0xb4 | ||
| 90 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | ||
| 91 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | ||
| 92 | |||
| 93 | #define AFI_INTR_CODE 0xb8 | ||
| 94 | #define AFI_INTR_CODE_MASK 0xf | ||
| 95 | #define AFI_INTR_MASTER_ABORT 4 | ||
| 96 | #define AFI_INTR_LEGACY 6 | ||
| 97 | |||
| 98 | #define AFI_INTR_SIGNATURE 0xbc | ||
| 99 | #define AFI_SM_INTR_ENABLE 0xc4 | ||
| 100 | |||
| 101 | #define AFI_AFI_INTR_ENABLE 0xc8 | ||
| 102 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | ||
| 103 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | ||
| 104 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | ||
| 105 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | ||
| 106 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | ||
| 107 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | ||
| 108 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | ||
| 109 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | ||
| 110 | |||
| 111 | #define AFI_PCIE_CONFIG 0x0f8 | ||
| 112 | #define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) | ||
| 113 | #define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) | ||
| 114 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | ||
| 115 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | ||
| 116 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) | ||
| 117 | |||
| 118 | #define AFI_FUSE 0x104 | ||
| 119 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | ||
| 120 | |||
| 121 | #define AFI_PEX0_CTRL 0x110 | ||
| 122 | #define AFI_PEX1_CTRL 0x118 | ||
| 123 | #define AFI_PEX_CTRL_RST (1 << 0) | ||
| 124 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) | ||
| 125 | |||
| 126 | #define RP_VEND_XP 0x00000F00 | ||
| 127 | #define RP_VEND_XP_DL_UP (1 << 30) | ||
| 128 | |||
| 129 | #define RP_LINK_CONTROL_STATUS 0x00000090 | ||
| 130 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | ||
| 131 | |||
| 132 | #define PADS_CTL_SEL 0x0000009C | ||
| 133 | |||
| 134 | #define PADS_CTL 0x000000A0 | ||
| 135 | #define PADS_CTL_IDDQ_1L (1 << 0) | ||
| 136 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | ||
| 137 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | ||
| 138 | |||
| 139 | #define PADS_PLL_CTL 0x000000B8 | ||
| 140 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) | ||
| 141 | #define PADS_PLL_CTL_LOCKDET (1 << 8) | ||
| 142 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | ||
| 143 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) | ||
| 144 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) | ||
| 145 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) | ||
| 146 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | ||
| 147 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) | ||
| 148 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) | ||
| 149 | |||
| 150 | /* PMC access is required for PCIE xclk (un)clamping */ | ||
| 151 | #define PMC_SCRATCH42 0x144 | ||
| 152 | #define PMC_SCRATCH42_PCX_CLAMP (1 << 0) | ||
| 153 | |||
| 154 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); | ||
| 155 | |||
| 156 | #define pmc_writel(value, reg) \ | ||
| 157 | __raw_writel(value, reg_pmc_base + (reg)) | ||
| 158 | #define pmc_readl(reg) \ | ||
| 159 | __raw_readl(reg_pmc_base + (reg)) | ||
| 160 | |||
| 161 | /* | ||
| 162 | * Tegra2 defines 1GB in the AXI address map for PCIe. | ||
| 163 | * | ||
| 164 | * That address space is split into different regions, with sizes and | ||
| 165 | * offsets as follows: | ||
| 166 | * | ||
| 167 | * 0x80000000 - 0x80003fff - PCI controller registers | ||
| 168 | * 0x80004000 - 0x80103fff - PCI configuration space | ||
| 169 | * 0x80104000 - 0x80203fff - PCI extended configuration space | ||
| 170 | * 0x80203fff - 0x803fffff - unused | ||
| 171 | * 0x80400000 - 0x8040ffff - downstream IO | ||
| 172 | * 0x80410000 - 0x8fffffff - unused | ||
| 173 | * 0x90000000 - 0x9fffffff - non-prefetchable memory | ||
| 174 | * 0xa0000000 - 0xbfffffff - prefetchable memory | ||
| 175 | */ | ||
| 176 | #define PCIE_REGS_SZ SZ_16K | ||
| 177 | #define PCIE_CFG_OFF PCIE_REGS_SZ | ||
| 178 | #define PCIE_CFG_SZ SZ_1M | ||
| 179 | #define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF) | ||
| 180 | #define PCIE_EXT_CFG_SZ SZ_1M | ||
| 181 | #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) | ||
| 182 | |||
| 183 | #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) | ||
| 184 | #define MEM_SIZE_0 SZ_128M | ||
| 185 | #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) | ||
| 186 | #define MEM_SIZE_1 SZ_128M | ||
| 187 | #define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) | ||
| 188 | #define PREFETCH_MEM_SIZE_0 SZ_128M | ||
| 189 | #define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) | ||
| 190 | #define PREFETCH_MEM_SIZE_1 SZ_128M | ||
| 191 | |||
| 192 | #define PCIE_CONF_BUS(b) ((b) << 16) | ||
| 193 | #define PCIE_CONF_DEV(d) ((d) << 11) | ||
| 194 | #define PCIE_CONF_FUNC(f) ((f) << 8) | ||
| 195 | #define PCIE_CONF_REG(r) \ | ||
| 196 | (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) | ||
| 197 | |||
| 198 | struct tegra_pcie_port { | ||
| 199 | int index; | ||
| 200 | u8 root_bus_nr; | ||
| 201 | void __iomem *base; | ||
| 202 | |||
| 203 | bool link_up; | ||
| 204 | |||
| 205 | char mem_space_name[16]; | ||
| 206 | char prefetch_space_name[20]; | ||
| 207 | struct resource res[2]; | ||
| 208 | }; | ||
| 209 | |||
| 210 | struct tegra_pcie_info { | ||
| 211 | struct tegra_pcie_port port[2]; | ||
| 212 | int num_ports; | ||
| 213 | |||
| 214 | void __iomem *regs; | ||
| 215 | struct resource res_mmio; | ||
| 216 | |||
| 217 | struct clk *pex_clk; | ||
| 218 | struct clk *afi_clk; | ||
| 219 | struct clk *pcie_xclk; | ||
| 220 | struct clk *pll_e; | ||
| 221 | }; | ||
| 222 | |||
| 223 | static struct tegra_pcie_info tegra_pcie; | ||
| 224 | |||
| 225 | static inline void afi_writel(u32 value, unsigned long offset) | ||
| 226 | { | ||
| 227 | writel(value, offset + AFI_OFFSET + tegra_pcie.regs); | ||
| 228 | } | ||
| 229 | |||
| 230 | static inline u32 afi_readl(unsigned long offset) | ||
| 231 | { | ||
| 232 | return readl(offset + AFI_OFFSET + tegra_pcie.regs); | ||
| 233 | } | ||
| 234 | |||
| 235 | static inline void pads_writel(u32 value, unsigned long offset) | ||
| 236 | { | ||
| 237 | writel(value, offset + PADS_OFFSET + tegra_pcie.regs); | ||
| 238 | } | ||
| 239 | |||
| 240 | static inline u32 pads_readl(unsigned long offset) | ||
| 241 | { | ||
| 242 | return readl(offset + PADS_OFFSET + tegra_pcie.regs); | ||
| 243 | } | ||
| 244 | |||
| 245 | static struct tegra_pcie_port *bus_to_port(int bus) | ||
| 246 | { | ||
| 247 | int i; | ||
| 248 | |||
| 249 | for (i = tegra_pcie.num_ports - 1; i >= 0; i--) { | ||
| 250 | int rbus = tegra_pcie.port[i].root_bus_nr; | ||
| 251 | if (rbus != -1 && rbus == bus) | ||
| 252 | break; | ||
| 253 | } | ||
| 254 | |||
| 255 | return i >= 0 ? tegra_pcie.port + i : NULL; | ||
| 256 | } | ||
| 257 | |||
| 258 | static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, | ||
| 259 | int where, int size, u32 *val) | ||
| 260 | { | ||
| 261 | struct tegra_pcie_port *pp = bus_to_port(bus->number); | ||
| 262 | void __iomem *addr; | ||
| 263 | |||
| 264 | if (pp) { | ||
| 265 | if (devfn != 0) { | ||
| 266 | *val = 0xffffffff; | ||
| 267 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 268 | } | ||
| 269 | |||
| 270 | addr = pp->base + (where & ~0x3); | ||
| 271 | } else { | ||
| 272 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + | ||
| 273 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + | ||
| 274 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + | ||
| 275 | PCIE_CONF_REG(where)); | ||
| 276 | } | ||
| 277 | |||
| 278 | *val = readl(addr); | ||
| 279 | |||
| 280 | if (size == 1) | ||
| 281 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 282 | else if (size == 2) | ||
| 283 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 284 | |||
| 285 | return PCIBIOS_SUCCESSFUL; | ||
| 286 | } | ||
| 287 | |||
| 288 | static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, | ||
| 289 | int where, int size, u32 val) | ||
| 290 | { | ||
| 291 | struct tegra_pcie_port *pp = bus_to_port(bus->number); | ||
| 292 | void __iomem *addr; | ||
| 293 | |||
| 294 | u32 mask; | ||
| 295 | u32 tmp; | ||
| 296 | |||
| 297 | if (pp) { | ||
| 298 | if (devfn != 0) | ||
| 299 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 300 | |||
| 301 | addr = pp->base + (where & ~0x3); | ||
| 302 | } else { | ||
| 303 | addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + | ||
| 304 | PCIE_CONF_DEV(PCI_SLOT(devfn)) + | ||
| 305 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) + | ||
| 306 | PCIE_CONF_REG(where)); | ||
| 307 | } | ||
| 308 | |||
| 309 | if (size == 4) { | ||
| 310 | writel(val, addr); | ||
| 311 | return PCIBIOS_SUCCESSFUL; | ||
| 312 | } | ||
| 313 | |||
| 314 | if (size == 2) | ||
| 315 | mask = ~(0xffff << ((where & 0x3) * 8)); | ||
| 316 | else if (size == 1) | ||
| 317 | mask = ~(0xff << ((where & 0x3) * 8)); | ||
| 318 | else | ||
| 319 | return PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 320 | |||
| 321 | tmp = readl(addr) & mask; | ||
| 322 | tmp |= val << ((where & 0x3) * 8); | ||
| 323 | writel(tmp, addr); | ||
| 324 | |||
| 325 | return PCIBIOS_SUCCESSFUL; | ||
| 326 | } | ||
| 327 | |||
| 328 | static struct pci_ops tegra_pcie_ops = { | ||
| 329 | .read = tegra_pcie_read_conf, | ||
| 330 | .write = tegra_pcie_write_conf, | ||
| 331 | }; | ||
| 332 | |||
| 333 | static void tegra_pcie_fixup_bridge(struct pci_dev *dev) | ||
| 334 | { | ||
| 335 | u16 reg; | ||
| 336 | |||
| 337 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { | ||
| 338 | pci_read_config_word(dev, PCI_COMMAND, ®); | ||
| 339 | reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | ||
| 340 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); | ||
| 341 | pci_write_config_word(dev, PCI_COMMAND, reg); | ||
| 342 | } | ||
| 343 | } | ||
| 344 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); | ||
| 345 | |||
| 346 | /* Tegra PCIE root complex wrongly reports device class */ | ||
| 347 | static void tegra_pcie_fixup_class(struct pci_dev *dev) | ||
| 348 | { | ||
| 349 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | ||
| 350 | } | ||
| 351 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); | ||
| 352 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); | ||
| 353 | |||
| 354 | /* Tegra PCIE requires relaxed ordering */ | ||
| 355 | static void tegra_pcie_relax_enable(struct pci_dev *dev) | ||
| 356 | { | ||
| 357 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); | ||
| 358 | } | ||
| 359 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); | ||
| 360 | |||
| 361 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) | ||
| 362 | { | ||
| 363 | struct tegra_pcie_port *pp; | ||
| 364 | |||
| 365 | if (nr >= tegra_pcie.num_ports) | ||
| 366 | return 0; | ||
| 367 | |||
| 368 | pp = tegra_pcie.port + nr; | ||
| 369 | pp->root_bus_nr = sys->busnr; | ||
| 370 | |||
| 371 | pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE); | ||
| 372 | |||
| 373 | /* | ||
| 374 | * IORESOURCE_MEM | ||
| 375 | */ | ||
| 376 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | ||
| 377 | "PCIe %d MEM", pp->index); | ||
| 378 | pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; | ||
| 379 | pp->res[0].name = pp->mem_space_name; | ||
| 380 | if (pp->index == 0) { | ||
| 381 | pp->res[0].start = MEM_BASE_0; | ||
| 382 | pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1; | ||
| 383 | } else { | ||
| 384 | pp->res[0].start = MEM_BASE_1; | ||
| 385 | pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1; | ||
| 386 | } | ||
| 387 | pp->res[0].flags = IORESOURCE_MEM; | ||
| 388 | if (request_resource(&iomem_resource, &pp->res[0])) | ||
| 389 | panic("Request PCIe Memory resource failed\n"); | ||
| 390 | pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset); | ||
| 391 | |||
| 392 | /* | ||
| 393 | * IORESOURCE_MEM | IORESOURCE_PREFETCH | ||
| 394 | */ | ||
| 395 | snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), | ||
| 396 | "PCIe %d PREFETCH MEM", pp->index); | ||
| 397 | pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; | ||
| 398 | pp->res[1].name = pp->prefetch_space_name; | ||
| 399 | if (pp->index == 0) { | ||
| 400 | pp->res[1].start = PREFETCH_MEM_BASE_0; | ||
| 401 | pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1; | ||
| 402 | } else { | ||
| 403 | pp->res[1].start = PREFETCH_MEM_BASE_1; | ||
| 404 | pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1; | ||
| 405 | } | ||
| 406 | pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; | ||
| 407 | if (request_resource(&iomem_resource, &pp->res[1])) | ||
| 408 | panic("Request PCIe Prefetch Memory resource failed\n"); | ||
| 409 | pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); | ||
| 410 | |||
| 411 | return 1; | ||
| 412 | } | ||
| 413 | |||
| 414 | static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | ||
| 415 | { | ||
| 416 | return INT_PCIE_INTR; | ||
| 417 | } | ||
| 418 | |||
| 419 | static struct pci_bus __init *tegra_pcie_scan_bus(int nr, | ||
| 420 | struct pci_sys_data *sys) | ||
| 421 | { | ||
| 422 | struct tegra_pcie_port *pp; | ||
| 423 | |||
| 424 | if (nr >= tegra_pcie.num_ports) | ||
| 425 | return NULL; | ||
| 426 | |||
| 427 | pp = tegra_pcie.port + nr; | ||
| 428 | pp->root_bus_nr = sys->busnr; | ||
| 429 | |||
| 430 | return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys, | ||
| 431 | &sys->resources); | ||
| 432 | } | ||
| 433 | |||
| 434 | static struct hw_pci tegra_pcie_hw __initdata = { | ||
| 435 | .nr_controllers = 2, | ||
| 436 | .setup = tegra_pcie_setup, | ||
| 437 | .scan = tegra_pcie_scan_bus, | ||
| 438 | .map_irq = tegra_pcie_map_irq, | ||
| 439 | }; | ||
| 440 | |||
| 441 | |||
| 442 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) | ||
| 443 | { | ||
| 444 | const char *err_msg[] = { | ||
| 445 | "Unknown", | ||
| 446 | "AXI slave error", | ||
| 447 | "AXI decode error", | ||
| 448 | "Target abort", | ||
| 449 | "Master abort", | ||
| 450 | "Invalid write", | ||
| 451 | "Response decoding error", | ||
| 452 | "AXI response decoding error", | ||
| 453 | "Transcation timeout", | ||
| 454 | }; | ||
| 455 | |||
| 456 | u32 code, signature; | ||
| 457 | |||
| 458 | code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK; | ||
| 459 | signature = afi_readl(AFI_INTR_SIGNATURE); | ||
| 460 | afi_writel(0, AFI_INTR_CODE); | ||
| 461 | |||
| 462 | if (code == AFI_INTR_LEGACY) | ||
| 463 | return IRQ_NONE; | ||
| 464 | |||
| 465 | if (code >= ARRAY_SIZE(err_msg)) | ||
| 466 | code = 0; | ||
| 467 | |||
| 468 | /* | ||
| 469 | * do not pollute kernel log with master abort reports since they | ||
| 470 | * happen a lot during enumeration | ||
| 471 | */ | ||
| 472 | if (code == AFI_INTR_MASTER_ABORT) | ||
| 473 | pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature); | ||
| 474 | else | ||
| 475 | pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature); | ||
| 476 | |||
| 477 | return IRQ_HANDLED; | ||
| 478 | } | ||
| 479 | |||
| 480 | static void tegra_pcie_setup_translations(void) | ||
| 481 | { | ||
| 482 | u32 fpci_bar; | ||
| 483 | u32 size; | ||
| 484 | u32 axi_address; | ||
| 485 | |||
| 486 | /* Bar 0: config Bar */ | ||
| 487 | fpci_bar = ((u32)0xfdff << 16); | ||
| 488 | size = PCIE_CFG_SZ; | ||
| 489 | axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF; | ||
| 490 | afi_writel(axi_address, AFI_AXI_BAR0_START); | ||
| 491 | afi_writel(size >> 12, AFI_AXI_BAR0_SZ); | ||
| 492 | afi_writel(fpci_bar, AFI_FPCI_BAR0); | ||
| 493 | |||
| 494 | /* Bar 1: extended config Bar */ | ||
| 495 | fpci_bar = ((u32)0xfe1 << 20); | ||
| 496 | size = PCIE_EXT_CFG_SZ; | ||
| 497 | axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF; | ||
| 498 | afi_writel(axi_address, AFI_AXI_BAR1_START); | ||
| 499 | afi_writel(size >> 12, AFI_AXI_BAR1_SZ); | ||
| 500 | afi_writel(fpci_bar, AFI_FPCI_BAR1); | ||
| 501 | |||
| 502 | /* Bar 2: downstream IO bar */ | ||
| 503 | fpci_bar = ((__u32)0xfdfc << 16); | ||
| 504 | size = SZ_128K; | ||
| 505 | axi_address = TEGRA_PCIE_IO_BASE; | ||
| 506 | afi_writel(axi_address, AFI_AXI_BAR2_START); | ||
| 507 | afi_writel(size >> 12, AFI_AXI_BAR2_SZ); | ||
| 508 | afi_writel(fpci_bar, AFI_FPCI_BAR2); | ||
| 509 | |||
| 510 | /* Bar 3: prefetchable memory BAR */ | ||
| 511 | fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1; | ||
| 512 | size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1; | ||
| 513 | axi_address = PREFETCH_MEM_BASE_0; | ||
| 514 | afi_writel(axi_address, AFI_AXI_BAR3_START); | ||
| 515 | afi_writel(size >> 12, AFI_AXI_BAR3_SZ); | ||
| 516 | afi_writel(fpci_bar, AFI_FPCI_BAR3); | ||
| 517 | |||
| 518 | /* Bar 4: non prefetchable memory BAR */ | ||
| 519 | fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1; | ||
| 520 | size = MEM_SIZE_0 + MEM_SIZE_1; | ||
| 521 | axi_address = MEM_BASE_0; | ||
| 522 | afi_writel(axi_address, AFI_AXI_BAR4_START); | ||
| 523 | afi_writel(size >> 12, AFI_AXI_BAR4_SZ); | ||
| 524 | afi_writel(fpci_bar, AFI_FPCI_BAR4); | ||
| 525 | |||
| 526 | /* Bar 5: NULL out the remaining BAR as it is not used */ | ||
| 527 | fpci_bar = 0; | ||
| 528 | size = 0; | ||
| 529 | axi_address = 0; | ||
| 530 | afi_writel(axi_address, AFI_AXI_BAR5_START); | ||
| 531 | afi_writel(size >> 12, AFI_AXI_BAR5_SZ); | ||
| 532 | afi_writel(fpci_bar, AFI_FPCI_BAR5); | ||
| 533 | |||
| 534 | /* map all upstream transactions as uncached */ | ||
| 535 | afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST); | ||
| 536 | afi_writel(0, AFI_CACHE_BAR0_SZ); | ||
| 537 | afi_writel(0, AFI_CACHE_BAR1_ST); | ||
| 538 | afi_writel(0, AFI_CACHE_BAR1_SZ); | ||
| 539 | |||
| 540 | /* No MSI */ | ||
| 541 | afi_writel(0, AFI_MSI_FPCI_BAR_ST); | ||
| 542 | afi_writel(0, AFI_MSI_BAR_SZ); | ||
| 543 | afi_writel(0, AFI_MSI_AXI_BAR_ST); | ||
| 544 | afi_writel(0, AFI_MSI_BAR_SZ); | ||
| 545 | } | ||
| 546 | |||
| 547 | static int tegra_pcie_enable_controller(void) | ||
| 548 | { | ||
| 549 | u32 val, reg; | ||
| 550 | int i, timeout; | ||
| 551 | |||
| 552 | /* Enable slot clock and pulse the reset signals */ | ||
| 553 | for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { | ||
| 554 | val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN; | ||
| 555 | afi_writel(val, reg); | ||
| 556 | val &= ~AFI_PEX_CTRL_RST; | ||
| 557 | afi_writel(val, reg); | ||
| 558 | |||
| 559 | val = afi_readl(reg) | AFI_PEX_CTRL_RST; | ||
| 560 | afi_writel(val, reg); | ||
| 561 | } | ||
| 562 | |||
| 563 | /* Enable dual controller and both ports */ | ||
| 564 | val = afi_readl(AFI_PCIE_CONFIG); | ||
| 565 | val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | | ||
| 566 | AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | | ||
| 567 | AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK); | ||
| 568 | val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | ||
| 569 | afi_writel(val, AFI_PCIE_CONFIG); | ||
| 570 | |||
| 571 | val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; | ||
| 572 | afi_writel(val, AFI_FUSE); | ||
| 573 | |||
| 574 | /* Initialze internal PHY, enable up to 16 PCIE lanes */ | ||
| 575 | pads_writel(0x0, PADS_CTL_SEL); | ||
| 576 | |||
| 577 | /* override IDDQ to 1 on all 4 lanes */ | ||
| 578 | val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L; | ||
| 579 | pads_writel(val, PADS_CTL); | ||
| 580 | |||
| 581 | /* | ||
| 582 | * set up PHY PLL inputs select PLLE output as refclock, | ||
| 583 | * set TX ref sel to div10 (not div5) | ||
| 584 | */ | ||
| 585 | val = pads_readl(PADS_PLL_CTL); | ||
| 586 | val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); | ||
| 587 | val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); | ||
| 588 | pads_writel(val, PADS_PLL_CTL); | ||
| 589 | |||
| 590 | /* take PLL out of reset */ | ||
| 591 | val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM; | ||
| 592 | pads_writel(val, PADS_PLL_CTL); | ||
| 593 | |||
| 594 | /* | ||
| 595 | * Hack, set the clock voltage to the DEFAULT provided by hw folks. | ||
| 596 | * This doesn't exist in the documentation | ||
| 597 | */ | ||
| 598 | pads_writel(0xfa5cfa5c, 0xc8); | ||
| 599 | |||
| 600 | /* Wait for the PLL to lock */ | ||
| 601 | timeout = 300; | ||
| 602 | do { | ||
| 603 | val = pads_readl(PADS_PLL_CTL); | ||
| 604 | usleep_range(1000, 1000); | ||
| 605 | if (--timeout == 0) { | ||
| 606 | pr_err("Tegra PCIe error: timeout waiting for PLL\n"); | ||
| 607 | return -EBUSY; | ||
| 608 | } | ||
| 609 | } while (!(val & PADS_PLL_CTL_LOCKDET)); | ||
| 610 | |||
| 611 | /* turn off IDDQ override */ | ||
| 612 | val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L; | ||
| 613 | pads_writel(val, PADS_CTL); | ||
| 614 | |||
| 615 | /* enable TX/RX data */ | ||
| 616 | val = pads_readl(PADS_CTL); | ||
| 617 | val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); | ||
| 618 | pads_writel(val, PADS_CTL); | ||
| 619 | |||
| 620 | /* Take the PCIe interface module out of reset */ | ||
| 621 | tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); | ||
| 622 | |||
| 623 | /* Finally enable PCIe */ | ||
| 624 | val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; | ||
| 625 | afi_writel(val, AFI_CONFIGURATION); | ||
| 626 | |||
| 627 | val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | | ||
| 628 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | | ||
| 629 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR); | ||
| 630 | afi_writel(val, AFI_AFI_INTR_ENABLE); | ||
| 631 | afi_writel(0xffffffff, AFI_SM_INTR_ENABLE); | ||
| 632 | |||
| 633 | /* FIXME: No MSI for now, only INT */ | ||
| 634 | afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); | ||
| 635 | |||
| 636 | /* Disable all execptions */ | ||
| 637 | afi_writel(0, AFI_FPCI_ERROR_MASKS); | ||
| 638 | |||
| 639 | return 0; | ||
| 640 | } | ||
| 641 | |||
| 642 | static void tegra_pcie_xclk_clamp(bool clamp) | ||
| 643 | { | ||
| 644 | u32 reg; | ||
| 645 | |||
| 646 | reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; | ||
| 647 | |||
| 648 | if (clamp) | ||
| 649 | reg |= PMC_SCRATCH42_PCX_CLAMP; | ||
| 650 | |||
| 651 | pmc_writel(reg, PMC_SCRATCH42); | ||
| 652 | } | ||
| 653 | |||
| 654 | static void tegra_pcie_power_off(void) | ||
| 655 | { | ||
| 656 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); | ||
| 657 | tegra_periph_reset_assert(tegra_pcie.afi_clk); | ||
| 658 | tegra_periph_reset_assert(tegra_pcie.pex_clk); | ||
| 659 | |||
| 660 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | ||
| 661 | tegra_pcie_xclk_clamp(true); | ||
| 662 | } | ||
| 663 | |||
| 664 | static int tegra_pcie_power_regate(void) | ||
| 665 | { | ||
| 666 | int err; | ||
| 667 | |||
| 668 | tegra_pcie_power_off(); | ||
| 669 | |||
| 670 | tegra_pcie_xclk_clamp(true); | ||
| 671 | |||
| 672 | tegra_periph_reset_assert(tegra_pcie.pcie_xclk); | ||
| 673 | tegra_periph_reset_assert(tegra_pcie.afi_clk); | ||
| 674 | |||
| 675 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, | ||
| 676 | tegra_pcie.pex_clk); | ||
| 677 | if (err) { | ||
| 678 | pr_err("PCIE: powerup sequence failed: %d\n", err); | ||
| 679 | return err; | ||
| 680 | } | ||
| 681 | |||
| 682 | tegra_periph_reset_deassert(tegra_pcie.afi_clk); | ||
| 683 | |||
| 684 | tegra_pcie_xclk_clamp(false); | ||
| 685 | |||
| 686 | clk_prepare_enable(tegra_pcie.afi_clk); | ||
| 687 | clk_prepare_enable(tegra_pcie.pex_clk); | ||
| 688 | return clk_prepare_enable(tegra_pcie.pll_e); | ||
| 689 | } | ||
| 690 | |||
| 691 | static int tegra_pcie_clocks_get(void) | ||
| 692 | { | ||
| 693 | int err; | ||
| 694 | |||
| 695 | tegra_pcie.pex_clk = clk_get(NULL, "pex"); | ||
| 696 | if (IS_ERR(tegra_pcie.pex_clk)) | ||
| 697 | return PTR_ERR(tegra_pcie.pex_clk); | ||
| 698 | |||
| 699 | tegra_pcie.afi_clk = clk_get(NULL, "afi"); | ||
| 700 | if (IS_ERR(tegra_pcie.afi_clk)) { | ||
| 701 | err = PTR_ERR(tegra_pcie.afi_clk); | ||
| 702 | goto err_afi_clk; | ||
| 703 | } | ||
| 704 | |||
| 705 | tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk"); | ||
| 706 | if (IS_ERR(tegra_pcie.pcie_xclk)) { | ||
| 707 | err = PTR_ERR(tegra_pcie.pcie_xclk); | ||
| 708 | goto err_pcie_xclk; | ||
| 709 | } | ||
| 710 | |||
| 711 | tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e"); | ||
| 712 | if (IS_ERR(tegra_pcie.pll_e)) { | ||
| 713 | err = PTR_ERR(tegra_pcie.pll_e); | ||
| 714 | goto err_pll_e; | ||
| 715 | } | ||
| 716 | |||
| 717 | return 0; | ||
| 718 | |||
| 719 | err_pll_e: | ||
| 720 | clk_put(tegra_pcie.pcie_xclk); | ||
| 721 | err_pcie_xclk: | ||
| 722 | clk_put(tegra_pcie.afi_clk); | ||
| 723 | err_afi_clk: | ||
| 724 | clk_put(tegra_pcie.pex_clk); | ||
| 725 | |||
| 726 | return err; | ||
| 727 | } | ||
| 728 | |||
| 729 | static void tegra_pcie_clocks_put(void) | ||
| 730 | { | ||
| 731 | clk_put(tegra_pcie.pll_e); | ||
| 732 | clk_put(tegra_pcie.pcie_xclk); | ||
| 733 | clk_put(tegra_pcie.afi_clk); | ||
| 734 | clk_put(tegra_pcie.pex_clk); | ||
| 735 | } | ||
| 736 | |||
| 737 | static int __init tegra_pcie_get_resources(void) | ||
| 738 | { | ||
| 739 | int err; | ||
| 740 | |||
| 741 | err = tegra_pcie_clocks_get(); | ||
| 742 | if (err) { | ||
| 743 | pr_err("PCIE: failed to get clocks: %d\n", err); | ||
| 744 | return err; | ||
| 745 | } | ||
| 746 | |||
| 747 | err = tegra_pcie_power_regate(); | ||
| 748 | if (err) { | ||
| 749 | pr_err("PCIE: failed to power up: %d\n", err); | ||
| 750 | goto err_pwr_on; | ||
| 751 | } | ||
| 752 | |||
| 753 | tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); | ||
| 754 | if (tegra_pcie.regs == NULL) { | ||
| 755 | pr_err("PCIE: Failed to map PCI/AFI registers\n"); | ||
| 756 | err = -ENOMEM; | ||
| 757 | goto err_map_reg; | ||
| 758 | } | ||
| 759 | |||
| 760 | err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, | ||
| 761 | IRQF_SHARED, "PCIE", &tegra_pcie); | ||
| 762 | if (err) { | ||
| 763 | pr_err("PCIE: Failed to register IRQ: %d\n", err); | ||
| 764 | goto err_req_io; | ||
| 765 | } | ||
| 766 | set_irq_flags(INT_PCIE_INTR, IRQF_VALID); | ||
| 767 | |||
| 768 | return 0; | ||
| 769 | |||
| 770 | err_req_io: | ||
| 771 | iounmap(tegra_pcie.regs); | ||
| 772 | err_map_reg: | ||
| 773 | tegra_pcie_power_off(); | ||
| 774 | err_pwr_on: | ||
| 775 | tegra_pcie_clocks_put(); | ||
| 776 | |||
| 777 | return err; | ||
| 778 | } | ||
| 779 | |||
| 780 | /* | ||
| 781 | * FIXME: If there are no PCIe cards attached, then calling this function | ||
| 782 | * can result in the increase of the bootup time as there are big timeout | ||
| 783 | * loops. | ||
| 784 | */ | ||
| 785 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ | ||
| 786 | static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, | ||
| 787 | u32 reset_reg) | ||
| 788 | { | ||
| 789 | u32 reg; | ||
| 790 | int retries = 3; | ||
| 791 | int timeout; | ||
| 792 | |||
| 793 | do { | ||
| 794 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | ||
| 795 | while (timeout) { | ||
| 796 | reg = readl(pp->base + RP_VEND_XP); | ||
| 797 | |||
| 798 | if (reg & RP_VEND_XP_DL_UP) | ||
| 799 | break; | ||
| 800 | |||
| 801 | mdelay(1); | ||
| 802 | timeout--; | ||
| 803 | } | ||
| 804 | |||
| 805 | if (!timeout) { | ||
| 806 | pr_err("PCIE: port %d: link down, retrying\n", idx); | ||
| 807 | goto retry; | ||
| 808 | } | ||
| 809 | |||
| 810 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | ||
| 811 | while (timeout) { | ||
| 812 | reg = readl(pp->base + RP_LINK_CONTROL_STATUS); | ||
| 813 | |||
| 814 | if (reg & 0x20000000) | ||
| 815 | return true; | ||
| 816 | |||
| 817 | mdelay(1); | ||
| 818 | timeout--; | ||
| 819 | } | ||
| 820 | |||
| 821 | retry: | ||
| 822 | /* Pulse the PEX reset */ | ||
| 823 | reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; | ||
| 824 | afi_writel(reg, reset_reg); | ||
| 825 | mdelay(1); | ||
| 826 | reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; | ||
| 827 | afi_writel(reg, reset_reg); | ||
| 828 | |||
| 829 | retries--; | ||
| 830 | } while (retries); | ||
| 831 | |||
| 832 | return false; | ||
| 833 | } | ||
| 834 | |||
| 835 | static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) | ||
| 836 | { | ||
| 837 | struct tegra_pcie_port *pp; | ||
| 838 | |||
| 839 | pp = tegra_pcie.port + tegra_pcie.num_ports; | ||
| 840 | |||
| 841 | pp->index = -1; | ||
| 842 | pp->base = tegra_pcie.regs + offset; | ||
| 843 | pp->link_up = tegra_pcie_check_link(pp, index, reset_reg); | ||
| 844 | |||
| 845 | if (!pp->link_up) { | ||
| 846 | pp->base = NULL; | ||
| 847 | printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); | ||
| 848 | return; | ||
| 849 | } | ||
| 850 | |||
| 851 | tegra_pcie.num_ports++; | ||
| 852 | pp->index = index; | ||
| 853 | pp->root_bus_nr = -1; | ||
| 854 | memset(pp->res, 0, sizeof(pp->res)); | ||
| 855 | } | ||
| 856 | |||
| 857 | int __init tegra_pcie_init(bool init_port0, bool init_port1) | ||
| 858 | { | ||
| 859 | int err; | ||
| 860 | |||
| 861 | if (!(init_port0 || init_port1)) | ||
| 862 | return -ENODEV; | ||
| 863 | |||
| 864 | pcibios_min_mem = 0; | ||
| 865 | |||
| 866 | err = tegra_pcie_get_resources(); | ||
| 867 | if (err) | ||
| 868 | return err; | ||
| 869 | |||
| 870 | err = tegra_pcie_enable_controller(); | ||
| 871 | if (err) | ||
| 872 | return err; | ||
| 873 | |||
| 874 | /* setup the AFI address translations */ | ||
| 875 | tegra_pcie_setup_translations(); | ||
| 876 | |||
| 877 | if (init_port0) | ||
| 878 | tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL); | ||
| 879 | |||
| 880 | if (init_port1) | ||
| 881 | tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL); | ||
| 882 | |||
| 883 | pci_common_init(&tegra_pcie_hw); | ||
| 884 | |||
| 885 | return 0; | ||
| 886 | } | ||
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 97b33a2a2d75..2d0203627fbb 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
| @@ -196,6 +196,5 @@ struct smp_operations tegra_smp_ops __initdata = { | |||
| 196 | #ifdef CONFIG_HOTPLUG_CPU | 196 | #ifdef CONFIG_HOTPLUG_CPU |
| 197 | .cpu_kill = tegra_cpu_kill, | 197 | .cpu_kill = tegra_cpu_kill, |
| 198 | .cpu_die = tegra_cpu_die, | 198 | .cpu_die = tegra_cpu_die, |
| 199 | .cpu_disable = tegra_cpu_disable, | ||
| 200 | #endif | 199 | #endif |
| 201 | }; | 200 | }; |
diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c new file mode 100644 index 000000000000..d65e1d786400 --- /dev/null +++ b/arch/arm/mach-tegra/pm-tegra20.c | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | |||
| 18 | #include "pm.h" | ||
| 19 | |||
| 20 | #ifdef CONFIG_PM_SLEEP | ||
| 21 | extern u32 tegra20_iram_start, tegra20_iram_end; | ||
| 22 | extern void tegra20_sleep_core_finish(unsigned long); | ||
| 23 | |||
| 24 | void tegra20_lp1_iram_hook(void) | ||
| 25 | { | ||
| 26 | tegra_lp1_iram.start_addr = &tegra20_iram_start; | ||
| 27 | tegra_lp1_iram.end_addr = &tegra20_iram_end; | ||
| 28 | } | ||
| 29 | |||
| 30 | void tegra20_sleep_core_init(void) | ||
| 31 | { | ||
| 32 | tegra_sleep_core_finish = tegra20_sleep_core_finish; | ||
| 33 | } | ||
| 34 | #endif | ||
diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c new file mode 100644 index 000000000000..8fa326d6ff1a --- /dev/null +++ b/arch/arm/mach-tegra/pm-tegra30.c | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | |||
| 18 | #include "pm.h" | ||
| 19 | |||
| 20 | #ifdef CONFIG_PM_SLEEP | ||
| 21 | extern u32 tegra30_iram_start, tegra30_iram_end; | ||
| 22 | extern void tegra30_sleep_core_finish(unsigned long); | ||
| 23 | |||
| 24 | void tegra30_lp1_iram_hook(void) | ||
| 25 | { | ||
| 26 | tegra_lp1_iram.start_addr = &tegra30_iram_start; | ||
| 27 | tegra_lp1_iram.end_addr = &tegra30_iram_end; | ||
| 28 | } | ||
| 29 | |||
| 30 | void tegra30_sleep_core_init(void) | ||
| 31 | { | ||
| 32 | tegra_sleep_core_finish = tegra30_sleep_core_finish; | ||
| 33 | } | ||
| 34 | #endif | ||
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 261fec140c06..ed294a04e1d3 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
| @@ -37,12 +37,18 @@ | |||
| 37 | #include "reset.h" | 37 | #include "reset.h" |
| 38 | #include "flowctrl.h" | 38 | #include "flowctrl.h" |
| 39 | #include "fuse.h" | 39 | #include "fuse.h" |
| 40 | #include "pm.h" | ||
| 40 | #include "pmc.h" | 41 | #include "pmc.h" |
| 41 | #include "sleep.h" | 42 | #include "sleep.h" |
| 42 | 43 | ||
| 43 | #ifdef CONFIG_PM_SLEEP | 44 | #ifdef CONFIG_PM_SLEEP |
| 44 | static DEFINE_SPINLOCK(tegra_lp2_lock); | 45 | static DEFINE_SPINLOCK(tegra_lp2_lock); |
| 46 | static u32 iram_save_size; | ||
| 47 | static void *iram_save_addr; | ||
| 48 | struct tegra_lp1_iram tegra_lp1_iram; | ||
| 45 | void (*tegra_tear_down_cpu)(void); | 49 | void (*tegra_tear_down_cpu)(void); |
| 50 | void (*tegra_sleep_core_finish)(unsigned long v2p); | ||
| 51 | static int (*tegra_sleep_func)(unsigned long v2p); | ||
| 46 | 52 | ||
| 47 | static void tegra_tear_down_cpu_init(void) | 53 | static void tegra_tear_down_cpu_init(void) |
| 48 | { | 54 | { |
| @@ -52,7 +58,9 @@ static void tegra_tear_down_cpu_init(void) | |||
| 52 | tegra_tear_down_cpu = tegra20_tear_down_cpu; | 58 | tegra_tear_down_cpu = tegra20_tear_down_cpu; |
| 53 | break; | 59 | break; |
| 54 | case TEGRA30: | 60 | case TEGRA30: |
| 55 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) | 61 | case TEGRA114: |
| 62 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | ||
| 63 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | ||
| 56 | tegra_tear_down_cpu = tegra30_tear_down_cpu; | 64 | tegra_tear_down_cpu = tegra30_tear_down_cpu; |
| 57 | break; | 65 | break; |
| 58 | } | 66 | } |
| @@ -171,19 +179,109 @@ void tegra_idle_lp2_last(void) | |||
| 171 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | 179 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( |
| 172 | enum tegra_suspend_mode mode) | 180 | enum tegra_suspend_mode mode) |
| 173 | { | 181 | { |
| 174 | /* Tegra114 didn't support any suspending mode yet. */ | ||
| 175 | if (tegra_chip_id == TEGRA114) | ||
| 176 | return TEGRA_SUSPEND_NONE; | ||
| 177 | |||
| 178 | /* | 182 | /* |
| 179 | * The Tegra devices only support suspending to LP2 currently. | 183 | * The Tegra devices support suspending to LP1 or lower currently. |
| 180 | */ | 184 | */ |
| 181 | if (mode > TEGRA_SUSPEND_LP2) | 185 | if (mode > TEGRA_SUSPEND_LP1) |
| 182 | return TEGRA_SUSPEND_LP2; | 186 | return TEGRA_SUSPEND_LP1; |
| 183 | 187 | ||
| 184 | return mode; | 188 | return mode; |
| 185 | } | 189 | } |
| 186 | 190 | ||
| 191 | static int tegra_sleep_core(unsigned long v2p) | ||
| 192 | { | ||
| 193 | setup_mm_for_reboot(); | ||
| 194 | tegra_sleep_core_finish(v2p); | ||
| 195 | |||
| 196 | /* should never here */ | ||
| 197 | BUG(); | ||
| 198 | |||
| 199 | return 0; | ||
| 200 | } | ||
| 201 | |||
| 202 | /* | ||
| 203 | * tegra_lp1_iram_hook | ||
| 204 | * | ||
| 205 | * Hooking the address of LP1 reset vector and SDRAM self-refresh code in | ||
| 206 | * SDRAM. These codes not be copied to IRAM in this fuction. We need to | ||
| 207 | * copy these code to IRAM before LP0/LP1 suspend and restore the content | ||
| 208 | * of IRAM after resume. | ||
| 209 | */ | ||
| 210 | static bool tegra_lp1_iram_hook(void) | ||
| 211 | { | ||
| 212 | switch (tegra_chip_id) { | ||
| 213 | case TEGRA20: | ||
| 214 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | ||
| 215 | tegra20_lp1_iram_hook(); | ||
| 216 | break; | ||
| 217 | case TEGRA30: | ||
| 218 | case TEGRA114: | ||
| 219 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | ||
| 220 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | ||
| 221 | tegra30_lp1_iram_hook(); | ||
| 222 | break; | ||
| 223 | default: | ||
| 224 | break; | ||
| 225 | } | ||
| 226 | |||
| 227 | if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) | ||
| 228 | return false; | ||
| 229 | |||
| 230 | iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; | ||
| 231 | iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); | ||
| 232 | if (!iram_save_addr) | ||
| 233 | return false; | ||
| 234 | |||
| 235 | return true; | ||
| 236 | } | ||
| 237 | |||
| 238 | static bool tegra_sleep_core_init(void) | ||
| 239 | { | ||
| 240 | switch (tegra_chip_id) { | ||
| 241 | case TEGRA20: | ||
| 242 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | ||
| 243 | tegra20_sleep_core_init(); | ||
| 244 | break; | ||
| 245 | case TEGRA30: | ||
| 246 | case TEGRA114: | ||
| 247 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | ||
| 248 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | ||
| 249 | tegra30_sleep_core_init(); | ||
| 250 | break; | ||
| 251 | default: | ||
| 252 | break; | ||
| 253 | } | ||
| 254 | |||
| 255 | if (!tegra_sleep_core_finish) | ||
| 256 | return false; | ||
| 257 | |||
| 258 | return true; | ||
| 259 | } | ||
| 260 | |||
| 261 | static void tegra_suspend_enter_lp1(void) | ||
| 262 | { | ||
| 263 | tegra_pmc_suspend(); | ||
| 264 | |||
| 265 | /* copy the reset vector & SDRAM shutdown code into IRAM */ | ||
| 266 | memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), | ||
| 267 | iram_save_size); | ||
| 268 | memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr, | ||
| 269 | iram_save_size); | ||
| 270 | |||
| 271 | *((u32 *)tegra_cpu_lp1_mask) = 1; | ||
| 272 | } | ||
| 273 | |||
| 274 | static void tegra_suspend_exit_lp1(void) | ||
| 275 | { | ||
| 276 | tegra_pmc_resume(); | ||
| 277 | |||
| 278 | /* restore IRAM */ | ||
| 279 | memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, | ||
| 280 | iram_save_size); | ||
| 281 | |||
| 282 | *(u32 *)tegra_cpu_lp1_mask = 0; | ||
| 283 | } | ||
| 284 | |||
| 187 | static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { | 285 | static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { |
| 188 | [TEGRA_SUSPEND_NONE] = "none", | 286 | [TEGRA_SUSPEND_NONE] = "none", |
| 189 | [TEGRA_SUSPEND_LP2] = "LP2", | 287 | [TEGRA_SUSPEND_LP2] = "LP2", |
| @@ -207,6 +305,9 @@ static int tegra_suspend_enter(suspend_state_t state) | |||
| 207 | 305 | ||
| 208 | suspend_cpu_complex(); | 306 | suspend_cpu_complex(); |
| 209 | switch (mode) { | 307 | switch (mode) { |
| 308 | case TEGRA_SUSPEND_LP1: | ||
| 309 | tegra_suspend_enter_lp1(); | ||
| 310 | break; | ||
| 210 | case TEGRA_SUSPEND_LP2: | 311 | case TEGRA_SUSPEND_LP2: |
| 211 | tegra_set_cpu_in_lp2(); | 312 | tegra_set_cpu_in_lp2(); |
| 212 | break; | 313 | break; |
| @@ -214,9 +315,12 @@ static int tegra_suspend_enter(suspend_state_t state) | |||
| 214 | break; | 315 | break; |
| 215 | } | 316 | } |
| 216 | 317 | ||
| 217 | cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); | 318 | cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); |
| 218 | 319 | ||
| 219 | switch (mode) { | 320 | switch (mode) { |
| 321 | case TEGRA_SUSPEND_LP1: | ||
| 322 | tegra_suspend_exit_lp1(); | ||
| 323 | break; | ||
| 220 | case TEGRA_SUSPEND_LP2: | 324 | case TEGRA_SUSPEND_LP2: |
| 221 | tegra_clear_cpu_in_lp2(); | 325 | tegra_clear_cpu_in_lp2(); |
| 222 | break; | 326 | break; |
| @@ -237,12 +341,36 @@ static const struct platform_suspend_ops tegra_suspend_ops = { | |||
| 237 | 341 | ||
| 238 | void __init tegra_init_suspend(void) | 342 | void __init tegra_init_suspend(void) |
| 239 | { | 343 | { |
| 240 | if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) | 344 | enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); |
| 345 | |||
| 346 | if (mode == TEGRA_SUSPEND_NONE) | ||
| 241 | return; | 347 | return; |
| 242 | 348 | ||
| 243 | tegra_tear_down_cpu_init(); | 349 | tegra_tear_down_cpu_init(); |
| 244 | tegra_pmc_suspend_init(); | 350 | tegra_pmc_suspend_init(); |
| 245 | 351 | ||
| 352 | if (mode >= TEGRA_SUSPEND_LP1) { | ||
| 353 | if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { | ||
| 354 | pr_err("%s: unable to allocate memory for SDRAM" | ||
| 355 | "self-refresh -- LP0/LP1 unavailable\n", | ||
| 356 | __func__); | ||
| 357 | tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); | ||
| 358 | mode = TEGRA_SUSPEND_LP2; | ||
| 359 | } | ||
| 360 | } | ||
| 361 | |||
| 362 | /* set up sleep function for cpu_suspend */ | ||
| 363 | switch (mode) { | ||
| 364 | case TEGRA_SUSPEND_LP1: | ||
| 365 | tegra_sleep_func = tegra_sleep_core; | ||
| 366 | break; | ||
| 367 | case TEGRA_SUSPEND_LP2: | ||
| 368 | tegra_sleep_func = tegra_sleep_cpu; | ||
| 369 | break; | ||
| 370 | default: | ||
| 371 | break; | ||
| 372 | } | ||
| 373 | |||
| 246 | suspend_set_ops(&tegra_suspend_ops); | 374 | suspend_set_ops(&tegra_suspend_ops); |
| 247 | } | 375 | } |
| 248 | #endif | 376 | #endif |
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 94c4b9d9077c..fe204e5256e7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h | |||
| @@ -23,6 +23,18 @@ | |||
| 23 | 23 | ||
| 24 | #include "pmc.h" | 24 | #include "pmc.h" |
| 25 | 25 | ||
| 26 | struct tegra_lp1_iram { | ||
| 27 | void *start_addr; | ||
| 28 | void *end_addr; | ||
| 29 | }; | ||
| 30 | extern struct tegra_lp1_iram tegra_lp1_iram; | ||
| 31 | extern void (*tegra_sleep_core_finish)(unsigned long v2p); | ||
| 32 | |||
| 33 | void tegra20_lp1_iram_hook(void); | ||
| 34 | void tegra20_sleep_core_init(void); | ||
| 35 | void tegra30_lp1_iram_hook(void); | ||
| 36 | void tegra30_sleep_core_init(void); | ||
| 37 | |||
| 26 | extern unsigned long l2x0_saved_regs_addr; | 38 | extern unsigned long l2x0_saved_regs_addr; |
| 27 | 39 | ||
| 28 | void save_cpu_arch_register(void); | 40 | void save_cpu_arch_register(void); |
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index eb3fa4aee0e4..8acb881f7cfe 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c | |||
| @@ -21,11 +21,14 @@ | |||
| 21 | #include <linux/of.h> | 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
| 23 | 23 | ||
| 24 | #include "flowctrl.h" | ||
| 24 | #include "fuse.h" | 25 | #include "fuse.h" |
| 25 | #include "pm.h" | 26 | #include "pm.h" |
| 26 | #include "pmc.h" | 27 | #include "pmc.h" |
| 27 | #include "sleep.h" | 28 | #include "sleep.h" |
| 28 | 29 | ||
| 30 | #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ | ||
| 31 | #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */ | ||
| 29 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ | 32 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ |
| 30 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ | 33 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ |
| 31 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | 34 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ |
| @@ -193,16 +196,50 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | |||
| 193 | return pmc_pm_data.suspend_mode; | 196 | return pmc_pm_data.suspend_mode; |
| 194 | } | 197 | } |
| 195 | 198 | ||
| 199 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) | ||
| 200 | { | ||
| 201 | if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) | ||
| 202 | return; | ||
| 203 | |||
| 204 | pmc_pm_data.suspend_mode = mode; | ||
| 205 | } | ||
| 206 | |||
| 207 | void tegra_pmc_suspend(void) | ||
| 208 | { | ||
| 209 | tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); | ||
| 210 | } | ||
| 211 | |||
| 212 | void tegra_pmc_resume(void) | ||
| 213 | { | ||
| 214 | tegra_pmc_writel(0x0, PMC_SCRATCH41); | ||
| 215 | } | ||
| 216 | |||
| 196 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) | 217 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) |
| 197 | { | 218 | { |
| 198 | u32 reg; | 219 | u32 reg, csr_reg; |
| 199 | unsigned long rate = 0; | 220 | unsigned long rate = 0; |
| 200 | 221 | ||
| 201 | reg = tegra_pmc_readl(PMC_CTRL); | 222 | reg = tegra_pmc_readl(PMC_CTRL); |
| 202 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | 223 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; |
| 203 | reg &= ~TEGRA_POWER_EFFECT_LP0; | 224 | reg &= ~TEGRA_POWER_EFFECT_LP0; |
| 204 | 225 | ||
| 226 | switch (tegra_chip_id) { | ||
| 227 | case TEGRA20: | ||
| 228 | case TEGRA30: | ||
| 229 | break; | ||
| 230 | default: | ||
| 231 | /* Turn off CRAIL */ | ||
| 232 | csr_reg = flowctrl_read_cpu_csr(0); | ||
| 233 | csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; | ||
| 234 | csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; | ||
| 235 | flowctrl_write_cpu_csr(0, csr_reg); | ||
| 236 | break; | ||
| 237 | } | ||
| 238 | |||
| 205 | switch (mode) { | 239 | switch (mode) { |
| 240 | case TEGRA_SUSPEND_LP1: | ||
| 241 | rate = 32768; | ||
| 242 | break; | ||
| 206 | case TEGRA_SUSPEND_LP2: | 243 | case TEGRA_SUSPEND_LP2: |
| 207 | rate = clk_get_rate(tegra_pclk); | 244 | rate = clk_get_rate(tegra_pclk); |
| 208 | break; | 245 | break; |
| @@ -224,6 +261,20 @@ void tegra_pmc_suspend_init(void) | |||
| 224 | reg = tegra_pmc_readl(PMC_CTRL); | 261 | reg = tegra_pmc_readl(PMC_CTRL); |
| 225 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | 262 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; |
| 226 | tegra_pmc_writel(reg, PMC_CTRL); | 263 | tegra_pmc_writel(reg, PMC_CTRL); |
| 264 | |||
| 265 | reg = tegra_pmc_readl(PMC_CTRL); | ||
| 266 | |||
| 267 | if (!pmc_pm_data.sysclkreq_high) | ||
| 268 | reg |= TEGRA_POWER_SYSCLK_POLARITY; | ||
| 269 | else | ||
| 270 | reg &= ~TEGRA_POWER_SYSCLK_POLARITY; | ||
| 271 | |||
| 272 | /* configure the output polarity while the request is tristated */ | ||
| 273 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 274 | |||
| 275 | /* now enable the request */ | ||
| 276 | reg |= TEGRA_POWER_SYSCLK_OE; | ||
| 277 | tegra_pmc_writel(reg, PMC_CTRL); | ||
| 227 | } | 278 | } |
| 228 | #endif | 279 | #endif |
| 229 | 280 | ||
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index e1c2df272f7d..549f8c7b762c 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h | |||
| @@ -28,6 +28,9 @@ enum tegra_suspend_mode { | |||
| 28 | 28 | ||
| 29 | #ifdef CONFIG_PM_SLEEP | 29 | #ifdef CONFIG_PM_SLEEP |
| 30 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); | 30 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); |
| 31 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); | ||
| 32 | void tegra_pmc_suspend(void); | ||
| 33 | void tegra_pmc_resume(void); | ||
| 31 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode); | 34 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode); |
| 32 | void tegra_pmc_suspend_init(void); | 35 | void tegra_pmc_suspend_init(void); |
| 33 | #endif | 36 | #endif |
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 39dc9e7834f3..f527b2c2dea7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S | |||
| @@ -40,9 +40,12 @@ | |||
| 40 | * re-enabling sdram. | 40 | * re-enabling sdram. |
| 41 | * | 41 | * |
| 42 | * r6: SoC ID | 42 | * r6: SoC ID |
| 43 | * r8: CPU part number | ||
| 43 | */ | 44 | */ |
| 44 | ENTRY(tegra_resume) | 45 | ENTRY(tegra_resume) |
| 45 | bl v7_invalidate_l1 | 46 | check_cpu_part_num 0xc09, r8, r9 |
| 47 | bleq v7_invalidate_l1 | ||
| 48 | blne tegra_init_l2_for_a15 | ||
| 46 | 49 | ||
| 47 | cpu_id r0 | 50 | cpu_id r0 |
| 48 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 | 51 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 |
| @@ -70,7 +73,8 @@ no_cpu0_chk: | |||
| 70 | str r1, [r2] | 73 | str r1, [r2] |
| 71 | 1: | 74 | 1: |
| 72 | 75 | ||
| 73 | check_cpu_part_num 0xc09, r8, r9 | 76 | mov32 r9, 0xc09 |
| 77 | cmp r8, r9 | ||
| 74 | bne not_ca9 | 78 | bne not_ca9 |
| 75 | #ifdef CONFIG_HAVE_ARM_SCU | 79 | #ifdef CONFIG_HAVE_ARM_SCU |
| 76 | /* enable SCU */ | 80 | /* enable SCU */ |
| @@ -178,6 +182,19 @@ after_errata: | |||
| 178 | 1: | 182 | 1: |
| 179 | #endif | 183 | #endif |
| 180 | 184 | ||
| 185 | /* Waking up from LP1? */ | ||
| 186 | ldr r8, [r12, #RESET_DATA(MASK_LP1)] | ||
| 187 | tst r8, r11 @ if in_lp1 | ||
| 188 | beq __is_not_lp1 | ||
| 189 | cmp r10, #0 | ||
| 190 | bne __die @ only CPU0 can be here | ||
| 191 | ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] | ||
| 192 | cmp lr, #0 | ||
| 193 | bleq __die @ no LP1 startup handler | ||
| 194 | THUMB( add lr, lr, #1 ) @ switch to Thumb mode | ||
| 195 | bx lr | ||
| 196 | __is_not_lp1: | ||
| 197 | |||
| 181 | /* Waking up from LP2? */ | 198 | /* Waking up from LP2? */ |
| 182 | ldr r9, [r12, #RESET_DATA(MASK_LP2)] | 199 | ldr r9, [r12, #RESET_DATA(MASK_LP2)] |
| 183 | tst r9, r11 @ if in_lp2 | 200 | tst r9, r11 @ if in_lp2 |
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e0068f..fd0bbf8a6c94 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c | |||
| @@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void) | |||
| 81 | #endif | 81 | #endif |
| 82 | 82 | ||
| 83 | #ifdef CONFIG_PM_SLEEP | 83 | #ifdef CONFIG_PM_SLEEP |
| 84 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = | ||
| 85 | TEGRA_IRAM_CODE_AREA; | ||
| 84 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = | 86 | __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = |
| 85 | virt_to_phys((void *)tegra_resume); | 87 | virt_to_phys((void *)tegra_resume); |
| 86 | #endif | 88 | #endif |
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index c90d8e9c4ad2..76a93434c6ee 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h | |||
| @@ -39,6 +39,10 @@ void __tegra_cpu_reset_handler_end(void); | |||
| 39 | void tegra_secondary_startup(void); | 39 | void tegra_secondary_startup(void); |
| 40 | 40 | ||
| 41 | #ifdef CONFIG_PM_SLEEP | 41 | #ifdef CONFIG_PM_SLEEP |
| 42 | #define tegra_cpu_lp1_mask \ | ||
| 43 | (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ | ||
| 44 | ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ | ||
| 45 | (u32)__tegra_cpu_reset_handler_start))) | ||
| 42 | #define tegra_cpu_lp2_mask \ | 46 | #define tegra_cpu_lp2_mask \ |
| 43 | (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ | 47 | (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ |
| 44 | ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ | 48 | ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ |
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index e3f2417c420e..5c3bd11c9838 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S | |||
| @@ -23,10 +23,49 @@ | |||
| 23 | #include <asm/assembler.h> | 23 | #include <asm/assembler.h> |
| 24 | #include <asm/proc-fns.h> | 24 | #include <asm/proc-fns.h> |
| 25 | #include <asm/cp15.h> | 25 | #include <asm/cp15.h> |
| 26 | #include <asm/cache.h> | ||
| 26 | 27 | ||
| 27 | #include "sleep.h" | 28 | #include "sleep.h" |
| 28 | #include "flowctrl.h" | 29 | #include "flowctrl.h" |
| 29 | 30 | ||
| 31 | #define EMC_CFG 0xc | ||
| 32 | #define EMC_ADR_CFG 0x10 | ||
| 33 | #define EMC_REFRESH 0x70 | ||
| 34 | #define EMC_NOP 0xdc | ||
| 35 | #define EMC_SELF_REF 0xe0 | ||
| 36 | #define EMC_REQ_CTRL 0x2b0 | ||
| 37 | #define EMC_EMC_STATUS 0x2b4 | ||
| 38 | |||
| 39 | #define CLK_RESET_CCLK_BURST 0x20 | ||
| 40 | #define CLK_RESET_CCLK_DIVIDER 0x24 | ||
| 41 | #define CLK_RESET_SCLK_BURST 0x28 | ||
| 42 | #define CLK_RESET_SCLK_DIVIDER 0x2c | ||
| 43 | #define CLK_RESET_PLLC_BASE 0x80 | ||
| 44 | #define CLK_RESET_PLLM_BASE 0x90 | ||
| 45 | #define CLK_RESET_PLLP_BASE 0xa0 | ||
| 46 | |||
| 47 | #define APB_MISC_XM2CFGCPADCTRL 0x8c8 | ||
| 48 | #define APB_MISC_XM2CFGDPADCTRL 0x8cc | ||
| 49 | #define APB_MISC_XM2CLKCFGPADCTRL 0x8d0 | ||
| 50 | #define APB_MISC_XM2COMPPADCTRL 0x8d4 | ||
| 51 | #define APB_MISC_XM2VTTGENPADCTRL 0x8d8 | ||
| 52 | #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 | ||
| 53 | #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 | ||
| 54 | |||
| 55 | .macro pll_enable, rd, r_car_base, pll_base | ||
| 56 | ldr \rd, [\r_car_base, #\pll_base] | ||
| 57 | tst \rd, #(1 << 30) | ||
| 58 | orreq \rd, \rd, #(1 << 30) | ||
| 59 | streq \rd, [\r_car_base, #\pll_base] | ||
| 60 | .endm | ||
| 61 | |||
| 62 | .macro emc_device_mask, rd, base | ||
| 63 | ldr \rd, [\base, #EMC_ADR_CFG] | ||
| 64 | tst \rd, #(0x3 << 24) | ||
| 65 | moveq \rd, #(0x1 << 8) @ just 1 device | ||
| 66 | movne \rd, #(0x3 << 8) @ 2 devices | ||
| 67 | .endm | ||
| 68 | |||
| 30 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) | 69 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) |
| 31 | /* | 70 | /* |
| 32 | * tegra20_hotplug_shutdown(void) | 71 | * tegra20_hotplug_shutdown(void) |
| @@ -181,6 +220,28 @@ ENTRY(tegra20_cpu_is_resettable_soon) | |||
| 181 | ENDPROC(tegra20_cpu_is_resettable_soon) | 220 | ENDPROC(tegra20_cpu_is_resettable_soon) |
| 182 | 221 | ||
| 183 | /* | 222 | /* |
| 223 | * tegra20_sleep_core_finish(unsigned long v2p) | ||
| 224 | * | ||
| 225 | * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to | ||
| 226 | * tegra20_tear_down_core in IRAM | ||
| 227 | */ | ||
| 228 | ENTRY(tegra20_sleep_core_finish) | ||
| 229 | /* Flush, disable the L1 data cache and exit SMP */ | ||
| 230 | bl tegra_disable_clean_inv_dcache | ||
| 231 | |||
| 232 | mov32 r3, tegra_shut_off_mmu | ||
| 233 | add r3, r3, r0 | ||
| 234 | |||
| 235 | mov32 r0, tegra20_tear_down_core | ||
| 236 | mov32 r1, tegra20_iram_start | ||
| 237 | sub r0, r0, r1 | ||
| 238 | mov32 r1, TEGRA_IRAM_CODE_AREA | ||
| 239 | add r0, r0, r1 | ||
| 240 | |||
| 241 | mov pc, r3 | ||
| 242 | ENDPROC(tegra20_sleep_core_finish) | ||
| 243 | |||
| 244 | /* | ||
| 184 | * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) | 245 | * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) |
| 185 | * | 246 | * |
| 186 | * Enters WFI on secondary CPU by exiting coherency. | 247 | * Enters WFI on secondary CPU by exiting coherency. |
| @@ -191,6 +252,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) | |||
| 191 | mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency | 252 | mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency |
| 192 | 253 | ||
| 193 | /* Flush and disable the L1 data cache */ | 254 | /* Flush and disable the L1 data cache */ |
| 255 | mov r0, #TEGRA_FLUSH_CACHE_LOUIS | ||
| 194 | bl tegra_disable_clean_inv_dcache | 256 | bl tegra_disable_clean_inv_dcache |
| 195 | 257 | ||
| 196 | mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 | 258 | mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 |
| @@ -250,6 +312,150 @@ ENTRY(tegra20_tear_down_cpu) | |||
| 250 | b tegra20_enter_sleep | 312 | b tegra20_enter_sleep |
| 251 | ENDPROC(tegra20_tear_down_cpu) | 313 | ENDPROC(tegra20_tear_down_cpu) |
| 252 | 314 | ||
| 315 | /* START OF ROUTINES COPIED TO IRAM */ | ||
| 316 | .align L1_CACHE_SHIFT | ||
| 317 | .globl tegra20_iram_start | ||
| 318 | tegra20_iram_start: | ||
| 319 | |||
| 320 | /* | ||
| 321 | * tegra20_lp1_reset | ||
| 322 | * | ||
| 323 | * reset vector for LP1 restore; copied into IRAM during suspend. | ||
| 324 | * Brings the system back up to a safe staring point (SDRAM out of | ||
| 325 | * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP, | ||
| 326 | * system clock running on the same PLL that it suspended at), and | ||
| 327 | * jumps to tegra_resume to restore virtual addressing and PLLX. | ||
| 328 | * The physical address of tegra_resume expected to be stored in | ||
| 329 | * PMC_SCRATCH41. | ||
| 330 | * | ||
| 331 | * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. | ||
| 332 | */ | ||
| 333 | ENTRY(tegra20_lp1_reset) | ||
| 334 | /* | ||
| 335 | * The CPU and system bus are running at 32KHz and executing from | ||
| 336 | * IRAM when this code is executed; immediately switch to CLKM and | ||
| 337 | * enable PLLM, PLLP, PLLC. | ||
| 338 | */ | ||
| 339 | mov32 r0, TEGRA_CLK_RESET_BASE | ||
| 340 | |||
| 341 | mov r1, #(1 << 28) | ||
| 342 | str r1, [r0, #CLK_RESET_SCLK_BURST] | ||
| 343 | str r1, [r0, #CLK_RESET_CCLK_BURST] | ||
| 344 | mov r1, #0 | ||
| 345 | str r1, [r0, #CLK_RESET_CCLK_DIVIDER] | ||
| 346 | str r1, [r0, #CLK_RESET_SCLK_DIVIDER] | ||
| 347 | |||
| 348 | pll_enable r1, r0, CLK_RESET_PLLM_BASE | ||
| 349 | pll_enable r1, r0, CLK_RESET_PLLP_BASE | ||
| 350 | pll_enable r1, r0, CLK_RESET_PLLC_BASE | ||
| 351 | |||
| 352 | adr r2, tegra20_sdram_pad_address | ||
| 353 | adr r4, tegra20_sdram_pad_save | ||
| 354 | mov r5, #0 | ||
| 355 | |||
| 356 | ldr r6, tegra20_sdram_pad_size | ||
| 357 | padload: | ||
| 358 | ldr r7, [r2, r5] @ r7 is the addr in the pad_address | ||
| 359 | |||
| 360 | ldr r1, [r4, r5] | ||
| 361 | str r1, [r7] @ restore the value in pad_save | ||
| 362 | |||
| 363 | add r5, r5, #4 | ||
| 364 | cmp r6, r5 | ||
| 365 | bne padload | ||
| 366 | |||
| 367 | padload_done: | ||
| 368 | /* 255uS delay for PLL stabilization */ | ||
| 369 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 370 | ldr r1, [r7] | ||
| 371 | add r1, r1, #0xff | ||
| 372 | wait_until r1, r7, r9 | ||
| 373 | |||
| 374 | adr r4, tegra20_sclk_save | ||
| 375 | ldr r4, [r4] | ||
| 376 | str r4, [r0, #CLK_RESET_SCLK_BURST] | ||
| 377 | mov32 r4, ((1 << 28) | (4)) @ burst policy is PLLP | ||
| 378 | str r4, [r0, #CLK_RESET_CCLK_BURST] | ||
| 379 | |||
| 380 | mov32 r0, TEGRA_EMC_BASE | ||
| 381 | ldr r1, [r0, #EMC_CFG] | ||
| 382 | bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP | ||
| 383 | str r1, [r0, #EMC_CFG] | ||
| 384 | |||
| 385 | mov r1, #0 | ||
| 386 | str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh | ||
| 387 | mov r1, #1 | ||
| 388 | str r1, [r0, #EMC_NOP] | ||
| 389 | str r1, [r0, #EMC_NOP] | ||
| 390 | str r1, [r0, #EMC_REFRESH] | ||
| 391 | |||
| 392 | emc_device_mask r1, r0 | ||
| 393 | |||
| 394 | exit_selfrefresh_loop: | ||
| 395 | ldr r2, [r0, #EMC_EMC_STATUS] | ||
| 396 | ands r2, r2, r1 | ||
| 397 | bne exit_selfrefresh_loop | ||
| 398 | |||
| 399 | mov r1, #0 @ unstall all transactions | ||
| 400 | str r1, [r0, #EMC_REQ_CTRL] | ||
| 401 | |||
| 402 | mov32 r0, TEGRA_PMC_BASE | ||
| 403 | ldr r0, [r0, #PMC_SCRATCH41] | ||
| 404 | mov pc, r0 @ jump to tegra_resume | ||
| 405 | ENDPROC(tegra20_lp1_reset) | ||
| 406 | |||
| 407 | /* | ||
| 408 | * tegra20_tear_down_core | ||
| 409 | * | ||
| 410 | * copied into and executed from IRAM | ||
| 411 | * puts memory in self-refresh for LP0 and LP1 | ||
| 412 | */ | ||
| 413 | tegra20_tear_down_core: | ||
| 414 | bl tegra20_sdram_self_refresh | ||
| 415 | bl tegra20_switch_cpu_to_clk32k | ||
| 416 | b tegra20_enter_sleep | ||
| 417 | |||
| 418 | /* | ||
| 419 | * tegra20_switch_cpu_to_clk32k | ||
| 420 | * | ||
| 421 | * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock | ||
| 422 | * to the 32KHz clock. | ||
| 423 | */ | ||
| 424 | tegra20_switch_cpu_to_clk32k: | ||
| 425 | /* | ||
| 426 | * start by switching to CLKM to safely disable PLLs, then switch to | ||
| 427 | * CLKS. | ||
| 428 | */ | ||
| 429 | mov r0, #(1 << 28) | ||
| 430 | str r0, [r5, #CLK_RESET_SCLK_BURST] | ||
| 431 | str r0, [r5, #CLK_RESET_CCLK_BURST] | ||
| 432 | mov r0, #0 | ||
| 433 | str r0, [r5, #CLK_RESET_CCLK_DIVIDER] | ||
| 434 | str r0, [r5, #CLK_RESET_SCLK_DIVIDER] | ||
| 435 | |||
| 436 | /* 2uS delay delay between changing SCLK and disabling PLLs */ | ||
| 437 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 438 | ldr r1, [r7] | ||
| 439 | add r1, r1, #2 | ||
| 440 | wait_until r1, r7, r9 | ||
| 441 | |||
| 442 | /* disable PLLM, PLLP and PLLC */ | ||
| 443 | ldr r0, [r5, #CLK_RESET_PLLM_BASE] | ||
| 444 | bic r0, r0, #(1 << 30) | ||
| 445 | str r0, [r5, #CLK_RESET_PLLM_BASE] | ||
| 446 | ldr r0, [r5, #CLK_RESET_PLLP_BASE] | ||
| 447 | bic r0, r0, #(1 << 30) | ||
| 448 | str r0, [r5, #CLK_RESET_PLLP_BASE] | ||
| 449 | ldr r0, [r5, #CLK_RESET_PLLC_BASE] | ||
| 450 | bic r0, r0, #(1 << 30) | ||
| 451 | str r0, [r5, #CLK_RESET_PLLC_BASE] | ||
| 452 | |||
| 453 | /* switch to CLKS */ | ||
| 454 | mov r0, #0 /* brust policy = 32KHz */ | ||
| 455 | str r0, [r5, #CLK_RESET_SCLK_BURST] | ||
| 456 | |||
| 457 | mov pc, lr | ||
| 458 | |||
| 253 | /* | 459 | /* |
| 254 | * tegra20_enter_sleep | 460 | * tegra20_enter_sleep |
| 255 | * | 461 | * |
| @@ -274,4 +480,95 @@ halted: | |||
| 274 | isb | 480 | isb |
| 275 | b halted | 481 | b halted |
| 276 | 482 | ||
| 483 | /* | ||
| 484 | * tegra20_sdram_self_refresh | ||
| 485 | * | ||
| 486 | * called with MMU off and caches disabled | ||
| 487 | * puts sdram in self refresh | ||
| 488 | * must be executed from IRAM | ||
| 489 | */ | ||
| 490 | tegra20_sdram_self_refresh: | ||
| 491 | mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr | ||
| 492 | |||
| 493 | mov r2, #3 | ||
| 494 | str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests | ||
| 495 | |||
| 496 | emcidle: | ||
| 497 | ldr r2, [r1, #EMC_EMC_STATUS] | ||
| 498 | tst r2, #4 | ||
| 499 | beq emcidle | ||
| 500 | |||
| 501 | mov r2, #1 | ||
| 502 | str r2, [r1, #EMC_SELF_REF] | ||
| 503 | |||
| 504 | emc_device_mask r2, r1 | ||
| 505 | |||
| 506 | emcself: | ||
| 507 | ldr r3, [r1, #EMC_EMC_STATUS] | ||
| 508 | and r3, r3, r2 | ||
| 509 | cmp r3, r2 | ||
| 510 | bne emcself @ loop until DDR in self-refresh | ||
| 511 | |||
| 512 | adr r2, tegra20_sdram_pad_address | ||
| 513 | adr r3, tegra20_sdram_pad_safe | ||
| 514 | adr r4, tegra20_sdram_pad_save | ||
| 515 | mov r5, #0 | ||
| 516 | |||
| 517 | ldr r6, tegra20_sdram_pad_size | ||
| 518 | padsave: | ||
| 519 | ldr r0, [r2, r5] @ r0 is the addr in the pad_address | ||
| 520 | |||
| 521 | ldr r1, [r0] | ||
| 522 | str r1, [r4, r5] @ save the content of the addr | ||
| 523 | |||
| 524 | ldr r1, [r3, r5] | ||
| 525 | str r1, [r0] @ set the save val to the addr | ||
| 526 | |||
| 527 | add r5, r5, #4 | ||
| 528 | cmp r6, r5 | ||
| 529 | bne padsave | ||
| 530 | padsave_done: | ||
| 531 | |||
| 532 | mov32 r5, TEGRA_CLK_RESET_BASE | ||
| 533 | ldr r0, [r5, #CLK_RESET_SCLK_BURST] | ||
| 534 | adr r2, tegra20_sclk_save | ||
| 535 | str r0, [r2] | ||
| 536 | dsb | ||
| 537 | mov pc, lr | ||
| 538 | |||
| 539 | tegra20_sdram_pad_address: | ||
| 540 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL | ||
| 541 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL | ||
| 542 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CLKCFGPADCTRL | ||
| 543 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2COMPPADCTRL | ||
| 544 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2VTTGENPADCTRL | ||
| 545 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL2 | ||
| 546 | .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL2 | ||
| 547 | |||
| 548 | tegra20_sdram_pad_size: | ||
| 549 | .word tegra20_sdram_pad_size - tegra20_sdram_pad_address | ||
| 550 | |||
| 551 | tegra20_sdram_pad_safe: | ||
| 552 | .word 0x8 | ||
| 553 | .word 0x8 | ||
| 554 | .word 0x0 | ||
| 555 | .word 0x8 | ||
| 556 | .word 0x5500 | ||
| 557 | .word 0x08080040 | ||
| 558 | .word 0x0 | ||
| 559 | |||
| 560 | tegra20_sclk_save: | ||
| 561 | .word 0x0 | ||
| 562 | |||
| 563 | tegra20_sdram_pad_save: | ||
| 564 | .rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4 | ||
| 565 | .long 0 | ||
| 566 | .endr | ||
| 567 | |||
| 568 | .ltorg | ||
| 569 | /* dummy symbol for end of IRAM */ | ||
| 570 | .align L1_CACHE_SHIFT | ||
| 571 | .globl tegra20_iram_end | ||
| 572 | tegra20_iram_end: | ||
| 573 | b . | ||
| 277 | #endif | 574 | #endif |
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index ada8821b48be..63fa91b5fafb 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S | |||
| @@ -18,13 +18,118 @@ | |||
| 18 | 18 | ||
| 19 | #include <asm/assembler.h> | 19 | #include <asm/assembler.h> |
| 20 | #include <asm/asm-offsets.h> | 20 | #include <asm/asm-offsets.h> |
| 21 | #include <asm/cache.h> | ||
| 21 | 22 | ||
| 22 | #include "fuse.h" | 23 | #include "fuse.h" |
| 23 | #include "sleep.h" | 24 | #include "sleep.h" |
| 24 | #include "flowctrl.h" | 25 | #include "flowctrl.h" |
| 25 | 26 | ||
| 27 | #define EMC_CFG 0xc | ||
| 28 | #define EMC_ADR_CFG 0x10 | ||
| 29 | #define EMC_TIMING_CONTROL 0x28 | ||
| 30 | #define EMC_REFRESH 0x70 | ||
| 31 | #define EMC_NOP 0xdc | ||
| 32 | #define EMC_SELF_REF 0xe0 | ||
| 33 | #define EMC_MRW 0xe8 | ||
| 34 | #define EMC_FBIO_CFG5 0x104 | ||
| 35 | #define EMC_AUTO_CAL_CONFIG 0x2a4 | ||
| 36 | #define EMC_AUTO_CAL_INTERVAL 0x2a8 | ||
| 37 | #define EMC_AUTO_CAL_STATUS 0x2ac | ||
| 38 | #define EMC_REQ_CTRL 0x2b0 | ||
| 39 | #define EMC_CFG_DIG_DLL 0x2bc | ||
| 40 | #define EMC_EMC_STATUS 0x2b4 | ||
| 41 | #define EMC_ZCAL_INTERVAL 0x2e0 | ||
| 42 | #define EMC_ZQ_CAL 0x2ec | ||
| 43 | #define EMC_XM2VTTGENPADCTRL 0x310 | ||
| 44 | #define EMC_XM2VTTGENPADCTRL2 0x314 | ||
| 45 | |||
| 46 | #define PMC_CTRL 0x0 | ||
| 47 | #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */ | ||
| 48 | |||
| 49 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | ||
| 50 | #define PMC_IO_DPD_REQ 0x1b8 | ||
| 51 | #define PMC_IO_DPD_STATUS 0x1bc | ||
| 52 | |||
| 53 | #define CLK_RESET_CCLK_BURST 0x20 | ||
| 54 | #define CLK_RESET_CCLK_DIVIDER 0x24 | ||
| 55 | #define CLK_RESET_SCLK_BURST 0x28 | ||
| 56 | #define CLK_RESET_SCLK_DIVIDER 0x2c | ||
| 57 | |||
| 58 | #define CLK_RESET_PLLC_BASE 0x80 | ||
| 59 | #define CLK_RESET_PLLC_MISC 0x8c | ||
| 60 | #define CLK_RESET_PLLM_BASE 0x90 | ||
| 61 | #define CLK_RESET_PLLM_MISC 0x9c | ||
| 62 | #define CLK_RESET_PLLP_BASE 0xa0 | ||
| 63 | #define CLK_RESET_PLLP_MISC 0xac | ||
| 64 | #define CLK_RESET_PLLA_BASE 0xb0 | ||
| 65 | #define CLK_RESET_PLLA_MISC 0xbc | ||
| 66 | #define CLK_RESET_PLLX_BASE 0xe0 | ||
| 67 | #define CLK_RESET_PLLX_MISC 0xe4 | ||
| 68 | #define CLK_RESET_PLLX_MISC3 0x518 | ||
| 69 | #define CLK_RESET_PLLX_MISC3_IDDQ 3 | ||
| 70 | #define CLK_RESET_PLLM_MISC_IDDQ 5 | ||
| 71 | #define CLK_RESET_PLLC_MISC_IDDQ 26 | ||
| 72 | |||
| 73 | #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 | ||
| 74 | |||
| 75 | #define MSELECT_CLKM (0x3 << 30) | ||
| 76 | |||
| 77 | #define LOCK_DELAY 50 /* safety delay after lock is detected */ | ||
| 78 | |||
| 26 | #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ | 79 | #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ |
| 27 | 80 | ||
| 81 | .macro emc_device_mask, rd, base | ||
| 82 | ldr \rd, [\base, #EMC_ADR_CFG] | ||
| 83 | tst \rd, #0x1 | ||
| 84 | moveq \rd, #(0x1 << 8) @ just 1 device | ||
| 85 | movne \rd, #(0x3 << 8) @ 2 devices | ||
| 86 | .endm | ||
| 87 | |||
| 88 | .macro emc_timing_update, rd, base | ||
| 89 | mov \rd, #1 | ||
| 90 | str \rd, [\base, #EMC_TIMING_CONTROL] | ||
| 91 | 1001: | ||
| 92 | ldr \rd, [\base, #EMC_EMC_STATUS] | ||
| 93 | tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear | ||
| 94 | bne 1001b | ||
| 95 | .endm | ||
| 96 | |||
| 97 | .macro pll_enable, rd, r_car_base, pll_base, pll_misc | ||
| 98 | ldr \rd, [\r_car_base, #\pll_base] | ||
| 99 | tst \rd, #(1 << 30) | ||
| 100 | orreq \rd, \rd, #(1 << 30) | ||
| 101 | streq \rd, [\r_car_base, #\pll_base] | ||
| 102 | /* Enable lock detector */ | ||
| 103 | .if \pll_misc | ||
| 104 | ldr \rd, [\r_car_base, #\pll_misc] | ||
| 105 | bic \rd, \rd, #(1 << 18) | ||
| 106 | str \rd, [\r_car_base, #\pll_misc] | ||
| 107 | ldr \rd, [\r_car_base, #\pll_misc] | ||
| 108 | ldr \rd, [\r_car_base, #\pll_misc] | ||
| 109 | orr \rd, \rd, #(1 << 18) | ||
| 110 | str \rd, [\r_car_base, #\pll_misc] | ||
| 111 | .endif | ||
| 112 | .endm | ||
| 113 | |||
| 114 | .macro pll_locked, rd, r_car_base, pll_base | ||
| 115 | 1: | ||
| 116 | ldr \rd, [\r_car_base, #\pll_base] | ||
| 117 | tst \rd, #(1 << 27) | ||
| 118 | beq 1b | ||
| 119 | .endm | ||
| 120 | |||
| 121 | .macro pll_iddq_exit, rd, car, iddq, iddq_bit | ||
| 122 | ldr \rd, [\car, #\iddq] | ||
| 123 | bic \rd, \rd, #(1<<\iddq_bit) | ||
| 124 | str \rd, [\car, #\iddq] | ||
| 125 | .endm | ||
| 126 | |||
| 127 | .macro pll_iddq_entry, rd, car, iddq, iddq_bit | ||
| 128 | ldr \rd, [\car, #\iddq] | ||
| 129 | orr \rd, \rd, #(1<<\iddq_bit) | ||
| 130 | str \rd, [\car, #\iddq] | ||
| 131 | .endm | ||
| 132 | |||
| 28 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) | 133 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) |
| 29 | /* | 134 | /* |
| 30 | * tegra30_hotplug_shutdown(void) | 135 | * tegra30_hotplug_shutdown(void) |
| @@ -99,6 +204,8 @@ flow_ctrl_setting_for_lp2: | |||
| 99 | cmp r10, #TEGRA30 | 204 | cmp r10, #TEGRA30 |
| 100 | moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 | 205 | moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 |
| 101 | movne r3, #FLOW_CTRL_WAITEVENT | 206 | movne r3, #FLOW_CTRL_WAITEVENT |
| 207 | orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ | ||
| 208 | orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ | ||
| 102 | flow_ctrl_done: | 209 | flow_ctrl_done: |
| 103 | cmp r10, #TEGRA30 | 210 | cmp r10, #TEGRA30 |
| 104 | str r3, [r2] | 211 | str r3, [r2] |
| @@ -127,6 +234,41 @@ ENDPROC(tegra30_cpu_shutdown) | |||
| 127 | 234 | ||
| 128 | #ifdef CONFIG_PM_SLEEP | 235 | #ifdef CONFIG_PM_SLEEP |
| 129 | /* | 236 | /* |
| 237 | * tegra30_sleep_core_finish(unsigned long v2p) | ||
| 238 | * | ||
| 239 | * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to | ||
| 240 | * tegra30_tear_down_core in IRAM | ||
| 241 | */ | ||
| 242 | ENTRY(tegra30_sleep_core_finish) | ||
| 243 | /* Flush, disable the L1 data cache and exit SMP */ | ||
| 244 | bl tegra_disable_clean_inv_dcache | ||
| 245 | |||
| 246 | /* | ||
| 247 | * Preload all the address literals that are needed for the | ||
| 248 | * CPU power-gating process, to avoid loading from SDRAM which | ||
| 249 | * are not supported once SDRAM is put into self-refresh. | ||
| 250 | * LP0 / LP1 use physical address, since the MMU needs to be | ||
| 251 | * disabled before putting SDRAM into self-refresh to avoid | ||
| 252 | * memory access due to page table walks. | ||
| 253 | */ | ||
| 254 | mov32 r4, TEGRA_PMC_BASE | ||
| 255 | mov32 r5, TEGRA_CLK_RESET_BASE | ||
| 256 | mov32 r6, TEGRA_FLOW_CTRL_BASE | ||
| 257 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 258 | |||
| 259 | mov32 r3, tegra_shut_off_mmu | ||
| 260 | add r3, r3, r0 | ||
| 261 | |||
| 262 | mov32 r0, tegra30_tear_down_core | ||
| 263 | mov32 r1, tegra30_iram_start | ||
| 264 | sub r0, r0, r1 | ||
| 265 | mov32 r1, TEGRA_IRAM_CODE_AREA | ||
| 266 | add r0, r0, r1 | ||
| 267 | |||
| 268 | mov pc, r3 | ||
| 269 | ENDPROC(tegra30_sleep_core_finish) | ||
| 270 | |||
| 271 | /* | ||
| 130 | * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) | 272 | * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) |
| 131 | * | 273 | * |
| 132 | * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. | 274 | * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. |
| @@ -135,6 +277,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) | |||
| 135 | mov r7, lr | 277 | mov r7, lr |
| 136 | 278 | ||
| 137 | /* Flush and disable the L1 data cache */ | 279 | /* Flush and disable the L1 data cache */ |
| 280 | mov r0, #TEGRA_FLUSH_CACHE_LOUIS | ||
| 138 | bl tegra_disable_clean_inv_dcache | 281 | bl tegra_disable_clean_inv_dcache |
| 139 | 282 | ||
| 140 | /* Powergate this CPU. */ | 283 | /* Powergate this CPU. */ |
| @@ -155,6 +298,351 @@ ENTRY(tegra30_tear_down_cpu) | |||
| 155 | b tegra30_enter_sleep | 298 | b tegra30_enter_sleep |
| 156 | ENDPROC(tegra30_tear_down_cpu) | 299 | ENDPROC(tegra30_tear_down_cpu) |
| 157 | 300 | ||
| 301 | /* START OF ROUTINES COPIED TO IRAM */ | ||
| 302 | .align L1_CACHE_SHIFT | ||
| 303 | .globl tegra30_iram_start | ||
| 304 | tegra30_iram_start: | ||
| 305 | |||
| 306 | /* | ||
| 307 | * tegra30_lp1_reset | ||
| 308 | * | ||
| 309 | * reset vector for LP1 restore; copied into IRAM during suspend. | ||
| 310 | * Brings the system back up to a safe staring point (SDRAM out of | ||
| 311 | * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX, | ||
| 312 | * system clock running on the same PLL that it suspended at), and | ||
| 313 | * jumps to tegra_resume to restore virtual addressing. | ||
| 314 | * The physical address of tegra_resume expected to be stored in | ||
| 315 | * PMC_SCRATCH41. | ||
| 316 | * | ||
| 317 | * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. | ||
| 318 | */ | ||
| 319 | ENTRY(tegra30_lp1_reset) | ||
| 320 | /* | ||
| 321 | * The CPU and system bus are running at 32KHz and executing from | ||
| 322 | * IRAM when this code is executed; immediately switch to CLKM and | ||
| 323 | * enable PLLP, PLLM, PLLC, PLLA and PLLX. | ||
| 324 | */ | ||
| 325 | mov32 r0, TEGRA_CLK_RESET_BASE | ||
| 326 | |||
| 327 | mov r1, #(1 << 28) | ||
| 328 | str r1, [r0, #CLK_RESET_SCLK_BURST] | ||
| 329 | str r1, [r0, #CLK_RESET_CCLK_BURST] | ||
| 330 | mov r1, #0 | ||
| 331 | str r1, [r0, #CLK_RESET_CCLK_DIVIDER] | ||
| 332 | str r1, [r0, #CLK_RESET_SCLK_DIVIDER] | ||
| 333 | |||
| 334 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 | ||
| 335 | cmp r10, #TEGRA30 | ||
| 336 | beq _no_pll_iddq_exit | ||
| 337 | |||
| 338 | pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ | ||
| 339 | pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ | ||
| 340 | pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ | ||
| 341 | |||
| 342 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 343 | ldr r1, [r7] | ||
| 344 | add r1, r1, #2 | ||
| 345 | wait_until r1, r7, r3 | ||
| 346 | |||
| 347 | /* enable PLLM via PMC */ | ||
| 348 | mov32 r2, TEGRA_PMC_BASE | ||
| 349 | ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | ||
| 350 | orr r1, r1, #(1 << 12) | ||
| 351 | str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | ||
| 352 | |||
| 353 | pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 | ||
| 354 | pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 | ||
| 355 | pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 | ||
| 356 | |||
| 357 | b _pll_m_c_x_done | ||
| 358 | |||
| 359 | _no_pll_iddq_exit: | ||
| 360 | /* enable PLLM via PMC */ | ||
| 361 | mov32 r2, TEGRA_PMC_BASE | ||
| 362 | ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | ||
| 363 | orr r1, r1, #(1 << 12) | ||
| 364 | str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] | ||
| 365 | |||
| 366 | pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC | ||
| 367 | pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC | ||
| 368 | pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC | ||
| 369 | |||
| 370 | _pll_m_c_x_done: | ||
| 371 | pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC | ||
| 372 | pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC | ||
| 373 | |||
| 374 | pll_locked r1, r0, CLK_RESET_PLLM_BASE | ||
| 375 | pll_locked r1, r0, CLK_RESET_PLLP_BASE | ||
| 376 | pll_locked r1, r0, CLK_RESET_PLLA_BASE | ||
| 377 | pll_locked r1, r0, CLK_RESET_PLLC_BASE | ||
| 378 | pll_locked r1, r0, CLK_RESET_PLLX_BASE | ||
| 379 | |||
| 380 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 381 | ldr r1, [r7] | ||
| 382 | add r1, r1, #LOCK_DELAY | ||
| 383 | wait_until r1, r7, r3 | ||
| 384 | |||
| 385 | adr r5, tegra30_sdram_pad_save | ||
| 386 | |||
| 387 | ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT | ||
| 388 | str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] | ||
| 389 | |||
| 390 | ldr r4, [r5, #0x1C] @ restore SCLK_BURST | ||
| 391 | str r4, [r0, #CLK_RESET_SCLK_BURST] | ||
| 392 | |||
| 393 | cmp r10, #TEGRA30 | ||
| 394 | movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX | ||
| 395 | movteq r4, #:upper16:((1 << 28) | (0x8)) | ||
| 396 | movwne r4, #:lower16:((1 << 28) | (0xe)) | ||
| 397 | movtne r4, #:upper16:((1 << 28) | (0xe)) | ||
| 398 | str r4, [r0, #CLK_RESET_CCLK_BURST] | ||
| 399 | |||
| 400 | /* Restore pad power state to normal */ | ||
| 401 | ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS | ||
| 402 | mvn r1, r1 | ||
| 403 | bic r1, r1, #(1 << 31) | ||
| 404 | orr r1, r1, #(1 << 30) | ||
| 405 | str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF | ||
| 406 | |||
| 407 | cmp r10, #TEGRA30 | ||
| 408 | movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base | ||
| 409 | movteq r0, #:upper16:TEGRA_EMC_BASE | ||
| 410 | movwne r0, #:lower16:TEGRA_EMC0_BASE | ||
| 411 | movtne r0, #:upper16:TEGRA_EMC0_BASE | ||
| 412 | |||
| 413 | exit_self_refresh: | ||
| 414 | ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL | ||
| 415 | str r1, [r0, #EMC_XM2VTTGENPADCTRL] | ||
| 416 | ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2 | ||
| 417 | str r1, [r0, #EMC_XM2VTTGENPADCTRL2] | ||
| 418 | ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL | ||
| 419 | str r1, [r0, #EMC_AUTO_CAL_INTERVAL] | ||
| 420 | |||
| 421 | /* Relock DLL */ | ||
| 422 | ldr r1, [r0, #EMC_CFG_DIG_DLL] | ||
| 423 | orr r1, r1, #(1 << 30) @ set DLL_RESET | ||
| 424 | str r1, [r0, #EMC_CFG_DIG_DLL] | ||
| 425 | |||
| 426 | emc_timing_update r1, r0 | ||
| 427 | |||
| 428 | cmp r10, #TEGRA114 | ||
| 429 | movweq r1, #:lower16:TEGRA_EMC1_BASE | ||
| 430 | movteq r1, #:upper16:TEGRA_EMC1_BASE | ||
| 431 | cmpeq r0, r1 | ||
| 432 | |||
| 433 | ldr r1, [r0, #EMC_AUTO_CAL_CONFIG] | ||
| 434 | orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE | ||
| 435 | orreq r1, r1, #(1 << 27) @ set slave mode for channel 1 | ||
| 436 | str r1, [r0, #EMC_AUTO_CAL_CONFIG] | ||
| 437 | |||
| 438 | emc_wait_auto_cal_onetime: | ||
| 439 | ldr r1, [r0, #EMC_AUTO_CAL_STATUS] | ||
| 440 | tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared | ||
| 441 | bne emc_wait_auto_cal_onetime | ||
| 442 | |||
| 443 | ldr r1, [r0, #EMC_CFG] | ||
| 444 | bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD | ||
| 445 | str r1, [r0, #EMC_CFG] | ||
| 446 | |||
| 447 | mov r1, #0 | ||
| 448 | str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh | ||
| 449 | mov r1, #1 | ||
| 450 | cmp r10, #TEGRA30 | ||
| 451 | streq r1, [r0, #EMC_NOP] | ||
| 452 | streq r1, [r0, #EMC_NOP] | ||
| 453 | streq r1, [r0, #EMC_REFRESH] | ||
| 454 | |||
| 455 | emc_device_mask r1, r0 | ||
| 456 | |||
| 457 | exit_selfrefresh_loop: | ||
| 458 | ldr r2, [r0, #EMC_EMC_STATUS] | ||
| 459 | ands r2, r2, r1 | ||
| 460 | bne exit_selfrefresh_loop | ||
| 461 | |||
| 462 | lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1 | ||
| 463 | |||
| 464 | mov32 r7, TEGRA_TMRUS_BASE | ||
| 465 | ldr r2, [r0, #EMC_FBIO_CFG5] | ||
| 466 | |||
| 467 | and r2, r2, #3 @ check DRAM_TYPE | ||
| 468 | cmp r2, #2 | ||
| 469 | beq emc_lpddr2 | ||
| 470 | |||
| 471 | /* Issue a ZQ_CAL for dev0 - DDR3 */ | ||
| 472 | mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1 | ||
| 473 | str r2, [r0, #EMC_ZQ_CAL] | ||
| 474 | ldr r2, [r7] | ||
| 475 | add r2, r2, #10 | ||
| 476 | wait_until r2, r7, r3 | ||
| 477 | |||
| 478 | tst r1, #2 | ||
| 479 | beq zcal_done | ||
| 480 | |||
| 481 | /* Issue a ZQ_CAL for dev1 - DDR3 */ | ||
| 482 | mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1 | ||
| 483 | str r2, [r0, #EMC_ZQ_CAL] | ||
| 484 | ldr r2, [r7] | ||
| 485 | add r2, r2, #10 | ||
| 486 | wait_until r2, r7, r3 | ||
| 487 | b zcal_done | ||
| 488 | |||
| 489 | emc_lpddr2: | ||
| 490 | /* Issue a ZQ_CAL for dev0 - LPDDR2 */ | ||
| 491 | mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB | ||
| 492 | str r2, [r0, #EMC_MRW] | ||
| 493 | ldr r2, [r7] | ||
| 494 | add r2, r2, #1 | ||
| 495 | wait_until r2, r7, r3 | ||
| 496 | |||
| 497 | tst r1, #2 | ||
| 498 | beq zcal_done | ||
| 499 | |||
| 500 | /* Issue a ZQ_CAL for dev0 - LPDDR2 */ | ||
| 501 | mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB | ||
| 502 | str r2, [r0, #EMC_MRW] | ||
| 503 | ldr r2, [r7] | ||
| 504 | add r2, r2, #1 | ||
| 505 | wait_until r2, r7, r3 | ||
| 506 | |||
| 507 | zcal_done: | ||
| 508 | mov r1, #0 @ unstall all transactions | ||
| 509 | str r1, [r0, #EMC_REQ_CTRL] | ||
| 510 | ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL | ||
| 511 | str r1, [r0, #EMC_ZCAL_INTERVAL] | ||
| 512 | ldr r1, [r5, #0x0] @ restore EMC_CFG | ||
| 513 | str r1, [r0, #EMC_CFG] | ||
| 514 | |||
| 515 | /* Tegra114 had dual EMC channel, now config the other one */ | ||
| 516 | cmp r10, #TEGRA114 | ||
| 517 | bne __no_dual_emc_chanl | ||
| 518 | mov32 r1, TEGRA_EMC1_BASE | ||
| 519 | cmp r0, r1 | ||
| 520 | movne r0, r1 | ||
| 521 | addne r5, r5, #0x20 | ||
| 522 | bne exit_self_refresh | ||
| 523 | __no_dual_emc_chanl: | ||
| 524 | |||
| 525 | mov32 r0, TEGRA_PMC_BASE | ||
| 526 | ldr r0, [r0, #PMC_SCRATCH41] | ||
| 527 | mov pc, r0 @ jump to tegra_resume | ||
| 528 | ENDPROC(tegra30_lp1_reset) | ||
| 529 | |||
| 530 | .align L1_CACHE_SHIFT | ||
| 531 | tegra30_sdram_pad_address: | ||
| 532 | .word TEGRA_EMC_BASE + EMC_CFG @0x0 | ||
| 533 | .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 | ||
| 534 | .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | ||
| 535 | .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc | ||
| 536 | .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | ||
| 537 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | ||
| 538 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | ||
| 539 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | ||
| 540 | |||
| 541 | tegra114_sdram_pad_address: | ||
| 542 | .word TEGRA_EMC0_BASE + EMC_CFG @0x0 | ||
| 543 | .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4 | ||
| 544 | .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | ||
| 545 | .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc | ||
| 546 | .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | ||
| 547 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | ||
| 548 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | ||
| 549 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | ||
| 550 | .word TEGRA_EMC1_BASE + EMC_CFG @0x20 | ||
| 551 | .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 | ||
| 552 | .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 | ||
| 553 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c | ||
| 554 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 | ||
| 555 | |||
| 556 | tegra30_sdram_pad_size: | ||
| 557 | .word tegra114_sdram_pad_address - tegra30_sdram_pad_address | ||
| 558 | |||
| 559 | tegra114_sdram_pad_size: | ||
| 560 | .word tegra30_sdram_pad_size - tegra114_sdram_pad_address | ||
| 561 | |||
| 562 | .type tegra30_sdram_pad_save, %object | ||
| 563 | tegra30_sdram_pad_save: | ||
| 564 | .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4 | ||
| 565 | .long 0 | ||
| 566 | .endr | ||
| 567 | |||
| 568 | /* | ||
| 569 | * tegra30_tear_down_core | ||
| 570 | * | ||
| 571 | * copied into and executed from IRAM | ||
| 572 | * puts memory in self-refresh for LP0 and LP1 | ||
| 573 | */ | ||
| 574 | tegra30_tear_down_core: | ||
| 575 | bl tegra30_sdram_self_refresh | ||
| 576 | bl tegra30_switch_cpu_to_clk32k | ||
| 577 | b tegra30_enter_sleep | ||
| 578 | |||
| 579 | /* | ||
| 580 | * tegra30_switch_cpu_to_clk32k | ||
| 581 | * | ||
| 582 | * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK | ||
| 583 | * to the 32KHz clock. | ||
| 584 | * r4 = TEGRA_PMC_BASE | ||
| 585 | * r5 = TEGRA_CLK_RESET_BASE | ||
| 586 | * r6 = TEGRA_FLOW_CTRL_BASE | ||
| 587 | * r7 = TEGRA_TMRUS_BASE | ||
| 588 | * r10= SoC ID | ||
| 589 | */ | ||
| 590 | tegra30_switch_cpu_to_clk32k: | ||
| 591 | /* | ||
| 592 | * start by jumping to CLKM to safely disable PLLs, then jump to | ||
| 593 | * CLKS. | ||
| 594 | */ | ||
| 595 | mov r0, #(1 << 28) | ||
| 596 | str r0, [r5, #CLK_RESET_SCLK_BURST] | ||
| 597 | /* 2uS delay delay between changing SCLK and CCLK */ | ||
| 598 | ldr r1, [r7] | ||
| 599 | add r1, r1, #2 | ||
| 600 | wait_until r1, r7, r9 | ||
| 601 | str r0, [r5, #CLK_RESET_CCLK_BURST] | ||
| 602 | mov r0, #0 | ||
| 603 | str r0, [r5, #CLK_RESET_CCLK_DIVIDER] | ||
| 604 | str r0, [r5, #CLK_RESET_SCLK_DIVIDER] | ||
| 605 | |||
| 606 | /* switch the clock source of mselect to be CLK_M */ | ||
| 607 | ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] | ||
| 608 | orr r0, r0, #MSELECT_CLKM | ||
| 609 | str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] | ||
| 610 | |||
| 611 | /* 2uS delay delay between changing SCLK and disabling PLLs */ | ||
| 612 | ldr r1, [r7] | ||
| 613 | add r1, r1, #2 | ||
| 614 | wait_until r1, r7, r9 | ||
| 615 | |||
| 616 | /* disable PLLM via PMC in LP1 */ | ||
| 617 | ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] | ||
| 618 | bic r0, r0, #(1 << 12) | ||
| 619 | str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] | ||
| 620 | |||
| 621 | /* disable PLLP, PLLA, PLLC and PLLX */ | ||
| 622 | ldr r0, [r5, #CLK_RESET_PLLP_BASE] | ||
| 623 | bic r0, r0, #(1 << 30) | ||
| 624 | str r0, [r5, #CLK_RESET_PLLP_BASE] | ||
| 625 | ldr r0, [r5, #CLK_RESET_PLLA_BASE] | ||
| 626 | bic r0, r0, #(1 << 30) | ||
| 627 | str r0, [r5, #CLK_RESET_PLLA_BASE] | ||
| 628 | ldr r0, [r5, #CLK_RESET_PLLC_BASE] | ||
| 629 | bic r0, r0, #(1 << 30) | ||
| 630 | str r0, [r5, #CLK_RESET_PLLC_BASE] | ||
| 631 | ldr r0, [r5, #CLK_RESET_PLLX_BASE] | ||
| 632 | bic r0, r0, #(1 << 30) | ||
| 633 | str r0, [r5, #CLK_RESET_PLLX_BASE] | ||
| 634 | |||
| 635 | cmp r10, #TEGRA30 | ||
| 636 | beq _no_pll_in_iddq | ||
| 637 | pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ | ||
| 638 | _no_pll_in_iddq: | ||
| 639 | |||
| 640 | /* switch to CLKS */ | ||
| 641 | mov r0, #0 /* brust policy = 32KHz */ | ||
| 642 | str r0, [r5, #CLK_RESET_SCLK_BURST] | ||
| 643 | |||
| 644 | mov pc, lr | ||
| 645 | |||
| 158 | /* | 646 | /* |
| 159 | * tegra30_enter_sleep | 647 | * tegra30_enter_sleep |
| 160 | * | 648 | * |
| @@ -172,8 +660,12 @@ tegra30_enter_sleep: | |||
| 172 | orr r0, r0, #FLOW_CTRL_CSR_ENABLE | 660 | orr r0, r0, #FLOW_CTRL_CSR_ENABLE |
| 173 | str r0, [r6, r2] | 661 | str r0, [r6, r2] |
| 174 | 662 | ||
| 663 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 | ||
| 664 | cmp r10, #TEGRA30 | ||
| 175 | mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT | 665 | mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT |
| 176 | orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ | 666 | orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ |
| 667 | orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ | ||
| 668 | |||
| 177 | cpu_to_halt_reg r2, r1 | 669 | cpu_to_halt_reg r2, r1 |
| 178 | str r0, [r6, r2] | 670 | str r0, [r6, r2] |
| 179 | dsb | 671 | dsb |
| @@ -187,4 +679,126 @@ halted: | |||
| 187 | /* !!!FIXME!!! Implement halt failure handler */ | 679 | /* !!!FIXME!!! Implement halt failure handler */ |
| 188 | b halted | 680 | b halted |
| 189 | 681 | ||
| 682 | /* | ||
| 683 | * tegra30_sdram_self_refresh | ||
| 684 | * | ||
| 685 | * called with MMU off and caches disabled | ||
| 686 | * must be executed from IRAM | ||
| 687 | * r4 = TEGRA_PMC_BASE | ||
| 688 | * r5 = TEGRA_CLK_RESET_BASE | ||
| 689 | * r6 = TEGRA_FLOW_CTRL_BASE | ||
| 690 | * r7 = TEGRA_TMRUS_BASE | ||
| 691 | * r10= SoC ID | ||
| 692 | */ | ||
| 693 | tegra30_sdram_self_refresh: | ||
| 694 | |||
| 695 | adr r8, tegra30_sdram_pad_save | ||
| 696 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 | ||
| 697 | cmp r10, #TEGRA30 | ||
| 698 | adreq r2, tegra30_sdram_pad_address | ||
| 699 | ldreq r3, tegra30_sdram_pad_size | ||
| 700 | adrne r2, tegra114_sdram_pad_address | ||
| 701 | ldrne r3, tegra114_sdram_pad_size | ||
| 702 | mov r9, #0 | ||
| 703 | |||
| 704 | padsave: | ||
| 705 | ldr r0, [r2, r9] @ r0 is the addr in the pad_address | ||
| 706 | |||
| 707 | ldr r1, [r0] | ||
| 708 | str r1, [r8, r9] @ save the content of the addr | ||
| 709 | |||
| 710 | add r9, r9, #4 | ||
| 711 | cmp r3, r9 | ||
| 712 | bne padsave | ||
| 713 | padsave_done: | ||
| 714 | |||
| 715 | dsb | ||
| 716 | |||
| 717 | cmp r10, #TEGRA30 | ||
| 718 | ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr | ||
| 719 | ldrne r0, =TEGRA_EMC0_BASE | ||
| 720 | |||
| 721 | enter_self_refresh: | ||
| 722 | cmp r10, #TEGRA30 | ||
| 723 | mov r1, #0 | ||
| 724 | str r1, [r0, #EMC_ZCAL_INTERVAL] | ||
| 725 | str r1, [r0, #EMC_AUTO_CAL_INTERVAL] | ||
| 726 | ldr r1, [r0, #EMC_CFG] | ||
| 727 | bic r1, r1, #(1 << 28) | ||
| 728 | bicne r1, r1, #(1 << 29) | ||
| 729 | str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF | ||
| 730 | |||
| 731 | emc_timing_update r1, r0 | ||
| 732 | |||
| 733 | ldr r1, [r7] | ||
| 734 | add r1, r1, #5 | ||
| 735 | wait_until r1, r7, r2 | ||
| 736 | |||
| 737 | emc_wait_auto_cal: | ||
| 738 | ldr r1, [r0, #EMC_AUTO_CAL_STATUS] | ||
| 739 | tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared | ||
| 740 | bne emc_wait_auto_cal | ||
| 741 | |||
| 742 | mov r1, #3 | ||
| 743 | str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests | ||
| 744 | |||
| 745 | emcidle: | ||
| 746 | ldr r1, [r0, #EMC_EMC_STATUS] | ||
| 747 | tst r1, #4 | ||
| 748 | beq emcidle | ||
| 749 | |||
| 750 | mov r1, #1 | ||
| 751 | str r1, [r0, #EMC_SELF_REF] | ||
| 752 | |||
| 753 | emc_device_mask r1, r0 | ||
| 754 | |||
| 755 | emcself: | ||
| 756 | ldr r2, [r0, #EMC_EMC_STATUS] | ||
| 757 | and r2, r2, r1 | ||
| 758 | cmp r2, r1 | ||
| 759 | bne emcself @ loop until DDR in self-refresh | ||
| 760 | |||
| 761 | /* Put VTTGEN in the lowest power mode */ | ||
| 762 | ldr r1, [r0, #EMC_XM2VTTGENPADCTRL] | ||
| 763 | mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN | ||
| 764 | and r1, r1, r2 | ||
| 765 | str r1, [r0, #EMC_XM2VTTGENPADCTRL] | ||
| 766 | ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2] | ||
| 767 | cmp r10, #TEGRA30 | ||
| 768 | orreq r1, r1, #7 @ set E_NO_VTTGEN | ||
| 769 | orrne r1, r1, #0x3f | ||
| 770 | str r1, [r0, #EMC_XM2VTTGENPADCTRL2] | ||
| 771 | |||
| 772 | emc_timing_update r1, r0 | ||
| 773 | |||
| 774 | /* Tegra114 had dual EMC channel, now config the other one */ | ||
| 775 | cmp r10, #TEGRA114 | ||
| 776 | bne no_dual_emc_chanl | ||
| 777 | mov32 r1, TEGRA_EMC1_BASE | ||
| 778 | cmp r0, r1 | ||
| 779 | movne r0, r1 | ||
| 780 | bne enter_self_refresh | ||
| 781 | no_dual_emc_chanl: | ||
| 782 | |||
| 783 | ldr r1, [r4, #PMC_CTRL] | ||
| 784 | tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 | ||
| 785 | bne pmc_io_dpd_skip | ||
| 786 | /* | ||
| 787 | * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK | ||
| 788 | * and COMP in the lowest power mode when LP1. | ||
| 789 | */ | ||
| 790 | mov32 r1, 0x8EC00000 | ||
| 791 | str r1, [r4, #PMC_IO_DPD_REQ] | ||
| 792 | pmc_io_dpd_skip: | ||
| 793 | |||
| 794 | dsb | ||
| 795 | |||
| 796 | mov pc, lr | ||
| 797 | |||
| 798 | .ltorg | ||
| 799 | /* dummy symbol for end of IRAM */ | ||
| 800 | .align L1_CACHE_SHIFT | ||
| 801 | .global tegra30_iram_end | ||
| 802 | tegra30_iram_end: | ||
| 803 | b . | ||
| 190 | #endif | 804 | #endif |
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 9daaef26b0f6..8d06213fbc47 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S | |||
| @@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache) | |||
| 56 | isb | 56 | isb |
| 57 | 57 | ||
| 58 | /* Flush the D-cache */ | 58 | /* Flush the D-cache */ |
| 59 | bl v7_flush_dcache_louis | 59 | cmp r0, #TEGRA_FLUSH_CACHE_ALL |
| 60 | blne v7_flush_dcache_louis | ||
| 61 | bleq v7_flush_dcache_all | ||
| 60 | 62 | ||
| 61 | /* Trun off coherency */ | 63 | /* Trun off coherency */ |
| 62 | exit_smp r4, r5 | 64 | exit_smp r4, r5 |
| @@ -67,15 +69,40 @@ ENDPROC(tegra_disable_clean_inv_dcache) | |||
| 67 | 69 | ||
| 68 | #ifdef CONFIG_PM_SLEEP | 70 | #ifdef CONFIG_PM_SLEEP |
| 69 | /* | 71 | /* |
| 72 | * tegra_init_l2_for_a15 | ||
| 73 | * | ||
| 74 | * set up the correct L2 cache data RAM latency | ||
| 75 | */ | ||
| 76 | ENTRY(tegra_init_l2_for_a15) | ||
| 77 | mrc p15, 0, r0, c0, c0, 5 | ||
| 78 | ubfx r0, r0, #8, #4 | ||
| 79 | tst r0, #1 @ only need for cluster 0 | ||
| 80 | bne _exit_init_l2_a15 | ||
| 81 | |||
| 82 | mrc p15, 0x1, r0, c9, c0, 2 | ||
| 83 | and r0, r0, #7 | ||
| 84 | cmp r0, #2 | ||
| 85 | bicne r0, r0, #7 | ||
| 86 | orrne r0, r0, #2 | ||
| 87 | mcrne p15, 0x1, r0, c9, c0, 2 | ||
| 88 | _exit_init_l2_a15: | ||
| 89 | |||
| 90 | mov pc, lr | ||
| 91 | ENDPROC(tegra_init_l2_for_a15) | ||
| 92 | |||
| 93 | /* | ||
| 70 | * tegra_sleep_cpu_finish(unsigned long v2p) | 94 | * tegra_sleep_cpu_finish(unsigned long v2p) |
| 71 | * | 95 | * |
| 72 | * enters suspend in LP2 by turning off the mmu and jumping to | 96 | * enters suspend in LP2 by turning off the mmu and jumping to |
| 73 | * tegra?_tear_down_cpu | 97 | * tegra?_tear_down_cpu |
| 74 | */ | 98 | */ |
| 75 | ENTRY(tegra_sleep_cpu_finish) | 99 | ENTRY(tegra_sleep_cpu_finish) |
| 100 | mov r4, r0 | ||
| 76 | /* Flush and disable the L1 data cache */ | 101 | /* Flush and disable the L1 data cache */ |
| 102 | mov r0, #TEGRA_FLUSH_CACHE_ALL | ||
| 77 | bl tegra_disable_clean_inv_dcache | 103 | bl tegra_disable_clean_inv_dcache |
| 78 | 104 | ||
| 105 | mov r0, r4 | ||
| 79 | mov32 r6, tegra_tear_down_cpu | 106 | mov32 r6, tegra_tear_down_cpu |
| 80 | ldr r1, [r6] | 107 | ldr r1, [r6] |
| 81 | add r1, r1, r0 | 108 | add r1, r1, r0 |
| @@ -107,10 +134,10 @@ ENTRY(tegra_shut_off_mmu) | |||
| 107 | #ifdef CONFIG_CACHE_L2X0 | 134 | #ifdef CONFIG_CACHE_L2X0 |
| 108 | /* Disable L2 cache */ | 135 | /* Disable L2 cache */ |
| 109 | check_cpu_part_num 0xc09, r9, r10 | 136 | check_cpu_part_num 0xc09, r9, r10 |
| 110 | movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) | 137 | movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) |
| 111 | movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) | 138 | movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) |
| 112 | moveq r5, #0 | 139 | moveq r3, #0 |
| 113 | streq r5, [r4, #L2X0_CTRL] | 140 | streq r3, [r2, #L2X0_CTRL] |
| 114 | #endif | 141 | #endif |
| 115 | mov pc, r0 | 142 | mov pc, r0 |
| 116 | ENDPROC(tegra_shut_off_mmu) | 143 | ENDPROC(tegra_shut_off_mmu) |
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 98b7da698f2b..a4edbb3abd3d 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
| @@ -41,7 +41,19 @@ | |||
| 41 | #define CPU_NOT_RESETTABLE 0 | 41 | #define CPU_NOT_RESETTABLE 0 |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */ | ||
| 45 | #define TEGRA_FLUSH_CACHE_LOUIS 0 | ||
| 46 | #define TEGRA_FLUSH_CACHE_ALL 1 | ||
| 47 | |||
| 44 | #ifdef __ASSEMBLY__ | 48 | #ifdef __ASSEMBLY__ |
| 49 | /* waits until the microsecond counter (base) is > rn */ | ||
| 50 | .macro wait_until, rn, base, tmp | ||
| 51 | add \rn, \rn, #1 | ||
| 52 | 1001: ldr \tmp, [\base] | ||
| 53 | cmp \tmp, \rn | ||
| 54 | bmi 1001b | ||
| 55 | .endm | ||
| 56 | |||
| 45 | /* returns the offset of the flow controller halt register for a cpu */ | 57 | /* returns the offset of the flow controller halt register for a cpu */ |
| 46 | .macro cpu_to_halt_reg rd, rcpu | 58 | .macro cpu_to_halt_reg rd, rcpu |
| 47 | cmp \rcpu, #0 | 59 | cmp \rcpu, #0 |
| @@ -144,7 +156,7 @@ void tegra_pen_lock(void); | |||
| 144 | void tegra_pen_unlock(void); | 156 | void tegra_pen_unlock(void); |
| 145 | void tegra_resume(void); | 157 | void tegra_resume(void); |
| 146 | int tegra_sleep_cpu_finish(unsigned long); | 158 | int tegra_sleep_cpu_finish(unsigned long); |
| 147 | void tegra_disable_clean_inv_dcache(void); | 159 | void tegra_disable_clean_inv_dcache(u32 flag); |
| 148 | 160 | ||
| 149 | #ifdef CONFIG_HOTPLUG_CPU | 161 | #ifdef CONFIG_HOTPLUG_CPU |
| 150 | void tegra20_hotplug_shutdown(void); | 162 | void tegra20_hotplug_shutdown(void); |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index fc97cfd52769..5b8605547a09 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
| @@ -80,28 +80,6 @@ out: | |||
| 80 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); | 80 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); |
| 81 | } | 81 | } |
| 82 | 82 | ||
| 83 | static void __init trimslice_init(void) | ||
| 84 | { | ||
| 85 | #ifdef CONFIG_TEGRA_PCI | ||
| 86 | int ret; | ||
| 87 | |||
| 88 | ret = tegra_pcie_init(true, true); | ||
| 89 | if (ret) | ||
| 90 | pr_err("tegra_pci_init() failed: %d\n", ret); | ||
| 91 | #endif | ||
| 92 | } | ||
| 93 | |||
| 94 | static void __init harmony_init(void) | ||
| 95 | { | ||
| 96 | #ifdef CONFIG_TEGRA_PCI | ||
| 97 | int ret; | ||
| 98 | |||
| 99 | ret = harmony_pcie_init(); | ||
| 100 | if (ret) | ||
| 101 | pr_err("harmony_pcie_init() failed: %d\n", ret); | ||
| 102 | #endif | ||
| 103 | } | ||
| 104 | |||
| 105 | static void __init paz00_init(void) | 83 | static void __init paz00_init(void) |
| 106 | { | 84 | { |
| 107 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 85 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
| @@ -112,8 +90,6 @@ static struct { | |||
| 112 | char *machine; | 90 | char *machine; |
| 113 | void (*init)(void); | 91 | void (*init)(void); |
| 114 | } board_init_funcs[] = { | 92 | } board_init_funcs[] = { |
| 115 | { "compulab,trimslice", trimslice_init }, | ||
| 116 | { "nvidia,harmony", harmony_init }, | ||
| 117 | { "compal,paz00", paz00_init }, | 93 | { "compal,paz00", paz00_init }, |
| 118 | }; | 94 | }; |
| 119 | 95 | ||
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index df5d27a532e9..4e7ab3a0dd60 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
| @@ -42,7 +42,6 @@ | |||
| 42 | #include <linux/platform_data/dma-ste-dma40.h> | 42 | #include <linux/platform_data/dma-ste-dma40.h> |
| 43 | 43 | ||
| 44 | #include <asm/mach-types.h> | 44 | #include <asm/mach-types.h> |
| 45 | #include <asm/mach/arch.h> | ||
| 46 | 45 | ||
| 47 | #include "setup.h" | 46 | #include "setup.h" |
| 48 | #include "devices.h" | 47 | #include "devices.h" |
| @@ -686,6 +685,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform") | |||
| 686 | .init_time = ux500_timer_init, | 685 | .init_time = ux500_timer_init, |
| 687 | .init_machine = mop500_init_machine, | 686 | .init_machine = mop500_init_machine, |
| 688 | .init_late = ux500_init_late, | 687 | .init_late = ux500_init_late, |
| 688 | .restart = ux500_restart, | ||
| 689 | MACHINE_END | 689 | MACHINE_END |
| 690 | 690 | ||
| 691 | MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") | 691 | MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") |
| @@ -695,6 +695,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") | |||
| 695 | .init_time = ux500_timer_init, | 695 | .init_time = ux500_timer_init, |
| 696 | .init_machine = mop500_init_machine, | 696 | .init_machine = mop500_init_machine, |
| 697 | .init_late = ux500_init_late, | 697 | .init_late = ux500_init_late, |
| 698 | .restart = ux500_restart, | ||
| 698 | MACHINE_END | 699 | MACHINE_END |
| 699 | 700 | ||
| 700 | MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") | 701 | MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") |
| @@ -705,6 +706,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") | |||
| 705 | .init_time = ux500_timer_init, | 706 | .init_time = ux500_timer_init, |
| 706 | .init_machine = hrefv60_init_machine, | 707 | .init_machine = hrefv60_init_machine, |
| 707 | .init_late = ux500_init_late, | 708 | .init_late = ux500_init_late, |
| 709 | .restart = ux500_restart, | ||
| 708 | MACHINE_END | 710 | MACHINE_END |
| 709 | 711 | ||
| 710 | MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") | 712 | MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") |
| @@ -716,4 +718,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") | |||
| 716 | .init_time = ux500_timer_init, | 718 | .init_time = ux500_timer_init, |
| 717 | .init_machine = snowball_init_machine, | 719 | .init_machine = snowball_init_machine, |
| 718 | .init_late = NULL, | 720 | .init_late = NULL, |
| 721 | .restart = ux500_restart, | ||
| 719 | MACHINE_END | 722 | MACHINE_END |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 2061b6a2a766..bfaf95d22cbb 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/pmu.h> | 27 | #include <asm/pmu.h> |
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/arch.h> | ||
| 30 | 29 | ||
| 31 | #include "setup.h" | 30 | #include "setup.h" |
| 32 | #include "devices.h" | 31 | #include "devices.h" |
| @@ -325,6 +324,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") | |||
| 325 | .init_machine = u8500_init_machine, | 324 | .init_machine = u8500_init_machine, |
| 326 | .init_late = NULL, | 325 | .init_late = NULL, |
| 327 | .dt_compat = stericsson_dt_platform_compat, | 326 | .dt_compat = stericsson_dt_platform_compat, |
| 327 | .restart = ux500_restart, | ||
| 328 | MACHINE_END | 328 | MACHINE_END |
| 329 | 329 | ||
| 330 | #endif | 330 | #endif |
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e6fb0239151b..5d7eebcabc63 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
| @@ -31,6 +31,14 @@ | |||
| 31 | #include "db8500-regs.h" | 31 | #include "db8500-regs.h" |
| 32 | #include "id.h" | 32 | #include "id.h" |
| 33 | 33 | ||
| 34 | void ux500_restart(enum reboot_mode mode, const char *cmd) | ||
| 35 | { | ||
| 36 | local_irq_disable(); | ||
| 37 | local_fiq_disable(); | ||
| 38 | |||
| 39 | prcmu_system_reset(0); | ||
| 40 | } | ||
| 41 | |||
| 34 | /* | 42 | /* |
| 35 | * FIXME: Should we set up the GPIO domain here? | 43 | * FIXME: Should we set up the GPIO domain here? |
| 36 | * | 44 | * |
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 516a6f57d159..bc316062e0c2 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c | |||
| @@ -49,6 +49,7 @@ struct stedma40_platform_data dma40_plat_data = { | |||
| 49 | struct platform_device u8500_dma40_device = { | 49 | struct platform_device u8500_dma40_device = { |
| 50 | .dev = { | 50 | .dev = { |
| 51 | .platform_data = &dma40_plat_data, | 51 | .platform_data = &dma40_plat_data, |
| 52 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 52 | }, | 53 | }, |
| 53 | .name = "dma40", | 54 | .name = "dma40", |
| 54 | .id = 0, | 55 | .id = 0, |
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S index 08da5589bcd8..9cdea049485d 100644 --- a/arch/arm/mach-ux500/headsmp.S +++ b/arch/arm/mach-ux500/headsmp.S | |||
| @@ -11,8 +11,6 @@ | |||
| 11 | #include <linux/linkage.h> | 11 | #include <linux/linkage.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | 13 | ||
| 14 | __INIT | ||
| 15 | |||
| 16 | /* | 14 | /* |
| 17 | * U8500 specific entry point for secondary CPUs. | 15 | * U8500 specific entry point for secondary CPUs. |
| 18 | */ | 16 | */ |
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index cad3ca86c540..656324aad18e 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h | |||
| @@ -11,10 +11,13 @@ | |||
| 11 | #ifndef __ASM_ARCH_SETUP_H | 11 | #ifndef __ASM_ARCH_SETUP_H |
| 12 | #define __ASM_ARCH_SETUP_H | 12 | #define __ASM_ARCH_SETUP_H |
| 13 | 13 | ||
| 14 | #include <asm/mach/arch.h> | ||
| 14 | #include <asm/mach/time.h> | 15 | #include <asm/mach/time.h> |
| 15 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 16 | #include <linux/mfd/abx500/ab8500.h> | 17 | #include <linux/mfd/abx500/ab8500.h> |
| 17 | 18 | ||
| 19 | void ux500_restart(enum reboot_mode mode, const char *cmd); | ||
| 20 | |||
| 18 | void __init ux500_map_io(void); | 21 | void __init ux500_map_io(void); |
| 19 | extern void __init u8500_map_io(void); | 22 | extern void __init u8500_map_io(void); |
| 20 | 23 | ||
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 83c8677bb181..365795447804 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig | |||
| @@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB | |||
| 66 | This is needed to provide CPU and cluster power management | 66 | This is needed to provide CPU and cluster power management |
| 67 | on RTSM implementing big.LITTLE. | 67 | on RTSM implementing big.LITTLE. |
| 68 | 68 | ||
| 69 | config ARCH_VEXPRESS_TC2_PM | ||
| 70 | bool "Versatile Express TC2 power management" | ||
| 71 | depends on MCPM | ||
| 72 | select ARM_CCI | ||
| 73 | help | ||
| 74 | Support for CPU and cluster power management on Versatile Express | ||
| 75 | with a TC2 (A15x2 A7x3) big.LITTLE core tile. | ||
| 76 | |||
| 69 | endmenu | 77 | endmenu |
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 48ba89a8149f..36ea8247123a 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile | |||
| @@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ | |||
| 7 | obj-y := v2m.o | 7 | obj-y := v2m.o |
| 8 | obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o | 8 | obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o |
| 9 | obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o | 9 | obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o |
| 10 | obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o | ||
| 10 | obj-$(CONFIG_SMP) += platsmp.o | 11 | obj-$(CONFIG_SMP) += platsmp.o |
| 11 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 12 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 16d57a8a9d5a..3a6384c6c435 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c | |||
| @@ -136,14 +136,35 @@ static void dcscb_power_down(void) | |||
| 136 | /* | 136 | /* |
| 137 | * Flush all cache levels for this cluster. | 137 | * Flush all cache levels for this cluster. |
| 138 | * | 138 | * |
| 139 | * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need | 139 | * To do so we do: |
| 140 | * a preliminary flush here for those CPUs. At least, that's | 140 | * - Clear the SCTLR.C bit to prevent further cache allocations |
| 141 | * the theory -- without the extra flush, Linux explodes on | 141 | * - Flush the whole cache |
| 142 | * RTSM (to be investigated). | 142 | * - Clear the ACTLR "SMP" bit to disable local coherency |
| 143 | * | ||
| 144 | * Let's do it in the safest possible way i.e. with | ||
| 145 | * no memory access within the following sequence | ||
| 146 | * including to the stack. | ||
| 147 | * | ||
| 148 | * Note: fp is preserved to the stack explicitly prior doing | ||
| 149 | * this since adding it to the clobber list is incompatible | ||
| 150 | * with having CONFIG_FRAME_POINTER=y. | ||
| 143 | */ | 151 | */ |
| 144 | flush_cache_all(); | 152 | asm volatile( |
| 145 | set_cr(get_cr() & ~CR_C); | 153 | "str fp, [sp, #-4]! \n\t" |
| 146 | flush_cache_all(); | 154 | "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" |
| 155 | "bic r0, r0, #"__stringify(CR_C)" \n\t" | ||
| 156 | "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" | ||
| 157 | "isb \n\t" | ||
| 158 | "bl v7_flush_dcache_all \n\t" | ||
| 159 | "clrex \n\t" | ||
| 160 | "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" | ||
| 161 | "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" | ||
| 162 | "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" | ||
| 163 | "isb \n\t" | ||
| 164 | "dsb \n\t" | ||
| 165 | "ldr fp, [sp], #4" | ||
| 166 | : : : "r0","r1","r2","r3","r4","r5","r6","r7", | ||
| 167 | "r9","r10","lr","memory"); | ||
| 147 | 168 | ||
| 148 | /* | 169 | /* |
| 149 | * This is a harmless no-op. On platforms with a real | 170 | * This is a harmless no-op. On platforms with a real |
| @@ -152,9 +173,6 @@ static void dcscb_power_down(void) | |||
| 152 | */ | 173 | */ |
| 153 | outer_flush_all(); | 174 | outer_flush_all(); |
| 154 | 175 | ||
| 155 | /* Disable local coherency by clearing the ACTLR "SMP" bit: */ | ||
| 156 | set_auxcr(get_auxcr() & ~(1 << 6)); | ||
| 157 | |||
| 158 | /* | 176 | /* |
| 159 | * Disable cluster-level coherency by masking | 177 | * Disable cluster-level coherency by masking |
| 160 | * incoming snoops and DVM messages: | 178 | * incoming snoops and DVM messages: |
| @@ -167,18 +185,24 @@ static void dcscb_power_down(void) | |||
| 167 | 185 | ||
| 168 | /* | 186 | /* |
| 169 | * Flush the local CPU cache. | 187 | * Flush the local CPU cache. |
| 170 | * | 188 | * Let's do it in the safest possible way as above. |
| 171 | * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need | ||
| 172 | * a preliminary flush here for those CPUs. At least, that's | ||
| 173 | * the theory -- without the extra flush, Linux explodes on | ||
| 174 | * RTSM (to be investigated). | ||
| 175 | */ | 189 | */ |
| 176 | flush_cache_louis(); | 190 | asm volatile( |
| 177 | set_cr(get_cr() & ~CR_C); | 191 | "str fp, [sp, #-4]! \n\t" |
| 178 | flush_cache_louis(); | 192 | "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" |
| 179 | 193 | "bic r0, r0, #"__stringify(CR_C)" \n\t" | |
| 180 | /* Disable local coherency by clearing the ACTLR "SMP" bit: */ | 194 | "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" |
| 181 | set_auxcr(get_auxcr() & ~(1 << 6)); | 195 | "isb \n\t" |
| 196 | "bl v7_flush_dcache_louis \n\t" | ||
| 197 | "clrex \n\t" | ||
| 198 | "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" | ||
| 199 | "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" | ||
| 200 | "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" | ||
| 201 | "isb \n\t" | ||
| 202 | "dsb \n\t" | ||
| 203 | "ldr fp, [sp], #4" | ||
| 204 | : : : "r0","r1","r2","r3","r4","r5","r6","r7", | ||
| 205 | "r9","r10","lr","memory"); | ||
| 182 | } | 206 | } |
| 183 | 207 | ||
| 184 | __mcpm_cpu_down(cpu, cluster); | 208 | __mcpm_cpu_down(cpu, cluster); |
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c new file mode 100644 index 000000000000..eefb029197ca --- /dev/null +++ b/arch/arm/mach-vexpress/spc.c | |||
| @@ -0,0 +1,180 @@ | |||
| 1 | /* | ||
| 2 | * Versatile Express Serial Power Controller (SPC) support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 ARM Ltd. | ||
| 5 | * | ||
| 6 | * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> | ||
| 7 | * Achin Gupta <achin.gupta@arm.com> | ||
| 8 | * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 15 | * kind, whether express or implied; without even the implied warranty | ||
| 16 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/slab.h> | ||
| 23 | |||
| 24 | #include <asm/cacheflush.h> | ||
| 25 | |||
| 26 | #define SPCLOG "vexpress-spc: " | ||
| 27 | |||
| 28 | /* SPC wake-up IRQs status and mask */ | ||
| 29 | #define WAKE_INT_MASK 0x24 | ||
| 30 | #define WAKE_INT_RAW 0x28 | ||
| 31 | #define WAKE_INT_STAT 0x2c | ||
| 32 | /* SPC power down registers */ | ||
| 33 | #define A15_PWRDN_EN 0x30 | ||
| 34 | #define A7_PWRDN_EN 0x34 | ||
| 35 | /* SPC per-CPU mailboxes */ | ||
| 36 | #define A15_BX_ADDR0 0x68 | ||
| 37 | #define A7_BX_ADDR0 0x78 | ||
| 38 | |||
| 39 | /* wake-up interrupt masks */ | ||
| 40 | #define GBL_WAKEUP_INT_MSK (0x3 << 10) | ||
| 41 | |||
| 42 | /* TC2 static dual-cluster configuration */ | ||
| 43 | #define MAX_CLUSTERS 2 | ||
| 44 | |||
| 45 | struct ve_spc_drvdata { | ||
| 46 | void __iomem *baseaddr; | ||
| 47 | /* | ||
| 48 | * A15s cluster identifier | ||
| 49 | * It corresponds to A15 processors MPIDR[15:8] bitfield | ||
| 50 | */ | ||
| 51 | u32 a15_clusid; | ||
| 52 | }; | ||
| 53 | |||
| 54 | static struct ve_spc_drvdata *info; | ||
| 55 | |||
| 56 | static inline bool cluster_is_a15(u32 cluster) | ||
| 57 | { | ||
| 58 | return cluster == info->a15_clusid; | ||
| 59 | } | ||
| 60 | |||
| 61 | /** | ||
| 62 | * ve_spc_global_wakeup_irq() | ||
| 63 | * | ||
| 64 | * Function to set/clear global wakeup IRQs. Not protected by locking since | ||
| 65 | * it might be used in code paths where normal cacheable locks are not | ||
| 66 | * working. Locking must be provided by the caller to ensure atomicity. | ||
| 67 | * | ||
| 68 | * @set: if true, global wake-up IRQs are set, if false they are cleared | ||
| 69 | */ | ||
| 70 | void ve_spc_global_wakeup_irq(bool set) | ||
| 71 | { | ||
| 72 | u32 reg; | ||
| 73 | |||
| 74 | reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); | ||
| 75 | |||
| 76 | if (set) | ||
| 77 | reg |= GBL_WAKEUP_INT_MSK; | ||
| 78 | else | ||
| 79 | reg &= ~GBL_WAKEUP_INT_MSK; | ||
| 80 | |||
| 81 | writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); | ||
| 82 | } | ||
| 83 | |||
| 84 | /** | ||
| 85 | * ve_spc_cpu_wakeup_irq() | ||
| 86 | * | ||
| 87 | * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since | ||
| 88 | * it might be used in code paths where normal cacheable locks are not | ||
| 89 | * working. Locking must be provided by the caller to ensure atomicity. | ||
| 90 | * | ||
| 91 | * @cluster: mpidr[15:8] bitfield describing cluster affinity level | ||
| 92 | * @cpu: mpidr[7:0] bitfield describing cpu affinity level | ||
| 93 | * @set: if true, wake-up IRQs are set, if false they are cleared | ||
| 94 | */ | ||
| 95 | void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set) | ||
| 96 | { | ||
| 97 | u32 mask, reg; | ||
| 98 | |||
| 99 | if (cluster >= MAX_CLUSTERS) | ||
| 100 | return; | ||
| 101 | |||
| 102 | mask = 1 << cpu; | ||
| 103 | |||
| 104 | if (!cluster_is_a15(cluster)) | ||
| 105 | mask <<= 4; | ||
| 106 | |||
| 107 | reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); | ||
| 108 | |||
| 109 | if (set) | ||
| 110 | reg |= mask; | ||
| 111 | else | ||
| 112 | reg &= ~mask; | ||
| 113 | |||
| 114 | writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); | ||
| 115 | } | ||
| 116 | |||
| 117 | /** | ||
| 118 | * ve_spc_set_resume_addr() - set the jump address used for warm boot | ||
| 119 | * | ||
| 120 | * @cluster: mpidr[15:8] bitfield describing cluster affinity level | ||
| 121 | * @cpu: mpidr[7:0] bitfield describing cpu affinity level | ||
| 122 | * @addr: physical resume address | ||
| 123 | */ | ||
| 124 | void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr) | ||
| 125 | { | ||
| 126 | void __iomem *baseaddr; | ||
| 127 | |||
| 128 | if (cluster >= MAX_CLUSTERS) | ||
| 129 | return; | ||
| 130 | |||
| 131 | if (cluster_is_a15(cluster)) | ||
| 132 | baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2); | ||
| 133 | else | ||
| 134 | baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2); | ||
| 135 | |||
| 136 | writel_relaxed(addr, baseaddr); | ||
| 137 | } | ||
| 138 | |||
| 139 | /** | ||
| 140 | * ve_spc_powerdown() | ||
| 141 | * | ||
| 142 | * Function to enable/disable cluster powerdown. Not protected by locking | ||
| 143 | * since it might be used in code paths where normal cacheable locks are not | ||
| 144 | * working. Locking must be provided by the caller to ensure atomicity. | ||
| 145 | * | ||
| 146 | * @cluster: mpidr[15:8] bitfield describing cluster affinity level | ||
| 147 | * @enable: if true enables powerdown, if false disables it | ||
| 148 | */ | ||
| 149 | void ve_spc_powerdown(u32 cluster, bool enable) | ||
| 150 | { | ||
| 151 | u32 pwdrn_reg; | ||
| 152 | |||
| 153 | if (cluster >= MAX_CLUSTERS) | ||
| 154 | return; | ||
| 155 | |||
| 156 | pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN; | ||
| 157 | writel_relaxed(enable, info->baseaddr + pwdrn_reg); | ||
| 158 | } | ||
| 159 | |||
| 160 | int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid) | ||
| 161 | { | ||
| 162 | info = kzalloc(sizeof(*info), GFP_KERNEL); | ||
| 163 | if (!info) { | ||
| 164 | pr_err(SPCLOG "unable to allocate mem\n"); | ||
| 165 | return -ENOMEM; | ||
| 166 | } | ||
| 167 | |||
| 168 | info->baseaddr = baseaddr; | ||
| 169 | info->a15_clusid = a15_clusid; | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Multi-cluster systems may need this data when non-coherent, during | ||
| 173 | * cluster power-up/power-down. Make sure driver info reaches main | ||
| 174 | * memory. | ||
| 175 | */ | ||
| 176 | sync_cache_w(info); | ||
| 177 | sync_cache_w(&info); | ||
| 178 | |||
| 179 | return 0; | ||
| 180 | } | ||
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h new file mode 100644 index 000000000000..5f7e4a446a17 --- /dev/null +++ b/arch/arm/mach-vexpress/spc.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify | ||
| 3 | * it under the terms of the GNU General Public License version 2 as | ||
| 4 | * published by the Free Software Foundation. | ||
| 5 | * | ||
| 6 | * This program is distributed in the hope that it will be useful, | ||
| 7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 9 | * GNU General Public License for more details. | ||
| 10 | * | ||
| 11 | * Copyright (C) 2012 ARM Limited | ||
| 12 | */ | ||
| 13 | |||
| 14 | |||
| 15 | #ifndef __SPC_H_ | ||
| 16 | #define __SPC_H_ | ||
| 17 | |||
| 18 | int __init ve_spc_init(void __iomem *base, u32 a15_clusid); | ||
| 19 | void ve_spc_global_wakeup_irq(bool set); | ||
| 20 | void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); | ||
| 21 | void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); | ||
| 22 | void ve_spc_powerdown(u32 cluster, bool enable); | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c new file mode 100644 index 000000000000..2b7c93a724ed --- /dev/null +++ b/arch/arm/mach-vexpress/tc2_pm.c | |||
| @@ -0,0 +1,352 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support | ||
| 3 | * | ||
| 4 | * Created by: Nicolas Pitre, October 2012 | ||
| 5 | * Copyright: (C) 2012-2013 Linaro Limited | ||
| 6 | * | ||
| 7 | * Some portions of this file were originally written by Achin Gupta | ||
| 8 | * Copyright: (C) 2012 ARM Limited | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <linux/spinlock.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | |||
| 22 | #include <asm/mcpm.h> | ||
| 23 | #include <asm/proc-fns.h> | ||
| 24 | #include <asm/cacheflush.h> | ||
| 25 | #include <asm/cputype.h> | ||
| 26 | #include <asm/cp15.h> | ||
| 27 | |||
| 28 | #include <linux/arm-cci.h> | ||
| 29 | |||
| 30 | #include "spc.h" | ||
| 31 | |||
| 32 | /* SCC conf registers */ | ||
| 33 | #define A15_CONF 0x400 | ||
| 34 | #define A7_CONF 0x500 | ||
| 35 | #define SYS_INFO 0x700 | ||
| 36 | #define SPC_BASE 0xb00 | ||
| 37 | |||
| 38 | /* | ||
| 39 | * We can't use regular spinlocks. In the switcher case, it is possible | ||
| 40 | * for an outbound CPU to call power_down() after its inbound counterpart | ||
| 41 | * is already live using the same logical CPU number which trips lockdep | ||
| 42 | * debugging. | ||
| 43 | */ | ||
| 44 | static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED; | ||
| 45 | |||
| 46 | #define TC2_CLUSTERS 2 | ||
| 47 | #define TC2_MAX_CPUS_PER_CLUSTER 3 | ||
| 48 | |||
| 49 | static unsigned int tc2_nr_cpus[TC2_CLUSTERS]; | ||
| 50 | |||
| 51 | /* Keep per-cpu usage count to cope with unordered up/down requests */ | ||
| 52 | static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS]; | ||
| 53 | |||
| 54 | #define tc2_cluster_unused(cluster) \ | ||
| 55 | (!tc2_pm_use_count[0][cluster] && \ | ||
| 56 | !tc2_pm_use_count[1][cluster] && \ | ||
| 57 | !tc2_pm_use_count[2][cluster]) | ||
| 58 | |||
| 59 | static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster) | ||
| 60 | { | ||
| 61 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); | ||
| 62 | if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) | ||
| 63 | return -EINVAL; | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Since this is called with IRQs enabled, and no arch_spin_lock_irq | ||
| 67 | * variant exists, we need to disable IRQs manually here. | ||
| 68 | */ | ||
| 69 | local_irq_disable(); | ||
| 70 | arch_spin_lock(&tc2_pm_lock); | ||
| 71 | |||
| 72 | if (tc2_cluster_unused(cluster)) | ||
| 73 | ve_spc_powerdown(cluster, false); | ||
| 74 | |||
| 75 | tc2_pm_use_count[cpu][cluster]++; | ||
| 76 | if (tc2_pm_use_count[cpu][cluster] == 1) { | ||
| 77 | ve_spc_set_resume_addr(cluster, cpu, | ||
| 78 | virt_to_phys(mcpm_entry_point)); | ||
| 79 | ve_spc_cpu_wakeup_irq(cluster, cpu, true); | ||
| 80 | } else if (tc2_pm_use_count[cpu][cluster] != 2) { | ||
| 81 | /* | ||
| 82 | * The only possible values are: | ||
| 83 | * 0 = CPU down | ||
| 84 | * 1 = CPU (still) up | ||
| 85 | * 2 = CPU requested to be up before it had a chance | ||
| 86 | * to actually make itself down. | ||
| 87 | * Any other value is a bug. | ||
| 88 | */ | ||
| 89 | BUG(); | ||
| 90 | } | ||
| 91 | |||
| 92 | arch_spin_unlock(&tc2_pm_lock); | ||
| 93 | local_irq_enable(); | ||
| 94 | |||
| 95 | return 0; | ||
| 96 | } | ||
| 97 | |||
| 98 | static void tc2_pm_down(u64 residency) | ||
| 99 | { | ||
| 100 | unsigned int mpidr, cpu, cluster; | ||
| 101 | bool last_man = false, skip_wfi = false; | ||
| 102 | |||
| 103 | mpidr = read_cpuid_mpidr(); | ||
| 104 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | ||
| 105 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); | ||
| 106 | |||
| 107 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); | ||
| 108 | BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); | ||
| 109 | |||
| 110 | __mcpm_cpu_going_down(cpu, cluster); | ||
| 111 | |||
| 112 | arch_spin_lock(&tc2_pm_lock); | ||
| 113 | BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); | ||
| 114 | tc2_pm_use_count[cpu][cluster]--; | ||
| 115 | if (tc2_pm_use_count[cpu][cluster] == 0) { | ||
| 116 | ve_spc_cpu_wakeup_irq(cluster, cpu, true); | ||
| 117 | if (tc2_cluster_unused(cluster)) { | ||
| 118 | ve_spc_powerdown(cluster, true); | ||
| 119 | ve_spc_global_wakeup_irq(true); | ||
| 120 | last_man = true; | ||
| 121 | } | ||
| 122 | } else if (tc2_pm_use_count[cpu][cluster] == 1) { | ||
| 123 | /* | ||
| 124 | * A power_up request went ahead of us. | ||
| 125 | * Even if we do not want to shut this CPU down, | ||
| 126 | * the caller expects a certain state as if the WFI | ||
| 127 | * was aborted. So let's continue with cache cleaning. | ||
| 128 | */ | ||
| 129 | skip_wfi = true; | ||
| 130 | } else | ||
| 131 | BUG(); | ||
| 132 | |||
| 133 | if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { | ||
| 134 | arch_spin_unlock(&tc2_pm_lock); | ||
| 135 | |||
| 136 | if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { | ||
| 137 | /* | ||
| 138 | * On the Cortex-A15 we need to disable | ||
| 139 | * L2 prefetching before flushing the cache. | ||
| 140 | */ | ||
| 141 | asm volatile( | ||
| 142 | "mcr p15, 1, %0, c15, c0, 3 \n\t" | ||
| 143 | "isb \n\t" | ||
| 144 | "dsb " | ||
| 145 | : : "r" (0x400) ); | ||
| 146 | } | ||
| 147 | |||
| 148 | /* | ||
| 149 | * We need to disable and flush the whole (L1 and L2) cache. | ||
| 150 | * Let's do it in the safest possible way i.e. with | ||
| 151 | * no memory access within the following sequence | ||
| 152 | * including the stack. | ||
| 153 | * | ||
| 154 | * Note: fp is preserved to the stack explicitly prior doing | ||
| 155 | * this since adding it to the clobber list is incompatible | ||
| 156 | * with having CONFIG_FRAME_POINTER=y. | ||
| 157 | */ | ||
| 158 | asm volatile( | ||
| 159 | "str fp, [sp, #-4]! \n\t" | ||
| 160 | "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" | ||
| 161 | "bic r0, r0, #"__stringify(CR_C)" \n\t" | ||
| 162 | "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" | ||
| 163 | "isb \n\t" | ||
| 164 | "bl v7_flush_dcache_all \n\t" | ||
| 165 | "clrex \n\t" | ||
| 166 | "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" | ||
| 167 | "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" | ||
| 168 | "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" | ||
| 169 | "isb \n\t" | ||
| 170 | "dsb \n\t" | ||
| 171 | "ldr fp, [sp], #4" | ||
| 172 | : : : "r0","r1","r2","r3","r4","r5","r6","r7", | ||
| 173 | "r9","r10","lr","memory"); | ||
| 174 | |||
| 175 | cci_disable_port_by_cpu(mpidr); | ||
| 176 | |||
| 177 | __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); | ||
| 178 | } else { | ||
| 179 | /* | ||
| 180 | * If last man then undo any setup done previously. | ||
| 181 | */ | ||
| 182 | if (last_man) { | ||
| 183 | ve_spc_powerdown(cluster, false); | ||
| 184 | ve_spc_global_wakeup_irq(false); | ||
| 185 | } | ||
| 186 | |||
| 187 | arch_spin_unlock(&tc2_pm_lock); | ||
| 188 | |||
| 189 | /* | ||
| 190 | * We need to disable and flush only the L1 cache. | ||
| 191 | * Let's do it in the safest possible way as above. | ||
| 192 | */ | ||
| 193 | asm volatile( | ||
| 194 | "str fp, [sp, #-4]! \n\t" | ||
| 195 | "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" | ||
| 196 | "bic r0, r0, #"__stringify(CR_C)" \n\t" | ||
| 197 | "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" | ||
| 198 | "isb \n\t" | ||
| 199 | "bl v7_flush_dcache_louis \n\t" | ||
| 200 | "clrex \n\t" | ||
| 201 | "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" | ||
| 202 | "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" | ||
| 203 | "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" | ||
| 204 | "isb \n\t" | ||
| 205 | "dsb \n\t" | ||
| 206 | "ldr fp, [sp], #4" | ||
| 207 | : : : "r0","r1","r2","r3","r4","r5","r6","r7", | ||
| 208 | "r9","r10","lr","memory"); | ||
| 209 | } | ||
| 210 | |||
| 211 | __mcpm_cpu_down(cpu, cluster); | ||
| 212 | |||
| 213 | /* Now we are prepared for power-down, do it: */ | ||
| 214 | if (!skip_wfi) | ||
| 215 | wfi(); | ||
| 216 | |||
| 217 | /* Not dead at this point? Let our caller cope. */ | ||
| 218 | } | ||
| 219 | |||
| 220 | static void tc2_pm_power_down(void) | ||
| 221 | { | ||
| 222 | tc2_pm_down(0); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void tc2_pm_suspend(u64 residency) | ||
| 226 | { | ||
| 227 | unsigned int mpidr, cpu, cluster; | ||
| 228 | |||
| 229 | mpidr = read_cpuid_mpidr(); | ||
| 230 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | ||
| 231 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); | ||
| 232 | ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point)); | ||
| 233 | tc2_pm_down(residency); | ||
| 234 | } | ||
| 235 | |||
| 236 | static void tc2_pm_powered_up(void) | ||
| 237 | { | ||
| 238 | unsigned int mpidr, cpu, cluster; | ||
| 239 | unsigned long flags; | ||
| 240 | |||
| 241 | mpidr = read_cpuid_mpidr(); | ||
| 242 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | ||
| 243 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); | ||
| 244 | |||
| 245 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); | ||
| 246 | BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); | ||
| 247 | |||
| 248 | local_irq_save(flags); | ||
| 249 | arch_spin_lock(&tc2_pm_lock); | ||
| 250 | |||
| 251 | if (tc2_cluster_unused(cluster)) { | ||
| 252 | ve_spc_powerdown(cluster, false); | ||
| 253 | ve_spc_global_wakeup_irq(false); | ||
| 254 | } | ||
| 255 | |||
| 256 | if (!tc2_pm_use_count[cpu][cluster]) | ||
| 257 | tc2_pm_use_count[cpu][cluster] = 1; | ||
| 258 | |||
| 259 | ve_spc_cpu_wakeup_irq(cluster, cpu, false); | ||
| 260 | ve_spc_set_resume_addr(cluster, cpu, 0); | ||
| 261 | |||
| 262 | arch_spin_unlock(&tc2_pm_lock); | ||
| 263 | local_irq_restore(flags); | ||
| 264 | } | ||
| 265 | |||
| 266 | static const struct mcpm_platform_ops tc2_pm_power_ops = { | ||
| 267 | .power_up = tc2_pm_power_up, | ||
| 268 | .power_down = tc2_pm_power_down, | ||
| 269 | .suspend = tc2_pm_suspend, | ||
| 270 | .powered_up = tc2_pm_powered_up, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static bool __init tc2_pm_usage_count_init(void) | ||
| 274 | { | ||
| 275 | unsigned int mpidr, cpu, cluster; | ||
| 276 | |||
| 277 | mpidr = read_cpuid_mpidr(); | ||
| 278 | cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | ||
| 279 | cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); | ||
| 280 | |||
| 281 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); | ||
| 282 | if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) { | ||
| 283 | pr_err("%s: boot CPU is out of bound!\n", __func__); | ||
| 284 | return false; | ||
| 285 | } | ||
| 286 | tc2_pm_use_count[cpu][cluster] = 1; | ||
| 287 | return true; | ||
| 288 | } | ||
| 289 | |||
| 290 | /* | ||
| 291 | * Enable cluster-level coherency, in preparation for turning on the MMU. | ||
| 292 | */ | ||
| 293 | static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) | ||
| 294 | { | ||
| 295 | asm volatile (" \n" | ||
| 296 | " cmp r0, #1 \n" | ||
| 297 | " bxne lr \n" | ||
| 298 | " b cci_enable_port_for_self "); | ||
| 299 | } | ||
| 300 | |||
| 301 | static int __init tc2_pm_init(void) | ||
| 302 | { | ||
| 303 | int ret; | ||
| 304 | void __iomem *scc; | ||
| 305 | u32 a15_cluster_id, a7_cluster_id, sys_info; | ||
| 306 | struct device_node *np; | ||
| 307 | |||
| 308 | /* | ||
| 309 | * The power management-related features are hidden behind | ||
| 310 | * SCC registers. We need to extract runtime information like | ||
| 311 | * cluster ids and number of CPUs really available in clusters. | ||
| 312 | */ | ||
| 313 | np = of_find_compatible_node(NULL, NULL, | ||
| 314 | "arm,vexpress-scc,v2p-ca15_a7"); | ||
| 315 | scc = of_iomap(np, 0); | ||
| 316 | if (!scc) | ||
| 317 | return -ENODEV; | ||
| 318 | |||
| 319 | a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; | ||
| 320 | a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; | ||
| 321 | if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS) | ||
| 322 | return -EINVAL; | ||
| 323 | |||
| 324 | sys_info = readl_relaxed(scc + SYS_INFO); | ||
| 325 | tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf; | ||
| 326 | tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf; | ||
| 327 | |||
| 328 | /* | ||
| 329 | * A subset of the SCC registers is also used to communicate | ||
| 330 | * with the SPC (power controller). We need to be able to | ||
| 331 | * drive it very early in the boot process to power up | ||
| 332 | * processors, so we initialize the SPC driver here. | ||
| 333 | */ | ||
| 334 | ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id); | ||
| 335 | if (ret) | ||
| 336 | return ret; | ||
| 337 | |||
| 338 | if (!cci_probed()) | ||
| 339 | return -ENODEV; | ||
| 340 | |||
| 341 | if (!tc2_pm_usage_count_init()) | ||
| 342 | return -EINVAL; | ||
| 343 | |||
| 344 | ret = mcpm_platform_register(&tc2_pm_power_ops); | ||
| 345 | if (!ret) { | ||
| 346 | mcpm_sync_init(tc2_pm_power_up_setup); | ||
| 347 | pr_info("TC2 power management initialized\n"); | ||
| 348 | } | ||
| 349 | return ret; | ||
| 350 | } | ||
| 351 | |||
| 352 | early_initcall(tc2_pm_init); | ||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index f82bae2171eb..436ea97074cd 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -106,7 +106,7 @@ config OMAP_32K_TIMER | |||
| 106 | This timer saves power compared to the OMAP_MPU_TIMER, and has | 106 | This timer saves power compared to the OMAP_MPU_TIMER, and has |
| 107 | support for no tick during idle. The 32KHz timer provides less | 107 | support for no tick during idle. The 32KHz timer provides less |
| 108 | intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is | 108 | intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is |
| 109 | currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5. | 109 | currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX. |
| 110 | 110 | ||
| 111 | On OMAP2PLUS this value is only used for CONFIG_HZ and | 111 | On OMAP2PLUS this value is only used for CONFIG_HZ and |
| 112 | CLOCK_TICK_RATE compile time calculation. | 112 | CLOCK_TICK_RATE compile time calculation. |
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 566642266324..a86a56d9e73f 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig | |||
| @@ -9,7 +9,6 @@ config IA64 | |||
| 9 | select PCI if (!IA64_HP_SIM) | 9 | select PCI if (!IA64_HP_SIM) |
| 10 | select ACPI if (!IA64_HP_SIM) | 10 | select ACPI if (!IA64_HP_SIM) |
| 11 | select PM if (!IA64_HP_SIM) | 11 | select PM if (!IA64_HP_SIM) |
| 12 | select ARCH_SUPPORTS_MSI | ||
| 13 | select HAVE_UNSTABLE_SCHED_CLOCK | 12 | select HAVE_UNSTABLE_SCHED_CLOCK |
| 14 | select HAVE_IDE | 13 | select HAVE_IDE |
| 15 | select HAVE_OPROFILE | 14 | select HAVE_OPROFILE |
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dccd7cec442d..71f15e73bc89 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -727,7 +727,6 @@ config CAVIUM_OCTEON_SOC | |||
| 727 | select SYS_HAS_CPU_CAVIUM_OCTEON | 727 | select SYS_HAS_CPU_CAVIUM_OCTEON |
| 728 | select SWAP_IO_SPACE | 728 | select SWAP_IO_SPACE |
| 729 | select HW_HAS_PCI | 729 | select HW_HAS_PCI |
| 730 | select ARCH_SUPPORTS_MSI | ||
| 731 | select ZONE_DMA32 | 730 | select ZONE_DMA32 |
| 732 | select USB_ARCH_HAS_OHCI | 731 | select USB_ARCH_HAS_OHCI |
| 733 | select USB_ARCH_HAS_EHCI | 732 | select USB_ARCH_HAS_EHCI |
| @@ -763,7 +762,6 @@ config NLM_XLR_BOARD | |||
| 763 | select CEVT_R4K | 762 | select CEVT_R4K |
| 764 | select CSRC_R4K | 763 | select CSRC_R4K |
| 765 | select IRQ_CPU | 764 | select IRQ_CPU |
| 766 | select ARCH_SUPPORTS_MSI | ||
| 767 | select ZONE_DMA32 if 64BIT | 765 | select ZONE_DMA32 if 64BIT |
| 768 | select SYNC_R4K | 766 | select SYNC_R4K |
| 769 | select SYS_HAS_EARLY_PRINTK | 767 | select SYS_HAS_EARLY_PRINTK |
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fa8e0aa250ca..f194c08bd057 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h | |||
| @@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |||
| 136 | return channel ? 15 : 14; | 136 | return channel ? 15 : 14; |
| 137 | } | 137 | } |
| 138 | 138 | ||
| 139 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
| 140 | /* MSI arch hook for OCTEON */ | ||
| 141 | #define arch_setup_msi_irqs arch_setup_msi_irqs | ||
| 142 | #endif | ||
| 143 | |||
| 144 | extern char * (*pcibios_plat_setup)(char *str); | 139 | extern char * (*pcibios_plat_setup)(char *str); |
| 145 | 140 | ||
| 146 | #ifdef CONFIG_OF | 141 | #ifdef CONFIG_OF |
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index a4e3a93bf2d4..6b7530f8183c 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig | |||
| @@ -747,7 +747,6 @@ config PCI | |||
| 747 | default y if !40x && !CPM2 && !8xx && !PPC_83xx \ | 747 | default y if !40x && !CPM2 && !8xx && !PPC_83xx \ |
| 748 | && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON | 748 | && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON |
| 749 | default PCI_QSPAN if !4xx && !CPM2 && 8xx | 749 | default PCI_QSPAN if !4xx && !CPM2 && 8xx |
| 750 | select ARCH_SUPPORTS_MSI | ||
| 751 | select GENERIC_PCI_IOMAP | 750 | select GENERIC_PCI_IOMAP |
| 752 | help | 751 | help |
| 753 | Find out whether your system includes a PCI bus. PCI is the name of | 752 | Find out whether your system includes a PCI bus. PCI is the name of |
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 6653f2743c4e..95145a15c708 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h | |||
| @@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus); | |||
| 113 | /* Decide whether to display the domain number in /proc */ | 113 | /* Decide whether to display the domain number in /proc */ |
| 114 | extern int pci_proc_domain(struct pci_bus *bus); | 114 | extern int pci_proc_domain(struct pci_bus *bus); |
| 115 | 115 | ||
| 116 | /* MSI arch hooks */ | ||
| 117 | #define arch_setup_msi_irqs arch_setup_msi_irqs | ||
| 118 | #define arch_teardown_msi_irqs arch_teardown_msi_irqs | ||
| 119 | #define arch_msi_check_device arch_msi_check_device | ||
| 120 | |||
| 121 | struct vm_area_struct; | 116 | struct vm_area_struct; |
| 122 | /* Map a range of PCI memory or I/O space for a device into user space */ | 117 | /* Map a range of PCI memory or I/O space for a device into user space */ |
| 123 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | 118 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, |
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 8b7892bf6d8b..c696ad7d3439 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig | |||
| @@ -431,7 +431,6 @@ menuconfig PCI | |||
| 431 | bool "PCI support" | 431 | bool "PCI support" |
| 432 | default n | 432 | default n |
| 433 | depends on 64BIT | 433 | depends on 64BIT |
| 434 | select ARCH_SUPPORTS_MSI | ||
| 435 | select PCI_MSI | 434 | select PCI_MSI |
| 436 | help | 435 | help |
| 437 | Enable PCI support. | 436 | Enable PCI support. |
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index c290f13d1c47..1cc185da9d38 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h | |||
| @@ -22,10 +22,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *); | |||
| 22 | int pci_domain_nr(struct pci_bus *); | 22 | int pci_domain_nr(struct pci_bus *); |
| 23 | int pci_proc_domain(struct pci_bus *); | 23 | int pci_proc_domain(struct pci_bus *); |
| 24 | 24 | ||
| 25 | /* MSI arch hooks */ | ||
| 26 | #define arch_setup_msi_irqs arch_setup_msi_irqs | ||
| 27 | #define arch_teardown_msi_irqs arch_teardown_msi_irqs | ||
| 28 | |||
| 29 | #define ZPCI_BUS_NR 0 /* default bus number */ | 25 | #define ZPCI_BUS_NR 0 /* default bus number */ |
| 30 | #define ZPCI_DEVFN 0 /* default device number */ | 26 | #define ZPCI_DEVFN 0 /* default device number */ |
| 31 | 27 | ||
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a00cbd356db5..1570ad2802b3 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig | |||
| @@ -52,7 +52,6 @@ config SPARC32 | |||
| 52 | 52 | ||
| 53 | config SPARC64 | 53 | config SPARC64 |
| 54 | def_bool 64BIT | 54 | def_bool 64BIT |
| 55 | select ARCH_SUPPORTS_MSI | ||
| 56 | select HAVE_FUNCTION_TRACER | 55 | select HAVE_FUNCTION_TRACER |
| 57 | select HAVE_FUNCTION_GRAPH_TRACER | 56 | select HAVE_FUNCTION_GRAPH_TRACER |
| 58 | select HAVE_FUNCTION_GRAPH_FP_TEST | 57 | select HAVE_FUNCTION_GRAPH_FP_TEST |
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 6e1ed55f6cfc..932fa14de5fe 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig | |||
| @@ -395,7 +395,6 @@ config PCI | |||
| 395 | select PCI_DOMAINS | 395 | select PCI_DOMAINS |
| 396 | select GENERIC_PCI_IOMAP | 396 | select GENERIC_PCI_IOMAP |
| 397 | select TILE_GXIO_TRIO if TILEGX | 397 | select TILE_GXIO_TRIO if TILEGX |
| 398 | select ARCH_SUPPORTS_MSI if TILEGX | ||
| 399 | select PCI_MSI if TILEGX | 398 | select PCI_MSI if TILEGX |
| 400 | ---help--- | 399 | ---help--- |
| 401 | Enable PCI root complex support, so PCIe endpoint devices can | 400 | Enable PCI root complex support, so PCIe endpoint devices can |
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c0ed72c02a2..30c40f08a3d4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig | |||
| @@ -2032,7 +2032,6 @@ menu "Bus options (PCI etc.)" | |||
| 2032 | config PCI | 2032 | config PCI |
| 2033 | bool "PCI support" | 2033 | bool "PCI support" |
| 2034 | default y | 2034 | default y |
| 2035 | select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) | ||
| 2036 | ---help--- | 2035 | ---help--- |
| 2037 | Find out whether you have a PCI motherboard. PCI is the name of a | 2036 | Find out whether you have a PCI motherboard. PCI is the name of a |
| 2038 | bus system, i.e. the way the CPU talks to the other stuff inside | 2037 | bus system, i.e. the way the CPU talks to the other stuff inside |
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index d9e9e6c7ed32..7d7443283a9d 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h | |||
| @@ -100,29 +100,6 @@ static inline void early_quirks(void) { } | |||
| 100 | extern void pci_iommu_alloc(void); | 100 | extern void pci_iommu_alloc(void); |
| 101 | 101 | ||
| 102 | #ifdef CONFIG_PCI_MSI | 102 | #ifdef CONFIG_PCI_MSI |
| 103 | /* MSI arch specific hooks */ | ||
| 104 | static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | ||
| 105 | { | ||
| 106 | return x86_msi.setup_msi_irqs(dev, nvec, type); | ||
| 107 | } | ||
| 108 | |||
| 109 | static inline void x86_teardown_msi_irqs(struct pci_dev *dev) | ||
| 110 | { | ||
| 111 | x86_msi.teardown_msi_irqs(dev); | ||
| 112 | } | ||
| 113 | |||
| 114 | static inline void x86_teardown_msi_irq(unsigned int irq) | ||
| 115 | { | ||
| 116 | x86_msi.teardown_msi_irq(irq); | ||
| 117 | } | ||
| 118 | static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq) | ||
| 119 | { | ||
| 120 | x86_msi.restore_msi_irqs(dev, irq); | ||
| 121 | } | ||
| 122 | #define arch_setup_msi_irqs x86_setup_msi_irqs | ||
| 123 | #define arch_teardown_msi_irqs x86_teardown_msi_irqs | ||
| 124 | #define arch_teardown_msi_irq x86_teardown_msi_irq | ||
| 125 | #define arch_restore_msi_irqs x86_restore_msi_irqs | ||
| 126 | /* implemented in arch/x86/kernel/apic/io_apic. */ | 103 | /* implemented in arch/x86/kernel/apic/io_apic. */ |
| 127 | struct msi_desc; | 104 | struct msi_desc; |
| 128 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); | 105 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); |
| @@ -130,16 +107,9 @@ void native_teardown_msi_irq(unsigned int irq); | |||
| 130 | void native_restore_msi_irqs(struct pci_dev *dev, int irq); | 107 | void native_restore_msi_irqs(struct pci_dev *dev, int irq); |
| 131 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, | 108 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
| 132 | unsigned int irq_base, unsigned int irq_offset); | 109 | unsigned int irq_base, unsigned int irq_offset); |
| 133 | /* default to the implementation in drivers/lib/msi.c */ | ||
| 134 | #define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | ||
| 135 | #define HAVE_DEFAULT_MSI_RESTORE_IRQS | ||
| 136 | void default_teardown_msi_irqs(struct pci_dev *dev); | ||
| 137 | void default_restore_msi_irqs(struct pci_dev *dev, int irq); | ||
| 138 | #else | 110 | #else |
| 139 | #define native_setup_msi_irqs NULL | 111 | #define native_setup_msi_irqs NULL |
| 140 | #define native_teardown_msi_irq NULL | 112 | #define native_teardown_msi_irq NULL |
| 141 | #define default_teardown_msi_irqs NULL | ||
| 142 | #define default_restore_msi_irqs NULL | ||
| 143 | #endif | 113 | #endif |
| 144 | 114 | ||
| 145 | #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) | 115 | #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) |
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 5f24c71accaa..8ce0072cd700 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c | |||
| @@ -107,6 +107,8 @@ struct x86_platform_ops x86_platform = { | |||
| 107 | }; | 107 | }; |
| 108 | 108 | ||
| 109 | EXPORT_SYMBOL_GPL(x86_platform); | 109 | EXPORT_SYMBOL_GPL(x86_platform); |
| 110 | |||
| 111 | #if defined(CONFIG_PCI_MSI) | ||
| 110 | struct x86_msi_ops x86_msi = { | 112 | struct x86_msi_ops x86_msi = { |
| 111 | .setup_msi_irqs = native_setup_msi_irqs, | 113 | .setup_msi_irqs = native_setup_msi_irqs, |
| 112 | .compose_msi_msg = native_compose_msi_msg, | 114 | .compose_msi_msg = native_compose_msi_msg, |
| @@ -116,6 +118,28 @@ struct x86_msi_ops x86_msi = { | |||
| 116 | .setup_hpet_msi = default_setup_hpet_msi, | 118 | .setup_hpet_msi = default_setup_hpet_msi, |
| 117 | }; | 119 | }; |
| 118 | 120 | ||
| 121 | /* MSI arch specific hooks */ | ||
| 122 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | ||
| 123 | { | ||
| 124 | return x86_msi.setup_msi_irqs(dev, nvec, type); | ||
| 125 | } | ||
| 126 | |||
| 127 | void arch_teardown_msi_irqs(struct pci_dev *dev) | ||
| 128 | { | ||
| 129 | x86_msi.teardown_msi_irqs(dev); | ||
| 130 | } | ||
| 131 | |||
| 132 | void arch_teardown_msi_irq(unsigned int irq) | ||
| 133 | { | ||
| 134 | x86_msi.teardown_msi_irq(irq); | ||
| 135 | } | ||
| 136 | |||
| 137 | void arch_restore_msi_irqs(struct pci_dev *dev, int irq) | ||
| 138 | { | ||
| 139 | x86_msi.restore_msi_irqs(dev, irq); | ||
| 140 | } | ||
| 141 | #endif | ||
| 142 | |||
| 119 | struct x86_io_apic_ops x86_io_apic_ops = { | 143 | struct x86_io_apic_ops x86_io_apic_ops = { |
| 120 | .init = native_io_apic_init_mappings, | 144 | .init = native_io_apic_init_mappings, |
| 121 | .read = native_io_apic_read, | 145 | .read = native_io_apic_read, |