ARM: dts: imx6q-sabrelite: add ssi device

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

2 files changed, 20 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 1ca9b3ecb882..1aebefe21571 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -35,6 +35,11 @@
                                                 reg = <0>;
                                         };
                                 };
+
+                                ssi1: ssi@02028000 {
+                                        fsl,mode = "i2s-slave";
+                                        status = "okay";
+                                };
                         };
 
                 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 72ccd1d21cd9..760ca335a9f8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -177,19 +177,31 @@
                                         interrupts = <0 51 0x04>;
                                 };
 
-                                ssi@02028000 { /* SSI1 */
+                                ssi1: ssi@02028000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 0x04>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <38 37>;
+                                        status = "disabled";
                                 };
 
-                                ssi@0202c000 { /* SSI2 */
+                                ssi2: ssi@0202c000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 0x04>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <42 41>;
+                                        status = "disabled";
                                 };
 
-                                ssi@02030000 { /* SSI3 */
+                                ssi3: ssi@02030000 {
+                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 0x04>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <46 45>;
+                                        status = "disabled";
                                 };
 
                                 asrc@02034000 {