diff options
| author | Joseph Lo <josephl@nvidia.com> | 2013-01-15 17:11:01 -0500 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 13:20:38 -0500 |
| commit | afec581c4b53e03a97d9ef1b7a746a67967573cf (patch) | |
| tree | 148b93a680ee69542ac3cb8dfc7ff77a64cea6ea /arch | |
| parent | 4a2e32794e71db679b91df1d9c98921b2e32ec4e (diff) | |
ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/flowctrl.c | 38 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/flowctrl.h | 4 |
2 files changed, 37 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index 5393eb2cae21..b477ef310dcd 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include "flowctrl.h" | 26 | #include "flowctrl.h" |
| 27 | #include "iomap.h" | 27 | #include "iomap.h" |
| 28 | #include "fuse.h" | ||
| 28 | 29 | ||
| 29 | static u8 flowctrl_offset_halt_cpu[] = { | 30 | static u8 flowctrl_offset_halt_cpu[] = { |
| 30 | FLOW_CTRL_HALT_CPU0_EVENTS, | 31 | FLOW_CTRL_HALT_CPU0_EVENTS, |
| @@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) | |||
| 75 | int i; | 76 | int i; |
| 76 | 77 | ||
| 77 | reg = flowctrl_read_cpu_csr(cpuid); | 78 | reg = flowctrl_read_cpu_csr(cpuid); |
| 78 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ | 79 | switch (tegra_chip_id) { |
| 79 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ | 80 | case TEGRA20: |
| 81 | /* clear wfe bitmap */ | ||
| 82 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; | ||
| 83 | /* clear wfi bitmap */ | ||
| 84 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; | ||
| 85 | /* pwr gating on wfe */ | ||
| 86 | reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; | ||
| 87 | break; | ||
| 88 | case TEGRA30: | ||
| 89 | /* clear wfe bitmap */ | ||
| 90 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | ||
| 91 | /* clear wfi bitmap */ | ||
| 92 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; | ||
| 93 | /* pwr gating on wfi */ | ||
| 94 | reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; | ||
| 95 | break; | ||
| 96 | } | ||
| 80 | reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ | 97 | reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ |
| 81 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ | 98 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ |
| 82 | reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */ | ||
| 83 | reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ | 99 | reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ |
| 84 | flowctrl_write_cpu_csr(cpuid, reg); | 100 | flowctrl_write_cpu_csr(cpuid, reg); |
| 85 | 101 | ||
| @@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) | |||
| 99 | 115 | ||
| 100 | /* Disable powergating via flow controller for CPU0 */ | 116 | /* Disable powergating via flow controller for CPU0 */ |
| 101 | reg = flowctrl_read_cpu_csr(cpuid); | 117 | reg = flowctrl_read_cpu_csr(cpuid); |
| 102 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ | 118 | switch (tegra_chip_id) { |
| 103 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ | 119 | case TEGRA20: |
| 120 | /* clear wfe bitmap */ | ||
| 121 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; | ||
| 122 | /* clear wfi bitmap */ | ||
| 123 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; | ||
| 124 | break; | ||
| 125 | case TEGRA30: | ||
| 126 | /* clear wfe bitmap */ | ||
| 127 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | ||
| 128 | /* clear wfi bitmap */ | ||
| 129 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; | ||
| 130 | break; | ||
| 131 | } | ||
| 104 | reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ | 132 | reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ |
| 105 | reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ | 133 | reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ |
| 106 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ | 134 | reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ |
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 0798dec1832d..67eab56699bd 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h | |||
| @@ -34,6 +34,10 @@ | |||
| 34 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 | 34 | #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 |
| 35 | #define FLOW_CTRL_CPU1_CSR 0x18 | 35 | #define FLOW_CTRL_CPU1_CSR 0x18 |
| 36 | 36 | ||
| 37 | #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) | ||
| 38 | #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) | ||
| 39 | #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 | ||
| 40 | |||
| 37 | #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) | 41 | #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) |
| 38 | #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) | 42 | #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) |
| 39 | #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) | 43 | #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) |
