diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-10-21 09:06:54 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-15 16:46:18 -0500 |
commit | adbefaa5fdc6673bf389c00c3448b12d6125990b (patch) | |
tree | abe2ab3a6c25e2f423437b3f2d30670dcf46382a /arch | |
parent | b915a125112b2500d5c6fd752948afc170a49cef (diff) |
[ARM] S3C: Move core clock support to plat-s3c
Move the core clock registration and definitions
in arch/arm/plat-s3c24xx/clock.c to arch/arm/plat-s3c
to be shared with the S3C64XX implementations.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-s3c/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/plat-s3c/clock.c | 356 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/clock.c | 314 |
3 files changed, 357 insertions, 314 deletions
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 3c543ed5fb97..51e7ed5c5c93 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
@@ -13,3 +13,4 @@ obj- := | |||
13 | 13 | ||
14 | obj-y += init.o | 14 | obj-y += init.o |
15 | obj-y += time.o | 15 | obj-y += time.o |
16 | obj-y += clock.o \ No newline at end of file | ||
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c new file mode 100644 index 000000000000..35249b58f383 --- /dev/null +++ b/arch/arm/plat-s3c/clock.c | |||
@@ -0,0 +1,356 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Core clock control support | ||
7 | * | ||
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | ||
9 | ** | ||
10 | ** Copyright (C) 2004 ARM Limited. | ||
11 | ** Written by Deep Blue Solutions Limited. | ||
12 | * | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, write to the Free Software | ||
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
27 | */ | ||
28 | |||
29 | #include <linux/init.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/list.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/err.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/sysdev.h> | ||
37 | #include <linux/interrupt.h> | ||
38 | #include <linux/ioport.h> | ||
39 | #include <linux/clk.h> | ||
40 | #include <linux/spinlock.h> | ||
41 | #include <linux/delay.h> | ||
42 | #include <linux/io.h> | ||
43 | |||
44 | #include <mach/hardware.h> | ||
45 | #include <asm/irq.h> | ||
46 | |||
47 | #include <plat/cpu-freq.h> | ||
48 | |||
49 | #include <plat/clock.h> | ||
50 | #include <plat/cpu.h> | ||
51 | |||
52 | /* clock information */ | ||
53 | |||
54 | static LIST_HEAD(clocks); | ||
55 | |||
56 | /* We originally used an mutex here, but some contexts (see resume) | ||
57 | * are calling functions such as clk_set_parent() with IRQs disabled | ||
58 | * causing an BUG to be triggered. | ||
59 | */ | ||
60 | DEFINE_SPINLOCK(clocks_lock); | ||
61 | |||
62 | /* enable and disable calls for use with the clk struct */ | ||
63 | |||
64 | static int clk_null_enable(struct clk *clk, int enable) | ||
65 | { | ||
66 | return 0; | ||
67 | } | ||
68 | |||
69 | /* Clock API calls */ | ||
70 | |||
71 | struct clk *clk_get(struct device *dev, const char *id) | ||
72 | { | ||
73 | struct clk *p; | ||
74 | struct clk *clk = ERR_PTR(-ENOENT); | ||
75 | int idno; | ||
76 | |||
77 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
78 | idno = -1; | ||
79 | else | ||
80 | idno = to_platform_device(dev)->id; | ||
81 | |||
82 | spin_lock(&clocks_lock); | ||
83 | |||
84 | list_for_each_entry(p, &clocks, list) { | ||
85 | if (p->id == idno && | ||
86 | strcmp(id, p->name) == 0 && | ||
87 | try_module_get(p->owner)) { | ||
88 | clk = p; | ||
89 | break; | ||
90 | } | ||
91 | } | ||
92 | |||
93 | /* check for the case where a device was supplied, but the | ||
94 | * clock that was being searched for is not device specific */ | ||
95 | |||
96 | if (IS_ERR(clk)) { | ||
97 | list_for_each_entry(p, &clocks, list) { | ||
98 | if (p->id == -1 && strcmp(id, p->name) == 0 && | ||
99 | try_module_get(p->owner)) { | ||
100 | clk = p; | ||
101 | break; | ||
102 | } | ||
103 | } | ||
104 | } | ||
105 | |||
106 | spin_unlock(&clocks_lock); | ||
107 | return clk; | ||
108 | } | ||
109 | |||
110 | void clk_put(struct clk *clk) | ||
111 | { | ||
112 | module_put(clk->owner); | ||
113 | } | ||
114 | |||
115 | int clk_enable(struct clk *clk) | ||
116 | { | ||
117 | if (IS_ERR(clk) || clk == NULL) | ||
118 | return -EINVAL; | ||
119 | |||
120 | clk_enable(clk->parent); | ||
121 | |||
122 | spin_lock(&clocks_lock); | ||
123 | |||
124 | if ((clk->usage++) == 0) | ||
125 | (clk->enable)(clk, 1); | ||
126 | |||
127 | spin_unlock(&clocks_lock); | ||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | void clk_disable(struct clk *clk) | ||
132 | { | ||
133 | if (IS_ERR(clk) || clk == NULL) | ||
134 | return; | ||
135 | |||
136 | spin_lock(&clocks_lock); | ||
137 | |||
138 | if ((--clk->usage) == 0) | ||
139 | (clk->enable)(clk, 0); | ||
140 | |||
141 | spin_unlock(&clocks_lock); | ||
142 | clk_disable(clk->parent); | ||
143 | } | ||
144 | |||
145 | |||
146 | unsigned long clk_get_rate(struct clk *clk) | ||
147 | { | ||
148 | if (IS_ERR(clk)) | ||
149 | return 0; | ||
150 | |||
151 | if (clk->rate != 0) | ||
152 | return clk->rate; | ||
153 | |||
154 | if (clk->get_rate != NULL) | ||
155 | return (clk->get_rate)(clk); | ||
156 | |||
157 | if (clk->parent != NULL) | ||
158 | return clk_get_rate(clk->parent); | ||
159 | |||
160 | return clk->rate; | ||
161 | } | ||
162 | |||
163 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
164 | { | ||
165 | if (!IS_ERR(clk) && clk->round_rate) | ||
166 | return (clk->round_rate)(clk, rate); | ||
167 | |||
168 | return rate; | ||
169 | } | ||
170 | |||
171 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
172 | { | ||
173 | int ret; | ||
174 | |||
175 | if (IS_ERR(clk)) | ||
176 | return -EINVAL; | ||
177 | |||
178 | /* We do not default just do a clk->rate = rate as | ||
179 | * the clock may have been made this way by choice. | ||
180 | */ | ||
181 | |||
182 | WARN_ON(clk->set_rate == NULL); | ||
183 | |||
184 | if (clk->set_rate == NULL) | ||
185 | return -EINVAL; | ||
186 | |||
187 | spin_lock(&clocks_lock); | ||
188 | ret = (clk->set_rate)(clk, rate); | ||
189 | spin_unlock(&clocks_lock); | ||
190 | |||
191 | return ret; | ||
192 | } | ||
193 | |||
194 | struct clk *clk_get_parent(struct clk *clk) | ||
195 | { | ||
196 | return clk->parent; | ||
197 | } | ||
198 | |||
199 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
200 | { | ||
201 | int ret = 0; | ||
202 | |||
203 | if (IS_ERR(clk)) | ||
204 | return -EINVAL; | ||
205 | |||
206 | spin_lock(&clocks_lock); | ||
207 | |||
208 | if (clk->set_parent) | ||
209 | ret = (clk->set_parent)(clk, parent); | ||
210 | |||
211 | spin_unlock(&clocks_lock); | ||
212 | |||
213 | return ret; | ||
214 | } | ||
215 | |||
216 | EXPORT_SYMBOL(clk_get); | ||
217 | EXPORT_SYMBOL(clk_put); | ||
218 | EXPORT_SYMBOL(clk_enable); | ||
219 | EXPORT_SYMBOL(clk_disable); | ||
220 | EXPORT_SYMBOL(clk_get_rate); | ||
221 | EXPORT_SYMBOL(clk_round_rate); | ||
222 | EXPORT_SYMBOL(clk_set_rate); | ||
223 | EXPORT_SYMBOL(clk_get_parent); | ||
224 | EXPORT_SYMBOL(clk_set_parent); | ||
225 | |||
226 | /* base clocks */ | ||
227 | |||
228 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
229 | { | ||
230 | clk->rate = rate; | ||
231 | return 0; | ||
232 | } | ||
233 | |||
234 | struct clk clk_xtal = { | ||
235 | .name = "xtal", | ||
236 | .id = -1, | ||
237 | .rate = 0, | ||
238 | .parent = NULL, | ||
239 | .ctrlbit = 0, | ||
240 | }; | ||
241 | |||
242 | struct clk clk_mpll = { | ||
243 | .name = "mpll", | ||
244 | .id = -1, | ||
245 | .set_rate = clk_default_setrate, | ||
246 | }; | ||
247 | |||
248 | struct clk clk_upll = { | ||
249 | .name = "upll", | ||
250 | .id = -1, | ||
251 | .parent = NULL, | ||
252 | .ctrlbit = 0, | ||
253 | }; | ||
254 | |||
255 | struct clk clk_f = { | ||
256 | .name = "fclk", | ||
257 | .id = -1, | ||
258 | .rate = 0, | ||
259 | .parent = &clk_mpll, | ||
260 | .ctrlbit = 0, | ||
261 | .set_rate = clk_default_setrate, | ||
262 | }; | ||
263 | |||
264 | struct clk clk_h = { | ||
265 | .name = "hclk", | ||
266 | .id = -1, | ||
267 | .rate = 0, | ||
268 | .parent = NULL, | ||
269 | .ctrlbit = 0, | ||
270 | .set_rate = clk_default_setrate, | ||
271 | }; | ||
272 | |||
273 | struct clk clk_p = { | ||
274 | .name = "pclk", | ||
275 | .id = -1, | ||
276 | .rate = 0, | ||
277 | .parent = NULL, | ||
278 | .ctrlbit = 0, | ||
279 | .set_rate = clk_default_setrate, | ||
280 | }; | ||
281 | |||
282 | struct clk clk_usb_bus = { | ||
283 | .name = "usb-bus", | ||
284 | .id = -1, | ||
285 | .rate = 0, | ||
286 | .parent = &clk_upll, | ||
287 | }; | ||
288 | |||
289 | |||
290 | |||
291 | struct clk s3c24xx_uclk = { | ||
292 | .name = "uclk", | ||
293 | .id = -1, | ||
294 | }; | ||
295 | |||
296 | /* initialise the clock system */ | ||
297 | |||
298 | int s3c24xx_register_clock(struct clk *clk) | ||
299 | { | ||
300 | clk->owner = THIS_MODULE; | ||
301 | |||
302 | if (clk->enable == NULL) | ||
303 | clk->enable = clk_null_enable; | ||
304 | |||
305 | /* add to the list of available clocks */ | ||
306 | |||
307 | spin_lock(&clocks_lock); | ||
308 | list_add(&clk->list, &clocks); | ||
309 | spin_unlock(&clocks_lock); | ||
310 | |||
311 | return 0; | ||
312 | } | ||
313 | |||
314 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | ||
315 | { | ||
316 | int fails = 0; | ||
317 | |||
318 | for (; nr_clks > 0; nr_clks--, clks++) { | ||
319 | if (s3c24xx_register_clock(*clks) < 0) | ||
320 | fails++; | ||
321 | } | ||
322 | |||
323 | return fails; | ||
324 | } | ||
325 | |||
326 | /* initalise all the clocks */ | ||
327 | |||
328 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | ||
329 | { | ||
330 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | ||
331 | |||
332 | clk_xtal.rate = xtal; | ||
333 | |||
334 | /* register our clocks */ | ||
335 | |||
336 | if (s3c24xx_register_clock(&clk_xtal) < 0) | ||
337 | printk(KERN_ERR "failed to register master xtal\n"); | ||
338 | |||
339 | if (s3c24xx_register_clock(&clk_mpll) < 0) | ||
340 | printk(KERN_ERR "failed to register mpll clock\n"); | ||
341 | |||
342 | if (s3c24xx_register_clock(&clk_upll) < 0) | ||
343 | printk(KERN_ERR "failed to register upll clock\n"); | ||
344 | |||
345 | if (s3c24xx_register_clock(&clk_f) < 0) | ||
346 | printk(KERN_ERR "failed to register cpu fclk\n"); | ||
347 | |||
348 | if (s3c24xx_register_clock(&clk_h) < 0) | ||
349 | printk(KERN_ERR "failed to register cpu hclk\n"); | ||
350 | |||
351 | if (s3c24xx_register_clock(&clk_p) < 0) | ||
352 | printk(KERN_ERR "failed to register cpu pclk\n"); | ||
353 | |||
354 | return 0; | ||
355 | } | ||
356 | |||
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index a4a0a67a3074..8474d05274bd 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
@@ -27,18 +27,8 @@ | |||
27 | */ | 27 | */ |
28 | 28 | ||
29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | 30 | #include <linux/kernel.h> |
32 | #include <linux/list.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/err.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/sysdev.h> | ||
37 | #include <linux/interrupt.h> | ||
38 | #include <linux/ioport.h> | ||
39 | #include <linux/clk.h> | 31 | #include <linux/clk.h> |
40 | #include <linux/spinlock.h> | ||
41 | #include <linux/delay.h> | ||
42 | #include <linux/io.h> | 32 | #include <linux/io.h> |
43 | 33 | ||
44 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
@@ -53,280 +43,6 @@ | |||
53 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
54 | #include <plat/pll.h> | 44 | #include <plat/pll.h> |
55 | 45 | ||
56 | /* clock information */ | ||
57 | |||
58 | static LIST_HEAD(clocks); | ||
59 | |||
60 | /* We originally used an mutex here, but some contexts (see resume) | ||
61 | * are calling functions such as clk_set_parent() with IRQs disabled | ||
62 | * causing an BUG to be triggered. | ||
63 | */ | ||
64 | DEFINE_SPINLOCK(clocks_lock); | ||
65 | |||
66 | /* enable and disable calls for use with the clk struct */ | ||
67 | |||
68 | static int clk_null_enable(struct clk *clk, int enable) | ||
69 | { | ||
70 | return 0; | ||
71 | } | ||
72 | |||
73 | /* Clock API calls */ | ||
74 | |||
75 | struct clk *clk_get(struct device *dev, const char *id) | ||
76 | { | ||
77 | struct clk *p; | ||
78 | struct clk *clk = ERR_PTR(-ENOENT); | ||
79 | int idno; | ||
80 | |||
81 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
82 | idno = -1; | ||
83 | else | ||
84 | idno = to_platform_device(dev)->id; | ||
85 | |||
86 | spin_lock(&clocks_lock); | ||
87 | |||
88 | list_for_each_entry(p, &clocks, list) { | ||
89 | if (p->id == idno && | ||
90 | strcmp(id, p->name) == 0 && | ||
91 | try_module_get(p->owner)) { | ||
92 | clk = p; | ||
93 | break; | ||
94 | } | ||
95 | } | ||
96 | |||
97 | /* check for the case where a device was supplied, but the | ||
98 | * clock that was being searched for is not device specific */ | ||
99 | |||
100 | if (IS_ERR(clk)) { | ||
101 | list_for_each_entry(p, &clocks, list) { | ||
102 | if (p->id == -1 && strcmp(id, p->name) == 0 && | ||
103 | try_module_get(p->owner)) { | ||
104 | clk = p; | ||
105 | break; | ||
106 | } | ||
107 | } | ||
108 | } | ||
109 | |||
110 | spin_unlock(&clocks_lock); | ||
111 | return clk; | ||
112 | } | ||
113 | |||
114 | void clk_put(struct clk *clk) | ||
115 | { | ||
116 | module_put(clk->owner); | ||
117 | } | ||
118 | |||
119 | int clk_enable(struct clk *clk) | ||
120 | { | ||
121 | if (IS_ERR(clk) || clk == NULL) | ||
122 | return -EINVAL; | ||
123 | |||
124 | clk_enable(clk->parent); | ||
125 | |||
126 | spin_lock(&clocks_lock); | ||
127 | |||
128 | if ((clk->usage++) == 0) | ||
129 | (clk->enable)(clk, 1); | ||
130 | |||
131 | spin_unlock(&clocks_lock); | ||
132 | return 0; | ||
133 | } | ||
134 | |||
135 | void clk_disable(struct clk *clk) | ||
136 | { | ||
137 | if (IS_ERR(clk) || clk == NULL) | ||
138 | return; | ||
139 | |||
140 | spin_lock(&clocks_lock); | ||
141 | |||
142 | if ((--clk->usage) == 0) | ||
143 | (clk->enable)(clk, 0); | ||
144 | |||
145 | spin_unlock(&clocks_lock); | ||
146 | clk_disable(clk->parent); | ||
147 | } | ||
148 | |||
149 | |||
150 | unsigned long clk_get_rate(struct clk *clk) | ||
151 | { | ||
152 | if (IS_ERR(clk)) | ||
153 | return 0; | ||
154 | |||
155 | if (clk->rate != 0) | ||
156 | return clk->rate; | ||
157 | |||
158 | if (clk->get_rate != NULL) | ||
159 | return (clk->get_rate)(clk); | ||
160 | |||
161 | if (clk->parent != NULL) | ||
162 | return clk_get_rate(clk->parent); | ||
163 | |||
164 | return clk->rate; | ||
165 | } | ||
166 | |||
167 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
168 | { | ||
169 | if (!IS_ERR(clk) && clk->round_rate) | ||
170 | return (clk->round_rate)(clk, rate); | ||
171 | |||
172 | return rate; | ||
173 | } | ||
174 | |||
175 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
176 | { | ||
177 | int ret; | ||
178 | |||
179 | if (IS_ERR(clk)) | ||
180 | return -EINVAL; | ||
181 | |||
182 | /* We do not default just do a clk->rate = rate as | ||
183 | * the clock may have been made this way by choice. | ||
184 | */ | ||
185 | |||
186 | WARN_ON(clk->set_rate == NULL); | ||
187 | |||
188 | if (clk->set_rate == NULL) | ||
189 | return -EINVAL; | ||
190 | |||
191 | spin_lock(&clocks_lock); | ||
192 | ret = (clk->set_rate)(clk, rate); | ||
193 | spin_unlock(&clocks_lock); | ||
194 | |||
195 | return ret; | ||
196 | } | ||
197 | |||
198 | struct clk *clk_get_parent(struct clk *clk) | ||
199 | { | ||
200 | return clk->parent; | ||
201 | } | ||
202 | |||
203 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
204 | { | ||
205 | int ret = 0; | ||
206 | |||
207 | if (IS_ERR(clk)) | ||
208 | return -EINVAL; | ||
209 | |||
210 | spin_lock(&clocks_lock); | ||
211 | |||
212 | if (clk->set_parent) | ||
213 | ret = (clk->set_parent)(clk, parent); | ||
214 | |||
215 | spin_unlock(&clocks_lock); | ||
216 | |||
217 | return ret; | ||
218 | } | ||
219 | |||
220 | EXPORT_SYMBOL(clk_get); | ||
221 | EXPORT_SYMBOL(clk_put); | ||
222 | EXPORT_SYMBOL(clk_enable); | ||
223 | EXPORT_SYMBOL(clk_disable); | ||
224 | EXPORT_SYMBOL(clk_get_rate); | ||
225 | EXPORT_SYMBOL(clk_round_rate); | ||
226 | EXPORT_SYMBOL(clk_set_rate); | ||
227 | EXPORT_SYMBOL(clk_get_parent); | ||
228 | EXPORT_SYMBOL(clk_set_parent); | ||
229 | |||
230 | /* base clocks */ | ||
231 | |||
232 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
233 | { | ||
234 | clk->rate = rate; | ||
235 | return 0; | ||
236 | } | ||
237 | |||
238 | struct clk clk_xtal = { | ||
239 | .name = "xtal", | ||
240 | .id = -1, | ||
241 | .rate = 0, | ||
242 | .parent = NULL, | ||
243 | .ctrlbit = 0, | ||
244 | }; | ||
245 | |||
246 | struct clk clk_mpll = { | ||
247 | .name = "mpll", | ||
248 | .id = -1, | ||
249 | .set_rate = clk_default_setrate, | ||
250 | }; | ||
251 | |||
252 | struct clk clk_upll = { | ||
253 | .name = "upll", | ||
254 | .id = -1, | ||
255 | .parent = NULL, | ||
256 | .ctrlbit = 0, | ||
257 | }; | ||
258 | |||
259 | struct clk clk_f = { | ||
260 | .name = "fclk", | ||
261 | .id = -1, | ||
262 | .rate = 0, | ||
263 | .parent = &clk_mpll, | ||
264 | .ctrlbit = 0, | ||
265 | .set_rate = clk_default_setrate, | ||
266 | }; | ||
267 | |||
268 | struct clk clk_h = { | ||
269 | .name = "hclk", | ||
270 | .id = -1, | ||
271 | .rate = 0, | ||
272 | .parent = NULL, | ||
273 | .ctrlbit = 0, | ||
274 | .set_rate = clk_default_setrate, | ||
275 | }; | ||
276 | |||
277 | struct clk clk_p = { | ||
278 | .name = "pclk", | ||
279 | .id = -1, | ||
280 | .rate = 0, | ||
281 | .parent = NULL, | ||
282 | .ctrlbit = 0, | ||
283 | .set_rate = clk_default_setrate, | ||
284 | }; | ||
285 | |||
286 | struct clk clk_usb_bus = { | ||
287 | .name = "usb-bus", | ||
288 | .id = -1, | ||
289 | .rate = 0, | ||
290 | .parent = &clk_upll, | ||
291 | }; | ||
292 | |||
293 | |||
294 | |||
295 | struct clk s3c24xx_uclk = { | ||
296 | .name = "uclk", | ||
297 | .id = -1, | ||
298 | }; | ||
299 | |||
300 | /* initialise the clock system */ | ||
301 | |||
302 | int s3c24xx_register_clock(struct clk *clk) | ||
303 | { | ||
304 | clk->owner = THIS_MODULE; | ||
305 | |||
306 | if (clk->enable == NULL) | ||
307 | clk->enable = clk_null_enable; | ||
308 | |||
309 | /* add to the list of available clocks */ | ||
310 | |||
311 | spin_lock(&clocks_lock); | ||
312 | list_add(&clk->list, &clocks); | ||
313 | spin_unlock(&clocks_lock); | ||
314 | |||
315 | return 0; | ||
316 | } | ||
317 | |||
318 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | ||
319 | { | ||
320 | int fails = 0; | ||
321 | |||
322 | for (; nr_clks > 0; nr_clks--, clks++) { | ||
323 | if (s3c24xx_register_clock(*clks) < 0) | ||
324 | fails++; | ||
325 | } | ||
326 | |||
327 | return fails; | ||
328 | } | ||
329 | |||
330 | /* initalise all the clocks */ | 46 | /* initalise all the clocks */ |
331 | 47 | ||
332 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, | 48 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, |
@@ -341,33 +57,3 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, | |||
341 | clk_p.rate = pclk; | 57 | clk_p.rate = pclk; |
342 | clk_f.rate = fclk; | 58 | clk_f.rate = fclk; |
343 | } | 59 | } |
344 | |||
345 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | ||
346 | { | ||
347 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | ||
348 | |||
349 | clk_xtal.rate = xtal; | ||
350 | |||
351 | /* register our clocks */ | ||
352 | |||
353 | if (s3c24xx_register_clock(&clk_xtal) < 0) | ||
354 | printk(KERN_ERR "failed to register master xtal\n"); | ||
355 | |||
356 | if (s3c24xx_register_clock(&clk_mpll) < 0) | ||
357 | printk(KERN_ERR "failed to register mpll clock\n"); | ||
358 | |||
359 | if (s3c24xx_register_clock(&clk_upll) < 0) | ||
360 | printk(KERN_ERR "failed to register upll clock\n"); | ||
361 | |||
362 | if (s3c24xx_register_clock(&clk_f) < 0) | ||
363 | printk(KERN_ERR "failed to register cpu fclk\n"); | ||
364 | |||
365 | if (s3c24xx_register_clock(&clk_h) < 0) | ||
366 | printk(KERN_ERR "failed to register cpu hclk\n"); | ||
367 | |||
368 | if (s3c24xx_register_clock(&clk_p) < 0) | ||
369 | printk(KERN_ERR "failed to register cpu pclk\n"); | ||
370 | |||
371 | return 0; | ||
372 | } | ||
373 | |||