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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 15:57:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 15:57:01 -0400
commita947e23a8ec04bccbfe98c5a2d64cd1f88b612d5 (patch)
treed64bfae3af141014e93b32036ee8cb3202655ecc /arch
parent08a8b79600101fd6e13dcf05409b330e7f5b0478 (diff)
parent9a3865b185e77d1a4ca2d8356e37c19b78168961 (diff)
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, asm: Clean up desc.h a bit x86, amd: Do not enable ARAT feature on AMD processors below family 0x12 x86: Move do_page_fault()'s error path under unlikely() x86, efi: Retain boot service code until after switching to virtual mode x86: Remove unnecessary check in detect_ht() x86: Reorder mm_context_t to remove x86_64 alignment padding and thus shrink mm_struct x86, UV: Clean up uv_tlb.c x86, UV: Add support for SGI UV2 hub chip x86, cpufeature: Update CPU feature RDRND to RDRAND
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/cpufeature.h2
-rw-r--r--arch/x86/include/asm/desc.h152
-rw-r--r--arch/x86/include/asm/mmu.h4
-rw-r--r--arch/x86/include/asm/uv/uv_bau.h590
-rw-r--r--arch/x86/include/asm/uv/uv_hub.h71
-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h1012
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c40
-rw-r--r--arch/x86/kernel/cpu/amd.c7
-rw-r--r--arch/x86/kernel/cpu/common.c7
-rw-r--r--arch/x86/kernel/setup.c7
-rw-r--r--arch/x86/mm/fault.c35
-rw-r--r--arch/x86/platform/efi/efi.c45
-rw-r--r--arch/x86/platform/efi/efi_64.c5
-rw-r--r--arch/x86/platform/uv/tlb_uv.c1484
-rw-r--r--arch/x86/platform/uv/uv_time.c16
15 files changed, 2283 insertions, 1194 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5dc6acc98dbd..71cc3800712c 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -125,7 +125,7 @@
125#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ 125#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
126#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 126#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
127#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ 127#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
128#define X86_FEATURE_RDRND (4*32+30) /* The RDRAND instruction */ 128#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
129#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ 129#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
130 130
131/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 131/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 617bd56b3070..7b439d9aea2a 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -4,30 +4,33 @@
4#include <asm/desc_defs.h> 4#include <asm/desc_defs.h>
5#include <asm/ldt.h> 5#include <asm/ldt.h>
6#include <asm/mmu.h> 6#include <asm/mmu.h>
7
7#include <linux/smp.h> 8#include <linux/smp.h>
8 9
9static inline void fill_ldt(struct desc_struct *desc, 10static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
10 const struct user_desc *info) 11{
11{ 12 desc->limit0 = info->limit & 0x0ffff;
12 desc->limit0 = info->limit & 0x0ffff; 13
13 desc->base0 = info->base_addr & 0x0000ffff; 14 desc->base0 = (info->base_addr & 0x0000ffff);
14 15 desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
15 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 16
16 desc->type = (info->read_exec_only ^ 1) << 1; 17 desc->type = (info->read_exec_only ^ 1) << 1;
17 desc->type |= info->contents << 2; 18 desc->type |= info->contents << 2;
18 desc->s = 1; 19
19 desc->dpl = 0x3; 20 desc->s = 1;
20 desc->p = info->seg_not_present ^ 1; 21 desc->dpl = 0x3;
21 desc->limit = (info->limit & 0xf0000) >> 16; 22 desc->p = info->seg_not_present ^ 1;
22 desc->avl = info->useable; 23 desc->limit = (info->limit & 0xf0000) >> 16;
23 desc->d = info->seg_32bit; 24 desc->avl = info->useable;
24 desc->g = info->limit_in_pages; 25 desc->d = info->seg_32bit;
25 desc->base2 = (info->base_addr & 0xff000000) >> 24; 26 desc->g = info->limit_in_pages;
27
28 desc->base2 = (info->base_addr & 0xff000000) >> 24;
26 /* 29 /*
27 * Don't allow setting of the lm bit. It is useless anyway 30 * Don't allow setting of the lm bit. It is useless anyway
28 * because 64bit system calls require __USER_CS: 31 * because 64bit system calls require __USER_CS:
29 */ 32 */
30 desc->l = 0; 33 desc->l = 0;
31} 34}
32 35
33extern struct desc_ptr idt_descr; 36extern struct desc_ptr idt_descr;
@@ -36,6 +39,7 @@ extern gate_desc idt_table[];
36struct gdt_page { 39struct gdt_page {
37 struct desc_struct gdt[GDT_ENTRIES]; 40 struct desc_struct gdt[GDT_ENTRIES];
38} __attribute__((aligned(PAGE_SIZE))); 41} __attribute__((aligned(PAGE_SIZE)));
42
39DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 43DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
40 44
41static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) 45static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
@@ -48,16 +52,16 @@ static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
48static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 52static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
49 unsigned dpl, unsigned ist, unsigned seg) 53 unsigned dpl, unsigned ist, unsigned seg)
50{ 54{
51 gate->offset_low = PTR_LOW(func); 55 gate->offset_low = PTR_LOW(func);
52 gate->segment = __KERNEL_CS; 56 gate->segment = __KERNEL_CS;
53 gate->ist = ist; 57 gate->ist = ist;
54 gate->p = 1; 58 gate->p = 1;
55 gate->dpl = dpl; 59 gate->dpl = dpl;
56 gate->zero0 = 0; 60 gate->zero0 = 0;
57 gate->zero1 = 0; 61 gate->zero1 = 0;
58 gate->type = type; 62 gate->type = type;
59 gate->offset_middle = PTR_MIDDLE(func); 63 gate->offset_middle = PTR_MIDDLE(func);
60 gate->offset_high = PTR_HIGH(func); 64 gate->offset_high = PTR_HIGH(func);
61} 65}
62 66
63#else 67#else
@@ -66,8 +70,7 @@ static inline void pack_gate(gate_desc *gate, unsigned char type,
66 unsigned short seg) 70 unsigned short seg)
67{ 71{
68 gate->a = (seg << 16) | (base & 0xffff); 72 gate->a = (seg << 16) | (base & 0xffff);
69 gate->b = (base & 0xffff0000) | 73 gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
70 (((0x80 | type | (dpl << 5)) & 0xff) << 8);
71} 74}
72 75
73#endif 76#endif
@@ -75,31 +78,29 @@ static inline void pack_gate(gate_desc *gate, unsigned char type,
75static inline int desc_empty(const void *ptr) 78static inline int desc_empty(const void *ptr)
76{ 79{
77 const u32 *desc = ptr; 80 const u32 *desc = ptr;
81
78 return !(desc[0] | desc[1]); 82 return !(desc[0] | desc[1]);
79} 83}
80 84
81#ifdef CONFIG_PARAVIRT 85#ifdef CONFIG_PARAVIRT
82#include <asm/paravirt.h> 86#include <asm/paravirt.h>
83#else 87#else
84#define load_TR_desc() native_load_tr_desc() 88#define load_TR_desc() native_load_tr_desc()
85#define load_gdt(dtr) native_load_gdt(dtr) 89#define load_gdt(dtr) native_load_gdt(dtr)
86#define load_idt(dtr) native_load_idt(dtr) 90#define load_idt(dtr) native_load_idt(dtr)
87#define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 91#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
88#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 92#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
89 93
90#define store_gdt(dtr) native_store_gdt(dtr) 94#define store_gdt(dtr) native_store_gdt(dtr)
91#define store_idt(dtr) native_store_idt(dtr) 95#define store_idt(dtr) native_store_idt(dtr)
92#define store_tr(tr) (tr = native_store_tr()) 96#define store_tr(tr) (tr = native_store_tr())
93 97
94#define load_TLS(t, cpu) native_load_tls(t, cpu) 98#define load_TLS(t, cpu) native_load_tls(t, cpu)
95#define set_ldt native_set_ldt 99#define set_ldt native_set_ldt
96 100
97#define write_ldt_entry(dt, entry, desc) \ 101#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
98 native_write_ldt_entry(dt, entry, desc) 102#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
99#define write_gdt_entry(dt, entry, desc, type) \ 103#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
100 native_write_gdt_entry(dt, entry, desc, type)
101#define write_idt_entry(dt, entry, g) \
102 native_write_idt_entry(dt, entry, g)
103 104
104static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 105static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
105{ 106{
@@ -112,33 +113,27 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
112 113
113#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 114#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
114 115
115static inline void native_write_idt_entry(gate_desc *idt, int entry, 116static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
116 const gate_desc *gate)
117{ 117{
118 memcpy(&idt[entry], gate, sizeof(*gate)); 118 memcpy(&idt[entry], gate, sizeof(*gate));
119} 119}
120 120
121static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, 121static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
122 const void *desc)
123{ 122{
124 memcpy(&ldt[entry], desc, 8); 123 memcpy(&ldt[entry], desc, 8);
125} 124}
126 125
127static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry, 126static inline void
128 const void *desc, int type) 127native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
129{ 128{
130 unsigned int size; 129 unsigned int size;
130
131 switch (type) { 131 switch (type) {
132 case DESC_TSS: 132 case DESC_TSS: size = sizeof(tss_desc); break;
133 size = sizeof(tss_desc); 133 case DESC_LDT: size = sizeof(ldt_desc); break;
134 break; 134 default: size = sizeof(*gdt); break;
135 case DESC_LDT:
136 size = sizeof(ldt_desc);
137 break;
138 default:
139 size = sizeof(struct desc_struct);
140 break;
141 } 135 }
136
142 memcpy(&gdt[entry], desc, size); 137 memcpy(&gdt[entry], desc, size);
143} 138}
144 139
@@ -154,20 +149,21 @@ static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
154} 149}
155 150
156 151
157static inline void set_tssldt_descriptor(void *d, unsigned long addr, 152static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
158 unsigned type, unsigned size)
159{ 153{
160#ifdef CONFIG_X86_64 154#ifdef CONFIG_X86_64
161 struct ldttss_desc64 *desc = d; 155 struct ldttss_desc64 *desc = d;
156
162 memset(desc, 0, sizeof(*desc)); 157 memset(desc, 0, sizeof(*desc));
163 desc->limit0 = size & 0xFFFF; 158
164 desc->base0 = PTR_LOW(addr); 159 desc->limit0 = size & 0xFFFF;
165 desc->base1 = PTR_MIDDLE(addr) & 0xFF; 160 desc->base0 = PTR_LOW(addr);
166 desc->type = type; 161 desc->base1 = PTR_MIDDLE(addr) & 0xFF;
167 desc->p = 1; 162 desc->type = type;
168 desc->limit1 = (size >> 16) & 0xF; 163 desc->p = 1;
169 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 164 desc->limit1 = (size >> 16) & 0xF;
170 desc->base3 = PTR_HIGH(addr); 165 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
166 desc->base3 = PTR_HIGH(addr);
171#else 167#else
172 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); 168 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
173#endif 169#endif
@@ -237,14 +233,16 @@ static inline void native_store_idt(struct desc_ptr *dtr)
237static inline unsigned long native_store_tr(void) 233static inline unsigned long native_store_tr(void)
238{ 234{
239 unsigned long tr; 235 unsigned long tr;
236
240 asm volatile("str %0":"=r" (tr)); 237 asm volatile("str %0":"=r" (tr));
238
241 return tr; 239 return tr;
242} 240}
243 241
244static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 242static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
245{ 243{
246 unsigned int i;
247 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 244 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
245 unsigned int i;
248 246
249 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 247 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
250 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 248 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
@@ -313,6 +311,7 @@ static inline void _set_gate(int gate, unsigned type, void *addr,
313 unsigned dpl, unsigned ist, unsigned seg) 311 unsigned dpl, unsigned ist, unsigned seg)
314{ 312{
315 gate_desc s; 313 gate_desc s;
314
316 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); 315 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
317 /* 316 /*
318 * does not need to be atomic because it is only done once at 317 * does not need to be atomic because it is only done once at
@@ -343,8 +342,9 @@ static inline void alloc_system_vector(int vector)
343 set_bit(vector, used_vectors); 342 set_bit(vector, used_vectors);
344 if (first_system_vector > vector) 343 if (first_system_vector > vector)
345 first_system_vector = vector; 344 first_system_vector = vector;
346 } else 345 } else {
347 BUG(); 346 BUG();
347 }
348} 348}
349 349
350static inline void alloc_intr_gate(unsigned int n, void *addr) 350static inline void alloc_intr_gate(unsigned int n, void *addr)
diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h
index aeff3e89b222..5f55e6962769 100644
--- a/arch/x86/include/asm/mmu.h
+++ b/arch/x86/include/asm/mmu.h
@@ -11,14 +11,14 @@
11typedef struct { 11typedef struct {
12 void *ldt; 12 void *ldt;
13 int size; 13 int size;
14 struct mutex lock;
15 void *vdso;
16 14
17#ifdef CONFIG_X86_64 15#ifdef CONFIG_X86_64
18 /* True if mm supports a task running in 32 bit compatibility mode. */ 16 /* True if mm supports a task running in 32 bit compatibility mode. */
19 unsigned short ia32_compat; 17 unsigned short ia32_compat;
20#endif 18#endif
21 19
20 struct mutex lock;
21 void *vdso;
22} mm_context_t; 22} mm_context_t;
23 23
24#ifdef CONFIG_SMP 24#ifdef CONFIG_SMP
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 130f1eeee5fe..a291c40efd43 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * SGI UV Broadcast Assist Unit definitions 6 * SGI UV Broadcast Assist Unit definitions
7 * 7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. 8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */ 9 */
10 10
11#ifndef _ASM_X86_UV_UV_BAU_H 11#ifndef _ASM_X86_UV_UV_BAU_H
@@ -35,17 +35,20 @@
35 35
36#define MAX_CPUS_PER_UVHUB 64 36#define MAX_CPUS_PER_UVHUB 64
37#define MAX_CPUS_PER_SOCKET 32 37#define MAX_CPUS_PER_SOCKET 32
38#define UV_ADP_SIZE 64 /* hardware-provided max. */ 38#define ADP_SZ 64 /* hardware-provided max. */
39#define UV_CPUS_PER_ACT_STATUS 32 /* hardware-provided max. */ 39#define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40#define UV_ITEMS_PER_DESCRIPTOR 8 40#define ITEMS_PER_DESC 8
41/* the 'throttle' to prevent the hardware stay-busy bug */ 41/* the 'throttle' to prevent the hardware stay-busy bug */
42#define MAX_BAU_CONCURRENT 3 42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3 43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2 44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256 45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8 46#define UV_SW_ACK_NPENDING 8
47#define UV_NET_ENDPOINT_INTD 0x38 47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV_DESC_BASE_PNODE_SHIFT 49 48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
49#define UV_PAYLOADQ_PNODE_SHIFT 49 52#define UV_PAYLOADQ_PNODE_SHIFT 49
50#define UV_PTC_BASENAME "sgi_uv/ptc_statistics" 53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
51#define UV_BAU_BASENAME "sgi_uv/bau_tunables" 54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
@@ -53,29 +56,64 @@
53#define UV_BAU_TUNABLES_FILE "bau_tunables" 56#define UV_BAU_TUNABLES_FILE "bau_tunables"
54#define WHITESPACE " \t\n" 57#define WHITESPACE " \t\n"
55#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask)) 58#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
56#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15 59#define cpubit_isset(cpu, bau_local_cpumask) \
57#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16 60 test_bit((cpu), (bau_local_cpumask).bits)
58#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x0000000009UL 61
59/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */ 62/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
60#define BAU_MISC_CONTROL_MULT_MASK 3 63/*
64 * UV2: Bit 19 selects between
65 * (0): 10 microsecond timebase and
66 * (1): 80 microseconds
67 * we're using 655us, similar to UV1: 65 units of 10us
68 */
69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)
71
72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
74 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
61 75
62#define UVH_AGING_PRESCALE_SEL 0x000000b000UL 76#define BAU_MISC_CONTROL_MULT_MASK 3
77
78#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
63/* [30:28] URGENCY_7 an index into a table of times */ 79/* [30:28] URGENCY_7 an index into a table of times */
64#define BAU_URGENCY_7_SHIFT 28 80#define BAU_URGENCY_7_SHIFT 28
65#define BAU_URGENCY_7_MASK 7 81#define BAU_URGENCY_7_MASK 7
66 82
67#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL 83#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
68/* [45:40] BAU - BAU transaction timeout select - a multiplier */ 84/* [45:40] BAU - BAU transaction timeout select - a multiplier */
69#define BAU_TRANS_SHIFT 40 85#define BAU_TRANS_SHIFT 40
70#define BAU_TRANS_MASK 0x3f 86#define BAU_TRANS_MASK 0x3f
87
88/*
89 * shorten some awkward names
90 */
91#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
92#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
93#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
94#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
95#define write_gmmr uv_write_global_mmr64
96#define write_lmmr uv_write_local_mmr
97#define read_lmmr uv_read_local_mmr
98#define read_gmmr uv_read_global_mmr64
71 99
72/* 100/*
73 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1 101 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
74 */ 102 */
75#define DESC_STATUS_IDLE 0 103#define DS_IDLE 0
76#define DESC_STATUS_ACTIVE 1 104#define DS_ACTIVE 1
77#define DESC_STATUS_DESTINATION_TIMEOUT 2 105#define DS_DESTINATION_TIMEOUT 2
78#define DESC_STATUS_SOURCE_TIMEOUT 3 106#define DS_SOURCE_TIMEOUT 3
107/*
108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
109 * values 1 and 5 will not occur
110 */
111#define UV2H_DESC_IDLE 0
112#define UV2H_DESC_DEST_TIMEOUT 2
113#define UV2H_DESC_DEST_STRONG_NACK 3
114#define UV2H_DESC_BUSY 4
115#define UV2H_DESC_SOURCE_TIMEOUT 6
116#define UV2H_DESC_DEST_PUT_ERR 7
79 117
80/* 118/*
81 * delay for 'plugged' timeout retries, in microseconds 119 * delay for 'plugged' timeout retries, in microseconds
@@ -86,15 +124,24 @@
86 * threshholds at which to use IPI to free resources 124 * threshholds at which to use IPI to free resources
87 */ 125 */
88/* after this # consecutive 'plugged' timeouts, use IPI to release resources */ 126/* after this # consecutive 'plugged' timeouts, use IPI to release resources */
89#define PLUGSB4RESET 100 127#define PLUGSB4RESET 100
90/* after this many consecutive timeouts, use IPI to release resources */ 128/* after this many consecutive timeouts, use IPI to release resources */
91#define TIMEOUTSB4RESET 1 129#define TIMEOUTSB4RESET 1
92/* at this number uses of IPI to release resources, giveup the request */ 130/* at this number uses of IPI to release resources, giveup the request */
93#define IPI_RESET_LIMIT 1 131#define IPI_RESET_LIMIT 1
94/* after this # consecutive successes, bump up the throttle if it was lowered */ 132/* after this # consecutive successes, bump up the throttle if it was lowered */
95#define COMPLETE_THRESHOLD 5 133#define COMPLETE_THRESHOLD 5
134
135#define UV_LB_SUBNODEID 0x10
96 136
97#define UV_LB_SUBNODEID 0x10 137/* these two are the same for UV1 and UV2: */
138#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
139#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
140/* 4 bits of software ack period */
141#define UV2_ACK_MASK 0x7UL
142#define UV2_ACK_UNITS_SHFT 3
143#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
144#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
98 145
99/* 146/*
100 * number of entries in the destination side payload queue 147 * number of entries in the destination side payload queue
@@ -115,9 +162,16 @@
115/* 162/*
116 * tuning the action when the numalink network is extremely delayed 163 * tuning the action when the numalink network is extremely delayed
117 */ 164 */
118#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in microseconds */ 165#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
119#define CONGESTED_REPS 10 /* long delays averaged over this many broadcasts */ 166 microseconds */
120#define CONGESTED_PERIOD 30 /* time for the bau to be disabled, in seconds */ 167#define CONGESTED_REPS 10 /* long delays averaged over
168 this many broadcasts */
169#define CONGESTED_PERIOD 30 /* time for the bau to be
170 disabled, in seconds */
171/* see msg_type: */
172#define MSG_NOOP 0
173#define MSG_REGULAR 1
174#define MSG_RETRY 2
121 175
122/* 176/*
123 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor) 177 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
@@ -129,8 +183,8 @@
129 * 'base_dest_nasid' field of the header corresponds to the 183 * 'base_dest_nasid' field of the header corresponds to the
130 * destination nodeID associated with that specified bit. 184 * destination nodeID associated with that specified bit.
131 */ 185 */
132struct bau_target_uvhubmask { 186struct bau_targ_hubmask {
133 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 187 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
134}; 188};
135 189
136/* 190/*
@@ -139,7 +193,7 @@ struct bau_target_uvhubmask {
139 * enough bits for max. cpu's per uvhub) 193 * enough bits for max. cpu's per uvhub)
140 */ 194 */
141struct bau_local_cpumask { 195struct bau_local_cpumask {
142 unsigned long bits; 196 unsigned long bits;
143}; 197};
144 198
145/* 199/*
@@ -160,14 +214,14 @@ struct bau_local_cpumask {
160 * The payload is software-defined for INTD transactions 214 * The payload is software-defined for INTD transactions
161 */ 215 */
162struct bau_msg_payload { 216struct bau_msg_payload {
163 unsigned long address; /* signifies a page or all TLB's 217 unsigned long address; /* signifies a page or all
164 of the cpu */ 218 TLB's of the cpu */
165 /* 64 bits */ 219 /* 64 bits */
166 unsigned short sending_cpu; /* filled in by sender */ 220 unsigned short sending_cpu; /* filled in by sender */
167 /* 16 bits */ 221 /* 16 bits */
168 unsigned short acknowledge_count;/* filled in by destination */ 222 unsigned short acknowledge_count; /* filled in by destination */
169 /* 16 bits */ 223 /* 16 bits */
170 unsigned int reserved1:32; /* not usable */ 224 unsigned int reserved1:32; /* not usable */
171}; 225};
172 226
173 227
@@ -176,93 +230,96 @@ struct bau_msg_payload {
176 * see table 4.2.3.0.1 in broacast_assist spec. 230 * see table 4.2.3.0.1 in broacast_assist spec.
177 */ 231 */
178struct bau_msg_header { 232struct bau_msg_header {
179 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ 233 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
180 /* bits 5:0 */ 234 /* bits 5:0 */
181 unsigned int base_dest_nasid:15; /* nasid of the */ 235 unsigned int base_dest_nasid:15; /* nasid of the first bit */
182 /* bits 20:6 */ /* first bit in uvhub map */ 236 /* bits 20:6 */ /* in uvhub map */
183 unsigned int command:8; /* message type */ 237 unsigned int command:8; /* message type */
184 /* bits 28:21 */ 238 /* bits 28:21 */
185 /* 0x38: SN3net EndPoint Message */ 239 /* 0x38: SN3net EndPoint Message */
186 unsigned int rsvd_1:3; /* must be zero */ 240 unsigned int rsvd_1:3; /* must be zero */
187 /* bits 31:29 */ 241 /* bits 31:29 */
188 /* int will align on 32 bits */ 242 /* int will align on 32 bits */
189 unsigned int rsvd_2:9; /* must be zero */ 243 unsigned int rsvd_2:9; /* must be zero */
190 /* bits 40:32 */ 244 /* bits 40:32 */
191 /* Suppl_A is 56-41 */ 245 /* Suppl_A is 56-41 */
192 unsigned int sequence:16;/* message sequence number */ 246 unsigned int sequence:16; /* message sequence number */
193 /* bits 56:41 */ /* becomes bytes 16-17 of msg */ 247 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
194 /* Address field (96:57) is never used as an 248 /* Address field (96:57) is
195 address (these are address bits 42:3) */ 249 never used as an address
196 250 (these are address bits
197 unsigned int rsvd_3:1; /* must be zero */ 251 42:3) */
252
253 unsigned int rsvd_3:1; /* must be zero */
198 /* bit 57 */ 254 /* bit 57 */
199 /* address bits 27:4 are payload */ 255 /* address bits 27:4 are payload */
200 /* these next 24 (58-81) bits become bytes 12-14 of msg */ 256 /* these next 24 (58-81) bits become bytes 12-14 of msg */
201
202 /* bits 65:58 land in byte 12 */ 257 /* bits 65:58 land in byte 12 */
203 unsigned int replied_to:1;/* sent as 0 by the source to byte 12 */ 258 unsigned int replied_to:1; /* sent as 0 by the source to
259 byte 12 */
204 /* bit 58 */ 260 /* bit 58 */
205 unsigned int msg_type:3; /* software type of the message*/ 261 unsigned int msg_type:3; /* software type of the
262 message */
206 /* bits 61:59 */ 263 /* bits 61:59 */
207 unsigned int canceled:1; /* message canceled, resource to be freed*/ 264 unsigned int canceled:1; /* message canceled, resource
265 is to be freed*/
208 /* bit 62 */ 266 /* bit 62 */
209 unsigned int payload_1a:1;/* not currently used */ 267 unsigned int payload_1a:1; /* not currently used */
210 /* bit 63 */ 268 /* bit 63 */
211 unsigned int payload_1b:2;/* not currently used */ 269 unsigned int payload_1b:2; /* not currently used */
212 /* bits 65:64 */ 270 /* bits 65:64 */
213 271
214 /* bits 73:66 land in byte 13 */ 272 /* bits 73:66 land in byte 13 */
215 unsigned int payload_1ca:6;/* not currently used */ 273 unsigned int payload_1ca:6; /* not currently used */
216 /* bits 71:66 */ 274 /* bits 71:66 */
217 unsigned int payload_1c:2;/* not currently used */ 275 unsigned int payload_1c:2; /* not currently used */
218 /* bits 73:72 */ 276 /* bits 73:72 */
219 277
220 /* bits 81:74 land in byte 14 */ 278 /* bits 81:74 land in byte 14 */
221 unsigned int payload_1d:6;/* not currently used */ 279 unsigned int payload_1d:6; /* not currently used */
222 /* bits 79:74 */ 280 /* bits 79:74 */
223 unsigned int payload_1e:2;/* not currently used */ 281 unsigned int payload_1e:2; /* not currently used */
224 /* bits 81:80 */ 282 /* bits 81:80 */
225 283
226 unsigned int rsvd_4:7; /* must be zero */ 284 unsigned int rsvd_4:7; /* must be zero */
227 /* bits 88:82 */ 285 /* bits 88:82 */
228 unsigned int sw_ack_flag:1;/* software acknowledge flag */ 286 unsigned int swack_flag:1; /* software acknowledge flag */
229 /* bit 89 */ 287 /* bit 89 */
230 /* INTD trasactions at destination are to 288 /* INTD trasactions at
231 wait for software acknowledge */ 289 destination are to wait for
232 unsigned int rsvd_5:6; /* must be zero */ 290 software acknowledge */
291 unsigned int rsvd_5:6; /* must be zero */
233 /* bits 95:90 */ 292 /* bits 95:90 */
234 unsigned int rsvd_6:5; /* must be zero */ 293 unsigned int rsvd_6:5; /* must be zero */
235 /* bits 100:96 */ 294 /* bits 100:96 */
236 unsigned int int_both:1;/* if 1, interrupt both sockets on the uvhub */ 295 unsigned int int_both:1; /* if 1, interrupt both sockets
296 on the uvhub */
237 /* bit 101*/ 297 /* bit 101*/
238 unsigned int fairness:3;/* usually zero */ 298 unsigned int fairness:3; /* usually zero */
239 /* bits 104:102 */ 299 /* bits 104:102 */
240 unsigned int multilevel:1; /* multi-level multicast format */ 300 unsigned int multilevel:1; /* multi-level multicast
301 format */
241 /* bit 105 */ 302 /* bit 105 */
242 /* 0 for TLB: endpoint multi-unicast messages */ 303 /* 0 for TLB: endpoint multi-unicast messages */
243 unsigned int chaining:1;/* next descriptor is part of this activation*/ 304 unsigned int chaining:1; /* next descriptor is part of
305 this activation*/
244 /* bit 106 */ 306 /* bit 106 */
245 unsigned int rsvd_7:21; /* must be zero */ 307 unsigned int rsvd_7:21; /* must be zero */
246 /* bits 127:107 */ 308 /* bits 127:107 */
247}; 309};
248 310
249/* see msg_type: */
250#define MSG_NOOP 0
251#define MSG_REGULAR 1
252#define MSG_RETRY 2
253
254/* 311/*
255 * The activation descriptor: 312 * The activation descriptor:
256 * The format of the message to send, plus all accompanying control 313 * The format of the message to send, plus all accompanying control
257 * Should be 64 bytes 314 * Should be 64 bytes
258 */ 315 */
259struct bau_desc { 316struct bau_desc {
260 struct bau_target_uvhubmask distribution; 317 struct bau_targ_hubmask distribution;
261 /* 318 /*
262 * message template, consisting of header and payload: 319 * message template, consisting of header and payload:
263 */ 320 */
264 struct bau_msg_header header; 321 struct bau_msg_header header;
265 struct bau_msg_payload payload; 322 struct bau_msg_payload payload;
266}; 323};
267/* 324/*
268 * -payload-- ---------header------ 325 * -payload-- ---------header------
@@ -281,59 +338,51 @@ struct bau_desc {
281 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17 338 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
282 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120) 339 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
283 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from 340 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
284 * sw_ack_vector and payload_2) 341 * swack_vec and payload_2)
285 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software 342 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
286 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload 343 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
287 * operation." 344 * operation."
288 */ 345 */
289struct bau_payload_queue_entry { 346struct bau_pq_entry {
290 unsigned long address; /* signifies a page or all TLB's 347 unsigned long address; /* signifies a page or all TLB's
291 of the cpu */ 348 of the cpu */
292 /* 64 bits, bytes 0-7 */ 349 /* 64 bits, bytes 0-7 */
293 350 unsigned short sending_cpu; /* cpu that sent the message */
294 unsigned short sending_cpu; /* cpu that sent the message */
295 /* 16 bits, bytes 8-9 */ 351 /* 16 bits, bytes 8-9 */
296 352 unsigned short acknowledge_count; /* filled in by destination */
297 unsigned short acknowledge_count; /* filled in by destination */
298 /* 16 bits, bytes 10-11 */ 353 /* 16 bits, bytes 10-11 */
299
300 /* these next 3 bytes come from bits 58-81 of the message header */ 354 /* these next 3 bytes come from bits 58-81 of the message header */
301 unsigned short replied_to:1; /* sent as 0 by the source */ 355 unsigned short replied_to:1; /* sent as 0 by the source */
302 unsigned short msg_type:3; /* software message type */ 356 unsigned short msg_type:3; /* software message type */
303 unsigned short canceled:1; /* sent as 0 by the source */ 357 unsigned short canceled:1; /* sent as 0 by the source */
304 unsigned short unused1:3; /* not currently using */ 358 unsigned short unused1:3; /* not currently using */
305 /* byte 12 */ 359 /* byte 12 */
306 360 unsigned char unused2a; /* not currently using */
307 unsigned char unused2a; /* not currently using */
308 /* byte 13 */ 361 /* byte 13 */
309 unsigned char unused2; /* not currently using */ 362 unsigned char unused2; /* not currently using */
310 /* byte 14 */ 363 /* byte 14 */
311 364 unsigned char swack_vec; /* filled in by the hardware */
312 unsigned char sw_ack_vector; /* filled in by the hardware */
313 /* byte 15 (bits 127:120) */ 365 /* byte 15 (bits 127:120) */
314 366 unsigned short sequence; /* message sequence number */
315 unsigned short sequence; /* message sequence number */
316 /* bytes 16-17 */ 367 /* bytes 16-17 */
317 unsigned char unused4[2]; /* not currently using bytes 18-19 */ 368 unsigned char unused4[2]; /* not currently using bytes 18-19 */
318 /* bytes 18-19 */ 369 /* bytes 18-19 */
319 370 int number_of_cpus; /* filled in at destination */
320 int number_of_cpus; /* filled in at destination */
321 /* 32 bits, bytes 20-23 (aligned) */ 371 /* 32 bits, bytes 20-23 (aligned) */
322 372 unsigned char unused5[8]; /* not using */
323 unsigned char unused5[8]; /* not using */
324 /* bytes 24-31 */ 373 /* bytes 24-31 */
325}; 374};
326 375
327struct msg_desc { 376struct msg_desc {
328 struct bau_payload_queue_entry *msg; 377 struct bau_pq_entry *msg;
329 int msg_slot; 378 int msg_slot;
330 int sw_ack_slot; 379 int swack_slot;
331 struct bau_payload_queue_entry *va_queue_first; 380 struct bau_pq_entry *queue_first;
332 struct bau_payload_queue_entry *va_queue_last; 381 struct bau_pq_entry *queue_last;
333}; 382};
334 383
335struct reset_args { 384struct reset_args {
336 int sender; 385 int sender;
337}; 386};
338 387
339/* 388/*
@@ -341,112 +390,226 @@ struct reset_args {
341 */ 390 */
342struct ptc_stats { 391struct ptc_stats {
343 /* sender statistics */ 392 /* sender statistics */
344 unsigned long s_giveup; /* number of fall backs to IPI-style flushes */ 393 unsigned long s_giveup; /* number of fall backs to
345 unsigned long s_requestor; /* number of shootdown requests */ 394 IPI-style flushes */
346 unsigned long s_stimeout; /* source side timeouts */ 395 unsigned long s_requestor; /* number of shootdown
347 unsigned long s_dtimeout; /* destination side timeouts */ 396 requests */
348 unsigned long s_time; /* time spent in sending side */ 397 unsigned long s_stimeout; /* source side timeouts */
349 unsigned long s_retriesok; /* successful retries */ 398 unsigned long s_dtimeout; /* destination side timeouts */
350 unsigned long s_ntargcpu; /* total number of cpu's targeted */ 399 unsigned long s_time; /* time spent in sending side */
351 unsigned long s_ntargself; /* times the sending cpu was targeted */ 400 unsigned long s_retriesok; /* successful retries */
352 unsigned long s_ntarglocals; /* targets of cpus on the local blade */ 401 unsigned long s_ntargcpu; /* total number of cpu's
353 unsigned long s_ntargremotes; /* targets of cpus on remote blades */ 402 targeted */
354 unsigned long s_ntarglocaluvhub; /* targets of the local hub */ 403 unsigned long s_ntargself; /* times the sending cpu was
355 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */ 404 targeted */
356 unsigned long s_ntarguvhub; /* total number of uvhubs targeted */ 405 unsigned long s_ntarglocals; /* targets of cpus on the local
357 unsigned long s_ntarguvhub16; /* number of times target hubs >= 16*/ 406 blade */
358 unsigned long s_ntarguvhub8; /* number of times target hubs >= 8 */ 407 unsigned long s_ntargremotes; /* targets of cpus on remote
359 unsigned long s_ntarguvhub4; /* number of times target hubs >= 4 */ 408 blades */
360 unsigned long s_ntarguvhub2; /* number of times target hubs >= 2 */ 409 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
361 unsigned long s_ntarguvhub1; /* number of times target hubs == 1 */ 410 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
362 unsigned long s_resets_plug; /* ipi-style resets from plug state */ 411 unsigned long s_ntarguvhub; /* total number of uvhubs
363 unsigned long s_resets_timeout; /* ipi-style resets from timeouts */ 412 targeted */
364 unsigned long s_busy; /* status stayed busy past s/w timer */ 413 unsigned long s_ntarguvhub16; /* number of times target
365 unsigned long s_throttles; /* waits in throttle */ 414 hubs >= 16*/
366 unsigned long s_retry_messages; /* retry broadcasts */ 415 unsigned long s_ntarguvhub8; /* number of times target
367 unsigned long s_bau_reenabled; /* for bau enable/disable */ 416 hubs >= 8 */
368 unsigned long s_bau_disabled; /* for bau enable/disable */ 417 unsigned long s_ntarguvhub4; /* number of times target
418 hubs >= 4 */
419 unsigned long s_ntarguvhub2; /* number of times target
420 hubs >= 2 */
421 unsigned long s_ntarguvhub1; /* number of times target
422 hubs == 1 */
423 unsigned long s_resets_plug; /* ipi-style resets from plug
424 state */
425 unsigned long s_resets_timeout; /* ipi-style resets from
426 timeouts */
427 unsigned long s_busy; /* status stayed busy past
428 s/w timer */
429 unsigned long s_throttles; /* waits in throttle */
430 unsigned long s_retry_messages; /* retry broadcasts */
431 unsigned long s_bau_reenabled; /* for bau enable/disable */
432 unsigned long s_bau_disabled; /* for bau enable/disable */
369 /* destination statistics */ 433 /* destination statistics */
370 unsigned long d_alltlb; /* times all tlb's on this cpu were flushed */ 434 unsigned long d_alltlb; /* times all tlb's on this
371 unsigned long d_onetlb; /* times just one tlb on this cpu was flushed */ 435 cpu were flushed */
372 unsigned long d_multmsg; /* interrupts with multiple messages */ 436 unsigned long d_onetlb; /* times just one tlb on this
373 unsigned long d_nomsg; /* interrupts with no message */ 437 cpu was flushed */
374 unsigned long d_time; /* time spent on destination side */ 438 unsigned long d_multmsg; /* interrupts with multiple
375 unsigned long d_requestee; /* number of messages processed */ 439 messages */
376 unsigned long d_retries; /* number of retry messages processed */ 440 unsigned long d_nomsg; /* interrupts with no message */
377 unsigned long d_canceled; /* number of messages canceled by retries */ 441 unsigned long d_time; /* time spent on destination
378 unsigned long d_nocanceled; /* retries that found nothing to cancel */ 442 side */
379 unsigned long d_resets; /* number of ipi-style requests processed */ 443 unsigned long d_requestee; /* number of messages
380 unsigned long d_rcanceled; /* number of messages canceled by resets */ 444 processed */
445 unsigned long d_retries; /* number of retry messages
446 processed */
447 unsigned long d_canceled; /* number of messages canceled
448 by retries */
449 unsigned long d_nocanceled; /* retries that found nothing
450 to cancel */
451 unsigned long d_resets; /* number of ipi-style requests
452 processed */
453 unsigned long d_rcanceled; /* number of messages canceled
454 by resets */
455};
456
457struct tunables {
458 int *tunp;
459 int deflt;
381}; 460};
382 461
383struct hub_and_pnode { 462struct hub_and_pnode {
384 short uvhub; 463 short uvhub;
385 short pnode; 464 short pnode;
386}; 465};
466
467struct socket_desc {
468 short num_cpus;
469 short cpu_number[MAX_CPUS_PER_SOCKET];
470};
471
472struct uvhub_desc {
473 unsigned short socket_mask;
474 short num_cpus;
475 short uvhub;
476 short pnode;
477 struct socket_desc socket[2];
478};
479
387/* 480/*
388 * one per-cpu; to locate the software tables 481 * one per-cpu; to locate the software tables
389 */ 482 */
390struct bau_control { 483struct bau_control {
391 struct bau_desc *descriptor_base; 484 struct bau_desc *descriptor_base;
392 struct bau_payload_queue_entry *va_queue_first; 485 struct bau_pq_entry *queue_first;
393 struct bau_payload_queue_entry *va_queue_last; 486 struct bau_pq_entry *queue_last;
394 struct bau_payload_queue_entry *bau_msg_head; 487 struct bau_pq_entry *bau_msg_head;
395 struct bau_control *uvhub_master; 488 struct bau_control *uvhub_master;
396 struct bau_control *socket_master; 489 struct bau_control *socket_master;
397 struct ptc_stats *statp; 490 struct ptc_stats *statp;
398 unsigned long timeout_interval; 491 unsigned long timeout_interval;
399 unsigned long set_bau_on_time; 492 unsigned long set_bau_on_time;
400 atomic_t active_descriptor_count; 493 atomic_t active_descriptor_count;
401 int plugged_tries; 494 int plugged_tries;
402 int timeout_tries; 495 int timeout_tries;
403 int ipi_attempts; 496 int ipi_attempts;
404 int conseccompletes; 497 int conseccompletes;
405 int baudisabled; 498 int baudisabled;
406 int set_bau_off; 499 int set_bau_off;
407 short cpu; 500 short cpu;
408 short osnode; 501 short osnode;
409 short uvhub_cpu; 502 short uvhub_cpu;
410 short uvhub; 503 short uvhub;
411 short cpus_in_socket; 504 short cpus_in_socket;
412 short cpus_in_uvhub; 505 short cpus_in_uvhub;
413 short partition_base_pnode; 506 short partition_base_pnode;
414 unsigned short message_number; 507 unsigned short message_number;
415 unsigned short uvhub_quiesce; 508 unsigned short uvhub_quiesce;
416 short socket_acknowledge_count[DEST_Q_SIZE]; 509 short socket_acknowledge_count[DEST_Q_SIZE];
417 cycles_t send_message; 510 cycles_t send_message;
418 spinlock_t uvhub_lock; 511 spinlock_t uvhub_lock;
419 spinlock_t queue_lock; 512 spinlock_t queue_lock;
420 /* tunables */ 513 /* tunables */
421 int max_bau_concurrent; 514 int max_concurr;
422 int max_bau_concurrent_constant; 515 int max_concurr_const;
423 int plugged_delay; 516 int plugged_delay;
424 int plugsb4reset; 517 int plugsb4reset;
425 int timeoutsb4reset; 518 int timeoutsb4reset;
426 int ipi_reset_limit; 519 int ipi_reset_limit;
427 int complete_threshold; 520 int complete_threshold;
428 int congested_response_us; 521 int cong_response_us;
429 int congested_reps; 522 int cong_reps;
430 int congested_period; 523 int cong_period;
431 cycles_t period_time; 524 cycles_t period_time;
432 long period_requests; 525 long period_requests;
433 struct hub_and_pnode *target_hub_and_pnode; 526 struct hub_and_pnode *thp;
434}; 527};
435 528
436static inline int bau_uvhub_isset(int uvhub, struct bau_target_uvhubmask *dstp) 529static unsigned long read_mmr_uv2_status(void)
530{
531 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
532}
533
534static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
535{
536 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
537}
538
539static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
540{
541 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
542}
543
544static void write_mmr_activation(unsigned long index)
545{
546 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
547}
548
549static void write_gmmr_activation(int pnode, unsigned long mmr_image)
550{
551 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
552}
553
554static void write_mmr_payload_first(int pnode, unsigned long mmr_image)
555{
556 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
557}
558
559static void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
560{
561 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
562}
563
564static void write_mmr_payload_last(int pnode, unsigned long mmr_image)
565{
566 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
567}
568
569static void write_mmr_misc_control(int pnode, unsigned long mmr_image)
570{
571 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
572}
573
574static unsigned long read_mmr_misc_control(int pnode)
575{
576 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
577}
578
579static void write_mmr_sw_ack(unsigned long mr)
580{
581 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
582}
583
584static unsigned long read_mmr_sw_ack(void)
585{
586 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
587}
588
589static unsigned long read_gmmr_sw_ack(int pnode)
590{
591 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
592}
593
594static void write_mmr_data_config(int pnode, unsigned long mr)
595{
596 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
597}
598
599static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp)
437{ 600{
438 return constant_test_bit(uvhub, &dstp->bits[0]); 601 return constant_test_bit(uvhub, &dstp->bits[0]);
439} 602}
440static inline void bau_uvhub_set(int pnode, struct bau_target_uvhubmask *dstp) 603static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp)
441{ 604{
442 __set_bit(pnode, &dstp->bits[0]); 605 __set_bit(pnode, &dstp->bits[0]);
443} 606}
444static inline void bau_uvhubs_clear(struct bau_target_uvhubmask *dstp, 607static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp,
445 int nbits) 608 int nbits)
446{ 609{
447 bitmap_zero(&dstp->bits[0], nbits); 610 bitmap_zero(&dstp->bits[0], nbits);
448} 611}
449static inline int bau_uvhub_weight(struct bau_target_uvhubmask *dstp) 612static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp)
450{ 613{
451 return bitmap_weight((unsigned long *)&dstp->bits[0], 614 return bitmap_weight((unsigned long *)&dstp->bits[0],
452 UV_DISTRIBUTION_SIZE); 615 UV_DISTRIBUTION_SIZE);
@@ -457,9 +620,6 @@ static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
457 bitmap_zero(&dstp->bits, nbits); 620 bitmap_zero(&dstp->bits, nbits);
458} 621}
459 622
460#define cpubit_isset(cpu, bau_local_cpumask) \
461 test_bit((cpu), (bau_local_cpumask).bits)
462
463extern void uv_bau_message_intr1(void); 623extern void uv_bau_message_intr1(void);
464extern void uv_bau_timeout_intr1(void); 624extern void uv_bau_timeout_intr1(void);
465 625
@@ -467,7 +627,7 @@ struct atomic_short {
467 short counter; 627 short counter;
468}; 628};
469 629
470/** 630/*
471 * atomic_read_short - read a short atomic variable 631 * atomic_read_short - read a short atomic variable
472 * @v: pointer of type atomic_short 632 * @v: pointer of type atomic_short
473 * 633 *
@@ -478,14 +638,14 @@ static inline int atomic_read_short(const struct atomic_short *v)
478 return v->counter; 638 return v->counter;
479} 639}
480 640
481/** 641/*
482 * atomic_add_short_return - add and return a short int 642 * atom_asr - add and return a short int
483 * @i: short value to add 643 * @i: short value to add
484 * @v: pointer of type atomic_short 644 * @v: pointer of type atomic_short
485 * 645 *
486 * Atomically adds @i to @v and returns @i + @v 646 * Atomically adds @i to @v and returns @i + @v
487 */ 647 */
488static inline int atomic_add_short_return(short i, struct atomic_short *v) 648static inline int atom_asr(short i, struct atomic_short *v)
489{ 649{
490 short __i = i; 650 short __i = i;
491 asm volatile(LOCK_PREFIX "xaddw %0, %1" 651 asm volatile(LOCK_PREFIX "xaddw %0, %1"
@@ -494,4 +654,26 @@ static inline int atomic_add_short_return(short i, struct atomic_short *v)
494 return i + __i; 654 return i + __i;
495} 655}
496 656
657/*
658 * conditionally add 1 to *v, unless *v is >= u
659 * return 0 if we cannot add 1 to *v because it is >= u
660 * return 1 if we can add 1 to *v because it is < u
661 * the add is atomic
662 *
663 * This is close to atomic_add_unless(), but this allows the 'u' value
664 * to be lowered below the current 'v'. atomic_add_unless can only stop
665 * on equal.
666 */
667static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
668{
669 spin_lock(lock);
670 if (atomic_read(v) >= u) {
671 spin_unlock(lock);
672 return 0;
673 }
674 atomic_inc(v);
675 spin_unlock(lock);
676 return 1;
677}
678
497#endif /* _ASM_X86_UV_UV_BAU_H */ 679#endif /* _ASM_X86_UV_UV_BAU_H */
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 4298002d0c83..f26544a15214 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -77,8 +77,9 @@
77 * 77 *
78 * 1111110000000000 78 * 1111110000000000
79 * 5432109876543210 79 * 5432109876543210
80 * pppppppppplc0cch Nehalem-EX 80 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg)
81 * ppppppppplcc0cch Westmere-EX 81 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg)
82 * pppppppppppcccch SandyBridge (15 bits in hdw reg)
82 * sssssssssss 83 * sssssssssss
83 * 84 *
84 * p = pnode bits 85 * p = pnode bits
@@ -87,7 +88,7 @@
87 * h = hyperthread 88 * h = hyperthread
88 * s = bits that are in the SOCKET_ID CSR 89 * s = bits that are in the SOCKET_ID CSR
89 * 90 *
90 * Note: Processor only supports 12 bits in the APICID register. The ACPI 91 * Note: Processor may support fewer bits in the APICID register. The ACPI
91 * tables hold all 16 bits. Software needs to be aware of this. 92 * tables hold all 16 bits. Software needs to be aware of this.
92 * 93 *
93 * Unless otherwise specified, all references to APICID refer to 94 * Unless otherwise specified, all references to APICID refer to
@@ -138,6 +139,8 @@ struct uv_hub_info_s {
138 unsigned long global_mmr_base; 139 unsigned long global_mmr_base;
139 unsigned long gpa_mask; 140 unsigned long gpa_mask;
140 unsigned int gnode_extra; 141 unsigned int gnode_extra;
142 unsigned char hub_revision;
143 unsigned char apic_pnode_shift;
141 unsigned long gnode_upper; 144 unsigned long gnode_upper;
142 unsigned long lowmem_remap_top; 145 unsigned long lowmem_remap_top;
143 unsigned long lowmem_remap_base; 146 unsigned long lowmem_remap_base;
@@ -149,13 +152,31 @@ struct uv_hub_info_s {
149 unsigned char m_val; 152 unsigned char m_val;
150 unsigned char n_val; 153 unsigned char n_val;
151 struct uv_scir_s scir; 154 struct uv_scir_s scir;
152 unsigned char apic_pnode_shift;
153}; 155};
154 156
155DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 157DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
156#define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 158#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
157#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 159#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
158 160
161/*
162 * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
163 * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
164 * This is a software convention - NOT the hardware revision numbers in
165 * the hub chip.
166 */
167#define UV1_HUB_REVISION_BASE 1
168#define UV2_HUB_REVISION_BASE 3
169
170static inline int is_uv1_hub(void)
171{
172 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
173}
174
175static inline int is_uv2_hub(void)
176{
177 return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
178}
179
159union uvh_apicid { 180union uvh_apicid {
160 unsigned long v; 181 unsigned long v;
161 struct uvh_apicid_s { 182 struct uvh_apicid_s {
@@ -180,11 +201,25 @@ union uvh_apicid {
180#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 201#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
181#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 202#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
182 203
183#define UV_LOCAL_MMR_BASE 0xf4000000UL 204#define UV1_LOCAL_MMR_BASE 0xf4000000UL
184#define UV_GLOBAL_MMR32_BASE 0xf8000000UL 205#define UV1_GLOBAL_MMR32_BASE 0xf8000000UL
206#define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
207#define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
208
209#define UV2_LOCAL_MMR_BASE 0xfa000000UL
210#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
211#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
212#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
213
214#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \
215 : UV2_LOCAL_MMR_BASE)
216#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \
217 : UV2_GLOBAL_MMR32_BASE)
218#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
219 UV2_LOCAL_MMR_SIZE)
220#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
221 UV2_GLOBAL_MMR32_SIZE)
185#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 222#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
186#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
187#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
188 223
189#define UV_GLOBAL_GRU_MMR_BASE 0x4000000 224#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
190 225
@@ -301,6 +336,17 @@ static inline int uv_apicid_to_pnode(int apicid)
301} 336}
302 337
303/* 338/*
339 * Convert an apicid to the socket number on the blade
340 */
341static inline int uv_apicid_to_socket(int apicid)
342{
343 if (is_uv1_hub())
344 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
345 else
346 return 0;
347}
348
349/*
304 * Access global MMRs using the low memory MMR32 space. This region supports 350 * Access global MMRs using the low memory MMR32 space. This region supports
305 * faster MMR access but not all MMRs are accessible in this space. 351 * faster MMR access but not all MMRs are accessible in this space.
306 */ 352 */
@@ -519,14 +565,13 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
519 565
520/* 566/*
521 * Get the minimum revision number of the hub chips within the partition. 567 * Get the minimum revision number of the hub chips within the partition.
522 * 1 - initial rev 1.0 silicon 568 * 1 - UV1 rev 1.0 initial silicon
523 * 2 - rev 2.0 production silicon 569 * 2 - UV1 rev 2.0 production silicon
570 * 3 - UV2 rev 1.0 initial silicon
524 */ 571 */
525static inline int uv_get_min_hub_revision_id(void) 572static inline int uv_get_min_hub_revision_id(void)
526{ 573{
527 extern int uv_min_hub_revision_id; 574 return uv_hub_info->hub_revision;
528
529 return uv_min_hub_revision_id;
530} 575}
531 576
532#endif /* CONFIG_X86_64 */ 577#endif /* CONFIG_X86_64 */
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index f5bb64a823d7..4be52c863448 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -11,13 +11,64 @@
11#ifndef _ASM_X86_UV_UV_MMRS_H 11#ifndef _ASM_X86_UV_UV_MMRS_H
12#define _ASM_X86_UV_UV_MMRS_H 12#define _ASM_X86_UV_UV_MMRS_H
13 13
14/*
15 * This file contains MMR definitions for both UV1 & UV2 hubs.
16 *
17 * In general, MMR addresses and structures are identical on both hubs.
18 * These MMRs are identified as:
19 * #define UVH_xxx <address>
20 * union uvh_xxx {
21 * unsigned long v;
22 * struct uvh_int_cmpd_s {
23 * } s;
24 * };
25 *
26 * If the MMR exists on both hub type but has different addresses or
27 * contents, the MMR definition is similar to:
28 * #define UV1H_xxx <uv1 address>
29 * #define UV2H_xxx <uv2address>
30 * #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx)
31 * union uvh_xxx {
32 * unsigned long v;
33 * struct uv1h_int_cmpd_s { (Common fields only)
34 * } s;
35 * struct uv1h_int_cmpd_s { (Full UV1 definition)
36 * } s1;
37 * struct uv2h_int_cmpd_s { (Full UV2 definition)
38 * } s2;
39 * };
40 *
41 * Only essential difference are enumerated. For example, if the address is
42 * the same for both UV1 & UV2, only a single #define is generated. Likewise,
43 * if the contents is the same for both hubs, only the "s" structure is
44 * generated.
45 *
46 * If the MMR exists on ONLY 1 type of hub, no generic definition is
47 * generated:
48 * #define UVnH_xxx <uvn address>
49 * union uvnh_xxx {
50 * unsigned long v;
51 * struct uvh_int_cmpd_s {
52 * } sn;
53 * };
54 */
55
14#define UV_MMR_ENABLE (1UL << 63) 56#define UV_MMR_ENABLE (1UL << 63)
15 57
58#define UV1_HUB_PART_NUMBER 0x88a5
59#define UV2_HUB_PART_NUMBER 0x8eb8
60
61/* Compat: if this #define is present, UV headers support UV2 */
62#define UV2_HUB_IS_SUPPORTED 1
63
64/* KABI compat: if this #define is present, KABI hacks are present */
65#define UV2_HUB_KABI_HACKS 1
66
16/* ========================================================================= */ 67/* ========================================================================= */
17/* UVH_BAU_DATA_BROADCAST */ 68/* UVH_BAU_DATA_BROADCAST */
18/* ========================================================================= */ 69/* ========================================================================= */
19#define UVH_BAU_DATA_BROADCAST 0x61688UL 70#define UVH_BAU_DATA_BROADCAST 0x61688UL
20#define UVH_BAU_DATA_BROADCAST_32 0x0440 71#define UVH_BAU_DATA_BROADCAST_32 0x440
21 72
22#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 73#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
23#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 74#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
@@ -34,7 +85,7 @@ union uvh_bau_data_broadcast_u {
34/* UVH_BAU_DATA_CONFIG */ 85/* UVH_BAU_DATA_CONFIG */
35/* ========================================================================= */ 86/* ========================================================================= */
36#define UVH_BAU_DATA_CONFIG 0x61680UL 87#define UVH_BAU_DATA_CONFIG 0x61680UL
37#define UVH_BAU_DATA_CONFIG_32 0x0438 88#define UVH_BAU_DATA_CONFIG_32 0x438
38 89
39#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 90#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
40#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 91#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
@@ -73,125 +124,245 @@ union uvh_bau_data_config_u {
73/* UVH_EVENT_OCCURRED0 */ 124/* UVH_EVENT_OCCURRED0 */
74/* ========================================================================= */ 125/* ========================================================================= */
75#define UVH_EVENT_OCCURRED0 0x70000UL 126#define UVH_EVENT_OCCURRED0 0x70000UL
76#define UVH_EVENT_OCCURRED0_32 0x005e8 127#define UVH_EVENT_OCCURRED0_32 0x5e8
77 128
78#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 129#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
79#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 130#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
80#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 131#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
81#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 132#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
82#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 133#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
83#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 134#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
84#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 135#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
85#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 136#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
86#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 137#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
87#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 138#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
88#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 139#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
89#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 140#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
90#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 141#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
91#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 142#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
92#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 143#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
93#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 144#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
94#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 145#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
95#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 146#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
96#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 147#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
97#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 148#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
98#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 149#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
99#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 150#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
100#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 151#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
101#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 152#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
102#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 153#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
103#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 154#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
104#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 155#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
105#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 156#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
106#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 157#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
107#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 158#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
108#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 159#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
109#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 160#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
110#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 161#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
111#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 162#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
112#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 163#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
113#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 164#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
114#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 165#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
115#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 166#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
116#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 167#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
117#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 168#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
118#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 169#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
119#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 170#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
120#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 171#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
121#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 172#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
122#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 173#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
123#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 174#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 175#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 176#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 177#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 178#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 179#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 180#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 181#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 182#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 183#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 184#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 185#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 186#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 187#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 188#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 189#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
139#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 190#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
140#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 191#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
141#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 192#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
142#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 193#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
143#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 194#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
144#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 195#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
145#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 196#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
146#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 197#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
147#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 198#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
148#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 199#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
149#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 200#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
150#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 201#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
151#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 202#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
152#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 203#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
153#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 204#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
154#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 205#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
155#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 206#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
156#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 207#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
157#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 208#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
158#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 209#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
159#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 210#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
160#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 211#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
161#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 212#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
162#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 213#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
163#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 214#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
164#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 215#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
165#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 216#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
166#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 217#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
167#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 218#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
168#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 219#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
169#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 220#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
170#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 221#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
171#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 222#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
172#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 223#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
173#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 224#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
174#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 225#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
175#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 226#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
176#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 227#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
177#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 228#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
178#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 229#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
179#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 230#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
180#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 231#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
181#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 232#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
182#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 233#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
183#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 234#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
184#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 235#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
185#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 236#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
186#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 237#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
187#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 238#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
188#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 239#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
189#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 240#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
190#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 241#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
191#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 242#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
243
244#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
245#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
246#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
247#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
248#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
249#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
250#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
251#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
252#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
253#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
254#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
255#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
256#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
257#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
258#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
259#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
260#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
261#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
262#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
263#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
264#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
265#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
266#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
267#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
268#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
269#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
270#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
271#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
272#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
273#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
274#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
275#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
276#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
277#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
278#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
279#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
280#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
281#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
282#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
283#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
284#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
285#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
286#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
287#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
288#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
289#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
290#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
291#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
292#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
293#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
294#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
295#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
296#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
297#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
298#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
299#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
300#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
301#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
302#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
303#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
304#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
305#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
306#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
307#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
308#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
309#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
310#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
311#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
312#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
313#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
314#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
315#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
316#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
317#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
318#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
319#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
320#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
321#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
322#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
323#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
324#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
325#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
326#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
327#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
328#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
329#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
330#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
331#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
332#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
333#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
334#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
335#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
336#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
337#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
338#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
339#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
340#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
341#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
342#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
343#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
344#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
345#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
346#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
347#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
348#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
349#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
350#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
351#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
352#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
353#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
354#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
355#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
356#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
357#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
358#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
359#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
360#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
361#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
362
192union uvh_event_occurred0_u { 363union uvh_event_occurred0_u {
193 unsigned long v; 364 unsigned long v;
194 struct uvh_event_occurred0_s { 365 struct uv1h_event_occurred0_s {
195 unsigned long lb_hcerr : 1; /* RW, W1C */ 366 unsigned long lb_hcerr : 1; /* RW, W1C */
196 unsigned long gr0_hcerr : 1; /* RW, W1C */ 367 unsigned long gr0_hcerr : 1; /* RW, W1C */
197 unsigned long gr1_hcerr : 1; /* RW, W1C */ 368 unsigned long gr1_hcerr : 1; /* RW, W1C */
@@ -250,14 +421,76 @@ union uvh_event_occurred0_u {
250 unsigned long bau_data : 1; /* RW, W1C */ 421 unsigned long bau_data : 1; /* RW, W1C */
251 unsigned long power_management_req : 1; /* RW, W1C */ 422 unsigned long power_management_req : 1; /* RW, W1C */
252 unsigned long rsvd_57_63 : 7; /* */ 423 unsigned long rsvd_57_63 : 7; /* */
253 } s; 424 } s1;
425 struct uv2h_event_occurred0_s {
426 unsigned long lb_hcerr : 1; /* RW */
427 unsigned long qp_hcerr : 1; /* RW */
428 unsigned long rh_hcerr : 1; /* RW */
429 unsigned long lh0_hcerr : 1; /* RW */
430 unsigned long lh1_hcerr : 1; /* RW */
431 unsigned long gr0_hcerr : 1; /* RW */
432 unsigned long gr1_hcerr : 1; /* RW */
433 unsigned long ni0_hcerr : 1; /* RW */
434 unsigned long ni1_hcerr : 1; /* RW */
435 unsigned long lb_aoerr0 : 1; /* RW */
436 unsigned long qp_aoerr0 : 1; /* RW */
437 unsigned long rh_aoerr0 : 1; /* RW */
438 unsigned long lh0_aoerr0 : 1; /* RW */
439 unsigned long lh1_aoerr0 : 1; /* RW */
440 unsigned long gr0_aoerr0 : 1; /* RW */
441 unsigned long gr1_aoerr0 : 1; /* RW */
442 unsigned long xb_aoerr0 : 1; /* RW */
443 unsigned long rt_aoerr0 : 1; /* RW */
444 unsigned long ni0_aoerr0 : 1; /* RW */
445 unsigned long ni1_aoerr0 : 1; /* RW */
446 unsigned long lb_aoerr1 : 1; /* RW */
447 unsigned long qp_aoerr1 : 1; /* RW */
448 unsigned long rh_aoerr1 : 1; /* RW */
449 unsigned long lh0_aoerr1 : 1; /* RW */
450 unsigned long lh1_aoerr1 : 1; /* RW */
451 unsigned long gr0_aoerr1 : 1; /* RW */
452 unsigned long gr1_aoerr1 : 1; /* RW */
453 unsigned long xb_aoerr1 : 1; /* RW */
454 unsigned long rt_aoerr1 : 1; /* RW */
455 unsigned long ni0_aoerr1 : 1; /* RW */
456 unsigned long ni1_aoerr1 : 1; /* RW */
457 unsigned long system_shutdown_int : 1; /* RW */
458 unsigned long lb_irq_int_0 : 1; /* RW */
459 unsigned long lb_irq_int_1 : 1; /* RW */
460 unsigned long lb_irq_int_2 : 1; /* RW */
461 unsigned long lb_irq_int_3 : 1; /* RW */
462 unsigned long lb_irq_int_4 : 1; /* RW */
463 unsigned long lb_irq_int_5 : 1; /* RW */
464 unsigned long lb_irq_int_6 : 1; /* RW */
465 unsigned long lb_irq_int_7 : 1; /* RW */
466 unsigned long lb_irq_int_8 : 1; /* RW */
467 unsigned long lb_irq_int_9 : 1; /* RW */
468 unsigned long lb_irq_int_10 : 1; /* RW */
469 unsigned long lb_irq_int_11 : 1; /* RW */
470 unsigned long lb_irq_int_12 : 1; /* RW */
471 unsigned long lb_irq_int_13 : 1; /* RW */
472 unsigned long lb_irq_int_14 : 1; /* RW */
473 unsigned long lb_irq_int_15 : 1; /* RW */
474 unsigned long l1_nmi_int : 1; /* RW */
475 unsigned long stop_clock : 1; /* RW */
476 unsigned long asic_to_l1 : 1; /* RW */
477 unsigned long l1_to_asic : 1; /* RW */
478 unsigned long la_seq_trigger : 1; /* RW */
479 unsigned long ipi_int : 1; /* RW */
480 unsigned long extio_int0 : 1; /* RW */
481 unsigned long extio_int1 : 1; /* RW */
482 unsigned long extio_int2 : 1; /* RW */
483 unsigned long extio_int3 : 1; /* RW */
484 unsigned long profile_int : 1; /* RW */
485 unsigned long rsvd_59_63 : 5; /* */
486 } s2;
254}; 487};
255 488
256/* ========================================================================= */ 489/* ========================================================================= */
257/* UVH_EVENT_OCCURRED0_ALIAS */ 490/* UVH_EVENT_OCCURRED0_ALIAS */
258/* ========================================================================= */ 491/* ========================================================================= */
259#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL 492#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
260#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 493#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
261 494
262/* ========================================================================= */ 495/* ========================================================================= */
263/* UVH_GR0_TLB_INT0_CONFIG */ 496/* UVH_GR0_TLB_INT0_CONFIG */
@@ -432,8 +665,16 @@ union uvh_int_cmpb_u {
432/* ========================================================================= */ 665/* ========================================================================= */
433#define UVH_INT_CMPC 0x22100UL 666#define UVH_INT_CMPC 0x22100UL
434 667
435#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 668#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0
436#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 669#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT 0
670#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT (is_uv1_hub() ? \
671 UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT : \
672 UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
673#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
674#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
675#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK (is_uv1_hub() ? \
676 UV1H_INT_CMPC_REAL_TIME_CMPC_MASK : \
677 UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
437 678
438union uvh_int_cmpc_u { 679union uvh_int_cmpc_u {
439 unsigned long v; 680 unsigned long v;
@@ -448,8 +689,16 @@ union uvh_int_cmpc_u {
448/* ========================================================================= */ 689/* ========================================================================= */
449#define UVH_INT_CMPD 0x22180UL 690#define UVH_INT_CMPD 0x22180UL
450 691
451#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 692#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0
452#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 693#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT 0
694#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT (is_uv1_hub() ? \
695 UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT : \
696 UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
697#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
698#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
699#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK (is_uv1_hub() ? \
700 UV1H_INT_CMPD_REAL_TIME_CMPD_MASK : \
701 UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
453 702
454union uvh_int_cmpd_u { 703union uvh_int_cmpd_u {
455 unsigned long v; 704 unsigned long v;
@@ -463,7 +712,7 @@ union uvh_int_cmpd_u {
463/* UVH_IPI_INT */ 712/* UVH_IPI_INT */
464/* ========================================================================= */ 713/* ========================================================================= */
465#define UVH_IPI_INT 0x60500UL 714#define UVH_IPI_INT 0x60500UL
466#define UVH_IPI_INT_32 0x0348 715#define UVH_IPI_INT_32 0x348
467 716
468#define UVH_IPI_INT_VECTOR_SHFT 0 717#define UVH_IPI_INT_VECTOR_SHFT 0
469#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 718#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
@@ -493,7 +742,7 @@ union uvh_ipi_int_u {
493/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 742/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
494/* ========================================================================= */ 743/* ========================================================================= */
495#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 744#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
496#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0 745#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
497 746
498#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 747#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
499#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 748#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -515,7 +764,7 @@ union uvh_lb_bau_intd_payload_queue_first_u {
515/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 764/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
516/* ========================================================================= */ 765/* ========================================================================= */
517#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 766#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
518#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8 767#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
519 768
520#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 769#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
521#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 770#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -533,7 +782,7 @@ union uvh_lb_bau_intd_payload_queue_last_u {
533/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 782/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
534/* ========================================================================= */ 783/* ========================================================================= */
535#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 784#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
536#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0 785#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
537 786
538#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 787#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
539#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 788#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
@@ -551,7 +800,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
551/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 800/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
552/* ========================================================================= */ 801/* ========================================================================= */
553#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 802#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
554#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68 803#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
555 804
556#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 805#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
557#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 806#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
@@ -585,6 +834,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
585#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 834#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
586#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 835#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
587#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 836#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
837
588union uvh_lb_bau_intd_software_acknowledge_u { 838union uvh_lb_bau_intd_software_acknowledge_u {
589 unsigned long v; 839 unsigned long v;
590 struct uvh_lb_bau_intd_software_acknowledge_s { 840 struct uvh_lb_bau_intd_software_acknowledge_s {
@@ -612,13 +862,13 @@ union uvh_lb_bau_intd_software_acknowledge_u {
612/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 862/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
613/* ========================================================================= */ 863/* ========================================================================= */
614#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 864#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
615#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 865#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
616 866
617/* ========================================================================= */ 867/* ========================================================================= */
618/* UVH_LB_BAU_MISC_CONTROL */ 868/* UVH_LB_BAU_MISC_CONTROL */
619/* ========================================================================= */ 869/* ========================================================================= */
620#define UVH_LB_BAU_MISC_CONTROL 0x320170UL 870#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
621#define UVH_LB_BAU_MISC_CONTROL_32 0x00a10 871#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
622 872
623#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 873#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
624#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 874#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
@@ -628,8 +878,8 @@ union uvh_lb_bau_intd_software_acknowledge_u {
628#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 878#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
629#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 879#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
630#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 880#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
631#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11 881#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
632#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 882#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
633#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 883#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
634#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 884#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
635#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 885#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
@@ -650,8 +900,86 @@ union uvh_lb_bau_intd_software_acknowledge_u {
650#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 900#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
651#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 901#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
652#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 902#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
653#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 903
654#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 904#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
905#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
906#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
907#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
908#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
909#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
910#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
911#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
912#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
913#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
914#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
915#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
916#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
917#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
918#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
919#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
920#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
921#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
922#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
923#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
924#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
925#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
926#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
927#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
928#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
929#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
930#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
931#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
932#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
933#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
934#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
935#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
936
937#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
938#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
939#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
940#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
941#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
942#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
943#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
944#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
945#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
946#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
947#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
948#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
949#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
950#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
951#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
952#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
953#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
954#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
955#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
956#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
957#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
958#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
959#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
960#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
961#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
962#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
963#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
964#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
965#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
966#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
967#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
968#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
969#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
970#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
971#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
972#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
973#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
974#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
975#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
976#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
977#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
978#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
979#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
980#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
981#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
982#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
655 983
656union uvh_lb_bau_misc_control_u { 984union uvh_lb_bau_misc_control_u {
657 unsigned long v; 985 unsigned long v;
@@ -660,7 +988,25 @@ union uvh_lb_bau_misc_control_u {
660 unsigned long apic_mode : 1; /* RW */ 988 unsigned long apic_mode : 1; /* RW */
661 unsigned long force_broadcast : 1; /* RW */ 989 unsigned long force_broadcast : 1; /* RW */
662 unsigned long force_lock_nop : 1; /* RW */ 990 unsigned long force_lock_nop : 1; /* RW */
663 unsigned long csi_agent_presence_vector : 3; /* RW */ 991 unsigned long qpi_agent_presence_vector : 3; /* RW */
992 unsigned long descriptor_fetch_mode : 1; /* RW */
993 unsigned long enable_intd_soft_ack_mode : 1; /* RW */
994 unsigned long intd_soft_ack_timeout_period : 4; /* RW */
995 unsigned long enable_dual_mapping_mode : 1; /* RW */
996 unsigned long vga_io_port_decode_enable : 1; /* RW */
997 unsigned long vga_io_port_16_bit_decode : 1; /* RW */
998 unsigned long suppress_dest_registration : 1; /* RW */
999 unsigned long programmed_initial_priority : 3; /* RW */
1000 unsigned long use_incoming_priority : 1; /* RW */
1001 unsigned long enable_programmed_initial_priority : 1; /* RW */
1002 unsigned long rsvd_29_63 : 35;
1003 } s;
1004 struct uv1h_lb_bau_misc_control_s {
1005 unsigned long rejection_delay : 8; /* RW */
1006 unsigned long apic_mode : 1; /* RW */
1007 unsigned long force_broadcast : 1; /* RW */
1008 unsigned long force_lock_nop : 1; /* RW */
1009 unsigned long qpi_agent_presence_vector : 3; /* RW */
664 unsigned long descriptor_fetch_mode : 1; /* RW */ 1010 unsigned long descriptor_fetch_mode : 1; /* RW */
665 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1011 unsigned long enable_intd_soft_ack_mode : 1; /* RW */
666 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1012 unsigned long intd_soft_ack_timeout_period : 4; /* RW */
@@ -673,14 +1019,40 @@ union uvh_lb_bau_misc_control_u {
673 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1019 unsigned long enable_programmed_initial_priority : 1; /* RW */
674 unsigned long rsvd_29_47 : 19; /* */ 1020 unsigned long rsvd_29_47 : 19; /* */
675 unsigned long fun : 16; /* RW */ 1021 unsigned long fun : 16; /* RW */
676 } s; 1022 } s1;
1023 struct uv2h_lb_bau_misc_control_s {
1024 unsigned long rejection_delay : 8; /* RW */
1025 unsigned long apic_mode : 1; /* RW */
1026 unsigned long force_broadcast : 1; /* RW */
1027 unsigned long force_lock_nop : 1; /* RW */
1028 unsigned long qpi_agent_presence_vector : 3; /* RW */
1029 unsigned long descriptor_fetch_mode : 1; /* RW */
1030 unsigned long enable_intd_soft_ack_mode : 1; /* RW */
1031 unsigned long intd_soft_ack_timeout_period : 4; /* RW */
1032 unsigned long enable_dual_mapping_mode : 1; /* RW */
1033 unsigned long vga_io_port_decode_enable : 1; /* RW */
1034 unsigned long vga_io_port_16_bit_decode : 1; /* RW */
1035 unsigned long suppress_dest_registration : 1; /* RW */
1036 unsigned long programmed_initial_priority : 3; /* RW */
1037 unsigned long use_incoming_priority : 1; /* RW */
1038 unsigned long enable_programmed_initial_priority : 1; /* RW */
1039 unsigned long enable_automatic_apic_mode_selection : 1; /* RW */
1040 unsigned long apic_mode_status : 1; /* RO */
1041 unsigned long suppress_interrupts_to_self : 1; /* RW */
1042 unsigned long enable_lock_based_system_flush : 1; /* RW */
1043 unsigned long enable_extended_sb_status : 1; /* RW */
1044 unsigned long suppress_int_prio_udt_to_self : 1; /* RW */
1045 unsigned long use_legacy_descriptor_formats : 1; /* RW */
1046 unsigned long rsvd_36_47 : 12; /* */
1047 unsigned long fun : 16; /* RW */
1048 } s2;
677}; 1049};
678 1050
679/* ========================================================================= */ 1051/* ========================================================================= */
680/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1052/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
681/* ========================================================================= */ 1053/* ========================================================================= */
682#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1054#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
683#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8 1055#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
684 1056
685#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1057#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
686#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 1058#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
@@ -703,7 +1075,7 @@ union uvh_lb_bau_sb_activation_control_u {
703/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1075/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
704/* ========================================================================= */ 1076/* ========================================================================= */
705#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1077#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
706#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0 1078#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
707 1079
708#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1080#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
709#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1081#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
@@ -719,7 +1091,7 @@ union uvh_lb_bau_sb_activation_status_0_u {
719/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1091/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
720/* ========================================================================= */ 1092/* ========================================================================= */
721#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1093#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
722#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8 1094#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
723 1095
724#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1096#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
725#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1097#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
@@ -735,7 +1107,7 @@ union uvh_lb_bau_sb_activation_status_1_u {
735/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1107/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
736/* ========================================================================= */ 1108/* ========================================================================= */
737#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1109#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
738#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0 1110#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
739 1111
740#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1112#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
741#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 1113#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
@@ -754,23 +1126,6 @@ union uvh_lb_bau_sb_descriptor_base_u {
754}; 1126};
755 1127
756/* ========================================================================= */ 1128/* ========================================================================= */
757/* UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK */
758/* ========================================================================= */
759#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
760#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0
761
762#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
763#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
764
765union uvh_lb_target_physical_apic_id_mask_u {
766 unsigned long v;
767 struct uvh_lb_target_physical_apic_id_mask_s {
768 unsigned long bit_enables : 32; /* RW */
769 unsigned long rsvd_32_63 : 32; /* */
770 } s;
771};
772
773/* ========================================================================= */
774/* UVH_NODE_ID */ 1129/* UVH_NODE_ID */
775/* ========================================================================= */ 1130/* ========================================================================= */
776#define UVH_NODE_ID 0x0UL 1131#define UVH_NODE_ID 0x0UL
@@ -785,10 +1140,36 @@ union uvh_lb_target_physical_apic_id_mask_u {
785#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1140#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
786#define UVH_NODE_ID_NODE_ID_SHFT 32 1141#define UVH_NODE_ID_NODE_ID_SHFT 32
787#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1142#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
788#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 1143
789#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 1144#define UV1H_NODE_ID_FORCE1_SHFT 0
790#define UVH_NODE_ID_NI_PORT_SHFT 56 1145#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
791#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 1146#define UV1H_NODE_ID_MANUFACTURER_SHFT 1
1147#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1148#define UV1H_NODE_ID_PART_NUMBER_SHFT 12
1149#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1150#define UV1H_NODE_ID_REVISION_SHFT 28
1151#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1152#define UV1H_NODE_ID_NODE_ID_SHFT 32
1153#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1154#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
1155#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1156#define UV1H_NODE_ID_NI_PORT_SHFT 56
1157#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1158
1159#define UV2H_NODE_ID_FORCE1_SHFT 0
1160#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1161#define UV2H_NODE_ID_MANUFACTURER_SHFT 1
1162#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1163#define UV2H_NODE_ID_PART_NUMBER_SHFT 12
1164#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1165#define UV2H_NODE_ID_REVISION_SHFT 28
1166#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1167#define UV2H_NODE_ID_NODE_ID_SHFT 32
1168#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1169#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
1170#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
1171#define UV2H_NODE_ID_NI_PORT_SHFT 57
1172#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
792 1173
793union uvh_node_id_u { 1174union uvh_node_id_u {
794 unsigned long v; 1175 unsigned long v;
@@ -798,12 +1179,31 @@ union uvh_node_id_u {
798 unsigned long part_number : 16; /* RO */ 1179 unsigned long part_number : 16; /* RO */
799 unsigned long revision : 4; /* RO */ 1180 unsigned long revision : 4; /* RO */
800 unsigned long node_id : 15; /* RW */ 1181 unsigned long node_id : 15; /* RW */
1182 unsigned long rsvd_47_63 : 17;
1183 } s;
1184 struct uv1h_node_id_s {
1185 unsigned long force1 : 1; /* RO */
1186 unsigned long manufacturer : 11; /* RO */
1187 unsigned long part_number : 16; /* RO */
1188 unsigned long revision : 4; /* RO */
1189 unsigned long node_id : 15; /* RW */
801 unsigned long rsvd_47 : 1; /* */ 1190 unsigned long rsvd_47 : 1; /* */
802 unsigned long nodes_per_bit : 7; /* RW */ 1191 unsigned long nodes_per_bit : 7; /* RW */
803 unsigned long rsvd_55 : 1; /* */ 1192 unsigned long rsvd_55 : 1; /* */
804 unsigned long ni_port : 4; /* RO */ 1193 unsigned long ni_port : 4; /* RO */
805 unsigned long rsvd_60_63 : 4; /* */ 1194 unsigned long rsvd_60_63 : 4; /* */
806 } s; 1195 } s1;
1196 struct uv2h_node_id_s {
1197 unsigned long force1 : 1; /* RO */
1198 unsigned long manufacturer : 11; /* RO */
1199 unsigned long part_number : 16; /* RO */
1200 unsigned long revision : 4; /* RO */
1201 unsigned long node_id : 15; /* RW */
1202 unsigned long rsvd_47_49 : 3; /* */
1203 unsigned long nodes_per_bit : 7; /* RO */
1204 unsigned long ni_port : 5; /* RO */
1205 unsigned long rsvd_62_63 : 2; /* */
1206 } s2;
807}; 1207};
808 1208
809/* ========================================================================= */ 1209/* ========================================================================= */
@@ -954,18 +1354,38 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
954#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1354#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
955#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1355#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
956#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1356#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
957#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 1357
958#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 1358#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1359#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1360#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1361#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1362#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
1363#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
1364
1365#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1366#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1367#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1368#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
959 1369
960union uvh_rh_gam_config_mmr_u { 1370union uvh_rh_gam_config_mmr_u {
961 unsigned long v; 1371 unsigned long v;
962 struct uvh_rh_gam_config_mmr_s { 1372 struct uvh_rh_gam_config_mmr_s {
963 unsigned long m_skt : 6; /* RW */ 1373 unsigned long m_skt : 6; /* RW */
964 unsigned long n_skt : 4; /* RW */ 1374 unsigned long n_skt : 4; /* RW */
1375 unsigned long rsvd_10_63 : 54;
1376 } s;
1377 struct uv1h_rh_gam_config_mmr_s {
1378 unsigned long m_skt : 6; /* RW */
1379 unsigned long n_skt : 4; /* RW */
965 unsigned long rsvd_10_11: 2; /* */ 1380 unsigned long rsvd_10_11: 2; /* */
966 unsigned long mmiol_cfg : 1; /* RW */ 1381 unsigned long mmiol_cfg : 1; /* RW */
967 unsigned long rsvd_13_63: 51; /* */ 1382 unsigned long rsvd_13_63: 51; /* */
968 } s; 1383 } s1;
1384 struct uv2h_rh_gam_config_mmr_s {
1385 unsigned long m_skt : 6; /* RW */
1386 unsigned long n_skt : 4; /* RW */
1387 unsigned long rsvd_10_63: 54; /* */
1388 } s2;
969}; 1389};
970 1390
971/* ========================================================================= */ 1391/* ========================================================================= */
@@ -975,25 +1395,49 @@ union uvh_rh_gam_config_mmr_u {
975 1395
976#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1396#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
977#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1397#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
978#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 1398
979#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 1399#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
980#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1400#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
981#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1401#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
982#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1402#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
983#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1403#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1404#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1405#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1406#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1407
1408#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1409#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1410#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1411#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1412#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1413#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
984 1414
985union uvh_rh_gam_gru_overlay_config_mmr_u { 1415union uvh_rh_gam_gru_overlay_config_mmr_u {
986 unsigned long v; 1416 unsigned long v;
987 struct uvh_rh_gam_gru_overlay_config_mmr_s { 1417 struct uvh_rh_gam_gru_overlay_config_mmr_s {
988 unsigned long rsvd_0_27: 28; /* */ 1418 unsigned long rsvd_0_27: 28; /* */
989 unsigned long base : 18; /* RW */ 1419 unsigned long base : 18; /* RW */
1420 unsigned long rsvd_46_62 : 17;
1421 unsigned long enable : 1; /* RW */
1422 } s;
1423 struct uv1h_rh_gam_gru_overlay_config_mmr_s {
1424 unsigned long rsvd_0_27: 28; /* */
1425 unsigned long base : 18; /* RW */
990 unsigned long rsvd_46_47: 2; /* */ 1426 unsigned long rsvd_46_47: 2; /* */
991 unsigned long gr4 : 1; /* RW */ 1427 unsigned long gr4 : 1; /* RW */
992 unsigned long rsvd_49_51: 3; /* */ 1428 unsigned long rsvd_49_51: 3; /* */
993 unsigned long n_gru : 4; /* RW */ 1429 unsigned long n_gru : 4; /* RW */
994 unsigned long rsvd_56_62: 7; /* */ 1430 unsigned long rsvd_56_62: 7; /* */
995 unsigned long enable : 1; /* RW */ 1431 unsigned long enable : 1; /* RW */
996 } s; 1432 } s1;
1433 struct uv2h_rh_gam_gru_overlay_config_mmr_s {
1434 unsigned long rsvd_0_27: 28; /* */
1435 unsigned long base : 18; /* RW */
1436 unsigned long rsvd_46_51: 6; /* */
1437 unsigned long n_gru : 4; /* RW */
1438 unsigned long rsvd_56_62: 7; /* */
1439 unsigned long enable : 1; /* RW */
1440 } s2;
997}; 1441};
998 1442
999/* ========================================================================= */ 1443/* ========================================================================= */
@@ -1001,25 +1445,42 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
1001/* ========================================================================= */ 1445/* ========================================================================= */
1002#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 1446#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1003 1447
1004#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1448#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1005#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1449#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1006#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1450#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1007#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 1451#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1008#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 1452#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1009#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 1453#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1010#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1454#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1011#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1455#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1456
1457#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
1458#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
1459#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1460#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1461#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1462#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1463#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1464#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1012 1465
1013union uvh_rh_gam_mmioh_overlay_config_mmr_u { 1466union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1014 unsigned long v; 1467 unsigned long v;
1015 struct uvh_rh_gam_mmioh_overlay_config_mmr_s { 1468 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
1016 unsigned long rsvd_0_29: 30; /* */ 1469 unsigned long rsvd_0_29: 30; /* */
1017 unsigned long base : 16; /* RW */ 1470 unsigned long base : 16; /* RW */
1018 unsigned long m_io : 6; /* RW */ 1471 unsigned long m_io : 6; /* RW */
1019 unsigned long n_io : 4; /* RW */ 1472 unsigned long n_io : 4; /* RW */
1020 unsigned long rsvd_56_62: 7; /* */ 1473 unsigned long rsvd_56_62: 7; /* */
1021 unsigned long enable : 1; /* RW */ 1474 unsigned long enable : 1; /* RW */
1022 } s; 1475 } s1;
1476 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
1477 unsigned long rsvd_0_26: 27; /* */
1478 unsigned long base : 19; /* RW */
1479 unsigned long m_io : 6; /* RW */
1480 unsigned long n_io : 4; /* RW */
1481 unsigned long rsvd_56_62: 7; /* */
1482 unsigned long enable : 1; /* RW */
1483 } s2;
1023}; 1484};
1024 1485
1025/* ========================================================================= */ 1486/* ========================================================================= */
@@ -1029,20 +1490,40 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1029 1490
1030#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1491#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1031#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1492#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1032#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1493
1033#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1494#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1034#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1495#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1035#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1496#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1497#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1498#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1499#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1500
1501#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1502#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1503#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1504#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1036 1505
1037union uvh_rh_gam_mmr_overlay_config_mmr_u { 1506union uvh_rh_gam_mmr_overlay_config_mmr_u {
1038 unsigned long v; 1507 unsigned long v;
1039 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 1508 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1040 unsigned long rsvd_0_25: 26; /* */ 1509 unsigned long rsvd_0_25: 26; /* */
1041 unsigned long base : 20; /* RW */ 1510 unsigned long base : 20; /* RW */
1511 unsigned long rsvd_46_62 : 17;
1512 unsigned long enable : 1; /* RW */
1513 } s;
1514 struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
1515 unsigned long rsvd_0_25: 26; /* */
1516 unsigned long base : 20; /* RW */
1042 unsigned long dual_hub : 1; /* RW */ 1517 unsigned long dual_hub : 1; /* RW */
1043 unsigned long rsvd_47_62: 16; /* */ 1518 unsigned long rsvd_47_62: 16; /* */
1044 unsigned long enable : 1; /* RW */ 1519 unsigned long enable : 1; /* RW */
1045 } s; 1520 } s1;
1521 struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
1522 unsigned long rsvd_0_25: 26; /* */
1523 unsigned long base : 20; /* RW */
1524 unsigned long rsvd_46_62: 17; /* */
1525 unsigned long enable : 1; /* RW */
1526 } s2;
1046}; 1527};
1047 1528
1048/* ========================================================================= */ 1529/* ========================================================================= */
@@ -1103,10 +1584,11 @@ union uvh_rtc1_int_config_u {
1103/* UVH_SCRATCH5 */ 1584/* UVH_SCRATCH5 */
1104/* ========================================================================= */ 1585/* ========================================================================= */
1105#define UVH_SCRATCH5 0x2d0200UL 1586#define UVH_SCRATCH5 0x2d0200UL
1106#define UVH_SCRATCH5_32 0x00778 1587#define UVH_SCRATCH5_32 0x778
1107 1588
1108#define UVH_SCRATCH5_SCRATCH5_SHFT 0 1589#define UVH_SCRATCH5_SCRATCH5_SHFT 0
1109#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 1590#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1591
1110union uvh_scratch5_u { 1592union uvh_scratch5_u {
1111 unsigned long v; 1593 unsigned long v;
1112 struct uvh_scratch5_s { 1594 struct uvh_scratch5_s {
@@ -1114,4 +1596,154 @@ union uvh_scratch5_u {
1114 } s; 1596 } s;
1115}; 1597};
1116 1598
1599/* ========================================================================= */
1600/* UV2H_EVENT_OCCURRED2 */
1601/* ========================================================================= */
1602#define UV2H_EVENT_OCCURRED2 0x70100UL
1603#define UV2H_EVENT_OCCURRED2_32 0xb68
1604
1605#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1606#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1607#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
1608#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1609#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
1610#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1611#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
1612#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1613#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
1614#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1615#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
1616#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1617#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
1618#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1619#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
1620#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1621#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
1622#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1623#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
1624#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1625#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
1626#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1627#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
1628#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1629#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
1630#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1631#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
1632#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1633#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
1634#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1635#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
1636#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1637#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
1638#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1639#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
1640#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1641#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
1642#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1643#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
1644#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1645#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
1646#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1647#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
1648#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1649#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
1650#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1651#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
1652#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1653#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
1654#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1655#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
1656#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1657#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
1658#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1659#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
1660#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1661#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
1662#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1663#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
1664#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1665#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
1666#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1667#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
1668#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1669
1670union uv2h_event_occurred2_u {
1671 unsigned long v;
1672 struct uv2h_event_occurred2_s {
1673 unsigned long rtc_0 : 1; /* RW */
1674 unsigned long rtc_1 : 1; /* RW */
1675 unsigned long rtc_2 : 1; /* RW */
1676 unsigned long rtc_3 : 1; /* RW */
1677 unsigned long rtc_4 : 1; /* RW */
1678 unsigned long rtc_5 : 1; /* RW */
1679 unsigned long rtc_6 : 1; /* RW */
1680 unsigned long rtc_7 : 1; /* RW */
1681 unsigned long rtc_8 : 1; /* RW */
1682 unsigned long rtc_9 : 1; /* RW */
1683 unsigned long rtc_10 : 1; /* RW */
1684 unsigned long rtc_11 : 1; /* RW */
1685 unsigned long rtc_12 : 1; /* RW */
1686 unsigned long rtc_13 : 1; /* RW */
1687 unsigned long rtc_14 : 1; /* RW */
1688 unsigned long rtc_15 : 1; /* RW */
1689 unsigned long rtc_16 : 1; /* RW */
1690 unsigned long rtc_17 : 1; /* RW */
1691 unsigned long rtc_18 : 1; /* RW */
1692 unsigned long rtc_19 : 1; /* RW */
1693 unsigned long rtc_20 : 1; /* RW */
1694 unsigned long rtc_21 : 1; /* RW */
1695 unsigned long rtc_22 : 1; /* RW */
1696 unsigned long rtc_23 : 1; /* RW */
1697 unsigned long rtc_24 : 1; /* RW */
1698 unsigned long rtc_25 : 1; /* RW */
1699 unsigned long rtc_26 : 1; /* RW */
1700 unsigned long rtc_27 : 1; /* RW */
1701 unsigned long rtc_28 : 1; /* RW */
1702 unsigned long rtc_29 : 1; /* RW */
1703 unsigned long rtc_30 : 1; /* RW */
1704 unsigned long rtc_31 : 1; /* RW */
1705 unsigned long rsvd_32_63: 32; /* */
1706 } s1;
1707};
1708
1709/* ========================================================================= */
1710/* UV2H_EVENT_OCCURRED2_ALIAS */
1711/* ========================================================================= */
1712#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
1713#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
1714
1715/* ========================================================================= */
1716/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */
1717/* ========================================================================= */
1718#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
1719#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
1720
1721#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
1722#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
1723
1724union uv2h_lb_bau_sb_activation_status_2_u {
1725 unsigned long v;
1726 struct uv2h_lb_bau_sb_activation_status_2_s {
1727 unsigned long aux_error : 64; /* RW */
1728 } s1;
1729};
1730
1731/* ========================================================================= */
1732/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */
1733/* ========================================================================= */
1734#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
1735#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
1736
1737#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
1738#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
1739
1740union uv1h_lb_target_physical_apic_id_mask_u {
1741 unsigned long v;
1742 struct uv1h_lb_target_physical_apic_id_mask_s {
1743 unsigned long bit_enables : 32; /* RW */
1744 unsigned long rsvd_32_63 : 32; /* */
1745 } s1;
1746};
1747
1748
1117#endif /* __ASM_UV_MMRS_X86_H__ */ 1749#endif /* __ASM_UV_MMRS_X86_H__ */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f450b683dfcf..b511a011b7d0 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -91,6 +91,10 @@ static int __init early_get_pnodeid(void)
91 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 91 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
92 uv_min_hub_revision_id = node_id.s.revision; 92 uv_min_hub_revision_id = node_id.s.revision;
93 93
94 if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
95 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
96
97 uv_hub_info->hub_revision = uv_min_hub_revision_id;
94 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 98 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
95 return pnode; 99 return pnode;
96} 100}
@@ -112,17 +116,25 @@ static void __init early_get_apic_pnode_shift(void)
112 */ 116 */
113static void __init uv_set_apicid_hibit(void) 117static void __init uv_set_apicid_hibit(void)
114{ 118{
115 union uvh_lb_target_physical_apic_id_mask_u apicid_mask; 119 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
116 120
117 apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK); 121 if (is_uv1_hub()) {
118 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK; 122 apicid_mask.v =
123 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
124 uv_apicid_hibits =
125 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
126 }
119} 127}
120 128
121static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 129static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
122{ 130{
123 int pnodeid; 131 int pnodeid, is_uv1, is_uv2;
124 132
125 if (!strcmp(oem_id, "SGI")) { 133 is_uv1 = !strcmp(oem_id, "SGI");
134 is_uv2 = !strcmp(oem_id, "SGI2");
135 if (is_uv1 || is_uv2) {
136 uv_hub_info->hub_revision =
137 is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
126 pnodeid = early_get_pnodeid(); 138 pnodeid = early_get_pnodeid();
127 early_get_apic_pnode_shift(); 139 early_get_apic_pnode_shift();
128 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 140 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
@@ -484,12 +496,19 @@ static __init void map_mmr_high(int max_pnode)
484static __init void map_mmioh_high(int max_pnode) 496static __init void map_mmioh_high(int max_pnode)
485{ 497{
486 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 498 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
487 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 499 int shift;
488 500
489 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 501 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
490 if (mmioh.s.enable) 502 if (is_uv1_hub() && mmioh.s1.enable) {
491 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io, 503 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
504 map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
505 max_pnode, map_uc);
506 }
507 if (is_uv2_hub() && mmioh.s2.enable) {
508 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
509 map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
492 max_pnode, map_uc); 510 max_pnode, map_uc);
511 }
493} 512}
494 513
495static __init void map_low_mmrs(void) 514static __init void map_low_mmrs(void)
@@ -736,13 +755,14 @@ void __init uv_system_init(void)
736 unsigned long mmr_base, present, paddr; 755 unsigned long mmr_base, present, paddr;
737 unsigned short pnode_mask, pnode_io_mask; 756 unsigned short pnode_mask, pnode_io_mask;
738 757
758 printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
739 map_low_mmrs(); 759 map_low_mmrs();
740 760
741 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 761 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
742 m_val = m_n_config.s.m_skt; 762 m_val = m_n_config.s.m_skt;
743 n_val = m_n_config.s.n_skt; 763 n_val = m_n_config.s.n_skt;
744 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 764 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
745 n_io = mmioh.s.n_io; 765 n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
746 mmr_base = 766 mmr_base =
747 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 767 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
748 ~UV_MMR_ENABLE; 768 ~UV_MMR_ENABLE;
@@ -811,6 +831,8 @@ void __init uv_system_init(void)
811 */ 831 */
812 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 832 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
813 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; 833 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
834 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
835
814 pnode = uv_apicid_to_pnode(apicid); 836 pnode = uv_apicid_to_pnode(apicid);
815 blade = boot_pnode_to_blade(pnode); 837 blade = boot_pnode_to_blade(pnode);
816 lcpu = uv_blade_info[blade].nr_possible_cpus; 838 lcpu = uv_blade_info[blade].nr_possible_cpus;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8f5cabb3c5b0..b13ed393dfce 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -612,8 +612,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
612 } 612 }
613#endif 613#endif
614 614
615 /* As a rule processors have APIC timer running in deep C states */ 615 /*
616 if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400)) 616 * Family 0x12 and above processors have APIC timer
617 * running in deep C states.
618 */
619 if (c->x86 > 0x11)
617 set_cpu_cap(c, X86_FEATURE_ARAT); 620 set_cpu_cap(c, X86_FEATURE_ARAT);
618 621
619 /* 622 /*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c8b41623377f..53f02f5d8cce 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -477,13 +477,6 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
477 if (smp_num_siblings <= 1) 477 if (smp_num_siblings <= 1)
478 goto out; 478 goto out;
479 479
480 if (smp_num_siblings > nr_cpu_ids) {
481 pr_warning("CPU: Unsupported number of siblings %d",
482 smp_num_siblings);
483 smp_num_siblings = 1;
484 return;
485 }
486
487 index_msb = get_count_order(smp_num_siblings); 480 index_msb = get_count_order(smp_num_siblings);
488 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 481 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
489 482
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index a3e5948670c2..afaf38447ef5 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -910,6 +910,13 @@ void __init setup_arch(char **cmdline_p)
910 memblock.current_limit = get_max_mapped(); 910 memblock.current_limit = get_max_mapped();
911 memblock_x86_fill(); 911 memblock_x86_fill();
912 912
913 /*
914 * The EFI specification says that boot service code won't be called
915 * after ExitBootServices(). This is, in fact, a lie.
916 */
917 if (efi_enabled)
918 efi_reserve_boot_services();
919
913 /* preallocate 4k for mptable mpc */ 920 /* preallocate 4k for mptable mpc */
914 early_reserve_e820_mpc_new(); 921 early_reserve_e820_mpc_new();
915 922
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index f7a2a054a3c0..2dbf6bf4c7e5 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -823,16 +823,30 @@ do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address,
823 force_sig_info_fault(SIGBUS, code, address, tsk, fault); 823 force_sig_info_fault(SIGBUS, code, address, tsk, fault);
824} 824}
825 825
826static noinline void 826static noinline int
827mm_fault_error(struct pt_regs *regs, unsigned long error_code, 827mm_fault_error(struct pt_regs *regs, unsigned long error_code,
828 unsigned long address, unsigned int fault) 828 unsigned long address, unsigned int fault)
829{ 829{
830 /*
831 * Pagefault was interrupted by SIGKILL. We have no reason to
832 * continue pagefault.
833 */
834 if (fatal_signal_pending(current)) {
835 if (!(fault & VM_FAULT_RETRY))
836 up_read(&current->mm->mmap_sem);
837 if (!(error_code & PF_USER))
838 no_context(regs, error_code, address);
839 return 1;
840 }
841 if (!(fault & VM_FAULT_ERROR))
842 return 0;
843
830 if (fault & VM_FAULT_OOM) { 844 if (fault & VM_FAULT_OOM) {
831 /* Kernel mode? Handle exceptions or die: */ 845 /* Kernel mode? Handle exceptions or die: */
832 if (!(error_code & PF_USER)) { 846 if (!(error_code & PF_USER)) {
833 up_read(&current->mm->mmap_sem); 847 up_read(&current->mm->mmap_sem);
834 no_context(regs, error_code, address); 848 no_context(regs, error_code, address);
835 return; 849 return 1;
836 } 850 }
837 851
838 out_of_memory(regs, error_code, address); 852 out_of_memory(regs, error_code, address);
@@ -843,6 +857,7 @@ mm_fault_error(struct pt_regs *regs, unsigned long error_code,
843 else 857 else
844 BUG(); 858 BUG();
845 } 859 }
860 return 1;
846} 861}
847 862
848static int spurious_fault_check(unsigned long error_code, pte_t *pte) 863static int spurious_fault_check(unsigned long error_code, pte_t *pte)
@@ -1133,19 +1148,9 @@ good_area:
1133 */ 1148 */
1134 fault = handle_mm_fault(mm, vma, address, flags); 1149 fault = handle_mm_fault(mm, vma, address, flags);
1135 1150
1136 if (unlikely(fault & VM_FAULT_ERROR)) { 1151 if (unlikely(fault & (VM_FAULT_RETRY|VM_FAULT_ERROR))) {
1137 mm_fault_error(regs, error_code, address, fault); 1152 if (mm_fault_error(regs, error_code, address, fault))
1138 return; 1153 return;
1139 }
1140
1141 /*
1142 * Pagefault was interrupted by SIGKILL. We have no reason to
1143 * continue pagefault.
1144 */
1145 if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {
1146 if (!(error_code & PF_USER))
1147 no_context(regs, error_code, address);
1148 return;
1149 } 1154 }
1150 1155
1151 /* 1156 /*
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index b30aa26a8df2..0d3a4fa34560 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -304,6 +304,40 @@ static void __init print_efi_memmap(void)
304} 304}
305#endif /* EFI_DEBUG */ 305#endif /* EFI_DEBUG */
306 306
307void __init efi_reserve_boot_services(void)
308{
309 void *p;
310
311 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
312 efi_memory_desc_t *md = p;
313 unsigned long long start = md->phys_addr;
314 unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
315
316 if (md->type != EFI_BOOT_SERVICES_CODE &&
317 md->type != EFI_BOOT_SERVICES_DATA)
318 continue;
319
320 memblock_x86_reserve_range(start, start + size, "EFI Boot");
321 }
322}
323
324static void __init efi_free_boot_services(void)
325{
326 void *p;
327
328 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
329 efi_memory_desc_t *md = p;
330 unsigned long long start = md->phys_addr;
331 unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
332
333 if (md->type != EFI_BOOT_SERVICES_CODE &&
334 md->type != EFI_BOOT_SERVICES_DATA)
335 continue;
336
337 free_bootmem_late(start, size);
338 }
339}
340
307void __init efi_init(void) 341void __init efi_init(void)
308{ 342{
309 efi_config_table_t *config_tables; 343 efi_config_table_t *config_tables;
@@ -536,7 +570,9 @@ void __init efi_enter_virtual_mode(void)
536 570
537 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 571 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
538 md = p; 572 md = p;
539 if (!(md->attribute & EFI_MEMORY_RUNTIME)) 573 if (!(md->attribute & EFI_MEMORY_RUNTIME) &&
574 md->type != EFI_BOOT_SERVICES_CODE &&
575 md->type != EFI_BOOT_SERVICES_DATA)
540 continue; 576 continue;
541 577
542 size = md->num_pages << EFI_PAGE_SHIFT; 578 size = md->num_pages << EFI_PAGE_SHIFT;
@@ -593,6 +629,13 @@ void __init efi_enter_virtual_mode(void)
593 } 629 }
594 630
595 /* 631 /*
632 * Thankfully, it does seem that no runtime services other than
633 * SetVirtualAddressMap() will touch boot services code, so we can
634 * get rid of it all at this point
635 */
636 efi_free_boot_services();
637
638 /*
596 * Now that EFI is in virtual mode, update the function 639 * Now that EFI is in virtual mode, update the function
597 * pointers in the runtime service table to the new virtual addresses. 640 * pointers in the runtime service table to the new virtual addresses.
598 * 641 *
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 2649426a7905..ac3aa54e2654 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -49,10 +49,11 @@ static void __init early_code_mapping_set_exec(int executable)
49 if (!(__supported_pte_mask & _PAGE_NX)) 49 if (!(__supported_pte_mask & _PAGE_NX))
50 return; 50 return;
51 51
52 /* Make EFI runtime service code area executable */ 52 /* Make EFI service code area executable */
53 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 53 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
54 md = p; 54 md = p;
55 if (md->type == EFI_RUNTIME_SERVICES_CODE) 55 if (md->type == EFI_RUNTIME_SERVICES_CODE ||
56 md->type == EFI_BOOT_SERVICES_CODE)
56 efi_set_executable(md, executable); 57 efi_set_executable(md, executable);
57 } 58 }
58} 59}
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index c58e0ea39ef5..68e467f69fec 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SGI UltraViolet TLB flush routines. 2 * SGI UltraViolet TLB flush routines.
3 * 3 *
4 * (c) 2008-2010 Cliff Wickman <cpw@sgi.com>, SGI. 4 * (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI.
5 * 5 *
6 * This code is released under the GNU General Public License version 2 or 6 * This code is released under the GNU General Public License version 2 or
7 * later. 7 * later.
@@ -35,6 +35,7 @@ static int timeout_base_ns[] = {
35 5242880, 35 5242880,
36 167772160 36 167772160
37}; 37};
38
38static int timeout_us; 39static int timeout_us;
39static int nobau; 40static int nobau;
40static int baudisabled; 41static int baudisabled;
@@ -42,20 +43,70 @@ static spinlock_t disable_lock;
42static cycles_t congested_cycles; 43static cycles_t congested_cycles;
43 44
44/* tunables: */ 45/* tunables: */
45static int max_bau_concurrent = MAX_BAU_CONCURRENT; 46static int max_concurr = MAX_BAU_CONCURRENT;
46static int max_bau_concurrent_constant = MAX_BAU_CONCURRENT; 47static int max_concurr_const = MAX_BAU_CONCURRENT;
47static int plugged_delay = PLUGGED_DELAY; 48static int plugged_delay = PLUGGED_DELAY;
48static int plugsb4reset = PLUGSB4RESET; 49static int plugsb4reset = PLUGSB4RESET;
49static int timeoutsb4reset = TIMEOUTSB4RESET; 50static int timeoutsb4reset = TIMEOUTSB4RESET;
50static int ipi_reset_limit = IPI_RESET_LIMIT; 51static int ipi_reset_limit = IPI_RESET_LIMIT;
51static int complete_threshold = COMPLETE_THRESHOLD; 52static int complete_threshold = COMPLETE_THRESHOLD;
52static int congested_response_us = CONGESTED_RESPONSE_US; 53static int congested_respns_us = CONGESTED_RESPONSE_US;
53static int congested_reps = CONGESTED_REPS; 54static int congested_reps = CONGESTED_REPS;
54static int congested_period = CONGESTED_PERIOD; 55static int congested_period = CONGESTED_PERIOD;
56
57static struct tunables tunables[] = {
58 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
59 {&plugged_delay, PLUGGED_DELAY},
60 {&plugsb4reset, PLUGSB4RESET},
61 {&timeoutsb4reset, TIMEOUTSB4RESET},
62 {&ipi_reset_limit, IPI_RESET_LIMIT},
63 {&complete_threshold, COMPLETE_THRESHOLD},
64 {&congested_respns_us, CONGESTED_RESPONSE_US},
65 {&congested_reps, CONGESTED_REPS},
66 {&congested_period, CONGESTED_PERIOD}
67};
68
55static struct dentry *tunables_dir; 69static struct dentry *tunables_dir;
56static struct dentry *tunables_file; 70static struct dentry *tunables_file;
57 71
58static int __init setup_nobau(char *arg) 72/* these correspond to the statistics printed by ptc_seq_show() */
73static char *stat_description[] = {
74 "sent: number of shootdown messages sent",
75 "stime: time spent sending messages",
76 "numuvhubs: number of hubs targeted with shootdown",
77 "numuvhubs16: number times 16 or more hubs targeted",
78 "numuvhubs8: number times 8 or more hubs targeted",
79 "numuvhubs4: number times 4 or more hubs targeted",
80 "numuvhubs2: number times 2 or more hubs targeted",
81 "numuvhubs1: number times 1 hub targeted",
82 "numcpus: number of cpus targeted with shootdown",
83 "dto: number of destination timeouts",
84 "retries: destination timeout retries sent",
85 "rok: : destination timeouts successfully retried",
86 "resetp: ipi-style resource resets for plugs",
87 "resett: ipi-style resource resets for timeouts",
88 "giveup: fall-backs to ipi-style shootdowns",
89 "sto: number of source timeouts",
90 "bz: number of stay-busy's",
91 "throt: number times spun in throttle",
92 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
93 "recv: shootdown messages received",
94 "rtime: time spent processing messages",
95 "all: shootdown all-tlb messages",
96 "one: shootdown one-tlb messages",
97 "mult: interrupts that found multiple messages",
98 "none: interrupts that found no messages",
99 "retry: number of retry messages processed",
100 "canc: number messages canceled by retries",
101 "nocan: number retries that found nothing to cancel",
102 "reset: number of ipi-style reset requests processed",
103 "rcan: number messages canceled by reset requests",
104 "disable: number times use of the BAU was disabled",
105 "enable: number times use of the BAU was re-enabled"
106};
107
108static int __init
109setup_nobau(char *arg)
59{ 110{
60 nobau = 1; 111 nobau = 1;
61 return 0; 112 return 0;
@@ -63,7 +114,7 @@ static int __init setup_nobau(char *arg)
63early_param("nobau", setup_nobau); 114early_param("nobau", setup_nobau);
64 115
65/* base pnode in this partition */ 116/* base pnode in this partition */
66static int uv_partition_base_pnode __read_mostly; 117static int uv_base_pnode __read_mostly;
67/* position of pnode (which is nasid>>1): */ 118/* position of pnode (which is nasid>>1): */
68static int uv_nshift __read_mostly; 119static int uv_nshift __read_mostly;
69static unsigned long uv_mmask __read_mostly; 120static unsigned long uv_mmask __read_mostly;
@@ -109,60 +160,52 @@ static int __init uvhub_to_first_apicid(int uvhub)
109 * clear of the Timeout bit (as well) will free the resource. No reply will 160 * clear of the Timeout bit (as well) will free the resource. No reply will
110 * be sent (the hardware will only do one reply per message). 161 * be sent (the hardware will only do one reply per message).
111 */ 162 */
112static inline void uv_reply_to_message(struct msg_desc *mdp, 163static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp)
113 struct bau_control *bcp)
114{ 164{
115 unsigned long dw; 165 unsigned long dw;
116 struct bau_payload_queue_entry *msg; 166 struct bau_pq_entry *msg;
117 167
118 msg = mdp->msg; 168 msg = mdp->msg;
119 if (!msg->canceled) { 169 if (!msg->canceled) {
120 dw = (msg->sw_ack_vector << UV_SW_ACK_NPENDING) | 170 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
121 msg->sw_ack_vector; 171 write_mmr_sw_ack(dw);
122 uv_write_local_mmr(
123 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
124 } 172 }
125 msg->replied_to = 1; 173 msg->replied_to = 1;
126 msg->sw_ack_vector = 0; 174 msg->swack_vec = 0;
127} 175}
128 176
129/* 177/*
130 * Process the receipt of a RETRY message 178 * Process the receipt of a RETRY message
131 */ 179 */
132static inline void uv_bau_process_retry_msg(struct msg_desc *mdp, 180static void bau_process_retry_msg(struct msg_desc *mdp,
133 struct bau_control *bcp) 181 struct bau_control *bcp)
134{ 182{
135 int i; 183 int i;
136 int cancel_count = 0; 184 int cancel_count = 0;
137 int slot2;
138 unsigned long msg_res; 185 unsigned long msg_res;
139 unsigned long mmr = 0; 186 unsigned long mmr = 0;
140 struct bau_payload_queue_entry *msg; 187 struct bau_pq_entry *msg = mdp->msg;
141 struct bau_payload_queue_entry *msg2; 188 struct bau_pq_entry *msg2;
142 struct ptc_stats *stat; 189 struct ptc_stats *stat = bcp->statp;
143 190
144 msg = mdp->msg;
145 stat = bcp->statp;
146 stat->d_retries++; 191 stat->d_retries++;
147 /* 192 /*
148 * cancel any message from msg+1 to the retry itself 193 * cancel any message from msg+1 to the retry itself
149 */ 194 */
150 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { 195 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
151 if (msg2 > mdp->va_queue_last) 196 if (msg2 > mdp->queue_last)
152 msg2 = mdp->va_queue_first; 197 msg2 = mdp->queue_first;
153 if (msg2 == msg) 198 if (msg2 == msg)
154 break; 199 break;
155 200
156 /* same conditions for cancellation as uv_do_reset */ 201 /* same conditions for cancellation as do_reset */
157 if ((msg2->replied_to == 0) && (msg2->canceled == 0) && 202 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
158 (msg2->sw_ack_vector) && ((msg2->sw_ack_vector & 203 (msg2->swack_vec) && ((msg2->swack_vec &
159 msg->sw_ack_vector) == 0) && 204 msg->swack_vec) == 0) &&
160 (msg2->sending_cpu == msg->sending_cpu) && 205 (msg2->sending_cpu == msg->sending_cpu) &&
161 (msg2->msg_type != MSG_NOOP)) { 206 (msg2->msg_type != MSG_NOOP)) {
162 slot2 = msg2 - mdp->va_queue_first; 207 mmr = read_mmr_sw_ack();
163 mmr = uv_read_local_mmr 208 msg_res = msg2->swack_vec;
164 (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
165 msg_res = msg2->sw_ack_vector;
166 /* 209 /*
167 * This is a message retry; clear the resources held 210 * This is a message retry; clear the resources held
168 * by the previous message only if they timed out. 211 * by the previous message only if they timed out.
@@ -170,6 +213,7 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
170 * situation to report. 213 * situation to report.
171 */ 214 */
172 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { 215 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
216 unsigned long mr;
173 /* 217 /*
174 * is the resource timed out? 218 * is the resource timed out?
175 * make everyone ignore the cancelled message. 219 * make everyone ignore the cancelled message.
@@ -177,10 +221,8 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
177 msg2->canceled = 1; 221 msg2->canceled = 1;
178 stat->d_canceled++; 222 stat->d_canceled++;
179 cancel_count++; 223 cancel_count++;
180 uv_write_local_mmr( 224 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
181 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, 225 write_mmr_sw_ack(mr);
182 (msg_res << UV_SW_ACK_NPENDING) |
183 msg_res);
184 } 226 }
185 } 227 }
186 } 228 }
@@ -192,20 +234,19 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
192 * Do all the things a cpu should do for a TLB shootdown message. 234 * Do all the things a cpu should do for a TLB shootdown message.
193 * Other cpu's may come here at the same time for this message. 235 * Other cpu's may come here at the same time for this message.
194 */ 236 */
195static void uv_bau_process_message(struct msg_desc *mdp, 237static void bau_process_message(struct msg_desc *mdp,
196 struct bau_control *bcp) 238 struct bau_control *bcp)
197{ 239{
198 int msg_ack_count;
199 short socket_ack_count = 0; 240 short socket_ack_count = 0;
200 struct ptc_stats *stat; 241 short *sp;
201 struct bau_payload_queue_entry *msg; 242 struct atomic_short *asp;
243 struct ptc_stats *stat = bcp->statp;
244 struct bau_pq_entry *msg = mdp->msg;
202 struct bau_control *smaster = bcp->socket_master; 245 struct bau_control *smaster = bcp->socket_master;
203 246
204 /* 247 /*
205 * This must be a normal message, or retry of a normal message 248 * This must be a normal message, or retry of a normal message
206 */ 249 */
207 msg = mdp->msg;
208 stat = bcp->statp;
209 if (msg->address == TLB_FLUSH_ALL) { 250 if (msg->address == TLB_FLUSH_ALL) {
210 local_flush_tlb(); 251 local_flush_tlb();
211 stat->d_alltlb++; 252 stat->d_alltlb++;
@@ -222,30 +263,32 @@ static void uv_bau_process_message(struct msg_desc *mdp,
222 * cpu number. 263 * cpu number.
223 */ 264 */
224 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) 265 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
225 uv_bau_process_retry_msg(mdp, bcp); 266 bau_process_retry_msg(mdp, bcp);
226 267
227 /* 268 /*
228 * This is a sw_ack message, so we have to reply to it. 269 * This is a swack message, so we have to reply to it.
229 * Count each responding cpu on the socket. This avoids 270 * Count each responding cpu on the socket. This avoids
230 * pinging the count's cache line back and forth between 271 * pinging the count's cache line back and forth between
231 * the sockets. 272 * the sockets.
232 */ 273 */
233 socket_ack_count = atomic_add_short_return(1, (struct atomic_short *) 274 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
234 &smaster->socket_acknowledge_count[mdp->msg_slot]); 275 asp = (struct atomic_short *)sp;
276 socket_ack_count = atom_asr(1, asp);
235 if (socket_ack_count == bcp->cpus_in_socket) { 277 if (socket_ack_count == bcp->cpus_in_socket) {
278 int msg_ack_count;
236 /* 279 /*
237 * Both sockets dump their completed count total into 280 * Both sockets dump their completed count total into
238 * the message's count. 281 * the message's count.
239 */ 282 */
240 smaster->socket_acknowledge_count[mdp->msg_slot] = 0; 283 smaster->socket_acknowledge_count[mdp->msg_slot] = 0;
241 msg_ack_count = atomic_add_short_return(socket_ack_count, 284 asp = (struct atomic_short *)&msg->acknowledge_count;
242 (struct atomic_short *)&msg->acknowledge_count); 285 msg_ack_count = atom_asr(socket_ack_count, asp);
243 286
244 if (msg_ack_count == bcp->cpus_in_uvhub) { 287 if (msg_ack_count == bcp->cpus_in_uvhub) {
245 /* 288 /*
246 * All cpus in uvhub saw it; reply 289 * All cpus in uvhub saw it; reply
247 */ 290 */
248 uv_reply_to_message(mdp, bcp); 291 reply_to_message(mdp, bcp);
249 } 292 }
250 } 293 }
251 294
@@ -268,62 +311,51 @@ static int uvhub_to_first_cpu(int uvhub)
268 * Last resort when we get a large number of destination timeouts is 311 * Last resort when we get a large number of destination timeouts is
269 * to clear resources held by a given cpu. 312 * to clear resources held by a given cpu.
270 * Do this with IPI so that all messages in the BAU message queue 313 * Do this with IPI so that all messages in the BAU message queue
271 * can be identified by their nonzero sw_ack_vector field. 314 * can be identified by their nonzero swack_vec field.
272 * 315 *
273 * This is entered for a single cpu on the uvhub. 316 * This is entered for a single cpu on the uvhub.
274 * The sender want's this uvhub to free a specific message's 317 * The sender want's this uvhub to free a specific message's
275 * sw_ack resources. 318 * swack resources.
276 */ 319 */
277static void 320static void do_reset(void *ptr)
278uv_do_reset(void *ptr)
279{ 321{
280 int i; 322 int i;
281 int slot; 323 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
282 int count = 0; 324 struct reset_args *rap = (struct reset_args *)ptr;
283 unsigned long mmr; 325 struct bau_pq_entry *msg;
284 unsigned long msg_res; 326 struct ptc_stats *stat = bcp->statp;
285 struct bau_control *bcp;
286 struct reset_args *rap;
287 struct bau_payload_queue_entry *msg;
288 struct ptc_stats *stat;
289 327
290 bcp = &per_cpu(bau_control, smp_processor_id());
291 rap = (struct reset_args *)ptr;
292 stat = bcp->statp;
293 stat->d_resets++; 328 stat->d_resets++;
294
295 /* 329 /*
296 * We're looking for the given sender, and 330 * We're looking for the given sender, and
297 * will free its sw_ack resource. 331 * will free its swack resource.
298 * If all cpu's finally responded after the timeout, its 332 * If all cpu's finally responded after the timeout, its
299 * message 'replied_to' was set. 333 * message 'replied_to' was set.
300 */ 334 */
301 for (msg = bcp->va_queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { 335 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
302 /* uv_do_reset: same conditions for cancellation as 336 unsigned long msg_res;
303 uv_bau_process_retry_msg() */ 337 /* do_reset: same conditions for cancellation as
338 bau_process_retry_msg() */
304 if ((msg->replied_to == 0) && 339 if ((msg->replied_to == 0) &&
305 (msg->canceled == 0) && 340 (msg->canceled == 0) &&
306 (msg->sending_cpu == rap->sender) && 341 (msg->sending_cpu == rap->sender) &&
307 (msg->sw_ack_vector) && 342 (msg->swack_vec) &&
308 (msg->msg_type != MSG_NOOP)) { 343 (msg->msg_type != MSG_NOOP)) {
344 unsigned long mmr;
345 unsigned long mr;
309 /* 346 /*
310 * make everyone else ignore this message 347 * make everyone else ignore this message
311 */ 348 */
312 msg->canceled = 1; 349 msg->canceled = 1;
313 slot = msg - bcp->va_queue_first;
314 count++;
315 /* 350 /*
316 * only reset the resource if it is still pending 351 * only reset the resource if it is still pending
317 */ 352 */
318 mmr = uv_read_local_mmr 353 mmr = read_mmr_sw_ack();
319 (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 354 msg_res = msg->swack_vec;
320 msg_res = msg->sw_ack_vector; 355 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
321 if (mmr & msg_res) { 356 if (mmr & msg_res) {
322 stat->d_rcanceled++; 357 stat->d_rcanceled++;
323 uv_write_local_mmr( 358 write_mmr_sw_ack(mr);
324 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS,
325 (msg_res << UV_SW_ACK_NPENDING) |
326 msg_res);
327 } 359 }
328 } 360 }
329 } 361 }
@@ -334,39 +366,38 @@ uv_do_reset(void *ptr)
334 * Use IPI to get all target uvhubs to release resources held by 366 * Use IPI to get all target uvhubs to release resources held by
335 * a given sending cpu number. 367 * a given sending cpu number.
336 */ 368 */
337static void uv_reset_with_ipi(struct bau_target_uvhubmask *distribution, 369static void reset_with_ipi(struct bau_targ_hubmask *distribution, int sender)
338 int sender)
339{ 370{
340 int uvhub; 371 int uvhub;
341 int cpu; 372 int maskbits;
342 cpumask_t mask; 373 cpumask_t mask;
343 struct reset_args reset_args; 374 struct reset_args reset_args;
344 375
345 reset_args.sender = sender; 376 reset_args.sender = sender;
346
347 cpus_clear(mask); 377 cpus_clear(mask);
348 /* find a single cpu for each uvhub in this distribution mask */ 378 /* find a single cpu for each uvhub in this distribution mask */
349 for (uvhub = 0; 379 maskbits = sizeof(struct bau_targ_hubmask) * BITSPERBYTE;
350 uvhub < sizeof(struct bau_target_uvhubmask) * BITSPERBYTE; 380 for (uvhub = 0; uvhub < maskbits; uvhub++) {
351 uvhub++) { 381 int cpu;
352 if (!bau_uvhub_isset(uvhub, distribution)) 382 if (!bau_uvhub_isset(uvhub, distribution))
353 continue; 383 continue;
354 /* find a cpu for this uvhub */ 384 /* find a cpu for this uvhub */
355 cpu = uvhub_to_first_cpu(uvhub); 385 cpu = uvhub_to_first_cpu(uvhub);
356 cpu_set(cpu, mask); 386 cpu_set(cpu, mask);
357 } 387 }
358 /* IPI all cpus; Preemption is already disabled */ 388
359 smp_call_function_many(&mask, uv_do_reset, (void *)&reset_args, 1); 389 /* IPI all cpus; preemption is already disabled */
390 smp_call_function_many(&mask, do_reset, (void *)&reset_args, 1);
360 return; 391 return;
361} 392}
362 393
363static inline unsigned long 394static inline unsigned long cycles_2_us(unsigned long long cyc)
364cycles_2_us(unsigned long long cyc)
365{ 395{
366 unsigned long long ns; 396 unsigned long long ns;
367 unsigned long us; 397 unsigned long us;
368 ns = (cyc * per_cpu(cyc2ns, smp_processor_id())) 398 int cpu = smp_processor_id();
369 >> CYC2NS_SCALE_FACTOR; 399
400 ns = (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR;
370 us = ns / 1000; 401 us = ns / 1000;
371 return us; 402 return us;
372} 403}
@@ -376,56 +407,56 @@ cycles_2_us(unsigned long long cyc)
376 * leaves uvhub_quiesce set so that no new broadcasts are started by 407 * leaves uvhub_quiesce set so that no new broadcasts are started by
377 * bau_flush_send_and_wait() 408 * bau_flush_send_and_wait()
378 */ 409 */
379static inline void 410static inline void quiesce_local_uvhub(struct bau_control *hmaster)
380quiesce_local_uvhub(struct bau_control *hmaster)
381{ 411{
382 atomic_add_short_return(1, (struct atomic_short *) 412 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
383 &hmaster->uvhub_quiesce);
384} 413}
385 414
386/* 415/*
387 * mark this quiet-requestor as done 416 * mark this quiet-requestor as done
388 */ 417 */
389static inline void 418static inline void end_uvhub_quiesce(struct bau_control *hmaster)
390end_uvhub_quiesce(struct bau_control *hmaster)
391{ 419{
392 atomic_add_short_return(-1, (struct atomic_short *) 420 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
393 &hmaster->uvhub_quiesce); 421}
422
423static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
424{
425 unsigned long descriptor_status;
426
427 descriptor_status = uv_read_local_mmr(mmr_offset);
428 descriptor_status >>= right_shift;
429 descriptor_status &= UV_ACT_STATUS_MASK;
430 return descriptor_status;
394} 431}
395 432
396/* 433/*
397 * Wait for completion of a broadcast software ack message 434 * Wait for completion of a broadcast software ack message
398 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP 435 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
399 */ 436 */
400static int uv_wait_completion(struct bau_desc *bau_desc, 437static int uv1_wait_completion(struct bau_desc *bau_desc,
401 unsigned long mmr_offset, int right_shift, int this_cpu, 438 unsigned long mmr_offset, int right_shift,
402 struct bau_control *bcp, struct bau_control *smaster, long try) 439 struct bau_control *bcp, long try)
403{ 440{
404 unsigned long descriptor_status; 441 unsigned long descriptor_status;
405 cycles_t ttime; 442 cycles_t ttm;
406 struct ptc_stats *stat = bcp->statp; 443 struct ptc_stats *stat = bcp->statp;
407 struct bau_control *hmaster;
408
409 hmaster = bcp->uvhub_master;
410 444
445 descriptor_status = uv1_read_status(mmr_offset, right_shift);
411 /* spin on the status MMR, waiting for it to go idle */ 446 /* spin on the status MMR, waiting for it to go idle */
412 while ((descriptor_status = (((unsigned long) 447 while ((descriptor_status != DS_IDLE)) {
413 uv_read_local_mmr(mmr_offset) >>
414 right_shift) & UV_ACT_STATUS_MASK)) !=
415 DESC_STATUS_IDLE) {
416 /* 448 /*
417 * Our software ack messages may be blocked because there are 449 * Our software ack messages may be blocked because
418 * no swack resources available. As long as none of them 450 * there are no swack resources available. As long
419 * has timed out hardware will NACK our message and its 451 * as none of them has timed out hardware will NACK
420 * state will stay IDLE. 452 * our message and its state will stay IDLE.
421 */ 453 */
422 if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) { 454 if (descriptor_status == DS_SOURCE_TIMEOUT) {
423 stat->s_stimeout++; 455 stat->s_stimeout++;
424 return FLUSH_GIVEUP; 456 return FLUSH_GIVEUP;
425 } else if (descriptor_status == 457 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
426 DESC_STATUS_DESTINATION_TIMEOUT) {
427 stat->s_dtimeout++; 458 stat->s_dtimeout++;
428 ttime = get_cycles(); 459 ttm = get_cycles();
429 460
430 /* 461 /*
431 * Our retries may be blocked by all destination 462 * Our retries may be blocked by all destination
@@ -433,8 +464,7 @@ static int uv_wait_completion(struct bau_desc *bau_desc,
433 * pending. In that case hardware returns the 464 * pending. In that case hardware returns the
434 * ERROR that looks like a destination timeout. 465 * ERROR that looks like a destination timeout.
435 */ 466 */
436 if (cycles_2_us(ttime - bcp->send_message) < 467 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
437 timeout_us) {
438 bcp->conseccompletes = 0; 468 bcp->conseccompletes = 0;
439 return FLUSH_RETRY_PLUGGED; 469 return FLUSH_RETRY_PLUGGED;
440 } 470 }
@@ -447,80 +477,160 @@ static int uv_wait_completion(struct bau_desc *bau_desc,
447 */ 477 */
448 cpu_relax(); 478 cpu_relax();
449 } 479 }
480 descriptor_status = uv1_read_status(mmr_offset, right_shift);
450 } 481 }
451 bcp->conseccompletes++; 482 bcp->conseccompletes++;
452 return FLUSH_COMPLETE; 483 return FLUSH_COMPLETE;
453} 484}
454 485
455static inline cycles_t 486/*
456sec_2_cycles(unsigned long sec) 487 * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register.
488 */
489static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu)
457{ 490{
458 unsigned long ns; 491 unsigned long descriptor_status;
459 cycles_t cyc; 492 unsigned long descriptor_status2;
460 493
461 ns = sec * 1000000000; 494 descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK);
462 cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id())); 495 descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL;
463 return cyc; 496 descriptor_status = (descriptor_status << 1) | descriptor_status2;
497 return descriptor_status;
498}
499
500static int uv2_wait_completion(struct bau_desc *bau_desc,
501 unsigned long mmr_offset, int right_shift,
502 struct bau_control *bcp, long try)
503{
504 unsigned long descriptor_stat;
505 cycles_t ttm;
506 int cpu = bcp->uvhub_cpu;
507 struct ptc_stats *stat = bcp->statp;
508
509 descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu);
510
511 /* spin on the status MMR, waiting for it to go idle */
512 while (descriptor_stat != UV2H_DESC_IDLE) {
513 /*
514 * Our software ack messages may be blocked because
515 * there are no swack resources available. As long
516 * as none of them has timed out hardware will NACK
517 * our message and its state will stay IDLE.
518 */
519 if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) ||
520 (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) ||
521 (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) {
522 stat->s_stimeout++;
523 return FLUSH_GIVEUP;
524 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
525 stat->s_dtimeout++;
526 ttm = get_cycles();
527 /*
528 * Our retries may be blocked by all destination
529 * swack resources being consumed, and a timeout
530 * pending. In that case hardware returns the
531 * ERROR that looks like a destination timeout.
532 */
533 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
534 bcp->conseccompletes = 0;
535 return FLUSH_RETRY_PLUGGED;
536 }
537 bcp->conseccompletes = 0;
538 return FLUSH_RETRY_TIMEOUT;
539 } else {
540 /*
541 * descriptor_stat is still BUSY
542 */
543 cpu_relax();
544 }
545 descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu);
546 }
547 bcp->conseccompletes++;
548 return FLUSH_COMPLETE;
464} 549}
465 550
466/* 551/*
467 * conditionally add 1 to *v, unless *v is >= u 552 * There are 2 status registers; each and array[32] of 2 bits. Set up for
468 * return 0 if we cannot add 1 to *v because it is >= u 553 * which register to read and position in that register based on cpu in
469 * return 1 if we can add 1 to *v because it is < u 554 * current hub.
470 * the add is atomic
471 *
472 * This is close to atomic_add_unless(), but this allows the 'u' value
473 * to be lowered below the current 'v'. atomic_add_unless can only stop
474 * on equal.
475 */ 555 */
476static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u) 556static int wait_completion(struct bau_desc *bau_desc,
557 struct bau_control *bcp, long try)
477{ 558{
478 spin_lock(lock); 559 int right_shift;
479 if (atomic_read(v) >= u) { 560 unsigned long mmr_offset;
480 spin_unlock(lock); 561 int cpu = bcp->uvhub_cpu;
481 return 0; 562
563 if (cpu < UV_CPUS_PER_AS) {
564 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
565 right_shift = cpu * UV_ACT_STATUS_SIZE;
566 } else {
567 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
568 right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
482 } 569 }
483 atomic_inc(v); 570
484 spin_unlock(lock); 571 if (is_uv1_hub())
485 return 1; 572 return uv1_wait_completion(bau_desc, mmr_offset, right_shift,
573 bcp, try);
574 else
575 return uv2_wait_completion(bau_desc, mmr_offset, right_shift,
576 bcp, try);
577}
578
579static inline cycles_t sec_2_cycles(unsigned long sec)
580{
581 unsigned long ns;
582 cycles_t cyc;
583
584 ns = sec * 1000000000;
585 cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
586 return cyc;
486} 587}
487 588
488/* 589/*
489 * Our retries are blocked by all destination swack resources being 590 * Our retries are blocked by all destination sw ack resources being
490 * in use, and a timeout is pending. In that case hardware immediately 591 * in use, and a timeout is pending. In that case hardware immediately
491 * returns the ERROR that looks like a destination timeout. 592 * returns the ERROR that looks like a destination timeout.
492 */ 593 */
493static void 594static void destination_plugged(struct bau_desc *bau_desc,
494destination_plugged(struct bau_desc *bau_desc, struct bau_control *bcp, 595 struct bau_control *bcp,
495 struct bau_control *hmaster, struct ptc_stats *stat) 596 struct bau_control *hmaster, struct ptc_stats *stat)
496{ 597{
497 udelay(bcp->plugged_delay); 598 udelay(bcp->plugged_delay);
498 bcp->plugged_tries++; 599 bcp->plugged_tries++;
600
499 if (bcp->plugged_tries >= bcp->plugsb4reset) { 601 if (bcp->plugged_tries >= bcp->plugsb4reset) {
500 bcp->plugged_tries = 0; 602 bcp->plugged_tries = 0;
603
501 quiesce_local_uvhub(hmaster); 604 quiesce_local_uvhub(hmaster);
605
502 spin_lock(&hmaster->queue_lock); 606 spin_lock(&hmaster->queue_lock);
503 uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu); 607 reset_with_ipi(&bau_desc->distribution, bcp->cpu);
504 spin_unlock(&hmaster->queue_lock); 608 spin_unlock(&hmaster->queue_lock);
609
505 end_uvhub_quiesce(hmaster); 610 end_uvhub_quiesce(hmaster);
611
506 bcp->ipi_attempts++; 612 bcp->ipi_attempts++;
507 stat->s_resets_plug++; 613 stat->s_resets_plug++;
508 } 614 }
509} 615}
510 616
511static void 617static void destination_timeout(struct bau_desc *bau_desc,
512destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp, 618 struct bau_control *bcp, struct bau_control *hmaster,
513 struct bau_control *hmaster, struct ptc_stats *stat) 619 struct ptc_stats *stat)
514{ 620{
515 hmaster->max_bau_concurrent = 1; 621 hmaster->max_concurr = 1;
516 bcp->timeout_tries++; 622 bcp->timeout_tries++;
517 if (bcp->timeout_tries >= bcp->timeoutsb4reset) { 623 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
518 bcp->timeout_tries = 0; 624 bcp->timeout_tries = 0;
625
519 quiesce_local_uvhub(hmaster); 626 quiesce_local_uvhub(hmaster);
627
520 spin_lock(&hmaster->queue_lock); 628 spin_lock(&hmaster->queue_lock);
521 uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu); 629 reset_with_ipi(&bau_desc->distribution, bcp->cpu);
522 spin_unlock(&hmaster->queue_lock); 630 spin_unlock(&hmaster->queue_lock);
631
523 end_uvhub_quiesce(hmaster); 632 end_uvhub_quiesce(hmaster);
633
524 bcp->ipi_attempts++; 634 bcp->ipi_attempts++;
525 stat->s_resets_timeout++; 635 stat->s_resets_timeout++;
526 } 636 }
@@ -530,34 +640,104 @@ destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp,
530 * Completions are taking a very long time due to a congested numalink 640 * Completions are taking a very long time due to a congested numalink
531 * network. 641 * network.
532 */ 642 */
533static void 643static void disable_for_congestion(struct bau_control *bcp,
534disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat) 644 struct ptc_stats *stat)
535{ 645{
536 int tcpu;
537 struct bau_control *tbcp;
538
539 /* let only one cpu do this disabling */ 646 /* let only one cpu do this disabling */
540 spin_lock(&disable_lock); 647 spin_lock(&disable_lock);
648
541 if (!baudisabled && bcp->period_requests && 649 if (!baudisabled && bcp->period_requests &&
542 ((bcp->period_time / bcp->period_requests) > congested_cycles)) { 650 ((bcp->period_time / bcp->period_requests) > congested_cycles)) {
651 int tcpu;
652 struct bau_control *tbcp;
543 /* it becomes this cpu's job to turn on the use of the 653 /* it becomes this cpu's job to turn on the use of the
544 BAU again */ 654 BAU again */
545 baudisabled = 1; 655 baudisabled = 1;
546 bcp->set_bau_off = 1; 656 bcp->set_bau_off = 1;
547 bcp->set_bau_on_time = get_cycles() + 657 bcp->set_bau_on_time = get_cycles();
548 sec_2_cycles(bcp->congested_period); 658 bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period);
549 stat->s_bau_disabled++; 659 stat->s_bau_disabled++;
550 for_each_present_cpu(tcpu) { 660 for_each_present_cpu(tcpu) {
551 tbcp = &per_cpu(bau_control, tcpu); 661 tbcp = &per_cpu(bau_control, tcpu);
552 tbcp->baudisabled = 1; 662 tbcp->baudisabled = 1;
553 } 663 }
554 } 664 }
665
555 spin_unlock(&disable_lock); 666 spin_unlock(&disable_lock);
556} 667}
557 668
558/** 669static void count_max_concurr(int stat, struct bau_control *bcp,
559 * uv_flush_send_and_wait 670 struct bau_control *hmaster)
560 * 671{
672 bcp->plugged_tries = 0;
673 bcp->timeout_tries = 0;
674 if (stat != FLUSH_COMPLETE)
675 return;
676 if (bcp->conseccompletes <= bcp->complete_threshold)
677 return;
678 if (hmaster->max_concurr >= hmaster->max_concurr_const)
679 return;
680 hmaster->max_concurr++;
681}
682
683static void record_send_stats(cycles_t time1, cycles_t time2,
684 struct bau_control *bcp, struct ptc_stats *stat,
685 int completion_status, int try)
686{
687 cycles_t elapsed;
688
689 if (time2 > time1) {
690 elapsed = time2 - time1;
691 stat->s_time += elapsed;
692
693 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
694 bcp->period_requests++;
695 bcp->period_time += elapsed;
696 if ((elapsed > congested_cycles) &&
697 (bcp->period_requests > bcp->cong_reps))
698 disable_for_congestion(bcp, stat);
699 }
700 } else
701 stat->s_requestor--;
702
703 if (completion_status == FLUSH_COMPLETE && try > 1)
704 stat->s_retriesok++;
705 else if (completion_status == FLUSH_GIVEUP)
706 stat->s_giveup++;
707}
708
709/*
710 * Because of a uv1 hardware bug only a limited number of concurrent
711 * requests can be made.
712 */
713static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
714{
715 spinlock_t *lock = &hmaster->uvhub_lock;
716 atomic_t *v;
717
718 v = &hmaster->active_descriptor_count;
719 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
720 stat->s_throttles++;
721 do {
722 cpu_relax();
723 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
724 }
725}
726
727/*
728 * Handle the completion status of a message send.
729 */
730static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
731 struct bau_control *bcp, struct bau_control *hmaster,
732 struct ptc_stats *stat)
733{
734 if (completion_status == FLUSH_RETRY_PLUGGED)
735 destination_plugged(bau_desc, bcp, hmaster, stat);
736 else if (completion_status == FLUSH_RETRY_TIMEOUT)
737 destination_timeout(bau_desc, bcp, hmaster, stat);
738}
739
740/*
561 * Send a broadcast and wait for it to complete. 741 * Send a broadcast and wait for it to complete.
562 * 742 *
563 * The flush_mask contains the cpus the broadcast is to be sent to including 743 * The flush_mask contains the cpus the broadcast is to be sent to including
@@ -568,44 +748,23 @@ disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat)
568 * returned to the kernel. 748 * returned to the kernel.
569 */ 749 */
570int uv_flush_send_and_wait(struct bau_desc *bau_desc, 750int uv_flush_send_and_wait(struct bau_desc *bau_desc,
571 struct cpumask *flush_mask, struct bau_control *bcp) 751 struct cpumask *flush_mask, struct bau_control *bcp)
572{ 752{
573 int right_shift;
574 int completion_status = 0;
575 int seq_number = 0; 753 int seq_number = 0;
754 int completion_stat = 0;
576 long try = 0; 755 long try = 0;
577 int cpu = bcp->uvhub_cpu;
578 int this_cpu = bcp->cpu;
579 unsigned long mmr_offset;
580 unsigned long index; 756 unsigned long index;
581 cycles_t time1; 757 cycles_t time1;
582 cycles_t time2; 758 cycles_t time2;
583 cycles_t elapsed;
584 struct ptc_stats *stat = bcp->statp; 759 struct ptc_stats *stat = bcp->statp;
585 struct bau_control *smaster = bcp->socket_master;
586 struct bau_control *hmaster = bcp->uvhub_master; 760 struct bau_control *hmaster = bcp->uvhub_master;
587 761
588 if (!atomic_inc_unless_ge(&hmaster->uvhub_lock, 762 if (is_uv1_hub())
589 &hmaster->active_descriptor_count, 763 uv1_throttle(hmaster, stat);
590 hmaster->max_bau_concurrent)) { 764
591 stat->s_throttles++;
592 do {
593 cpu_relax();
594 } while (!atomic_inc_unless_ge(&hmaster->uvhub_lock,
595 &hmaster->active_descriptor_count,
596 hmaster->max_bau_concurrent));
597 }
598 while (hmaster->uvhub_quiesce) 765 while (hmaster->uvhub_quiesce)
599 cpu_relax(); 766 cpu_relax();
600 767
601 if (cpu < UV_CPUS_PER_ACT_STATUS) {
602 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
603 right_shift = cpu * UV_ACT_STATUS_SIZE;
604 } else {
605 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
606 right_shift =
607 ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
608 }
609 time1 = get_cycles(); 768 time1 = get_cycles();
610 do { 769 do {
611 if (try == 0) { 770 if (try == 0) {
@@ -615,64 +774,134 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc,
615 bau_desc->header.msg_type = MSG_RETRY; 774 bau_desc->header.msg_type = MSG_RETRY;
616 stat->s_retry_messages++; 775 stat->s_retry_messages++;
617 } 776 }
777
618 bau_desc->header.sequence = seq_number; 778 bau_desc->header.sequence = seq_number;
619 index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) | 779 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
620 bcp->uvhub_cpu;
621 bcp->send_message = get_cycles(); 780 bcp->send_message = get_cycles();
622 uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 781
782 write_mmr_activation(index);
783
623 try++; 784 try++;
624 completion_status = uv_wait_completion(bau_desc, mmr_offset, 785 completion_stat = wait_completion(bau_desc, bcp, try);
625 right_shift, this_cpu, bcp, smaster, try); 786
787 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
626 788
627 if (completion_status == FLUSH_RETRY_PLUGGED) {
628 destination_plugged(bau_desc, bcp, hmaster, stat);
629 } else if (completion_status == FLUSH_RETRY_TIMEOUT) {
630 destination_timeout(bau_desc, bcp, hmaster, stat);
631 }
632 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { 789 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
633 bcp->ipi_attempts = 0; 790 bcp->ipi_attempts = 0;
634 completion_status = FLUSH_GIVEUP; 791 completion_stat = FLUSH_GIVEUP;
635 break; 792 break;
636 } 793 }
637 cpu_relax(); 794 cpu_relax();
638 } while ((completion_status == FLUSH_RETRY_PLUGGED) || 795 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
639 (completion_status == FLUSH_RETRY_TIMEOUT)); 796 (completion_stat == FLUSH_RETRY_TIMEOUT));
797
640 time2 = get_cycles(); 798 time2 = get_cycles();
641 bcp->plugged_tries = 0; 799
642 bcp->timeout_tries = 0; 800 count_max_concurr(completion_stat, bcp, hmaster);
643 if ((completion_status == FLUSH_COMPLETE) && 801
644 (bcp->conseccompletes > bcp->complete_threshold) &&
645 (hmaster->max_bau_concurrent <
646 hmaster->max_bau_concurrent_constant))
647 hmaster->max_bau_concurrent++;
648 while (hmaster->uvhub_quiesce) 802 while (hmaster->uvhub_quiesce)
649 cpu_relax(); 803 cpu_relax();
804
650 atomic_dec(&hmaster->active_descriptor_count); 805 atomic_dec(&hmaster->active_descriptor_count);
651 if (time2 > time1) { 806
652 elapsed = time2 - time1; 807 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
653 stat->s_time += elapsed; 808
654 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { 809 if (completion_stat == FLUSH_GIVEUP)
655 bcp->period_requests++; 810 return 1;
656 bcp->period_time += elapsed; 811 return 0;
657 if ((elapsed > congested_cycles) && 812}
658 (bcp->period_requests > bcp->congested_reps)) { 813
659 disable_for_congestion(bcp, stat); 814/*
815 * The BAU is disabled. When the disabled time period has expired, the cpu
816 * that disabled it must re-enable it.
817 * Return 0 if it is re-enabled for all cpus.
818 */
819static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
820{
821 int tcpu;
822 struct bau_control *tbcp;
823
824 if (bcp->set_bau_off) {
825 if (get_cycles() >= bcp->set_bau_on_time) {
826 stat->s_bau_reenabled++;
827 baudisabled = 0;
828 for_each_present_cpu(tcpu) {
829 tbcp = &per_cpu(bau_control, tcpu);
830 tbcp->baudisabled = 0;
831 tbcp->period_requests = 0;
832 tbcp->period_time = 0;
660 } 833 }
834 return 0;
661 } 835 }
836 }
837 return -1;
838}
839
840static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
841 int remotes, struct bau_desc *bau_desc)
842{
843 stat->s_requestor++;
844 stat->s_ntargcpu += remotes + locals;
845 stat->s_ntargremotes += remotes;
846 stat->s_ntarglocals += locals;
847
848 /* uvhub statistics */
849 hubs = bau_uvhub_weight(&bau_desc->distribution);
850 if (locals) {
851 stat->s_ntarglocaluvhub++;
852 stat->s_ntargremoteuvhub += (hubs - 1);
662 } else 853 } else
663 stat->s_requestor--; 854 stat->s_ntargremoteuvhub += hubs;
664 if (completion_status == FLUSH_COMPLETE && try > 1) 855
665 stat->s_retriesok++; 856 stat->s_ntarguvhub += hubs;
666 else if (completion_status == FLUSH_GIVEUP) { 857
667 stat->s_giveup++; 858 if (hubs >= 16)
668 return 1; 859 stat->s_ntarguvhub16++;
860 else if (hubs >= 8)
861 stat->s_ntarguvhub8++;
862 else if (hubs >= 4)
863 stat->s_ntarguvhub4++;
864 else if (hubs >= 2)
865 stat->s_ntarguvhub2++;
866 else
867 stat->s_ntarguvhub1++;
868}
869
870/*
871 * Translate a cpu mask to the uvhub distribution mask in the BAU
872 * activation descriptor.
873 */
874static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
875 struct bau_desc *bau_desc, int *localsp, int *remotesp)
876{
877 int cpu;
878 int pnode;
879 int cnt = 0;
880 struct hub_and_pnode *hpp;
881
882 for_each_cpu(cpu, flush_mask) {
883 /*
884 * The distribution vector is a bit map of pnodes, relative
885 * to the partition base pnode (and the partition base nasid
886 * in the header).
887 * Translate cpu to pnode and hub using a local memory array.
888 */
889 hpp = &bcp->socket_master->thp[cpu];
890 pnode = hpp->pnode - bcp->partition_base_pnode;
891 bau_uvhub_set(pnode, &bau_desc->distribution);
892 cnt++;
893 if (hpp->uvhub == bcp->uvhub)
894 (*localsp)++;
895 else
896 (*remotesp)++;
669 } 897 }
898 if (!cnt)
899 return 1;
670 return 0; 900 return 0;
671} 901}
672 902
673/** 903/*
674 * uv_flush_tlb_others - globally purge translation cache of a virtual 904 * globally purge translation cache of a virtual address or all TLB's
675 * address or all TLB's
676 * @cpumask: mask of all cpu's in which the address is to be removed 905 * @cpumask: mask of all cpu's in which the address is to be removed
677 * @mm: mm_struct containing virtual address range 906 * @mm: mm_struct containing virtual address range
678 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) 907 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
@@ -696,20 +925,16 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc,
696 * done. The returned pointer is valid till preemption is re-enabled. 925 * done. The returned pointer is valid till preemption is re-enabled.
697 */ 926 */
698const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, 927const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
699 struct mm_struct *mm, 928 struct mm_struct *mm, unsigned long va,
700 unsigned long va, unsigned int cpu) 929 unsigned int cpu)
701{ 930{
702 int locals = 0; 931 int locals = 0;
703 int remotes = 0; 932 int remotes = 0;
704 int hubs = 0; 933 int hubs = 0;
705 int tcpu;
706 int tpnode;
707 struct bau_desc *bau_desc; 934 struct bau_desc *bau_desc;
708 struct cpumask *flush_mask; 935 struct cpumask *flush_mask;
709 struct ptc_stats *stat; 936 struct ptc_stats *stat;
710 struct bau_control *bcp; 937 struct bau_control *bcp;
711 struct bau_control *tbcp;
712 struct hub_and_pnode *hpp;
713 938
714 /* kernel was booted 'nobau' */ 939 /* kernel was booted 'nobau' */
715 if (nobau) 940 if (nobau)
@@ -720,20 +945,8 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
720 945
721 /* bau was disabled due to slow response */ 946 /* bau was disabled due to slow response */
722 if (bcp->baudisabled) { 947 if (bcp->baudisabled) {
723 /* the cpu that disabled it must re-enable it */ 948 if (check_enable(bcp, stat))
724 if (bcp->set_bau_off) { 949 return cpumask;
725 if (get_cycles() >= bcp->set_bau_on_time) {
726 stat->s_bau_reenabled++;
727 baudisabled = 0;
728 for_each_present_cpu(tcpu) {
729 tbcp = &per_cpu(bau_control, tcpu);
730 tbcp->baudisabled = 0;
731 tbcp->period_requests = 0;
732 tbcp->period_time = 0;
733 }
734 }
735 }
736 return cpumask;
737 } 950 }
738 951
739 /* 952 /*
@@ -744,59 +957,20 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
744 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); 957 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
745 /* don't actually do a shootdown of the local cpu */ 958 /* don't actually do a shootdown of the local cpu */
746 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); 959 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
960
747 if (cpu_isset(cpu, *cpumask)) 961 if (cpu_isset(cpu, *cpumask))
748 stat->s_ntargself++; 962 stat->s_ntargself++;
749 963
750 bau_desc = bcp->descriptor_base; 964 bau_desc = bcp->descriptor_base;
751 bau_desc += UV_ITEMS_PER_DESCRIPTOR * bcp->uvhub_cpu; 965 bau_desc += ITEMS_PER_DESC * bcp->uvhub_cpu;
752 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); 966 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
753 967 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
754 for_each_cpu(tcpu, flush_mask) {
755 /*
756 * The distribution vector is a bit map of pnodes, relative
757 * to the partition base pnode (and the partition base nasid
758 * in the header).
759 * Translate cpu to pnode and hub using an array stored
760 * in local memory.
761 */
762 hpp = &bcp->socket_master->target_hub_and_pnode[tcpu];
763 tpnode = hpp->pnode - bcp->partition_base_pnode;
764 bau_uvhub_set(tpnode, &bau_desc->distribution);
765 if (hpp->uvhub == bcp->uvhub)
766 locals++;
767 else
768 remotes++;
769 }
770 if ((locals + remotes) == 0)
771 return NULL; 968 return NULL;
772 stat->s_requestor++;
773 stat->s_ntargcpu += remotes + locals;
774 stat->s_ntargremotes += remotes;
775 stat->s_ntarglocals += locals;
776 remotes = bau_uvhub_weight(&bau_desc->distribution);
777 969
778 /* uvhub statistics */ 970 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
779 hubs = bau_uvhub_weight(&bau_desc->distribution);
780 if (locals) {
781 stat->s_ntarglocaluvhub++;
782 stat->s_ntargremoteuvhub += (hubs - 1);
783 } else
784 stat->s_ntargremoteuvhub += hubs;
785 stat->s_ntarguvhub += hubs;
786 if (hubs >= 16)
787 stat->s_ntarguvhub16++;
788 else if (hubs >= 8)
789 stat->s_ntarguvhub8++;
790 else if (hubs >= 4)
791 stat->s_ntarguvhub4++;
792 else if (hubs >= 2)
793 stat->s_ntarguvhub2++;
794 else
795 stat->s_ntarguvhub1++;
796 971
797 bau_desc->payload.address = va; 972 bau_desc->payload.address = va;
798 bau_desc->payload.sending_cpu = cpu; 973 bau_desc->payload.sending_cpu = cpu;
799
800 /* 974 /*
801 * uv_flush_send_and_wait returns 0 if all cpu's were messaged, 975 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
802 * or 1 if it gave up and the original cpumask should be returned. 976 * or 1 if it gave up and the original cpumask should be returned.
@@ -825,26 +999,31 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
825{ 999{
826 int count = 0; 1000 int count = 0;
827 cycles_t time_start; 1001 cycles_t time_start;
828 struct bau_payload_queue_entry *msg; 1002 struct bau_pq_entry *msg;
829 struct bau_control *bcp; 1003 struct bau_control *bcp;
830 struct ptc_stats *stat; 1004 struct ptc_stats *stat;
831 struct msg_desc msgdesc; 1005 struct msg_desc msgdesc;
832 1006
833 time_start = get_cycles(); 1007 time_start = get_cycles();
1008
834 bcp = &per_cpu(bau_control, smp_processor_id()); 1009 bcp = &per_cpu(bau_control, smp_processor_id());
835 stat = bcp->statp; 1010 stat = bcp->statp;
836 msgdesc.va_queue_first = bcp->va_queue_first; 1011
837 msgdesc.va_queue_last = bcp->va_queue_last; 1012 msgdesc.queue_first = bcp->queue_first;
1013 msgdesc.queue_last = bcp->queue_last;
1014
838 msg = bcp->bau_msg_head; 1015 msg = bcp->bau_msg_head;
839 while (msg->sw_ack_vector) { 1016 while (msg->swack_vec) {
840 count++; 1017 count++;
841 msgdesc.msg_slot = msg - msgdesc.va_queue_first; 1018
842 msgdesc.sw_ack_slot = ffs(msg->sw_ack_vector) - 1; 1019 msgdesc.msg_slot = msg - msgdesc.queue_first;
1020 msgdesc.swack_slot = ffs(msg->swack_vec) - 1;
843 msgdesc.msg = msg; 1021 msgdesc.msg = msg;
844 uv_bau_process_message(&msgdesc, bcp); 1022 bau_process_message(&msgdesc, bcp);
1023
845 msg++; 1024 msg++;
846 if (msg > msgdesc.va_queue_last) 1025 if (msg > msgdesc.queue_last)
847 msg = msgdesc.va_queue_first; 1026 msg = msgdesc.queue_first;
848 bcp->bau_msg_head = msg; 1027 bcp->bau_msg_head = msg;
849 } 1028 }
850 stat->d_time += (get_cycles() - time_start); 1029 stat->d_time += (get_cycles() - time_start);
@@ -852,18 +1031,17 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
852 stat->d_nomsg++; 1031 stat->d_nomsg++;
853 else if (count > 1) 1032 else if (count > 1)
854 stat->d_multmsg++; 1033 stat->d_multmsg++;
1034
855 ack_APIC_irq(); 1035 ack_APIC_irq();
856} 1036}
857 1037
858/* 1038/*
859 * uv_enable_timeouts 1039 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
860 *
861 * Each target uvhub (i.e. a uvhub that has no cpu's) needs to have
862 * shootdown message timeouts enabled. The timeout does not cause 1040 * shootdown message timeouts enabled. The timeout does not cause
863 * an interrupt, but causes an error message to be returned to 1041 * an interrupt, but causes an error message to be returned to
864 * the sender. 1042 * the sender.
865 */ 1043 */
866static void __init uv_enable_timeouts(void) 1044static void __init enable_timeouts(void)
867{ 1045{
868 int uvhub; 1046 int uvhub;
869 int nuvhubs; 1047 int nuvhubs;
@@ -877,47 +1055,44 @@ static void __init uv_enable_timeouts(void)
877 continue; 1055 continue;
878 1056
879 pnode = uv_blade_to_pnode(uvhub); 1057 pnode = uv_blade_to_pnode(uvhub);
880 mmr_image = 1058 mmr_image = read_mmr_misc_control(pnode);
881 uv_read_global_mmr64(pnode, UVH_LB_BAU_MISC_CONTROL);
882 /* 1059 /*
883 * Set the timeout period and then lock it in, in three 1060 * Set the timeout period and then lock it in, in three
884 * steps; captures and locks in the period. 1061 * steps; captures and locks in the period.
885 * 1062 *
886 * To program the period, the SOFT_ACK_MODE must be off. 1063 * To program the period, the SOFT_ACK_MODE must be off.
887 */ 1064 */
888 mmr_image &= ~((unsigned long)1 << 1065 mmr_image &= ~(1L << SOFTACK_MSHIFT);
889 UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 1066 write_mmr_misc_control(pnode, mmr_image);
890 uv_write_global_mmr64
891 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
892 /* 1067 /*
893 * Set the 4-bit period. 1068 * Set the 4-bit period.
894 */ 1069 */
895 mmr_image &= ~((unsigned long)0xf << 1070 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
896 UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT); 1071 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
897 mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD << 1072 write_mmr_misc_control(pnode, mmr_image);
898 UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT);
899 uv_write_global_mmr64
900 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
901 /* 1073 /*
1074 * UV1:
902 * Subsequent reversals of the timebase bit (3) cause an 1075 * Subsequent reversals of the timebase bit (3) cause an
903 * immediate timeout of one or all INTD resources as 1076 * immediate timeout of one or all INTD resources as
904 * indicated in bits 2:0 (7 causes all of them to timeout). 1077 * indicated in bits 2:0 (7 causes all of them to timeout).
905 */ 1078 */
906 mmr_image |= ((unsigned long)1 << 1079 mmr_image |= (1L << SOFTACK_MSHIFT);
907 UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 1080 if (is_uv2_hub()) {
908 uv_write_global_mmr64 1081 mmr_image |= (1L << UV2_LEG_SHFT);
909 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 1082 mmr_image |= (1L << UV2_EXT_SHFT);
1083 }
1084 write_mmr_misc_control(pnode, mmr_image);
910 } 1085 }
911} 1086}
912 1087
913static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset) 1088static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
914{ 1089{
915 if (*offset < num_possible_cpus()) 1090 if (*offset < num_possible_cpus())
916 return offset; 1091 return offset;
917 return NULL; 1092 return NULL;
918} 1093}
919 1094
920static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) 1095static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
921{ 1096{
922 (*offset)++; 1097 (*offset)++;
923 if (*offset < num_possible_cpus()) 1098 if (*offset < num_possible_cpus())
@@ -925,12 +1100,11 @@ static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
925 return NULL; 1100 return NULL;
926} 1101}
927 1102
928static void uv_ptc_seq_stop(struct seq_file *file, void *data) 1103static void ptc_seq_stop(struct seq_file *file, void *data)
929{ 1104{
930} 1105}
931 1106
932static inline unsigned long long 1107static inline unsigned long long usec_2_cycles(unsigned long microsec)
933microsec_2_cycles(unsigned long microsec)
934{ 1108{
935 unsigned long ns; 1109 unsigned long ns;
936 unsigned long long cyc; 1110 unsigned long long cyc;
@@ -941,29 +1115,27 @@ microsec_2_cycles(unsigned long microsec)
941} 1115}
942 1116
943/* 1117/*
944 * Display the statistics thru /proc. 1118 * Display the statistics thru /proc/sgi_uv/ptc_statistics
945 * 'data' points to the cpu number 1119 * 'data' points to the cpu number
1120 * Note: see the descriptions in stat_description[].
946 */ 1121 */
947static int uv_ptc_seq_show(struct seq_file *file, void *data) 1122static int ptc_seq_show(struct seq_file *file, void *data)
948{ 1123{
949 struct ptc_stats *stat; 1124 struct ptc_stats *stat;
950 int cpu; 1125 int cpu;
951 1126
952 cpu = *(loff_t *)data; 1127 cpu = *(loff_t *)data;
953
954 if (!cpu) { 1128 if (!cpu) {
955 seq_printf(file, 1129 seq_printf(file,
956 "# cpu sent stime self locals remotes ncpus localhub "); 1130 "# cpu sent stime self locals remotes ncpus localhub ");
957 seq_printf(file, 1131 seq_printf(file,
958 "remotehub numuvhubs numuvhubs16 numuvhubs8 "); 1132 "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
959 seq_printf(file, 1133 seq_printf(file,
960 "numuvhubs4 numuvhubs2 numuvhubs1 dto "); 1134 "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok ");
961 seq_printf(file,
962 "retries rok resetp resett giveup sto bz throt ");
963 seq_printf(file, 1135 seq_printf(file,
964 "sw_ack recv rtime all "); 1136 "resetp resett giveup sto bz throt swack recv rtime ");
965 seq_printf(file, 1137 seq_printf(file,
966 "one mult none retry canc nocan reset rcan "); 1138 "all one mult none retry canc nocan reset rcan ");
967 seq_printf(file, 1139 seq_printf(file,
968 "disable enable\n"); 1140 "disable enable\n");
969 } 1141 }
@@ -990,8 +1162,7 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
990 /* destination side statistics */ 1162 /* destination side statistics */
991 seq_printf(file, 1163 seq_printf(file,
992 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", 1164 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
993 uv_read_global_mmr64(uv_cpu_to_pnode(cpu), 1165 read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
994 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
995 stat->d_requestee, cycles_2_us(stat->d_time), 1166 stat->d_requestee, cycles_2_us(stat->d_time),
996 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, 1167 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
997 stat->d_nomsg, stat->d_retries, stat->d_canceled, 1168 stat->d_nomsg, stat->d_retries, stat->d_canceled,
@@ -1000,7 +1171,6 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
1000 seq_printf(file, "%ld %ld\n", 1171 seq_printf(file, "%ld %ld\n",
1001 stat->s_bau_disabled, stat->s_bau_reenabled); 1172 stat->s_bau_disabled, stat->s_bau_reenabled);
1002 } 1173 }
1003
1004 return 0; 1174 return 0;
1005} 1175}
1006 1176
@@ -1008,18 +1178,18 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
1008 * Display the tunables thru debugfs 1178 * Display the tunables thru debugfs
1009 */ 1179 */
1010static ssize_t tunables_read(struct file *file, char __user *userbuf, 1180static ssize_t tunables_read(struct file *file, char __user *userbuf,
1011 size_t count, loff_t *ppos) 1181 size_t count, loff_t *ppos)
1012{ 1182{
1013 char *buf; 1183 char *buf;
1014 int ret; 1184 int ret;
1015 1185
1016 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", 1186 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n",
1017 "max_bau_concurrent plugged_delay plugsb4reset", 1187 "max_concur plugged_delay plugsb4reset",
1018 "timeoutsb4reset ipi_reset_limit complete_threshold", 1188 "timeoutsb4reset ipi_reset_limit complete_threshold",
1019 "congested_response_us congested_reps congested_period", 1189 "congested_response_us congested_reps congested_period",
1020 max_bau_concurrent, plugged_delay, plugsb4reset, 1190 max_concurr, plugged_delay, plugsb4reset,
1021 timeoutsb4reset, ipi_reset_limit, complete_threshold, 1191 timeoutsb4reset, ipi_reset_limit, complete_threshold,
1022 congested_response_us, congested_reps, congested_period); 1192 congested_respns_us, congested_reps, congested_period);
1023 1193
1024 if (!buf) 1194 if (!buf)
1025 return -ENOMEM; 1195 return -ENOMEM;
@@ -1030,13 +1200,16 @@ static ssize_t tunables_read(struct file *file, char __user *userbuf,
1030} 1200}
1031 1201
1032/* 1202/*
1033 * -1: resetf the statistics 1203 * handle a write to /proc/sgi_uv/ptc_statistics
1204 * -1: reset the statistics
1034 * 0: display meaning of the statistics 1205 * 0: display meaning of the statistics
1035 */ 1206 */
1036static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user, 1207static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1037 size_t count, loff_t *data) 1208 size_t count, loff_t *data)
1038{ 1209{
1039 int cpu; 1210 int cpu;
1211 int i;
1212 int elements;
1040 long input_arg; 1213 long input_arg;
1041 char optstr[64]; 1214 char optstr[64];
1042 struct ptc_stats *stat; 1215 struct ptc_stats *stat;
@@ -1046,79 +1219,18 @@ static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
1046 if (copy_from_user(optstr, user, count)) 1219 if (copy_from_user(optstr, user, count))
1047 return -EFAULT; 1220 return -EFAULT;
1048 optstr[count - 1] = '\0'; 1221 optstr[count - 1] = '\0';
1222
1049 if (strict_strtol(optstr, 10, &input_arg) < 0) { 1223 if (strict_strtol(optstr, 10, &input_arg) < 0) {
1050 printk(KERN_DEBUG "%s is invalid\n", optstr); 1224 printk(KERN_DEBUG "%s is invalid\n", optstr);
1051 return -EINVAL; 1225 return -EINVAL;
1052 } 1226 }
1053 1227
1054 if (input_arg == 0) { 1228 if (input_arg == 0) {
1229 elements = sizeof(stat_description)/sizeof(*stat_description);
1055 printk(KERN_DEBUG "# cpu: cpu number\n"); 1230 printk(KERN_DEBUG "# cpu: cpu number\n");
1056 printk(KERN_DEBUG "Sender statistics:\n"); 1231 printk(KERN_DEBUG "Sender statistics:\n");
1057 printk(KERN_DEBUG 1232 for (i = 0; i < elements; i++)
1058 "sent: number of shootdown messages sent\n"); 1233 printk(KERN_DEBUG "%s\n", stat_description[i]);
1059 printk(KERN_DEBUG
1060 "stime: time spent sending messages\n");
1061 printk(KERN_DEBUG
1062 "numuvhubs: number of hubs targeted with shootdown\n");
1063 printk(KERN_DEBUG
1064 "numuvhubs16: number times 16 or more hubs targeted\n");
1065 printk(KERN_DEBUG
1066 "numuvhubs8: number times 8 or more hubs targeted\n");
1067 printk(KERN_DEBUG
1068 "numuvhubs4: number times 4 or more hubs targeted\n");
1069 printk(KERN_DEBUG
1070 "numuvhubs2: number times 2 or more hubs targeted\n");
1071 printk(KERN_DEBUG
1072 "numuvhubs1: number times 1 hub targeted\n");
1073 printk(KERN_DEBUG
1074 "numcpus: number of cpus targeted with shootdown\n");
1075 printk(KERN_DEBUG
1076 "dto: number of destination timeouts\n");
1077 printk(KERN_DEBUG
1078 "retries: destination timeout retries sent\n");
1079 printk(KERN_DEBUG
1080 "rok: : destination timeouts successfully retried\n");
1081 printk(KERN_DEBUG
1082 "resetp: ipi-style resource resets for plugs\n");
1083 printk(KERN_DEBUG
1084 "resett: ipi-style resource resets for timeouts\n");
1085 printk(KERN_DEBUG
1086 "giveup: fall-backs to ipi-style shootdowns\n");
1087 printk(KERN_DEBUG
1088 "sto: number of source timeouts\n");
1089 printk(KERN_DEBUG
1090 "bz: number of stay-busy's\n");
1091 printk(KERN_DEBUG
1092 "throt: number times spun in throttle\n");
1093 printk(KERN_DEBUG "Destination side statistics:\n");
1094 printk(KERN_DEBUG
1095 "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
1096 printk(KERN_DEBUG
1097 "recv: shootdown messages received\n");
1098 printk(KERN_DEBUG
1099 "rtime: time spent processing messages\n");
1100 printk(KERN_DEBUG
1101 "all: shootdown all-tlb messages\n");
1102 printk(KERN_DEBUG
1103 "one: shootdown one-tlb messages\n");
1104 printk(KERN_DEBUG
1105 "mult: interrupts that found multiple messages\n");
1106 printk(KERN_DEBUG
1107 "none: interrupts that found no messages\n");
1108 printk(KERN_DEBUG
1109 "retry: number of retry messages processed\n");
1110 printk(KERN_DEBUG
1111 "canc: number messages canceled by retries\n");
1112 printk(KERN_DEBUG
1113 "nocan: number retries that found nothing to cancel\n");
1114 printk(KERN_DEBUG
1115 "reset: number of ipi-style reset requests processed\n");
1116 printk(KERN_DEBUG
1117 "rcan: number messages canceled by reset requests\n");
1118 printk(KERN_DEBUG
1119 "disable: number times use of the BAU was disabled\n");
1120 printk(KERN_DEBUG
1121 "enable: number times use of the BAU was re-enabled\n");
1122 } else if (input_arg == -1) { 1234 } else if (input_arg == -1) {
1123 for_each_present_cpu(cpu) { 1235 for_each_present_cpu(cpu) {
1124 stat = &per_cpu(ptcstats, cpu); 1236 stat = &per_cpu(ptcstats, cpu);
@@ -1145,27 +1257,18 @@ static int local_atoi(const char *name)
1145} 1257}
1146 1258
1147/* 1259/*
1148 * set the tunables 1260 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1149 * 0 values reset them to defaults 1261 * Zero values reset them to defaults.
1150 */ 1262 */
1151static ssize_t tunables_write(struct file *file, const char __user *user, 1263static int parse_tunables_write(struct bau_control *bcp, char *instr,
1152 size_t count, loff_t *data) 1264 int count)
1153{ 1265{
1154 int cpu;
1155 int cnt = 0;
1156 int val;
1157 char *p; 1266 char *p;
1158 char *q; 1267 char *q;
1159 char instr[64]; 1268 int cnt = 0;
1160 struct bau_control *bcp; 1269 int val;
1161 1270 int e = sizeof(tunables) / sizeof(*tunables);
1162 if (count == 0 || count > sizeof(instr)-1)
1163 return -EINVAL;
1164 if (copy_from_user(instr, user, count))
1165 return -EFAULT;
1166 1271
1167 instr[count] = '\0';
1168 /* count the fields */
1169 p = instr + strspn(instr, WHITESPACE); 1272 p = instr + strspn(instr, WHITESPACE);
1170 q = p; 1273 q = p;
1171 for (; *p; p = q + strspn(q, WHITESPACE)) { 1274 for (; *p; p = q + strspn(q, WHITESPACE)) {
@@ -1174,8 +1277,8 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
1174 if (q == p) 1277 if (q == p)
1175 break; 1278 break;
1176 } 1279 }
1177 if (cnt != 9) { 1280 if (cnt != e) {
1178 printk(KERN_INFO "bau tunable error: should be 9 numbers\n"); 1281 printk(KERN_INFO "bau tunable error: should be %d values\n", e);
1179 return -EINVAL; 1282 return -EINVAL;
1180 } 1283 }
1181 1284
@@ -1187,97 +1290,80 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
1187 switch (cnt) { 1290 switch (cnt) {
1188 case 0: 1291 case 0:
1189 if (val == 0) { 1292 if (val == 0) {
1190 max_bau_concurrent = MAX_BAU_CONCURRENT; 1293 max_concurr = MAX_BAU_CONCURRENT;
1191 max_bau_concurrent_constant = 1294 max_concurr_const = MAX_BAU_CONCURRENT;
1192 MAX_BAU_CONCURRENT;
1193 continue; 1295 continue;
1194 } 1296 }
1195 bcp = &per_cpu(bau_control, smp_processor_id());
1196 if (val < 1 || val > bcp->cpus_in_uvhub) { 1297 if (val < 1 || val > bcp->cpus_in_uvhub) {
1197 printk(KERN_DEBUG 1298 printk(KERN_DEBUG
1198 "Error: BAU max concurrent %d is invalid\n", 1299 "Error: BAU max concurrent %d is invalid\n",
1199 val); 1300 val);
1200 return -EINVAL; 1301 return -EINVAL;
1201 } 1302 }
1202 max_bau_concurrent = val; 1303 max_concurr = val;
1203 max_bau_concurrent_constant = val; 1304 max_concurr_const = val;
1204 continue;
1205 case 1:
1206 if (val == 0)
1207 plugged_delay = PLUGGED_DELAY;
1208 else
1209 plugged_delay = val;
1210 continue;
1211 case 2:
1212 if (val == 0)
1213 plugsb4reset = PLUGSB4RESET;
1214 else
1215 plugsb4reset = val;
1216 continue;
1217 case 3:
1218 if (val == 0)
1219 timeoutsb4reset = TIMEOUTSB4RESET;
1220 else
1221 timeoutsb4reset = val;
1222 continue;
1223 case 4:
1224 if (val == 0)
1225 ipi_reset_limit = IPI_RESET_LIMIT;
1226 else
1227 ipi_reset_limit = val;
1228 continue;
1229 case 5:
1230 if (val == 0)
1231 complete_threshold = COMPLETE_THRESHOLD;
1232 else
1233 complete_threshold = val;
1234 continue;
1235 case 6:
1236 if (val == 0)
1237 congested_response_us = CONGESTED_RESPONSE_US;
1238 else
1239 congested_response_us = val;
1240 continue;
1241 case 7:
1242 if (val == 0)
1243 congested_reps = CONGESTED_REPS;
1244 else
1245 congested_reps = val;
1246 continue; 1305 continue;
1247 case 8: 1306 default:
1248 if (val == 0) 1307 if (val == 0)
1249 congested_period = CONGESTED_PERIOD; 1308 *tunables[cnt].tunp = tunables[cnt].deflt;
1250 else 1309 else
1251 congested_period = val; 1310 *tunables[cnt].tunp = val;
1252 continue; 1311 continue;
1253 } 1312 }
1254 if (q == p) 1313 if (q == p)
1255 break; 1314 break;
1256 } 1315 }
1316 return 0;
1317}
1318
1319/*
1320 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1321 */
1322static ssize_t tunables_write(struct file *file, const char __user *user,
1323 size_t count, loff_t *data)
1324{
1325 int cpu;
1326 int ret;
1327 char instr[100];
1328 struct bau_control *bcp;
1329
1330 if (count == 0 || count > sizeof(instr)-1)
1331 return -EINVAL;
1332 if (copy_from_user(instr, user, count))
1333 return -EFAULT;
1334
1335 instr[count] = '\0';
1336
1337 bcp = &per_cpu(bau_control, smp_processor_id());
1338
1339 ret = parse_tunables_write(bcp, instr, count);
1340 if (ret)
1341 return ret;
1342
1257 for_each_present_cpu(cpu) { 1343 for_each_present_cpu(cpu) {
1258 bcp = &per_cpu(bau_control, cpu); 1344 bcp = &per_cpu(bau_control, cpu);
1259 bcp->max_bau_concurrent = max_bau_concurrent; 1345 bcp->max_concurr = max_concurr;
1260 bcp->max_bau_concurrent_constant = max_bau_concurrent; 1346 bcp->max_concurr_const = max_concurr;
1261 bcp->plugged_delay = plugged_delay; 1347 bcp->plugged_delay = plugged_delay;
1262 bcp->plugsb4reset = plugsb4reset; 1348 bcp->plugsb4reset = plugsb4reset;
1263 bcp->timeoutsb4reset = timeoutsb4reset; 1349 bcp->timeoutsb4reset = timeoutsb4reset;
1264 bcp->ipi_reset_limit = ipi_reset_limit; 1350 bcp->ipi_reset_limit = ipi_reset_limit;
1265 bcp->complete_threshold = complete_threshold; 1351 bcp->complete_threshold = complete_threshold;
1266 bcp->congested_response_us = congested_response_us; 1352 bcp->cong_response_us = congested_respns_us;
1267 bcp->congested_reps = congested_reps; 1353 bcp->cong_reps = congested_reps;
1268 bcp->congested_period = congested_period; 1354 bcp->cong_period = congested_period;
1269 } 1355 }
1270 return count; 1356 return count;
1271} 1357}
1272 1358
1273static const struct seq_operations uv_ptc_seq_ops = { 1359static const struct seq_operations uv_ptc_seq_ops = {
1274 .start = uv_ptc_seq_start, 1360 .start = ptc_seq_start,
1275 .next = uv_ptc_seq_next, 1361 .next = ptc_seq_next,
1276 .stop = uv_ptc_seq_stop, 1362 .stop = ptc_seq_stop,
1277 .show = uv_ptc_seq_show 1363 .show = ptc_seq_show
1278}; 1364};
1279 1365
1280static int uv_ptc_proc_open(struct inode *inode, struct file *file) 1366static int ptc_proc_open(struct inode *inode, struct file *file)
1281{ 1367{
1282 return seq_open(file, &uv_ptc_seq_ops); 1368 return seq_open(file, &uv_ptc_seq_ops);
1283} 1369}
@@ -1288,9 +1374,9 @@ static int tunables_open(struct inode *inode, struct file *file)
1288} 1374}
1289 1375
1290static const struct file_operations proc_uv_ptc_operations = { 1376static const struct file_operations proc_uv_ptc_operations = {
1291 .open = uv_ptc_proc_open, 1377 .open = ptc_proc_open,
1292 .read = seq_read, 1378 .read = seq_read,
1293 .write = uv_ptc_proc_write, 1379 .write = ptc_proc_write,
1294 .llseek = seq_lseek, 1380 .llseek = seq_lseek,
1295 .release = seq_release, 1381 .release = seq_release,
1296}; 1382};
@@ -1324,7 +1410,7 @@ static int __init uv_ptc_init(void)
1324 return -EINVAL; 1410 return -EINVAL;
1325 } 1411 }
1326 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, 1412 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
1327 tunables_dir, NULL, &tunables_fops); 1413 tunables_dir, NULL, &tunables_fops);
1328 if (!tunables_file) { 1414 if (!tunables_file) {
1329 printk(KERN_ERR "unable to create debugfs file %s\n", 1415 printk(KERN_ERR "unable to create debugfs file %s\n",
1330 UV_BAU_TUNABLES_FILE); 1416 UV_BAU_TUNABLES_FILE);
@@ -1336,24 +1422,24 @@ static int __init uv_ptc_init(void)
1336/* 1422/*
1337 * Initialize the sending side's sending buffers. 1423 * Initialize the sending side's sending buffers.
1338 */ 1424 */
1339static void 1425static void activation_descriptor_init(int node, int pnode, int base_pnode)
1340uv_activation_descriptor_init(int node, int pnode, int base_pnode)
1341{ 1426{
1342 int i; 1427 int i;
1343 int cpu; 1428 int cpu;
1344 unsigned long pa; 1429 unsigned long pa;
1345 unsigned long m; 1430 unsigned long m;
1346 unsigned long n; 1431 unsigned long n;
1432 size_t dsize;
1347 struct bau_desc *bau_desc; 1433 struct bau_desc *bau_desc;
1348 struct bau_desc *bd2; 1434 struct bau_desc *bd2;
1349 struct bau_control *bcp; 1435 struct bau_control *bcp;
1350 1436
1351 /* 1437 /*
1352 * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR) 1438 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1353 * per cpu; and one per cpu on the uvhub (UV_ADP_SIZE) 1439 * per cpu; and one per cpu on the uvhub (ADP_SZ)
1354 */ 1440 */
1355 bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE 1441 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1356 * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node); 1442 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
1357 BUG_ON(!bau_desc); 1443 BUG_ON(!bau_desc);
1358 1444
1359 pa = uv_gpa(bau_desc); /* need the real nasid*/ 1445 pa = uv_gpa(bau_desc); /* need the real nasid*/
@@ -1361,27 +1447,25 @@ uv_activation_descriptor_init(int node, int pnode, int base_pnode)
1361 m = pa & uv_mmask; 1447 m = pa & uv_mmask;
1362 1448
1363 /* the 14-bit pnode */ 1449 /* the 14-bit pnode */
1364 uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, 1450 write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
1365 (n << UV_DESC_BASE_PNODE_SHIFT | m));
1366 /* 1451 /*
1367 * Initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each 1452 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
1368 * cpu even though we only use the first one; one descriptor can 1453 * cpu even though we only use the first one; one descriptor can
1369 * describe a broadcast to 256 uv hubs. 1454 * describe a broadcast to 256 uv hubs.
1370 */ 1455 */
1371 for (i = 0, bd2 = bau_desc; i < (UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR); 1456 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
1372 i++, bd2++) {
1373 memset(bd2, 0, sizeof(struct bau_desc)); 1457 memset(bd2, 0, sizeof(struct bau_desc));
1374 bd2->header.sw_ack_flag = 1; 1458 bd2->header.swack_flag = 1;
1375 /* 1459 /*
1376 * The base_dest_nasid set in the message header is the nasid 1460 * The base_dest_nasid set in the message header is the nasid
1377 * of the first uvhub in the partition. The bit map will 1461 * of the first uvhub in the partition. The bit map will
1378 * indicate destination pnode numbers relative to that base. 1462 * indicate destination pnode numbers relative to that base.
1379 * They may not be consecutive if nasid striding is being used. 1463 * They may not be consecutive if nasid striding is being used.
1380 */ 1464 */
1381 bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode); 1465 bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode);
1382 bd2->header.dest_subnodeid = UV_LB_SUBNODEID; 1466 bd2->header.dest_subnodeid = UV_LB_SUBNODEID;
1383 bd2->header.command = UV_NET_ENDPOINT_INTD; 1467 bd2->header.command = UV_NET_ENDPOINT_INTD;
1384 bd2->header.int_both = 1; 1468 bd2->header.int_both = 1;
1385 /* 1469 /*
1386 * all others need to be set to zero: 1470 * all others need to be set to zero:
1387 * fairness chaining multilevel count replied_to 1471 * fairness chaining multilevel count replied_to
@@ -1401,57 +1485,55 @@ uv_activation_descriptor_init(int node, int pnode, int base_pnode)
1401 * - node is first node (kernel memory notion) on the uvhub 1485 * - node is first node (kernel memory notion) on the uvhub
1402 * - pnode is the uvhub's physical identifier 1486 * - pnode is the uvhub's physical identifier
1403 */ 1487 */
1404static void 1488static void pq_init(int node, int pnode)
1405uv_payload_queue_init(int node, int pnode)
1406{ 1489{
1407 int pn;
1408 int cpu; 1490 int cpu;
1491 size_t plsize;
1409 char *cp; 1492 char *cp;
1410 unsigned long pa; 1493 void *vp;
1411 struct bau_payload_queue_entry *pqp; 1494 unsigned long pn;
1412 struct bau_payload_queue_entry *pqp_malloc; 1495 unsigned long first;
1496 unsigned long pn_first;
1497 unsigned long last;
1498 struct bau_pq_entry *pqp;
1413 struct bau_control *bcp; 1499 struct bau_control *bcp;
1414 1500
1415 pqp = kmalloc_node((DEST_Q_SIZE + 1) 1501 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1416 * sizeof(struct bau_payload_queue_entry), 1502 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1417 GFP_KERNEL, node); 1503 pqp = (struct bau_pq_entry *)vp;
1418 BUG_ON(!pqp); 1504 BUG_ON(!pqp);
1419 pqp_malloc = pqp;
1420 1505
1421 cp = (char *)pqp + 31; 1506 cp = (char *)pqp + 31;
1422 pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5); 1507 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
1423 1508
1424 for_each_present_cpu(cpu) { 1509 for_each_present_cpu(cpu) {
1425 if (pnode != uv_cpu_to_pnode(cpu)) 1510 if (pnode != uv_cpu_to_pnode(cpu))
1426 continue; 1511 continue;
1427 /* for every cpu on this pnode: */ 1512 /* for every cpu on this pnode: */
1428 bcp = &per_cpu(bau_control, cpu); 1513 bcp = &per_cpu(bau_control, cpu);
1429 bcp->va_queue_first = pqp; 1514 bcp->queue_first = pqp;
1430 bcp->bau_msg_head = pqp; 1515 bcp->bau_msg_head = pqp;
1431 bcp->va_queue_last = pqp + (DEST_Q_SIZE - 1); 1516 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
1432 } 1517 }
1433 /* 1518 /*
1434 * need the pnode of where the memory was really allocated 1519 * need the pnode of where the memory was really allocated
1435 */ 1520 */
1436 pa = uv_gpa(pqp); 1521 pn = uv_gpa(pqp) >> uv_nshift;
1437 pn = pa >> uv_nshift; 1522 first = uv_physnodeaddr(pqp);
1438 uv_write_global_mmr64(pnode, 1523 pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
1439 UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, 1524 last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
1440 ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | 1525 write_mmr_payload_first(pnode, pn_first);
1441 uv_physnodeaddr(pqp)); 1526 write_mmr_payload_tail(pnode, first);
1442 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, 1527 write_mmr_payload_last(pnode, last);
1443 uv_physnodeaddr(pqp)); 1528
1444 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
1445 (unsigned long)
1446 uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)));
1447 /* in effect, all msg_type's are set to MSG_NOOP */ 1529 /* in effect, all msg_type's are set to MSG_NOOP */
1448 memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE); 1530 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
1449} 1531}
1450 1532
1451/* 1533/*
1452 * Initialization of each UV hub's structures 1534 * Initialization of each UV hub's structures
1453 */ 1535 */
1454static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode) 1536static void __init init_uvhub(int uvhub, int vector, int base_pnode)
1455{ 1537{
1456 int node; 1538 int node;
1457 int pnode; 1539 int pnode;
@@ -1459,24 +1541,24 @@ static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode)
1459 1541
1460 node = uvhub_to_first_node(uvhub); 1542 node = uvhub_to_first_node(uvhub);
1461 pnode = uv_blade_to_pnode(uvhub); 1543 pnode = uv_blade_to_pnode(uvhub);
1462 uv_activation_descriptor_init(node, pnode, base_pnode); 1544
1463 uv_payload_queue_init(node, pnode); 1545 activation_descriptor_init(node, pnode, base_pnode);
1546
1547 pq_init(node, pnode);
1464 /* 1548 /*
1465 * The below initialization can't be in firmware because the 1549 * The below initialization can't be in firmware because the
1466 * messaging IRQ will be determined by the OS. 1550 * messaging IRQ will be determined by the OS.
1467 */ 1551 */
1468 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; 1552 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1469 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, 1553 write_mmr_data_config(pnode, ((apicid << 32) | vector));
1470 ((apicid << 32) | vector));
1471} 1554}
1472 1555
1473/* 1556/*
1474 * We will set BAU_MISC_CONTROL with a timeout period. 1557 * We will set BAU_MISC_CONTROL with a timeout period.
1475 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. 1558 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1476 * So the destination timeout period has be be calculated from them. 1559 * So the destination timeout period has to be calculated from them.
1477 */ 1560 */
1478static int 1561static int calculate_destination_timeout(void)
1479calculate_destination_timeout(void)
1480{ 1562{
1481 unsigned long mmr_image; 1563 unsigned long mmr_image;
1482 int mult1; 1564 int mult1;
@@ -1486,73 +1568,92 @@ calculate_destination_timeout(void)
1486 int ret; 1568 int ret;
1487 unsigned long ts_ns; 1569 unsigned long ts_ns;
1488 1570
1489 mult1 = UV_INTD_SOFT_ACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; 1571 if (is_uv1_hub()) {
1490 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); 1572 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
1491 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; 1573 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1492 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); 1574 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1493 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; 1575 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1494 base = timeout_base_ns[index]; 1576 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1495 ts_ns = base * mult1 * mult2; 1577 base = timeout_base_ns[index];
1496 ret = ts_ns / 1000; 1578 ts_ns = base * mult1 * mult2;
1579 ret = ts_ns / 1000;
1580 } else {
1581 /* 4 bits 0/1 for 10/80us, 3 bits of multiplier */
1582 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1583 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1584 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
1585 mult1 = 80;
1586 else
1587 mult1 = 10;
1588 base = mmr_image & UV2_ACK_MASK;
1589 ret = mult1 * base;
1590 }
1497 return ret; 1591 return ret;
1498} 1592}
1499 1593
1594static void __init init_per_cpu_tunables(void)
1595{
1596 int cpu;
1597 struct bau_control *bcp;
1598
1599 for_each_present_cpu(cpu) {
1600 bcp = &per_cpu(bau_control, cpu);
1601 bcp->baudisabled = 0;
1602 bcp->statp = &per_cpu(ptcstats, cpu);
1603 /* time interval to catch a hardware stay-busy bug */
1604 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1605 bcp->max_concurr = max_concurr;
1606 bcp->max_concurr_const = max_concurr;
1607 bcp->plugged_delay = plugged_delay;
1608 bcp->plugsb4reset = plugsb4reset;
1609 bcp->timeoutsb4reset = timeoutsb4reset;
1610 bcp->ipi_reset_limit = ipi_reset_limit;
1611 bcp->complete_threshold = complete_threshold;
1612 bcp->cong_response_us = congested_respns_us;
1613 bcp->cong_reps = congested_reps;
1614 bcp->cong_period = congested_period;
1615 }
1616}
1617
1500/* 1618/*
1501 * initialize the bau_control structure for each cpu 1619 * Scan all cpus to collect blade and socket summaries.
1502 */ 1620 */
1503static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode) 1621static int __init get_cpu_topology(int base_pnode,
1622 struct uvhub_desc *uvhub_descs,
1623 unsigned char *uvhub_mask)
1504{ 1624{
1505 int i;
1506 int cpu; 1625 int cpu;
1507 int tcpu;
1508 int pnode; 1626 int pnode;
1509 int uvhub; 1627 int uvhub;
1510 int have_hmaster; 1628 int socket;
1511 short socket = 0;
1512 unsigned short socket_mask;
1513 unsigned char *uvhub_mask;
1514 struct bau_control *bcp; 1629 struct bau_control *bcp;
1515 struct uvhub_desc *bdp; 1630 struct uvhub_desc *bdp;
1516 struct socket_desc *sdp; 1631 struct socket_desc *sdp;
1517 struct bau_control *hmaster = NULL;
1518 struct bau_control *smaster = NULL;
1519 struct socket_desc {
1520 short num_cpus;
1521 short cpu_number[MAX_CPUS_PER_SOCKET];
1522 };
1523 struct uvhub_desc {
1524 unsigned short socket_mask;
1525 short num_cpus;
1526 short uvhub;
1527 short pnode;
1528 struct socket_desc socket[2];
1529 };
1530 struct uvhub_desc *uvhub_descs;
1531
1532 timeout_us = calculate_destination_timeout();
1533 1632
1534 uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
1535 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
1536 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
1537 for_each_present_cpu(cpu) { 1633 for_each_present_cpu(cpu) {
1538 bcp = &per_cpu(bau_control, cpu); 1634 bcp = &per_cpu(bau_control, cpu);
1635
1539 memset(bcp, 0, sizeof(struct bau_control)); 1636 memset(bcp, 0, sizeof(struct bau_control));
1637
1540 pnode = uv_cpu_hub_info(cpu)->pnode; 1638 pnode = uv_cpu_hub_info(cpu)->pnode;
1541 if ((pnode - base_part_pnode) >= UV_DISTRIBUTION_SIZE) { 1639 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
1542 printk(KERN_EMERG 1640 printk(KERN_EMERG
1543 "cpu %d pnode %d-%d beyond %d; BAU disabled\n", 1641 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1544 cpu, pnode, base_part_pnode, 1642 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
1545 UV_DISTRIBUTION_SIZE);
1546 return 1; 1643 return 1;
1547 } 1644 }
1645
1548 bcp->osnode = cpu_to_node(cpu); 1646 bcp->osnode = cpu_to_node(cpu);
1549 bcp->partition_base_pnode = uv_partition_base_pnode; 1647 bcp->partition_base_pnode = base_pnode;
1648
1550 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; 1649 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1551 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); 1650 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1552 bdp = &uvhub_descs[uvhub]; 1651 bdp = &uvhub_descs[uvhub];
1652
1553 bdp->num_cpus++; 1653 bdp->num_cpus++;
1554 bdp->uvhub = uvhub; 1654 bdp->uvhub = uvhub;
1555 bdp->pnode = pnode; 1655 bdp->pnode = pnode;
1656
1556 /* kludge: 'assuming' one node per socket, and assuming that 1657 /* kludge: 'assuming' one node per socket, and assuming that
1557 disabling a socket just leaves a gap in node numbers */ 1658 disabling a socket just leaves a gap in node numbers */
1558 socket = bcp->osnode & 1; 1659 socket = bcp->osnode & 1;
@@ -1561,84 +1662,129 @@ static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode)
1561 sdp->cpu_number[sdp->num_cpus] = cpu; 1662 sdp->cpu_number[sdp->num_cpus] = cpu;
1562 sdp->num_cpus++; 1663 sdp->num_cpus++;
1563 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { 1664 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1564 printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus); 1665 printk(KERN_EMERG "%d cpus per socket invalid\n",
1666 sdp->num_cpus);
1565 return 1; 1667 return 1;
1566 } 1668 }
1567 } 1669 }
1670 return 0;
1671}
1672
1673/*
1674 * Each socket is to get a local array of pnodes/hubs.
1675 */
1676static void make_per_cpu_thp(struct bau_control *smaster)
1677{
1678 int cpu;
1679 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
1680
1681 smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
1682 memset(smaster->thp, 0, hpsz);
1683 for_each_present_cpu(cpu) {
1684 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
1685 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1686 }
1687}
1688
1689/*
1690 * Initialize all the per_cpu information for the cpu's on a given socket,
1691 * given what has been gathered into the socket_desc struct.
1692 * And reports the chosen hub and socket masters back to the caller.
1693 */
1694static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
1695 struct bau_control **smasterp,
1696 struct bau_control **hmasterp)
1697{
1698 int i;
1699 int cpu;
1700 struct bau_control *bcp;
1701
1702 for (i = 0; i < sdp->num_cpus; i++) {
1703 cpu = sdp->cpu_number[i];
1704 bcp = &per_cpu(bau_control, cpu);
1705 bcp->cpu = cpu;
1706 if (i == 0) {
1707 *smasterp = bcp;
1708 if (!(*hmasterp))
1709 *hmasterp = bcp;
1710 }
1711 bcp->cpus_in_uvhub = bdp->num_cpus;
1712 bcp->cpus_in_socket = sdp->num_cpus;
1713 bcp->socket_master = *smasterp;
1714 bcp->uvhub = bdp->uvhub;
1715 bcp->uvhub_master = *hmasterp;
1716 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
1717 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
1718 printk(KERN_EMERG "%d cpus per uvhub invalid\n",
1719 bcp->uvhub_cpu);
1720 return 1;
1721 }
1722 }
1723 return 0;
1724}
1725
1726/*
1727 * Summarize the blade and socket topology into the per_cpu structures.
1728 */
1729static int __init summarize_uvhub_sockets(int nuvhubs,
1730 struct uvhub_desc *uvhub_descs,
1731 unsigned char *uvhub_mask)
1732{
1733 int socket;
1734 int uvhub;
1735 unsigned short socket_mask;
1736
1568 for (uvhub = 0; uvhub < nuvhubs; uvhub++) { 1737 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1738 struct uvhub_desc *bdp;
1739 struct bau_control *smaster = NULL;
1740 struct bau_control *hmaster = NULL;
1741
1569 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) 1742 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
1570 continue; 1743 continue;
1571 have_hmaster = 0; 1744
1572 bdp = &uvhub_descs[uvhub]; 1745 bdp = &uvhub_descs[uvhub];
1573 socket_mask = bdp->socket_mask; 1746 socket_mask = bdp->socket_mask;
1574 socket = 0; 1747 socket = 0;
1575 while (socket_mask) { 1748 while (socket_mask) {
1576 if (!(socket_mask & 1)) 1749 struct socket_desc *sdp;
1577 goto nextsocket; 1750 if ((socket_mask & 1)) {
1578 sdp = &bdp->socket[socket]; 1751 sdp = &bdp->socket[socket];
1579 for (i = 0; i < sdp->num_cpus; i++) { 1752 if (scan_sock(sdp, bdp, &smaster, &hmaster))
1580 cpu = sdp->cpu_number[i];
1581 bcp = &per_cpu(bau_control, cpu);
1582 bcp->cpu = cpu;
1583 if (i == 0) {
1584 smaster = bcp;
1585 if (!have_hmaster) {
1586 have_hmaster++;
1587 hmaster = bcp;
1588 }
1589 }
1590 bcp->cpus_in_uvhub = bdp->num_cpus;
1591 bcp->cpus_in_socket = sdp->num_cpus;
1592 bcp->socket_master = smaster;
1593 bcp->uvhub = bdp->uvhub;
1594 bcp->uvhub_master = hmaster;
1595 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->
1596 blade_processor_id;
1597 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
1598 printk(KERN_EMERG
1599 "%d cpus per uvhub invalid\n",
1600 bcp->uvhub_cpu);
1601 return 1; 1753 return 1;
1602 }
1603 } 1754 }
1604nextsocket:
1605 socket++; 1755 socket++;
1606 socket_mask = (socket_mask >> 1); 1756 socket_mask = (socket_mask >> 1);
1607 /* each socket gets a local array of pnodes/hubs */ 1757 make_per_cpu_thp(smaster);
1608 bcp = smaster;
1609 bcp->target_hub_and_pnode = kmalloc_node(
1610 sizeof(struct hub_and_pnode) *
1611 num_possible_cpus(), GFP_KERNEL, bcp->osnode);
1612 memset(bcp->target_hub_and_pnode, 0,
1613 sizeof(struct hub_and_pnode) *
1614 num_possible_cpus());
1615 for_each_present_cpu(tcpu) {
1616 bcp->target_hub_and_pnode[tcpu].pnode =
1617 uv_cpu_hub_info(tcpu)->pnode;
1618 bcp->target_hub_and_pnode[tcpu].uvhub =
1619 uv_cpu_hub_info(tcpu)->numa_blade_id;
1620 }
1621 } 1758 }
1622 } 1759 }
1760 return 0;
1761}
1762
1763/*
1764 * initialize the bau_control structure for each cpu
1765 */
1766static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
1767{
1768 unsigned char *uvhub_mask;
1769 void *vp;
1770 struct uvhub_desc *uvhub_descs;
1771
1772 timeout_us = calculate_destination_timeout();
1773
1774 vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
1775 uvhub_descs = (struct uvhub_desc *)vp;
1776 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
1777 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
1778
1779 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
1780 return 1;
1781
1782 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
1783 return 1;
1784
1623 kfree(uvhub_descs); 1785 kfree(uvhub_descs);
1624 kfree(uvhub_mask); 1786 kfree(uvhub_mask);
1625 for_each_present_cpu(cpu) { 1787 init_per_cpu_tunables();
1626 bcp = &per_cpu(bau_control, cpu);
1627 bcp->baudisabled = 0;
1628 bcp->statp = &per_cpu(ptcstats, cpu);
1629 /* time interval to catch a hardware stay-busy bug */
1630 bcp->timeout_interval = microsec_2_cycles(2*timeout_us);
1631 bcp->max_bau_concurrent = max_bau_concurrent;
1632 bcp->max_bau_concurrent_constant = max_bau_concurrent;
1633 bcp->plugged_delay = plugged_delay;
1634 bcp->plugsb4reset = plugsb4reset;
1635 bcp->timeoutsb4reset = timeoutsb4reset;
1636 bcp->ipi_reset_limit = ipi_reset_limit;
1637 bcp->complete_threshold = complete_threshold;
1638 bcp->congested_response_us = congested_response_us;
1639 bcp->congested_reps = congested_reps;
1640 bcp->congested_period = congested_period;
1641 }
1642 return 0; 1788 return 0;
1643} 1789}
1644 1790
@@ -1651,8 +1797,9 @@ static int __init uv_bau_init(void)
1651 int pnode; 1797 int pnode;
1652 int nuvhubs; 1798 int nuvhubs;
1653 int cur_cpu; 1799 int cur_cpu;
1800 int cpus;
1654 int vector; 1801 int vector;
1655 unsigned long mmr; 1802 cpumask_var_t *mask;
1656 1803
1657 if (!is_uv_system()) 1804 if (!is_uv_system())
1658 return 0; 1805 return 0;
@@ -1660,24 +1807,25 @@ static int __init uv_bau_init(void)
1660 if (nobau) 1807 if (nobau)
1661 return 0; 1808 return 0;
1662 1809
1663 for_each_possible_cpu(cur_cpu) 1810 for_each_possible_cpu(cur_cpu) {
1664 zalloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu), 1811 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
1665 GFP_KERNEL, cpu_to_node(cur_cpu)); 1812 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
1813 }
1666 1814
1667 uv_nshift = uv_hub_info->m_val; 1815 uv_nshift = uv_hub_info->m_val;
1668 uv_mmask = (1UL << uv_hub_info->m_val) - 1; 1816 uv_mmask = (1UL << uv_hub_info->m_val) - 1;
1669 nuvhubs = uv_num_possible_blades(); 1817 nuvhubs = uv_num_possible_blades();
1670 spin_lock_init(&disable_lock); 1818 spin_lock_init(&disable_lock);
1671 congested_cycles = microsec_2_cycles(congested_response_us); 1819 congested_cycles = usec_2_cycles(congested_respns_us);
1672 1820
1673 uv_partition_base_pnode = 0x7fffffff; 1821 uv_base_pnode = 0x7fffffff;
1674 for (uvhub = 0; uvhub < nuvhubs; uvhub++) { 1822 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1675 if (uv_blade_nr_possible_cpus(uvhub) && 1823 cpus = uv_blade_nr_possible_cpus(uvhub);
1676 (uv_blade_to_pnode(uvhub) < uv_partition_base_pnode)) 1824 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
1677 uv_partition_base_pnode = uv_blade_to_pnode(uvhub); 1825 uv_base_pnode = uv_blade_to_pnode(uvhub);
1678 } 1826 }
1679 1827
1680 if (uv_init_per_cpu(nuvhubs, uv_partition_base_pnode)) { 1828 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
1681 nobau = 1; 1829 nobau = 1;
1682 return 0; 1830 return 0;
1683 } 1831 }
@@ -1685,21 +1833,21 @@ static int __init uv_bau_init(void)
1685 vector = UV_BAU_MESSAGE; 1833 vector = UV_BAU_MESSAGE;
1686 for_each_possible_blade(uvhub) 1834 for_each_possible_blade(uvhub)
1687 if (uv_blade_nr_possible_cpus(uvhub)) 1835 if (uv_blade_nr_possible_cpus(uvhub))
1688 uv_init_uvhub(uvhub, vector, uv_partition_base_pnode); 1836 init_uvhub(uvhub, vector, uv_base_pnode);
1689 1837
1690 uv_enable_timeouts(); 1838 enable_timeouts();
1691 alloc_intr_gate(vector, uv_bau_message_intr1); 1839 alloc_intr_gate(vector, uv_bau_message_intr1);
1692 1840
1693 for_each_possible_blade(uvhub) { 1841 for_each_possible_blade(uvhub) {
1694 if (uv_blade_nr_possible_cpus(uvhub)) { 1842 if (uv_blade_nr_possible_cpus(uvhub)) {
1843 unsigned long val;
1844 unsigned long mmr;
1695 pnode = uv_blade_to_pnode(uvhub); 1845 pnode = uv_blade_to_pnode(uvhub);
1696 /* INIT the bau */ 1846 /* INIT the bau */
1697 uv_write_global_mmr64(pnode, 1847 val = 1L << 63;
1698 UVH_LB_BAU_SB_ACTIVATION_CONTROL, 1848 write_gmmr_activation(pnode, val);
1699 ((unsigned long)1 << 63));
1700 mmr = 1; /* should be 1 to broadcast to both sockets */ 1849 mmr = 1; /* should be 1 to broadcast to both sockets */
1701 uv_write_global_mmr64(pnode, UVH_BAU_DATA_BROADCAST, 1850 write_mmr_data_broadcast(pnode, mmr);
1702 mmr);
1703 } 1851 }
1704 } 1852 }
1705 1853
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 0eb90184515f..9f29a01ee1b3 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -99,8 +99,12 @@ static void uv_rtc_send_IPI(int cpu)
99/* Check for an RTC interrupt pending */ 99/* Check for an RTC interrupt pending */
100static int uv_intr_pending(int pnode) 100static int uv_intr_pending(int pnode)
101{ 101{
102 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 102 if (is_uv1_hub())
103 UVH_EVENT_OCCURRED0_RTC1_MASK; 103 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
104 UV1H_EVENT_OCCURRED0_RTC1_MASK;
105 else
106 return uv_read_global_mmr64(pnode, UV2H_EVENT_OCCURRED2) &
107 UV2H_EVENT_OCCURRED2_RTC_1_MASK;
104} 108}
105 109
106/* Setup interrupt and return non-zero if early expiration occurred. */ 110/* Setup interrupt and return non-zero if early expiration occurred. */
@@ -114,8 +118,12 @@ static int uv_setup_intr(int cpu, u64 expires)
114 UVH_RTC1_INT_CONFIG_M_MASK); 118 UVH_RTC1_INT_CONFIG_M_MASK);
115 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); 119 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
116 120
117 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 121 if (is_uv1_hub())
118 UVH_EVENT_OCCURRED0_RTC1_MASK); 122 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
123 UV1H_EVENT_OCCURRED0_RTC1_MASK);
124 else
125 uv_write_global_mmr64(pnode, UV2H_EVENT_OCCURRED2_ALIAS,
126 UV2H_EVENT_OCCURRED2_RTC_1_MASK);
119 127
120 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | 128 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
121 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); 129 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 15:24:56 -0500