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authorLennert Buytenhek <buytenh@wantstofly.org>2008-06-22 16:45:09 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 16:45:09 -0400
commita9311cfed241ebcd6b5f9be5c8c6d519bf22f9e7 (patch)
treee8d8fdf57be1e05dfb78005e71e4f62a109633c5 /arch
parent0a17c7bc0b81e4556eea08c7e27923e5534d3c25 (diff)
[ARM] Orion: PCIe x4/x1 detection support
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either be used in x4 mode or in quad x1 mode. This patch adds an accessor function to the generic plat-orion PCIe handling code to detect in which of the two modes we're running (which is determined by strap pins and/or configured by the bootloader). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-orion/pcie.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index abfda53f1800..ca32c60e14d7 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -39,6 +39,7 @@
39#define PCIE_CONF_DATA_OFF 0x18fc 39#define PCIE_CONF_DATA_OFF 0x18fc
40#define PCIE_MASK_OFF 0x1910 40#define PCIE_MASK_OFF 0x1910
41#define PCIE_CTRL_OFF 0x1a00 41#define PCIE_CTRL_OFF 0x1a00
42#define PCIE_CTRL_X1_MODE 0x0001
42#define PCIE_STAT_OFF 0x1a04 43#define PCIE_STAT_OFF 0x1a04
43#define PCIE_STAT_DEV_OFFS 20 44#define PCIE_STAT_DEV_OFFS 20
44#define PCIE_STAT_DEV_MASK 0x1f 45#define PCIE_STAT_DEV_MASK 0x1f
@@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base)
62 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 63 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
63} 64}
64 65
66int __init orion_pcie_x4_mode(void __iomem *base)
67{
68 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
69}
70
65int orion_pcie_get_local_bus_nr(void __iomem *base) 71int orion_pcie_get_local_bus_nr(void __iomem *base)
66{ 72{
67 u32 stat = readl(base + PCIE_STAT_OFF); 73 u32 stat = readl(base + PCIE_STAT_OFF);