diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-03 19:24:35 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-03 19:24:35 -0400 |
commit | a9238741987386bb549d61572973c7e62b2a4145 (patch) | |
tree | 4e49f9c472f86b88cd569a088f7c0ac87ce8b78a /arch | |
parent | 40031da445fb4d269af9c7c445b2adf674f171e7 (diff) | |
parent | e89c33168aad32436da842ddda307dcc31c0c4e2 (diff) |
Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
PCI device hotplug:
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)
MPS (Max Payload Size):
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)
SR-IOV:
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)
Virtualization:
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)
Miscellaneous:
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
PCI: exynos: Add I/O access wrappers
PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
PCI: Remove pcie_cap_has_devctl()
PCI: Support PCIe Capability Slot registers only for ports with slots
PCI: Remove PCIe Capability version checks
PCI: Allow PCIe Capability link-related register access for switches
PCI: Add offsets of PCIe capability registers
PCI: Tidy bitmasks and spacing of PCIe capability definitions
PCI: Remove obsolete comment reference to pci_pcie_cap2()
PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
PCI: Rename PCIe capability definitions to follow convention
PCI: Warn if unsafe MPS settings detected
PCI: Fix MPS peer-to-peer DMA comment syntax
PCI: Disable decoding for BAR sizing only when it was actually enabled
PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
PCI: Don't restrict MPS for slots below Root Ports
PCI: Simplify MPS test for Downstream Port
PCI: Remove unnecessary check for pcie_get_mps() failure
...
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boot/dts/exynos5440.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/kernel/bios32.c | 5 | ||||
-rw-r--r-- | arch/frv/mb93090-mb00/pci-vdk.c | 2 | ||||
-rw-r--r-- | arch/m68k/platform/coldfire/pci.c | 1 | ||||
-rw-r--r-- | arch/mips/pci/pci.c | 1 | ||||
-rw-r--r-- | arch/powerpc/kernel/pci-common.c | 8 | ||||
-rw-r--r-- | arch/sh/drivers/pci/pci.c | 1 | ||||
-rw-r--r-- | arch/tile/kernel/pci_gx.c | 9 | ||||
-rw-r--r-- | arch/x86/pci/acpi.c | 9 | ||||
-rw-r--r-- | arch/x86/pci/mmconfig-shared.c | 7 | ||||
-rw-r--r-- | arch/x86/pci/mrst.c | 41 |
11 files changed, 34 insertions, 52 deletions
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index ff7f5d855845..586134e2a382 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
@@ -248,6 +248,7 @@ | |||
248 | #interrupt-cells = <1>; | 248 | #interrupt-cells = <1>; |
249 | interrupt-map-mask = <0 0 0 0>; | 249 | interrupt-map-mask = <0 0 0 0>; |
250 | interrupt-map = <0x0 0 &gic 53>; | 250 | interrupt-map = <0x0 0 &gic 53>; |
251 | num-lanes = <4>; | ||
251 | }; | 252 | }; |
252 | 253 | ||
253 | pcie@2a0000 { | 254 | pcie@2a0000 { |
@@ -267,5 +268,6 @@ | |||
267 | #interrupt-cells = <1>; | 268 | #interrupt-cells = <1>; |
268 | interrupt-map-mask = <0 0 0 0>; | 269 | interrupt-map-mask = <0 0 0 0>; |
269 | interrupt-map = <0x0 0 &gic 56>; | 270 | interrupt-map = <0x0 0 &gic 56>; |
271 | num-lanes = <4>; | ||
270 | }; | 272 | }; |
271 | }; | 273 | }; |
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 261fcc826169..88e14d74b6de 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c | |||
@@ -525,11 +525,6 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) | |||
525 | * Assign resources. | 525 | * Assign resources. |
526 | */ | 526 | */ |
527 | pci_bus_assign_resources(bus); | 527 | pci_bus_assign_resources(bus); |
528 | |||
529 | /* | ||
530 | * Enable bridges | ||
531 | */ | ||
532 | pci_enable_bridges(bus); | ||
533 | } | 528 | } |
534 | 529 | ||
535 | /* | 530 | /* |
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c index 0aa35f0eb0db..deb67843693c 100644 --- a/arch/frv/mb93090-mb00/pci-vdk.c +++ b/arch/frv/mb93090-mb00/pci-vdk.c | |||
@@ -320,7 +320,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); | |||
320 | * are examined. | 320 | * are examined. |
321 | */ | 321 | */ |
322 | 322 | ||
323 | void __init pcibios_fixup_bus(struct pci_bus *bus) | 323 | void pcibios_fixup_bus(struct pci_bus *bus) |
324 | { | 324 | { |
325 | #if 0 | 325 | #if 0 |
326 | printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); | 326 | printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); |
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c index b33f97a13e6d..df9679238b6d 100644 --- a/arch/m68k/platform/coldfire/pci.c +++ b/arch/m68k/platform/coldfire/pci.c | |||
@@ -319,7 +319,6 @@ static int __init mcf_pci_init(void) | |||
319 | pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq); | 319 | pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq); |
320 | pci_bus_size_bridges(rootbus); | 320 | pci_bus_size_bridges(rootbus); |
321 | pci_bus_assign_resources(rootbus); | 321 | pci_bus_assign_resources(rootbus); |
322 | pci_enable_bridges(rootbus); | ||
323 | return 0; | 322 | return 0; |
324 | } | 323 | } |
325 | 324 | ||
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 594e60d6a43b..33e7aa52d9c4 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c | |||
@@ -113,7 +113,6 @@ static void pcibios_scanbus(struct pci_controller *hose) | |||
113 | if (!pci_has_flag(PCI_PROBE_ONLY)) { | 113 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
114 | pci_bus_size_bridges(bus); | 114 | pci_bus_size_bridges(bus); |
115 | pci_bus_assign_resources(bus); | 115 | pci_bus_assign_resources(bus); |
116 | pci_enable_bridges(bus); | ||
117 | } | 116 | } |
118 | } | 117 | } |
119 | } | 118 | } |
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 7d22a675fe1a..2b4a9a4db7d9 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c | |||
@@ -1674,12 +1674,8 @@ void pcibios_scan_phb(struct pci_controller *hose) | |||
1674 | /* Configure PCI Express settings */ | 1674 | /* Configure PCI Express settings */ |
1675 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { | 1675 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
1676 | struct pci_bus *child; | 1676 | struct pci_bus *child; |
1677 | list_for_each_entry(child, &bus->children, node) { | 1677 | list_for_each_entry(child, &bus->children, node) |
1678 | struct pci_dev *self = child->self; | 1678 | pcie_bus_configure_settings(child); |
1679 | if (!self) | ||
1680 | continue; | ||
1681 | pcie_bus_configure_settings(child, self->pcie_mpss); | ||
1682 | } | ||
1683 | } | 1679 | } |
1684 | } | 1680 | } |
1685 | 1681 | ||
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 102f5d58b037..60ed3e1c4b75 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c | |||
@@ -69,7 +69,6 @@ static void pcibios_scanbus(struct pci_channel *hose) | |||
69 | 69 | ||
70 | pci_bus_size_bridges(bus); | 70 | pci_bus_size_bridges(bus); |
71 | pci_bus_assign_resources(bus); | 71 | pci_bus_assign_resources(bus); |
72 | pci_enable_bridges(bus); | ||
73 | } else { | 72 | } else { |
74 | pci_free_resource_list(&resources); | 73 | pci_free_resource_list(&resources); |
75 | } | 74 | } |
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 11425633b2d7..6640e7bbeaa2 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c | |||
@@ -508,13 +508,8 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller) | |||
508 | rc_dev_cap.word); | 508 | rc_dev_cap.word); |
509 | 509 | ||
510 | /* Configure PCI Express MPS setting. */ | 510 | /* Configure PCI Express MPS setting. */ |
511 | list_for_each_entry(child, &root_bus->children, node) { | 511 | list_for_each_entry(child, &root_bus->children, node) |
512 | struct pci_dev *self = child->self; | 512 | pcie_bus_configure_settings(child); |
513 | if (!self) | ||
514 | continue; | ||
515 | |||
516 | pcie_bus_configure_settings(child, self->pcie_mpss); | ||
517 | } | ||
518 | 513 | ||
519 | /* | 514 | /* |
520 | * Set the mac_config register in trio based on the MPS/MRS of the link. | 515 | * Set the mac_config register in trio based on the MPS/MRS of the link. |
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index d641897a1f4e..b30e937689d6 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c | |||
@@ -568,13 +568,8 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) | |||
568 | */ | 568 | */ |
569 | if (bus) { | 569 | if (bus) { |
570 | struct pci_bus *child; | 570 | struct pci_bus *child; |
571 | list_for_each_entry(child, &bus->children, node) { | 571 | list_for_each_entry(child, &bus->children, node) |
572 | struct pci_dev *self = child->self; | 572 | pcie_bus_configure_settings(child); |
573 | if (!self) | ||
574 | continue; | ||
575 | |||
576 | pcie_bus_configure_settings(child, self->pcie_mpss); | ||
577 | } | ||
578 | } | 573 | } |
579 | 574 | ||
580 | if (bus && node != -1) { | 575 | if (bus && node != -1) { |
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 082e88129712..5596c7bdd327 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c | |||
@@ -700,7 +700,7 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, | |||
700 | if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed) | 700 | if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed) |
701 | return -ENODEV; | 701 | return -ENODEV; |
702 | 702 | ||
703 | if (start > end) | 703 | if (start > end || !addr) |
704 | return -EINVAL; | 704 | return -EINVAL; |
705 | 705 | ||
706 | mutex_lock(&pci_mmcfg_lock); | 706 | mutex_lock(&pci_mmcfg_lock); |
@@ -716,11 +716,6 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, | |||
716 | return -EEXIST; | 716 | return -EEXIST; |
717 | } | 717 | } |
718 | 718 | ||
719 | if (!addr) { | ||
720 | mutex_unlock(&pci_mmcfg_lock); | ||
721 | return -EINVAL; | ||
722 | } | ||
723 | |||
724 | rc = -EBUSY; | 719 | rc = -EBUSY; |
725 | cfg = pci_mmconfig_alloc(seg, start, end, addr); | 720 | cfg = pci_mmconfig_alloc(seg, start, end, addr); |
726 | if (cfg == NULL) { | 721 | if (cfg == NULL) { |
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c index 6eb18c42a28a..903fded50786 100644 --- a/arch/x86/pci/mrst.c +++ b/arch/x86/pci/mrst.c | |||
@@ -23,11 +23,11 @@ | |||
23 | #include <linux/ioport.h> | 23 | #include <linux/ioport.h> |
24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
25 | #include <linux/dmi.h> | 25 | #include <linux/dmi.h> |
26 | #include <linux/acpi.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/smp.h> | ||
26 | 29 | ||
27 | #include <asm/acpi.h> | ||
28 | #include <asm/segment.h> | 30 | #include <asm/segment.h> |
29 | #include <asm/io.h> | ||
30 | #include <asm/smp.h> | ||
31 | #include <asm/pci_x86.h> | 31 | #include <asm/pci_x86.h> |
32 | #include <asm/hw_irq.h> | 32 | #include <asm/hw_irq.h> |
33 | #include <asm/io_apic.h> | 33 | #include <asm/io_apic.h> |
@@ -43,7 +43,7 @@ | |||
43 | #define PCI_FIXED_BAR_4_SIZE 0x14 | 43 | #define PCI_FIXED_BAR_4_SIZE 0x14 |
44 | #define PCI_FIXED_BAR_5_SIZE 0x1c | 44 | #define PCI_FIXED_BAR_5_SIZE 0x1c |
45 | 45 | ||
46 | static int pci_soc_mode = 0; | 46 | static int pci_soc_mode; |
47 | 47 | ||
48 | /** | 48 | /** |
49 | * fixed_bar_cap - return the offset of the fixed BAR cap if found | 49 | * fixed_bar_cap - return the offset of the fixed BAR cap if found |
@@ -141,7 +141,8 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, | |||
141 | */ | 141 | */ |
142 | static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) | 142 | static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) |
143 | { | 143 | { |
144 | /* This is a workaround for A0 LNC bug where PCI status register does | 144 | /* |
145 | * This is a workaround for A0 LNC bug where PCI status register does | ||
145 | * not have new CAP bit set. can not be written by SW either. | 146 | * not have new CAP bit set. can not be written by SW either. |
146 | * | 147 | * |
147 | * PCI header type in real LNC indicates a single function device, this | 148 | * PCI header type in real LNC indicates a single function device, this |
@@ -154,7 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) | |||
154 | || devfn == PCI_DEVFN(0, 0) | 155 | || devfn == PCI_DEVFN(0, 0) |
155 | || devfn == PCI_DEVFN(3, 0))) | 156 | || devfn == PCI_DEVFN(3, 0))) |
156 | return 1; | 157 | return 1; |
157 | return 0; /* langwell on others */ | 158 | return 0; /* Langwell on others */ |
158 | } | 159 | } |
159 | 160 | ||
160 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, | 161 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
@@ -172,7 +173,8 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, | |||
172 | { | 173 | { |
173 | int offset; | 174 | int offset; |
174 | 175 | ||
175 | /* On MRST, there is no PCI ROM BAR, this will cause a subsequent read | 176 | /* |
177 | * On MRST, there is no PCI ROM BAR, this will cause a subsequent read | ||
176 | * to ROM BAR return 0 then being ignored. | 178 | * to ROM BAR return 0 then being ignored. |
177 | */ | 179 | */ |
178 | if (where == PCI_ROM_ADDRESS) | 180 | if (where == PCI_ROM_ADDRESS) |
@@ -210,7 +212,8 @@ static int mrst_pci_irq_enable(struct pci_dev *dev) | |||
210 | 212 | ||
211 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | 213 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
212 | 214 | ||
213 | /* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to | 215 | /* |
216 | * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to | ||
214 | * IOAPIC RTE entries, so we just enable RTE for the device. | 217 | * IOAPIC RTE entries, so we just enable RTE for the device. |
215 | */ | 218 | */ |
216 | irq_attr.ioapic = mp_find_ioapic(dev->irq); | 219 | irq_attr.ioapic = mp_find_ioapic(dev->irq); |
@@ -235,7 +238,7 @@ struct pci_ops pci_mrst_ops = { | |||
235 | */ | 238 | */ |
236 | int __init pci_mrst_init(void) | 239 | int __init pci_mrst_init(void) |
237 | { | 240 | { |
238 | printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n"); | 241 | pr_info("Intel MID platform detected, using MID PCI ops\n"); |
239 | pci_mmcfg_late_init(); | 242 | pci_mmcfg_late_init(); |
240 | pcibios_enable_irq = mrst_pci_irq_enable; | 243 | pcibios_enable_irq = mrst_pci_irq_enable; |
241 | pci_root_ops = pci_mrst_ops; | 244 | pci_root_ops = pci_mrst_ops; |
@@ -244,17 +247,21 @@ int __init pci_mrst_init(void) | |||
244 | return 1; | 247 | return 1; |
245 | } | 248 | } |
246 | 249 | ||
247 | /* Langwell devices are not true pci devices, they are not subject to 10 ms | 250 | /* |
248 | * d3 to d0 delay required by pci spec. | 251 | * Langwell devices are not true PCI devices; they are not subject to 10 ms |
252 | * d3 to d0 delay required by PCI spec. | ||
249 | */ | 253 | */ |
250 | static void pci_d3delay_fixup(struct pci_dev *dev) | 254 | static void pci_d3delay_fixup(struct pci_dev *dev) |
251 | { | 255 | { |
252 | /* PCI fixups are effectively decided compile time. If we have a dual | 256 | /* |
253 | SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */ | 257 | * PCI fixups are effectively decided compile time. If we have a dual |
254 | if (!pci_soc_mode) | 258 | * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices. |
255 | return; | 259 | */ |
256 | /* true pci devices in lincroft should allow type 1 access, the rest | 260 | if (!pci_soc_mode) |
257 | * are langwell fake pci devices. | 261 | return; |
262 | /* | ||
263 | * True PCI devices in Lincroft should allow type 1 access, the rest | ||
264 | * are Langwell fake PCI devices. | ||
258 | */ | 265 | */ |
259 | if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) | 266 | if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) |
260 | return; | 267 | return; |