Merge tag 'efi-urgent' into x86/urgent

 * Avoid WARN_ON() when mapping BGRT on Baytrail (EFI 32-bit).

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

1753 files changed, 59393 insertions, 27077 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index d39dc9b95a2c..f6c6b345388c 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -2,6 +2,7 @@ config ALPHA
         bool
         default y
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select HAVE_AOUT
         select HAVE_IDE
         select HAVE_OPROFILE
@@ -16,6 +17,7 @@ config ALPHA
         select ARCH_WANT_IPC_PARSE_VERSION
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
+        select AUDIT_ARCH
         select GENERIC_CLOCKEVENTS
         select GENERIC_SMP_IDLE_THREAD
         select GENERIC_STRNCPY_FROM_USER
@@ -76,6 +78,8 @@ config GENERIC_ISA_DMA
 source "init/Kconfig"
 source "kernel/Kconfig.freezer"
 
+config AUDIT_ARCH
+        bool
 
 menu "System setup"
 
@@ -539,13 +543,13 @@ config SMP
         depends on ALPHA_SABLE || ALPHA_LYNX || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           See also the SMP-HOWTO available at
diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild
index f01fb505ad52..a73a8e208a4a 100644
--- a/arch/alpha/include/asm/Kbuild
+++ b/arch/alpha/include/asm/Kbuild
@@ -4,3 +4,4 @@ generic-y += clkdev.h
 generic-y += exec.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/alpha/include/asm/ptrace.h b/arch/alpha/include/asm/ptrace.h
index 21128505ddbe..9047c2fe8f23 100644
--- a/arch/alpha/include/asm/ptrace.h
+++ b/arch/alpha/include/asm/ptrace.h
@@ -19,4 +19,9 @@
 
 #define force_successful_syscall_return() (current_pt_regs()->r0 = 0)
 
+static inline unsigned long regs_return_value(struct pt_regs *regs)
+{
+        return regs->r0;
+}
+
 #endif
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index 453597b91f3a..3d6ce6d56fc9 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -70,6 +70,7 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define TIF_NOTIFY_RESUME       1       /* callback before returning to user */
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_SYSCALL_AUDIT       4       /* syscall audit active */
 #define TIF_DIE_IF_KERNEL       9       /* dik recursion lock */
 #define TIF_MEMDIE              13      /* is terminating due to OOM killer */
 
@@ -77,6 +78,7 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 
 /* Work to do on interrupt/exception return.  */
 #define _TIF_WORK_MASK          (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h
index e3a1491d5073..3de1394bcab8 100644
--- a/arch/alpha/include/uapi/asm/socket.h
+++ b/arch/alpha/include/uapi/asm/socket.h
@@ -85,4 +85,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _UAPI_ASM_SOCKET_H */
diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile
index 0d54650e78fc..3ecac0106c8a 100644
--- a/arch/alpha/kernel/Makefile
+++ b/arch/alpha/kernel/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_SRM_ENV)	+= srm_env.o
 obj-$(CONFIG_MODULES)   += module.o
 obj-$(CONFIG_PERF_EVENTS) += perf_event.o
 obj-$(CONFIG_RTC_DRV_ALPHA) += rtc.o
+obj-$(CONFIG_AUDIT)     += audit.o
 
 ifdef CONFIG_ALPHA_GENERIC
 
diff --git a/arch/alpha/kernel/audit.c b/arch/alpha/kernel/audit.c
new file mode 100644
index 000000000000..96a9d18ff4c4
--- /dev/null
+++ b/arch/alpha/kernel/audit.c
@@ -0,0 +1,60 @@
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/audit.h>
+#include <asm/unistd.h>
+
+static unsigned dir_class[] = {
+#include <asm-generic/audit_dir_write.h>
+~0U
+};
+
+static unsigned read_class[] = {
+#include <asm-generic/audit_read.h>
+~0U
+};
+
+static unsigned write_class[] = {
+#include <asm-generic/audit_write.h>
+~0U
+};
+
+static unsigned chattr_class[] = {
+#include <asm-generic/audit_change_attr.h>
+~0U
+};
+
+static unsigned signal_class[] = {
+#include <asm-generic/audit_signal.h>
+~0U
+};
+
+int audit_classify_arch(int arch)
+{
+        return 0;
+}
+
+int audit_classify_syscall(int abi, unsigned syscall)
+{
+        switch(syscall) {
+        case __NR_open:
+                return 2;
+        case __NR_openat:
+                return 3;
+        case __NR_execve:
+                return 5;
+        default:
+                return 0;
+        }
+}
+
+static int __init audit_classes_init(void)
+{
+        audit_register_class(AUDIT_CLASS_WRITE, write_class);
+        audit_register_class(AUDIT_CLASS_READ, read_class);
+        audit_register_class(AUDIT_CLASS_DIR_WRITE, dir_class);
+        audit_register_class(AUDIT_CLASS_CHATTR, chattr_class);
+        audit_register_class(AUDIT_CLASS_SIGNAL, signal_class);
+        return 0;
+}
+
+__initcall(audit_classes_init);
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index a969b95ee5ac..98703d99b565 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -465,7 +465,11 @@ entSys:
         .cfi_rel_offset $16, SP_OFF+24
         .cfi_rel_offset $17, SP_OFF+32
         .cfi_rel_offset $18, SP_OFF+40
-        blbs    $3, strace
+#ifdef CONFIG_AUDITSYSCALL
+        lda     $6, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
+        and     $3, $6, $3
+#endif
+        bne     $3, strace
         beq     $4, 1f
         ldq     $27, 0($5)
 1:      jsr     $26, ($27), alpha_ni_syscall
diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c
index 2b183b0d3207..99e8d4796c96 100644
--- a/arch/alpha/kernel/pci-sysfs.c
+++ b/arch/alpha/kernel/pci-sysfs.c
@@ -83,7 +83,7 @@ static int pci_mmap_resource(struct kobject *kobj,
         if (iomem_is_exclusive(res->start))
                 return -EINVAL;
 
-        pcibios_resource_to_bus(pdev, &bar, res);
+        pcibios_resource_to_bus(pdev->bus, &bar, res);
         vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));
         mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
 
@@ -139,7 +139,7 @@ static int sparse_mem_mmap_fits(struct pci_dev *pdev, int num)
         long dense_offset;
         unsigned long sparse_size;
 
-        pcibios_resource_to_bus(pdev, &bar, &pdev->resource[num]);
+        pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]);
 
         /* All core logic chips have 4G sparse address space, except
            CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index a21d0ab3b19e..eddee7720343 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -325,7 +325,7 @@ pci_map_single_1(struct pci_dev *pdev, void *cpu_addr, size_t size,
 /* Helper for generic DMA-mapping functions. */
 static struct pci_dev *alpha_gendev_to_pci(struct device *dev)
 {
-        if (dev && dev->bus == &pci_bus_type)
+        if (dev && dev_is_pci(dev))
                 return to_pci_dev(dev);
 
         /* Assume that non-PCI devices asking for DMA are either ISA or EISA,
diff --git a/arch/alpha/kernel/ptrace.c b/arch/alpha/kernel/ptrace.c
index 2a4a80ff4a20..86d835157b54 100644
--- a/arch/alpha/kernel/ptrace.c
+++ b/arch/alpha/kernel/ptrace.c
@@ -14,6 +14,7 @@
 #include <linux/security.h>
 #include <linux/signal.h>
 #include <linux/tracehook.h>
+#include <linux/audit.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -316,15 +317,18 @@ long arch_ptrace(struct task_struct *child, long request,
 asmlinkage unsigned long syscall_trace_enter(void)
 {
         unsigned long ret = 0;
+        struct pt_regs *regs = current_pt_regs();
         if (test_thread_flag(TIF_SYSCALL_TRACE) &&
             tracehook_report_syscall_entry(current_pt_regs()))
                 ret = -1UL;
+        audit_syscall_entry(AUDIT_ARCH_ALPHA, regs->r0, regs->r16, regs->r17, regs->r18, regs->r19);
         return ret ?: current_pt_regs()->r0;
 }
 
 asmlinkage void
 syscall_trace_leave(void)
 {
+        audit_syscall_exit(current_pt_regs());
         if (test_thread_flag(TIF_SYSCALL_TRACE))
                 tracehook_report_syscall_exit(current_pt_regs(), 0);
 }
diff --git a/arch/alpha/lib/csum_partial_copy.c b/arch/alpha/lib/csum_partial_copy.c
index ff3c10721caf..5675dca8dbb1 100644
--- a/arch/alpha/lib/csum_partial_copy.c
+++ b/arch/alpha/lib/csum_partial_copy.c
@@ -378,6 +378,11 @@ csum_partial_copy_from_user(const void __user *src, void *dst, int len,
 __wsum
 csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
 {
-        return csum_partial_copy_from_user((__force const void __user *)src,
-                        dst, len, sum, NULL);
+        __wsum checksum;
+        mm_segment_t oldfs = get_fs();
+        set_fs(KERNEL_DS);
+        checksum = csum_partial_copy_from_user((__force const void __user *)src,
+                                                dst, len, sum, NULL);
+        set_fs(oldfs);
+        return checksum;
 }
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 9063ae6553cc..9be30c8cb0c2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -128,8 +128,8 @@ config SMP
         default n
         help
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
 if SMP
 
@@ -409,17 +409,6 @@ config ARC_DBG_TLB_MISS_COUNT
           Counts number of I and D TLB Misses and exports them via Debugfs
           The counters can be cleared via Debugfs as well
 
-config CMDLINE_UBOOT
-        bool "Support U-boot kernel command line passing"
-        default n
-        help
-          If you are using U-boot (www.denx.de) and wish to pass the kernel
-          command line from the U-boot environment to the Linux kernel then
-          switch this option on.
-          ARC U-boot will setup the cmdline in RAM/flash and set r2 to point
-          to it. kernel startup code will append this to DeviceTree
-          /bootargs provided cmdline args.
-
 config ARC_BUILTIN_DTB_NAME
         string "Built in DTB"
         help
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index 9ae21c198007..0d3362991c31 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -12,6 +12,7 @@ generic-y += fcntl.h
 generic-y += fb.h
 generic-y += ftrace.h
 generic-y += hardirq.h
+generic-y += hash.h
 generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ioctls.h
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h
index 0283e9e44e0d..66ee5527aefc 100644
--- a/arch/arc/include/asm/linkage.h
+++ b/arch/arc/include/asm/linkage.h
@@ -11,6 +11,8 @@
 
 #ifdef __ASSEMBLY__
 
+#define ASM_NL           `      /* use '`' to mark new line in macro */
+
 /* Can't use the ENTRY macro in linux/linkage.h
  * gas considers ';' as comment vs. newline
  */
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index eefc29f08cdb..5d06eee43ea9 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -46,14 +46,14 @@ extern int smp_ipi_irq_setup(int cpu, int irq);
  *
  * @info:               SoC SMP specific info for /proc/cpuinfo etc
  * @cpu_kick:           For Master to kickstart a cpu (optionally at a PC)
- * @ipi_send:           To send IPI to a @cpumask
- * @ips_clear:          To clear IPI received by @cpu at @irq
+ * @ipi_send:           To send IPI to a @cpu
+ * @ips_clear:          To clear IPI received at @irq
  */
 struct plat_smp_ops {
         const char      *info;
         void            (*cpu_kick)(int cpu, unsigned long pc);
-        void            (*ipi_send)(void *callmap);
-        void            (*ipi_clear)(int cpu, int irq);
+        void            (*ipi_send)(int cpu);
+        void            (*ipi_clear)(int irq);
 };
 
 /* TBD: stop exporting it for direct population by platform */
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 2c878e964a64..991997269d02 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -49,25 +49,13 @@ stext:
         st.ab   0, [r5,4]
         brlt    r5, r6, 1b
 
-#ifdef CONFIG_CMDLINE_UBOOT
-        ; support for bootloader provided cmdline
-        ;    If cmdline passed by u-boot, then
-        ;    r0 = 1  (because ATAGS parsing, now retired, used to use 0)
-        ;    r1 = magic number (board identity)
-        ;    r2 = addr of cmdline string (somewhere in memory/flash)
-
-        brne    r0, 1, .Lother_bootup_chores    ; u-boot didn't pass cmdline
-        breq    r2, 0, .Lother_bootup_chores    ; or cmdline is NULL
-
-        mov     r5, @command_line
-1:
-        ldb.ab  r6, [r2, 1]
-        breq    r6, 0, .Lother_bootup_chores
-        b.d     1b
-        stb.ab  r6, [r5, 1]
-#endif
-
-.Lother_bootup_chores:
+        ; Uboot - kernel ABI
+        ;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
+        ;    r1 = magic number (board identity, unused as of now
+        ;    r2 = pointer to uboot provided cmdline or external DTB in mem
+        ; These are handled later in setup_arch()
+        st      r0, [@uboot_tag]
+        st      r2, [@uboot_arg]
 
         ; Identify if running on ISS vs Silicon
         ;       IDENTITY Reg [ 3  2  1  0 ]
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 643eae4436e0..119dddb752b2 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -29,7 +29,10 @@
 
 int running_on_hw = 1;  /* vs. on ISS */
 
-char __initdata command_line[COMMAND_LINE_SIZE];
+/* Part of U-boot ABI: see head.S */
+int __initdata uboot_tag;
+char __initdata *uboot_arg;
+
 const struct machine_desc *machine_desc;
 
 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
@@ -311,19 +314,40 @@ void setup_processor(void)
         arc_chk_fpu();
 }
 
+static inline int is_kernel(unsigned long addr)
+{
+        if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
+                return 1;
+        return 0;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
-        /* This also populates @boot_command_line from /bootargs */
-        machine_desc = setup_machine_fdt(__dtb_start);
-        if (!machine_desc)
-                panic("Embedded DT invalid\n");
-
-        /* Append any u-boot provided cmdline */
-#ifdef CONFIG_CMDLINE_UBOOT
-        /* Add a whitespace seperator between the 2 cmdlines */
-        strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
-        strlcat(boot_command_line, command_line, COMMAND_LINE_SIZE);
-#endif
+        /* make sure that uboot passed pointer to cmdline/dtb is valid */
+        if (uboot_tag && is_kernel((unsigned long)uboot_arg))
+                panic("Invalid uboot arg\n");
+
+        /* See if u-boot passed an external Device Tree blob */
+        machine_desc = setup_machine_fdt(uboot_arg);    /* uboot_tag == 2 */
+        if (!machine_desc) {
+                /* No, so try the embedded one */
+                machine_desc = setup_machine_fdt(__dtb_start);
+                if (!machine_desc)
+                        panic("Embedded DT invalid\n");
+
+                /*
+                 * If we are here, it is established that @uboot_arg didn't
+                 * point to DT blob. Instead if u-boot says it is cmdline,
+                 * Appent to embedded DT cmdline.
+                 * setup_machine_fdt() would have populated @boot_command_line
+                 */
+                if (uboot_tag == 1) {
+                        /* Ensure a whitespace between the 2 cmdlines */
+                        strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
+                        strlcat(boot_command_line, uboot_arg,
+                                COMMAND_LINE_SIZE);
+                }
+        }
 
         /* Save unparsed command line copy for /proc/cmdline */
         *cmdline_p = boot_command_line;
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index c2f9ebbc38f6..40859e5619f9 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -197,51 +197,65 @@ int __init setup_profiling_timer(unsigned int multiplier)
 /*              Inter Processor Interrupt Handling                           */
 /*****************************************************************************/
 
-/*
- * structures for inter-processor calls
- * A Collection of single bit ipi messages
- *
- */
-
-/*
- * TODO_rajesh investigate tlb message types.
- * IPI Timer not needed because each ARC has an individual Interrupting Timer
- */
 enum ipi_msg_type {
-        IPI_NOP = 0,
+        IPI_EMPTY = 0,
         IPI_RESCHEDULE = 1,
         IPI_CALL_FUNC,
-        IPI_CPU_STOP
+        IPI_CPU_STOP,
 };
 
-struct ipi_data {
-        unsigned long bits;
-};
+/*
+ * In arches with IRQ for each msg type (above), receiver can use IRQ-id  to
+ * figure out what msg was sent. For those which don't (ARC has dedicated IPI
+ * IRQ), the msg-type needs to be conveyed via per-cpu data
+ */
 
-static DEFINE_PER_CPU(struct ipi_data, ipi_data);
+static DEFINE_PER_CPU(unsigned long, ipi_data);
 
-static void ipi_send_msg(const struct cpumask *callmap, enum ipi_msg_type msg)
+static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg)
 {
+        unsigned long __percpu *ipi_data_ptr = per_cpu_ptr(&ipi_data, cpu);
+        unsigned long old, new;
         unsigned long flags;
-        unsigned int cpu;
+
+        pr_debug("%d Sending msg [%d] to %d\n", smp_processor_id(), msg, cpu);
 
         local_irq_save(flags);
 
-        for_each_cpu(cpu, callmap) {
-                struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
-                set_bit(msg, &ipi->bits);
-        }
+        /*
+         * Atomically write new msg bit (in case others are writing too),
+         * and read back old value
+         */
+        do {
+                new = old = *ipi_data_ptr;
+                new |= 1U << msg;
+        } while (cmpxchg(ipi_data_ptr, old, new) != old);
 
-        /* Call the platform specific cross-CPU call function  */
-        if (plat_smp_ops.ipi_send)
-                plat_smp_ops.ipi_send((void *)callmap);
+        /*
+         * Call the platform specific IPI kick function, but avoid if possible:
+         * Only do so if there's no pending msg from other concurrent sender(s).
+         * Otherwise, recevier will see this msg as well when it takes the
+         * IPI corresponding to that msg. This is true, even if it is already in
+         * IPI handler, because !@old means it has not yet dequeued the msg(s)
+         * so @new msg can be a free-loader
+         */
+        if (plat_smp_ops.ipi_send && !old)
+                plat_smp_ops.ipi_send(cpu);
 
         local_irq_restore(flags);
 }
 
+static void ipi_send_msg(const struct cpumask *callmap, enum ipi_msg_type msg)
+{
+        unsigned int cpu;
+
+        for_each_cpu(cpu, callmap)
+                ipi_send_msg_one(cpu, msg);
+}
+
 void smp_send_reschedule(int cpu)
 {
-        ipi_send_msg(cpumask_of(cpu), IPI_RESCHEDULE);
+        ipi_send_msg_one(cpu, IPI_RESCHEDULE);
 }
 
 void smp_send_stop(void)
@@ -254,7 +268,7 @@ void smp_send_stop(void)
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        ipi_send_msg(cpumask_of(cpu), IPI_CALL_FUNC);
+        ipi_send_msg_one(cpu, IPI_CALL_FUNC);
 }
 
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -265,33 +279,29 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 /*
  * ipi_cpu_stop - handle IPI from smp_send_stop()
  */
-static void ipi_cpu_stop(unsigned int cpu)
+static void ipi_cpu_stop(void)
 {
         machine_halt();
 }
 
-static inline void __do_IPI(unsigned long *ops, struct ipi_data *ipi, int cpu)
+static inline void __do_IPI(unsigned long msg)
 {
-        unsigned long msg = 0;
+        switch (msg) {
+        case IPI_RESCHEDULE:
+                scheduler_ipi();
+                break;
 
-        do {
-                msg = find_next_bit(ops, BITS_PER_LONG, msg+1);
+        case IPI_CALL_FUNC:
+                generic_smp_call_function_interrupt();
+                break;
 
-                switch (msg) {
-                case IPI_RESCHEDULE:
-                        scheduler_ipi();
-                        break;
-
-                case IPI_CALL_FUNC:
-                        generic_smp_call_function_interrupt();
-                        break;
-
-                case IPI_CPU_STOP:
-                        ipi_cpu_stop(cpu);
-                        break;
-                }
-        } while (msg < BITS_PER_LONG);
+        case IPI_CPU_STOP:
+                ipi_cpu_stop();
+                break;
 
+        default:
+                pr_warn("IPI with unexpected msg %ld\n", msg);
+        }
 }
 
 /*
@@ -300,19 +310,25 @@ static inline void __do_IPI(unsigned long *ops, struct ipi_data *ipi, int cpu)
  */
 irqreturn_t do_IPI(int irq, void *dev_id)
 {
-        int cpu = smp_processor_id();
-        struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
-        unsigned long ops;
+        unsigned long pending;
+
+        pr_debug("IPI [%ld] received on cpu %d\n",
+                 *this_cpu_ptr(&ipi_data), smp_processor_id());
 
         if (plat_smp_ops.ipi_clear)
-                plat_smp_ops.ipi_clear(cpu, irq);
+                plat_smp_ops.ipi_clear(irq);
 
         /*
-         * XXX: is this loop really needed
-         * And do we need to move ipi_clean inside
+         * "dequeue" the msg corresponding to this IPI (and possibly other
+         * piggybacked msg from elided IPIs: see ipi_send_msg_one() above)
          */
-        while ((ops = xchg(&ipi->bits, 0)) != 0)
-                __do_IPI(&ops, ipi, cpu);
+        pending = xchg(this_cpu_ptr(&ipi_data), 0);
+
+        do {
+                unsigned long msg = __ffs(pending);
+                __do_IPI(msg);
+                pending &= ~(1U << msg);
+        } while (pending);
 
         return IRQ_HANDLED;
 }
diff --git a/arch/arc/plat-arcfpga/smp.c b/arch/arc/plat-arcfpga/smp.c
index 91b55349a5f8..8a12741f5f7a 100644
--- a/arch/arc/plat-arcfpga/smp.c
+++ b/arch/arc/plat-arcfpga/smp.c
@@ -88,18 +88,14 @@ void iss_model_init_smp(unsigned int cpu)
         smp_ipi_irq_setup(cpu, IDU_INTERRUPT_0 + cpu);
 }
 
-static void iss_model_ipi_send(void *arg)
+static void iss_model_ipi_send(int cpu)
 {
-        struct cpumask *callmap = arg;
-        unsigned int cpu;
-
-        for_each_cpu(cpu, callmap)
-                idu_irq_assert(cpu);
+        idu_irq_assert(cpu);
 }
 
-static void iss_model_ipi_clear(int cpu, int irq)
+static void iss_model_ipi_clear(int irq)
 {
-        idu_irq_clear(IDU_INTERRUPT_0 + cpu);
+        idu_irq_clear(IDU_INTERRUPT_0 + smp_processor_id());
 }
 
 void iss_model_init_early_smp(void)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9c909fc29272..e25419817791 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -6,12 +6,13 @@ config ARM
         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
         select ARCH_HAVE_CUSTOM_GPIO_H
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_USE_BUILTIN_BSWAP
         select ARCH_USE_CMPXCHG_LOCKREF
         select ARCH_WANT_IPC_PARSE_VERSION
         select BUILDTIME_EXTABLE_SORT if MMU
         select CLONE_BACKWARDS
         select CPU_PM if (SUSPEND || CPU_IDLE)
-        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
+        select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_IDLE_POLL_SETUP
@@ -36,6 +37,7 @@ config ARM
         select HAVE_DMA_ATTRS
         select HAVE_DMA_CONTIGUOUS if MMU
         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
+        select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -63,6 +65,7 @@ config ARM
         select IRQ_FORCED_THREADING
         select KTIME_SCALAR
         select MODULES_USE_ELF_REL
+        select NO_BOOTMEM
         select OLD_SIGACTION
         select OLD_SIGSUSPEND3
         select PERF_USE_VMALLOC
@@ -314,6 +317,8 @@ config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARCH_HAS_CPUFREQ
         select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
+        select AUTO_ZRELADDR
         select COMMON_CLK
         select COMMON_CLK_VERSATILE
         select GENERIC_CLOCKEVENTS
@@ -411,6 +416,26 @@ config ARCH_EBSA110
           Ethernet interface, two PCMCIA sockets, two serial ports and a
           parallel port.
 
+config ARCH_EFM32
+        bool "Energy Micro efm32"
+        depends on !MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_NVIC
+        # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
+        # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select CPU_V7M
+        select GENERIC_CLOCKEVENTS
+        select NO_DMA
+        select NO_IOPORT
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
+          processors.
+
 config ARCH_EP93XX
         bool "EP93xx-based"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -632,10 +657,10 @@ config ARCH_PXA
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
-config ARCH_MSM
+config ARCH_MSM_NODT
         bool "Qualcomm MSM"
+        select ARCH_MSM
         select ARCH_REQUIRE_GPIOLIB
-        select CLKSRC_OF if OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         help
@@ -645,8 +670,9 @@ config ARCH_MSM
           stack and controls some vital subsystems
           (clock and power control, etc).
 
-config ARCH_SHMOBILE
-        bool "Renesas SH-Mobile / R-Mobile"
+config ARCH_SHMOBILE_LEGACY
+        bool "Renesas ARM SoCs (non-multiplatform)"
+        select ARCH_SHMOBILE
         select ARM_PATCH_PHYS_VIRT
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
@@ -661,7 +687,9 @@ config ARCH_SHMOBILE
         select PM_GENERIC_DOMAINS if PM
         select SPARSE_IRQ
         help
-          Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
+          Support for Renesas ARM SoC platforms using a non-multiplatform
+          kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
+          and RZ families.
 
 config ARCH_RPC
         bool "RiscPC"
@@ -711,7 +739,6 @@ config ARCH_S3C24XX
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select MULTI_IRQ_HANDLER
-        select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         select SAMSUNG_ATAGS
         help
@@ -724,24 +751,23 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
         select ARM_VIC
         select CLKDEV_LOOKUP
         select CLKSRC_SAMSUNG_PWM
         select COMMON_CLK
-        select CPU_V6
+        select CPU_V6K
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_TCM
-        select NEED_MACH_GPIO_H
         select NO_IOPORT
         select PLAT_SAMSUNG
         select PM_GENERIC_DOMAINS
         select S3C_DEV_NAND
         select S3C_GPIO_TRACK
         select SAMSUNG_ATAGS
-        select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_WAKEMASK
         select SAMSUNG_WDT_RESET
         select USB_ARCH_HAS_OHCI
@@ -912,6 +938,8 @@ source "arch/arm/mach-bcm/Kconfig"
 
 source "arch/arm/mach-bcm2835/Kconfig"
 
+source "arch/arm/mach-berlin/Kconfig"
+
 source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -928,6 +956,8 @@ source "arch/arm/mach-gemini/Kconfig"
 
 source "arch/arm/mach-highbank/Kconfig"
 
+source "arch/arm/mach-hisi/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -946,6 +976,8 @@ source "arch/arm/mach-ks8695/Kconfig"
 
 source "arch/arm/mach-msm/Kconfig"
 
+source "arch/arm/mach-moxart/Kconfig"
+
 source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"
@@ -1054,6 +1086,8 @@ config ARM_TIMER_SP804
         select CLKSRC_MMIO
         select CLKSRC_OF if OF
 
+source "arch/arm/firmware/Kconfig"
+
 source arch/arm/mm/Kconfig
 
 config ARM_NR_BANKS
@@ -1436,14 +1470,14 @@ config SMP
         depends on MMU || ARM_MPU
         help
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
-          you say Y here, the kernel will run on many, but not all, single
-          processor machines. On a single processor machine, the kernel will
-          run faster if you say N here.
+          you say Y here, the kernel will run on many, but not all,
+          uniprocessor machines. On a uniprocessor machine, the kernel
+          will run faster if you say N here.
 
           See also <file:Documentation/x86/i386/IO-APIC.txt>,
           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
@@ -1594,7 +1628,7 @@ config ARM_PSCI
 config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
+        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
         default 392 if ARCH_U8500
         default 352 if ARCH_VT8500
         default 288 if ARCH_SUNXI
@@ -1612,7 +1646,7 @@ config HZ_FIXED
         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
                 ARCH_S5PV210 || ARCH_EXYNOS4
         default AT91_TIMER_HZ if ARCH_AT91
-        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
+        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
         default 0
 
 choice
@@ -1652,9 +1686,6 @@ config HZ
 config SCHED_HRTICK
         def_bool HIGH_RES_TIMERS
 
-config SCHED_HRTICK
-        def_bool HIGH_RES_TIMERS
-
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
@@ -1797,10 +1828,10 @@ config ARCH_WANT_GENERAL_HUGETLB
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
-        int "Maximum zone order" if ARCH_SHMOBILE
-        range 11 64 if ARCH_SHMOBILE
+        int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
+        range 11 64 if ARCH_SHMOBILE_LEGACY
         default "12" if SOC_AM33XX
-        default "9" if SA1111
+        default "9" if SA1111 || ARCH_EFM32
         default "11"
         help
           The kernel memory allocator divides physically contiguous memory
@@ -1874,6 +1905,7 @@ config XEN
         depends on !GENERIC_ATOMIC64
         select ARM_PSCI
         select SWIOTLB_XEN
+        select ARCH_DMA_ADDR_T_64BIT
         help
           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
@@ -1935,6 +1967,7 @@ config ZBOOT_ROM_BSS
 config ZBOOT_ROM
         bool "Compressed boot loader in ROM/flash"
         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
+        depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
         help
           Say Y here if you intend to execute your compressed kernel image
           (zImage) directly from ROM or flash.  If unsure, say N.
@@ -1970,7 +2003,7 @@ endchoice
 
 config ARM_APPENDED_DTB
         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
-        depends on OF && !ZBOOT_ROM
+        depends on OF
         help
           With this option, the boot code will look for a device tree binary
           (DTB) appended to zImage
@@ -2058,7 +2091,7 @@ endchoice
 
 config XIP_KERNEL
         bool "Kernel Execute-In-Place from ROM"
-        depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
+        depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
         help
           Execute-In-Place allows the kernel to run from non-volatile storage
           directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2121,7 +2154,6 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
         bool "Auto calculation of the decompressed kernel image address"
-        depends on !ZBOOT_ROM
         help
           ZRELADDR is the physical address where the decompressed kernel
           image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5765abf5ce84..0531da8e5216 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,6 +2,18 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config ARM_PTDUMP
+        bool "Export kernel pagetable layout to userspace via debugfs"
+        depends on DEBUG_KERNEL
+        select DEBUG_FS
+        ---help---
+          Say Y here if you want to show the kernel pagetable layout in a
+          debugfs file. This information is only useful for kernel developers
+          who are working in architecture specific areas of the kernel.
+          It is probably not a good idea to enable this feature in a production
+          kernel.
+          If in doubt, say "N"
+
 config STRICT_DEVMEM
         bool "Filter access to /dev/mem"
         depends on MMU
@@ -94,6 +106,25 @@ choice
                 depends on ARCH_BCM2835
                 select DEBUG_UART_PL01X
 
+        config DEBUG_BCM_KONA_UART
+                bool "Kernel low-level debugging messages via BCM KONA UART"
+                depends on ARCH_BCM
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Broadcom SoC platforms.
+                  This low level debug works for Broadcom
+                  mobile SoCs in the Kona family of chips (e.g. bcm28155,
+                  bcm11351, etc...)
+
+        config DEBUG_BERLIN_UART
+                bool "Marvell Berlin SoC Debug UART"
+                depends on ARCH_BERLIN
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Marvell Berlin SoC based platforms.
+
         config DEBUG_CLPS711X_UART1
                 bool "Kernel low-level debugging messages via UART1"
                 depends on ARCH_CLPS711X
@@ -255,6 +286,13 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX35.
 
+        config DEBUG_IMX50_UART
+                bool "i.MX50 Debug UART"
+                depends on SOC_IMX50
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX50.
+
         config DEBUG_IMX51_UART
                 bool "i.MX51 Debug UART"
                 depends on SOC_IMX51
@@ -897,6 +935,7 @@ config DEBUG_IMX_UART_PORT
                                                 DEBUG_IMX21_IMX27_UART || \
                                                 DEBUG_IMX31_UART || \
                                                 DEBUG_IMX35_UART || \
+                                                DEBUG_IMX50_UART || \
                                                 DEBUG_IMX51_UART || \
                                                 DEBUG_IMX53_UART || \
                                                 DEBUG_IMX6Q_UART || \
@@ -931,6 +970,7 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX21_IMX27_UART || \
                                  DEBUG_IMX31_UART || \
                                  DEBUG_IMX35_UART || \
+                                 DEBUG_IMX50_UART || \
                                  DEBUG_IMX51_UART || \
                                  DEBUG_IMX53_UART ||\
                                  DEBUG_IMX6Q_UART || \
@@ -988,6 +1028,7 @@ config DEBUG_UART_PHYS
         default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
         default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
         default 0x20201000 if DEBUG_BCM2835
+        default 0x3e000000 if DEBUG_BCM_KONA_UART
         default 0x4000e400 if DEBUG_LL_UART_EFM32
         default 0x40090000 if ARCH_LPC32XX
         default 0x40100000 if DEBUG_PXA_UART1
@@ -1011,6 +1052,7 @@ config DEBUG_UART_PHYS
         default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
         default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
                                 ARCH_ORION5X
+        default 0xf7fc9000 if DEBUG_BERLIN_UART
         default 0xf8b00000 if DEBUG_HI3716_UART
         default 0xfcb00000 if DEBUG_HI3620_UART
         default 0xfe800000 if ARCH_IOP32X
@@ -1036,6 +1078,7 @@ config DEBUG_UART_VIRT
         default 0xf2100000 if DEBUG_PXA_UART1
         default 0xf4090000 if ARCH_LPC32XX
         default 0xf4200000 if ARCH_GEMINI
+        default 0xf7fc9000 if DEBUG_BERLIN_UART
         default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
         default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
         default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
@@ -1049,6 +1092,7 @@ config DEBUG_UART_VIRT
         default 0xfe018000 if DEBUG_MMP_UART3
         default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
         default 0xfe230000 if DEBUG_PICOXCELL_UART
+        default 0xfe300000 if DEBUG_BCM_KONA_UART
         default 0xfe800000 if ARCH_IOP32X
         default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART
         default 0xfeb24000 if DEBUG_RK3X_UART0
@@ -1091,7 +1135,8 @@ config DEBUG_UART_8250_WORD
         default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
                 ARCH_KEYSTONE || \
                 DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
-                DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1
+                DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+                DEBUG_BCM_KONA_UART
 
 config DEBUG_UART_8250_FLOW_CONTROL
         bool "Enable flow control for 8250 UART"
@@ -1150,4 +1195,15 @@ config PID_IN_CONTEXTIDR
           additional instructions during context switch. Say Y here only if you
           are planning to use hardware trace tools with this kernel.
 
+config DEBUG_SET_MODULE_RONX
+        bool "Set loadable kernel module data as NX and text as RO"
+        depends on MODULES
+        ---help---
+          This option helps catch unintended modifications to loadable
+          kernel module's text and read-only data. It also prevents execution
+          of module data. Such protection may interfere with run-time code
+          patching and dynamic kernel tracing - and they might also protect
+          against certain classes of kernel exploits.
+          If in doubt, say "N".
+
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 55b4255ad6ed..08a9ef58d9c3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -96,7 +96,7 @@ tune-$(CONFIG_CPU_V6K)		=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
 tune-y := $(tune-y)
 
 ifeq ($(CONFIG_AEABI),y)
-CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork
+CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp
 else
 CFLAGS_ABI      :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
 endif
@@ -144,15 +144,18 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 machine-$(CONFIG_ARCH_AT91)             += at91
 machine-$(CONFIG_ARCH_BCM)              += bcm
 machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
+machine-$(CONFIG_ARCH_BERLIN)           += berlin
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
 machine-$(CONFIG_ARCH_DAVINCI)          += davinci
 machine-$(CONFIG_ARCH_DOVE)             += dove
 machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
+machine-$(CONFIG_ARCH_EFM32)            += efm32
 machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
 machine-$(CONFIG_ARCH_EXYNOS)           += exynos
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
+machine-$(CONFIG_ARCH_HI3xxx)           += hisi
 machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
 machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
 machine-$(CONFIG_ARCH_IOP32X)           += iop32x
@@ -163,6 +166,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD)		+= kirkwood
 machine-$(CONFIG_ARCH_KS8695)           += ks8695
 machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
 machine-$(CONFIG_ARCH_MMP)              += mmp
+machine-$(CONFIG_ARCH_MOXART)           += moxart
 machine-$(CONFIG_ARCH_MSM)              += msm
 machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)            += mvebu
@@ -186,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100)		+= s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          += s5pv210
 machine-$(CONFIG_ARCH_SA1100)           += sa1100
 machine-$(CONFIG_ARCH_SHMOBILE)         += shmobile
-machine-$(CONFIG_ARCH_SHMOBILE_MULTI)   += shmobile
 machine-$(CONFIG_ARCH_SIRF)             += prima2
 machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
 machine-$(CONFIG_ARCH_STI)              += sti
@@ -264,6 +267,7 @@ core-$(CONFIG_KVM_ARM_HOST) 	+= arch/arm/kvm/
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 core-y                          += arch/arm/net/
 core-y                          += arch/arm/crypto/
+core-y                          += arch/arm/firmware/
 core-y                          += $(machdirs) $(platdirs)
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index e7190bb5998e..68c918362b79 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -64,7 +64,7 @@ else
 endif
 endif
 
-ifeq ($(CONFIG_ARCH_SHMOBILE),y)
+ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
 OBJS            += head-shmobile.o
 endif
 
@@ -108,12 +108,12 @@ endif
 
 targets       := vmlinux vmlinux.lds \
                  piggy.$(suffix_y) piggy.$(suffix_y).o \
-                 lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S \
-                 font.o font.c head.o misc.o $(OBJS)
+                 lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S bswapsdi2.o \
+                 bswapsdi2.S font.o font.c head.o misc.o $(OBJS)
 
 # Make sure files are removed during clean
 extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern piggy.lz4 \
-                 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \
+                 lib1funcs.S ashldi3.S bswapsdi2.S $(libfdt) $(libfdt_hdrs) \
                  hyp-stub.S
 
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
@@ -156,6 +156,12 @@ ashldi3 = $(obj)/ashldi3.o
 $(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S
         $(call cmd,shipped)
 
+# For __bswapsi2, __bswapdi2
+bswapsdi2 = $(obj)/bswapsdi2.o
+
+$(obj)/bswapsdi2.S: $(srctree)/arch/$(SRCARCH)/lib/bswapsdi2.S
+        $(call cmd,shipped)
+
 # We need to prevent any GOTOFF relocs being used with references
 # to symbols in the .bss section since we cannot relocate them
 # independently from the rest at run time.  This can be achieved by
@@ -177,7 +183,8 @@ if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \
 fi
 
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
-                $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) FORCE
+                $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \
+                $(bswapsdi2) FORCE
         @$(check_for_multiple_zreladdr)
         $(call if_changed,ld)
         @$(check_for_bad_syms)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a65b24f..b9d6a8b485e0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb
 # sam9260
 dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91-qil_a9260.dtb
 dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
 dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
 dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
@@ -30,6 +31,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
 # sam9x5
 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
+dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
@@ -40,11 +42,16 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d31ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
+
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
         bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+        berlin2-sony-nsz-gs7.dtb        \
+        berlin2cd-google-chromecast.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
         da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
@@ -52,6 +59,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
         dove-d2plug.dtb \
         dove-d3plug.dtb \
         dove-dove-db.dtb
+dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
@@ -59,13 +67,16 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4412-odroidx.dtb \
         exynos4412-origen.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-tiny4412.dtb \
         exynos4412-trats2.dtb \
         exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
+        exynos5420-arndale-octa.dtb \
         exynos5420-smdk5420.dtb \
         exynos5440-sd5v1.dtb \
         exynos5440-ssdk5440.dtb
+dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
         ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@@ -85,11 +96,13 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-iomega_ix2_200.dtb \
         kirkwood-is2.dtb \
         kirkwood-km_kirkwood.dtb \
+        kirkwood-laplug.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-mplcec4.dtb \
         kirkwood-mv88f6281gtw-ge.dtb \
         kirkwood-netgear_readynas_duo_v2.dtb \
+        kirkwood-netgear_readynas_nv+_v2.dtb \
         kirkwood-ns2.dtb \
         kirkwood-ns2lite.dtb \
         kirkwood-ns2max.dtb \
@@ -104,8 +117,10 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-ts219-6281.dtb \
         kirkwood-ts219-6282.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
+dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
-        qcom-msm8960-cdp.dtb
+        qcom-msm8960-cdp.dtb \
+        qcom-apq8074-dragonboard.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-370-mirabox.dtb \
         armada-370-netgear-rn102.dtb \
@@ -114,6 +129,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
         armada-xp-gp.dtb \
+        armada-xp-netgear-rn2120.dtb \
         armada-xp-matrix.dtb \
         armada-xp-openblocks-ax3-4.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
@@ -136,10 +152,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx53-mba53.dtb \
         imx53-qsb.dtb \
         imx53-smd.dtb \
+        imx6dl-cubox-i.dtb \
+        imx6dl-hummingboard.dtb \
         imx6dl-sabreauto.dtb \
         imx6dl-sabresd.dtb \
         imx6dl-wandboard.dtb \
         imx6q-arm2.dtb \
+        imx6q-cubox-i.dtb \
         imx6q-phytec-pbab01.dtb \
         imx6q-sabreauto.dtb \
         imx6q-sabrelite.dtb \
@@ -173,12 +192,19 @@ dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
         nspire-tp.dtb \
         nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+        omap2430-sdp.dtb \
+        omap2420-n800.dtb \
+        omap2420-n810.dtb \
+        omap2420-n810-wimax.dtb \
         omap3430-sdp.dtb \
         omap3-beagle.dtb \
+        omap3-cm-t3730.dtb \
+        omap3-sbc-t3730.dtb \
         omap3-devkit8000.dtb \
         omap3-beagle-xm.dtb \
         omap3-evm.dtb \
         omap3-evm-37xx.dtb \
+        omap3-ldp.dtb \
         omap3-n900.dtb \
         omap3-n9.dtb \
         omap3-n950.dtb \
@@ -216,8 +242,9 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
 dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
         s3c6410-smdk6410.dtb
-dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
+dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
         r7s72100-genmai.dtb \
+        r7s72100-genmai-reference.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
         r8a7778-bockw-reference.dtb \
@@ -226,13 +253,15 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a7779-marzen-reference.dtb \
         r8a7791-koelsch.dtb \
         r8a7790-lager.dtb \
-        r8a7790-lager-reference.dtb \
         sh73a0-kzm9g.dtb \
         sh73a0-kzm9g-reference.dtb \
         r8a73a4-ape6evm.dtb \
         r8a73a4-ape6evm-reference.dtb \
         sh7372-mackerel.dtb
-dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb
+dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
+        r7s72100-genmai-reference.dtb \
+        r8a7791-koelsch.dtb \
+        r8a7790-lager.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_sockit.dtb \
@@ -255,6 +284,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
         sun4i-a10-hackberry.dtb \
         sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a13-olinuxino.dtb \
+        sun5i-a13-olinuxino-micro.dtb \
         sun6i-a31-colombus.dtb \
         sun7i-a20-cubieboard2.dtb \
         sun7i-a20-cubietruck.dtb \
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 000000000000..9ccfe508dea2
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,664 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        rng_fck: rng_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm0_tbclk: ehrpwm0_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm0_gate_tbclk>;
+        };
+
+        ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm1_tbclk: ehrpwm1_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm1_gate_tbclk>;
+        };
+
+        ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm2_tbclk: ehrpwm2_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm2_gate_tbclk>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0490>, <0x045c>, <0x0468>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0480>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0484>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x04d8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0488>, <0x0420>, <0x042c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0494>, <0x0434>, <0x0440>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0498>, <0x0448>, <0x0454>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a4>;
+                ti,index-starts-at-one;
+                ti,set-rate-parent;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x048c>, <0x0470>, <0x049c>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x04ac>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        cefuse_fck: cefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0a20>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x014c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+                reg = <0x0530>;
+        };
+
+        mmu_fck: mmu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0914>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+                reg = <0x0528>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0508>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x050c>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0510>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0518>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x051c>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0504>;
+        };
+
+        usbotg_fck: usbotg_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x047c>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ieee5000_fck: ieee5000_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x00e4>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x0538>;
+        };
+
+        l4_rtc_gclk: l4_rtc_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4fw_gclk: l4fw_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sysclk_div_ck: sysclk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+                reg = <0x0520>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+                reg = <0x053c>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0408>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00ac>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b0>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b4>;
+        };
+
+        lcd_gclk: lcd_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x0534>;
+                ti,set-rate-parent;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x052c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x052c>;
+                ti,max-div = <2>;
+        };
+
+        sysclkout_pre_ck: sysclkout_pre_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+                reg = <0x0700>;
+        };
+
+        clkout2_div_ck: clkout2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sysclkout_pre_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <8>;
+                reg = <0x0700>;
+        };
+
+        dbg_sysclk_ck: dbg_sysclk_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0414>;
+        };
+
+        dbg_clka_ck: dbg_clka_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <30>;
+                reg = <0x0414>;
+        };
+
+        stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0414>;
+        };
+
+        trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0414>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&stm_pmd_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&trace_pmd_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        clkout2_ck: clkout2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkout2_div_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0700>;
+        };
+};
+
+&prcm_clockdomains {
+        clk_24mhz_clkdm: clk_24mhz_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&clkdiv32k_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f6d8ffe98d0b..6d95d3df33c7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,6 +102,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44e00000 {
+                        compatible = "ti,am3-prcm";
+                        reg = <0x44e00000 0x4000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am3-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 intc: interrupt-controller@48200000 {
                         compatible = "ti,omap2-intc";
                         interrupt-controller;
@@ -794,3 +820,5 @@
                 };
         };
 };
+
+/include/ "am33xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 03fcbf0a88a8..b4127c6493a2 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -17,6 +17,21 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        vmmc_fixed: vmmc {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmc_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&davinci_emac {
+             status = "okay";
+};
+
+&davinci_mdio {
+             status = "okay";
 };
 
 &i2c1 {
@@ -30,3 +45,17 @@
 &i2c3 {
         clock-frequency = <400000>;
 };
+
+&mmc1 {
+        vmmc-supply = <&vmmc_fixed>;
+        bus-width = <4>;
+};
+
+&mmc2 {
+      status = "disabled";
+};
+
+&mmc3 {
+      status = "disabled";
+};
+
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 2fbe02faa8b1..788391f91684 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -61,3 +61,6 @@
                 };
         };
 };
+
+/include/ "am35xx-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 000000000000..df489d310b50
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,128 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        emac_ick: emac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <1>;
+        };
+
+        emac_fck: emac_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&rmii_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <9>;
+        };
+
+        vpfe_ick: vpfe_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <2>;
+        };
+
+        vpfe_fck: vpfe_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pclk_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <10>;
+        };
+
+        hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <0>;
+        };
+
+        hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <8>;
+        };
+
+        hecc_ck: hecc_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <3>;
+        };
+};
+&cm_clocks {
+        ipss_ick: ipss_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        rmii_ck: rmii_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <50000000>;
+        };
+
+        pclk_ck: pclk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        uart4_ick_am35xx: uart4_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        uart4_fck_am35xx: uart4_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
+                         <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
+                         <&hecc_ck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
+        };
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103ab3b1..c6bd4d986c29 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44df0000 {
+                        compatible = "ti,am4-prcm";
+                        reg = <0x44df0000 0x11000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am4-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 edma: edma@49000000 {
                         compatible = "ti,edma3";
                         ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
@@ -665,3 +691,5 @@
                 };
         };
 };
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 000000000000..142009cc9332
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d38>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d3c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d40>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2da0>, <0x2da4>, <0x2dac>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e30>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2de0>, <0x2de4>, <0x2dec>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2df0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a38>;
+        };
+
+        sysclk_div: sysclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+                reg = <0x4248>;
+        };
+
+        clk_32k_tpm_ck: clk_32k_tpm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4200>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4204>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4208>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x420c>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4210>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4214>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4218>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x422c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+                reg = <0x4238>;
+        };
+
+        clk_32k_mosc_ck: clk_32k_mosc_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4240>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2b68>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c78>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c80>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c88>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c90>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c98>;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x423c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x423c>;
+                ti,max-div = <2>;
+        };
+
+        disp_clk: disp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x4244>;
+        };
+
+        dpll_extdev_ck: dpll_extdev_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+        };
+
+        dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_extdev_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mux_synctimer32k_ck: mux_synctimer32k_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+                reg = <0x4230>;
+        };
+
+        synctimer_32kclk: synctimer_32kclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&mux_synctimer32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a30>;
+        };
+
+        timer8_fck: timer8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x421c>;
+        };
+
+        timer9_fck: timer9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4220>;
+        };
+
+        timer10_fck: timer10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4224>;
+        };
+
+        timer11_fck: timer11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4228>;
+        };
+
+        cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cpsw_50m_clkdiv>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dll_aging_clk_div: dll_aging_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x4250>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        div_core_25m_ck: div_core_25m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_12m_clk: func_12m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        vtp_clk_div: vtp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4260>;
+        };
+};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9eb5111..3c4f6d983cbd 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -90,34 +90,19 @@
                         nand-on-flash-bbt;
                         status = "okay";
 
-                        at91bootstrap@0 {
-                                label = "at91bootstrap";
-                                reg = <0x0 0x8000>;
-                        };
-
-                        barebox@8000 {
+                        barebox@0 {
                                 label = "barebox";
-                                reg = <0x8000 0x40000>;
-                        };
-
-                        bareboxenv@48000 {
-                                label = "bareboxenv";
-                                reg = <0x48000 0x8000>;
-                        };
-
-                        user_block@0x50000 {
-                                label = "user_block";
-                                reg = <0x50000 0xb0000>;
+                                reg = <0x0 0x58000>;
                         };
 
-                        kernel@100000 {
-                                label = "kernel";
-                                reg = <0x100000 0x1b0000>;
+                        u_boot_env@58000 {
+                                label = "u_boot_env";
+                                reg = <0x58000 0x8000>;
                         };
 
-                        root@2b0000 {
-                                label = "root";
-                                reg = <0x2b0000 0x1D50000>;
+                        ubi@60000 {
+                                label = "ubi";
+                                reg = <0x60000 0x1FA0000>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2471d9da767b..944e8785b308 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -74,13 +74,13 @@
                                 green_pwr_led {
                                         label = "mirabox:green:pwr";
                                         gpios = <&gpio1 31 1>;
-                                        linux,default-trigger = "heartbeat";
+                                        default-state = "keep";
                                 };
 
                                 blue_stat_led {
                                         label = "mirabox:blue:stat";
                                         gpios = <&gpio2 0 1>;
-                                        linux,default-trigger = "cpu0";
+                                        default-state = "off";
                                 };
 
                                 green_stat_led {
@@ -139,6 +139,27 @@
                                         reg = <0x25>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x400000>;
+                                };
+                                partition@400000 {
+                                        label = "Linux";
+                                        reg = <0x400000 0x400000>;
+                                };
+                                partition@800000 {
+                                        label = "Filesystem";
+                                        reg = <0x800000 0x3f800000>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 8ac2ac1f69cc..651aeb5ef439 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 
 / {
@@ -62,6 +64,7 @@
                                         marvell,pins = "mpp57";
                                         marvell,function = "gpio";
                                 };
+
                                 sata1_led_pin: sata1-led-pin {
                                         marvell,pins = "mpp15";
                                         marvell,function = "gpio";
@@ -77,6 +80,21 @@
                                         marvell,function = "gpio";
                                 };
 
+                                backup_button_pin: backup-button-pin {
+                                        marvell,pins = "mpp58";
+                                        marvell,function = "gpio";
+                                };
+
+                                power_button_pin: power-button-pin {
+                                        marvell,pins = "mpp62";
+                                        marvell,function = "gpio";
+                                };
+
+                                reset_button_pin: reset-button-pin {
+                                        marvell,pins = "mpp6";
+                                        marvell,function = "gpio";
+                                };
+
                                 poweroff: poweroff {
                                         marvell,pins = "mpp8";
                                         marvell,function = "gpio";
@@ -84,7 +102,7 @@
                         };
 
                         mdio {
-                                phy0: ethernet-phy@0 {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
                         };
@@ -104,6 +122,11 @@
                                 clock-frequency = <100000>;
                                 status = "okay";
 
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
                                 g762: g762@3e {
                                         compatible = "gmt,g762";
                                         reg = <0x3e>;
@@ -113,82 +136,116 @@
                                         pwm_polarity = <0>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
+                        };
                 };
         };
 
         clocks {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               g762_clk: fixedclk {
+               g762_clk: g762-oscillator {
                          compatible = "fixed-clock";
                          #clock-cells = <0>;
                          clock-frequency = <8192>;
                };
         };
 
-        gpio_leds {
+        gpio-leds {
                 compatible = "gpio-leds";
-                pinctrl-0 = < &power_led_pin
-                              &sata1_led_pin
-                              &sata2_led_pin
-                              &backup_led_pin >;
+                pinctrl-0 = <&power_led_pin
+                             &sata1_led_pin
+                             &sata2_led_pin
+                             &backup_led_pin>;
                 pinctrl-names = "default";
 
-                blue_power_led {
+                blue-power-led {
                         label = "rn102:blue:pwr";
-                        gpios = <&gpio1 25 1>;  /* GPIO 57 Active Low */
-                        linux,default-trigger = "heartbeat";
+                        gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
-                green_sata1_led {
+                green-sata1-led {
                         label = "rn102:green:sata1";
-                        gpios = <&gpio0 15 1>;  /* GPIO 15 Active Low */
+                        gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green_sata2_led {
+                green-sata2-led {
                         label = "rn102:green:sata2";
-                        gpios = <&gpio0 14 1>;   /* GPIO 14 Active Low */
+                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green_backup_led {
+                green-backup-led {
                         label = "rn102:green:backup";
-                        gpios = <&gpio1 24 1>;   /* GPIO 56 Active Low */
+                        gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
+                pinctrl-0 = <&power_button_pin
+                             &reset_button_pin
+                             &backup_button_pin>;
+                pinctrl-names = "default";
 
-                button@1 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 30 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
                 };
 
-                button@2 {
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio0 6 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
                 };
 
-                button@3 {
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 26 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_poweroff {
+        gpio-poweroff {
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&poweroff>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 8 1>;
+                gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
         };
-
 };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index b0b32f5fbeb4..4e27587667bf 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 
 / {
@@ -58,12 +60,12 @@
                                         marvell,function = "gpio";
                                 };
 
-                                backup_key_pin: backup-key-pin {
+                                backup_button_pin: backup-button-pin {
                                         marvell,pins = "mpp52";
                                         marvell,function = "gpio";
                                 };
 
-                                power_key_pin: power-key-pin {
+                                power_button_pin: power-button-pin {
                                         marvell,pins = "mpp62";
                                         marvell,function = "gpio";
                                 };
@@ -78,18 +80,18 @@
                                         marvell,function = "gpio";
                                 };
 
-                                reset_key_pin: reset-key-pin {
+                                reset_button_pin: reset-button-pin {
                                         marvell,pins = "mpp65";
                                         marvell,function = "gpio";
                                 };
                         };
 
                         mdio {
-                                phy0: ethernet-phy@0 {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
                                         reg = <0>;
                                 };
 
-                                phy1: ethernet-phy@1 {
+                                phy1: ethernet-phy@1 { /* Marvell 88E1318 */
                                         reg = <1>;
                                 };
                         };
@@ -115,6 +117,11 @@
                                 clock-frequency = <100000>;
                                 status = "okay";
 
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
                                 g762: g762@3e {
                                         compatible = "gmt,g762";
                                         reg = <0x3e>;
@@ -123,71 +130,133 @@
                                         fan_startv = <1>;
                                         pwm_polarity = <0>;
                                 };
+
+                                pca9554: pca9554@23 {
+                                        compatible = "nxp,pca9554";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0x23>;
+                                };
+                        };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
                         };
                 };
         };
 
         clocks {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               g762_clk: fixedclk {
+               g762_clk: g762-oscillator {
                          compatible = "fixed-clock";
                          #clock-cells = <0>;
                          clock-frequency = <8192>;
                };
         };
 
-        gpio_leds {
+        gpio-leds {
                 compatible = "gpio-leds";
                 pinctrl-0 = <&backup_led_pin &power_led_pin>;
                 pinctrl-names = "default";
 
-                blue_backup_led {
+                blue-backup-led {
                         label = "rn104:blue:backup";
-                        gpios = <&gpio1 31 0>;   /* GPIO 63 Active High */
+                        gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
-                blue_power_led {
+                blue-power-led {
                         label = "rn104:blue:pwr";
-                        gpios = <&gpio2 0 1>;    /* GPIO 64 Active Low */
+                        gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "keep";
                 };
+
+                blue-sata1-led {
+                        label = "rn104:blue:sata1";
+                        gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata2-led {
+                        label = "rn104:blue:sata2";
+                        gpios = <&pca9554 1 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata3-led {
+                        label = "rn104:blue:sata3";
+                        gpios = <&pca9554 2 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                blue-sata4-led {
+                        label = "rn104:blue:sata4";
+                        gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-0 = <&backup_key_pin
-                             &power_key_pin
-                             &reset_key_pin>;
+                pinctrl-0 = <&backup_button_pin
+                             &power_button_pin
+                             &reset_button_pin>;
                 pinctrl-names = "default";
 
-                button@1 {
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 20 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
                 };
 
-                button@2 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 30 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
                 };
 
-                button@3 {
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio2 1 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_poweroff {
+        gpio-poweroff {
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&poweroff>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 28 1>;
+                gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index f81810a59629..abbb807459d2 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -104,6 +104,27 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 7f10f627ae5b..74b5964430ac 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -103,22 +103,52 @@
                         #size-cells = <1>;
                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 
-                        mbusc: mbus-controller@20000 {
-                                compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        rtc@10300 {
+                                compatible = "marvell,orion-rtc";
+                                reg = <0x10300 0x20>;
+                                interrupts = <50>;
                         };
 
-                        mpic: interrupt-controller@20000 {
-                                compatible = "marvell,mpic";
-                                #interrupt-cells = <1>;
-                                #size-cells = <1>;
-                                interrupt-controller;
-                                msi-controller;
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x28>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <30>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
                         };
 
-                        coherency-fabric@20200 {
-                                compatible = "marvell,coherency-fabric";
-                                reg = <0x20200 0xb0>, <0x21010 0x1c>;
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x28>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <92>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <31>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <32>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
                         };
 
                         serial@12000 {
@@ -146,25 +176,41 @@
                                 clock-output-names = "nand";
                         };
 
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        mpic: interrupt-controller@20000 {
+                                compatible = "marvell,mpic";
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                        };
+
+                        coherency-fabric@20200 {
+                                compatible = "marvell,coherency-fabric";
+                                reg = <0x20200 0xb0>, <0x21010 0x1c>;
+                        };
+
                         timer@20300 {
                                 reg = <0x20300 0x30>, <0x21040 0x30>;
                                 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
                         };
 
-                        sata@a0000 {
-                                compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x5000>;
-                                interrupts = <55>;
-                                clocks = <&gateclk 15>, <&gateclk 30>;
-                                clock-names = "0", "1";
+                        usb@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x50000 0x500>;
+                                interrupts = <45>;
                                 status = "disabled";
                         };
 
-                        mdio {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "marvell,orion-mdio";
-                                reg = <0x72004 0x4>;
+                        usb@51000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x51000 0x500>;
+                                interrupts = <46>;
+                                status = "disabled";
                         };
 
                         eth0: ethernet@70000 {
@@ -175,6 +221,13 @@
                                 status = "disabled";
                         };
 
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "marvell,orion-mdio";
+                                reg = <0x72004 0x4>;
+                        };
+
                         eth1: ethernet@74000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x74000 0x4000>;
@@ -183,32 +236,25 @@
                                 status = "disabled";
                         };
 
-                        i2c0: i2c@11000 {
-                                compatible = "marvell,mv64xxx-i2c";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <31>;
-                                timeout-ms = <1000>;
-                                clocks = <&coreclk 0>;
+                        sata@a0000 {
+                                compatible = "marvell,armada-370-sata";
+                                reg = <0xa0000 0x5000>;
+                                interrupts = <55>;
+                                clocks = <&gateclk 15>, <&gateclk 30>;
+                                clock-names = "0", "1";
                                 status = "disabled";
                         };
 
-                        i2c1: i2c@11100 {
-                                compatible = "marvell,mv64xxx-i2c";
+                        nand@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
                                 #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <32>;
-                                timeout-ms = <1000>;
-                                clocks = <&coreclk 0>;
+                                #size-cells = <1>;
+                                interrupts = <113>;
+                                clocks = <&coredivclk 0>;
                                 status = "disabled";
                         };
 
-                        rtc@10300 {
-                                compatible = "marvell,orion-rtc";
-                                reg = <0x10300 0x20>;
-                                interrupts = <50>;
-                        };
-
                         mvsdio@d4000 {
                                 compatible = "marvell,orion-sdio";
                                 reg = <0xd4000 0x200>;
@@ -220,43 +266,6 @@
                                 cap-mmc-highspeed;
                                 status = "disabled";
                         };
-
-                        usb@50000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x50000 0x500>;
-                                interrupts = <45>;
-                                status = "disabled";
-                        };
-
-                        usb@51000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x51000 0x500>;
-                                interrupts = <46>;
-                                status = "disabled";
-                        };
-
-                        spi0: spi@10600 {
-                                compatible = "marvell,orion-spi";
-                                reg = <0x10600 0x28>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                interrupts = <30>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        spi1: spi@10680 {
-                                compatible = "marvell,orion-spi";
-                                reg = <0x10680 0x28>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <1>;
-                                interrupts = <92>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
                 };
         };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 7a4b82e71aaf..0d8530c98cf5 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -91,11 +91,6 @@
                 };
 
                 internal-regs {
-                        system-controller@18200 {
-                                compatible = "marvell,armada-370-xp-system-controller";
-                                reg = <0x18200 0x100>;
-                        };
-
                         L2: l2-cache {
                                 compatible = "marvell,aurora-outer-cache";
                                 reg = <0x08000 0x1000>;
@@ -103,8 +98,17 @@
                                 wt-override;
                         };
 
-                        interrupt-controller@20000 {
-                                reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+                        i2c0: i2c@11000 {
+                                reg = <0x11000 0x20>;
+                        };
+
+                        i2c1: i2c@11100 {
+                                reg = <0x11100 0x20>;
+                        };
+
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
                         };
 
                         pinctrl {
@@ -163,9 +167,11 @@
                                 interrupts = <91>;
                         };
 
-                        timer@20300 {
-                                compatible = "marvell,armada-370-timer";
-                                clocks = <&coreclk 2>;
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-370-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
                         };
 
                         coreclk: mvebu-sar@18230 {
@@ -174,11 +180,28 @@
                                 #clock-cells = <1>;
                         };
 
-                        gateclk: clock-gating-control@18220 {
-                                compatible = "marvell,armada-370-gating-clock";
-                                reg = <0x18220 0x4>;
+                        thermal@18300 {
+                                compatible = "marvell,armada370-thermal";
+                                reg = <0x18300 0x4
+                                        0x18304 0x4>;
+                                status = "okay";
+                        };
+
+                        interrupt-controller@20000 {
+                                reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+                        };
+
+                        timer@20300 {
+                                compatible = "marvell,armada-370-timer";
+                                clocks = <&coreclk 2>;
+                        };
+
+                        usb@50000 {
+                                clocks = <&coreclk 0>;
+                        };
+
+                        usb@51000 {
                                 clocks = <&coreclk 0>;
-                                #clock-cells = <1>;
                         };
 
                         xor@60800 {
@@ -218,29 +241,6 @@
                                         dmacap,memset;
                                 };
                         };
-
-                        i2c0: i2c@11000 {
-                                reg = <0x11000 0x20>;
-                        };
-
-                        i2c1: i2c@11100 {
-                                reg = <0x11100 0x20>;
-                        };
-
-                        usb@50000 {
-                                clocks = <&coreclk 0>;
-                        };
-
-                        usb@51000 {
-                                clocks = <&coreclk 0>;
-                        };
-
-                        thermal@18300 {
-                                compatible = "marvell,armada370-thermal";
-                                reg = <0x18300 0x4
-                                        0x18304 0x4>;
-                                status = "okay";
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 2298e4a910e2..274e2ad5f51c 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -175,6 +175,14 @@
                                         spi-max-frequency = <108000000>;
                                 };
                         };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
new file mode 100644
index 000000000000..ff049ee862eb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -0,0 +1,327 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS 2120
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS 2120";
+        compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x00000000 0 0x80000000>; /* 2GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Connected to first Marvell 88SE9170 SATA controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected to second Marvell 88SE9170 SATA controller */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+
+                        /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+                        pcie@5,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        pinctrl {
+                                poweroff: poweroff {
+                                        marvell,pins = "mpp42";
+                                        marvell,function = "gpio";
+                                };
+
+                                power_button_pin: power-button-pin {
+                                        marvell,pins = "mpp27";
+                                        marvell,function = "gpio";
+                                };
+
+                                reset_button_pin: reset-button-pin {
+                                        marvell,pins = "mpp41";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_led_pin: sata1-led-pin {
+                                        marvell,pins = "mpp31";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_led_pin: sata2-led-pin {
+                                        marvell,pins = "mpp40";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_led_pin: sata3-led-pin {
+                                        marvell,pins = "mpp44";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_led_pin: sata4-led-pin {
+                                        marvell,pins = "mpp47";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_power_pin: sata1-power-pin {
+                                        marvell,pins = "mpp24";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_power_pin: sata2-power-pin {
+                                        marvell,pins = "mpp25";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_power_pin: sata3-power-pin {
+                                        marvell,pins = "mpp26";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_power_pin: sata4-power-pin {
+                                        marvell,pins = "mpp28";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata1_pres_pin: sata1-pres-pin {
+                                        marvell,pins = "mpp32";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_pres_pin: sata2-pres-pin {
+                                        marvell,pins = "mpp33";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata3_pres_pin: sata3-pres-pin {
+                                        marvell,pins = "mpp34";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata4_pres_pin: sata4-pres-pin {
+                                        marvell,pins = "mpp35";
+                                        marvell,function = "gpio";
+                                };
+
+                                err_led_pin: err-led-pin {
+                                        marvell,pins = "mpp45";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
+                        serial@12000 {
+                                clocks = <&coreclk 0>;
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 { /* Marvell 88E1318 */
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        ethernet@74000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        /* Front USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                clock-frequency = <400000>;
+                                status = "okay";
+
+                                isl12057: isl12057@68 {
+                                        compatible = "isl,isl12057";
+                                        reg = <0x68>;
+                                };
+
+                                /* Controller for rear fan #1 of 3 (Protechnic
+                                 * MGT4012XB-O20, 8000RPM) near eSATA port */
+                                g762_fan1: g762@3e {
+                                        compatible = "gmt,g762";
+                                        reg = <0x3e>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /*  Controller for rear (center) fan #2 of 3 */
+                                g762_fan2: g762@48 {
+                                        compatible = "gmt,g762";
+                                        reg = <0x48>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /*  Controller for rear fan #3 of 3 */
+                                g762_fan3: g762@49 {
+                                        compatible = "gmt,g762";
+                                        reg = <0x49>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+
+                                /* Temperature sensor */
+                                g751: g751@4c {
+                                        compatible = "gmt,g751";
+                                        reg = <0x4c>;
+                                };
+                        };
+
+                        nand@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+
+                                partition@0 {
+                                        label = "u-boot";
+                                        reg = <0x0000000 0x180000>;  /* 1.5MB */
+                                        read-only;
+                                };
+
+                                partition@180000 {
+                                        label = "u-boot-env";
+                                        reg = <0x180000 0x20000>;    /* 128KB */
+                                        read-only;
+                                };
+
+                                partition@200000 {
+                                        label = "uImage";
+                                        reg = <0x0200000 0x600000>;    /* 6MB */
+                                };
+
+                                partition@800000 {
+                                        label = "minirootfs";
+                                        reg = <0x0800000 0x400000>;    /* 4MB */
+                                };
+
+                                /* Last MB is for the BBT, i.e. not writable */
+                                partition@c00000 {
+                                        label = "ubifs";
+                                        reg = <0x0c00000 0x7400000>; /* 116MB */
+                                };
+                        };
+                };
+        };
+
+        clocks {
+               g762_clk: g762-oscillator {
+                         compatible = "fixed-clock";
+                         #clock-cells = <0>;
+                         clock-frequency = <32768>;
+               };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin
+                             &sata3_led_pin &sata4_led_pin>;
+                pinctrl-names = "default";
+
+                red-sata1-led {
+                        label = "rn2120:red:sata1";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata2-led {
+                        label = "rn2120:red:sata2";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata3-led {
+                        label = "rn2120:red:sata3";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-sata4-led {
+                        label = "rn2120:red:sata4";
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red-err-led {
+                        label = "rn2120:red:err";
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&power_button_pin &reset_button_pin>;
+                pinctrl-names = "default";
+
+                power-button {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+                };
+
+                reset-button {
+                        label = "Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 5695afcc04bf..99bcf76e6953 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -103,8 +103,7 @@
                                 green_led {
                                         label = "green_led";
                                         gpios = <&gpio1 21 1>;
-                                        default-state = "off";
-                                        linux,default-trigger = "heartbeat";
+                                        default-state = "keep";
                                 };
                         };
 
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 281c6447e872..b8b84a22f0f3 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -42,13 +42,14 @@
                                 wt-override;
                         };
 
-                        interrupt-controller@20000 {
-                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x100>;
                         };
 
-                        armada-370-xp-pmsu@22000 {
-                                compatible = "marvell,armada-370-xp-pmsu";
-                                reg = <0x22100 0x430>, <0x20800 0x20>;
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x100>;
                         };
 
                         serial@12200 {
@@ -68,10 +69,16 @@
                                 status = "disabled";
                         };
 
-                        timer@20300 {
-                                compatible = "marvell,armada-xp-timer";
-                                clocks = <&coreclk 2>, <&refclk>;
-                                clock-names = "nbclk", "fixed";
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x500>;
+                        };
+
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-xp-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
                         };
 
                         coreclk: mvebu-sar@18230 {
@@ -80,6 +87,13 @@
                                 #clock-cells = <1>;
                         };
 
+                        thermal@182b0 {
+                                compatible = "marvell,armadaxp-thermal";
+                                reg = <0x182b0 0x4
+                                        0x184d0 0x4>;
+                                status = "okay";
+                        };
+
                         cpuclk: clock-complex@18700 {
                                 #clock-cells = <1>;
                                 compatible = "marvell,armada-xp-cpu-clock";
@@ -87,16 +101,19 @@
                                 clocks = <&coreclk 1>;
                         };
 
-                        gateclk: clock-gating-control@18220 {
-                                compatible = "marvell,armada-xp-gating-clock";
-                                reg = <0x18220 0x4>;
-                                clocks = <&coreclk 0>;
-                                #clock-cells = <1>;
+                        interrupt-controller@20000 {
+                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
                         };
 
-                        system-controller@18200 {
-                                compatible = "marvell,armada-370-xp-system-controller";
-                                reg = <0x18200 0x500>;
+                        timer@20300 {
+                                compatible = "marvell,armada-xp-timer";
+                                clocks = <&coreclk 2>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
+                        };
+
+                        armada-370-xp-pmsu@22000 {
+                                compatible = "marvell,armada-370-xp-pmsu";
+                                reg = <0x22100 0x400>, <0x20800 0x20>;
                         };
 
                         eth2: ethernet@30000 {
@@ -107,6 +124,22 @@
                                 status = "disabled";
                         };
 
+                        usb@50000 {
+                                clocks = <&gateclk 18>;
+                        };
+
+                        usb@51000 {
+                                clocks = <&gateclk 19>;
+                        };
+
+                        usb@52000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x52000 0x500>;
+                                interrupts = <47>;
+                                clocks = <&gateclk 20>;
+                                status = "disabled";
+                        };
+
                         xor@60900 {
                                 compatible = "marvell,orion-xor";
                                 reg = <0x60900 0x100
@@ -146,39 +179,6 @@
                                         dmacap,memset;
                                 };
                         };
-
-                        i2c0: i2c@11000 {
-                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                                reg = <0x11000 0x100>;
-                        };
-
-                        i2c1: i2c@11100 {
-                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                                reg = <0x11100 0x100>;
-                        };
-
-                        usb@50000 {
-                                clocks = <&gateclk 18>;
-                        };
-
-                        usb@51000 {
-                                clocks = <&gateclk 19>;
-                        };
-
-                        usb@52000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x52000 0x500>;
-                                interrupts = <47>;
-                                clocks = <&gateclk 20>;
-                                status = "disabled";
-                        };
-
-                        thermal@182b0 {
-                                compatible = "marvell,armadaxp-thermal";
-                                reg = <0x182b0 0x4
-                                        0x184d0 0x4>;
-                                status = "okay";
-                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi
new file mode 100644
index 000000000000..5a660d0faf42
--- /dev/null
+++ b/arch/arm/boot/dts/armv7-m.dtsi
@@ -0,0 +1,18 @@
+#include "skeleton.dtsi"
+
+/ {
+        nvic: nv-interrupt-controller  {
+                compatible = "arm,armv7m-nvic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xe000e100 0xc00>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&nvic>;
+                ranges;
+        };
+};
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
new file mode 100644
index 000000000000..2093c4d7cd6a
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -0,0 +1,122 @@
+/*
+ * at91-cosino.dtsi - Device Tree file for Cosino core module
+ *
+ * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
+ *                      HCE Engineering
+ *
+ * Derived from at91sam9x5ek.dtsi by:
+ *      Copyright (C) 2012 Atmel,
+ *      2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "at91sam9g35.dtsi"
+
+/ {
+        model = "HCE Cosino core module";
+        compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
+        };
+
+        memory {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0008000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@f801c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                atmel,adc-clock-rate = <1000000>;
+                                atmel,adc-ts-wires = <4>;
+                                atmel,adc-ts-pressure-threshold = <10000>;
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD15 gpio CD pin pull up and deglitch */
+                                        };
+                                };
+                        };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;        /* Enable PMECC */
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        uboot@40000 {
+                                label = "u-boot";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        ubootenv@c0000 {
+                                label = "U-Boot Env";
+                                reg = <0xc0000 0x140000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
new file mode 100644
index 000000000000..f9415dd11f17
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -0,0 +1,84 @@
+/*
+ * at91-cosino_mega2560.dts - Device Tree file for Cosino board with
+ *                            Mega 2560 extension
+ *
+ * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
+ *                      HCE Engineering
+ *
+ * Derived from at91sam9g35ek.dts by:
+ *      Copyright (C) 2012 Atmel,
+ *      2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+#include "at91-cosino.dtsi"
+
+/ {
+        model = "HCE Cosino Mega 2560";
+        compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                atmel,adc-clock-rate = <1000000>;
+                                atmel,adc-ts-wires = <4>;
+                                atmel,adc-ts-pressure-threshold = <10000>;
+                                status = "okay";
+                        };
+
+
+                        tsadcc: tsadcc@f804c000 {
+                                status = "okay";
+                        };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@f8020000 {
+                                status = "okay";
+                        };
+
+                        usart2: serial@f8024000 {
+                                status = "okay";
+                        };
+
+                        usb2: gadget@f803c000 {
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc1: mmc@f000c000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc1_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc1_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        non-removable;
+                                };
+                        };
+                };
+
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
+                                           &pioD 19 GPIO_ACTIVE_LOW
+                                           &pioD 20 GPIO_ACTIVE_LOW
+                                          >;
+                };
+
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts
new file mode 100644
index 000000000000..5576ae8786c0
--- /dev/null
+++ b/arch/arm/boot/dts/at91-qil_a9260.dts
@@ -0,0 +1,185 @@
+/*
+ * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board
+ *
+ * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9260.dtsi"
+/ {
+        model = "Calao QIL A9260";
+        compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot0_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                };
+                        };
+
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                         &pinctrl_usart0_dtr_dsr
+                                         &pinctrl_usart0_dcd
+                                         &pinctrl_usart0_ri>;
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart1
+                                         &pinctrl_usart1_rts
+                                         &pinctrl_usart1_cts>;
+                                status = "okay";
+                        };
+
+                        usart2: serial@fffb8000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart2
+                                         &pinctrl_usart2_rts
+                                         &pinctrl_usart2_cts>;
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        spi0: spi@fffc8000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>;
+
+                                m41t94@0 {
+                                        compatible = "st,m41t94";
+                                        reg = <0>;
+                                        spi-max-frequency = <1000000>;
+                                };
+
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        oftree@a0000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        kernel@c0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+
+                        rootfs@4c0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+
+                        data@7cc0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index f77065506f1e..c61b16fba79b 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -191,12 +191,12 @@
                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
                                         };
 
-                                        pinctrl_uart0_rts: uart0_rts-0 {
+                                        pinctrl_uart0_cts: uart0_cts-0 {
                                                 atmel,pins =
                                                         <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
                                         };
 
-                                        pinctrl_uart0_cts: uart0_cts-0 {
+                                        pinctrl_uart0_rts: uart0_rts-0 {
                                                 atmel,pins =
                                                         <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                         };
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3b44c4..df6b0aa0e4dd 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -29,10 +29,22 @@
 
         ahb {
                 apb {
-                        dbgu: serial@fffff200 {
+                        usb1: gadget@fffb0000 {
+                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
+                                atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+
+                                phy0: ethernet-phy {
+                                        interrupt-parent = <&pioC>;
+                                        interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+                                };
+                        };
+
                         usart1: serial@fffc4000 {
                                 pinctrl-0 =
                                                 <&pinctrl_uart1
@@ -44,16 +56,6 @@
                                 status = "okay";
                         };
 
-                        macb0: ethernet@fffbc000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-
-                        usb1: gadget@fffb0000 {
-                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
-                                status = "okay";
-                        };
-
                         spi0: spi@fffe0000 {
                                 status = "okay";
                                 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
@@ -63,12 +65,45 @@
                                         reg = <0>;
                                 };
                         };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00300000 {
                         num-ports = <2>;
                         status = "okay";
                 };
+
+                nor_flash@10000000 {
+                        compatible = "cfi-flash";
+                        reg = <0x10000000 0x800000>;
+                        linux,mtd-name = "physmap-flash.0";
+                        bank-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        barebox@0 {
+                                label = "barebox";
+                                reg = <0x00000 0x40000>;
+                        };
+
+                        bareboxenv@40000 {
+                                label = "bareboxenv";
+                                reg = <0x40000 0x10000>;
+                        };
+
+                        kernel@50000 {
+                                label = "kernel";
+                                reg = <0x50000 0x300000>;
+                        };
+
+                        root@350000  {
+                                label = "root";
+                                reg = <0x350000 0x4B0000>;
+                        };
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 56ee8282a7a8..997901f7ed73 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -648,6 +648,11 @@
                         watchdog@fffffd40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffd40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f74602..0042f73068b0 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -30,6 +30,7 @@
                 i2c0 = &i2c0;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -366,6 +367,34 @@
                                         };
                                 };
 
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC1 periph A */
+                                                         AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC2 periph A */
+                                                         AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC3 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB9 periph B */
+                                                         AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 periph A */
+                                                         AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 periph A */
+                                                         AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 periph A */
+                                                         AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 periph A */
+                                                         AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 periph A */
+                                                         AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A */
+                                                         AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A */
+                                                         AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC15 periph A */
+                                                         AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC16 periph A */
+                                                         AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC12 periph B */
+                                                         AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC18 periph A */
+                                                         AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC19 periph A */
+                                                         AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC22 periph A */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC23 periph A */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC24 periph A */
+                                                         AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC17 periph B */
+                                                         AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC26 periph A */
+                                                         AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -523,6 +552,11 @@
                         watchdog@fffffd40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffd40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
                                 status = "disabled";
                         };
 
@@ -547,6 +581,23 @@
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        pwm0: pwm@fffb8000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xfffb8000 0x300>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+                };
+
+                fb0: fb@0x00700000 {
+                        compatible = "atmel,at91sam9263-lcdc";
+                        reg = <0x00700000 0x1000>;
+                        interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        status = "disabled";
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b55c0b..15009c9f2293 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,6 +95,36 @@
                         };
                 };
 
+                fb0: fb@0x00700000 {
+                        display = <&display0>;
+                        status = "okay";
+
+                        display0: display {
+                                bits-per-pixel = <16>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <1>;
+
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <4965000>;
+                                                hactive = <240>;
+                                                vactive = <320>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <33>;
+                                                vback-porch = <1>;
+                                                vfront-porch = <0>;
+                                                hsync-len = <5>;
+                                                vsync-len = <1>;
+                                                hsync-active = <1>;
+                                                vsync-active = <1>;
+                                        };
+                                };
+                        };
+                };
+
                 nand0: nand@40000000 {
                         nand-bus-width = <8>;
                         nand-ecc-mode = "soft";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e514837074..cbcc058b26b4 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -37,6 +37,7 @@
                 i2c1 = &i2c1;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -143,6 +144,22 @@
                                         };
                                 };
 
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA21 periph A TWCK0 */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A TWCK1 */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
+                                        };
+                                };
+
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
@@ -425,6 +442,42 @@
                                         };
                                 };
 
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE0 periph A */
+                                                         AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE2 periph A */
+                                                         AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE3 periph A */
+                                                         AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE4 periph A */
+                                                         AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE5 periph A */
+                                                         AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE6 periph A */
+                                                         AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE7 periph A */
+                                                         AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE8 periph A */
+                                                         AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PE9 periph A */
+                                                         AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE10 periph A */
+                                                         AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE11 periph A */
+                                                         AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE12 periph A */
+                                                         AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE13 periph A */
+                                                         AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE14 periph A */
+                                                         AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE15 periph A */
+                                                         AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE16 periph A */
+                                                         AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE17 periph A */
+                                                         AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE18 periph A */
+                                                         AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE19 periph A */
+                                                         AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE20 periph A */
+                                                         AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE21 periph A */
+                                                         AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE22 periph A */
+                                                         AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE23 periph A */
+                                                         AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE24 periph A */
+                                                         AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE25 periph A */
+                                                         AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE26 periph A */
+                                                         AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE27 periph A */
+                                                         AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE28 periph A */
+                                                         AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE29 periph A */
+                                                         AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -542,6 +595,8 @@
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff84000 0x100>;
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -551,6 +606,8 @@
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff88000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -614,10 +671,19 @@
                                 };
                         };
 
+                        pwm0: pwm@fffb8000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xfffb8000 0x300>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+
                         mmc0: mmc@fff80000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
@@ -629,6 +695,7 @@
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffd0000 0x600>;
                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
                                 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
@@ -639,6 +706,11 @@
                         watchdog@fffffd40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffd40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
                                 status = "disabled";
                         };
 
@@ -727,6 +799,15 @@
                         };
                 };
 
+                fb0: fb@0x00500000 {
+                        compatible = "atmel,at91sam9g45-lcdc";
+                        reg = <0x00500000 0x1000>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        status = "disabled";
+                };
+
                 nand0: nand@40000000 {
                         compatible = "atmel,at91rm9200-nand";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5c61c0..7ff665a8c708 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -105,6 +105,14 @@
                                                          AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD29 gpio WP pin pull up */
                                         };
                                 };
+
+                                pwm0 {
+                                        pinctrl_pwm_leds: pwm-led {
+                                                atmel,pins =
+                                                        <AT91_PIOD 0  AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PD0 periph B */
+                                                         AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PD31 periph B */
+                                        };
+                                };
                         };
 
                         spi0: spi@fffa4000{
@@ -121,6 +129,42 @@
                                 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
+
+                        pwm0: pwm@fffb8000 {
+                                status = "okay";
+
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_pwm_leds>;
+                        };
+                };
+
+                fb0: fb@0x00500000 {
+                        display = <&display0>;
+                        status = "okay";
+
+                        display0: display {
+                                bits-per-pixel = <32>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <9>;
+                                atmel,lcd-wiring-mode = "RGB";
+
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <9000000>;
+                                                hactive = <480>;
+                                                vactive = <272>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <1>;
+                                                vback-porch = <40>;
+                                                vfront-porch = <1>;
+                                                hsync-len = <45>;
+                                                vsync-len = <1>;
+                                        };
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -165,16 +209,22 @@
                         gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
+        };
+
+        pwmleds {
+                compatible = "pwm-leds";
 
                 d6 {
                         label = "d6";
-                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 3 5000 0>;
+                        max-brightness = <255>;
                         linux,default-trigger = "nand-disk";
                 };
 
                 d7 {
                         label = "d7";
-                        gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 1 5000 0>;
+                        max-brightness = <255>;
                         linux,default-trigger = "mmc0";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 6224f9fe2f2b..394e6ce2afb7 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -33,6 +33,7 @@
                 i2c0 = &i2c0;
                 i2c1 = &i2c1;
                 ssc0 = &ssc0;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -540,6 +541,19 @@
                         watchdog@fffffe40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffe40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
+                                status = "disabled";
+                        };
+
+                        pwm0: pwm@f8034000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xf8034000 0x300>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40267a116c3c..174219de92fa 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -35,6 +35,7 @@
                 i2c1 = &i2c1;
                 i2c2 = &i2c2;
                 ssc0 = &ssc0;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <0>;
@@ -753,6 +754,11 @@
                         watchdog@fffffe40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffe40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
                                 status = "disabled";
                         };
 
@@ -762,6 +768,14 @@
                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 status = "disabled";
                         };
+
+                        pwm0: pwm@f8034000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xf8034000 0x300>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 978bab4991df..f8674bcc4489 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -27,6 +27,15 @@
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
+                        clocks = <&clks 12>;
+                        operating-points = <
+                                /* kHz    uV */
+                                200000  1025000
+                                400000  1025000
+                                600000  1050000
+                                800000  1100000
+                        >;
+                        clock-latency = <150000>;
                 };
         };
 
@@ -69,6 +78,7 @@
                         cphifbg@88030000 {
                                 compatible = "sirf,prima2-cphifbg";
                                 reg = <0x88030000 0x1000>;
+                                clocks = <&clks 42>;
                         };
                 };
 
@@ -546,6 +556,12 @@
                                                 sirf,function = "usp1";
                                         };
                                 };
+                                usp1_uart_nostreamctrl_pins_a: usp1@1 {
+                                        usp1 {
+                                                sirf,pins = "usp1_uart_nostreamctrl_grp";
+                                                sirf,function = "usp1_uart_nostreamctrl";
+                                        };
+                                };
                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
                                         usb0_upli_drvbus {
                                                 sirf,pins = "usb0_upli_drvbusgrp";
@@ -636,6 +652,7 @@
                                         reg = <0x56100000 0x100000>;
                                         interrupts = <38>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 36>;
                                 };
 
@@ -645,6 +662,7 @@
                                         reg = <0x56200000 0x100000>;
                                         interrupts = <23>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 37>;
                                 };
 
@@ -654,6 +672,7 @@
                                         reg = <0x56300000 0x100000>;
                                         interrupts = <23>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 37>;
                                 };
 
@@ -663,6 +682,7 @@
                                         reg = <0x56500000 0x100000>;
                                         interrupts = <39>;
                                         status = "disabled";
+                                        bus-width = <4>;
                                         clocks = <&clks 38>;
                                 };
 
@@ -697,6 +717,12 @@
                                 interrupts = <52 53 54>;
                         };
 
+                        minigpsrtc@2000 {
+                                compatible = "sirf,prima2-minigpsrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <54>;
+                        };
+
                         pwrc@3000 {
                                 compatible = "sirf,prima2-pwrc";
                                 reg = <0x3000 0x1000>;
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 23cd16d736bf..396b70459cdc 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -44,5 +44,11 @@
                 status = "okay";
         };
 
+        usbotg: usb@3f120000 {
+                status = "okay";
+        };
 
+        usbphy: usb-phy@3f130000 {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index b0c0610d1395..e491b82f8d67 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -43,7 +43,7 @@
                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                 status = "disabled";
                 reg = <0x3e000000 0x1000>;
-                clock-frequency = <13000000>;
+                clocks = <&uartb_clk>;
                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
@@ -53,7 +53,7 @@
                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                 status = "disabled";
                 reg = <0x3e001000 0x1000>;
-                clock-frequency = <13000000>;
+                clocks = <&uartb2_clk>;
                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
@@ -63,7 +63,7 @@
                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                 status = "disabled";
                 reg = <0x3e002000 0x1000>;
-                clock-frequency = <13000000>;
+                clocks = <&uartb3_clk>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
@@ -73,7 +73,7 @@
                 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                 status = "disabled";
                 reg = <0x3e003000 0x1000>;
-                clock-frequency = <13000000>;
+                clocks = <&uartb4_clk>;
                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
@@ -95,7 +95,7 @@
                 compatible = "brcm,kona-timer";
                 reg = <0x35006000 0x1000>;
                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                clock-frequency = <32768>;
+                clocks = <&hub_timer_clk>;
         };
 
         gpio: gpio@35003000 {
@@ -118,6 +118,7 @@
                 compatible = "brcm,kona-sdhci";
                 reg = <0x3f180000 0x10000>;
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio1_clk>;
                 status = "disabled";
         };
 
@@ -125,6 +126,7 @@
                 compatible = "brcm,kona-sdhci";
                 reg = <0x3f190000 0x10000>;
                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio2_clk>;
                 status = "disabled";
         };
 
@@ -132,6 +134,7 @@
                 compatible = "brcm,kona-sdhci";
                 reg = <0x3f1a0000 0x10000>;
                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio3_clk>;
                 status = "disabled";
         };
 
@@ -139,7 +142,168 @@
                 compatible = "brcm,kona-sdhci";
                 reg = <0x3f1b0000 0x10000>;
                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio4_clk>;
                 status = "disabled";
         };
 
+        pinctrl@35004800 {
+                compatible = "brcm,capri-pinctrl";
+                reg = <0x35004800 0x430>;
+        };
+
+        i2c@3e016000 {
+                compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
+                reg = <0x3e016000 0x80>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc1_clk>;
+                status = "disabled";
+        };
+
+        i2c@3e017000 {
+                compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
+                reg = <0x3e017000 0x80>;
+                interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc2_clk>;
+                status = "disabled";
+        };
+
+        i2c@3e018000 {
+                compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
+                reg = <0x3e018000 0x80>;
+                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc3_clk>;
+                status = "disabled";
+        };
+
+        i2c@3500d000 {
+                compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
+                reg = <0x3500d000 0x80>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&pmu_bsc_clk>;
+                status = "disabled";
+        };
+
+        clocks {
+                bsc1_clk: bsc1 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                bsc2_clk: bsc2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                bsc3_clk: bsc3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                pmu_bsc_clk: pmu_bsc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                hub_timer_clk: hub_timer {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        #clock-cells = <0>;
+                };
+
+                pwm_clk: pwm {
+                        compatible = "fixed-clock";
+                        clock-frequency = <26000000>;
+                        #clock-cells = <0>;
+                };
+
+                sdio1_clk: sdio1 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+
+                sdio2_clk: sdio2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+
+                sdio3_clk: sdio3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+
+                sdio4_clk: sdio4 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+
+                tmon_1m_clk: tmon_1m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <1000000>;
+                        #clock-cells = <0>;
+                };
+
+                uartb_clk: uartb {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                uartb2_clk: uartb2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                uartb3_clk: uartb3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                uartb4_clk: uartb4 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                usb_otg_ahb_clk: usb_otg_ahb {
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
+                        #clock-cells = <0>;
+                };
+        };
+
+        usbotg: usb@3f120000 {
+                compatible = "snps,dwc2";
+                reg = <0x3f120000 0x10000>;
+                interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usb_otg_ahb_clk>;
+                clock-names = "otg";
+                phys = <&usbphy>;
+                phy-names = "usb2-phy";
+                status = "disabled";
+        };
+
+        usbphy: usb-phy@3f130000 {
+                compatible = "brcm,kona-usb2-phy";
+                reg = <0x3f130000 0x28>;
+                #phy-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 08e47c285227..5ff2382a49e4 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -13,6 +13,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "bcm11351.dtsi"
 
 / {
@@ -27,6 +29,26 @@
                 status = "okay";
         };
 
+        i2c@3e016000 {
+                status="okay";
+                clock-frequency = <400000>;
+        };
+
+        i2c@3e017000 {
+                status="okay";
+                clock-frequency = <400000>;
+        };
+
+        i2c@3e018000 {
+                status="okay";
+                clock-frequency = <400000>;
+        };
+
+        i2c@3500d000 {
+                status="okay";
+                clock-frequency = <400000>;
+        };
+
         sdio1: sdio@3f180000 {
                 max-frequency = <48000000>;
                 status = "okay";
@@ -40,7 +62,15 @@
 
         sdio4: sdio@3f1b0000 {
                 max-frequency = <48000000>;
-                cd-gpios = <&gpio 14 0>;
+                cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+                status = "okay";
+        };
+
+        usbotg: usb@3f120000 {
+                status = "okay";
+        };
+
+        usbphy: usb-phy@3f130000 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 6e9deb786a7d..2a3b1c1313a0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -23,10 +23,15 @@
 
 &gpio {
         pinctrl-names = "default";
-        pinctrl-0 = <&alt0 &alt3>;
+        pinctrl-0 = <&gpioout &alt0 &alt3>;
+
+        gpioout: gpioout {
+                brcm,pins = <6>;
+                brcm,function = <1>; /* GPIO out */
+        };
 
         alt0: alt0 {
-                brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
+                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
                 brcm,function = <4>; /* alt0 */
         };
 
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index aa537ed13f0a..b021c96d3ba1 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -107,6 +107,12 @@
                         clocks = <&clk_mmc>;
                         status = "disabled";
                 };
+
+                usb {
+                        compatible = "brcm,bcm2835-usb";
+                        reg = <0x7e980000 0x10000>;
+                        interrupts = <1 9>;
+                };
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
new file mode 100644
index 000000000000..c72bfd468d10
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2.dtsi"
+
+/ {
+        model = "Sony NSZ-GS7";
+        compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>; /* 1 GB */
+        };
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
new file mode 100644
index 000000000000..56a1af2f1052
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "Marvell Armada 1500 (BG2) SoC";
+        compatible = "marvell,berlin2", "marvell,berlin";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "marvell,pj4b";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "marvell,pj4b";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                smclk: sysmgr-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+
+                cfgclk: cfg-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <100000000>;
+                };
+
+                sysclk: system-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <400000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&gic>;
+
+                ranges = <0 0xf7000000 0x1000000>;
+
+                l2: l2-cache-controller@ac0000 {
+                        compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+                        reg = <0xac0000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                gic: interrupt-controller@ad1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+
+                local-timer@ad0600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xad0600 0x20>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sysclk>;
+                };
+
+                apb@e80000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xe80000 0x10000>;
+                        interrupt-parent = <&aic>;
+
+                        timer0: timer@2c00 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c00 0x14>;
+                                interrupts = <8>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer1: timer@2c14 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c14 0x14>;
+                                interrupts = <9>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer2: timer@2c28 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c28 0x14>;
+                                interrupts = <10>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer3: timer@2c3c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c3c 0x14>;
+                                interrupts = <11>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer4: timer@2c50 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c50 0x14>;
+                                interrupts = <12>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer5: timer@2c64 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c64 0x14>;
+                                interrupts = <13>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer6: timer@2c78 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c78 0x14>;
+                                interrupts = <14>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer7: timer@2c8c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c8c 0x14>;
+                                interrupts = <15>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@3000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0x3000 0xc00>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                apb@fc0000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xfc0000 0x10000>;
+                        interrupt-parent = <&sic>;
+
+                        uart0: serial@9000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x9000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <8>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@a000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xa000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <9>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        uart2: serial@b000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xb000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <10>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        sic: interrupt-controller@e000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0xe000 0x400>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
new file mode 100644
index 000000000000..bcd81ffc495d
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Google Chromecast
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2cd.dtsi"
+
+/ {
+        model = "Google Chromecast";
+        compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
new file mode 100644
index 000000000000..094968c27533
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -0,0 +1,210 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "Marvell Armada 1500-mini (BG2CD) SoC";
+        compatible = "marvell,berlin2cd", "marvell,berlin";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <0>;
+                };
+        };
+
+        clocks {
+                smclk: sysmgr-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+
+                cfgclk: cfg-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <75000000>;
+                };
+
+                sysclk: system-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <300000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&gic>;
+
+                ranges = <0 0xf7000000 0x1000000>;
+
+                l2: l2-cache-controller@ac0000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xac0000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                gic: interrupt-controller@ad1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+
+                local-timer@ad0600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xad0600 0x20>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sysclk>;
+                };
+
+                apb@e80000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xe80000 0x10000>;
+                        interrupt-parent = <&aic>;
+
+                        timer0: timer@2c00 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c00 0x14>;
+                                interrupts = <8>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer1: timer@2c14 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c14 0x14>;
+                                interrupts = <9>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer2: timer@2c28 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c28 0x14>;
+                                interrupts = <10>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer3: timer@2c3c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c3c 0x14>;
+                                interrupts = <11>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer4: timer@2c50 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c50 0x14>;
+                                interrupts = <12>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer5: timer@2c64 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c64 0x14>;
+                                interrupts = <13>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer6: timer@2c78 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c78 0x14>;
+                                interrupts = <14>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer7: timer@2c8c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c8c 0x14>;
+                                interrupts = <15>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@3000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0x3000 0xc00>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                apb@fc0000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xfc0000 0x10000>;
+                        interrupt-parent = <&sic>;
+
+                        uart0: serial@9000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x9000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <8>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@a000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xa000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <9>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        sic: interrupt-controller@e000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0xe000 0x400>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 588ce58a2959..1e11e5a5f723 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -101,6 +101,9 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&mii_pins>;
                 };
+                gpio: gpio@1e26000 {
+                        status = "okay";
+                };
         };
         nand_cs3@62000000 {
                 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 8d17346f9702..b695548dbb4e 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -8,6 +8,7 @@
  * option) any later version.
  */
 #include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         arm {
@@ -256,6 +257,19 @@
                                         36
                                         >;
                 };
+                gpio: gpio@1e26000 {
+                        compatible = "ti,dm6441-gpio";
+                        gpio-controller;
+                        reg = <0x226000 0x1000>;
+                        interrupts = <42 IRQ_TYPE_EDGE_BOTH
+                                43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
+                                45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
+                                47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
+                                49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
+                        ti,ngpio = <144>;
+                        ti,davinci-gpio-unbanked = <0>;
+                        status = "disabled";
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 8349a248ecea..7a70f4ca502a 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -23,7 +23,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio0 18 1>;
-                        linux,default-trigger = "default-on";
+                        default-state = "keep";
                 };
         };
 
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 113a8bc7bee7..2b76524f4aa7 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -107,51 +107,29 @@
                                   0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
                                   0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */
 
-                        mbusc: mbus-ctrl@20000 {
-                                compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x80>, <0x800100 0x8>;
-                        };
-
-                        timer: timer@20300 {
-                                compatible = "marvell,orion-timer";
-                                reg = <0x20300 0x20>;
-                                interrupt-parent = <&bridge_intc>;
-                                interrupts = <1>, <2>;
+                        spi0: spi-ctrl@10600 {
+                                compatible = "marvell,orion-spi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <6>;
+                                reg = <0x10600 0x28>;
                                 clocks = <&core_clk 0>;
+                                pinctrl-0 = <&pmx_spi0>;
+                                pinctrl-names = "default";
+                                status = "disabled";
                         };
 
-                        intc: main-interrupt-ctrl@20200 {
-                                compatible = "marvell,orion-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0x20200 0x10>, <0x20210 0x10>;
-                        };
-
-                        bridge_intc: bridge-interrupt-ctrl@20110 {
-                                compatible = "marvell,orion-bridge-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0x20110 0x8>;
-                                interrupts = <0>;
-                                marvell,#interrupts = <5>;
-                        };
-
-                        core_clk: core-clocks@d0214 {
-                                compatible = "marvell,dove-core-clock";
-                                reg = <0xd0214 0x4>;
-                                #clock-cells = <1>;
-                        };
-
-                        gate_clk: clock-gating-ctrl@d0038 {
-                                compatible = "marvell,dove-gating-clock";
-                                reg = <0xd0038 0x4>;
+                        i2c0: i2c-ctrl@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <11>;
+                                clock-frequency = <400000>;
+                                timeout-ms = <1000>;
                                 clocks = <&core_clk 0>;
-                                #clock-cells = <1>;
-                        };
-
-                        thermal: thermal-diode@d001c {
-                                compatible = "marvell,dove-thermal";
-                                reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                                status = "disabled";
                         };
 
                         uart0: serial@12000 {
@@ -192,34 +170,222 @@
                                 status = "disabled";
                         };
 
-                        gpio0: gpio-ctrl@d0400 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xd0400 0x20>;
-                                ngpios = <32>;
+                        spi1: spi-ctrl@14600 {
+                                compatible = "marvell,orion-spi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <5>;
+                                reg = <0x14600 0x28>;
+                                clocks = <&core_clk 0>;
+                                status = "disabled";
+                        };
+
+                        mbusc: mbus-ctrl@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x80>, <0x800100 0x8>;
+                        };
+
+                        bridge_intc: bridge-interrupt-ctrl@20110 {
+                                compatible = "marvell,orion-bridge-intc";
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <12>, <13>, <14>, <60>;
+                                #interrupt-cells = <1>;
+                                reg = <0x20110 0x8>;
+                                interrupts = <0>;
+                                marvell,#interrupts = <5>;
                         };
 
-                        gpio1: gpio-ctrl@d0420 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xd0420 0x20>;
-                                ngpios = <32>;
+                        intc: main-interrupt-ctrl@20200 {
+                                compatible = "marvell,orion-intc";
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <61>;
+                                #interrupt-cells = <1>;
+                                reg = <0x20200 0x10>, <0x20210 0x10>;
                         };
 
-                        gpio2: gpio-ctrl@e8400 {
-                                compatible = "marvell,orion-gpio";
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                reg = <0xe8400 0x0c>;
-                                ngpios = <8>;
+                        timer: timer@20300 {
+                                compatible = "marvell,orion-timer";
+                                reg = <0x20300 0x20>;
+                                interrupt-parent = <&bridge_intc>;
+                                interrupts = <1>, <2>;
+                                clocks = <&core_clk 0>;
+                        };
+
+                        crypto: crypto-engine@30000 {
+                                compatible = "marvell,orion-crypto";
+                                reg = <0x30000 0x10000>,
+                                      <0xffffe000 0x800>;
+                                reg-names = "regs", "sram";
+                                interrupts = <31>;
+                                clocks = <&gate_clk 15>;
+                                status = "okay";
+                        };
+
+                        ehci0: usb-host@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x50000 0x1000>;
+                                interrupts = <24>;
+                                clocks = <&gate_clk 0>;
+                                status = "okay";
+                        };
+
+                        ehci1: usb-host@51000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x51000 0x1000>;
+                                interrupts = <25>;
+                                clocks = <&gate_clk 1>;
+                                status = "okay";
+                        };
+
+                        xor0: dma-engine@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60a00 0x100>;
+                                clocks = <&gate_clk 23>;
+                                status = "okay";
+
+                                channel0 {
+                                        interrupts = <39>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+
+                                channel1 {
+                                        interrupts = <40>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                        };
+
+                        xor1: dma-engine@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gate_clk 24>;
+                                status = "okay";
+
+                                channel0 {
+                                        interrupts = <42>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+
+                                channel1 {
+                                        interrupts = <43>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                        };
+
+                        sdio1: sdio-host@90000 {
+                                compatible = "marvell,dove-sdhci";
+                                reg = <0x90000 0x100>;
+                                interrupts = <36>, <38>;
+                                clocks = <&gate_clk 9>;
+                                pinctrl-0 = <&pmx_sdio1>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+
+                        eth: ethernet-ctrl@72000 {
+                                compatible = "marvell,orion-eth";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72000 0x4000>;
+                                clocks = <&gate_clk 2>;
+                                marvell,tx-checksum-limit = <1600>;
+                                status = "disabled";
+
+                                ethernet-port@0 {
+                                        compatible = "marvell,orion-eth-port";
+                                        reg = <0>;
+                                        interrupts = <29>;
+                                        /* overwrite MAC address in bootloader */
+                                        local-mac-address = [00 00 00 00 00 00];
+                                        phy-handle = <&ethphy>;
+                                };
+                        };
+
+                        mdio: mdio-bus@72004 {
+                                compatible = "marvell,orion-mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72004 0x84>;
+                                interrupts = <30>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+
+                                ethphy: ethernet-phy {
+                                        /* set phy address in board file */
+                                };
+                        };
+
+                        sdio0: sdio-host@92000 {
+                                compatible = "marvell,dove-sdhci";
+                                reg = <0x92000 0x100>;
+                                interrupts = <35>, <37>;
+                                clocks = <&gate_clk 8>;
+                                pinctrl-0 = <&pmx_sdio0>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+
+                        sata0: sata-host@a0000 {
+                                compatible = "marvell,orion-sata";
+                                reg = <0xa0000 0x2400>;
+                                interrupts = <62>;
+                                clocks = <&gate_clk 3>;
+                                phys = <&sata_phy0>;
+                                phy-names = "port0";
+                                nr-ports = <1>;
+                                status = "disabled";
+                        };
+
+                        sata_phy0: sata-phy@a2000 {
+                                compatible = "marvell,mvebu-sata-phy";
+                                reg = <0xa2000 0x0334>;
+                                clocks = <&gate_clk 3>;
+                                clock-names = "sata";
+                                #phy-cells = <0>;
+                                status = "ok";
+                        };
+
+                        audio0: audio-controller@b0000 {
+                                compatible = "marvell,dove-audio";
+                                reg = <0xb0000 0x2210>;
+                                interrupts = <19>, <20>;
+                                clocks = <&gate_clk 12>;
+                                clock-names = "internal";
+                                status = "disabled";
+                        };
+
+                        audio1: audio-controller@b4000 {
+                                compatible = "marvell,dove-audio";
+                                reg = <0xb4000 0x2210>;
+                                interrupts = <21>, <22>;
+                                clocks = <&gate_clk 13>;
+                                clock-names = "internal";
+                                status = "disabled";
+                        };
+
+                        thermal: thermal-diode@d001c {
+                                compatible = "marvell,dove-thermal";
+                                reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                        };
+
+                        gate_clk: clock-gating-ctrl@d0038 {
+                                compatible = "marvell,dove-gating-clock";
+                                reg = <0xd0038 0x4>;
+                                clocks = <&core_clk 0>;
+                                #clock-cells = <1>;
+                        };
+
+                        pmu_intc: pmu-interrupt-ctrl@d0050 {
+                                compatible = "marvell,dove-pmu-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd0050 0x8>;
+                                interrupts = <33>;
+                                marvell,#interrupts = <7>;
                         };
 
                         pinctrl: pin-ctrl@d0200 {
@@ -413,193 +579,47 @@
                                 };
                         };
 
-                        spi0: spi-ctrl@10600 {
-                                compatible = "marvell,orion-spi";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <0>;
-                                interrupts = <6>;
-                                reg = <0x10600 0x28>;
-                                clocks = <&core_clk 0>;
-                                pinctrl-0 = <&pmx_spi0>;
-                                pinctrl-names = "default";
-                                status = "disabled";
-                        };
-
-                        spi1: spi-ctrl@14600 {
-                                compatible = "marvell,orion-spi";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                cell-index = <1>;
-                                interrupts = <5>;
-                                reg = <0x14600 0x28>;
-                                clocks = <&core_clk 0>;
-                                status = "disabled";
-                        };
-
-                        i2c0: i2c-ctrl@11000 {
-                                compatible = "marvell,mv64xxx-i2c";
-                                reg = <0x11000 0x20>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                interrupts = <11>;
-                                clock-frequency = <400000>;
-                                timeout-ms = <1000>;
-                                clocks = <&core_clk 0>;
-                                status = "disabled";
-                        };
-
-                        ehci0: usb-host@50000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x50000 0x1000>;
-                                interrupts = <24>;
-                                clocks = <&gate_clk 0>;
-                                status = "okay";
-                        };
-
-                        ehci1: usb-host@51000 {
-                                compatible = "marvell,orion-ehci";
-                                reg = <0x51000 0x1000>;
-                                interrupts = <25>;
-                                clocks = <&gate_clk 1>;
-                                status = "okay";
-                        };
-
-                        sdio0: sdio-host@92000 {
-                                compatible = "marvell,dove-sdhci";
-                                reg = <0x92000 0x100>;
-                                interrupts = <35>, <37>;
-                                clocks = <&gate_clk 8>;
-                                pinctrl-0 = <&pmx_sdio0>;
-                                pinctrl-names = "default";
-                                status = "disabled";
+                        core_clk: core-clocks@d0214 {
+                                compatible = "marvell,dove-core-clock";
+                                reg = <0xd0214 0x4>;
+                                #clock-cells = <1>;
                         };
 
-                        sdio1: sdio-host@90000 {
-                                compatible = "marvell,dove-sdhci";
-                                reg = <0x90000 0x100>;
-                                interrupts = <36>, <38>;
-                                clocks = <&gate_clk 9>;
-                                pinctrl-0 = <&pmx_sdio1>;
-                                pinctrl-names = "default";
-                                status = "disabled";
+                        gpio0: gpio-ctrl@d0400 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xd0400 0x20>;
+                                ngpios = <32>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <12>, <13>, <14>, <60>;
                         };
 
-                        sata0: sata-host@a0000 {
-                                compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x2400>;
-                                interrupts = <62>;
-                                clocks = <&gate_clk 3>;
-                                nr-ports = <1>;
-                                status = "disabled";
+                        gpio1: gpio-ctrl@d0420 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xd0420 0x20>;
+                                ngpios = <32>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <61>;
                         };
 
                         rtc: real-time-clock@d8500 {
                                 compatible = "marvell,orion-rtc";
                                 reg = <0xd8500 0x20>;
+                                interrupt-parent = <&pmu_intc>;
+                                interrupts = <5>;
                         };
 
-                        crypto: crypto-engine@30000 {
-                                compatible = "marvell,orion-crypto";
-                                reg = <0x30000 0x10000>,
-                                      <0xffffe000 0x800>;
-                                reg-names = "regs", "sram";
-                                interrupts = <31>;
-                                clocks = <&gate_clk 15>;
-                                status = "okay";
-                        };
-
-                        xor0: dma-engine@60800 {
-                                compatible = "marvell,orion-xor";
-                                reg = <0x60800 0x100
-                                       0x60a00 0x100>;
-                                clocks = <&gate_clk 23>;
-                                status = "okay";
-
-                                channel0 {
-                                        interrupts = <39>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-
-                                channel1 {
-                                        interrupts = <40>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-                        };
-
-                        xor1: dma-engine@60900 {
-                                compatible = "marvell,orion-xor";
-                                reg = <0x60900 0x100
-                                       0x60b00 0x100>;
-                                clocks = <&gate_clk 24>;
-                                status = "okay";
-
-                                channel0 {
-                                        interrupts = <42>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-
-                                channel1 {
-                                        interrupts = <43>;
-                                        dmacap,memcpy;
-                                        dmacap,xor;
-                                };
-                        };
-
-                        mdio: mdio-bus@72004 {
-                                compatible = "marvell,orion-mdio";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                reg = <0x72004 0x84>;
-                                interrupts = <30>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-
-                                ethphy: ethernet-phy {
-                                        device-type = "ethernet-phy";
-                                        /* set phy address in board file */
-                                };
-                        };
-
-                        eth: ethernet-ctrl@72000 {
-                                compatible = "marvell,orion-eth";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                reg = <0x72000 0x4000>;
-                                clocks = <&gate_clk 2>;
-                                marvell,tx-checksum-limit = <1600>;
-                                status = "disabled";
-
-                                ethernet-port@0 {
-                                        device_type = "network";
-                                        compatible = "marvell,orion-eth-port";
-                                        reg = <0>;
-                                        interrupts = <29>;
-                                        /* overwrite MAC address in bootloader */
-                                        local-mac-address = [00 00 00 00 00 00];
-                                        phy-handle = <&ethphy>;
-                                };
-                        };
-
-                        audio0: audio-controller@b0000 {
-                                compatible = "marvell,dove-audio";
-                                reg = <0xb0000 0x2210>;
-                                interrupts = <19>, <20>;
-                                clocks = <&gate_clk 12>;
-                                clock-names = "internal";
-                                status = "disabled";
-                        };
-
-                        audio1: audio-controller@b4000 {
-                                compatible = "marvell,dove-audio";
-                                reg = <0xb4000 0x2210>;
-                                interrupts = <21>, <22>;
-                                clocks = <&gate_clk 13>;
-                                clock-names = "internal";
-                                status = "disabled";
+                        gpio2: gpio-ctrl@e8400 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0xe8400 0x0c>;
+                                ngpios = <8>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4e8b0a..1fd75aa4639d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,45 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,dra7-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a005000 {
+                        compatible = "ti,dra7-cm-core-aon";
+                        reg = <0x4a005000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,dra7-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -584,3 +623,5 @@
                 };
         };
 };
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 000000000000..e96da9a898ad
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2015 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        atl_clkin0_ck: atl_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin1_ck: atl_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin2_ck: atl_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atlclkin3_ck: atlclkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        hdmi_clkin_ck: hdmi_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlb_clkin_ck: mlb_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlbp_clkin_ck: mlbp_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <100000000>;
+        };
+
+        ref_clkin0_ck: ref_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin1_ck: ref_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin2_ck: ref_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin3_ck: ref_clkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        rmii_clk_ck: rmii_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        sdvenc_clkin_ck: sdvenc_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_20000000_ck: virt_20000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <20000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        sys_clkin2: sys_clkin2 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <22579200>;
+        };
+
+        usb_otg_clkin_ck: usb_otg_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_clkin_ck: video1_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_m2_clkin_ck: video1_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_clkin_ck: video2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_m2_clkin_ck: video2_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dclk_div: mpu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_dsp_ck: dpll_dsp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+                reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+        };
+
+        dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0244>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_m2_ck: dpll_iva_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dclk: iva_dclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_iva_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_gpu_ck: dpll_gpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+        };
+
+        dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02e8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0220>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_ck: dpll_gmac_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+        };
+
+        dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        video2_dclk_div: video2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_dclk_div: video1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_dclk_div: hdmi_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_eve_ck: dpll_eve_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+                reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+        };
+
+        dpll_eve_m2_ck: dpll_eve_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_eve_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0294>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        eve_dclk_div: eve_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_eve_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0228>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_dsp_ck>;
+        };
+
+        dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0248>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_gmac_ck>;
+        };
+
+        dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        gmii_m_clk_div: gmii_m_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_gmac_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hdmi_clk2_div: hdmi_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_div_clk: hdmi_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_clk2_div: video1_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_div_clk: video1_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_clk2_div: video2_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_div_clk: video2_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ipu1_gfclk_mux: ipu1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0520>;
+        };
+
+        mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x0550>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0560>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        uart6_gfclk_mux: uart6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin1: sys_clkin1 {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x0118>;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x0114>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x011c>;
+                ti,dividers = <8>, <16>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                reg = <0x0178>;
+                ti,max-div = <2>;
+        };
+
+        abe_giclk_div: abe_giclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                reg = <0x0174>;
+                ti,max-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x01d8>;
+                ti,dividers = <16>, <32>;
+        };
+
+        abe_sys_clk_div: abe_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0120>;
+                ti,max-div = <2>;
+        };
+
+        adc_gfclk_mux: adc_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+                reg = <0x01dc>;
+        };
+
+        sys_clk1_dclk_div: sys_clk1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c8>;
+                ti,index-power-of-two;
+        };
+
+        sys_clk2_dclk_div: sys_clk2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin2>;
+                ti,max-div = <64>;
+                reg = <0x01cc>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01bc>;
+                ti,index-power-of-two;
+        };
+
+        dsp_gclk_div: dsp_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x018c>;
+                ti,index-power-of-two;
+        };
+
+        gpu_dclk: gpu_dclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01a0>;
+                ti,index-power-of-two;
+        };
+
+        emif_phy_dclk_div: emif_phy_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0190>;
+                ti,index-power-of-two;
+        };
+
+        gmac_250m_dclk_div: gmac_250m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        l3init_480m_dclk_div: l3init_480m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01ac>;
+                ti,index-power-of-two;
+        };
+
+        usb_otg_dclk_div: usb_otg_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&usb_otg_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0184>;
+                ti,index-power-of-two;
+        };
+
+        sata_dclk_div: sata_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c0>;
+                ti,index-power-of-two;
+        };
+
+        pcie2_dclk_div: pcie2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b8>;
+                ti,index-power-of-two;
+        };
+
+        pcie_dclk_div: pcie_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b4>;
+                ti,index-power-of-two;
+        };
+
+        emu_dclk_div: emu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x0194>;
+                ti,index-power-of-two;
+        };
+
+        secure_32k_dclk_div: secure_32k_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&secure_32k_clk_src_ck>;
+                ti,max-div = <64>;
+                reg = <0x01c4>;
+                ti,index-power-of-two;
+        };
+
+        clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0158>;
+        };
+
+        clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x015c>;
+        };
+
+        clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0160>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        eve_clk: eve_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+                reg = <0x0180>;
+        };
+
+        hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01a4>;
+        };
+
+        mlb_clk: mlb_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlb_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0134>;
+                ti,index-power-of-two;
+        };
+
+        mlbp_clk: mlbp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlbp_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0130>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0138>;
+                ti,index-power-of-two;
+        };
+
+        timer_sys_clk_div: timer_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0144>;
+                ti,max-div = <2>;
+        };
+
+        video1_dpll_clk_mux: video1_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d0>;
+        };
+
+        video2_dpll_clk_mux: video2_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d4>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart10_gfclk_mux: uart10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1880>;
+        };
+};
+&cm_core_clocks {
+        dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin1>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c 0x4>;
+                ti,bit-shift = <7>;
+        };
+
+        apll_pcie_ck: apll_pcie_ck {
+                #clock-cells = <0>;
+                compatible = "ti,dra7-apll-clock";
+                clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+                reg = <0x021c>, <0x0220>;
+        };
+
+        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+        };
+
+        optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <9>;
+        };
+
+        optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&optfclk_pciephy_div>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <10>;
+        };
+
+        apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_m2_ck: apll_pcie_m2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+        };
+
+        dss_hdmi_clk: dss_hdmi_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&hdmi_dpll_clk_mux>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_video1_clk: dss_video1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video1_dpll_clk_mux>;
+                ti,bit-shift = <12>;
+                reg = <0x1120>;
+        };
+
+        dss_video2_clk: dss_video2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video2_dpll_clk_mux>;
+                ti,bit-shift = <13>;
+                reg = <0x1120>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1760>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1768>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1770>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1778>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1780>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1810>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1818>;
+        };
+
+        mmc1_clk32k: mmc1_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1328>;
+        };
+
+        mmc2_clk32k: mmc2_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1330>;
+        };
+
+        mmc3_clk32k: mmc3_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1820>;
+        };
+
+        mmc4_clk32k: mmc4_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1828>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin1>;
+                ti,bit-shift = <8>;
+                reg = <0x1388>;
+        };
+
+        usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x13f0>;
+        };
+
+        usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x1340>;
+        };
+
+        usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0688>;
+        };
+
+        usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0698>;
+        };
+
+        atl_dpll_clk_mux: atl_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0c00>;
+        };
+
+        atl_gfclk_mux: atl_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+                ti,bit-shift = <26>;
+                reg = <0x0c00>;
+        };
+
+        gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x13d0>;
+                ti,dividers = <2>;
+        };
+
+        gmac_rft_clk_mux: gmac_rft_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+                ti,bit-shift = <25>;
+                reg = <0x13d0>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <26>;
+                reg = <0x1220>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0e50>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1860>;
+        };
+
+        mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1868>;
+        };
+
+        mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1868>;
+        };
+
+        mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1898>;
+        };
+
+        mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1898>;
+        };
+
+        mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1878>;
+        };
+
+        mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1878>;
+        };
+
+        mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1904>;
+        };
+
+        mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1904>;
+        };
+
+        mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1908>;
+        };
+
+        mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1908>;
+        };
+
+        mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <22>;
+                reg = <0x1890>;
+        };
+
+        mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <24>;
+                reg = <0x1890>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        mmc1_fclk_div: mmc1_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1328>;
+                ti,index-power-of-two;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        mmc2_fclk_div: mmc2_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1330>;
+                ti,index-power-of-two;
+        };
+
+        mmc3_gfclk_mux: mmc3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1820>;
+        };
+
+        mmc3_gfclk_div: mmc3_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc3_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1820>;
+                ti,index-power-of-two;
+        };
+
+        mmc4_gfclk_mux: mmc4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1828>;
+        };
+
+        mmc4_gfclk_div: mmc4_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc4_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1828>;
+                ti,index-power-of-two;
+        };
+
+        qspi_gfclk_mux: qspi_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1838>;
+        };
+
+        qspi_gfclk_div: qspi_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&qspi_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1838>;
+                ti,index-power-of-two;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1728>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1730>;
+        };
+
+        timer13_gfclk_mux: timer13_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17c8>;
+        };
+
+        timer14_gfclk_mux: timer14_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d0>;
+        };
+
+        timer15_gfclk_mux: timer15_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d8>;
+        };
+
+        timer16_gfclk_mux: timer16_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1830>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1738>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1740>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1748>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1750>;
+        };
+
+        uart1_gfclk_mux: uart1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart2_gfclk_mux: uart2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1848>;
+        };
+
+        uart3_gfclk_mux: uart3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1850>;
+        };
+
+        uart4_gfclk_mux: uart4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+        };
+
+        uart5_gfclk_mux: uart5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1870>;
+        };
+
+        uart7_gfclk_mux: uart7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18d0>;
+        };
+
+        uart8_gfclk_mux: uart8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e0>;
+        };
+
+        uart9_gfclk_mux: uart9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e8>;
+        };
+
+        vip1_gclk_mux: vip1_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1020>;
+        };
+
+        vip2_gclk_mux: vip2_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        vip3_gclk_mux: vip3_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+};
+
+&cm_core_clockdomains {
+        coreaon_clkdm: coreaon_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts
new file mode 100644
index 000000000000..aa5c0f6363d6
--- /dev/null
+++ b/arch/arm/boot/dts/efm32gg-dk3750.dts
@@ -0,0 +1,86 @@
+/*
+ * Device tree for EFM32GG-DK3750 development board.
+ *
+ * Documentation available from
+ * http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf
+ */
+
+/dts-v1/;
+#include "efm32gg.dtsi"
+
+/ {
+        model = "Energy Micro Giant Gecko Development Kit";
+        compatible = "efm32,dk3750";
+
+        chosen {
+                bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0";
+        };
+
+        memory {
+                reg = <0x88000000 0x400000>;
+        };
+
+        soc {
+                adc@40002000 {
+                        status = "ok";
+                };
+
+                i2c@4000a000 {
+                        location = <3>;
+                        status = "ok";
+
+                        temp@48 {
+                                compatible = "st,stds75";
+                                reg = <0x48>;
+                        };
+
+                        eeprom@50 {
+                                compatible = "microchip,24c02";
+                                reg = <0x50>;
+                                pagesize = <16>;
+                        };
+                };
+
+                spi0: spi@4000c000 { /* USART0 */
+                        cs-gpios = <&gpio 68 1>; // E4
+                        location = <1>;
+                        status = "ok";
+
+                        microsd@0 {
+                                compatible = "mmc-spi-slot";
+                                spi-max-frequency = <100000>;
+                                voltage-ranges = <3200 3400>;
+                                broken-cd;
+                                reg = <0>;
+                        };
+                };
+
+                spi1: spi@4000c400 { /* USART1 */
+                        cs-gpios = <&gpio 51 1>; // D3
+                        location = <1>;
+                        status = "ok";
+
+                        ks8851@0 {
+                                compatible = "ks8851";
+                                spi-max-frequency = <6000000>;
+                                reg = <0>;
+                                interrupt-parent = <&boardfpga>;
+                                interrupts = <4>;
+                        };
+                };
+
+                uart4: uart@4000e400 { /* UART1 */
+                        location = <2>;
+                        status = "ok";
+                };
+
+                boardfpga: boardfpga {
+                        compatible = "efm32board";
+                        reg = <0x80000000 0x400>;
+                        irq-gpios = <&gpio 64 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        status = "ok";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi
new file mode 100644
index 000000000000..a342ab0e6e4f
--- /dev/null
+++ b/arch/arm/boot/dts/efm32gg.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Device tree for Energy Micro EFM32 Giant Gecko SoC.
+ *
+ * Documentation available from
+ * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
+ */
+#include "armv7-m.dtsi"
+#include "dt-bindings/clock/efm32-cmu.h"
+
+/ {
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                spi0 = &spi0;
+                spi1 = &spi1;
+                spi2 = &spi2;
+        };
+
+        soc {
+                adc: adc@40002000 {
+                        compatible = "efm32,adc";
+                        reg = <0x40002000 0x400>;
+                        interrupts = <7>;
+                        clocks = <&cmu clk_HFPERCLKADC0>;
+                        status = "disabled";
+                };
+
+                gpio: gpio@40006000 {
+                        compatible = "efm32,gpio";
+                        reg = <0x40006000 0x1000>;
+                        interrupts = <1 11>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        clocks = <&cmu clk_HFPERCLKGPIO>;
+                        status = "ok";
+                };
+
+                i2c0: i2c@4000a000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "efm32,i2c";
+                        reg = <0x4000a000 0x400>;
+                        interrupts = <9>;
+                        clocks = <&cmu clk_HFPERCLKI2C0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@4000a400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "efm32,i2c";
+                        reg = <0x4000a400 0x400>;
+                        interrupts = <10>;
+                        clocks = <&cmu clk_HFPERCLKI2C1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                spi0: spi@4000c000 { /* USART0 */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "efm32,spi";
+                        reg = <0x4000c000 0x400>;
+                        interrupts = <3 4>;
+                        clocks = <&cmu clk_HFPERCLKUSART0>;
+                        status = "disabled";
+                };
+
+                spi1: spi@4000c400 { /* USART1 */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "efm32,spi";
+                        reg = <0x4000c400 0x400>;
+                        interrupts = <15 16>;
+                        clocks = <&cmu clk_HFPERCLKUSART1>;
+                        status = "disabled";
+                };
+
+                spi2: spi@40x4000c800 { /* USART2 */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "efm32,spi";
+                        reg = <0x4000c800 0x400>;
+                        interrupts = <18 19>;
+                        clocks = <&cmu clk_HFPERCLKUSART2>;
+                        status = "disabled";
+                };
+
+                uart0: uart@4000c000 { /* USART0 */
+                        compatible = "efm32,uart";
+                        reg = <0x4000c000 0x400>;
+                        interrupts = <3 4>;
+                        clocks = <&cmu clk_HFPERCLKUSART0>;
+                        status = "disabled";
+                };
+
+                uart1: uart@4000c400 { /* USART1 */
+                        compatible = "efm32,uart";
+                        reg = <0x4000c400 0x400>;
+                        interrupts = <15 16>;
+                        clocks = <&cmu clk_HFPERCLKUSART1>;
+                        status = "disabled";
+                };
+
+                uart2: uart@40x4000c800 { /* USART2 */
+                        compatible = "efm32,uart";
+                        reg = <0x4000c800 0x400>;
+                        interrupts = <18 19>;
+                        clocks = <&cmu clk_HFPERCLKUSART2>;
+                        status = "disabled";
+                };
+
+                uart3: uart@4000e000 { /* UART0 */
+                        compatible = "efm32,uart";
+                        reg = <0x4000e000 0x400>;
+                        interrupts = <20 21>;
+                        clocks = <&cmu clk_HFPERCLKUART0>;
+                        status = "disabled";
+                };
+
+                uart4: uart@4000e400 { /* UART1 */
+                        compatible = "efm32,uart";
+                        reg = <0x4000e400 0x400>;
+                        interrupts = <22 23>;
+                        clocks = <&cmu clk_HFPERCLKUART1>;
+                        status = "disabled";
+                };
+
+                timer0: timer@40010000 {
+                        compatible = "efm32,timer";
+                        reg = <0x40010000 0x400>;
+                        interrupts = <2>;
+                        clocks = <&cmu clk_HFPERCLKTIMER0>;
+                };
+
+                timer1: timer@40010400 {
+                        compatible = "efm32,timer";
+                        reg = <0x40010400 0x400>;
+                        interrupts = <12>;
+                        clocks = <&cmu clk_HFPERCLKTIMER1>;
+                };
+
+                timer2: timer@40010800 {
+                        compatible = "efm32,timer";
+                        reg = <0x40010800 0x400>;
+                        interrupts = <13>;
+                        clocks = <&cmu clk_HFPERCLKTIMER2>;
+                };
+
+                timer3: timer@40010c00 {
+                        compatible = "efm32,timer";
+                        reg = <0x40010c00 0x400>;
+                        interrupts = <14>;
+                        clocks = <&cmu clk_HFPERCLKTIMER3>;
+                };
+
+                cmu: cmu@400c8000 {
+                        compatible = "efm32gg,cmu";
+                        reg = <0x400c8000 0x400>;
+                        interrupts = <32>;
+                        #clock-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 861aa7d6fc7d..50ccd151091e 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -9,7 +9,10 @@
  */
 /dts-v1/;
 
-/include/ "emev2.dtsi"
+#include "emev2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "EMEV2 KZM9D Board";
@@ -47,11 +50,46 @@
                 reg = <0x20000000 0x10000>;
                 phy-mode = "mii";
                 interrupt-parent = <&gpio0>;
-                interrupts = <1 1>;     /* active high */
+                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
                 reg-io-width = <4>;
                 smsc,irq-active-high;
                 smsc,irq-push-pull;
                 vddvario-supply = <&reg_1p8v>;
                 vdd33a-supply = <&reg_3p3v>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-1";
+                        linux,code = <KEY_1>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+                };
+                button@2 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-2";
+                        linux,code = <KEY_2>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+                };
+                button@3 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-3";
+                        linux,code = <KEY_3>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+                };
+                button@4 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        label = "DSW2-4";
+                        linux,code = <KEY_4>;
+                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 9063a4434d6a..e37985fa10e2 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -8,7 +8,8 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         compatible = "renesas,emev2";
@@ -48,44 +49,129 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 120 4>,
-                             <0 121 4>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 121 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        smu@e0110000 {
+                compatible = "renesas,emev2-smu";
+                reg = <0xe0110000 0x10000>;
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                c32ki: c32ki {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        #clock-cells = <0>;
+                };
+                pll3_fo: pll3_fo {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&c32ki>;
+                        clock-div = <1>;
+                        clock-mult = <7000>;
+                        #clock-cells = <0>;
+                };
+                usia_u0_sclkdiv: usia_u0_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x610 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u1_sclkdiv: usib_u1_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x65c 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u2_sclkdiv: usib_u2_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x65c 16>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usib_u3_sclkdiv: usib_u3_sclkdiv {
+                        compatible = "renesas,emev2-smu-clkdiv";
+                        reg = <0x660 0>;
+                        clocks = <&pll3_fo>;
+                        #clock-cells = <0>;
+                };
+                usia_u0_sclk: usia_u0_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4a0 1>;
+                        clocks = <&usia_u0_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u1_sclk: usib_u1_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4b8 1>;
+                        clocks = <&usib_u1_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u2_sclk: usib_u2_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4bc 1>;
+                        clocks = <&usib_u2_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                usib_u3_sclk: usib_u3_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x4c0 1>;
+                        clocks = <&usib_u3_sclkdiv>;
+                        #clock-cells = <0>;
+                };
+                sti_sclk: sti_sclk {
+                        compatible = "renesas,emev2-smu-gclk";
+                        reg = <0x528 1>;
+                        clocks = <&c32ki>;
+                        #clock-cells = <0>;
+                };
         };
 
         sti@e0180000 {
                 compatible = "renesas,em-sti";
                 reg = <0xe0180000 0x54>;
-                interrupts = <0 125 0>;
+                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sti_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1020000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1020000 0x38>;
-                interrupts = <0 8 0>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usia_u0_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1030000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1030000 0x38>;
-                interrupts = <0 9 0>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u1_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1040000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1040000 0x38>;
-                interrupts = <0 10 0>;
+                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u2_sclk>;
+                clock-names = "sclk";
         };
 
         uart@e1050000 {
                 compatible = "renesas,em-uart";
                 reg = <0xe1050000 0x38>;
-                interrupts = <0 11 0>;
+                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usib_u3_sclk>;
+                clock-names = "sclk";
         };
 
         gpio0: gpio@e0050000 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
-                interrupts = <0 67 0>, <0 68 0>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 68 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -95,7 +181,8 @@
         gpio1: gpio@e0050080 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
-                interrupts = <0 69 0>, <0 70 0>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 70 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -105,7 +192,8 @@
         gpio2: gpio@e0050100 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
-                interrupts = <0 71 0>, <0 72 0>;
+                interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 72 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -115,7 +203,8 @@
         gpio3: gpio@e0050180 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
-                interrupts = <0 73 0>, <0 74 0>;
+                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <32>;
@@ -125,7 +214,8 @@
         gpio4: gpio@e0050200 {
                 compatible = "renesas,em-gio";
                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
-                interrupts = <0 75 0>, <0 76 0>;
+                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 76 IRQ_TYPE_LEVEL_HIGH>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpios = <31>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a73eeb5f258f..08452e183b57 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -85,21 +85,21 @@
                 reg = <0x10023CE0 0x20>;
         };
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
                 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 compatible = "samsung,exynos4210-combiner";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0x10440000 0x1000>;
         };
 
-        sys_reg: sysreg {
+        sys_reg: syscon@10010000 {
                 compatible = "samsung,exynos4-sysreg", "syscon";
                 reg = <0x10010000 0x400>;
         };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 1a12fb23767c..2aa13cb3bbed 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -313,7 +313,7 @@
         display-timings {
                 native-mode = <&timing0>;
                 timing0: timing {
-                        clock-frequency = <50000>;
+                        clock-frequency = <47500000>;
                         hactive = <1024>;
                         vactive = <600>;
                         hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 057d6829d319..48ecd7a755ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -36,11 +36,11 @@
                 reg = <0x10023CA0 0x20>;
         };
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 samsung,combiner-nr = <16>;
                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
@@ -51,24 +51,21 @@
         mct@10050000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
                 clocks = <&clock 3>, <&clock 344>;
                 clock-names = "fin_pll", "mct";
 
                 mct_map: mct-map {
-                        #interrupt-cells = <2>;
+                        #interrupt-cells = <1>;
                         #address-cells = <0>;
                         #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &gic 0 69 0>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 0 42 0>,
-                                        <0x5 0 &gic 0 48 0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &gic 0 69 0>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 0 42 0>,
+                                        <5 &gic 0 48 0>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 6f34d7f6ba7e..94a43f9a05e2 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,7 +22,7 @@
 / {
         compatible = "samsung,exynos4212";
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
 
@@ -34,26 +34,4 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
                              <0 107 0>, <0 108 0>;
         };
-
-        mct@10050000 {
-                compatible = "samsung,exynos4412-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
-
-                mct_map: mct-map {
-                        #interrupt-cells = <2>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &combiner 12 5>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 1 12 0>,
-                                        <0x5 0 &gic 1 12 0>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 46c678ee119c..9804fcb71f8c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -38,9 +38,7 @@
                 };
         };
 
-        mshc@12550000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
+        mmc@12550000 {
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
                 vmmc-supply = <&ldo20_reg &buck8_reg>;
@@ -49,7 +47,6 @@
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -119,6 +116,7 @@
                 max77686: pmic@09 {
                         compatible = "maxim,max77686";
                         reg = <0x09>;
+                        #clock-cells = <1>;
 
                         voltage-regulators {
                                 ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index d65984c440f6..6bc053924e9e 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -122,9 +122,7 @@
                 status = "okay";
         };
 
-        mshc@12550000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
+        mmc@12550000 {
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
                 status = "okay";
@@ -132,7 +130,6 @@
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -159,7 +156,7 @@
         display-timings {
                 native-mode = <&timing0>;
                 timing0: timing {
-                        clock-frequency = <50000>;
+                        clock-frequency = <47500000>;
                         hactive = <1024>;
                         vactive = <600>;
                         hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
new file mode 100644
index 000000000000..0a9831256b33
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -0,0 +1,93 @@
+/*
+ * FriendlyARM's Exynos4412 based TINY4412 board device tree source
+ *
+ * Copyright (c) 2013 Alex Ling <kasimling@gmail.com>
+ *
+ * Device tree source file for FriendlyARM's TINY4412 board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+
+/ {
+        model = "FriendlyARM TINY4412 board based on Exynos4412";
+        compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led1 {
+                        label = "led1";
+                        gpios = <&gpm4 0 1>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led2 {
+                        label = "led2";
+                        gpios = <&gpm4 1 1>;
+                        default-state = "off";
+                };
+
+                led3 {
+                        label = "led3";
+                        gpios = <&gpm4 2 1>;
+                        default-state = "off";
+                };
+
+                led4 {
+                        label = "led4";
+                        gpios = <&gpm4 3 1>;
+                        default-state = "off";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index fb7b9ae5f399..4f851ccf40eb 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -139,6 +139,7 @@
                         interrupt-parent = <&gpx0>;
                         interrupts = <7 0>;
                         reg = <0x09>;
+                        #clock-cells = <1>;
 
                         voltage-regulators {
                                 ldo1_reg: ldo1 {
@@ -442,13 +443,25 @@
                 };
         };
 
-        sdhci@12510000 {
-                bus-width = <8>;
+        mmc@12550000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
                 non-removable;
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
-                pinctrl-names = "default";
+                card-detect-delay = <200>;
                 vmmc-supply = <&vemmc_reg>;
+                clock-frequency = <400000000>;
+                samsung,dw-mshc-ciu-div = <0>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
                 status = "okay";
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
         };
 
         serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index e743e677a9e2..87b339c739de 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,7 +22,7 @@
 / {
         compatible = "samsung,exynos4412";
 
-        gic:interrupt-controller@10490000 {
+        gic: interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
 
@@ -35,37 +35,4 @@
                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
         };
 
-        mct@10050000 {
-                compatible = "samsung,exynos4412-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>, <6 0>, <7 0>;
-                clocks = <&clock 3>, <&clock 344>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
-                        #interrupt-cells = <2>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0x0 0 &gic 0 57 0>,
-                                        <0x1 0 &combiner 12 5>,
-                                        <0x2 0 &combiner 12 6>,
-                                        <0x3 0 &combiner 12 7>,
-                                        <0x4 0 &gic 1 12 0>,
-                                        <0x5 0 &gic 1 12 0>,
-                                        <0x6 0 &gic 1 12 0>,
-                                        <0x7 0 &gic 1 12 0>;
-                };
-        };
-
-        mshc@12550000 {
-                compatible = "samsung,exynos4412-dw-mshc";
-                reg = <0x12550000 0x1000>;
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe6ab95..5c412aa14738 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -28,6 +28,7 @@
                 pinctrl3 = &pinctrl_3;
                 fimc-lite0 = &fimc_lite_0;
                 fimc-lite1 = &fimc_lite_1;
+                mshc0 = &mshc_0;
         };
 
         pd_isp: isp-power-domain@10023CA0 {
@@ -41,6 +42,26 @@
                 #clock-cells = <1>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0>, <1>, <2>, <3>, <4>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &combiner 12 5>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 1 12 0>;
+                };
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
@@ -176,4 +197,16 @@
                         };
                 };
         };
+
+        mshc_0: mmc@12550000 {
+                compatible = "samsung,exynos4412-dw-mshc";
+                reg = <0x12550000 0x1000>;
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                fifo-depth = <0x80>;
+                clocks = <&clock 301>, <&clock 149>;
+                clock-names = "biu", "ciu";
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 074739d39e2d..258dca441f36 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -23,7 +23,7 @@
                 reg = <0x10000000 0x100>;
         };
 
-        combiner:interrupt-controller@10440000 {
+        combiner: interrupt-controller@10440000 {
                 compatible = "samsung,exynos4210-combiner";
                 #interrupt-cells = <2>;
                 interrupt-controller;
@@ -39,7 +39,7 @@
                                 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
-        gic:interrupt-controller@10481000 {
+        gic: interrupt-controller@10481000 {
                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
@@ -50,27 +50,6 @@
                 interrupts = <1 9 0xf04>;
         };
 
-        dwmmc_0: dwmmc0@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc_1: dwmmc1@12210000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        dwmmc_2: dwmmc2@12220000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 684527087aa4..b42e658876e5 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -34,6 +34,7 @@
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
                 samsung,i2c-slave-addr = <0x66>;
+                status = "okay";
 
                 s5m8767_pmic@66 {
                         compatible = "samsung,s5m8767-pmic";
@@ -266,7 +267,7 @@
 
                                 buck2_reg: BUCK2 {
                                         regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <925000>;
+                                        regulator-min-microvolt = <912500>;
                                         regulator-max-microvolt = <1300000>;
                                         regulator-always-on;
                                         regulator-boot-on;
@@ -302,11 +303,13 @@
                                 buck7_reg: BUCK7 {
                                         regulator-name = "PVDD_BUCK7";
                                         regulator-always-on;
+                                        op_mode = <1>;
                                 };
 
                                 buck8_reg: BUCK8 {
                                         regulator-name = "PVDD_BUCK8";
                                         regulator-always-on;
+                                        op_mode = <1>;
                                 };
 
                                 buck9_reg: BUCK9 {
@@ -319,11 +322,9 @@
                 };
         };
 
-        i2c@12C70000 {
-                status = "disabled";
-        };
-
         i2c@12C80000 {
+                status = "okay";
+
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
                 samsung,i2c-slave-addr = <0x50>;
@@ -335,7 +336,10 @@
         };
 
         i2c@12C90000 {
+                status = "okay";
+
                 wm1811a@1a {
+
                         compatible = "wlf,wm1811";
                         reg = <0x1a>;
 
@@ -353,23 +357,9 @@
                 };
         };
 
-        i2c@12CA0000 {
-                status = "disabled";
-        };
-
-        i2c@12CB0000 {
-                status = "disabled";
-        };
-
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
-        i2c@12CD0000 {
-                status = "disabled";
-        };
-
         i2c@12CE0000 {
+                status = "okay";
+
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
                 samsung,i2c-slave-addr = <0x38>;
@@ -380,15 +370,11 @@
                 };
         };
 
-        i2c@121D0000 {
-                status = "disabled";
-        };
-
-        dwmmc_0: dwmmc0@12200000 {
+        mmc_0: mmc@12200000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -403,14 +389,10 @@
                 };
         };
 
-        dwmmc_1: dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc_2: dwmmc2@12220000 {
+        mmc_2: mmc@12220000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -426,26 +408,10 @@
                 };
         };
 
-        dwmmc_3: dwmmc3@12230000 {
-                status = "disabled";
-        };
-
         i2s0: i2s@03830000 {
                 status = "okay";
         };
 
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
-
-        spi_1: spi@12d30000 {
-                status = "disabled";
-        };
-
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         gpio_keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 9b186ac06c8b..2c1560d52f1a 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -37,6 +37,7 @@
         };
 
         i2c@12C60000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -48,6 +49,7 @@
                         pinctrl-0 = <&max77686_irq>;
                         wakeup-source;
                         reg = <0x09>;
+                        #clock-cells = <1>;
 
                         voltage-regulators {
                                 ldo1_reg: LDO1 {
@@ -185,6 +187,7 @@
         };
 
         i2c@12C70000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -198,6 +201,7 @@
         };
 
         i2c@12C80000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
 
@@ -208,30 +212,31 @@
         };
 
         i2c@12C90000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CA0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CB0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
         i2c@12CD0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
         };
 
         i2c@12CE0000 {
+                status = "okay";
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
 
@@ -241,11 +246,10 @@
                 };
         };
 
-        dwmmc0@12200000 {
+        mmc@12200000 {
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -259,14 +263,9 @@
                 };
         };
 
-        dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc2@12220000 {
+        mmc@12220000 {
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -281,11 +280,10 @@
                 };
         };
 
-        dwmmc3@12230000 {
+        mmc@12230000 {
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -298,19 +296,12 @@
                 };
         };
 
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
-
         spi_1: spi@12d30000 {
+                status = "okay";
                 samsung,spi-src-clk = <0>;
                 num-cs = <1>;
         };
 
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         hdmi {
                 hpd-gpio = <&gpx3 7 0>;
         };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f86d56760a45..3e69837c435c 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,7 @@
         i2c@12C60000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
+                status = "okay";
 
                 eeprom@50 {
                         compatible = "samsung,s524ad0xd1";
@@ -37,7 +38,7 @@
                 };
         };
 
-        vdd:fixed-regulator@0 {
+        vdd: fixed-regulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "vdd-supply";
                 regulator-min-microvolt = <1800000>;
@@ -45,7 +46,7 @@
                 regulator-always-on;
         };
 
-        dbvdd:fixed-regulator@1 {
+        dbvdd: fixed-regulator@1 {
                 compatible = "regulator-fixed";
                 regulator-name = "dbvdd-supply";
                 regulator-min-microvolt = <3300000>;
@@ -53,7 +54,7 @@
                 regulator-always-on;
         };
 
-        spkvdd:fixed-regulator@2 {
+        spkvdd: fixed-regulator@2 {
                 compatible = "regulator-fixed";
                 regulator-name = "spkvdd-supply";
                 regulator-min-microvolt = <5000000>;
@@ -64,6 +65,7 @@
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
+                status = "okay";
 
                 eeprom@51 {
                         compatible = "samsung,s524ad0xd1";
@@ -77,6 +79,9 @@
                         gpio-controller;
                         #gpio-cells = <2>;
 
+                        clocks = <&codec_mclk>;
+                        clock-names = "MCLK1";
+
                         AVDD2-supply = <&vdd>;
                         CPVDD-supply = <&vdd>;
                         DBVDD-supply = <&dbvdd>;
@@ -89,6 +94,7 @@
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <40000>;
                 samsung,i2c-slave-addr = <0x38>;
+                status = "okay";
 
                 sata-phy {
                         compatible = "samsung,sata-phy";
@@ -103,6 +109,7 @@
         i2c@12C80000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
+                status = "okay";
 
                 hdmiddc@50 {
                         compatible = "samsung,exynos4210-hdmiddc";
@@ -110,29 +117,10 @@
                 };
         };
 
-        i2c@12C90000 {
-                status = "disabled";
-        };
-
-        i2c@12CA0000 {
-                status = "disabled";
-        };
-
-        i2c@12CB0000 {
-                status = "disabled";
-        };
-
-        i2c@12CC0000 {
-                status = "disabled";
-        };
-
-        i2c@12CD0000 {
-                status = "disabled";
-        };
-
         i2c@12CE0000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
+                status = "okay";
 
                 hdmiphy@38 {
                         compatible = "samsung,exynos4212-hdmiphy";
@@ -140,11 +128,11 @@
                 };
         };
 
-        dwmmc0@12200000 {
+        mmc@12200000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
                 broken-cd;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -158,14 +146,10 @@
                 };
         };
 
-        dwmmc1@12210000 {
-                status = "disabled";
-        };
-
-        dwmmc2@12220000 {
+        mmc@12220000 {
+                status = "okay";
                 num-slots = <1>;
                 supports-highspeed;
-                fifo-depth = <0x80>;
                 card-detect-delay = <200>;
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -180,15 +164,13 @@
                 };
         };
 
-        dwmmc3@12230000 {
-                status = "disabled";
-        };
-
         spi_0: spi@12d20000 {
                 status = "disabled";
         };
 
         spi_1: spi@12d30000 {
+                status = "okay";
+
                 w25q80bw@0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -214,10 +196,6 @@
                 };
         };
 
-        spi_2: spi@12d40000 {
-                status = "disabled";
-        };
-
         hdmi {
                 hpd-gpio = <&gpx3 7 0>;
         };
@@ -279,5 +257,11 @@
                         compatible = "samsung,clock-xxti";
                         clock-frequency = <24000000>;
                 };
+
+                codec_mclk: codec-mclk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <16934000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index fd711e245e8d..7e45eea2d78f 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -10,7 +10,7 @@
 
 /dts-v1/;
 #include "exynos5250.dtsi"
-#include "cros5250-common.dtsi"
+#include "exynos5250-cros-common.dtsi"
 
 / {
         model = "Google Snow";
@@ -85,7 +85,7 @@
                                         keypad,num-rows = <8>;
                                         keypad,num-columns = <13>;
                                         google,needs-ghost-filter;
-                                        linux,keymap = <0x0001003a      /* CAPSLK */
+                                        linux,keymap = <0x0001007d      /* L_META */
                                                         0x0002003b      /* F1 */
                                                         0x00030030      /* B */
                                                         0x00040044      /* F10 */
@@ -130,6 +130,7 @@
                                                         0x04060024      /* J */
                                                         0x04080027      /* ; */
                                                         0x04090026      /* L */
+                                                        0x040a002b      /* \ */
                                                         0x040b001c      /* ENTER */
 
                                                         0x0501002c      /* Z */
@@ -171,11 +172,20 @@
                 };
         };
 
+        mmc@12200000 {
+                status = "okay";
+        };
+
+        mmc@12220000 {
+                status = "okay";
+        };
+
         /*
          * On Snow we've got SIP WiFi and so can keep drive strengths low to
          * reduce EMI.
          */
-        dwmmc3@12230000 {
+        mmc@12230000 {
+                status = "okay";
                 slot@0 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 177becde7a26..b7dec41e32af 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -33,10 +33,10 @@
                 gsc1 = &gsc_1;
                 gsc2 = &gsc_2;
                 gsc3 = &gsc_3;
-                mshc0 = &dwmmc_0;
-                mshc1 = &dwmmc_1;
-                mshc2 = &dwmmc_2;
-                mshc3 = &dwmmc_3;
+                mshc0 = &mmc_0;
+                mshc1 = &mmc_1;
+                mshc2 = &mmc_2;
+                mshc3 = &mmc_3;
                 i2c0 = &i2c_0;
                 i2c1 = &i2c_1;
                 i2c2 = &i2c_2;
@@ -60,11 +60,13 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
+                        clock-frequency = <1700000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
+                        clock-frequency = <1700000000>;
                 };
         };
 
@@ -88,6 +90,8 @@
                 compatible = "samsung,exynos5250-audss-clock";
                 reg = <0x03810000 0x0C>;
                 #clock-cells = <1>;
+                clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
+                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
         };
 
         timer {
@@ -242,6 +246,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c0_bus>;
+                status = "disabled";
         };
 
         i2c_1: i2c@12C70000 {
@@ -254,6 +259,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c1_bus>;
+                status = "disabled";
         };
 
         i2c_2: i2c@12C80000 {
@@ -266,6 +272,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c2_bus>;
+                status = "disabled";
         };
 
         i2c_3: i2c@12C90000 {
@@ -278,6 +285,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c3_bus>;
+                status = "disabled";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -290,6 +298,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c4_bus>;
+                status = "disabled";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -302,6 +311,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c5_bus>;
+                status = "disabled";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -314,6 +324,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c6_bus>;
+                status = "disabled";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -326,6 +337,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c7_bus>;
+                status = "disabled";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -336,6 +348,7 @@
                 #size-cells = <0>;
                 clocks = <&clock 302>;
                 clock-names = "i2c";
+                status = "disabled";
         };
 
         i2c@121D0000 {
@@ -345,10 +358,12 @@
                 #size-cells = <0>;
                 clocks = <&clock 288>;
                 clock-names = "i2c";
+                status = "disabled";
         };
 
         spi_0: spi@12d20000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d20000 0x100>;
                 interrupts = <0 66 0>;
                 dmas = <&pdma0 5
@@ -364,6 +379,7 @@
 
         spi_1: spi@12d30000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d30000 0x100>;
                 interrupts = <0 67 0>;
                 dmas = <&pdma1 5
@@ -379,6 +395,7 @@
 
         spi_2: spi@12d40000 {
                 compatible = "samsung,exynos4210-spi";
+                status = "disabled";
                 reg = <0x12d40000 0x100>;
                 interrupts = <0 68 0>;
                 dmas = <&pdma0 7
@@ -392,25 +409,43 @@
                 pinctrl-0 = <&spi2_bus>;
         };
 
-        dwmmc_0: dwmmc0@12200000 {
+        mmc_0: mmc@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12200000 0x1000>;
                 clocks = <&clock 280>, <&clock 139>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_1: dwmmc1@12210000 {
+        mmc_1: mmc@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12210000 0x1000>;
                 clocks = <&clock 281>, <&clock 140>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_2: dwmmc2@12220000 {
+        mmc_2: mmc@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 reg = <0x12220000 0x1000>;
                 clocks = <&clock 282>, <&clock 141>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
-        dwmmc_3: dwmmc3@12230000 {
+        mmc_3: mmc@12230000 {
                 compatible = "samsung,exynos5250-dw-mshc";
                 reg = <0x12230000 0x1000>;
                 interrupts = <0 78 0>;
@@ -418,6 +453,8 @@
                 #size-cells = <0>;
                 clocks = <&clock 283>, <&clock 142>;
                 clock-names = "biu", "ciu";
+                fifo-depth = <0x80>;
+                status = "disabled";
         };
 
         i2s0: i2s@03830000 {
@@ -526,6 +563,15 @@
                 };
         };
 
+        pwm: pwm@12dd0000 {
+                compatible = "samsung,exynos4210-pwm";
+                reg = <0x12dd0000 0x100>;
+                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+                #pwm-cells = <3>;
+                clocks = <&clock 311>;
+                clock-names = "timers";
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
new file mode 100644
index 000000000000..7340745ff979
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -0,0 +1,66 @@
+/*
+ * Samsung's Exynos5420 based Arndale Octa board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5420.dtsi"
+
+/ {
+        model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
+        compatible = "insignal,arndale-octa", "samsung,exynos5420";
+
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC3,115200";
+        };
+
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        mmc@12200000 {
+                status = "okay";
+                broken-cd;
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <0 4>;
+                samsung,dw-mshc-ddr-timing = <0 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        mmc@12220000 {
+                status = "okay";
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e695aba5f73c..e62c8eb57438 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -64,7 +64,7 @@
                         samsung,pins = "gpx0-7";
                         samsung,pin-function = <3>;
                         samsung,pin-pud = <0>;
-                        samaung,pin-drv = <0>;
+                        samsung,pin-drv = <0>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 79524c74c603..fb5a1e25c632 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
                 };
         };
 
+        mmc@12200000 {
+                status = "okay";
+                broken-cd;
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <0 4>;
+                samsung,dw-mshc-ddr-timing = <0 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        mmc@12220000 {
+                status = "okay";
+                supports-highspeed;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                };
+        };
+
         dp-controller@145B0000 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 09aa06cb3d3a..8db792b26f79 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
         compatible = "samsung,exynos5420";
 
         aliases {
+                mshc0 = &mmc_0;
+                mshc1 = &mmc_1;
+                mshc2 = &mmc_2;
                 pinctrl0 = &pinctrl_0;
                 pinctrl1 = &pinctrl_1;
                 pinctrl2 = &pinctrl_2;
@@ -31,6 +34,18 @@
                 i2c1 = &i2c_1;
                 i2c2 = &i2c_2;
                 i2c3 = &i2c_3;
+                i2c4 = &hsi2c_4;
+                i2c5 = &hsi2c_5;
+                i2c6 = &hsi2c_6;
+                i2c7 = &hsi2c_7;
+                i2c8 = &hsi2c_8;
+                i2c9 = &hsi2c_9;
+                i2c10 = &hsi2c_10;
+                gsc0 = &gsc_0;
+                gsc1 = &gsc_1;
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
         };
 
         cpus {
@@ -64,6 +79,34 @@
                         reg = <0x3>;
                         clock-frequency = <1800000000>;
                 };
+
+                cpu4: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu5: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu6: cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x102>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu7: cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x103>;
+                        clock-frequency = <1000000000>;
+                };
         };
 
         clock: clock-controller@10010000 {
@@ -76,8 +119,8 @@
                 compatible = "samsung,exynos5420-audss-clock";
                 reg = <0x03810000 0x0C>;
                 #clock-cells = <1>;
-                clocks = <&clock 148>;
-                clock-names = "sclk_audio";
+                clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
+                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
         };
 
         codec@11000000 {
@@ -88,13 +131,50 @@
                 clock-names = "mfc";
         };
 
+        mmc_0: mmc@12200000 {
+                compatible = "samsung,exynos5420-dw-mshc-smu";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12200000 0x2000>;
+                clocks = <&clock 351>, <&clock 132>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
+        mmc_1: mmc@12210000 {
+                compatible = "samsung,exynos5420-dw-mshc-smu";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12210000 0x2000>;
+                clocks = <&clock 352>, <&clock 133>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
+        mmc_2: mmc@12220000 {
+                compatible = "samsung,exynos5420-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x12220000 0x1000>;
+                clocks = <&clock 353>, <&clock 134>;
+                clock-names = "biu", "ciu";
+                fifo-depth = <0x40>;
+                status = "disabled";
+        };
+
         mct@101C0000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
                 interrupt-controller;
                 #interrups-cells = <1>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+                                <8>, <9>, <10>, <11>;
                 clocks = <&clock 1>, <&clock 315>;
                 clock-names = "fin_pll", "mct";
 
@@ -109,7 +189,11 @@
                                         <4 &gic 0 120 0>,
                                         <5 &gic 0 121 0>,
                                         <6 &gic 0 122 0>,
-                                        <7 &gic 0 123 0>;
+                                        <7 &gic 0 123 0>,
+                                        <8 &gic 0 128 0>,
+                                        <9 &gic 0 129 0>,
+                                        <10 &gic 0 130 0>,
+                                        <11 &gic 0 131 0>;
                 };
         };
 
@@ -190,6 +274,106 @@
                 status = "okay";
         };
 
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@121A0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121A0000 0x1000>;
+                        interrupts = <0 34 0>;
+                        clocks = <&clock 362>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
+                };
+
+                pdma1: pdma@121B0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121B0000 0x1000>;
+                        interrupts = <0 35 0>;
+                        clocks = <&clock 363>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
+                };
+
+                mdma0: mdma@10800000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x10800000 0x1000>;
+                        interrupts = <0 33 0>;
+                        clocks = <&clock 473>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
+                };
+
+                mdma1: mdma@11C10000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x11C10000 0x1000>;
+                        interrupts = <0 124 0>;
+                        clocks = <&clock 442>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
+                };
+        };
+
+        spi_0: spi@12d20000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d20000 0x100>;
+                interrupts = <0 66 0>;
+                dmas = <&pdma0 5
+                        &pdma0 4>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_bus>;
+                clocks = <&clock 271>, <&clock 135>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d30000 0x100>;
+                interrupts = <0 67 0>;
+                dmas = <&pdma1 5
+                        &pdma1 4>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_bus>;
+                clocks = <&clock 272>, <&clock 136>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d40000 0x100>;
+                interrupts = <0 68 0>;
+                dmas = <&pdma0 7
+                        &pdma0 6>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_bus>;
+                clocks = <&clock 273>, <&clock 137>;
+                clock-names = "spi", "spi_busclk0";
+                status = "disabled";
+        };
+
         serial@12C00000 {
                 clocks = <&clock 257>, <&clock 128>;
                 clock-names = "uart", "clk_uart_baud0";
@@ -210,6 +394,15 @@
                 clock-names = "uart", "clk_uart_baud0";
         };
 
+        pwm: pwm@12dd0000 {
+                compatible = "samsung,exynos4210-pwm";
+                reg = <0x12dd0000 0x100>;
+                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+                #pwm-cells = <3>;
+                clocks = <&clock 279>;
+                clock-names = "timers";
+        };
+
         dp_phy: video-phy@10040728 {
                 compatible = "samsung,exynos5250-dp-video-phy";
                 reg = <0x10040728 4>;
@@ -292,6 +485,97 @@
                 status = "disabled";
         };
 
+        hsi2c_4: i2c@12CA0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CA0000 0x1000>;
+                interrupts = <0 60 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c4_hs_bus>;
+                clocks = <&clock 265>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_5: i2c@12CB0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CB0000 0x1000>;
+                interrupts = <0 61 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c5_hs_bus>;
+                clocks = <&clock 266>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_6: i2c@12CC0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CC0000 0x1000>;
+                interrupts = <0 62 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c6_hs_bus>;
+                clocks = <&clock 267>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_7: i2c@12CD0000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12CD0000 0x1000>;
+                interrupts = <0 63 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c7_hs_bus>;
+                clocks = <&clock 268>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_8: i2c@12E00000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E00000 0x1000>;
+                interrupts = <0 87 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c8_hs_bus>;
+                clocks = <&clock 281>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_9: i2c@12E10000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E10000 0x1000>;
+                interrupts = <0 88 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c9_hs_bus>;
+                clocks = <&clock 282>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
+        hsi2c_10: i2c@12E20000 {
+                compatible = "samsung,exynos5-hsi2c";
+                reg = <0x12E20000 0x1000>;
+                interrupts = <0 203 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c10_hs_bus>;
+                clocks = <&clock 283>;
+                clock-names = "hsi2c";
+                status = "disabled";
+        };
+
         hdmi@14530000 {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;
@@ -310,4 +594,62 @@
                 clocks = <&clock 431>, <&clock 143>;
                 clock-names = "mixer", "sclk_hdmi";
         };
+
+        gsc_0: video-scaler@13e00000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e00000 0x1000>;
+                interrupts = <0 85 0>;
+                clocks = <&clock 465>;
+                clock-names = "gscl";
+                samsung,power-domain = <&gsc_pd>;
+        };
+
+        gsc_1: video-scaler@13e10000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e10000 0x1000>;
+                interrupts = <0 86 0>;
+                clocks = <&clock 466>;
+                clock-names = "gscl";
+                samsung,power-domain = <&gsc_pd>;
+        };
+
+        tmu_cpu0: tmu@10060000 {
+                compatible = "samsung,exynos5420-tmu";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 65 0>;
+                clocks = <&clock 318>;
+                clock-names = "tmu_apbif";
+        };
+
+        tmu_cpu1: tmu@10064000 {
+                compatible = "samsung,exynos5420-tmu";
+                reg = <0x10064000 0x100>;
+                interrupts = <0 183 0>;
+                clocks = <&clock 318>;
+                clock-names = "tmu_apbif";
+        };
+
+        tmu_cpu2: tmu@10068000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+                interrupts = <0 184 0>;
+                clocks = <&clock 318>, <&clock 318>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
+
+        tmu_cpu3: tmu@1006c000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+                interrupts = <0 185 0>;
+                clocks = <&clock 318>, <&clock 319>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
+
+        tmu_gpu: tmu@100a0000 {
+                compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+                interrupts = <0 215 0>;
+                clocks = <&clock 319>, <&clock 318>;
+                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 8da107088ce4..02a0a1226cef 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -29,7 +29,7 @@
                 #clock-cells = <1>;
         };
 
-        gic:interrupt-controller@2E0000 {
+        gic: interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts
new file mode 100644
index 000000000000..fe623928f687
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620-hi4511.dts
@@ -0,0 +1,649 @@
+/*
+ *  Copyright (C) 2012-2013 Linaro Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hi3620.dtsi"
+
+/ {
+        model = "Hisilicon Hi4511 Development Board";
+        compatible = "hisilicon,hi3620-hi4511";
+
+        chosen {
+                bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x20000000>;
+        };
+
+        amba {
+                dual_timer0: dual_timer@800000 {
+                        status = "ok";
+                };
+
+                uart0: uart@b00000 {    /* console */
+                        pinctrl-names = "default", "idle";
+                        pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+                        pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
+                        status = "ok";
+                };
+
+                uart1: uart@b01000 { /* modem */
+                        pinctrl-names = "default", "idle";
+                        pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+                        pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
+                        status = "ok";
+                };
+
+                uart2: uart@b02000 { /* audience */
+                        pinctrl-names = "default", "idle";
+                        pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+                        pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
+                        status = "ok";
+                };
+
+                uart3: uart@b03000 {
+                        pinctrl-names = "default", "idle";
+                        pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+                        pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
+                        status = "ok";
+                };
+
+                uart4: uart@b04000 {
+                        pinctrl-names = "default", "idle";
+                        pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+                        pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
+                        status = "ok";
+                };
+
+                pmx0: pinmux@803000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&board_pmx_pins>;
+
+                        board_pmx_pins: board_pmx_pins {
+                                pinctrl-single,pins = <
+                                        0x008 0x0       /* GPIO -- eFUSE_DOUT */
+                                        0x100 0x0       /* USIM_CLK & USIM_DATA (IOMG63) */
+                                >;
+                        };
+                        uart0_pmx_func: uart0_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0f0 0x0
+                                        0x0f4 0x0       /* UART0_RX & UART0_TX */
+                                >;
+                        };
+                        uart0_pmx_idle: uart0_pmx_idle {
+                                pinctrl-single,pins = <
+                                        /*0x0f0 0x1*/   /* UART0_CTS & UART0_RTS */
+                                        0x0f4 0x1       /* UART0_RX & UART0_TX */
+                                >;
+                        };
+                        uart1_pmx_func: uart1_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0f8 0x0       /* UART1_CTS & UART1_RTS (IOMG61) */
+                                        0x0fc 0x0       /* UART1_RX & UART1_TX (IOMG62) */
+                                >;
+                        };
+                        uart1_pmx_idle: uart1_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0f8 0x1       /* GPIO (IOMG61) */
+                                        0x0fc 0x1       /* GPIO (IOMG62) */
+                                >;
+                        };
+                        uart2_pmx_func: uart2_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x104 0x2       /* UART2_RXD (IOMG96) */
+                                        0x108 0x2       /* UART2_TXD (IOMG64) */
+                                >;
+                        };
+                        uart2_pmx_idle: uart2_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x104 0x1       /* GPIO (IOMG96) */
+                                        0x108 0x1       /* GPIO (IOMG64) */
+                                >;
+                        };
+                        uart3_pmx_func: uart3_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x160 0x2       /* UART3_CTS & UART3_RTS (IOMG85) */
+                                        0x164 0x2       /* UART3_RXD & UART3_TXD (IOMG86) */
+                                >;
+                        };
+                        uart3_pmx_idle: uart3_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x160 0x1       /* GPIO (IOMG85) */
+                                        0x164 0x1       /* GPIO (IOMG86) */
+                                >;
+                        };
+                        uart4_pmx_func: uart4_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x168 0x0       /* UART4_CTS & UART4_RTS (IOMG87) */
+                                        0x16c 0x0       /* UART4_RXD (IOMG88) */
+                                        0x170 0x0       /* UART4_TXD (IOMG93) */
+                                >;
+                        };
+                        uart4_pmx_idle: uart4_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x168 0x1       /* GPIO (IOMG87) */
+                                        0x16c 0x1       /* GPIO (IOMG88) */
+                                        0x170 0x1       /* GPIO (IOMG93) */
+                                >;
+                        };
+                        i2c0_pmx_func: i2c0_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0b4 0x0       /* I2C0_SCL & I2C0_SDA (IOMG45) */
+                                >;
+                        };
+                        i2c0_pmx_idle: i2c0_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0b4 0x1       /* GPIO (IOMG45) */
+                                >;
+                        };
+                        i2c1_pmx_func: i2c1_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0b8 0x0       /* I2C1_SCL & I2C1_SDA (IOMG46) */
+                                >;
+                        };
+                        i2c1_pmx_idle: i2c1_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0b8 0x1       /* GPIO (IOMG46) */
+                                >;
+                        };
+                        i2c2_pmx_func: i2c2_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x068 0x0       /* I2C2_SCL (IOMG26) */
+                                        0x06c 0x0       /* I2C2_SDA (IOMG27) */
+                                >;
+                        };
+                        i2c2_pmx_idle: i2c2_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x068 0x1       /* GPIO (IOMG26) */
+                                        0x06c 0x1       /* GPIO (IOMG27) */
+                                >;
+                        };
+                        i2c3_pmx_func: i2c3_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x050 0x2       /* I2C3_SCL (IOMG20) */
+                                        0x054 0x2       /* I2C3_SDA (IOMG21) */
+                                >;
+                        };
+                        i2c3_pmx_idle: i2c3_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x050 0x1       /* GPIO (IOMG20) */
+                                        0x054 0x1       /* GPIO (IOMG21) */
+                                >;
+                        };
+                        spi0_pmx_func: spi0_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0d4 0x0       /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
+                                        0x0d8 0x0       /* SPI0_CS0 (IOMG54) */
+                                        0x0dc 0x0       /* SPI0_CS1 (IOMG55) */
+                                        0x0e0 0x0       /* SPI0_CS2 (IOMG56) */
+                                        0x0e4 0x0       /* SPI0_CS3 (IOMG57) */
+                                >;
+                        };
+                        spi0_pmx_idle: spi0_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0d4 0x1       /* GPIO (IOMG53) */
+                                        0x0d8 0x1       /* GPIO (IOMG54) */
+                                        0x0dc 0x1       /* GPIO (IOMG55) */
+                                        0x0e0 0x1       /* GPIO (IOMG56) */
+                                        0x0e4 0x1       /* GPIO (IOMG57) */
+                                >;
+                        };
+                        spi1_pmx_func: spi1_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x184 0x0       /* SPI1_CLK/SPI1_DI (IOMG98) */
+                                        0x0e8 0x0       /* SPI1_DO (IOMG58) */
+                                        0x0ec 0x0       /* SPI1_CS (IOMG95) */
+                                >;
+                        };
+                        spi1_pmx_idle: spi1_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x184 0x1       /* GPIO (IOMG98) */
+                                        0x0e8 0x1       /* GPIO (IOMG58) */
+                                        0x0ec 0x1       /* GPIO (IOMG95) */
+                                >;
+                        };
+                        kpc_pmx_func: kpc_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x12c 0x0       /* KEY_IN0 (IOMG73) */
+                                        0x130 0x0       /* KEY_IN1 (IOMG74) */
+                                        0x134 0x0       /* KEY_IN2 (IOMG75) */
+                                        0x10c 0x0       /* KEY_OUT0 (IOMG65) */
+                                        0x110 0x0       /* KEY_OUT1 (IOMG66) */
+                                        0x114 0x0       /* KEY_OUT2 (IOMG67) */
+                                >;
+                        };
+                        kpc_pmx_idle: kpc_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x12c 0x1       /* GPIO (IOMG73) */
+                                        0x130 0x1       /* GPIO (IOMG74) */
+                                        0x134 0x1       /* GPIO (IOMG75) */
+                                        0x10c 0x1       /* GPIO (IOMG65) */
+                                        0x110 0x1       /* GPIO (IOMG66) */
+                                        0x114 0x1       /* GPIO (IOMG67) */
+                                >;
+                        };
+                        gpio_key_func: gpio_key_func {
+                                pinctrl-single,pins = <
+                                        0x10c 0x1       /* KEY_OUT0/GPIO (IOMG65) */
+                                        0x130 0x1       /* KEY_IN1/GPIO (IOMG74) */
+                                >;
+                        };
+                        emmc_pmx_func: emmc_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x030 0x2       /* eMMC_CMD/eMMC_CLK (IOMG12) */
+                                        0x018 0x0       /* NAND_CS3_N (IOMG6) */
+                                        0x024 0x0       /* NAND_BUSY2_N (IOMG8) */
+                                        0x028 0x0       /* NAND_BUSY3_N (IOMG9) */
+                                        0x02c 0x2       /* eMMC_DATA[0:7] (IOMG10) */
+                                >;
+                        };
+                        emmc_pmx_idle: emmc_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x030 0x0       /* GPIO (IOMG12) */
+                                        0x018 0x1       /* GPIO (IOMG6) */
+                                        0x024 0x1       /* GPIO (IOMG8) */
+                                        0x028 0x1       /* GPIO (IOMG9) */
+                                        0x02c 0x1       /* GPIO (IOMG10) */
+                                >;
+                        };
+                        sd_pmx_func: sd_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0bc 0x0       /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
+                                        0x0c0 0x0       /* SD_DATA3 (IOMG48) */
+                                >;
+                        };
+                        sd_pmx_idle: sd_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0bc 0x1       /* GPIO (IOMG47) */
+                                        0x0c0 0x1       /* GPIO (IOMG48) */
+                                >;
+                        };
+                        nand_pmx_func: nand_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x00c 0x0       /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
+                                        0x010 0x0       /* NAND_CS1_N (IOMG4) */
+                                        0x014 0x0       /* NAND_CS2_N (IOMG5) */
+                                        0x018 0x0       /* NAND_CS3_N (IOMG6) */
+                                        0x01c 0x0       /* NAND_BUSY0_N (IOMG94) */
+                                        0x020 0x0       /* NAND_BUSY1_N (IOMG7) */
+                                        0x024 0x0       /* NAND_BUSY2_N (IOMG8) */
+                                        0x028 0x0       /* NAND_BUSY3_N (IOMG9) */
+                                        0x02c 0x0       /* NAND_DATA[8:15] (IOMG10) */
+                                >;
+                        };
+                        nand_pmx_idle: nand_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x00c 0x1       /* GPIO (IOMG3) */
+                                        0x010 0x1       /* GPIO (IOMG4) */
+                                        0x014 0x1       /* GPIO (IOMG5) */
+                                        0x018 0x1       /* GPIO (IOMG6) */
+                                        0x01c 0x1       /* GPIO (IOMG94) */
+                                        0x020 0x1       /* GPIO (IOMG7) */
+                                        0x024 0x1       /* GPIO (IOMG8) */
+                                        0x028 0x1       /* GPIO (IOMG9) */
+                                        0x02c 0x1       /* GPIO (IOMG10) */
+                                >;
+                        };
+                        sdio_pmx_func: sdio_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0c4 0x0       /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
+                                >;
+                        };
+                        sdio_pmx_idle: sdio_pmx_idle {
+                                pinctrl-single,pins = <
+                                        0x0c4 0x1       /* GPIO (IOMG49) */
+                                >;
+                        };
+                        audio_out_pmx_func: audio_out_pmx_func {
+                                pinctrl-single,pins = <
+                                        0x0f0 0x1       /* GPIO (IOMG59), audio spk & earphone */
+                                >;
+                        };
+                };
+
+                pmx1: pinmux@803800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <   &board_pu_pins &board_pd_pins &board_pd_ps_pins
+                                        &board_np_pins &board_ps_pins &kpc_cfg_func
+                                        &audio_out_cfg_func>;
+                        board_pu_pins: board_pu_pins {
+                                pinctrl-single,pins = <
+                                        0x014 0         /* GPIO_158 (IOCFG2) */
+                                        0x018 0         /* GPIO_159 (IOCFG3) */
+                                        0x01c 0         /* BOOT_MODE0 (IOCFG4) */
+                                        0x020 0         /* BOOT_MODE1 (IOCFG5) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <1 1 0 1>;
+                        };
+                        board_pd_pins: board_pd_pins {
+                                pinctrl-single,pins = <
+                                        0x038 0         /* eFUSE_DOUT (IOCFG11) */
+                                        0x150 0         /* ISP_GPIO8 (IOCFG93) */
+                                        0x154 0         /* ISP_GPIO9 (IOCFG94) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        board_pd_ps_pins: board_pd_ps_pins {
+                                pinctrl-single,pins = <
+                                        0x2d8 0         /* CLK_OUT0 (IOCFG190) */
+                                        0x004 0         /* PMU_SPI_DATA (IOCFG192) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        board_np_pins: board_np_pins {
+                                pinctrl-single,pins = <
+                                        0x24c 0         /* KEYPAD_OUT7 (IOCFG155) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        board_ps_pins: board_ps_pins {
+                                pinctrl-single,pins = <
+                                        0x000 0         /* PMU_SPI_CLK (IOCFG191) */
+                                        0x008 0         /* PMU_SPI_CS_N (IOCFG193) */
+                                >;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        uart0_cfg_func: uart0_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x208 0         /* UART0_RXD (IOCFG138) */
+                                        0x20c 0         /* UART0_TXD (IOCFG139) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart0_cfg_idle: uart0_cfg_idle {
+                                pinctrl-single,pins = <
+                                        0x208 0         /* UART0_RXD (IOCFG138) */
+                                        0x20c 0         /* UART0_TXD (IOCFG139) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart1_cfg_func: uart1_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x210 0         /* UART1_CTS (IOCFG140) */
+                                        0x214 0         /* UART1_RTS (IOCFG141) */
+                                        0x218 0         /* UART1_RXD (IOCFG142) */
+                                        0x21c 0         /* UART1_TXD (IOCFG143) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart1_cfg_idle: uart1_cfg_idle {
+                                pinctrl-single,pins = <
+                                        0x210 0         /* UART1_CTS (IOCFG140) */
+                                        0x214 0         /* UART1_RTS (IOCFG141) */
+                                        0x218 0         /* UART1_RXD (IOCFG142) */
+                                        0x21c 0         /* UART1_TXD (IOCFG143) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart2_cfg_func: uart2_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x220 0         /* UART2_CTS (IOCFG144) */
+                                        0x224 0         /* UART2_RTS (IOCFG145) */
+                                        0x228 0         /* UART2_RXD (IOCFG146) */
+                                        0x22c 0         /* UART2_TXD (IOCFG147) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart2_cfg_idle: uart2_cfg_idle {
+                                pinctrl-single,pins = <
+                                        0x220 0         /* GPIO (IOCFG144) */
+                                        0x224 0         /* GPIO (IOCFG145) */
+                                        0x228 0         /* GPIO (IOCFG146) */
+                                        0x22c 0         /* GPIO (IOCFG147) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart3_cfg_func: uart3_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x294 0         /* UART3_CTS (IOCFG173) */
+                                        0x298 0         /* UART3_RTS (IOCFG174) */
+                                        0x29c 0         /* UART3_RXD (IOCFG175) */
+                                        0x2a0 0         /* UART3_TXD (IOCFG176) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart3_cfg_idle: uart3_cfg_idle {
+                                pinctrl-single,pins = <
+                                        0x294 0         /* UART3_CTS (IOCFG173) */
+                                        0x298 0         /* UART3_RTS (IOCFG174) */
+                                        0x29c 0         /* UART3_RXD (IOCFG175) */
+                                        0x2a0 0         /* UART3_TXD (IOCFG176) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        uart4_cfg_func: uart4_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x2a4 0         /* UART4_CTS (IOCFG177) */
+                                        0x2a8 0         /* UART4_RTS (IOCFG178) */
+                                        0x2ac 0         /* UART4_RXD (IOCFG179) */
+                                        0x2b0 0         /* UART4_TXD (IOCFG180) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        i2c0_cfg_func: i2c0_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x17c 0         /* I2C0_SCL (IOCFG103) */
+                                        0x180 0         /* I2C0_SDA (IOCFG104) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        i2c1_cfg_func: i2c1_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x184 0         /* I2C1_SCL (IOCFG105) */
+                                        0x188 0         /* I2C1_SDA (IOCFG106) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        i2c2_cfg_func: i2c2_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x118 0         /* I2C2_SCL (IOCFG79) */
+                                        0x11c 0         /* I2C2_SDA (IOCFG80) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        i2c3_cfg_func: i2c3_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x100 0         /* I2C3_SCL (IOCFG73) */
+                                        0x104 0         /* I2C3_SDA (IOCFG74) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        spi0_cfg_func1: spi0_cfg_func1 {
+                                pinctrl-single,pins = <
+                                        0x1d4 0         /* SPI0_CLK (IOCFG125) */
+                                        0x1d8 0         /* SPI0_DI (IOCFG126) */
+                                        0x1dc 0         /* SPI0_DO (IOCFG127) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        spi0_cfg_func2: spi0_cfg_func2 {
+                                pinctrl-single,pins = <
+                                        0x1e0 0         /* SPI0_CS0 (IOCFG128) */
+                                        0x1e4 0         /* SPI0_CS1 (IOCFG129) */
+                                        0x1e8 0         /* SPI0_CS2 (IOCFG130 */
+                                        0x1ec 0         /* SPI0_CS3 (IOCFG131) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <1 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        spi1_cfg_func1: spi1_cfg_func1 {
+                                pinctrl-single,pins = <
+                                        0x1f0 0         /* SPI1_CLK (IOCFG132) */
+                                        0x1f4 0         /* SPI1_DI (IOCFG133) */
+                                        0x1f8 0         /* SPI1_DO (IOCFG134) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        spi1_cfg_func2: spi1_cfg_func2 {
+                                pinctrl-single,pins = <
+                                        0x1fc 0         /* SPI1_CS (IOCFG135) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <1 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        kpc_cfg_func: kpc_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x250 0         /* KEY_IN0 (IOCFG156) */
+                                        0x254 0         /* KEY_IN1 (IOCFG157) */
+                                        0x258 0         /* KEY_IN2 (IOCFG158) */
+                                        0x230 0         /* KEY_OUT0 (IOCFG148) */
+                                        0x234 0         /* KEY_OUT1 (IOCFG149) */
+                                        0x238 0         /* KEY_OUT2 (IOCFG150) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                        emmc_cfg_func: emmc_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x0ac 0         /* eMMC_CMD (IOCFG40) */
+                                        0x0b0 0         /* eMMC_CLK (IOCFG41) */
+                                        0x058 0         /* NAND_CS3_N (IOCFG19) */
+                                        0x064 0         /* NAND_BUSY2_N (IOCFG22) */
+                                        0x068 0         /* NAND_BUSY3_N (IOCFG23) */
+                                        0x08c 0         /* NAND_DATA8 (IOCFG32) */
+                                        0x090 0         /* NAND_DATA9 (IOCFG33) */
+                                        0x094 0         /* NAND_DATA10 (IOCFG34) */
+                                        0x098 0         /* NAND_DATA11 (IOCFG35) */
+                                        0x09c 0         /* NAND_DATA12 (IOCFG36) */
+                                        0x0a0 0         /* NAND_DATA13 (IOCFG37) */
+                                        0x0a4 0         /* NAND_DATA14 (IOCFG38) */
+                                        0x0a8 0         /* NAND_DATA15 (IOCFG39) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <1 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        sd_cfg_func1: sd_cfg_func1 {
+                                pinctrl-single,pins = <
+                                        0x18c 0         /* SD_CLK (IOCFG107) */
+                                        0x190 0         /* SD_CMD (IOCFG108) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        sd_cfg_func2: sd_cfg_func2 {
+                                pinctrl-single,pins = <
+                                        0x194 0         /* SD_DATA0 (IOCFG109) */
+                                        0x198 0         /* SD_DATA1 (IOCFG110) */
+                                        0x19c 0         /* SD_DATA2 (IOCFG111) */
+                                        0x1a0 0         /* SD_DATA3 (IOCFG112) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x70 0xf0>;
+                        };
+                        nand_cfg_func1: nand_cfg_func1 {
+                                pinctrl-single,pins = <
+                                        0x03c 0         /* NAND_ALE (IOCFG12) */
+                                        0x040 0         /* NAND_CLE (IOCFG13) */
+                                        0x06c 0         /* NAND_DATA0 (IOCFG24) */
+                                        0x070 0         /* NAND_DATA1 (IOCFG25) */
+                                        0x074 0         /* NAND_DATA2 (IOCFG26) */
+                                        0x078 0         /* NAND_DATA3 (IOCFG27) */
+                                        0x07c 0         /* NAND_DATA4 (IOCFG28) */
+                                        0x080 0         /* NAND_DATA5 (IOCFG29) */
+                                        0x084 0         /* NAND_DATA6 (IOCFG30) */
+                                        0x088 0         /* NAND_DATA7 (IOCFG31) */
+                                        0x08c 0         /* NAND_DATA8 (IOCFG32) */
+                                        0x090 0         /* NAND_DATA9 (IOCFG33) */
+                                        0x094 0         /* NAND_DATA10 (IOCFG34) */
+                                        0x098 0         /* NAND_DATA11 (IOCFG35) */
+                                        0x09c 0         /* NAND_DATA12 (IOCFG36) */
+                                        0x0a0 0         /* NAND_DATA13 (IOCFG37) */
+                                        0x0a4 0         /* NAND_DATA14 (IOCFG38) */
+                                        0x0a8 0         /* NAND_DATA15 (IOCFG39) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        nand_cfg_func2: nand_cfg_func2 {
+                                pinctrl-single,pins = <
+                                        0x044 0         /* NAND_RE_N (IOCFG14) */
+                                        0x048 0         /* NAND_WE_N (IOCFG15) */
+                                        0x04c 0         /* NAND_CS0_N (IOCFG16) */
+                                        0x050 0         /* NAND_CS1_N (IOCFG17) */
+                                        0x054 0         /* NAND_CS2_N (IOCFG18) */
+                                        0x058 0         /* NAND_CS3_N (IOCFG19) */
+                                        0x05c 0         /* NAND_BUSY0_N (IOCFG20) */
+                                        0x060 0         /* NAND_BUSY1_N (IOCFG21) */
+                                        0x064 0         /* NAND_BUSY2_N (IOCFG22) */
+                                        0x068 0         /* NAND_BUSY3_N (IOCFG23) */
+                                >;
+                                pinctrl-single,bias-pulldown = <0 2 0 2>;
+                                pinctrl-single,bias-pullup = <1 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        sdio_cfg_func: sdio_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x1a4 0         /* SDIO0_CLK (IOCG113) */
+                                        0x1a8 0         /* SDIO0_CMD (IOCG114) */
+                                        0x1ac 0         /* SDIO0_DATA0 (IOCG115) */
+                                        0x1b0 0         /* SDIO0_DATA1 (IOCG116) */
+                                        0x1b4 0         /* SDIO0_DATA2 (IOCG117) */
+                                        0x1b8 0         /* SDIO0_DATA3 (IOCG118) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                                pinctrl-single,drive-strength = <0x30 0xf0>;
+                        };
+                        audio_out_cfg_func: audio_out_cfg_func {
+                                pinctrl-single,pins = <
+                                        0x200 0         /* GPIO (IOCFG136) */
+                                        0x204 0         /* GPIO (IOCFG137) */
+                                >;
+                                pinctrl-single,bias-pulldown = <2 2 0 2>;
+                                pinctrl-single,bias-pullup = <0 1 0 1>;
+                        };
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                call {
+                        label = "call";
+                        gpios = <&gpio17 2 0>;
+                        linux,code = <169>;     /* KEY_PHONE */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
new file mode 100644
index 000000000000..ab1116d086be
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -0,0 +1,565 @@
+/*
+ * Hisilicon Ltd. Hi3620 SoC
+ *
+ * Copyright (C) 2012-2013 Hisilicon Ltd.
+ * Copyright (C) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/hi3620-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+        };
+
+        pclk: clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <26000000>;
+                clock-output-names = "apb_pclk";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        amba {
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0 0xfc000000 0x2000000>;
+
+                L2: l2-cache {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfc10000 0x100000>;
+                        interrupts = <0 15 4>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                gic: interrupt-controller@1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        /* gic dist base, gic cpu base */
+                        reg = <0x1000 0x1000>, <0x100 0x100>;
+                };
+
+                sysctrl: system-controller@802000 {
+                        compatible = "hisilicon,sysctrl";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x802000 0x1000>;
+                        reg = <0x802000 0x1000>;
+
+                        smp-offset = <0x31c>;
+                        resume-offset = <0x308>;
+                        reboot-offset = <0x4>;
+
+                        clock: clock@0 {
+                                compatible = "hisilicon,hi3620-clock";
+                                reg = <0 0x10000>;
+                                #clock-cells = <1>;
+                        };
+                };
+
+                dual_timer0: dual_timer@800000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x800000 0x1000>;
+                        /* timer00 & timer01 */
+                        interrupts = <0 0 4>, <0 1 4>;
+                        clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dual_timer1: dual_timer@801000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x801000 0x1000>;
+                        /* timer10 & timer11 */
+                        interrupts = <0 2 4>, <0 3 4>;
+                        clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dual_timer2: dual_timer@a01000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xa01000 0x1000>;
+                        /* timer20 & timer21 */
+                        interrupts = <0 4 4>, <0 5 4>;
+                        clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dual_timer3: dual_timer@a02000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xa02000 0x1000>;
+                        /* timer30 & timer31 */
+                        interrupts = <0 6 4>, <0 7 4>;
+                        clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                dual_timer4: dual_timer@a03000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0xa03000 0x1000>;
+                        /* timer40 & timer41 */
+                        interrupts = <0 96 4>, <0 97 4>;
+                        clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                timer5: timer@600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x600 0x20>;
+                        interrupts = <1 13 0xf01>;
+                };
+
+                uart0: uart@b00000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xb00000 0x1000>;
+                        interrupts = <0 20 4>;
+                        clocks = <&clock HI3620_UARTCLK0>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart1: uart@b01000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xb01000 0x1000>;
+                        interrupts = <0 21 4>;
+                        clocks = <&clock HI3620_UARTCLK1>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart2: uart@b02000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xb02000 0x1000>;
+                        interrupts = <0 22 4>;
+                        clocks = <&clock HI3620_UARTCLK2>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart3: uart@b03000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xb03000 0x1000>;
+                        interrupts = <0 23 4>;
+                        clocks = <&clock HI3620_UARTCLK3>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart4: uart@b04000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xb04000 0x1000>;
+                        interrupts = <0 24 4>;
+                        clocks = <&clock HI3620_UARTCLK4>;
+                        clock-names = "apb_pclk";
+                        status = "disabled";
+                };
+
+                gpio0: gpio@806000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x806000 0x1000>;
+                        interrupts = <0 64 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
+                                        &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK0>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio1: gpio@807000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x807000 0x1000>;
+                        interrupts = <0 65 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+                                        &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
+                                        &pmx0 6 5 1 &pmx0 7 6 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK1>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio2: gpio@808000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x808000 0x1000>;
+                        interrupts = <0 66 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
+                                        &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
+                                        &pmx0 6 3 1 &pmx0 7 3 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK2>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio3: gpio@809000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x809000 0x1000>;
+                        interrupts = <0 67 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
+                                        &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
+                                        &pmx0 6 11 1 &pmx0 7 11 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK3>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio4: gpio@80a000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80a000 0x1000>;
+                        interrupts = <0 68 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
+                                        &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
+                                        &pmx0 6 13 1 &pmx0 7 13 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK4>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio5: gpio@80b000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80b000 0x1000>;
+                        interrupts = <0 69 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
+                                        &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
+                                        &pmx0 6 16 1 &pmx0 7 16 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK5>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio6: gpio@80c000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80c000 0x1000>;
+                        interrupts = <0 70 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
+                                        &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
+                                        &pmx0 6 18 1 &pmx0 7 19 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK6>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio7: gpio@80d000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80d000 0x1000>;
+                        interrupts = <0 71 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
+                                        &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
+                                        &pmx0 6 25 1 &pmx0 7 26 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK7>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio8: gpio@80e000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80e000 0x1000>;
+                        interrupts = <0 72 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
+                                        &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
+                                        &pmx0 6 33 1 &pmx0 7 34 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK8>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio9: gpio@80f000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x80f000 0x1000>;
+                        interrupts = <0 73 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
+                                        &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
+                                        &pmx0 6 41 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK9>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio10: gpio@810000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x810000 0x1000>;
+                        interrupts = <0 74 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
+                                        &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK10>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio11: gpio@811000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x811000 0x1000>;
+                        interrupts = <0 75 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
+                                        &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
+                                        &pmx0 6 49 1 &pmx0 7 49 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK11>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio12: gpio@812000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x812000 0x1000>;
+                        interrupts = <0 76 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
+                                        &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
+                                        &pmx0 6 51 1 &pmx0 7 52 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK12>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio13: gpio@813000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x813000 0x1000>;
+                        interrupts = <0 77 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
+                                        &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
+                                        &pmx0 6 55 1 &pmx0 7 56 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK13>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio14: gpio@814000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x814000 0x1000>;
+                        interrupts = <0 78 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
+                                        &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
+                                        &pmx0 6 60 1 &pmx0 7 61 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK14>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio15: gpio@815000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x815000 0x1000>;
+                        interrupts = <0 79 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
+                                        &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
+                                        &pmx0 6 64 1 &pmx0 7 65 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK15>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio16: gpio@816000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x816000 0x1000>;
+                        interrupts = <0 80 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
+                                        &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
+                                        &pmx0 6 72 1 &pmx0 7 73 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK16>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio17: gpio@817000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x817000 0x1000>;
+                        interrupts = <0 81 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
+                                        &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
+                                        &pmx0 6 80 1 &pmx0 7 81 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK17>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio18: gpio@818000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x818000 0x1000>;
+                        interrupts = <0 82 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
+                                        &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
+                                        &pmx0 6 86 1 &pmx0 7 87 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK18>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio19: gpio@819000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x819000 0x1000>;
+                        interrupts = <0 83 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
+                                        &pmx0 3 88 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK19>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio20: gpio@81a000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x81a000 0x1000>;
+                        interrupts = <0 84 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
+                                        &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK20>;
+                        clock-names = "apb_pclk";
+                };
+
+                gpio21: gpio@81b000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x81b000 0x1000>;
+                        interrupts = <0 85 0x4>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&clock HI3620_GPIOCLK21>;
+                        clock-names = "apb_pclk";
+                };
+
+                pmx0: pinmux@803000 {
+                        compatible = "pinctrl-single";
+                        reg = <0x803000 0x188>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        #gpio-range-cells = <3>;
+                        ranges;
+
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <7>;
+                        /* pin base, nr pins & gpio function */
+                        pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+                                                &range 12 1 0 &range 13 29 1
+                                                &range 43 1 0 &range 44 49 1
+                                                &range 94 1 1 &range 96 2 1>;
+
+                        range: gpio-range {
+                                #pinctrl-single,gpio-range-cells = <3>;
+                        };
+                };
+
+                pmx1: pinmux@803800 {
+                        compatible = "pinconf-single";
+                        reg = <0x803800 0x2dc>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pinctrl-single,register-width = <32>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index c96ceaef7ddf..581b75433be6 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -337,8 +337,10 @@
                         };
 
                         dcp@80028000 {
+                                compatible = "fsl,imx23-dcp";
                                 reg = <0x80028000 0x2000>;
-                                status = "disabled";
+                                interrupts = <53 54>;
+                                status = "okay";
                         };
 
                         pxp@8002a000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index cda19c8b0a47..f8e9b20f6982 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -813,9 +813,10 @@
                         };
 
                         dcp: dcp@80028000 {
+                                compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
                                 reg = <0x80028000 0x2000>;
                                 interrupts = <52 53 54>;
-                                compatible = "fsl-dcp";
+                                status = "okay";
                         };
 
                         pxp: pxp@8002a000 {
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
new file mode 100644
index 000000000000..58aa8f2b0f26
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Russell King
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-cubox-i.dtsi"
+
+/ {
+        model = "SolidRun Cubox-i Solo/DualLite";
+        compatible = "solidrun,cubox-i/dl", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
new file mode 100644
index 000000000000..fd8fc7cd53f3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2013,2014 Russell King
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+        model = "SolidRun HummingBoard DL/Solo";
+        compatible = "solidrun,hummingboard", "fsl,imx6dl";
+
+        ir_recv: ir-receiver {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio1 2 1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                reg_usbh1_vbus: usb-h1-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio1 0 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+
+                reg_usbotg_vbus: usb-otg-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio3 22 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
+
+        codec: spdif-transmitter {
+                compatible = "linux,spdif-dit";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_spdif>;
+        };
+
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif";
+                model = "imx-spdif";
+                /* IMX6 doesn't implement this yet */
+                spdif-controller = <&spdif>;
+                spdif-out;
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
+
+        /*
+         * Not fitted on Carrier-1 board... yet
+        status = "okay";
+
+        rtc: pcf8523@68 {
+                compatible = "nxp,pcf8523";
+                reg = <0x68>;
+        };
+         */
+};
+
+&iomuxc {
+        hummingboard {
+                pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
+                                MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
+                        >;
+                };
+
+                pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+                        >;
+                };
+
+                pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+                        >;
+                };
+
+                pinctrl_hummingboard_spdif: hummingboard-spdif {
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                };
+
+                pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
+                        fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
+                };
+
+                pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
+                        fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
+                };
+
+                pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04    0x1f071
+                        >;
+                };
+
+                pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+                        >;
+                };
+        };
+};
+
+&spdif {
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usbh1_vbus>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &pinctrl_hummingboard_usdhc2_aux
+                &pinctrl_hummingboard_usdhc2
+        >;
+        vmmc-supply = <&reg_3p3v>;
+        cd-gpios = <&gpio1 4 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
new file mode 100644
index 000000000000..bc5f31e3e892
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2014 Russell King
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-cubox-i.dtsi"
+
+/ {
+        model = "SolidRun Cubox-i Dual/Quad";
+        compatible = "solidrun,cubox-i/q", "fsl,imx6q";
+};
+
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
new file mode 100644
index 000000000000..64daa3b311f6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2014 Russell King
+ */
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+        ir_recv: ir-receiver {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio3 9 1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_cubox_i_ir>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                reg_usbh1_vbus: usb-h1-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio1 0 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+
+                reg_usbotg_vbus: usb-otg-vbus {
+                        compatible = "regulator-fixed";
+                        enable-active-high;
+                        gpio = <&gpio3 22 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
+
+        codec: spdif-transmitter {
+                compatible = "linux,spdif-dit";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_cubox_i_spdif>;
+        };
+
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif";
+                model = "imx-spdif";
+                /* IMX6 doesn't implement this yet */
+                spdif-controller = <&spdif>;
+                spdif-out;
+        };
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_i2c3>;
+
+        status = "okay";
+
+        rtc: pcf8523@68 {
+                compatible = "nxp,pcf8523";
+                reg = <0x68>;
+        };
+};
+
+&iomuxc {
+        cubox_i {
+                pinctrl_cubox_i_i2c3: cubox-i-i2c3 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                        >;
+                };
+
+                pinctrl_cubox_i_ir: cubox-i-ir {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
+                        >;
+                };
+
+                pinctrl_cubox_i_spdif: cubox-i-spdif {
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                };
+
+                pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
+                        fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
+                };
+
+                pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
+                        fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
+                };
+
+                pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04    0x1f071
+                                MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071
+                        >;
+                };
+
+                pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+                        >;
+                };
+        };
+};
+
+&spdif {
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usbh1_vbus>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
+        vmmc-supply = <&reg_3p3v>;
+        cd-gpios = <&gpio1 4 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
new file mode 100644
index 000000000000..a3cb2fff8f61
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013,2014 Russell King
+ *
+ * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
+ * MicroSOM.
+ */
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+        phy-mode = "rgmii";
+        phy-reset-duration = <2>;
+        phy-reset-gpios = <&gpio4 15 0>;
+        status = "okay";
+};
+
+&iomuxc {
+        enet {
+                pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                /* AR8035 reset */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x130b0
+                                /* AR8035 interrupt */
+                                MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x80000000
+                                /* GPIO16 -> AR8035 25MHz */
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0xc0000000
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x80000000
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1
+                                /* AR8035 pin strapping: IO voltage: pull up */
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                /* AR8035 pin strapping: PHYADDR#0: pull down */
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x130b0
+                                /* AR8035 pin strapping: PHYADDR#1: pull down */
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x130b0
+                                /* AR8035 pin strapping: MODE#1: pull up */
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                /* AR8035 pin strapping: MODE#3: pull up */
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                /* AR8035 pin strapping: MODE#0: pull down */
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0
+
+                                /*
+                                 * As the RMII pins are also connected to RGMII
+                                 * so that an AR8030 can be placed, set these
+                                 * to high-z with the same pulls as above.
+                                 * Use the GPIO settings to avoid changing the
+                                 * input select registers.
+                                 */
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x03000
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x03000
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x03000
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
new file mode 100644
index 000000000000..d729d0b15f25
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013,2014 Russell King
+ */
+
+&iomuxc {
+        microsom {
+                pinctrl_microsom_uart1: microsom-uart1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+
+                pinctrl_microsom_usbotg: microsom-usbotg {
+                        /*
+                         * Similar to pinctrl_usbotg_2, but we want it
+                         * pulled down for a fixed host connection.
+                         */
+                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                };
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_microsom_uart1>;
+        status = "okay";
+};
+
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_microsom_usbotg>;
+};
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 0f06f8687b0b..88e3d477bf16 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -10,6 +10,11 @@
                 reg = <0x10000000 0x200>;
         };
 
+        ebi@12000000 {
+                compatible = "arm,external-bus-interface";
+                reg = <0x12000000 0x100>;
+        };
+
         timer@13000000 {
                 reg = <0x13000000 0x100>;
                 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 7deb3a3182b4..a21c17de9a5e 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -47,8 +47,11 @@
                 valid-mask = <0x00000007>;
         };
 
+        /* The SIC is cascaded off IRQ 26 on the PIC */
         sic: sic@ca000000 {
                 compatible = "arm,versatile-fpga-irq";
+                interrupt-parent = <&pic>;
+                interrupts = <26>;
                 #interrupt-cells = <1>;
                 interrupt-controller;
                 reg = <0xca000000 0x100>;
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
new file mode 100644
index 000000000000..eaefdfef65c3
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone.dtsi"
+
+/ {
+        compatible =  "ti,keystone-evm";
+
+        soc {
+                clock {
+                        refclksys: refclksys {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <122880000>;
+                                clock-output-names = "refclk-sys";
+                        };
+
+                        refclkpass: refclkpass {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <122880000>;
+                                clock-output-names = "refclk-pass";
+                        };
+
+                        refclkarm: refclkarm {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <125000000>;
+                                clock-output-names = "refclk-arm";
+                        };
+
+                        refclkddr3a: refclkddr3a {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-ddr3a";
+                        };
+
+                        refclkddr3b: refclkddr3b {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-ddr3b";
+                        };
+                };
+        };
+};
+
+&usb_phy {
+        status = "okay";
+};
+
+&usb {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index d6713b113258..2363593e1050 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,17 +13,10 @@ clocks {
         #size-cells = <1>;
         ranges;
 
-        refclkmain: refclkmain {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <122880000>;
-                clock-output-names = "refclk-main";
-        };
-
         mainpllclk: mainpllclk@2310110 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,main-pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclksys>;
                 reg = <0x02620350 4>, <0x02310110 4>;
                 reg-names = "control", "multiplier";
                 fixed-postdiv = <2>;
@@ -32,47 +25,43 @@ clocks {
         papllclk: papllclk@2620358 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkpass>;
                 clock-output-names = "pa-pll-clk";
                 reg = <0x02620358 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
-        ddr3allclk: ddr3apllclk@2620360 {
+        ddr3apllclk: ddr3apllclk@2620360 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkddr3a>;
                 clock-output-names = "ddr-3a-pll-clk";
                 reg = <0x02620360 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
-        ddr3bllclk: ddr3bpllclk@2620368 {
+        ddr3bpllclk: ddr3bpllclk@2620368 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkddr3b>;
                 clock-output-names = "ddr-3b-pll-clk";
                 reg = <0x02620368 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
         armpllclk: armpllclk@2620370 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkmain>;
+                clocks = <&refclkarm>;
                 clock-output-names = "arm-pll-clk";
                 reg = <0x02620370 4>;
                 reg-names = "control";
-                fixed-postdiv = <6>;
         };
 
         mainmuxclk: mainmuxclk@2310108 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,pll-mux-clock";
-                clocks = <&mainpllclk>, <&refclkmain>;
+                clocks = <&mainpllclk>, <&refclksys>;
                 reg = <0x02310108 4>;
                 bit-shift = <23>;
                 bit-mask = <1>;
@@ -135,6 +124,15 @@ clocks {
                 clock-output-names = "chipclk13";
         };
 
+        paclk13: paclk13 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&papllclk>;
+                clock-div = <3>;
+                clock-mult = <1>;
+                clock-output-names = "paclk13";
+        };
+
         chipclk14: chipclk14 {
                 #clock-cells = <0>;
                 compatible = "fixed-factor-clock";
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dtsi
index 100bdf52b847..b4202907a27b 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -6,14 +6,12 @@
  * published by the Free Software Foundation.
  */
 
-/dts-v1/;
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
 / {
         model = "Texas Instruments Keystone 2 SoC";
-        compatible =  "ti,keystone-evm";
         #address-cells = <2>;
         #size-cells = <2>;
         interrupt-parent = <&gic>;
@@ -64,7 +62,11 @@
                 #address-cells = <1>;
                 interrupt-controller;
                 reg = <0x0 0x02561000 0x0 0x1000>,
-                      <0x0 0x02562000 0x0 0x2000>;
+                      <0x0 0x02562000 0x0 0x2000>,
+                      <0x0 0x02564000 0x0 0x1000>,
+                      <0x0 0x02566000 0x0 0x2000>;
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+                                IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer {
@@ -179,5 +181,32 @@
                         interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
                         clocks = <&clkspi>;
                 };
+
+                usb_phy: usb_phy@2620738 {
+                        compatible = "ti,keystone-usbphy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x2620738 32>;
+                        status = "disabled";
+                };
+
+                usb: usb@2680000 {
+                        compatible = "ti,keystone-dwc3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x2680000 0x10000>;
+                        clocks = <&clkusb>;
+                        clock-names = "usb";
+                        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                        ranges;
+                        status = "disabled";
+
+                        dwc3@2690000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x2690000 0x70000>;
+                                interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                                usb-phy = <&usb_phy>, <&usb_phy>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
new file mode 100644
index 000000000000..3916937d6818
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -0,0 +1,107 @@
+/ {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        compatible = "marvell,88f6192-pinctrl";
+                        reg = <0x10000 0x20>;
+
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                               "mpp4", "mpp5", "mpp18",
+                                               "mpp19";
+                                marvell,function = "nand";
+                        };
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins = "mpp5", "mpp21", "mpp23";
+                                marvell,function = "sata0";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins = "mpp4", "mpp20", "mpp22";
+                                marvell,function = "sata1";
+                        };
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                        pmx_sdio: pmx-sdio {
+                                marvell,pins = "mpp12", "mpp13", "mpp14",
+                                               "mpp15", "mpp16", "mpp17";
+                                marvell,function = "sdio";
+                        };
+                };
+
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 650ef30e1856..416d96e1302f 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -89,6 +89,8 @@
                         interrupts = <21>;
                         clocks = <&gate_clk 14>, <&gate_clk 15>;
                         clock-names = "0", "1";
+                        phys = <&sata_phy0>, <&sata_phy1>;
+                        phy-names = "port0", "port1";
                         status = "disabled";
                 };
 
@@ -97,6 +99,8 @@
                         reg = <0x90000 0x200>;
                         interrupts = <28>;
                         clocks = <&gate_clk 4>;
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
                         bus-width = <4>;
                         cap-sdio-irq;
                         cap-sd-highspeed;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 3933a331ddc2..2902e0d7971d 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -104,6 +104,12 @@
                         };
                 };
 
+                thermal@10078 {
+                        compatible = "marvell,kirkwood-thermal";
+                        reg = <0x10078 0x4>;
+                        status = "okay";
+                };
+
                 rtc@10300 {
                         compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                         reg = <0x10300 0x20>;
@@ -111,12 +117,25 @@
                         clocks = <&gate_clk 7>;
                 };
 
+                i2c@11100 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11100 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <32>;
+                        clock-frequency = <100000>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
+                };
+
                 sata@80000 {
                         compatible = "marvell,orion-sata";
                         reg = <0x80000 0x5000>;
                         interrupts = <21>;
                         clocks = <&gate_clk 14>, <&gate_clk 15>;
                         clock-names = "0", "1";
+                        phys = <&sata_phy0>, <&sata_phy1>;
+                        phy-names = "port0", "port1";
                         status = "disabled";
                 };
 
@@ -125,29 +144,13 @@
                         reg = <0x90000 0x200>;
                         interrupts = <28>;
                         clocks = <&gate_clk 4>;
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
                         bus-width = <4>;
                         cap-sdio-irq;
                         cap-sd-highspeed;
                         cap-mmc-highspeed;
                         status = "disabled";
                 };
-
-                thermal@10078 {
-                        compatible = "marvell,kirkwood-thermal";
-                        reg = <0x10078 0x4>;
-                        status = "okay";
-                };
-
-                i2c@11100 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11100 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <32>;
-                        clock-frequency = <100000>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
-                };
-
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 142b9cd3b454..0e06fd3cee4d 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -66,8 +66,8 @@
 
                 button@1 {
                         label = "Power push button";
-                        linux,code = <116>;
-                        gpios = <&gpio0 16 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -76,17 +76,17 @@
 
                 red-fail {
                         label = "cloudbox:red:fail";
-                        gpios = <&gpio0 14 0>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
                 };
                 blue-sata {
                         label = "cloudbox:blue:sata";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
         };
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio0 17 0>;
+                gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
         };
 };
 
@@ -94,7 +94,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index 053aa20fb30f..02d1225ef99f 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -51,8 +51,8 @@
                 mvsdio@90000 {
                         pinctrl-0 = <&pmx_sdio_gpios>;
                         pinctrl-names = "default";
-                        wp-gpios = <&gpio1 5 0>;
-                        cd-gpios = <&gpio1 6 0>;
+                        wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                         status = "okay";
                 };
         };
@@ -84,7 +84,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@8 {
-                device_type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index e112ca62d978..bf7fe8ab88f4 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -24,24 +24,24 @@
 
                 blue-power {
                         label = "dns320:blue:power";
-                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 blue-usb {
                         label = "dns320:blue:usb";
-                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
                 orange-l_hdd {
                         label = "dns320:orange:l_hdd";
-                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
                 orange-r_hdd {
                         label = "dns320:orange:r_hdd";
-                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                        gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
                 };
                 orange-usb {
                         label = "dns320:orange:usb";
-                        gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */
                 };
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 5119fb8a8eb6..cb9978c652f2 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -24,24 +24,24 @@
 
                 white-power {
                         label = "dns325:white:power";
-                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 white-usb {
                         label = "dns325:white:usb";
-                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
                 };
                 red-l_hdd {
                         label = "dns325:red:l_hdd";
-                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
                 red-r_hdd {
                         label = "dns325:red:r_hdd";
-                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                        gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
                 };
                 red-usb {
                         label = "dns325:red:usb";
-                        gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index aefa375a550d..d5aa9564a287 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -15,18 +15,18 @@
 
                 button@1 {
                         label = "Power button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 2 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "USB unmount button";
-                        linux,code = <161>;
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 16 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -35,8 +35,8 @@
                 compatible = "gpio-fan";
                 pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 14 1
-                         &gpio1 13 1>;
+                gpios = <&gpio1 14 GPIO_ACTIVE_LOW
+                         &gpio1 13 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map = <0    0
                                       3000 1
                                       6000 2>;
@@ -46,7 +46,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_power_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 4 0>;
+                gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
         };
 
         ocp@f1000000 {
@@ -224,7 +224,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@8 {
-                device_type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 33ff368fbfa5..f31312ebd0d6 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -42,12 +42,12 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio1 14 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 fault {
                         label = "status:orange:fault";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
         };
         regulators {
@@ -95,7 +95,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 compatible = "marvell,88e1116";
                 reg = <0>;
         };
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 6f62af99c9cb..ef3463e0ae19 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -87,15 +87,15 @@
 
                 bluetooth {
                         label = "dreamplug:blue:bluetooth";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 wifi {
                         label = "dreamplug:green:wifi";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
                 wifi-ap {
                         label = "dreamplug:green:wifi_ap";
-                        gpios = <&gpio1 17 1>;
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
                 };
         };
 };
@@ -104,12 +104,10 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 
         ethphy1: ethernet-phy@1 {
-                device_type = "ethernet-phy";
                 reg = <1>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index a43bebb25110..eb9329420107 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -85,44 +85,44 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio1 14 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
                 fault {
                         label = "status:orange:fault";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 left0 {
                         label = "status:white:left0";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 left1 {
                         label = "status:white:left1";
-                        gpios = <&gpio1 11 0>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
                 };
                 left2 {
                         label = "status:white:left2";
-                        gpios = <&gpio1 12 0>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                 };
                 left3 {
                         label = "status:white:left3";
-                        gpios = <&gpio1 13 0>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
                 };
                 right0 {
                         label = "status:white:right0";
-                        gpios = <&gpio1 6 0>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
                 right1 {
                         label = "status:white:right1";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 right2 {
                         label = "status:white:right2";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
                 right3 {
                         label = "status:white:right3";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
         };
         regulators {
@@ -141,7 +141,7 @@
                         enable-active-high;
                         regulator-always-on;
                         regulator-boot-on;
-                        gpio = <&gpio0 29 0>;
+                        gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
@@ -176,7 +176,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index d30a91a5047d..2d51fce74a5a 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -45,10 +45,10 @@
                         nr-ports = <1>;
                 };
 
+                /* AzureWave AW-GH381 WiFi/BT */
                 mvsdio@90000 {
                         status = "okay";
-                        /* No CD or WP GPIOs */
-                        broken-cd;
+                        non-removable;
                 };
         };
 
@@ -60,19 +60,19 @@
 
                 health-r {
                         label = "guruplug:red:health";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
                 health-g {
                         label = "guruplug:green:health";
-                        gpios = <&gpio1 15 1>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 wmode-r {
                         label = "guruplug:red:wmode";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
                 wmode-g {
                         label = "guruplug:green:wmode";
-                        gpios = <&gpio1 17 1>;
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
                 };
         };
 };
@@ -101,13 +101,11 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 compatible = "marvell,88e1121";
                 reg = <0>;
         };
 
         ethphy1: ethernet-phy@1 {
-                device_type = "ethernet-phy";
                 compatible = "marvell,88e1121";
                 reg = <1>;
         };
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index c5fb02f7ebc3..a1add3f215e3 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -63,13 +63,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio0 29 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 28 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -81,16 +81,16 @@
 
                 green-os {
                         label = "ib62x0:green:os";
-                        gpios = <&gpio0 25 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 red-os {
                         label = "ib62x0:red:os";
-                        gpios = <&gpio0 22 0>;
+                        gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
                 };
                 usb-copy {
                         label = "ib62x0:red:usb_copy";
-                        gpios = <&gpio0 27 0>;
+                        gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -98,7 +98,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_power_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 24 0>;
+                gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
         };
 };
 
@@ -133,7 +133,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@8 {
-                device_type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 4a62b206f680..8d8c80e3656d 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -94,37 +94,37 @@
 
                 led-level {
                         label = "led_level";
-                        gpios = <&gpio1 9 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
                 };
                 power-blue {
                         label = "power:blue";
-                        gpios = <&gpio1 10 0>;
-                        linux,default-trigger = "timer";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 power-red {
                         label = "power:red";
-                        gpios = <&gpio1 11 0>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
                 };
                 usb1 {
                         label = "usb1:blue";
-                        gpios = <&gpio1 12 0>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                 };
                 usb2 {
                         label = "usb2:blue";
-                        gpios = <&gpio1 13 0>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
                 };
                 usb3 {
                         label = "usb3:blue";
-                        gpios = <&gpio1 14 0>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 usb4 {
                         label = "usb4:blue";
-                        gpios = <&gpio1 15 0>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
                 };
                 otb {
                         label = "otb:blue";
-                        gpios = <&gpio1 16 0>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -137,14 +137,14 @@
 
                 button@1 {
                         label = "OTB Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 3 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
                         debounce-interval = <100>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 12 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                         debounce-interval = <100>;
                 };
         };
@@ -183,7 +183,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@11 {
-                device_type = "ethernet-phy";
                 reg = <11>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index d15395d671ed..59e7a5adeedb 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -127,20 +127,20 @@
 
                 power_led {
                         label = "status:white:power_led";
-                        gpios = <&gpio0 16 0>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
                 };
                 rebuild_led {
                         label = "status:white:rebuild_led";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                 };
                 health_led {
                         label = "status:red:health_led";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                 };
                 backup_led {
                         label = "status:blue:backup_led";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
         };
         gpio-keys {
@@ -154,18 +154,18 @@
 
                 Power {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio0 14 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                 };
                 Reset {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 12 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                 };
                 OTB {
                         label = "OTB Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 3 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
                 };
         };
 };
@@ -200,7 +200,6 @@
         status = "okay";
 
         ethphy1: ethernet-phy@11 {
-                device_type = "ethernet-phy";
                 reg = <11>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index cd44f37e54b5..04a1e44541b3 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -38,8 +38,8 @@
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = < &gpio0 8 0            /* sda */
-                        &gpio0 9 0 >;           /* scl */
+                gpios = < &gpio0 8 GPIO_ACTIVE_HIGH             /* sda */
+                          &gpio0 9 GPIO_ACTIVE_HIGH>;           /* scl */
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
         };
 };
@@ -55,7 +55,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts
new file mode 100644
index 000000000000..c9e82eff9bf2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-laplug.dts
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2013 Maxime Hadjinlian <maxime.hadjinlian@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+
+/ {
+        model = "LaCie LaPlug";
+        compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>; /* 128 MB */
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                i2c@11000 {
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+
+                        eeprom@50 {
+                                compatible = "at,24c04";
+                                pagesize = <16>;
+                                reg = <0x50>;
+                        };
+                };
+
+                pinctrl: pinctrl@10000 {
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp14";
+                                marvell,function = "gpio";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                button@1{
+                        label = "Power push button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                red-fail {
+                        label = "laplug_v2:red:power";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+                blue-power {
+                        label = "laplug_v2:blue:power";
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
+
+                usb_power_back1: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power Back 1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb_power_back2: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "USB Power Back 2";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb_power_front: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "USB Power Front";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&nand {
+        /* Total size : 512MB */
+        status = "okay";
+        pinctrl-0 = <&pmx_nand>;
+
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0 0x100000>; /* 1MB */
+                read-only;
+        };
+
+        partition@100000 {
+                label = "uImage";
+                reg = <0x100000 0x1000000>; /* 16MB */
+        };
+
+        partition@1100000 {
+                label = "rootfs";
+                reg = <0x1100000 0x1EF00000>; /* 495MB */
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 4e8f9e42c592..1656653d339b 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -108,20 +108,20 @@
 
                 button@1 {
                         label = "Function Button";
-                        linux,code = <357>;
-                        gpios = <&gpio1 9 1>;
+                        linux,code = <KEY_OPTION>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Power-on Switch";
-                        linux,code = <0>;
+                        linux,code = <KEY_RESERVED>;
                         linux,input-type = <5>;
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Power-auto Switch";
-                        linux,code = <1>;
+                        linux,code = <KEY_ESC>;
                         linux,input-type = <5>;
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -134,28 +134,28 @@
 
                 led@1 {
                         label = "lsxl:blue:func";
-                        gpios = <&gpio1 4 1>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
 
                 led@2 {
                         label = "lsxl:red:alarm";
-                        gpios = <&gpio1 5 1>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
 
                 led@3 {
                         label = "lsxl:amber:info";
-                        gpios = <&gpio1 6 1>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                 };
 
                 led@4 {
                         label = "lsxl:blue:power";
-                        gpios = <&gpio1 7 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
                 led@5 {
                         label = "lsxl:red:func";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -163,13 +163,13 @@
                 compatible = "gpio-fan";
                 pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
                 pinctrl-names = "default";
-                gpios = <&gpio0 19 1
-                         &gpio0 18 1>;
+                gpios = <&gpio0 19 GPIO_ACTIVE_LOW
+                         &gpio0 18 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map = <0    3
                                       1500 2
                                       3250 1
                                       5000 0>;
-                alarm-gpios = <&gpio1 8 0>;
+                alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
         };
 
         restart_poweroff {
@@ -212,12 +212,10 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 
         ethphy1: ethernet-phy@8 {
-                device_type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6c1ec2786e6e..73722c067501 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -110,7 +110,7 @@
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 15 1>;
+                        cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                         /* No WP GPIO */
                 };
         };
@@ -126,36 +126,36 @@
 
                 health {
                         label = "status:green:health";
-                        gpios = <&gpio0 7 1>;
+                        gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
                 };
 
                 user1o {
                         label = "user1:orange";
-                        gpios = <&gpio1 8 1>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user1g {
                         label = "user1:green";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user0o {
                         label = "user0:orange";
-                        gpios = <&gpio1 12 1>;
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 user0g {
                         label = "user0:green";
-                        gpios = <&gpio1 13 1>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
                 misc {
                         label = "status:orange:misc";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
@@ -197,12 +197,10 @@
         status = "okay";
 
         ethphy0: ethernet-phy@1 {
-                device_type = "ethernet-phy";
                 reg = <1>;
         };
 
         ethphy1: ethernet-phy@2 {
-                device_type = "ethernet-phy";
                 reg = <2>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 6317e1d088b3..dc86429756d7 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -90,17 +90,17 @@
 
                 green-status {
                         label = "gtw:green:Status";
-                        gpios = <&gpio0 20 0>;
+                        gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
                 };
 
                 red-status {
                         label = "gtw:red:Status";
-                        gpios = <&gpio0 21 0>;
+                        gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
                 };
 
                 green-usb {
                         label = "gtw:green:USB";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -113,13 +113,13 @@
 
                 button@1 {
                         label = "SWR Button";
-                        linux,code = <0x198>; /* KEY_RESTART */
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "WPS Button";
-                        linux,code = <0x211>; /* KEY_WPS_BUTTON */
-                        gpios = <&gpio1 14 1>;
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index e6a102cf424c..4838478019cc 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,3 +1,14 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS Duo v2
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
 /dts-v1/;
 
 #include "kirkwood.dtsi"
@@ -32,41 +43,50 @@
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
                         };
+
                         pmx_button_backup: pmx-button-backup {
                                 marvell,pins = "mpp45";
                                 marvell,function = "gpio";
                         };
+
                         pmx_button_reset: pmx-button-reset {
                                 marvell,pins = "mpp13";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_power: pmx-led-blue-power {
                                 marvell,pins = "mpp31";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_activity: pmx-led-blue-activity {
                                 marvell,pins = "mpp38";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_disk1: pmx-led-blue-disk1 {
                                 marvell,pins = "mpp23";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_disk2: pmx-led-blue-disk2 {
                                 marvell,pins = "mpp22";
                                 marvell,function = "gpio";
                         };
+
                         pmx_led_blue_backup: pmx-led-blue-backup {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
                         };
+
+                        pmx_poweroff: pmx-poweroff {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
                 };
 
                 clocks {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       g762_clk: fixedclk {
+                       g762_clk: g762-oscillator {
                                  compatible = "fixed-clock";
                                  #clock-cells = <0>;
                                  clock-frequency = <8192>;
@@ -112,69 +132,80 @@
 
                 power_led {
                         label = "status:blue:power_led";
-                        gpios = <&gpio0 31 1>;   /* GPIO 31 Active Low */
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
+
                 activity_led {
                         label = "status:blue:activity_led";
-                        gpios = <&gpio1 6 1>;    /* GPIO 38 Active Low */
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                 };
+
                 disk1_led {
                         label = "status:blue:disk1_led";
-                        gpios = <&gpio0 23 1>;   /* GPIO 23 Active Low */
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
                 };
+
                 disk2_led {
                         label = "status:blue:disk2_led";
-                        gpios = <&gpio0 22 1>;   /* GPIO 22 Active Low */
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
                 };
+
                 backup_led {
                         label = "status:blue:backup_led";
-                        gpios = <&gpio0 29 1>;   /* GPIO 29 Active Low*/
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
                 pinctrl-0 = <&pmx_button_power &pmx_button_backup
                              &pmx_button_reset>;
                 pinctrl-names = "default";
 
-                button@1 {
+                power-button {
                         label = "Power Button";
-                        linux,code = <116>;     /* KEY_POWER */
-                        gpios = <&gpio1 15 1>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                 };
-                button@2 {
+
+                reset-button {
                         label = "Reset Button";
-                        linux,code = <0x198>;   /* KEY_RESTART */
-                        gpios = <&gpio0 13 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
                 };
-                button@3 {
+
+                backup-button {
                         label = "Backup Button";
-                        linux,code = <133>;     /* KEY_COPY */
-                        gpios = <&gpio1 13 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
                 };
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                usb_power: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "USB 3.0 Power";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        gpio = <&gpio1 14 0>;
-                };
-        };
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb3_regulator: usb3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
 };
 
 &nand {
@@ -210,8 +241,7 @@
 &mdio {
         status = "okay";
 
-        ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
+        ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
new file mode 100644
index 000000000000..7c8a0d9d8d1f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -0,0 +1,268 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS NV+ v2
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS NV+ v2";
+        compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        memory { /* 256 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        /* Connected to NEC uPD720200 USB 3.0 controller */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_button_backup: pmx-button-backup {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_power: pmx-led-blue-power {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_backup: pmx-led-blue-backup {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk1: pmx-led-blue-disk1 {
+                                marvell,pins = "mpp20";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk2: pmx-led-blue-disk2 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk3: pmx-led-blue-disk3 {
+                                marvell,pins = "mpp24";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_blue_disk4: pmx-led-blue-disk4 {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_poweroff: pmx-poweroff {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                clocks {
+                       g762_clk: g762-oscillator {
+                                 compatible = "fixed-clock";
+                                 #clock-cells = <0>;
+                                 clock-frequency = <8192>;
+                       };
+                };
+
+                i2c@11000 {
+                        status = "okay";
+
+                        rs5c372a: rs5c372a@32 {
+                                compatible = "ricoh,rs5c372a";
+                                reg = <0x32>;
+                        };
+
+                        g762: g762@3e {
+                                compatible = "gmt,g762";
+                                reg = <0x3e>;
+                                clocks = <&g762_clk>; /* input clock */
+                                fan_gear_mode = <0>;
+                                fan_startv = <1>;
+                                pwm_polarity = <0>;
+                        };
+                };
+
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
+                              &pmx_led_blue_disk1 &pmx_led_blue_disk2
+                              &pmx_led_blue_disk3 &pmx_led_blue_disk3 >;
+                pinctrl-names = "default";
+
+                power_led {
+                        label = "status:blue:power_led";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+                };
+
+                disk1_led {
+                        label = "status:blue:disk1_led";
+                        gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+                };
+
+                disk2_led {
+                        label = "status:blue:disk2_led";
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+                };
+
+                disk3_led {
+                        label = "status:blue:disk3_led";
+                        gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+                };
+
+                disk4_led {
+                        label = "status:blue:disk4_led";
+                        gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_button_power &pmx_button_backup
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
+                power-button {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+                };
+
+                reset-button {
+                        label = "Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+                };
+
+                backup-button {
+                        label = "Backup Button";
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_poweroff>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb3_regulator: usb3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&nand {
+        status = "okay";
+
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0000000 0x180000>;
+                read-only;
+        };
+
+        partition@180000 {
+                label = "u-boot-env";
+                reg = <0x180000 0x20000>;
+        };
+
+        partition@200000 {
+                label = "uImage";
+                reg = <0x0200000 0x600000>;
+        };
+
+        partition@800000 {
+                label = "minirootfs";
+                reg = <0x0800000 0x1000000>;
+        };
+
+        partition@1800000 {
+                label = "jffs2";
+                reg = <0x1800000 0x6800000>;
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2fcb82e20828..743152f31a81 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -64,8 +64,8 @@
 
                 button@1 {
                         label = "Power push button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 0 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -74,13 +74,13 @@
 
                 red-fail {
                         label = "ns2:red:fail";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
         };
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio0 31 0>;
+                gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
         };
 
 };
@@ -89,7 +89,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy {
-                device_type = "ethernet-phy";
                 /* overwrite reg property in board file */
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index 279607093cdb..1f2ca60d8b3d 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -25,8 +25,8 @@
 
                 blue-sata {
                         label = "ns2:blue:sata";
-                        gpios = <&gpio0 30 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "ide-disk";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index defdc77fb550..72c78d0b1116 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -22,10 +22,10 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
-                gpios = <&gpio0 22 1
-                         &gpio0  7 1
-                         &gpio1  1 1
-                         &gpio0 23 1>;
+                gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+                         &gpio0  7 GPIO_ACTIVE_LOW
+                         &gpio1  1 GPIO_ACTIVE_LOW
+                         &gpio0 23 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map =
                         <   0  0
                          1500 15
@@ -36,7 +36,7 @@
                          3300 10
                          4300  9
                          5500  8>;
-                alarm-gpios = <&gpio0 25 1>;
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
         };
 
         ns2-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adbafdd90991..c441bf62c09f 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -23,10 +23,10 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
-                gpios = <&gpio0 22 1
-                         &gpio0  7 1
-                         &gpio1  1 1
-                         &gpio0 23 1>;
+                gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+                         &gpio0  7 GPIO_ACTIVE_LOW
+                         &gpio1  1 GPIO_ACTIVE_LOW
+                         &gpio0 23 GPIO_ACTIVE_LOW>;
                 gpio-fan,speed-map =
                         <   0  0
                          3000 15
@@ -37,7 +37,7 @@
                          7140 10
                          7980  9
                          9200  8>;
-                alarm-gpios = <&gpio0 25 1>;
+                alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
         };
 
         ns2-leds {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
index e3f915defd3d..aa78c2d11fe7 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -40,7 +40,7 @@
                 compatible = "gpio-poweroff";
                 pinctrl-0 = <&pmx_pwr_off>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 16 0>;
+                gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
         };
 
         regulators {
@@ -58,7 +58,7 @@
                         regulator-max-microvolt = <5000000>;
                         regulator-always-on;
                         regulator-boot-on;
-                        gpio = <&gpio0 21 0>;
+                        gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index b5418bcaecce..03fa24cf3344 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -119,18 +119,18 @@
 
                 button@1 {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 14 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 button@2 {
                         label = "Copy Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 4 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -145,43 +145,43 @@
 
                 green-sys {
                         label = "nsa310:green:sys";
-                        gpios = <&gpio0 28 0>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
                 };
                 red-sys {
                         label = "nsa310:red:sys";
-                        gpios = <&gpio0 29 0>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
                 green-hdd {
                         label = "nsa310:green:hdd";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
                 red-hdd {
                         label = "nsa310:red:hdd";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 green-esata {
                         label = "nsa310:green:esata";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
                 red-esata {
                         label = "nsa310:red:esata";
-                        gpios = <&gpio0 13 0>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
                 };
                 green-usb {
                         label = "nsa310:green:usb";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
                 red-usb {
                         label = "nsa310:red:usb";
-                        gpios = <&gpio0 16 0>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
                 };
                 green-copy {
                         label = "nsa310:green:copy";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 red-copy {
                         label = "nsa310:red:copy";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
index ab0212b0e6f5..a5e779452867 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310a.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -107,18 +107,18 @@
 
                 button@1 {
                         label = "Power Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 14 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
                 };
                 button@2 {
                         label = "Copy Button";
-                        linux,code = <133>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 button@3 {
                         label = "Reset Button";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 4 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -127,39 +127,39 @@
 
                 green-sys {
                         label = "nsa310:green:sys";
-                        gpios = <&gpio0 28 0>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
                 };
                 red-sys {
                         label = "nsa310:red:sys";
-                        gpios = <&gpio0 29 0>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
                 };
                 green-hdd {
                         label = "nsa310:green:hdd";
-                        gpios = <&gpio1 9 0>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                 };
                 red-hdd {
                         label = "nsa310:red:hdd";
-                        gpios = <&gpio1 10 0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                 };
                 green-esata {
                         label = "nsa310:green:esata";
-                        gpios = <&gpio0 12 0>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 };
                 red-esata {
                         label = "nsa310:red:esata";
-                        gpios = <&gpio0 13 0>;
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
                 };
                 green-usb {
                         label = "nsa310:green:usb";
-                        gpios = <&gpio0 15 0>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
                 green-copy {
                         label = "nsa310:green:copy";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                 };
                 red-copy {
                         label = "nsa310:red:copy";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index f0e3d213604c..b88da9392c32 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -101,17 +101,17 @@
 
                 led-red {
                         label = "obsa6:red:stat";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
 
                 led-green {
                         label = "obsa6:green:stat";
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
 
                 led-yellow {
                         label = "obsa6:yellow:stat";
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -124,8 +124,8 @@
 
                 button@1 {
                         label = "Init Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 6 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
@@ -171,7 +171,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
index 851fb2a60f20..b2f7cae06839 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -126,17 +126,17 @@
 
                 led-red {
                         label = "obsa7:red:stat";
-                        gpios = <&gpio1 9 1>;
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                 };
 
                 led-green {
                         label = "obsa7:green:stat";
-                        gpios = <&gpio1 10 1>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
                 };
 
                 led-yellow {
                         label = "obsa7:yellow:stat";
-                        gpios = <&gpio1 11 1>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -149,8 +149,8 @@
 
                 button@1 {
                         label = "Init Button";
-                        linux,code = <116>;
-                        gpios = <&gpio1 6 0>;
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                 };
         };
 };
@@ -196,12 +196,10 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 
         ethphy1: ethernet-phy@1 {
-                device_type = "ethernet-phy";
                 reg = <1>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index 1173d7fb31b2..1ff848d570a9 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -1,5 +1,5 @@
 /*
- * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
  *
  * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
  *
@@ -96,7 +96,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index eac6a21f3b1f..e2b4ea4f9e10 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -24,8 +24,8 @@
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 12 1>;
-                        wp-gpios = <&gpio1 15 0>;
+                        cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -36,8 +36,8 @@
 
                 health {
                         label = "sheevaplug:blue:health";
-                        gpios = <&gpio1 17 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bb61918313db..82f6abf120fd 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -1,5 +1,5 @@
 /*
- * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
  *
  * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
  *
@@ -31,13 +31,13 @@
 
                 health {
                         label = "sheevaplug:blue:health";
-                        gpios = <&gpio1 17 1>;
-                        linux,default-trigger = "default-on";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
                 };
 
                 misc {
                         label = "sheevaplug:red:misc";
-                        gpios = <&gpio1 14 1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 320da677b984..5fc817c2cb87 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -131,25 +131,25 @@
 
                 disk {
                         label = "topkick:yellow:disk";
-                        gpios = <&gpio0 21 1>;
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "ide-disk";
                 };
                 system2 {
                         label = "topkick:red:system";
-                        gpios = <&gpio1 5 1>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
                 system {
                         label = "topkick:blue:system";
-                        gpios = <&gpio1 6 1>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
                 wifi {
                         label = "topkick:green:wifi";
-                        gpios = <&gpio1 7 1>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
                 };
                 wifi2 {
                         label = "topkick:yellow:wifi";
-                        gpios = <&gpio1 16 1>;
+                        gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                 };
         };
         regulators {
@@ -208,7 +208,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy@0 {
-                device_type = "ethernet-phy";
                 reg = <0>;
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index f755bc1dc604..c17ae45e19be 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -41,13 +41,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio0 15 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio0 16 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 345562f75891..0713d072758a 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -51,13 +51,13 @@
 
                 button@1 {
                         label = "USB Copy";
-                        linux,code = <133>;
-                        gpios = <&gpio1 11 1>;
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
                 };
                 button@2 {
                         label = "Reset";
-                        linux,code = <0x198>;
-                        gpios = <&gpio1 5 1>;
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 39158cf16258..911f3a8cee23 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -104,7 +104,6 @@
         status = "okay";
 
         ethphy0: ethernet-phy {
-                device_type = "ethernet-phy";
                 /* overwrite reg property in board file */
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 8b73c80f1dad..6abf44d257df 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,4 +1,6 @@
 /include/ "skeleton.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
@@ -68,39 +70,21 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
 
-                mbusc: mbus-controller@20000 {
-                        compatible = "marvell,mbus-controller";
-                        reg = <0x20000 0x80>, <0x1500 0x20>;
-                };
-
-                timer: timer@20300 {
-                        compatible = "marvell,orion-timer";
-                        reg = <0x20300 0x20>;
-                        interrupt-parent = <&bridge_intc>;
-                        interrupts = <1>, <2>;
-                        clocks = <&core_clk 0>;
-                };
-
-                intc: main-interrupt-ctrl@20200 {
-                        compatible = "marvell,orion-intc";
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        reg = <0x20200 0x10>, <0x20210 0x10>;
-                };
-
-                bridge_intc: bridge-interrupt-ctrl@20110 {
-                        compatible = "marvell,orion-bridge-intc";
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        reg = <0x20110 0x8>;
-                        interrupts = <1>;
-                        marvell,#interrupts = <6>;
-                };
-
                 core_clk: core-clocks@10030 {
                         compatible = "marvell,kirkwood-core-clock";
                         reg = <0x10030 0x4>;
-                        #clock-cells = <1>;
+                        #clock-cells = <1>;
+                };
+
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <23>;
+                        reg = <0x10600 0x28>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
                 };
 
                 gpio0: gpio@10100 {
@@ -127,6 +111,17 @@
                         clocks = <&gate_clk 7>;
                 };
 
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <29>;
+                        clock-frequency = <100000>;
+                        clocks = <&gate_clk 7>;
+                        status = "disabled";
+                };
+
                 serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -145,15 +140,18 @@
                         status = "disabled";
                 };
 
-                spi@10600 {
-                        compatible = "marvell,orion-spi";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        interrupts = <23>;
-                        reg = <0x10600 0x28>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
+                mbusc: mbus-controller@20000 {
+                        compatible = "marvell,mbus-controller";
+                        reg = <0x20000 0x80>, <0x1500 0x20>;
+                };
+
+                bridge_intc: bridge-interrupt-ctrl@20110 {
+                        compatible = "marvell,orion-bridge-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x20110 0x8>;
+                        interrupts = <1>;
+                        marvell,#interrupts = <6>;
                 };
 
                 gate_clk: clock-gating-control@2011c {
@@ -163,6 +161,21 @@
                         #clock-cells = <1>;
                 };
 
+                intc: main-interrupt-ctrl@20200 {
+                        compatible = "marvell,orion-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0x20200 0x10>, <0x20210 0x10>;
+                };
+
+                timer: timer@20300 {
+                        compatible = "marvell,orion-timer";
+                        reg = <0x20300 0x20>;
+                        interrupt-parent = <&bridge_intc>;
+                        interrupts = <1>, <2>;
+                        clocks = <&core_clk 0>;
+                };
+
                 wdt: watchdog-timer@20300 {
                         compatible = "marvell,orion-wdt";
                         reg = <0x20300 0x28>;
@@ -172,6 +185,14 @@
                         status = "okay";
                 };
 
+                ehci@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&gate_clk 3>;
+                        status = "okay";
+                };
+
                 xor@60800 {
                         compatible = "marvell,orion-xor";
                         reg = <0x60800 0x100
@@ -212,37 +233,6 @@
                         };
                 };
 
-                ehci@50000 {
-                        compatible = "marvell,orion-ehci";
-                        reg = <0x50000 0x1000>;
-                        interrupts = <19>;
-                        clocks = <&gate_clk 3>;
-                        status = "okay";
-                };
-
-                i2c@11000 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11000 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <29>;
-                        clock-frequency = <100000>;
-                        clocks = <&gate_clk 7>;
-                        status = "disabled";
-                };
-
-                mdio: mdio-bus@72004 {
-                        compatible = "marvell,orion-mdio";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x72004 0x84>;
-                        interrupts = <46>;
-                        clocks = <&gate_clk 0>;
-                        status = "disabled";
-
-                        /* add phy nodes in board file */
-                };
-
                 eth0: ethernet-controller@72000 {
                         compatible = "marvell,kirkwood-eth";
                         #address-cells = <1>;
@@ -253,7 +243,6 @@
                         status = "disabled";
 
                         ethernet0-port@0 {
-                                device_type = "network";
                                 compatible = "marvell,kirkwood-eth-port";
                                 reg = <0>;
                                 interrupts = <11>;
@@ -263,6 +252,18 @@
                         };
                 };
 
+                mdio: mdio-bus@72004 {
+                        compatible = "marvell,orion-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x72004 0x84>;
+                        interrupts = <46>;
+                        clocks = <&gate_clk 0>;
+                        status = "disabled";
+
+                        /* add phy nodes in board file */
+                };
+
                 eth1: ethernet-controller@76000 {
                         compatible = "marvell,kirkwood-eth";
                         #address-cells = <1>;
@@ -273,7 +274,6 @@
                         status = "disabled";
 
                         ethernet1-port@0 {
-                                device_type = "network";
                                 compatible = "marvell,kirkwood-eth-port";
                                 reg = <0>;
                                 interrupts = <15>;
@@ -282,5 +282,23 @@
                                 /* set phy-handle property in board file */
                         };
                 };
+
+                sata_phy0: sata-phy@82000 {
+                        compatible = "marvell,mvebu-sata-phy";
+                        reg = <0x82000 0x0334>;
+                        clocks = <&gate_clk 14>;
+                        clock-names = "sata";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+
+                sata_phy1: sata-phy@84000 {
+                        compatible = "marvell,mvebu-sata-phy";
+                        reg = <0x84000 0x0334>;
+                        clocks = <&gate_clk 15>;
+                        clock-names = "sata";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 02df1914a47c..928f6eef2d59 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -53,6 +53,12 @@
                                 status = "okay";
                         };
 
+                        watchdog@fffffd40 {
+                                timeout-sec = <15>;
+                                atmel,max-heartbeat-sec = <16>;
+                                atmel,min-heartbeat-sec = <0>;
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
new file mode 100644
index 000000000000..10d088df0c35
--- /dev/null
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -0,0 +1,117 @@
+/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+/include/ "moxart.dtsi"
+
+/ {
+        model = "MOXA UC-7112-LX";
+        compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        clocks {
+                ref12: ref12M {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        flash@80000000,0 {
+                compatible = "numonyx,js28f128", "cfi-flash";
+                reg = <0x80000000 0x1000000>;
+                bank-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "bootloader";
+                        reg = <0x0 0x40000>;
+                };
+                partition@40000 {
+                        label = "linux kernel";
+                        reg = <0x40000 0x1C0000>;
+                };
+                partition@200000 {
+                        label = "root filesystem";
+                        reg = <0x200000 0x800000>;
+                };
+                partition@a00000 {
+                        label = "user filesystem";
+                        reg = <0xa00000 0x600000>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                user-led {
+                        label = "ready-led";
+                        gpios = <&gpio 27 0x1>;
+                        default-state = "on";
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        gpio_keys_polled {
+                compatible = "gpio-keys-polled";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <500>;
+                button@25 {
+                        label = "GPIO Reset";
+                        linux,code = <116>;
+                        gpios = <&gpio 25 1>;
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait";
+        };
+};
+
+&clk_pll {
+        clocks = <&ref12>;
+};
+
+&sdhci {
+        status = "okay";
+};
+
+&mdio0 {
+        status = "okay";
+
+        ethphy0: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&mdio1 {
+        status = "okay";
+
+        ethphy1: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&mac0 {
+        status = "okay";
+};
+
+&mac1 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
new file mode 100644
index 000000000000..1fd27ed65a01
--- /dev/null
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -0,0 +1,148 @@
+/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
+ *
+ * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "moxa,moxart";
+        model = "MOXART";
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "faraday,fa526";
+                        reg = <0>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x90000000 0x10000000>;
+                ranges;
+
+                intc: interrupt-controller@98800000 {
+                        compatible = "moxa,moxart-ic";
+                        reg = <0x98800000 0x38>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupt-mask = <0x00080000>;
+                };
+
+                clk_pll: clk_pll@98100000 {
+                        compatible = "moxa,moxart-pll-clock";
+                        #clock-cells = <0>;
+                        reg = <0x98100000 0x34>;
+                };
+
+                clk_apb: clk_apb@98100000 {
+                        compatible = "moxa,moxart-apb-clock";
+                        #clock-cells = <0>;
+                        reg = <0x98100000 0x34>;
+                        clocks = <&clk_pll>;
+                };
+
+                timer: timer@98400000 {
+                        compatible = "moxa,moxart-timer";
+                        reg = <0x98400000 0x42>;
+                        interrupts = <19 1>;
+                        clocks = <&clk_apb>;
+                };
+
+                gpio: gpio@98700000 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        compatible = "moxa,moxart-gpio";
+                        reg = <0x98700000 0xC>;
+                };
+
+                rtc: rtc {
+                        compatible = "moxa,moxart-rtc";
+                        gpio-rtc-sclk = <&gpio 5 0>;
+                        gpio-rtc-data = <&gpio 6 0>;
+                        gpio-rtc-reset = <&gpio 7 0>;
+                };
+
+                dma: dma@90500000 {
+                        compatible = "moxa,moxart-dma";
+                        reg = <0x90500080 0x40>;
+                        interrupts = <24 0>;
+                        #dma-cells = <1>;
+                };
+
+                watchdog: watchdog@98500000 {
+                        compatible = "moxa,moxart-watchdog";
+                        reg = <0x98500000 0x10>;
+                        clocks = <&clk_apb>;
+                };
+
+                sdhci: sdhci@98e00000 {
+                        compatible = "moxa,moxart-sdhci";
+                        reg = <0x98e00000 0x5C>;
+                        interrupts = <5 0>;
+                        clocks = <&clk_apb>;
+                        dmas =  <&dma 5>,
+                                <&dma 5>;
+                        dma-names = "tx", "rx";
+                        status = "disabled";
+                };
+
+                mdio0: mdio@90900090 {
+                        compatible = "moxa,moxart-mdio";
+                        reg = <0x90900090 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mdio1: mdio@92000090 {
+                        compatible = "moxa,moxart-mdio";
+                        reg = <0x92000090 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mac0: mac@90900000 {
+                        compatible = "moxa,moxart-mac";
+                        reg = <0x90900000 0x90>;
+                        interrupts = <25 0>;
+                        phy-handle = <&ethphy0>;
+                        phy-mode = "mii";
+                        status = "disabled";
+                };
+
+                mac1: mac@92000000 {
+                        compatible = "moxa,moxart-mac";
+                        reg = <0x92000000 0x90>;
+                        interrupts = <27 0>;
+                        phy-handle = <&ethphy1>;
+                        phy-mode = "mii";
+                        status = "disabled";
+                };
+
+                uart0: uart@98200000 {
+                        compatible = "ns16550a";
+                        reg = <0x98200000 0x20>;
+                        interrupts = <31 8>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <14745600>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index d0c5b37e248c..5377ddf83bf8 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -145,7 +145,7 @@
                         compatible = "ti,omap2-rng";
                         ti,hwmods = "rng";
                         reg = <0x480a0000 0x50>;
-                        interrupts = <36>;
+                        interrupts = <52>;
                 };
 
                 sham: sham@480a4000 {
diff --git a/arch/arm/boot/dts/omap2420-n800.dts b/arch/arm/boot/dts/omap2420-n800.dts
new file mode 100644
index 000000000000..d8c1b423606a
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-n800.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "omap2420-n8x0-common.dtsi"
+
+/ {
+        model = "Nokia N800";
+        compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
+};
diff --git a/arch/arm/boot/dts/omap2420-n810-wimax.dts b/arch/arm/boot/dts/omap2420-n810-wimax.dts
new file mode 100644
index 000000000000..6b25b0359ac9
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-n810-wimax.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "omap2420-n8x0-common.dtsi"
+
+/ {
+        model = "Nokia N810 WiMax";
+        compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
+};
diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts
new file mode 100644
index 000000000000..21baec154b78
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-n810.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "omap2420-n8x0-common.dtsi"
+
+/ {
+        model = "Nokia N810";
+        compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
+};
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
new file mode 100644
index 000000000000..89608b206519
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -0,0 +1,99 @@
+#include "omap2420.dtsi"
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x8000000>; /* 128 MB */
+        };
+
+        ocp {
+                i2c@0 {
+                        compatible = "i2c-cbus-gpio";
+                        gpios = <&gpio3 2 0 /* gpio66 clk */
+                                 &gpio3 1 0 /* gpio65 dat */
+                                 &gpio3 0 0 /* gpio64 sel */
+                                >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        retu_mfd: retu@1 {
+                                compatible = "retu-mfd";
+                                interrupt-parent = <&gpio4>;
+                                interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+                                reg = <0x1>;
+                        };
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&gpmc {
+        ranges = <0 0 0x04000000 0x10000000>;
+
+        /* gpio-irq for dma: 26 */
+
+        onenand@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0 0x10000000>;
+
+                gpmc,sync-read;
+                gpmc,burst-length = <16>;
+                gpmc,burst-read;
+                gpmc,burst-wrap;
+                gpmc,device-width = <2>;
+                gpmc,mux-add-data = <2>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <127>;
+                gpmc,cs-wr-off-ns = <109>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <18>;
+                gpmc,adv-wr-off-ns = <18>;
+                gpmc,oe-on-ns = <27>;
+                gpmc,oe-off-ns = <127>;
+                gpmc,we-on-ns = <27>;
+                gpmc,we-off-ns = <72>;
+                gpmc,rd-cycle-ns = <145>;
+                gpmc,wr-cycle-ns = <136>;
+                gpmc,access-ns = <118>;
+                gpmc,page-burst-access-ns = <27>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <9>;
+                gpmc,sync-clk-ps = <27000>;
+
+                /* MTD partition table corresponding to old board-n8x0 file. */
+                partition@0 {
+                        label = "bootloader";
+                        reg = <0x00000000 0x00020000>;
+                        read-only;
+                };
+                partition@1 {
+                        label = "config";
+                        reg = <0x00020000 0x00060000>;
+                };
+                partition@2 {
+                        label = "kernel";
+                        reg = <0x00080000 0x00200000>;
+                };
+                partition@3 {
+                        label = "initfs";
+                        reg = <0x00280000 0x00400000>;
+                };
+                partition@4 {
+                        label = "rootfs";
+                        reg = <0x00680000 0x0f980000>;
+                };
+                partition@5 {
+                        label = "omap2-onenand";
+                        reg = <0x00000000 0x10000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
new file mode 100644
index 000000000000..2c90d29b4cad
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap2430.dtsi"
+
+/ {
+        model = "TI OMAP2430 SDP";
+        compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x8000000>; /* 128 MB */
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+        };
+};
+
+#include "twl4030.dtsi"
+
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+
+&gpmc {
+        ranges = <5 0 0x08000000 0x01000000>;
+        ethernet@gpmc {
+                compatible = "smsc,lan91c94";
+                interrupt-parent = <&gpio5>;
+                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;   /* gpio149 */
+                reg = <5 0x300 0xf>;
+                bank-width = <2>;
+                gpmc,mux-add-data;
+        };
+};
+
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index df33a50bc070..447e714d435b 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -99,7 +99,7 @@
 &omap3_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
-                        &hsusbb2_pins
+                        &hsusb2_pins
         >;
 
         uart3_pins: pinmux_uart3_pins {
@@ -109,20 +109,32 @@
                 >;
         };
 
-        hsusbb2_pins: pinmux_hsusbb2_pins {
+        hsusb2_pins: pinmux_hsusb2_pins {
                 pinctrl-single,pins = <
-                        0x5c0 (PIN_OUTPUT | MUX_MODE3)          /* etk_d10.hsusb2_clk */
-                        0x5c2 (PIN_OUTPUT | MUX_MODE3)          /* etk_d11.hsusb2_stp */
-                        0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d12.hsusb2_dir */
-                        0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d13.hsusb2_nxt */
-                        0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d14.hsusb2_data0 */
-                        0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d15.hsusb2_data1 */
-                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi1_cs3.hsusb2_data2 */
-                        0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_clk.hsusb2_data7 */
-                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_simo.hsusb2_data4 */
-                        0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_somi.hsusb2_data5 */
-                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_cs0.hsusb2_data6 */
-                        0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_cs1.hsusb2_data3 */
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+                >;
+        };
+};
+
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_2_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
                 >;
         };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 3ba4a625ea5b..5053766d369b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -93,23 +93,17 @@
 &omap3_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
-                        &hsusbb2_pins
+                        &hsusb2_pins
         >;
 
-        hsusbb2_pins: pinmux_hsusbb2_pins {
+        hsusb2_pins: pinmux_hsusb2_pins {
                 pinctrl-single,pins = <
-                        0x5c0 (PIN_OUTPUT | MUX_MODE3)          /* etk_d10.hsusb2_clk */
-                        0x5c2 (PIN_OUTPUT | MUX_MODE3)          /* etk_d11.hsusb2_stp */
-                        0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d12.hsusb2_dir */
-                        0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d13.hsusb2_nxt */
-                        0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d14.hsusb2_data0 */
-                        0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d15.hsusb2_data1 */
-                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi1_cs3.hsusb2_data2 */
-                        0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_clk.hsusb2_data7 */
-                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_simo.hsusb2_data4 */
-                        0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_somi.hsusb2_data5 */
-                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_cs0.hsusb2_data6 */
-                        0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* mcspi2_cs1.hsusb2_data3 */
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
                 >;
         };
 
@@ -121,6 +115,24 @@
         };
 };
 
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_2_pins
+        >;
+
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+};
+
 &i2c1 {
         clock-frequency = <2600000>;
 
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
new file mode 100644
index 000000000000..486f4d6c4219
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -0,0 +1,104 @@
+/*
+ * Support for CompuLab CM-T3730
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-cm-t3x30.dtsi"
+
+/ {
+        model = "CompuLab CM-T3730";
+        compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+
+        wl12xx_vmmc2: wl12xx_vmmc2 {
+                compatible = "regulator-fixed";
+                regulator-name = "vw1271";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wl12xx_gpio>;
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;   /* gpio73 */
+                startup-delay-us = <20000>;
+                enable-active-high;
+        };
+
+        wl12xx_vaux2: wl12xx_vaux2 {
+                compatible = "regulator-fixed";
+                regulator-name = "vwl1271_vaux2";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vaux2>;
+        };
+};
+
+&omap3_pmx_core {
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
+                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
+                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
+                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
+                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
+                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        0x128 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_clk.sdmmc2_clk */
+                        0x12a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_cmd.sdmmc2_cmd */
+                        0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat0.sdmmc2_dat0 */
+                        0x12e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat1.sdmmc2_dat1 */
+                        0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat2.sdmmc2_dat2 */
+                        0x132 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat3.sdmmc2_dat3 */
+                >;
+        };
+
+        smsc1_pins: pinmux_smsc1_pins {
+                pinctrl-single,pins = <
+                        0x88 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_ncs5.gpmc_ncs5 */
+                        0x16a (PIN_INPUT_PULLUP | MUX_MODE4)    /* uart3_cts_rctx.gpio_163 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+
+        wl12xx_gpio: pinmux_wl12xx_gpio {
+                pinctrl-single,pins = <
+                        0xb2 (PIN_OUTPUT | MUX_MODE4)           /* dss_data3.gpio_73 */
+                        0x134 (PIN_INPUT | MUX_MODE4)           /* sdmmc2_dat4.gpio_136 */
+                >;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&wl12xx_vmmc2>;
+        vmmc_aux-supply = <&wl12xx_vaux2>;
+        non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+};
+
+&smsc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&smsc1_pins>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
new file mode 100644
index 000000000000..3a9f004d8924
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Common support for CompuLab CM-T3530 and  CM-T3730
+ */
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                ledb {
+                        label = "cm-t35:green";
+                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;  /* gpio186 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        vddvario: regulator-vddvario {
+                compatible = "regulator-fixed";
+                regulator-name = "vddvario";
+                regulator-always-on;
+        };
+
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+
+&gpmc {
+        ranges = <5 0 0x2c000000 0x01000000>;
+
+        smsc1: ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                interrupt-parent = <&gpio6>;
+                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                vddvario-supply = <&vddvario>;
+                vdd33a-supply = <&vdd33a>;
+                reg-io-width = <4>;
+                smsc,save-mac-address;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c3 {
+        clock-frequency = <400000>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 165aaf7591ba..c17009323520 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -133,8 +133,6 @@
                         0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
                 >;
         };
-
-        leds_pins: pinmux_leds_pins { };
 };
 
 &i2c1 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 1c7e74d2d2bc..25a2b5f652fd 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -66,28 +66,10 @@
 &omap3_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
-                &hsusbb1_pins
                 &tfp410_pins
                 &dss_pins
         >;
 
-        hsusbb1_pins: pinmux_hsusbb1_pins {
-                pinctrl-single,pins = <
-                        0x5aa (PIN_OUTPUT | MUX_MODE3)          /* etk_ctl.hsusb1_clk */
-                        0x5a8 (PIN_OUTPUT | MUX_MODE3)          /* etk_clk.hsusb1_stp */
-                        0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d8.hsusb1_dir */
-                        0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d9.hsusb1_nxt */
-                        0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d0.hsusb1_data0 */
-                        0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d1.hsusb1_data1 */
-                        0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d2.hsusb1_data2 */
-                        0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d3.hsusb1_data7 */
-                        0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d4.hsusb1_data4 */
-                        0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d5.hsusb1_data5 */
-                        0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d6.hsusb1_data6 */
-                        0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* etk_d7.hsusb1_data3 */
-                >;
-        };
-
         tfp410_pins: tfp410_dvi_pins {
                 pinctrl-single,pins = <
                         0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
@@ -128,12 +110,36 @@
         };
 };
 
-&leds_pins {
-        pinctrl-single,pins = <
-                0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
-                0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
-                0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb1_pins
         >;
+
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)            /* etk_ctl.hsusb1_clk */
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)            /* etk_clk.hsusb1_stp */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d8.hsusb1_dir */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d9.hsusb1_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d0.hsusb1_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d1.hsusb1_data1 */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d2.hsusb1_data2 */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d3.hsusb1_data7 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d4.hsusb1_data4 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d5.hsusb1_data5 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d6.hsusb1_data6 */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d7.hsusb1_data3 */
+                >;
+        };
+
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
+                >;
+        };
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 02a23f8a3384..145c58cfc8ac 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -46,10 +46,12 @@
         };
 };
 
-&leds_pins {
-        pinctrl-single,pins = <
-                0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
-        >;
+&omap3_pmx_core2 {
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
+                >;
+        };
 };
 
 &gpmc {
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
new file mode 100644
index 000000000000..ddce0d807f70
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap-gpmc-smsc911x.dtsi"
+
+/ {
+        model = "TI OMAP3430 LDP (Zoom1 Labrador)";
+        compatible = "ti,omap3-ldp", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x8000000>; /* 128 MB */
+        };
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vcc>;
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_key_pins>;
+
+                key_enter {
+                        label = "enter";
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */
+                        linux,code = <0x0107001c>; /* KEY_ENTER */
+                        gpio-key,wakeup;
+                };
+
+                key_f1 {
+                        label = "f1";
+                        gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */
+                        linux,code = <0x0303003b>; /* KEY_F1 */
+                        gpio-key,wakeup;
+                };
+
+                key_f2 {
+                        label = "f2";
+                        gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */
+                        linux,code = <0x0403003c>; /* KEY_F2 */
+                        gpio-key,wakeup;
+                };
+
+                key_f3 {
+                        label = "f3";
+                        gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */
+                        linux,code = <0x0503003d>; /* KEY_F3 */
+                        gpio-key,wakeup;
+                };
+
+                key_f4 {
+                        label = "f4";
+                        gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */
+                        linux,code = <0x0704003e>; /* KEY_F4 */
+                        gpio-key,wakeup;
+                };
+
+                key_left {
+                        label = "left";
+                        gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */
+                        linux,code = <0x04070069>; /* KEY_LEFT */
+                        gpio-key,wakeup;
+                };
+
+                key_right {
+                        label = "right";
+                        gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */
+                        linux,code = <0x0507006a>; /* KEY_RIGHT */
+                        gpio-key,wakeup;
+                };
+
+                key_up {
+                        label = "up";
+                        gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */
+                        linux,code = <0x06070067>; /* KEY_UP */
+                        gpio-key,wakeup;
+                };
+
+                key_down {
+                        label = "down";
+                        gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */
+                        linux,code = <0x0707006c>; /* KEY_DOWN */
+                        gpio-key,wakeup;
+                };
+        };
+};
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x01000000>,
+                 <1 0 0x08000000 0x01000000>;
+
+        nand@0,0 {
+                linux,mtd-name= "micron,nand";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x140000>;
+                };
+                partition@1c0000 {
+                        label = "Environment";
+                        reg = <0x1c0000 0x40000>;
+                };
+                partition@200000 {
+                        label = "Kernel";
+                        reg = <0x200000 0x1e00000>;
+                };
+                partition@2000000 {
+                        label = "Filesystem";
+                        reg = <0x2000000 0xe000000>;
+                };
+        };
+
+        ethernet@gpmc {
+                interrupt-parent = <&gpio5>;
+                interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+                reg = <1 0 0xff>;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+
+&omap3_pmx_core {
+        gpio_key_pins: pinmux_gpio_key_pins {
+                pinctrl-single,pins = <
+                        0xea (PIN_INPUT | MUX_MODE4)    /* cam_d2.gpio_101 */
+                        0xec (PIN_INPUT | MUX_MODE4)    /* cam_d3.gpio_102 */
+                        0xee (PIN_INPUT | MUX_MODE4)    /* cam_d4.gpio_103 */
+                        0xf0 (PIN_INPUT | MUX_MODE4)    /* cam_d5.gpio_104 */
+                        0xf2 (PIN_INPUT | MUX_MODE4)    /* cam_d6.gpio_105 */
+                        0xf4 (PIN_INPUT | MUX_MODE4)    /* cam_d7.gpio_106 */
+                        0xf6 (PIN_INPUT | MUX_MODE4)    /* cam_d8.gpio_107 */
+                        0xf8 (PIN_INPUT | MUX_MODE4)    /* cam_d9.gpio_108 */
+                        0xfa (PIN_INPUT | MUX_MODE4)    /* cam_d10.gpio_109 */
+                >;
+        };
+
+        musb_pins: pinmux_musb_pins {
+                pinctrl-single,pins = <
+                        0x172 (PIN_INPUT | MUX_MODE0)   /* hsusb0_clk.hsusb0_clk */
+                        0x17a (PIN_INPUT | MUX_MODE0)   /* hsusb0_data0.hsusb0_data0 */
+                        0x17c (PIN_INPUT | MUX_MODE0)   /* hsusb0_data1.hsusb0_data1 */
+                        0x17e (PIN_INPUT | MUX_MODE0)   /* hsusb0_data2.hsusb0_data2 */
+                        0x180 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data3.hsusb0_data3 */
+                        0x182 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data4.hsusb0_data4 */
+                        0x184 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data5.hsusb0_data5 */
+                        0x186 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
+                        0x188 (PIN_INPUT | MUX_MODE0)   /* hsusb0_data7.hsusb0_data7 */
+                        0x176 (PIN_INPUT | MUX_MODE0)   /* hsusb0_dir.hsusb0_dir */
+                        0x178 (PIN_INPUT | MUX_MODE0)   /* hsusb0_nxt.hsusb0_nxt */
+                        0x174 (PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
+                >;
+        };
+};
+
+&usb_otg_hs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&musb_pins>;
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        mode = <3>;
+        power = <50>;
+};
+
+&vaux1 {
+        /* Needed for ads7846 */
+        regulator-name = "vcc";
+};
+
+&vpll2 {
+       /* Needed for DSS */
+       regulator-name = "vdds_dsi";
+};
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
new file mode 100644
index 000000000000..b9a2fedce7ee
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
+ */
+
+&gpmc {
+        ranges = <4 0 0x2d000000 0x01000000>;
+
+        smsc2: ethernet@4,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                interrupt-parent = <&gpio3>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                reg = <4 0 0xff>;
+                bank-width = <2>;
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                vddvario-supply = <&vddvario>;
+                vdd33a-supply = <&vdd33a>;
+                reg-io-width = <4>;
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
new file mode 100644
index 000000000000..c119bd545053
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -0,0 +1,30 @@
+/*
+ * Suppport for CompuLab SBC-T3730 with CM-T3730
+ */
+
+#include "omap3-cm-t3730.dts"
+#include "omap3-sb-t35.dtsi"
+
+/ {
+        model = "CompuLab SBC-T3730 with CM-T3730";
+        compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+};
+
+&gpmc {
+        ranges = <5 0 0x2c000000 0x01000000>,
+                 <4 0 0x2d000000 0x01000000>;
+};
+
+&smsc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&smsc2_pins>;
+};
+
+&omap3_pmx_core {
+        smsc2_pins: pinmux_smsc2_pins {
+                pinctrl-single,pins = <
+                        0x86 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_ncs4.gpmc_ncs4 */
+                        0xa2 (PIN_INPUT_PULLUP | MUX_MODE4)     /* gpmc_wait3.gpio_65 */
+                >;
+        };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index 15eb9fe5169c..6644f516a42b 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -80,13 +80,8 @@
 
         mmc3_pins: pinmux_mmc3_pins {
                 pinctrl-single,pins = <
-                        0x168 (PIN_INPUT | MUX_MODE4)   /* mcbsp1_clkx.gpio_162 WLAN IRQ */
-                        0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3)    /* mcspi1_cs1.sdmmc3_cmd */
-                        0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2)    /* etk_clk.sdmmc3_clk */
-                        0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2)    /* etk_d4.sdmmc3_dat0 */
-                        0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
-                        0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2)    /* etk_d6.sdmmc3_dat2 */
-                        0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2)    /* etk_d3.sdmmc3_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4)        /* mcbsp1_clkx.gpio_162 WLAN IRQ */
+                        OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
                 >;
         };
 
@@ -125,6 +120,18 @@
         };
 };
 
+&omap3_pmx_core2 {
+        mmc3_2_pins: pinmux_mmc3_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_clk.sdmmc3_clk */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d4.sdmmc3_dat0 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d6.sdmmc3_dat2 */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)      /* etk_d3.sdmmc3_dat3 */
+                >;
+        };
+};
+
 &omap3_pmx_wkup {
         wlan_host_wkup: pinmux_wlan_host_wkup_pins {
                 pinctrl-single,pins = <
@@ -187,7 +194,7 @@
         bus-width = <4>;
         cap-power-off-card;
         pinctrl-names = "default";
-        pinctrl-0 = <&mmc3_pins>;
+        pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index daabf99d402a..a5fc83b9c835 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -89,6 +89,45 @@
                         interrupts = <0>;
                 };
 
+                prm: prm@48306000 {
+                        compatible = "ti,omap3-prm";
+                        reg = <0x48306000 0x4000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm: cm@48004000 {
+                        compatible = "ti,omap3-cm";
+                        reg = <0x48004000 0x4000>;
+
+                        cm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@48002000 {
+                        compatible = "ti,omap3-scrm";
+                        reg = <0x48002000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@48320000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x48320000 0x20>;
@@ -117,7 +156,7 @@
 
                 omap3_pmx_core: pinmux@48002030 {
                         compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002030 0x05cc>;
+                        reg = <0x48002030 0x0238>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         #interrupt-cells = <1>;
@@ -632,3 +671,5 @@
                 };
         };
 };
+
+/include/ "omap3xxx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 000000000000..02f6c7fabbec
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        gfx_l3_ck: gfx_l3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        gfx_l3_fck: gfx_l3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,max-div = <7>;
+                reg = <0x0b40>;
+                ti,index-starts-at-one;
+        };
+
+        gfx_l3_ick: gfx_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&gfx_l3_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gfx_cg1_ck: gfx_cg1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <1>;
+        };
+
+        gfx_cg2_ck: gfx_cg2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <2>;
+        };
+
+        d2d_26m_fck: d2d_26m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <3>;
+        };
+
+        fshostusb_fck: fshostusb_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <5>;
+        };
+
+        ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
+        };
+
+        ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        fac_ick: fac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <8>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es1: ssi_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usb_l4_gate_ick: usb_l4_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <5>;
+                reg = <0x0a10>;
+        };
+
+        usb_l4_div_ick: usb_l4_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <4>;
+                ti,max-div = <1>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        usb_l4_ick: usb_l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+        };
+
+        dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es1: dss_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
+        };
+
+        gfx_3430es1_clkdm: gfx_3430es1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&d2d_26m_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..b02017b7630e
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Device Tree Source for OMAP34XX/OMAP36XX clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        security_l4_ick2: security_l4_ick2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes1_ick: aes1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                ti,bit-shift = <3>;
+                reg = <0x0a14>;
+        };
+
+        rng_ick: rng_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <2>;
+        };
+
+        sha11_ick: sha11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <1>;
+        };
+
+        des1_ick: des1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <0>;
+        };
+
+        cam_mclk: cam_mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0f00>;
+                ti,set-rate-parent;
+        };
+
+        cam_ick: cam_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0f10>;
+                ti,bit-shift = <0>;
+        };
+
+        csi2_96m_fck: csi2_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0f00>;
+                ti,bit-shift = <1>;
+        };
+
+        security_l3_ick: security_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pka_ick: pka_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l3_ick>;
+                reg = <0x0a14>;
+                ti,bit-shift = <4>;
+        };
+
+        icr_ick: icr_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <29>;
+        };
+
+        des2_ick: des2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <26>;
+        };
+
+        mspro_ick: mspro_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        mailboxes_ick: mailboxes_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <7>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sr1_fck: sr1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <6>;
+        };
+
+        sr2_fck: sr2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <7>;
+        };
+
+        sr_l4_ick: sr_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll2_fck: dpll2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0040>;
+                ti,index-starts-at-one;
+        };
+
+        dpll2_ck: dpll2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll2_fck>;
+                reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+                ti,low-power-stop;
+                ti,lock;
+                ti,low-power-bypass;
+        };
+
+        dpll2_m2_ck: dpll2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0044>;
+                ti,index-starts-at-one;
+        };
+
+        iva2_ck: iva2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll2_m2_ck>;
+                reg = <0x0000>;
+                ti,bit-shift = <0>;
+        };
+
+        modem_fck: modem_fck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <31>;
+        };
+
+        sad2d_ick: sad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <3>;
+        };
+
+        mad2d_ick: mad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <3>;
+        };
+
+        mspro_fck: mspro_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        cam_clkdm: cam_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cam_ick>, <&csi2_96m_fck>;
+        };
+
+        iva2_clkdm: iva2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&iva2_ck>;
+        };
+
+        dpll2_clkdm: dpll2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll2_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+                         <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+                         <&mspro_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 5355d6173748..2e92360da1f3 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -25,4 +25,21 @@
                         clock-latency = <300000>; /* From legacy driver */
                 };
         };
+
+        ocp {
+                omap3_pmx_core2: pinmux@480025d8 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x480025d8 0x24>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0xff1f>;
+                };
+        };
 };
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..af9ae5346bf2
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,242 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        corex2_d3_fck: corex2_d3_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        corex2_d5_fck: corex2_d5_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <5>;
+        };
+};
+&cm_clocks {
+        dpll5_ck: dpll5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+                ti,low-power-stop;
+                ti,lock;
+        };
+
+        dpll5_m2_ck: dpll5_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll5_ck>;
+                ti,max-div = <31>;
+                reg = <0x0d50>;
+                ti,index-starts-at-one;
+        };
+
+        sgx_gate_fck: sgx_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0b00>;
+        };
+
+        core_d3_ck: core_d3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        core_d4_ck: core_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        core_d6_ck: core_d6_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <6>;
+        };
+
+        omap_192m_alwon_fck: omap_192m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_d2_ck: core_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        sgx_mux_fck: sgx_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+                reg = <0x0b40>;
+        };
+
+        sgx_fck: sgx_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+        };
+
+        sgx_ick: sgx_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        cpefuse_fck: cpefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <0>;
+        };
+
+        ts_fck: ts_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_32k_fck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <1>;
+        };
+
+        usbtll_fck: usbtll_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <2>;
+        };
+
+        usbtll_ick: usbtll_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <2>;
+        };
+
+        mmchs3_ick: mmchs3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <30>;
+        };
+
+        mmchs3_fck: mmchs3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <30>;
+        };
+
+        dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es2: dss_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_120m_fck: usbhost_120m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x1400>;
+                ti,bit-shift = <1>;
+        };
+
+        usbhost_48m_fck: usbhost_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&omap_48m_fck>;
+                reg = <0x1400>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_ick: usbhost_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x1410>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        dpll5_clkdm: dpll5_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll5_ck>;
+        };
+
+        sgx_clkdm: sgx_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sgx_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+        };
+
+        usbhost_clkdm: usbhost_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+                         <&usbhost_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..2fcf253b677c
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-j-type-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-rate-parent;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        uart4_fck: uart4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <18>;
+        };
+};
+
+&cm_clockdomains {
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>, <&uart4_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..8ed475dd63c9
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+        };
+
+        ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es2>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-hsotgusb-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es2: ssi_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-ssi-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usim_gate_fck: usim_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&omap_96m_fck>;
+                ti,bit-shift = <9>;
+                reg = <0x0c00>;
+        };
+
+        sys_d2_ck: sys_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d2_fck: omap_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d4_fck: omap_96m_d4_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        omap_96m_d8_fck: omap_96m_d8_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        omap_96m_d10_fck: omap_96m_d10_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <20>;
+        };
+
+        usim_mux_fck: usim_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        usim_fck: usim_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+        };
+
+        usim_ick: usim_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <9>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&usim_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&ssi_ick_3430es2>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 380c22eb468e..7e8dee9175d6 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -38,5 +38,21 @@
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
+
+                omap3_pmx_core2: pinmux@480025a0 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x480025a0 0x5c>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0xff1f>;
+                };
         };
 };
+
+/include/ "omap36xx-clocks.dtsi"
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 000000000000..cb04d4b37e7f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1660 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        virt_16_8m_ck: virt_16_8m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        osc_sys_ck: osc_sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+                reg = <0x0d40>;
+        };
+
+        sys_ck: sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&osc_sys_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1270>;
+                ti,index-starts-at-one;
+        };
+
+        sys_clkout1: sys_clkout1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&osc_sys_ck>;
+                reg = <0x0d70>;
+                ti,bit-shift = <7>;
+        };
+
+        dpll3_x2_ck: dpll3_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m2x2_ck: dpll3_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_x2_ck: dpll4_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        corex2_fck: corex2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkup_l4_ick: wkup_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&scrm_clocks {
+        mcbsp5_mux_fck: mcbsp5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp5_fck: mcbsp5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+        };
+
+        mcbsp1_mux_fck: mcbsp1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x0274>;
+        };
+
+        mcbsp1_fck: mcbsp1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+        };
+
+        mcbsp2_mux_fck: mcbsp2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <6>;
+                reg = <0x0274>;
+        };
+
+        mcbsp2_fck: mcbsp2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+        };
+
+        mcbsp3_mux_fck: mcbsp3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp3_fck: mcbsp3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+        };
+
+        mcbsp4_mux_fck: mcbsp4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp4_fck: mcbsp4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+        };
+};
+&cm_clocks {
+        dummy_apb_pclk: dummy_apb_pclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        omap_32k_fck: omap_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12m_ck: virt_12m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13m_ck: virt_13m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_38_4m_ck: virt_38_4m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m2_ck: dpll4_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0d48>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_96m_alwon_fck: omap_96m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll3_ck: dpll3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-core-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+        };
+
+        dpll3_m3_ck: dpll3_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <31>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_core_alwon_ck: emu_core_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sys_altclk: sys_altclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        mcbsp_clks: mcbsp_clks {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        dpll3_m2_ck: dpll3_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <31>;
+                reg = <0x0d40>;
+                ti,index-starts-at-one;
+        };
+
+        core_ck: core_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll1_fck: dpll1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0940>;
+                ti,index-starts-at-one;
+        };
+
+        dpll1_ck: dpll1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll1_fck>;
+                reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+        };
+
+        dpll1_x2_ck: dpll1_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll1_x2m2_ck: dpll1_x2m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll1_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0944>;
+                ti,index-starts-at-one;
+        };
+
+        cm_96m_fck: cm_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        omap_96m_fck: omap_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0d40>;
+        };
+
+        dpll4_m3_ck: dpll4_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_54m_fck: omap_54m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+                ti,bit-shift = <5>;
+                reg = <0x0d40>;
+        };
+
+        cm_96m_d2_fck: cm_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cm_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_48m_fck: omap_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+                ti,bit-shift = <3>;
+                reg = <0x0d40>;
+        };
+
+        omap_12m_fck: omap_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll4_m4_ck: dpll4_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m4x2_ck: dpll4_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_mul_ck>;
+                ti,bit-shift = <0x1d>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m5_ck: dpll4_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0f40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m5_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6_ck: dpll4_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <63>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_per_alwon_ck: emu_per_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        clkout2_src_gate_ck: clkout2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_mux_ck: clkout2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_ck: clkout2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+        };
+
+        sys_clkout2: sys_clkout2 {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&clkout2_src_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <64>;
+                reg = <0x0d70>;
+                ti,index-power-of-two;
+        };
+
+        mpu_ck: mpu_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_x2m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        arm_fck: arm_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mpu_ck>;
+                reg = <0x0924>;
+                ti,max-div = <2>;
+        };
+
+        emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_ick: l3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        l4_ick: l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,bit-shift = <2>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        rm_ick: rm_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <1>;
+                ti,max-div = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        gpt10_gate_fck: gpt10_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0a00>;
+        };
+
+        gpt10_mux_fck: gpt10_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0a40>;
+        };
+
+        gpt10_fck: gpt10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+        };
+
+        gpt11_gate_fck: gpt11_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0a00>;
+        };
+
+        gpt11_mux_fck: gpt11_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0a40>;
+        };
+
+        gpt11_fck: gpt11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+        };
+
+        core_96m_fck: core_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_fck: mmchs2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_fck: mmchs1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <24>;
+        };
+
+        i2c3_fck: i2c3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_fck: i2c2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_fck: i2c1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <15>;
+        };
+
+        mcbsp5_gate_fck: mcbsp5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <10>;
+                reg = <0x0a00>;
+        };
+
+        mcbsp1_gate_fck: mcbsp1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <9>;
+                reg = <0x0a00>;
+        };
+
+        core_48m_fck: core_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcspi4_fck: mcspi4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_fck: mcspi3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_fck: mcspi2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_fck: mcspi1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <18>;
+        };
+
+        uart2_fck: uart2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_fck: uart1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <13>;
+        };
+
+        core_12m_fck: core_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_12m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdq_fck: hdq_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_12m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <22>;
+        };
+
+        core_l3_ick: core_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sdrc_ick: sdrc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpmc_fck: gpmc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_l4_ick: core_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_ick: mmchs2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_ick: mmchs1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <24>;
+        };
+
+        hdq_ick: hdq_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <22>;
+        };
+
+        mcspi4_ick: mcspi4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_ick: mcspi3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_ick: mcspi2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_ick: mcspi1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <18>;
+        };
+
+        i2c3_ick: i2c3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_ick: i2c2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_ick: i2c1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <15>;
+        };
+
+        uart2_ick: uart2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_ick: uart1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <13>;
+        };
+
+        gpt11_ick: gpt11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <12>;
+        };
+
+        gpt10_ick: gpt10_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <11>;
+        };
+
+        mcbsp5_ick: mcbsp5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <10>;
+        };
+
+        mcbsp1_ick: mcbsp1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <9>;
+        };
+
+        omapctrl_ick: omapctrl_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <6>;
+        };
+
+        dss_tv_fck: dss_tv_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_54m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss_96m_fck: dss_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_96m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss2_alwon_fck: dss2_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <1>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        gpt1_gate_fck: gpt1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0c00>;
+        };
+
+        gpt1_mux_fck: gpt1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x0c40>;
+        };
+
+        gpt1_fck: gpt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+        };
+
+        aes2_ick: aes2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                ti,bit-shift = <28>;
+                reg = <0x0a10>;
+        };
+
+        wkup_32k_fck: wkup_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbck: gpio1_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <3>;
+        };
+
+        sha12_ick: sha12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <27>;
+        };
+
+        wdt2_fck: wdt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt2_ick: wdt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt1_ick: wdt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <4>;
+        };
+
+        gpio1_ick: gpio1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <3>;
+        };
+
+        omap_32ksync_ick: omap_32ksync_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <2>;
+        };
+
+        gpt12_ick: gpt12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpt1_ick: gpt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <0>;
+        };
+
+        per_96m_fck: per_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_48m_fck: per_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        uart3_fck: uart3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <11>;
+        };
+
+        gpt2_gate_fck: gpt2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1000>;
+        };
+
+        gpt2_mux_fck: gpt2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x1040>;
+        };
+
+        gpt2_fck: gpt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+        };
+
+        gpt3_gate_fck: gpt3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1000>;
+        };
+
+        gpt3_mux_fck: gpt3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1040>;
+        };
+
+        gpt3_fck: gpt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+        };
+
+        gpt4_gate_fck: gpt4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1000>;
+        };
+
+        gpt4_mux_fck: gpt4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1040>;
+        };
+
+        gpt4_fck: gpt4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+        };
+
+        gpt5_gate_fck: gpt5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1000>;
+        };
+
+        gpt5_mux_fck: gpt5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1040>;
+        };
+
+        gpt5_fck: gpt5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+        };
+
+        gpt6_gate_fck: gpt6_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1000>;
+        };
+
+        gpt6_mux_fck: gpt6_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1040>;
+        };
+
+        gpt6_fck: gpt6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+        };
+
+        gpt7_gate_fck: gpt7_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1000>;
+        };
+
+        gpt7_mux_fck: gpt7_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1040>;
+        };
+
+        gpt7_fck: gpt7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+        };
+
+        gpt8_gate_fck: gpt8_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x1000>;
+        };
+
+        gpt8_mux_fck: gpt8_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1040>;
+        };
+
+        gpt8_fck: gpt8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+        };
+
+        gpt9_gate_fck: gpt9_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1000>;
+        };
+
+        gpt9_mux_fck: gpt9_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1040>;
+        };
+
+        gpt9_fck: gpt9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+        };
+
+        per_32k_alwon_fck: per_32k_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_dbck: gpio6_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_dbck: gpio5_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_dbck: gpio4_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_dbck: gpio3_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_dbck: gpio2_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_fck: wdt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <12>;
+        };
+
+        per_l4_ick: per_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_ick: gpio6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_ick: gpio5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_ick: gpio4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_ick: gpio3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_ick: gpio2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_ick: wdt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <12>;
+        };
+
+        uart3_ick: uart3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <11>;
+        };
+
+        uart4_ick: uart4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <18>;
+        };
+
+        gpt9_ick: gpt9_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <10>;
+        };
+
+        gpt8_ick: gpt8_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <9>;
+        };
+
+        gpt7_ick: gpt7_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <8>;
+        };
+
+        gpt6_ick: gpt6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <7>;
+        };
+
+        gpt5_ick: gpt5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <6>;
+        };
+
+        gpt4_ick: gpt4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <5>;
+        };
+
+        gpt3_ick: gpt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <4>;
+        };
+
+        gpt2_ick: gpt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <3>;
+        };
+
+        mcbsp2_ick: mcbsp2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <0>;
+        };
+
+        mcbsp3_ick: mcbsp3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <1>;
+        };
+
+        mcbsp4_ick: mcbsp4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <2>;
+        };
+
+        mcbsp2_gate_fck: mcbsp2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <0>;
+                reg = <0x1000>;
+        };
+
+        mcbsp3_gate_fck: mcbsp3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <1>;
+                reg = <0x1000>;
+        };
+
+        mcbsp4_gate_fck: mcbsp4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x1000>;
+        };
+
+        emu_src_mux_ck: emu_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                reg = <0x1140>;
+        };
+
+        emu_src_ck: emu_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&emu_src_mux_ck>;
+        };
+
+        pclk_fck: pclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        pclkx2_fck: pclkx2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        atclk_fck: atclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        traceclk_src_fck: traceclk_src_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1140>;
+        };
+
+        traceclk_fck: traceclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&traceclk_src_fck>;
+                ti,bit-shift = <11>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        secure_32k_fck: secure_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpt12_fck: gpt12_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>;
+        };
+
+        dpll3_clkdm: dpll3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll3_ck>;
+        };
+
+        dpll1_clkdm: dpll1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll1_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>;
+        };
+
+        emu_clkdm: emu_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&emu_src_ck>;
+        };
+
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
new file mode 100644
index 000000000000..cb9458feb2e3
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for OMAP4/5 SoC CPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+        polling-delay-passive = <250>; /* milliseconds */
+        polling-delay = <1000>; /* milliseconds */
+
+                        /* sensor       ID */
+        thermal-sensors = <&bandgap     0>;
+
+        trips {
+                cpu_alert0: cpu_alert {
+                        temperature = <100000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "passive";
+                };
+                cpu_crit: cpu_crit {
+                        temperature = <125000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+
+        cooling-maps {
+                map0 {
+                        trip = <&cpu_alert0>;
+                        cooling-device =
+                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e05853afcd..d3f8a6e8ca20 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                cm1: cm1@4a004000 {
+                        compatible = "ti,omap4-cm1";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm1_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm1_clockdomains: clockdomains {
+                        };
+                };
+
+                prm: prm@4a306000 {
+                        compatible = "ti,omap4-prm";
+                        reg = <0x4a306000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm2: cm2@4a008000 {
+                        compatible = "ti,omap4-cm2";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm2_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm2_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4a30a000 {
+                        compatible = "ti,omap4-scrm";
+                        reg = <0x4a30a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4a304000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4a304000 0x20>;
@@ -707,3 +759,5 @@
                 };
         };
 };
+
+/include/ "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000000000000..2bd2166f88d3
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        bandgap_fclk: bandgap_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index bcf455efe18d..8c1cfad30d60 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -12,7 +12,7 @@
 
 / {
         cpus {
-                cpu@0 {
+                cpu0: cpu@0 {
                         /* OMAP443x variants OPP50-OPPNT */
                         operating-points = <
                                 /* kHz    uV */
@@ -22,12 +22,27 @@
                                 1008000 1375000
                         >;
                         clock-latency = <300000>; /* From legacy driver */
+
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <3>;
+                        #cooling-cells = <2>; /* min followed by max */
                 };
         };
 
-        bandgap {
-                reg = <0x4a002260 0x4
-                       0x4a00232C 0x4>;
-                compatible = "ti,omap4430-bandgap";
+        thermal-zones {
+                #include "omap4-cpu-thermal.dtsi"
+        };
+
+        ocp {
+                bandgap: bandgap {
+                        reg = <0x4a002260 0x4
+                               0x4a00232C 0x4>;
+                        compatible = "ti,omap4430-bandgap";
+
+                        #thermal-sensor-cells = <0>;
+                };
         };
 };
+
+/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c2f0f39b5a24..6b32f520741a 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -12,7 +12,7 @@
 / {
         cpus {
                 /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
-                cpu@0 {
+                cpu0: cpu@0 {
                         operating-points = <
                                 /* kHz    uV */
                                 350000  1025000
@@ -20,6 +20,11 @@
                                 920000  1313000
                         >;
                         clock-latency = <300000>; /* From legacy driver */
+
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                 };
         };
 
@@ -30,12 +35,22 @@
                 ti,hwmods = "debugss";
         };
 
-        bandgap {
-                reg = <0x4a002260 0x4
-                       0x4a00232C 0x4
-                       0x4a002378 0x18>;
-                compatible = "ti,omap4460-bandgap";
-                interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
-                gpios = <&gpio3 22 0>; /* tshut */
+        thermal-zones {
+                #include "omap4-cpu-thermal.dtsi"
+        };
+
+        ocp {
+                bandgap: bandgap {
+                        reg = <0x4a002260 0x4
+                               0x4a00232C 0x4
+                               0x4a002378 0x18>;
+                        compatible = "ti,omap4460-bandgap";
+                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+                        gpios = <&gpio3 22 0>; /* tshut */
+
+                        #thermal-sensor-cells = <0>;
+                };
         };
 };
+
+/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 000000000000..be033e9803e9
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        div_ts_ck: div_ts_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        bandgap_ts_fclk: bandgap_ts_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&div_ts_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 000000000000..c821ff5e9b8d
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1651 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm1_clocks {
+        extalt_clkin_ck: extalt_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <59000000>;
+        };
+
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        tie_low_clock_ck: tie_low_clock_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60motg_ck: xclk60motg_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+                reg = <0x01f0>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x012c>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m6x2_ck: dpll_core_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ddrphy_ck: ddrphy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_m5x2_ck: dpll_core_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        div_core_ck: div_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        div_iva_hs_clk: div_iva_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x01dc>;
+                ti,index-power-of-two;
+        };
+
+        div_mpu_hs_clk: div_mpu_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        dpll_core_m4x2_ck: dpll_core_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dll_clk_div_ck: dll_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0134>;
+        };
+
+        dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+        };
+
+        dpll_core_m7x2_ck: dpll_core_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+                ti,bit-shift = <23>;
+                reg = <0x01ac>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_hs_clk_div_ck: per_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_div_ck: l3_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&div_core_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        l4_div_ck: l4_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        lp_clk_div_ck: lp_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        mpu_periphclk: mpu_periphclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ocp_abe_iclk: ocp_abe_iclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x0528>;
+                ti,dividers = <2>, <1>;
+        };
+
+        per_abe_24m_fclk: per_abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0538>;
+        };
+
+        func_dmic_abe_gfclk: func_dmic_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0540>;
+        };
+
+        func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0548>;
+        };
+
+        func_mcbsp1_gfclk: func_mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0550>;
+        };
+
+        func_mcbsp2_gfclk: func_mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0558>;
+        };
+
+        func_mcbsp3_gfclk: func_mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        slimbus1_fclk_1: slimbus1_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24m_clk>;
+                ti,bit-shift = <9>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_0: slimbus1_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&abe_24m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_2: slimbus1_fclk_2 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        timer5_sync_mux: timer5_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_sync_mux: timer6_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_sync_mux: timer7_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_sync_mux: timer8_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        dbgclk_mux_ck: dbgclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+                reg = <0x0108>;
+        };
+
+        syc_clk_div_ck: syc_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dmt1_clk_mux: dmt1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        usim_ck: usim_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+                ti,dividers = <14>, <18>;
+        };
+
+        usim_fclk: usim_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&usim_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1858>;
+        };
+
+        pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x1a20>;
+        };
+
+        pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x1a20>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_stm_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x1a20>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_div_ck: trace_clk_div_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_trace_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1a20>;
+                ti,dividers = <0>, <1>, <2>, <0>, <4>;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&trace_clk_div_div_ck>;
+        };
+};
+
+&prm_clockdomains {
+        emu_sys_clkdm: emu_sys_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&trace_clk_div_ck>;
+        };
+};
+
+&cm2_clocks {
+        per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x014c>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+                reg = <0x0150>;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0154>;
+        };
+
+        dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+        };
+
+        dpll_per_m4x2_ck: dpll_per_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m5x2_ck: dpll_per_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m6x2_ck: dpll_per_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m7x2_ck: dpll_per_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b4>;
+                ti,clock-mult = <1>;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ducati_clk_mux_ck: ducati_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+                reg = <0x0100>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_24mc_fclk: func_24mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <4>, <8>;
+        };
+
+        func_48mc_fclk: func_48mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_64m_fclk: func_64m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        init_60m_fclk: init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        per_abe_nc_fclk: per_abe_nc_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                reg = <0x0108>;
+                ti,max-div = <2>;
+        };
+
+        aes1_fck: aes1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a0>;
+        };
+
+        aes2_fck: aes2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a8>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&syc_clk_div_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_tv_clk: dss_tv_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&extalt_clkin_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m5x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+                ti,set-rate-parent;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_fck: dss_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1120>;
+        };
+
+        fdif_fck: fdif_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1028>;
+                ti,index-power-of-two;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1460>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1468>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1470>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1478>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1480>;
+        };
+
+        sgx_clk_mux: sgx_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        hsi_fck: hsi_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1338>;
+                ti,index-power-of-two;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1020>;
+        };
+
+        mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+                ti,bit-shift = <25>;
+                reg = <0x14e0>;
+        };
+
+        per_mcbsp4_gfclk: per_mcbsp4_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x14e0>;
+        };
+
+        hsmmc1_fclk: hsmmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        hsmmc2_fclk: hsmmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x13e0>;
+        };
+
+        sha2md5_fck: sha2md5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15c8>;
+        };
+
+        slimbus2_fclk_1: slimbus2_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_abe_24m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_fclk_0: slimbus2_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24mc_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_slimbus_clk: slimbus2_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_slimbus_core_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1538>;
+        };
+
+        smartreflex_core_fck: smartreflex_core_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0638>;
+        };
+
+        smartreflex_iva_fck: smartreflex_iva_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0630>;
+        };
+
+        smartreflex_mpu_fck: smartreflex_mpu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0628>;
+        };
+
+        cm2_dm10_mux: cm2_dm10_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1428>;
+        };
+
+        cm2_dm11_mux: cm2_dm11_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1430>;
+        };
+
+        cm2_dm2_mux: cm2_dm2_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1438>;
+        };
+
+        cm2_dm3_mux: cm2_dm3_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1440>;
+        };
+
+        cm2_dm4_mux: cm2_dm4_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1448>;
+        };
+
+        cm2_dm9_mux: cm2_dm9_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1450>;
+        };
+
+        usb_host_fs_fck: usb_host_fs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x13d0>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1358>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_func48mclk: usb_host_hs_func48mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <15>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_fck: usb_host_hs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x1358>;
+        };
+
+        otg_60m_gfclk: otg_60m_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_xclk: usb_otg_hs_xclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&otg_60m_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_ick: usb_otg_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1360>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_ick: usb_tll_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1368>;
+        };
+};
+
+&cm2_clockdomains {
+        l3_init_clkdm: l3_init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclk5_src_gate_ck: auxclk5_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_mux_ck: auxclk5_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_ck: auxclk5_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+        };
+
+        auxclk5_ck: auxclk5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk5_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0324>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+
+        auxclkreq4_ck: auxclkreq4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0220>;
+        };
+
+        auxclkreq5_ck: auxclkreq5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0224>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
new file mode 100644
index 000000000000..19212ac6eef0
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC CORE thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+core_thermal: core_thermal {
+        polling-delay-passive = <250>; /* milliseconds */
+        polling-delay = <1000>; /* milliseconds */
+
+                        /* sensor       ID */
+        thermal-sensors = <&bandgap     2>;
+
+        trips {
+                core_crit: core_crit {
+                        temperature = <125000>; /* milliCelsius */
+                        hysteresis = <2000>; /* milliCelsius */
+                        type = "critical";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
new file mode 100644
index 000000000000..1b87aca88b77
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC GPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+gpu_thermal: gpu_thermal {
+        polling-delay-passive = <250>; /* milliseconds */
+        polling-delay = <1000>; /* milliseconds */
+
+                        /* sensor       ID */
+        thermal-sensors = <&bandgap     1>;
+
+        trips {
+                gpu_crit: gpu_crit {
+                        temperature = <125000>; /* milliCelsius */
+                        hysteresis = <2000>; /* milliCelsius */
+                        type = "critical";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index fc3fad563861..a72813a9663e 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -49,6 +49,10 @@
                                 1000000 1060000
                                 1500000 1250000
                         >;
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -57,6 +61,12 @@
                 };
         };
 
+        thermal-zones {
+                #include "omap4-cpu-thermal.dtsi"
+                #include "omap5-gpu-thermal.dtsi"
+                #include "omap5-core-thermal.dtsi"
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
                 /* PPI secure/nonsecure IRQ */
@@ -107,6 +117,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,omap5-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a004000 {
+                        compatible = "ti,omap5-cm-core-aon";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4ae0a000 {
+                        compatible = "ti,omap5-scrm";
+                        reg = <0x4ae0a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,omap5-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -729,13 +791,17 @@
                         };
                 };
 
-                bandgap@4a0021e0 {
+                bandgap: bandgap@4a0021e0 {
                         reg = <0x4a0021e0 0xc
                                0x4a00232c 0xc
                                0x4a002380 0x2c
                                0x4a0023C0 0x3c>;
                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
                         compatible = "ti,omap5430-bandgap";
+
+                        #thermal-sensor-cells = <1>;
                 };
         };
 };
+
+/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 000000000000..d487fdab3921
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1399 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        abe_iclk: abe_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&abe_clk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h21x2_ck: dpll_core_h21x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        c2c_fclk: c2c_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h21x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        c2c_iclk: c2c_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&c2c_fclk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_h11x2_ck: dpll_core_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpu_l3_iclk: gpu_l3_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0538>;
+        };
+
+        dmic_gfclk: dmic_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0540>;
+        };
+
+        mcasp_gfclk: mcasp_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0548>;
+        };
+
+        mcbsp1_gfclk: mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0550>;
+        };
+
+        mcbsp2_gfclk: mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0558>;
+        };
+
+        mcbsp3_gfclk: mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin: sys_clkin {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dss_syc_gfclk_div: dss_syc_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1938>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1940>;
+        };
+};
+&cm_core_clocks {
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro1_ck: dpll_unipro1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro1_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro1_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro2_ck: dpll_unipro2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+        };
+
+        dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro2_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01d0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1420>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1420>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1420>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dss_syc_gfclk_div>;
+                ti,bit-shift = <10>;
+                reg = <0x1420>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1060>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1068>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1070>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1078>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1080>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1110>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1118>;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1320>;
+        };
+
+        lli_txphy_clk: lli_txphy_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x0f20>;
+        };
+
+        lli_txphy_ls_clk: lli_txphy_ls_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_m2_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0f20>;
+        };
+
+        mmc1_32khz_clk: mmc1_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1628>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin>;
+                ti,bit-shift = <8>;
+                reg = <0x1688>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <6>;
+                reg = <0x1658>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1658>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1658>;
+        };
+
+        usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x16f0>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1668>;
+        };
+
+        fdif_fclk: fdif_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1328>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1520>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1520>;
+        };
+
+        hsi_fclk: hsi_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1638>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1628>;
+        };
+
+        mmc1_fclk: mmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1628>;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1630>;
+        };
+
+        mmc2_fclk: mmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1630>;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1038>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1040>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1048>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1050>;
+        };
+};
+
+&cm_core_clockdomains {
+        l3init_clkdm: l3init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index aed83deaa991..5ed6c1376901 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -58,7 +58,6 @@
         status = "okay";
 
         ethphy: ethernet-phy {
-                device-type = "ethernet-phy";
                 reg = <8>;
         };
 };
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index e06c37e91ac6..174d89241f70 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -42,6 +42,25 @@
                         interrupts = <6>, <7>, <8>, <9>;
                 };
 
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <5>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
                 serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -60,15 +79,6 @@
                         status = "disabled";
                 };
 
-                spi@10600 {
-                        compatible = "marvell,orion-spi";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        reg = <0x10600 0x28>;
-                        status = "disabled";
-                };
-
                 wdt@20300 {
                         compatible = "marvell,orion-wdt";
                         reg = <0x20300 0x28>;
@@ -82,30 +92,6 @@
                         status = "disabled";
                 };
 
-                ehci@a0000 {
-                        compatible = "marvell,orion-ehci";
-                        reg = <0xa0000 0x1000>;
-                        interrupts = <12>;
-                        status = "disabled";
-                };
-
-                sata@80000 {
-                        compatible = "marvell,orion-sata";
-                        reg = <0x80000 0x5000>;
-                        interrupts = <29>;
-                        status = "disabled";
-                };
-
-                i2c@11000 {
-                        compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x11000 0x20>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <5>;
-                        clock-frequency = <100000>;
-                        status = "disabled";
-                };
-
                 xor@60900 {
                         compatible = "marvell,orion-xor";
                         reg = <0x60900 0x100
@@ -125,26 +111,6 @@
                         };
                 };
 
-                crypto@90000 {
-                        compatible = "marvell,orion-crypto";
-                        reg = <0x90000 0x10000>,
-                              <0xf2200000 0x800>;
-                        reg-names = "regs", "sram";
-                        interrupts = <28>;
-                        status = "okay";
-                };
-
-                mdio: mdio-bus@72004 {
-                        compatible = "marvell,orion-mdio";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x72004 0x84>;
-                        interrupts = <22>;
-                        status = "disabled";
-
-                        /* add phy nodes in board file */
-                };
-
                 eth: ethernet-controller@72000 {
                         compatible = "marvell,orion-eth";
                         #address-cells = <1>;
@@ -154,7 +120,6 @@
                         status = "disabled";
 
                         ethernet-port@0 {
-                                device_type = "network";
                                 compatible = "marvell,orion-eth-port";
                                 reg = <0>;
                                 /* overwrite MAC address in bootloader */
@@ -162,5 +127,39 @@
                                 /* set phy-handle property in board file */
                         };
                 };
+
+                mdio: mdio-bus@72004 {
+                        compatible = "marvell,orion-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x72004 0x84>;
+                        interrupts = <22>;
+                        status = "disabled";
+
+                        /* add phy nodes in board file */
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                crypto@90000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x90000 0x10000>,
+                              <0xf2200000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <28>;
+                        status = "okay";
+                };
+
+                ehci@a0000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xa0000 0x1000>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index daee58944e15..0e219932d7cc 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -29,6 +29,15 @@
                         timebase-frequency = <0>;
                         bus-frequency = <0>;
                         clock-frequency = <0>;
+                        clocks = <&clks 12>;
+                        operating-points = <
+                                /* kHz    uV */
+                                200000  1025000
+                                400000  1025000
+                                664000  1050000
+                                800000  1100000
+                        >;
+                        clock-latency = <150000>;
                 };
         };
 
@@ -80,6 +89,7 @@
                         cphifbg@88030000 {
                                 compatible = "sirf,prima2-cphifbg";
                                 reg = <0x88030000 0x1000>;
+                                clocks = <&clks 42>;
                         };
                 };
 
@@ -540,6 +550,18 @@
                                                         "usp0_uart_nostreamctrl";
                                         };
                                 };
+                                usp0_only_utfs_pins_a: usp0@2 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_utfs_grp";
+                                                sirf,function = "usp0_only_utfs";
+                                        };
+                                };
+                                usp0_only_urfs_pins_a: usp0@3 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_urfs_grp";
+                                                sirf,function = "usp0_only_urfs";
+                                        };
+                                };
                                 usp1_pins_a: usp1@0 {
                                         usp1 {
                                                 sirf,pins = "usp1grp";
@@ -648,6 +670,9 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56000000 0x100000>;
                                         interrupts = <38>;
+                                        status = "disabled";
+                                        bus-width = <8>;
+                                        clocks = <&clks 36>;
                                 };
 
                                 sd1: sdhci@56100000 {
@@ -655,6 +680,9 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56100000 0x100000>;
                                         interrupts = <38>;
+                                        status = "disabled";
+                                        bus-width = <4>;
+                                        clocks = <&clks 36>;
                                 };
 
                                 sd2: sdhci@56200000 {
@@ -662,6 +690,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56200000 0x100000>;
                                         interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
                                 };
 
                                 sd3: sdhci@56300000 {
@@ -669,6 +699,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56300000 0x100000>;
                                         interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
                                 };
 
                                 sd4: sdhci@56400000 {
@@ -676,6 +708,8 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56400000 0x100000>;
                                         interrupts = <39>;
+                                        status = "disabled";
+                                        clocks = <&clks 38>;
                                 };
 
                                 sd5: sdhci@56500000 {
@@ -683,6 +717,7 @@
                                         compatible = "sirf,prima2-sdhc";
                                         reg = <0x56500000 0x100000>;
                                         interrupts = <39>;
+                                        clocks = <&clks 38>;
                                 };
 
                                 pci-copy@57900000 {
@@ -716,6 +751,12 @@
                                 interrupts = <52 53 54>;
                         };
 
+                        minigpsrtc@2000 {
+                                compatible = "sirf,prima2-minigpsrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <54>;
+                        };
+
                         pwrc@3000 {
                                 compatible = "sirf,prima2-pwrc";
                                 reg = <0x3000 0x1000>;
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index d7c5d721a5c7..a70546945985 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -10,5 +10,29 @@
                         marvell,intc-priority;
                         marvell,intc-nr-irqs = <34>;
                 };
+
+                pwm0: pwm@40b00000 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40b00000 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm1: pwm@40b00010 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40b00010 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm2: pwm@40c00000 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40c00000 0x10>;
+                        #pwm-cells = <1>;
+                };
+
+                pwm3: pwm@40c00010 {
+                        compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
+                        reg = <0x40c00010 0x10>;
+                        #pwm-cells = <1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
new file mode 100644
index 000000000000..13ac3e222495
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -0,0 +1,6 @@
+#include "qcom-msm8974.dtsi"
+
+/ {
+        model = "Qualcomm APQ8074 Dragonboard";
+        compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
+};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 386d42870215..68a72f5507b9 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -2,6 +2,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+
 / {
         model = "Qualcomm MSM8660 SURF";
         compatible = "qcom,msm8660-surf", "qcom,msm8660";
@@ -28,20 +30,29 @@
 
         msmgpio: gpio@800000 {
                 compatible = "qcom,msm-gpio";
-                reg = <0x00800000 0x1000>;
+                reg = <0x00800000 0x4000>;
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpio = <173>;
-                interrupts = <0 32 0x4>;
+                interrupts = <0 16 0x4>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
         };
 
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8660";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+
         serial@19c40000 {
                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                 reg = <0x19c40000 0x1000>,
                       <0x19c00000 0x1000>;
                 interrupts = <0 195 0x0>;
+                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                clock-names = "core", "iface";
         };
 
         qcom,ssbi@500000 {
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 93e9f7e0b7ad..7c30de4fa302 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -2,6 +2,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+
 / {
         model = "Qualcomm MSM8960 CDP";
         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
@@ -31,17 +33,33 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 ngpio = <150>;
-                interrupts = <0 32 0x4>;
+                interrupts = <0 16 0x4>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
                 reg = <0x800000 0x4000>;
         };
 
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8960";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+
+        clock-controller@4000000 {
+                compatible = "qcom,mmcc-msm8960";
+                reg = <0x4000000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
         serial@16440000 {
                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                 reg = <0x16440000 0x1000>,
                       <0x16400000 0x1000>;
                 interrupts = <0 154 0x0>;
+                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                clock-names = "core", "iface";
         };
 
         qcom,ssbi@500000 {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
new file mode 100644
index 000000000000..9e5dadb101eb
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -0,0 +1,121 @@
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+
+/ {
+        model = "Qualcomm MSM8974";
+        compatible = "qcom,msm8974";
+        interrupt-parent = <&intc>;
+
+        soc: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+
+                intc: interrupt-controller@f9000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0xf9000000 0x1000>,
+                              <0xf9002000 0x1000>;
+                };
+
+                timer {
+                        compatible = "arm,armv7-timer";
+                        interrupts = <1 2 0xf08>,
+                                     <1 3 0xf08>,
+                                     <1 4 0xf08>,
+                                     <1 1 0xf08>;
+                        clock-frequency = <19200000>;
+                };
+
+                timer@f9020000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        compatible = "arm,armv7-timer-mem";
+                        reg = <0xf9020000 0x1000>;
+                        clock-frequency = <19200000>;
+
+                        frame@f9021000 {
+                                frame-number = <0>;
+                                interrupts = <0 8 0x4>,
+                                             <0 7 0x4>;
+                                reg = <0xf9021000 0x1000>,
+                                      <0xf9022000 0x1000>;
+                        };
+
+                        frame@f9023000 {
+                                frame-number = <1>;
+                                interrupts = <0 9 0x4>;
+                                reg = <0xf9023000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9024000 {
+                                frame-number = <2>;
+                                interrupts = <0 10 0x4>;
+                                reg = <0xf9024000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9025000 {
+                                frame-number = <3>;
+                                interrupts = <0 11 0x4>;
+                                reg = <0xf9025000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9026000 {
+                                frame-number = <4>;
+                                interrupts = <0 12 0x4>;
+                                reg = <0xf9026000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9027000 {
+                                frame-number = <5>;
+                                interrupts = <0 13 0x4>;
+                                reg = <0xf9027000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9028000 {
+                                frame-number = <6>;
+                                interrupts = <0 14 0x4>;
+                                reg = <0xf9028000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+
+                restart@fc4ab000 {
+                        compatible = "qcom,pshold";
+                        reg = <0xfc4ab000 0x4>;
+                };
+
+                gcc: clock-controller@fc400000 {
+                        compatible = "qcom,gcc-msm8974";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        reg = <0xfc400000 0x4000>;
+                };
+
+                mmcc: clock-controller@fd8c0000 {
+                        compatible = "qcom,mmcc-msm8974";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        reg = <0xfd8c0000 0x6000>;
+                };
+
+                serial@f991e000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0xf991e000 0x1000>;
+                        interrupts = <0 108 0x0>;
+                        clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
new file mode 100644
index 000000000000..da19c70ed82b
--- /dev/null
+++ b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
@@ -0,0 +1,31 @@
+/*
+ * Device Tree Source for the Genmai board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r7s72100.dtsi"
+
+/ {
+        model = "Genmai";
+        compatible = "renesas,genmai-reference", "renesas,r7s72100";
+
+        chosen {
+                bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x08000000 0x08000000>;
+        };
+
+        lbsc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 1fb20f2333cc..b1deaf7e2e06 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r7s72100.dtsi"
+#include "r7s72100.dtsi"
 
 / {
         model = "Genmai";
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 9443e93d3cac..70b1fff8f4a3 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a73a4.dtsi"
+#include "r8a73a4.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -25,6 +25,11 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
+        };
+
         vcc_mmc0: regulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "MMC0 Vcc";
@@ -88,22 +93,22 @@
         pinctrl-0 = <&scifa0_pins>;
         pinctrl-names = "default";
 
-        scifa0_pins: scifa0 {
+        scifa0_pins: serial0 {
                 renesas,groups = "scifa0_data";
                 renesas,function = "scifa0";
         };
 
-        mmc0_pins: mmcif {
+        mmc0_pins: mmc {
                 renesas,groups = "mmc0_data8", "mmc0_ctrl";
                 renesas,function = "mmc0";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
                 renesas,function = "sdhi0";
         };
 
-        sdhi1_pins: sdhi1 {
+        sdhi1_pins: sd1 {
                 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
                 renesas,function = "sdhi1";
         };
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 91436b58016f..ce085fa444a1 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -9,7 +9,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a73a4.dtsi"
+#include "r8a73a4.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "APE6EVM";
@@ -24,6 +25,11 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
+        };
+
         ape6evm_fixed_3v3: fixedregulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "3V3";
@@ -40,7 +46,7 @@
                         compatible = "smsc,lan9118", "smsc,lan9115";
                         reg = <0x08000000 0x1000>;
                         interrupt-parent = <&irqc1>;
-                        interrupts = <8 0x4>;
+                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
                         phy-mode = "mii";
                         reg-io-width = <4>;
                         smsc,irq-active-high;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 287e047592a0..62d0211bd192 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,9 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a73a4";
         interrupt-parent = <&gic>;
@@ -36,15 +39,15 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
@@ -53,14 +56,38 @@
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
-                                <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
-                                <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
-                                <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
-                                <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
-                                <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
-                                <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
-                                <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 4 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 5 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 6 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 7 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 8 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 10 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 11 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 14 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 15 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 17 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 18 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 19 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 20 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 21 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 22 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 23 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 24 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 25 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 26 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 27 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 28 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 29 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 31 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqc1: interrupt-controller@e61c0200 {
@@ -69,13 +96,32 @@
                 interrupt-controller;
                 reg = <0 0xe61c0200 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
-                                <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
-                                <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
-                                <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
-                                <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
-                                <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
-                                <0 56 4>, <0 57 4>;
+                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 38 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 39 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 40 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 43 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 44 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 45 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 46 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 47 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 48 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 49 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 50 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 51 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 52 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 53 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 56 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 57 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         dmac: dma-multiplexer@0 {
@@ -91,27 +137,27 @@
                         compatible = "renesas,shdma-r8a73a4";
                         reg = <0 0xe6700020 0 0x89e0>;
                         interrupt-parent = <&gic>;
-                        interrupts = <0 220 4
-                                        0 200 4
-                                        0 201 4
-                                        0 202 4
-                                        0 203 4
-                                        0 204 4
-                                        0 205 4
-                                        0 206 4
-                                        0 207 4
-                                        0 208 4
-                                        0 209 4
-                                        0 210 4
-                                        0 211 4
-                                        0 212 4
-                                        0 213 4
-                                        0 214 4
-                                        0 215 4
-                                        0 216 4
-                                        0 217 4
-                                        0 218 4
-                                        0 219 4>;
+                        interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                                        0 200 IRQ_TYPE_LEVEL_HIGH
+                                        0 201 IRQ_TYPE_LEVEL_HIGH
+                                        0 202 IRQ_TYPE_LEVEL_HIGH
+                                        0 203 IRQ_TYPE_LEVEL_HIGH
+                                        0 204 IRQ_TYPE_LEVEL_HIGH
+                                        0 205 IRQ_TYPE_LEVEL_HIGH
+                                        0 206 IRQ_TYPE_LEVEL_HIGH
+                                        0 207 IRQ_TYPE_LEVEL_HIGH
+                                        0 208 IRQ_TYPE_LEVEL_HIGH
+                                        0 209 IRQ_TYPE_LEVEL_HIGH
+                                        0 210 IRQ_TYPE_LEVEL_HIGH
+                                        0 211 IRQ_TYPE_LEVEL_HIGH
+                                        0 212 IRQ_TYPE_LEVEL_HIGH
+                                        0 213 IRQ_TYPE_LEVEL_HIGH
+                                        0 214 IRQ_TYPE_LEVEL_HIGH
+                                        0 215 IRQ_TYPE_LEVEL_HIGH
+                                        0 216 IRQ_TYPE_LEVEL_HIGH
+                                        0 217 IRQ_TYPE_LEVEL_HIGH
+                                        0 218 IRQ_TYPE_LEVEL_HIGH
+                                        0 219 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "error",
                                         "ch0", "ch1", "ch2", "ch3",
                                         "ch4", "ch5", "ch6", "ch7",
@@ -126,7 +172,7 @@
                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
                          <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 69 4>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6500000 {
@@ -135,7 +181,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6500000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 174 0x4>;
+                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -145,7 +191,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6510000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 175 0x4>;
+                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -155,7 +201,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6520000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 176 0x4>;
+                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -165,7 +211,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6530000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 177 0x4>;
+                interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -175,7 +221,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6540000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 178 0x4>;
+                interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -185,7 +231,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe60b0000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 179 0x4>;
+                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -195,7 +241,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6550000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 184 0x4>;
+                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -205,7 +251,7 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6560000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 185 0x4>;
+                interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -215,24 +261,24 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0 0xe6570000 0 0x428>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 173 0x4>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        mmcif0: mmcif@ee200000 {
+        mmcif0: mmc@ee200000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 169 0x4>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        mmcif1: mmcif@ee220000 {
+        mmcif1: mmc@ee220000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0 0xee220000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 170 0x4>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -242,31 +288,47 @@
                 reg = <0 0xe6050000 0 0x9000>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
+                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
+                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
+                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
+                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
+                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
+                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
+                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
+                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
+                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
+                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
+                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
+                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
+                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
+                        <&irqc1 24 0>, <&irqc1 25 0>;
         };
 
-        sdhi0: sdhi@ee100000 {
+        sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee100000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 165 4>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@ee120000 {
+        sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee120000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 166 4>;
+                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
+        sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-r8a73a4";
                 reg = <0 0xee140000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 1c56c5e56950..95a849bf921f 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -9,8 +9,9 @@
  */
 
 /dts-v1/;
-/include/ "r8a7740.dtsi"
+#include "r8a7740.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
@@ -62,6 +63,44 @@
                 enable-active-high;
         };
 
+        reg_5p0v: regulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5.0V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power-key {
+                        gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
+                        linux,code = <116>;
+                        label = "SW3";
+                        gpio-key,wakeup;
+                };
+
+                back-key {
+                        gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
+                        linux,code = <158>;
+                        label = "SW4";
+                };
+
+                menu-key {
+                        gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
+                        linux,code = <139>;
+                        label = "SW5";
+                };
+
+                home-key {
+                        gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
+                        linux,code = <102>;
+                        label = "SW6";
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 led1 {
@@ -85,32 +124,58 @@
                 default-brightness-level = <9>;
                 pinctrl-0 = <&backlight_pins>;
                 pinctrl-names = "default";
+                power-supply = <&reg_5p0v>;
+                enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,format = "i2s";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                        bitclock-inversion;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&wm8978>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <12288000>;
+                };
         };
 };
 
 &i2c0 {
         status = "okay";
-        touchscreen: st1232@55 {
+        touchscreen@55 {
                 compatible = "sitronix,st1232";
                 reg = <0x55>;
                 interrupt-parent = <&irqpin1>;
-                interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                 pinctrl-0 = <&st1232_pins>;
                 pinctrl-names = "default";
                 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
         };
+
+        wm8978: wm8978@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8978";
+                reg = <0x1a>;
+        };
 };
 
 &pfc {
         pinctrl-0 = <&scifa1_pins>;
         pinctrl-names = "default";
 
-        scifa1_pins: scifa1 {
+        scifa1_pins: serial1 {
                 renesas,groups = "scifa1_data";
                 renesas,function = "scifa1";
         };
 
-        st1232_pins: st1232 {
+        st1232_pins: touchscreen {
                 renesas,groups = "intc_irq10";
                 renesas,function = "intc";
         };
@@ -125,10 +190,16 @@
                 renesas,function = "mmc0";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
                 renesas,function = "sdhi0";
         };
+
+        fsia_pins: sounda {
+                renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
+                                 "fsia_data_in_1", "fsia_data_out_0";
+                renesas,function = "fsia";
+        };
 };
 
 &tpu {
@@ -155,3 +226,10 @@
         cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
+
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 426cd9c3e1c4..a06a11e1a840 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7740.dtsi"
+#include "r8a7740.dtsi"
 
 / {
         model = "armadillo 800 eva";
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ae1e230f711d..8280884bfa59 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7740";
 
@@ -34,12 +36,12 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 83 4>;
+                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin0: IRQ0 - IRQ7 */
         irqpin0: irqpin@e6900000 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900000 4>,
@@ -48,19 +50,19 @@
                         <0xe6900040 1>,
                         <0xe6900060 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin1: IRQ8 - IRQ15 */
         irqpin1: irqpin@e6900004 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900004 4>,
@@ -69,19 +71,19 @@
                         <0xe6900044 1>,
                         <0xe6900064 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin2: IRQ16 - IRQ23 */
         irqpin2: irqpin@e6900008 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900008 4>,
@@ -90,19 +92,19 @@
                         <0xe6900048 1>,
                         <0xe6900068 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         /* irqpin3: IRQ24 - IRQ31 */
         irqpin3: irqpin@e690000c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe690000c 4>,
@@ -111,14 +113,14 @@
                         <0xe690004c 1>,
                         <0xe690006c 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4
-                              0 149 0x4>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH
+                              0 149 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@fff20000 {
@@ -127,10 +129,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xfff20000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 201 0x4
-                              0 202 0x4
-                              0 203 0x4
-                              0 204 0x4>;
+                interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
+                              0 202 IRQ_TYPE_LEVEL_HIGH
+                              0 203 IRQ_TYPE_LEVEL_HIGH
+                              0 204 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -140,10 +142,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6c20000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 70 0x4
-                              0 71 0x4
-                              0 72 0x4
-                              0 73 0x4>;
+                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
+                              0 71 IRQ_TYPE_LEVEL_HIGH
+                              0 72 IRQ_TYPE_LEVEL_HIGH
+                              0 73 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -153,6 +155,15 @@
                       <0xe605800c 0x20>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
+                        <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
+                        <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
+                        <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
+                        <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
+                        <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
+                        <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
+                        <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
         };
 
         tpu: pwm@e6600000 {
@@ -162,36 +173,57 @@
                 #pwm-cells = <3>;
         };
 
-        mmcif0: mmcif@e6bd0000 {
+        mmcif0: mmc@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 56 4
-                                0 57 4>;
+                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
+                              0 57 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        sdhi0: sdhi@e6850000 {
+        sdhi0: sd@e6850000 {
                 compatible = "renesas,sdhi-r8a7740";
                 reg = <0xe6850000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 117 4
-                                0 118 4
-                                0 119 4>;
+                interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
+                              0 118 IRQ_TYPE_LEVEL_HIGH
+                              0 119 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@e6860000 {
+        sdhi1: sd@e6860000 {
                 compatible = "renesas,sdhi-r8a7740";
                 reg = <0xe6860000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 121 4
-                                0 122 4
-                                0 123 4>;
+                interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
+                              0 122 IRQ_TYPE_LEVEL_HIGH
+                              0 123 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@e6870000 {
+                compatible = "renesas,sdhi-r8a7740";
+                reg = <0xe6870000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
+                              0 126 IRQ_TYPE_LEVEL_HIGH
+                              0 127 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
         };
+
+        sh_fsi2: sound@fe1f0000 {
+                #sound-dai-cells = <1>;
+                compatible = "renesas,sh_fsi2";
+                reg = <0xfe1f0000 0x400>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 9 0x4>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 969e386e852c..bb62c7a906f4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -15,7 +15,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7778.dtsi"
+#include "r8a7778.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "bockw";
@@ -45,13 +46,65 @@
 
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin>;
-                interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 vddvario-supply = <&fixedregulator3v3>;
                 vdd33a-supply = <&fixedregulator3v3>;
         };
+
+};
+
+&mmcif {
+        pinctrl-0 = <&mmc_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <8>;
+        broken-cd;
+        status = "okay";
 };
 
 &irqpin {
         status = "okay";
 };
+
+&pfc {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_a", "scif0_ctrl";
+                renesas,function = "scif0";
+        };
+
+        mmc_pins: mmc {
+                renesas,groups = "mmc_data8", "mmc_ctrl";
+                renesas,function = "mmc";
+        };
+
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
+                                  "sdhi0_cd", "sdhi0_wp";
+                renesas,function = "sdhi0";
+        };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0_a";
+                renesas,function = "hspi0";
+        };
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 12bbebc9c955..46a884d45175 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -15,7 +15,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7778.dtsi"
+#include "r8a7778.dtsi"
 
 / {
         model = "bockw";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index a6308a399e2d..ddb3bd7a8838 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7778";
 
@@ -25,6 +27,12 @@
                 };
         };
 
+        aliases {
+                spi0 = &hspi0;
+                spi1 = &hspi1;
+                spi2 = &hspi2;
+        };
+
         gic: interrupt-controller@fe438000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -35,7 +43,7 @@
 
         /* irqpin: IRQ0 - IRQ3 */
         irqpin: irqpin@fe78001c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 status = "disabled"; /* default off */
@@ -45,10 +53,10 @@
                         <0xfe780044 4>,
                         <0xfe780064 4>;
                 interrupt-parent = <&gic>;
-                interrupts =   <0 27 0x4
-                                0 28 0x4
-                                0 29 0x4
-                                0 30 0x4>;
+                interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
+                                0 28 IRQ_TYPE_LEVEL_HIGH
+                                0 29 IRQ_TYPE_LEVEL_HIGH
+                                0 30 IRQ_TYPE_LEVEL_HIGH>;
                 sense-bitfield-width = <2>;
         };
 
@@ -56,7 +64,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc40000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -68,7 +76,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc41000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -80,7 +88,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc42000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -92,7 +100,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc43000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -104,7 +112,7 @@
                 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                 reg = <0xffc44000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 103 0x4>;
+                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 27>;
@@ -114,6 +122,148 @@
 
         pfc: pfc@fffc0000 {
                 compatible = "renesas,pfc-r8a7778";
-                reg = <0xfffc000 0x118>;
+                reg = <0xfffc0000 0x118>;
+        };
+
+        i2c0: i2c@ffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@ffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@ffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c3: i2c@ffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        mmcif: mmc@ffe4e000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0xffe4e000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        sdhi0: sd@ffe4c000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4c000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi1: sd@ffe4d000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4d000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@ffe4f000 {
+                compatible = "renesas,sdhi-r8a7778";
+                reg = <0xffe4f000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        i2c0: i2c@ffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@ffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@ffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        i2c3: i2c@ffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7778";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi0: spi@fffc7000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc7000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi1: spi@fffc8000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc8000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi2: spi@fffc6000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc6000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index ab4110aa3c3b..76f5eef7d1cc 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -10,8 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "r8a7779.dtsi"
+#include "r8a7779.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "marzen";
@@ -43,7 +44,7 @@
 
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin0>;
-                interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 vddvario-supply = <&fixedregulator3v3>;
                 vdd33a-supply = <&fixedregulator3v3>;
@@ -68,7 +69,7 @@
 };
 
 &pfc {
-        pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
+        pinctrl-0 = <&scif2_pins &scif4_pins>;
         pinctrl-names = "default";
 
         lan0_pins: lan0 {
@@ -82,19 +83,38 @@
                 };
         };
 
-        scif2_pins: scif2 {
+        scif2_pins: serial2 {
                 renesas,groups = "scif2_data_c";
                 renesas,function = "scif2";
         };
 
-        scif4_pins: scif4 {
+        scif4_pins: serial4 {
                 renesas,groups = "scif4_data";
                 renesas,function = "scif4";
         };
 
-        sdhi0_pins: sdhi0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd",
-                                 "sdhi0_wp";
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
                 renesas,function = "sdhi0";
         };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0";
+                renesas,function = "hspi0";
+        };
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index f3f7f7999736..a7af2c2371f2 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "r8a7779.dtsi"
+#include "r8a7779.dtsi"
 
 / {
         model = "marzen";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 19faeac3fd2e..d0561d4c7c46 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7779";
 
@@ -40,6 +42,12 @@
                 };
         };
 
+        aliases {
+                spi0 = &hspi0;
+                spi1 = &hspi1;
+                spi2 = &hspi2;
+        };
+
         gic: interrupt-controller@f0001000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -52,7 +60,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc40000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 141 0x4>;
+                interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -64,7 +72,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc41000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 142 0x4>;
+                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -76,7 +84,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc42000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 143 0x4>;
+                interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -88,7 +96,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc43000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 144 0x4>;
+                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -100,7 +108,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc44000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 145 0x4>;
+                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 32>;
@@ -112,7 +120,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc45000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 146 0x4>;
+                interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 160 32>;
@@ -124,7 +132,7 @@
                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                 reg = <0xffc46000 0x2c>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 147 0x4>;
+                interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 192 9>;
@@ -133,7 +141,7 @@
         };
 
         irqpin0: irqpin@fe780010 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 status = "disabled";
                 interrupt-controller;
@@ -143,50 +151,50 @@
                         <0xfe780044 4>,
                         <0xfe780064 4>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 27 0x4
-                                0 28 0x4
-                                0 29 0x4
-                                0 30 0x4>;
+                interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
+                              0 28 IRQ_TYPE_LEVEL_HIGH
+                              0 29 IRQ_TYPE_LEVEL_HIGH
+                              0 30 IRQ_TYPE_LEVEL_HIGH>;
                 sense-bitfield-width = <2>;
         };
 
         i2c0: i2c@ffc70000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc70000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 79 0x4>;
+                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c1: i2c@ffc71000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc71000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 82 0x4>;
+                interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c2: i2c@ffc72000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc72000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 80 0x4>;
+                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
         i2c3: i2c@ffc73000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc73000 0x1000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 81 0x4>;
+                interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -204,6 +212,70 @@
                 compatible = "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 100 0x4>;
+                interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        sdhi0: sd@ffe4c000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4c000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi1: sd@ffe4d000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4d000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi2: sd@ffe4e000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4e000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        sdhi3: sd@ffe4f000 {
+                compatible = "renesas,sdhi-r8a7779";
+                reg = <0xffe4f000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                cap-sd-highspeed;
+                cap-sdio-irq;
+                status = "disabled";
+        };
+
+        hspi0: spi@fffc7000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc7000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi1: spi@fffc8000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc8000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        hspi2: spi@fffc6000 {
+                compatible = "renesas,hspi";
+                reg = <0xfffc6000 0x18>;
+                interrupt-controller = <&gic>;
+                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts
deleted file mode 100644
index c462ef138922..000000000000
--- a/arch/arm/boot/dts/r8a7790-lager-reference.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Device Tree Source for the Lager board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "r8a7790.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-        model = "Lager";
-        compatible = "renesas,lager-reference", "renesas,r8a7790";
-
-        chosen {
-                bootargs = "console=ttySC6,115200 ignore_loglevel rw";
-        };
-
-        memory@40000000 {
-                device_type = "memory";
-                reg = <0 0x40000000 0 0x80000000>;
-        };
-
-        lbsc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                led6 {
-                        gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-                };
-                led7 {
-                        gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
-                };
-                led8 {
-                        gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 203bd089af29..57569cba1528 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,7 +9,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7790.dtsi"
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Lager";
@@ -24,8 +25,69 @@
                 reg = <0 0x40000000 0 0x80000000>;
         };
 
+        memory@180000000 {
+                device_type = "memory";
+                reg = <1 0x80000000 0 0x80000000>;
+        };
+
         lbsc {
                 #address-cells = <1>;
                 #size-cells = <1>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data";
+                renesas,function = "scif1";
+        };
+
+        mmc1_pins: mmc1 {
+                renesas,groups = "mmc1_data8", "mmc1_ctrl";
+                renesas,function = "mmc1";
+        };
+};
+
+&mmcif1 {
+        pinctrl-0 = <&mmc1_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 9987dd0e9c59..71b1251f79c7 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,10 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7790-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7790";
         interrupt-parent = <&gic>;
@@ -84,14 +88,14 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         gpio0: gpio@e6050000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6050000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 4 0x4>;
+                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -103,7 +107,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6051000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 5 0x4>;
+                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -115,7 +119,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6052000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 6 0x4>;
+                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -127,7 +131,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6053000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 7 0x4>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -139,7 +143,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6054000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 8 0x4>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 32>;
@@ -151,7 +155,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6055000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 9 0x4>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 160 32>;
@@ -159,21 +163,31 @@
                 interrupt-controller;
         };
 
+        thermal@e61f0000 {
+                compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a7790", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6508000 {
@@ -182,7 +196,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6508000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 287 0x4>;
+                interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
                 status = "disabled";
         };
 
@@ -192,7 +207,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6518000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 288 0x4>;
+                interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
                 status = "disabled";
         };
 
@@ -202,7 +218,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6530000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 286 0x4>;
+                interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
                 status = "disabled";
         };
 
@@ -212,24 +229,27 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6540000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 290 0x4>;
+                interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
                 status = "disabled";
         };
 
         mmcif0: mmcif@ee200000 {
-                compatible = "renesas,sh-mmcif";
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 169 0x4>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        mmcif1: mmcif@ee220000 {
-                compatible = "renesas,sh-mmcif";
+        mmcif1: mmc@ee220000 {
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee220000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 170 0x4>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -239,39 +259,372 @@
                 reg = <0 0xe6060000 0 0x250>;
         };
 
-        sdhi0: sdhi@ee100000 {
+        sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee100000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 165 4>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@ee120000 {
+        sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee120000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 166 4>;
+                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
+        sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee140000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi3: sdhi@ee160000 {
+        sdhi3: sd@ee160000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee160000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 168 4>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7790-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "sd1",
+                                             "z";
+                };
+
+                /* Variable factor clocks */
+                sd2_clk: sd2_clk@e6150078 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd2";
+                };
+                sd3_clk: sd3_clk@e615007c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd3";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                mmc1_clk: mmc1_clk@e6150244 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150244 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc1";
+                };
+                ssp_clk: ssp_clk@e6150248 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150248 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssp";
+                };
+                ssprs_clk: ssprs_clk@e615024c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615024c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssprs";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                z2_clk: z2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "z2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
+                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
+                                R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
+                                R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+                                "scifb1", "msiof1", "msiof3", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                                 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                                 <&mmc0_clk>, <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                                R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                                "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        clock-output-names = "thermal", "pwm";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                                 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
+                                 <&zx_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
+                                R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
+                                R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
+                                R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
+                        >;
+                        clock-output-names =
+                                "ehci", "hsusb", "hscif1", "hscif0", "scif1",
+                                "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_ETHER>;
+                        clock-output-names = "ether";
+                };
+                mstp9_clks: mstp9_clks@e6150994 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
+                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
+                                R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
+                                R8A7790_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
new file mode 100644
index 000000000000..588ca17ea1f0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree Source for the Koelsch board
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Koelsch";
+        compatible = "renesas,koelsch-reference", "renesas,r8a7791";
+
+        chosen {
+                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x80000000>;
+        };
+
+        lbsc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                key-a {
+                        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <30>;
+                        label = "SW30";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-b {
+                        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <48>;
+                        label = "SW31";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-c {
+                        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <46>;
+                        label = "SW32";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-d {
+                        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <32>;
+                        label = "SW33";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-e {
+                        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <18>;
+                        label = "SW34";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-f {
+                        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <33>;
+                        label = "SW35";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-g {
+                        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+                        linux,code = <34>;
+                        label = "SW36";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_d";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data_d";
+                renesas,function = "scif1";
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 1ce5250ec278..fd556c3483e3 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,7 +10,8 @@
  */
 
 /dts-v1/;
-/include/ "r8a7791.dtsi"
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Koelsch";
@@ -29,4 +30,36 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+                led6 {
+                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                };
+                led7 {
+                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                };
+                led8 {
+                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&pfc {
+        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-names = "default";
+
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_d";
+                renesas,function = "scif0";
+        };
+
+        scif1_pins: serial1 {
+                renesas,groups = "scif1_data_d";
+                renesas,function = "scif1";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index fea5cfef4691..19c65509a22d 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -9,6 +9,10 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7791-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7791";
         interrupt-parent = <&gic>;
@@ -43,32 +47,463 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        gpio0: gpio@e6050000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6050000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 0 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio1: gpio@e6051000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6051000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 32 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio2: gpio@e6052000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6052000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 64 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio3: gpio@e6053000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6053000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 96 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio4: gpio@e6054000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6054000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 128 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio5: gpio@e6055000 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055000 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 160 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio6: gpio@e6055400 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055400 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 192 32>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        gpio7: gpio@e6055800 {
+                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
+                reg = <0 0xe6055800 0 0x50>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 224 26>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+        };
+
+        thermal@e61f0000 {
+                compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
+                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a7791", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>,
-                              <0 1 4>,
-                              <0 2 4>,
-                              <0 3 4>,
-                              <0 12 4>,
-                              <0 13 4>,
-                              <0 14 4>,
-                              <0 15 4>,
-                              <0 16 4>,
-                              <0 17 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 14 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 15 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        pfc: pfc@e6060000 {
+                compatible = "renesas,pfc-r8a7791";
+                reg = <0 0xe6060000 0 0x250>;
+                #gpio-range-cells = <3>;
+        };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7791-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "z";
+                };
+
+                /* Variable factor clocks */
+                sd1_clk: sd2_clk@e6150078 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd1";
+                };
+                sd2_clk: sd3_clk@e615007c {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd2";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                ssp_clk: ssp_clk@e6150248 {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150248 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssp";
+                };
+                ssprs_clk: ssprs_clk@e615024c {
+                        compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615024c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssprs";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
+                                R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
+                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vsp1-du0", "vsp1-sy";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
+                                R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
+                                R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
+                                "scifb1", "msiof1", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
+                                <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
+                                R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
+                        clock-output-names = "thermal", "pwm";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                 <&zx_clk>, <&zx_clk>, <&zx_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+                                R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
+                                R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
+                                R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
+                                R8A7791_CLK_LVDS0
+                        >;
+                        clock-output-names =
+                                "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+                                "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7791_CLK_ETHER>;
+                        clock-output-names = "ether";
+                };
+                mstp9_clks: mstp9_clks@e6150994 {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
+                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                 <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
+                                R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
+                                R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
+                                "i2c2", "i2c1", "i2c0";
+                };
+                mstp11_clks: mstp11_clks@e615099c {
+                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
+                        >;
+                        clock-output-names = "scifa3", "scifa4", "scifa5";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5cdaba4cea86..52447c17537a 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1,6 +1,6 @@
 /*
  * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
- *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
+ *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
  *
  *  Copyright (C) 2013 Atmel,
  *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
@@ -13,6 +13,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/at91.h>
 
 / {
         model = "Atmel SAMA5D3 family SoC";
@@ -36,6 +37,7 @@
                 i2c2 = &i2c2;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
+                pwm0 = &pwm0;
         };
         cpus {
                 #address-cells = <1>;
@@ -56,6 +58,14 @@
                 reg = <0x20000000 0x8000000>;
         };
 
+        clocks {
+                adc_op_clk: adc_op_clk{
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <20000000>;
+                };
+        };
+
         ahb {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -79,6 +89,8 @@
                                 status = "disabled";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
                         };
 
                         spi0: spi@f0004000 {
@@ -92,6 +104,8 @@
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
                                 status = "disabled";
                         };
 
@@ -101,6 +115,8 @@
                                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
                                 status = "disabled";
                         };
 
@@ -108,6 +124,8 @@
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf0010000 0x100>;
                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb0_clk>;
+                                clock-names = "t0_clk";
                         };
 
                         i2c0: i2c@f0014000 {
@@ -121,6 +139,7 @@
                                 pinctrl-0 = <&pinctrl_i2c0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                clocks = <&twi0_clk>;
                                 status = "disabled";
                         };
 
@@ -135,6 +154,7 @@
                                 pinctrl-0 = <&pinctrl_i2c1>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                clocks = <&twi1_clk>;
                                 status = "disabled";
                         };
 
@@ -144,6 +164,8 @@
                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
+                                clocks = <&usart0_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
 
@@ -153,6 +175,17 @@
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
+                                clocks = <&usart1_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+
+                        pwm0: pwm@f002c000 {
+                                compatible = "atmel,sama5d3-pwm";
+                                reg = <0xf002c000 0x300>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
                                 status = "disabled";
                         };
 
@@ -174,6 +207,8 @@
                                 status = "disabled";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                clocks = <&mci1_clk>;
+                                clock-names = "mci_clk";
                         };
 
                         spi1: spi@f8008000 {
@@ -187,6 +222,8 @@
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
+                                clocks = <&spi1_clk>;
+                                clock-names = "spi_clk";
                                 status = "disabled";
                         };
 
@@ -196,6 +233,8 @@
                                 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                clocks = <&ssc1_clk>;
+                                clock-names = "pclk";
                                 status = "disabled";
                         };
 
@@ -219,6 +258,9 @@
                                         &pinctrl_adc0_ad10
                                         &pinctrl_adc0_ad11
                                         >;
+                                clocks = <&adc_clk>,
+                                         <&adc_op_clk>;
+                                clock-names = "adc_clk", "adc_op_clk";
                                 atmel,adc-channel-base = <0x50>;
                                 atmel,adc-channels-used = <0xfff>;
                                 atmel,adc-drdy-mask = <0x1000000>;
@@ -272,8 +314,11 @@
                                 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
                                        <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
                                 dma-names = "tx", "rx";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                clocks = <&twi2_clk>;
                                 status = "disabled";
                         };
 
@@ -283,6 +328,8 @@
                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
 
@@ -292,25 +339,41 @@
                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart3>;
+                                clocks = <&usart3_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
 
                         sha@f8034000 {
-                                compatible = "atmel,sam9g46-sha";
+                                compatible = "atmel,at91sam9g46-sha";
                                 reg = <0xf8034000 0x100>;
                                 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
+                                dma-names = "tx";
+                                clocks = <&sha_clk>;
+                                clock-names = "sha_clk";
                         };
 
                         aes@f8038000 {
-                                compatible = "atmel,sam9g46-aes";
+                                compatible = "atmel,at91sam9g46-aes";
                                 reg = <0xf8038000 0x100>;
-                                interrupts = <43 4 0>;
+                                interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&aes_clk>;
+                                clock-names = "aes_clk";
                         };
 
                         tdes@f803c000 {
-                                compatible = "atmel,sam9g46-tdes";
+                                compatible = "atmel,at91sam9g46-tdes";
                                 reg = <0xf803c000 0x100>;
                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
+                                dma-names = "tx", "rx";
+                                clocks = <&tdes_clk>;
+                                clock-names = "tdes_clk";
                         };
 
                         dma0: dma-controller@ffffe600 {
@@ -318,6 +381,8 @@
                                 reg = <0xffffe600 0x200>;
                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
+                                clocks = <&dma0_clk>;
+                                clock-names = "dma_clk";
                         };
 
                         dma1: dma-controller@ffffe800 {
@@ -325,6 +390,8 @@
                                 reg = <0xffffe800 0x200>;
                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
+                                clocks = <&dma1_clk>;
+                                clock-names = "dma_clk";
                         };
 
                         ramc0: ramc@ffffea00 {
@@ -338,6 +405,8 @@
                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&dbgu_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
 
@@ -443,6 +512,14 @@
                                         };
                                 };
 
+                                i2c2 {
+                                        pinctrl_i2c2: i2c2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
+                                                         AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
+                                        };
+                                };
+
                                 isi {
                                         pinctrl_isi: isi-0 {
                                                 atmel,pins =
@@ -626,6 +703,7 @@
                                         gpio-controller;
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
+                                        clocks = <&pioA_clk>;
                                 };
 
                                 pioB: gpio@fffff400 {
@@ -636,6 +714,7 @@
                                         gpio-controller;
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
+                                        clocks = <&pioB_clk>;
                                 };
 
                                 pioC: gpio@fffff600 {
@@ -646,6 +725,7 @@
                                         gpio-controller;
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
+                                        clocks = <&pioC_clk>;
                                 };
 
                                 pioD: gpio@fffff800 {
@@ -656,6 +736,7 @@
                                         gpio-controller;
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
+                                        clocks = <&pioD_clk>;
                                 };
 
                                 pioE: gpio@fffffa00 {
@@ -666,12 +747,334 @@
                                         gpio-controller;
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
+                                        clocks = <&pioE_clk>;
                                 };
                         };
 
                         pmc: pmc@fffffc00 {
-                                compatible = "atmel,at91rm9200-pmc";
+                                compatible = "atmel,sama5d3-pmc";
                                 reg = <0xfffffc00 0x120>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+
+                                clk32k: slck {
+                                        compatible = "fixed-clock";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                };
+
+                                main: mainck {
+                                        compatible = "atmel,at91rm9200-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCS>;
+                                        clocks = <&clk32k>;
+                                };
+
+                                plla: pllack {
+                                        compatible = "atmel,sama5d3-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <8000000 50000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
+                                };
+
+                                plladiv: plladivck {
+                                        compatible = "atmel,at91sam9x5-clk-plldiv";
+                                        #clock-cells = <0>;
+                                        clocks = <&plla>;
+                                };
+
+                                utmi: utmick {
+                                        compatible = "atmel,at91sam9x5-clk-utmi";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_LOCKU>;
+                                        clocks = <&main>;
+                                };
+
+                                mck: masterck {
+                                        compatible = "atmel,at91sam9x5-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+                                        atmel,clk-output-range = <0 166000000>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                };
+
+                                usb: usbck {
+                                        compatible = "atmel,at91sam9x5-clk-usb";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+
+                                prog: progck {
+                                        compatible = "atmel,at91sam9x5-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+
+                                        prog2: prog2 {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                interrupts = <AT91_PMC_PCKRDY(2)>;
+                                        };
+                                };
+
+                                smd: smdclk {
+                                        compatible = "atmel,at91sam9x5-clk-smd";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        ddrck: ddrck {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                clocks = <&mck>;
+                                        };
+
+                                        smdck: smdck {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                                clocks = <&smd>;
+                                        };
+
+                                        uhpck: uhpck {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                                clocks = <&usb>;
+                                        };
+
+                                        udpck: udpck {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                                clocks = <&usb>;
+                                        };
+
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+
+                                        pck2: pck2 {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                                clocks = <&prog2>;
+                                        };
+                                };
+
+                                periphck {
+                                        compatible = "atmel,at91sam9x5-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+
+                                        dbgu_clk: dbgu_clk {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                        };
+
+                                        pioA_clk: pioA_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+
+                                        pioB_clk: pioB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+
+                                        pioC_clk: pioC_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+
+                                        pioD_clk: pioD_clk {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                        };
+
+                                        pioE_clk: pioE_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        usart3_clk: usart3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        twi0_clk: twi0_clk {
+                                                reg = <18>;
+                                                #clock-cells = <0>;
+                                                atmel,clk-output-range = <0 16625000>;
+                                        };
+
+                                        twi1_clk: twi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                                atmel,clk-output-range = <0 16625000>;
+                                        };
+
+                                        twi2_clk: twi2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <20>;
+                                                atmel,clk-output-range = <0 16625000>;
+                                        };
+
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <21>;
+                                        };
+
+                                        mci1_clk: mci1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <22>;
+                                        };
+
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <24>;
+                                                atmel,clk-output-range = <0 133000000>;
+                                        };
+
+                                        spi1_clk: spi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <25>;
+                                                atmel,clk-output-range = <0 133000000>;
+                                        };
+
+                                        tcb0_clk: tcb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <26>;
+                                                atmel,clk-output-range = <0 133000000>;
+                                        };
+
+                                        pwm_clk: pwm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <28>;
+                                        };
+
+                                        adc_clk: adc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <29>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        dma0_clk: dma0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <30>;
+                                        };
+
+                                        dma1_clk: dma1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <31>;
+                                        };
+
+                                        uhphs_clk: uhphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <32>;
+                                        };
+
+                                        udphs_clk: udphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <33>;
+                                        };
+
+                                        isi_clk: isi_clk {
+                                                #clock-cells = <0>;
+                                                reg = <37>;
+                                        };
+
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <38>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        ssc1_clk: ssc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <39>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        sha_clk: sha_clk {
+                                                #clock-cells = <0>;
+                                                reg = <42>;
+                                        };
+
+                                        aes_clk: aes_clk {
+                                                #clock-cells = <0>;
+                                                reg = <43>;
+                                        };
+
+                                        tdes_clk: tdes_clk {
+                                                #clock-cells = <0>;
+                                                reg = <44>;
+                                        };
+
+                                        trng_clk: trng_clk {
+                                                #clock-cells = <0>;
+                                                reg = <45>;
+                                        };
+
+                                        fuse_clk: fuse_clk {
+                                                #clock-cells = <0>;
+                                                reg = <48>;
+                                        };
+                                };
                         };
 
                         rstc@fffffe00 {
@@ -683,11 +1086,17 @@
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+                                clocks = <&mck>;
                         };
 
                         watchdog@fffffe40 {
                                 compatible = "atmel,at91sam9260-wdt";
                                 reg = <0xfffffe40 0x10>;
+                                interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
+                                atmel,watchdog-type = "hardware";
+                                atmel,reset-type = "all";
+                                atmel,dbg-halt;
+                                atmel,idle-halt;
                                 status = "disabled";
                         };
 
@@ -705,6 +1114,8 @@
                         reg = <0x00500000 0x100000
                                0xf8030000 0x4000>;
                         interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&udphs_clk>, <&utmi>;
+                        clock-names = "pclk", "hclk";
                         status = "disabled";
 
                         ep0 {
@@ -817,6 +1228,9 @@
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+                                 <&uhpck>;
+                        clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                         status = "disabled";
                 };
 
@@ -824,6 +1238,8 @@
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00700000 0x100000>;
                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
+                        clock-names = "usb_clk", "ehci_clk", "uhpck";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi
new file mode 100644
index 000000000000..6c31c26e6cc0
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36.dtsi
@@ -0,0 +1,20 @@
+/*
+ * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Josh Wu <josh.wu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include "sama5d3.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_tcb1.dtsi"
+#include "sama5d3_uart.dtsi"
+
+/ {
+        compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5";
+};
diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts
new file mode 100644
index 000000000000..59576c6f9826
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36ek.dts
@@ -0,0 +1,53 @@
+/*
+ * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Josh Wu <josh.wu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D36-EK";
+        compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index 8ed3260cef66..a0775851cce5 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -32,12 +32,30 @@
 
                         };
 
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        can0_clk: can0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <40>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        can1_clk: can0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <41>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+                                };
+                        };
+
                         can0: can@f000c000 {
                                 compatible = "atmel,at91sam9x5-can";
                                 reg = <0xf000c000 0x300>;
                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                clocks = <&can0_clk>;
+                                clock-names = "can_clk";
                                 status = "disabled";
                         };
 
@@ -47,6 +65,8 @@
                                 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                                clocks = <&can1_clk>;
+                                clock-names = "can_clk";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index 4d4f351f1f9f..fe2af9276312 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -31,12 +31,23 @@
                                 };
                         };
 
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        macb1_clk: macb1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <35>;
+                                        };
+                                };
+                        };
+
                         macb1: ethernet@f802c000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf802c000 0x100>;
                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb1_rmii>;
+                                clocks = <&macb1_clk>, <&macb1_clk>;
+                                clock-names = "hclk", "pclk";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index 0ba8be30ccd8..a6cb0508762f 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -64,12 +64,23 @@
                                 };
                         };
 
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        macb0_clk: macb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <34>;
+                                        };
+                                };
+                        };
+
                         macb0: ethernet@f0028000 {
                                 compatible = "cdns,pc302-gem", "cdns,gem";
                                 reg = <0xf0028000 0x100>;
                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+                                clocks = <&macb0_clk>, <&macb0_clk>;
+                                clock-names = "hclk", "pclk";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 01f52a79f8ba..85d302701565 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -50,6 +50,23 @@
                                         };
                                 };
                         };
+
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        lcdc_clk: lcdc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <36>;
+                                        };
+                                };
+
+                                systemck {
+                                        lcdck: lcdck {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                                clocks = <&mck>;
+                                        };
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 38e88e39e551..b029fe7ef17a 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clk/at91.h>
 
 / {
         ahb {
@@ -30,6 +31,15 @@
                                 };
                         };
 
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        mci2_clk: mci2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <23>;
+                                        };
+                                };
+                        };
+
                         mmc2: mmc@f8004000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf8004000 0x600>;
@@ -38,6 +48,8 @@
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+                                clocks = <&mci2_clk>;
+                                clock-names = "mci_clk";
                                 status = "disabled";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 5264bb4a6998..382b04431f66 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -9,6 +9,7 @@
 
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clk/at91.h>
 
 / {
         aliases {
@@ -17,10 +18,21 @@
 
         ahb {
                 apb {
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        tcb1_clk: tcb1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <27>;
+                                        };
+                                };
+                        };
+
                         tcb1: timer@f8014000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8014000 0x100>;
                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb1_clk>;
+                                clock-names = "t0_clk";
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 98fcb2d57446..a9fa75e41652 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,8 +9,14 @@
 
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clk/at91.h>
 
 / {
+        aliases {
+                serial5 = &uart0;
+                serial6 = &uart1;
+        };
+
         ahb {
                 apb {
                         pinctrl@fffff200 {
@@ -31,12 +37,30 @@
                                 };
                         };
 
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+
+                                        uart1_clk: uart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                                atmel,clk-output-range = <0 66000000>;
+                                        };
+                                };
+                        };
+
                         uart0: serial@f0024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf0024000 0x200>;
                                 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_uart0>;
+                                clocks = <&uart0_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
 
@@ -46,6 +70,8 @@
                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_uart1>;
+                                clocks = <&uart1_clk>;
+                                clock-names = "usart";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 726a0f35100c..f55ed072c8e6 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,17 +18,6 @@
                 reg = <0x20000000 0x20000000>;
         };
 
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-        };
-
         ahb {
                 apb {
                         spi0: spi@f0004000 {
@@ -38,6 +27,12 @@
                         macb0: ethernet@f0028000 {
                                 phy-mode = "rgmii";
                         };
+
+                        pmc: pmc@fffffc00 {
+                                main: mainck {
+                                        clock-frequency = <12000000>;
+                                };
+                        };
                 };
 
                 nand0: nand@60000000 {
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 1c296d6b2f2a..f9bdde542ced 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -18,6 +18,7 @@
                                         interrupts = <31 0x0>;
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&pinctrl_qt1070_irq>;
+                                        wakeup-source;
                                 };
                         };
 
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
index 8acf51e0cdae..a759a276c9a9 100644
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "sh7372.dtsi"
+#include "sh7372.dtsi"
 
 / {
         model = "Mackerel (AP4 EVM 2nd)";
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 8ee06dd81799..eb8886b535e4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -12,8 +12,9 @@
  */
 
 /dts-v1/;
-/include/ "sh73a0.dtsi"
+#include "sh73a0.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "KZM-A9-GT";
@@ -82,7 +83,7 @@
                 reg = <0x10000000 0x100>;
                 phy-mode = "mii";
                 interrupt-parent = <&irqpin0>;
-                interrupts = <3 0>;     /* active low */
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
                 reg-io-width = <4>;
                 smsc,irq-push-pull;
                 smsc,save-mac-address;
@@ -105,6 +106,66 @@
                         gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
                 };
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                back-key {
+                        gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <158>;
+                        label = "SW3";
+                };
+
+                right-key {
+                        gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
+                        linux,code = <106>;
+                        label = "SW2-R";
+                };
+
+                left-key {
+                        gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <105>;
+                        label = "SW2-L";
+                };
+
+                enter-key {
+                        gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <28>;
+                        label = "SW2-P";
+                };
+
+                up-key {
+                        gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <103>;
+                        label = "SW2-U";
+                };
+
+                down-key {
+                        gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
+                        linux,code = <108>;
+                        label = "SW2-D";
+                };
+
+                home-key {
+                        gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
+                        linux,code = <102>;
+                        label = "SW1";
+                };
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,cpu {
+                        sound-dai = <&sh_fsi2 0>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&ak4648>;
+                        bitclock-master;
+                        frame-master;
+                        system-clock-frequency = <11289600>;
+                };
+        };
 };
 
 &i2c0 {
@@ -179,12 +240,29 @@
                         };
                 };
         };
+
+        ak4648: ak4648@0x12 {
+                #sound-dai-cells = <0>;
+                compatible = "asahi-kasei,ak4648";
+                reg = <0x12>;
+        };
 };
 
 &i2c3 {
         pinctrl-0 = <&i2c3_pins>;
         pinctrl-names = "default";
         status = "okay";
+
+        pcf8575: gpio@20 {
+                compatible = "nxp,pcf8575";
+                reg = <0x20>;
+                interrupt-parent = <&irqpin2>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
 };
 
 &mmcif {
@@ -205,7 +283,7 @@
                 renesas,function = "i2c3";
         };
 
-        mmcif_pins: mmcif {
+        mmcif_pins: mmc {
                 mux {
                         renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
                         renesas,function = "mmc0";
@@ -217,20 +295,26 @@
                 };
         };
 
-        scifa4_pins: scifa4 {
+        scifa4_pins: serial4 {
                 renesas,groups = "scifa4_data", "scifa4_ctrl";
                 renesas,function = "scifa4";
         };
 
-        sdhi0_pins: sdhi0 {
+        sdhi0_pins: sd0 {
                 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
                 renesas,function = "sdhi0";
         };
 
-        sdhi2_pins: sdhi2 {
+        sdhi2_pins: sd2 {
                 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
                 renesas,function = "sdhi2";
         };
+
+        fsia_pins: sounda {
+                renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
+                                 "fsia_data_in", "fsia_data_out";
+                renesas,function = "fsia";
+        };
 };
 
 &sdhi0 {
@@ -251,3 +335,10 @@
         broken-cd;
         status = "okay";
 };
+
+&sh_fsi2 {
+        pinctrl-0 = <&fsia_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 0f1ca7792c46..27c5f426d172 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "sh73a0.dtsi"
+#include "sh73a0.dtsi"
 
 / {
         model = "KZM-A9-GT";
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index fcf26889a8a0..b7bd3b9a6753 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -10,6 +10,8 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,sh73a0";
 
@@ -40,12 +42,12 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 55 4>,
-                             <0 56 4>;
+                interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 56 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin0: irqpin@e6900000 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900000 4>,
@@ -54,18 +56,18 @@
                         <0xe6900040 1>,
                         <0xe6900060 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 1 0x4
-                              0 2 0x4
-                              0 3 0x4
-                              0 4 0x4
-                              0 5 0x4
-                              0 6 0x4
-                              0 7 0x4
-                              0 8 0x4>;
+                interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
+                              0 2 IRQ_TYPE_LEVEL_HIGH
+                              0 3 IRQ_TYPE_LEVEL_HIGH
+                              0 4 IRQ_TYPE_LEVEL_HIGH
+                              0 5 IRQ_TYPE_LEVEL_HIGH
+                              0 6 IRQ_TYPE_LEVEL_HIGH
+                              0 7 IRQ_TYPE_LEVEL_HIGH
+                              0 8 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin1: irqpin@e6900004 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900004 4>,
@@ -74,19 +76,19 @@
                         <0xe6900044 1>,
                         <0xe6900064 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 9 0x4
-                              0 10 0x4
-                              0 11 0x4
-                              0 12 0x4
-                              0 13 0x4
-                              0 14 0x4
-                              0 15 0x4
-                              0 16 0x4>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
+                              0 10 IRQ_TYPE_LEVEL_HIGH
+                              0 11 IRQ_TYPE_LEVEL_HIGH
+                              0 12 IRQ_TYPE_LEVEL_HIGH
+                              0 13 IRQ_TYPE_LEVEL_HIGH
+                              0 14 IRQ_TYPE_LEVEL_HIGH
+                              0 15 IRQ_TYPE_LEVEL_HIGH
+                              0 16 IRQ_TYPE_LEVEL_HIGH>;
                 control-parent;
         };
 
         irqpin2: irqpin@e6900008 {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe6900008 4>,
@@ -95,18 +97,18 @@
                         <0xe6900048 1>,
                         <0xe6900068 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 17 0x4
-                              0 18 0x4
-                              0 19 0x4
-                              0 20 0x4
-                              0 21 0x4
-                              0 22 0x4
-                              0 23 0x4
-                              0 24 0x4>;
+                interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
+                              0 18 IRQ_TYPE_LEVEL_HIGH
+                              0 19 IRQ_TYPE_LEVEL_HIGH
+                              0 20 IRQ_TYPE_LEVEL_HIGH
+                              0 21 IRQ_TYPE_LEVEL_HIGH
+                              0 22 IRQ_TYPE_LEVEL_HIGH
+                              0 23 IRQ_TYPE_LEVEL_HIGH
+                              0 24 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         irqpin3: irqpin@e690000c {
-                compatible = "renesas,intc-irqpin";
+                compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0xe690000c 4>,
@@ -115,14 +117,14 @@
                         <0xe690004c 1>,
                         <0xe690006c 1>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 25 0x4
-                              0 26 0x4
-                              0 27 0x4
-                              0 28 0x4
-                              0 29 0x4
-                              0 30 0x4
-                              0 31 0x4
-                              0 32 0x4>;
+                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
+                              0 26 IRQ_TYPE_LEVEL_HIGH
+                              0 27 IRQ_TYPE_LEVEL_HIGH
+                              0 28 IRQ_TYPE_LEVEL_HIGH
+                              0 29 IRQ_TYPE_LEVEL_HIGH
+                              0 30 IRQ_TYPE_LEVEL_HIGH
+                              0 31 IRQ_TYPE_LEVEL_HIGH
+                              0 32 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6820000 {
@@ -131,10 +133,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6820000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 0x4
-                              0 168 0x4
-                              0 169 0x4
-                              0 170 0x4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
+                              0 168 IRQ_TYPE_LEVEL_HIGH
+                              0 169 IRQ_TYPE_LEVEL_HIGH
+                              0 170 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -144,10 +146,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6822000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 51 0x4
-                              0 52 0x4
-                              0 53 0x4
-                              0 54 0x4>;
+                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
+                              0 52 IRQ_TYPE_LEVEL_HIGH
+                              0 53 IRQ_TYPE_LEVEL_HIGH
+                              0 54 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -157,10 +159,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6824000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 171 0x4
-                              0 172 0x4
-                              0 173 0x4
-                              0 174 0x4>;
+                interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
+                              0 172 IRQ_TYPE_LEVEL_HIGH
+                              0 173 IRQ_TYPE_LEVEL_HIGH
+                              0 174 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -170,10 +172,10 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6826000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 183 0x4
-                              0 184 0x4
-                              0 185 0x4
-                              0 186 0x4>;
+                interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
+                              0 184 IRQ_TYPE_LEVEL_HIGH
+                              0 185 IRQ_TYPE_LEVEL_HIGH
+                              0 186 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
@@ -183,52 +185,52 @@
                 compatible = "renesas,rmobile-iic";
                 reg = <0xe6828000 0x425>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 187 0x4
-                              0 188 0x4
-                              0 189 0x4
-                              0 190 0x4>;
+                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
+                              0 188 IRQ_TYPE_LEVEL_HIGH
+                              0 189 IRQ_TYPE_LEVEL_HIGH
+                              0 190 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        mmcif: mmcif@e6bd0000 {
+        mmcif: mmc@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 140 0x4
-                              0 141 0x4>;
+                interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
+                              0 141 IRQ_TYPE_LEVEL_HIGH>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        sdhi0: sdhi@ee100000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi0: sd@ee100000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee100000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 83 4
-                                0 84 4
-                                0 85 4>;
+                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
+                              0 84 IRQ_TYPE_LEVEL_HIGH
+                              0 85 IRQ_TYPE_LEVEL_HIGH>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
-        sdhi1: sdhi@ee120000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi1: sd@ee120000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee120000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 88 4
-                                0 89 4>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
+                              0 89 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
-                compatible = "renesas,sdhi-r8a7740";
+        sdhi2: sd@ee140000 {
+                compatible = "renesas,sdhi-sh73a0";
                 reg = <0xee140000 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 104 4
-                                0 105 4>;
+                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
+                              0 105 IRQ_TYPE_LEVEL_HIGH>;
                 toshiba,mmc-wrprotect-disable;
                 cap-sd-highspeed;
                 status = "disabled";
@@ -240,5 +242,23 @@
                       <0xe605801c 0x1c>;
                 gpio-controller;
                 #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
+                        <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
+                        <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
+                        <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
+                        <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
+                        <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
+                        <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
+                        <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
+        };
+
+        sh_fsi2: sound@ec230000 {
+                #sound-dai-cells = <1>;
+                compatible = "renesas,sh_fsi2";
+                reg = <0xec230000 0x400>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 146 0x4>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f936476c2753..537f1a5c07f5 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -79,6 +79,8 @@
                                 #dma-cells = <1>;
                                 #dma-channels = <8>;
                                 #dma-requests = <32>;
+                                clocks = <&l4_main_clk>;
+                                clock-names = "apb_pclk";
                         };
                 };
 
@@ -467,6 +469,8 @@
                         interrupts = <0 38 0x04>;
                         cache-unified;
                         cache-level = <2>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <2 1 1>;
                 };
 
                 /* Local timer */
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
index 8c45d85ac13e..4851c387d52d 100644
--- a/arch/arm/boot/dts/st-pincfg.h
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -15,7 +15,7 @@
 /* Pull Up */
 #define PU                      (1 << 26)
 /* Open Drain */
-#define OD                      (1 << 26)
+#define OD                      (1 << 25)
 #define RT                      (1 << 23)
 #define INVERTCLK               (1 << 22)
 #define CLKNOTDATA              (1 << 21)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 7da99fe497e1..e0853ea02df2 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -913,6 +913,10 @@
                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
+                               <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
+                        dma-names = "rx", "tx";
+
                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
                         clock-names = "msp", "apb_pclk";
 
@@ -925,6 +929,9 @@
                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
+                        dma-names = "tx";
+
                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
                         clock-names = "msp", "apb_pclk";
 
@@ -938,6 +945,11 @@
                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
+                               <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
+                                                    HighPrio - Fixed */
+                        dma-names = "rx", "tx";
+
                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
                         clock-names = "msp", "apb_pclk";
 
@@ -950,6 +962,9 @@
                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
 
+                        dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
+                        dma-names = "rx";
+
                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
                         clock-names = "msp", "apb_pclk";
 
@@ -987,6 +1002,23 @@
                         status = "disabled";
                 };
 
+                mcde@a0350000 {
+                        compatible = "stericsson,mcde";
+                        reg = <0xa0350000 0x1000>, /* MCDE */
+                              <0xa0351000 0x1000>, /* DSI link 1 */
+                              <0xa0352000 0x1000>, /* DSI link 2 */
+                              <0xa0353000 0x1000>; /* DSI link 3 */
+                        interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
+                                 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
+                                 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
+                                 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
+                                 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
+                                 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
+                                 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
+                                 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
+                };
+
                 cryp@a03cb000 {
                         compatible = "stericsson,ux500-cryp";
                         reg = <0xa03cb000 0x1000>;
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
new file mode 100644
index 000000000000..addfcc7c2750
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -0,0 +1,745 @@
+/*
+ * Copyright 2013 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ste-nomadik-pinctrl.dtsi"
+
+/ {
+        soc {
+                pinctrl {
+                        /* Settings for all UART default and sleep states */
+                        uart0 {
+                                uart0_default_mode: uart0_default {
+                                        default_mux {
+                                                ste,function = "u0";
+                                                ste,pins = "u0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart0_sleep_mode: uart0_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO1_AJ3"; /* RTS */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO3_AH3"; /* TXD */
+                                                ste,config = <&slpm_out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        uart1 {
+                                uart1_default_mode: uart1_default {
+                                        default_mux {
+                                                ste,function = "u1";
+                                                ste,pins = "u1rxtx_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart1_sleep_mode: uart1_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                ste,config = <&slpm_out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        uart2 {
+                                uart2_default_mode: uart2_default {
+                                        default_mux {
+                                                ste,function = "u2";
+                                                ste,pins = "u2rxtx_c_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                ste,config = <&in_pu>;
+                                        };
+
+                                        default_cfg2 {
+                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                uart2_sleep_mode: uart2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                ste,config = <&in_wkup_pdis>;
+                                        };
+
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                ste,config = <&out_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all I2C default and sleep states */
+                        i2c0 {
+                                i2c0_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c0";
+                                                ste,pins = "i2c0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c0_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                i2c1_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c1";
+                                                ste,pins = "i2c1_b_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c1_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c2 {
+                                i2c2_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c2";
+                                                ste,pins = "i2c2_b_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c2_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        i2c3 {
+                                i2c3_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c3";
+                                                ste,pins = "i2c3_c_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c3_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /*
+                         * Activating I2C4 will conflict with UART1 about the same pins so do not
+                         * enable I2C4 and UART1 at the same time.
+                         */
+                        i2c4 {
+                                i2c4_default_mode: i2c_default {
+                                        default_mux {
+                                                ste,function = "i2c4";
+                                                ste,pins = "i2c4_b_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                i2c4_sleep_mode: i2c_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all SPI default and sleep states */
+                        spi2 {
+                                spi2_default_mode: spi_default {
+                                        default_mux {
+                                                ste,function = "spi2";
+                                                ste,pins = "spi2_oc1_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO216_AG12"; /* FRM */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO215_AH13", /* TXD */
+                                                "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+
+                                spi2_idle_mode: spi_idle {
+                                        /*
+                                         * The idle mode is basically sleep mode sans wakeups. Also
+                                         * note that we have muxes the pins off the function here
+                                         * as we do not state any muxing.
+                                         */
+                                        idle_cfg1 {
+                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&slpm_in_pdis>;
+                                        };
+                                        idle_cfg2 {
+                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                ste,config = <&slpm_out_lo_pdis>;
+                                        };
+                                        idle_cfg3 {
+                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&slpm_pdis>;
+                                        };
+                                };
+
+                                spi2_sleep_mode: spi_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO216_AG12", /* FRM */
+                                                "GPIO218_AH11"; /* RXD */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                ste,config = <&slpm_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /* Settings for all MMC/SD/SDIO default and sleep states */
+                        sdi0 {
+                                /* This is the external SD card slot, 4 bits wide */
+                                sdi0_default_mode: sdi0_default {
+                                        default_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO18_AC2", /* CMDDIR */
+                                                "GPIO19_AC1", /* DAT0DIR */
+                                                "GPIO20_AB4"; /* DAT2DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO22_AA3"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg4 {
+                                                ste,pins =
+                                                "GPIO24_AB2", /* CMD */
+                                                "GPIO25_Y4", /* DAT0 */
+                                                "GPIO26_Y2", /* DAT1 */
+                                                "GPIO27_AA2", /* DAT2 */
+                                                "GPIO28_AA1"; /* DAT3 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi0_sleep_mode: sdi0_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO18_AC2", /* CMDDIR */
+                                                "GPIO19_AC1", /* DAT0DIR */
+                                                "GPIO20_AB4"; /* DAT2DIR */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO22_AA3", /* FBCLK */
+                                                "GPIO24_AB2", /* CMD */
+                                                "GPIO25_Y4", /* DAT0 */
+                                                "GPIO26_Y2", /* DAT1 */
+                                                "GPIO27_AA2", /* DAT2 */
+                                                "GPIO28_AA1"; /* DAT3 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi1 {
+                                /* This is the WLAN SDIO 4 bits wide */
+                                sdi1_default_mode: sdi1_default {
+                                        default_mux {
+                                                ste,function = "mc1";
+                                                ste,pins = "mc1_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO209_AG15"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO210_AJ15", /* CMD */
+                                                "GPIO211_AG14", /* DAT0 */
+                                                "GPIO212_AF13", /* DAT1 */
+                                                "GPIO213_AG13", /* DAT2 */
+                                                "GPIO214_AH15"; /* DAT3 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi1_sleep_mode: sdi1_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                ste,config = <&slpm_out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO209_AG15", /* FBCLK */
+                                                "GPIO210_AJ15", /* CMD */
+                                                "GPIO211_AG14", /* DAT0 */
+                                                "GPIO212_AF13", /* DAT1 */
+                                                "GPIO213_AG13", /* DAT2 */
+                                                "GPIO214_AH15"; /* DAT3 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi2 {
+                                /* This is the eMMC 8 bits wide, usually PoP eMMC */
+                                sdi2_default_mode: sdi2_default {
+                                        default_mux {
+                                                ste,function = "mc2";
+                                                ste,pins = "mc2_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO130_C8"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO129_B4", /* CMD */
+                                                "GPIO131_A12", /* DAT0 */
+                                                "GPIO132_C10", /* DAT1 */
+                                                "GPIO133_B10", /* DAT2 */
+                                                "GPIO134_B9", /* DAT3 */
+                                                "GPIO135_A9", /* DAT4 */
+                                                "GPIO136_C7", /* DAT5 */
+                                                "GPIO137_A7", /* DAT6 */
+                                                "GPIO138_C5"; /* DAT7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi2_sleep_mode: sdi2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                ste,config = <&out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO130_C8", /* FBCLK */
+                                                "GPIO129_B4"; /* CMD */
+                                                ste,config = <&in_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins =
+                                                "GPIO131_A12", /* DAT0 */
+                                                "GPIO132_C10", /* DAT1 */
+                                                "GPIO133_B10", /* DAT2 */
+                                                "GPIO134_B9", /* DAT3 */
+                                                "GPIO135_A9", /* DAT4 */
+                                                "GPIO136_C7", /* DAT5 */
+                                                "GPIO137_A7", /* DAT6 */
+                                                "GPIO138_C5"; /* DAT7 */
+                                                ste,config = <&in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        sdi4 {
+                                /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
+                                sdi4_default_mode: sdi4_default {
+                                        default_mux {
+                                                ste,function = "mc4";
+                                                ste,pins = "mc4_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO202_AF25"; /* FBCLK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg3 {
+                                                ste,pins =
+                                                "GPIO201_AF24", /* CMD */
+                                                "GPIO200_AH26", /* DAT0 */
+                                                "GPIO199_AH23", /* DAT1 */
+                                                "GPIO198_AG25", /* DAT2 */
+                                                "GPIO197_AH24", /* DAT3 */
+                                                "GPIO207_AJ23", /* DAT4 */
+                                                "GPIO206_AG24", /* DAT5 */
+                                                "GPIO205_AG23", /* DAT6 */
+                                                "GPIO204_AF23"; /* DAT7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+
+                                sdi4_sleep_mode: sdi4_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                ste,config = <&out_lo_wkup_pdis>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO202_AF25", /* FBCLK */
+                                                "GPIO201_AF24", /* CMD */
+                                                "GPIO200_AH26", /* DAT0 */
+                                                "GPIO199_AH23", /* DAT1 */
+                                                "GPIO198_AG25", /* DAT2 */
+                                                "GPIO197_AH24", /* DAT3 */
+                                                "GPIO207_AJ23", /* DAT4 */
+                                                "GPIO206_AG24", /* DAT5 */
+                                                "GPIO205_AG23", /* DAT6 */
+                                                "GPIO204_AF23"; /* DAT7 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        /*
+                         * Multi-rate serial ports (MSPs) - MSP3 output is internal and
+                         * cannot be muxed onto any pins.
+                         */
+                        msp0 {
+                                msp0_default_mode: msp0_default {
+                                        default_msp0_mux {
+                                                ste,function = "msp0";
+                                                ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
+                                        };
+                                        default_msp0_cfg {
+                                                ste,pins =
+                                                "GPIO12_AC4", /* TXD */
+                                                "GPIO15_AC3", /* RXD */
+                                                "GPIO13_AF3", /* TFS */
+                                                "GPIO14_AE3"; /* TCK */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                };
+                        };
+
+                        msp1 {
+                                msp1_default_mode: msp1_default {
+                                        default_mux {
+                                                ste,function = "msp1";
+                                                ste,pins = "msp1txrx_a_1", "msp1_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins = "GPIO33_AF2";
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO34_AE1",
+                                                "GPIO35_AE2",
+                                                "GPIO36_AG2";
+                                                ste,config = <&in_nopull>;
+                                        };
+
+                                };
+                        };
+
+                        msp2 {
+                                msp2_default_mode: msp2_default {
+                                        /* MSP2 usually used for HDMI audio */
+                                        default_mux {
+                                                ste,function = "msp2";
+                                                ste,pins = "msp2_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO193_AH27", /* TXD */
+                                                "GPIO194_AF27", /* TCK */
+                                                "GPIO195_AG28"; /* TFS */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO196_AG26"; /* RXD */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                        };
+
+
+                        musb {
+                                musb_default_mode: musb_default {
+                                        default_mux {
+                                                ste,function = "usb";
+                                                ste,pins = "usb_a_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO256_AF28", /* NXT */
+                                                "GPIO258_AD29", /* XCLK */
+                                                "GPIO259_AC29", /* DIR */
+                                                "GPIO260_AD28", /* DAT7 */
+                                                "GPIO261_AD26", /* DAT6 */
+                                                "GPIO262_AE26", /* DAT5 */
+                                                "GPIO263_AG29", /* DAT4 */
+                                                "GPIO264_AE27", /* DAT3 */
+                                                "GPIO265_AD27", /* DAT2 */
+                                                "GPIO266_AC28", /* DAT1 */
+                                                "GPIO267_AC27"; /* DAT0 */
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                ste,config = <&out_hi>;
+                                        };
+                                };
+
+                                musb_sleep_mode: musb_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO256_AF28", /* NXT */
+                                                "GPIO258_AD29", /* XCLK */
+                                                "GPIO259_AC29"; /* DIR */
+                                                ste,config = <&slpm_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                ste,config = <&slpm_out_hi_wkup_pdis>;
+                                        };
+                                        sleep_cfg3 {
+                                                ste,pins =
+                                                "GPIO260_AD28", /* DAT7 */
+                                                "GPIO261_AD26", /* DAT6 */
+                                                "GPIO262_AE26", /* DAT5 */
+                                                "GPIO263_AG29", /* DAT4 */
+                                                "GPIO264_AE27", /* DAT3 */
+                                                "GPIO265_AD27", /* DAT2 */
+                                                "GPIO266_AC28", /* DAT1 */
+                                                "GPIO267_AC27"; /* DAT0 */
+                                                ste,config = <&slpm_in_wkup_pdis_en>;
+                                        };
+                                };
+                        };
+
+                        mcde {
+                                lcd_default_mode: lcd_default {
+                                        default_mux {
+                                                /* Mux in VSI0 and all the data lines */
+                                                ste,function = "lcd";
+                                                ste,pins =
+                                                "lcdvsi0_a_1", /* VSI0 for LCD */
+                                                "lcd_d0_d7_a_1", /* Data lines */
+                                                "lcd_d8_d11_a_1", /* TV-out */
+                                                "lcdaclk_b_1", /* Clock line for TV-out */
+                                                "lcdvsi1_a_1"; /* VSI1 for HDMI */
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO68_E1", /* VSI0 */
+                                                "GPIO69_E2"; /* VSI1 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+                                lcd_sleep_mode: lcd_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins = "GPIO69_E2"; /* VSI1 */
+                                                ste,config = <&slpm_in_wkup_pdis>;
+                                        };
+                                };
+                        };
+
+                        ske {
+                                /* SKE keys on position 2 in an 8x8 matrix */
+                                ske_kpa2_default_mode: ske_kpa2_default {
+                                        default_mux {
+                                                ste,function = "kp";
+                                                ste,pins = "kp_a_2";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO153_B17", /* I7 */
+                                                "GPIO154_C16", /* I6 */
+                                                "GPIO155_C19", /* I5 */
+                                                "GPIO156_C17", /* I4 */
+                                                "GPIO161_D21", /* I3 */
+                                                "GPIO162_D20", /* I2 */
+                                                "GPIO163_C20", /* I1 */
+                                                "GPIO164_B21"; /* I0 */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO157_A18", /* O7 */
+                                                "GPIO158_C18", /* O6 */
+                                                "GPIO159_B19", /* O5 */
+                                                "GPIO160_B20", /* O4 */
+                                                "GPIO165_C21", /* O3 */
+                                                "GPIO166_A22", /* O2 */
+                                                "GPIO167_B24", /* O1 */
+                                                "GPIO168_C22"; /* O0 */
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                                ske_kpa2_sleep_mode: ske_kpa2_sleep {
+                                        sleep_cfg1 {
+                                                ste,pins =
+                                                "GPIO153_B17", /* I7 */
+                                                "GPIO154_C16", /* I6 */
+                                                "GPIO155_C19", /* I5 */
+                                                "GPIO156_C17", /* I4 */
+                                                "GPIO161_D21", /* I3 */
+                                                "GPIO162_D20", /* I2 */
+                                                "GPIO163_C20", /* I1 */
+                                                "GPIO164_B21"; /* I0 */
+                                                ste,config = <&slpm_in_pu_wkup_pdis_en>;
+                                        };
+                                        sleep_cfg2 {
+                                                ste,pins =
+                                                "GPIO157_A18", /* O7 */
+                                                "GPIO158_C18", /* O6 */
+                                                "GPIO159_B19", /* O5 */
+                                                "GPIO160_B20", /* O4 */
+                                                "GPIO165_C21", /* O3 */
+                                                "GPIO166_A22", /* O2 */
+                                                "GPIO167_B24", /* O1 */
+                                                "GPIO168_C22"; /* O0 */
+                                                ste,config = <&slpm_out_lo_pdis>;
+                                        };
+                                };
+                                /*
+                                 * SKE keys on position 1 and "other C1" combi giving
+                                 * six rows of six keys.
+                                 */
+                                ske_kpaoc1_default_mode: ske_kpaoc1_default {
+                                        default_mux {
+                                                ste,function = "kp";
+                                                ste,pins = "kp_a_1", "kp_oc1_1";
+                                        };
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO91_B6", /* KP_O0 */
+                                                "GPIO90_A3", /* KP_O1 */
+                                                "GPIO87_B3", /* KP_O2 */
+                                                "GPIO86_C6", /* KP_O3 */
+                                                "GPIO96_D8", /* KP_O6 */
+                                                "GPIO94_D7"; /* KP_O7 */
+                                                ste,config = <&out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins =
+                                                "GPIO93_B7", /* KP_I0 */
+                                                "GPIO92_D6", /* KP_I1 */
+                                                "GPIO89_E6", /* KP_I2 */
+                                                "GPIO88_C4", /* KP_I3 */
+                                                "GPIO97_D9", /* KP_I6 */
+                                                "GPIO95_E8"; /* KP_I7 */
+                                                ste,config = <&in_pu>;
+                                        };
+                                };
+                        };
+
+                        wlan {
+                                wlan_default_mode: wlan_default {
+                                        /*
+                                         * Activate this mode with the WLAN chip.
+                                         * These are plain GPIO pins used by WLAN
+                                         */
+                                        default_cfg1 {
+                                                ste,pins =
+                                                "GPIO226_AF8", /* WLAN_PMU_EN */
+                                                "GPIO85_D5"; /* WLAN_ENA */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        default_cfg2 {
+                                                ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 76704ec0ffcc..1c3574435ea8 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -12,6 +12,28 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd-supply = <&ab8500_ldo_aux1_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>;
+
+                button@139 {
+                        /* Proximity sensor */
+                        gpios = <&gpio6 25 0x4>;
+                        linux,code = <11>; /* SW_FRONT_PROXIMITY */
+                        label = "SFH7741 Proximity Sensor";
+                };
+                button@145 {
+                        /* Hall sensor */
+                        gpios = <&gpio4 17 0x4>;
+                        linux,code = <0>; /* SW_LID */
+                        label = "HED54XXU11 Hall Effect Sensor";
+                };
+        };
+
         soc {
                 i2c@80004000 {
                         stmpe1601: stmpe1601@40 {
@@ -74,5 +96,24 @@
                                 rohm,flip-y;
                         };
                 };
+
+                pinctrl {
+                        prox {
+                                prox_stuib_mode: prox_stuib {
+                                        stuib_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        hall {
+                                hall_stuib_mode: stuib_tvk {
+                                        stuib_cfg {
+                                                ste,pins = "GPIO145_C13";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 76d3ef13175f..c40565320978 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -14,27 +14,105 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd-supply = <&ab8500_ldo_aux1_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
+
+                button@139 {
+                        /* Proximity sensor */
+                        gpios = <&gpio6 25 0x4>;
+                        linux,code = <11>; /* SW_FRONT_PROXIMITY */
+                        label = "SFH7741 Proximity Sensor";
+                };
+                button@145 {
+                        /* Hall sensor */
+                        gpios = <&gpio4 17 0x4>;
+                        linux,code = <0>; /* SW_LID */
+                        label = "HED54XXU11 Hall Effect Sensor";
+                };
+        };
+
         soc {
-                /* Add Synaptics touch screen, TC35892 keypad etc here */
+                /* Add Synaptics touch screen, TC35893 keypad etc here */
                 i2c@80004000 {
-                        tc3589x@44 {
-                                compatible = "tc3589x";
+                        tc35893@44 {
+                                compatible = "toshiba,tc35893";
                                 reg = <0x44>;
                                 interrupt-parent = <&gpio6>;
                                 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&tc35893_tvk_mode>;
 
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <1>;
 
                                 tc3589x_gpio {
-                                        compatible = "tc3589x-gpio";
-                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                        compatible = "toshiba,tc3589x-gpio";
+                                        interrupts = <0>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
                                 };
+                                tc3589x_keypad {
+                                        compatible = "toshiba,tc3589x-keypad";
+                                        interrupts = <6>;
+                                        debounce-delay-ms = <4>;
+                                        keypad,num-columns = <8>;
+                                        keypad,num-rows = <8>;
+                                        linux,no-autorepeat;
+                                        linux,wakeup;
+                                        linux,keymap = <0x0301006b
+                                                        0x04010066
+                                                        0x06040072
+                                                        0x040200d7
+                                                        0x0303006a
+                                                        0x0205000e
+                                                        0x0607008b
+                                                        0x0500001c
+                                                        0x0403000b
+                                                        0x03040034
+                                                        0x05020067
+                                                        0x0305006c
+                                                        0x040500e7
+                                                        0x0005009e
+                                                        0x06020073
+                                                        0x01030039
+                                                        0x07060069
+                                                        0x050500d9>;
+                                };
+                        };
+                };
+                pinctrl {
+                        /* Pull up this GPIO pin */
+                        tc35893 {
+                                tc35893_tvk_mode: tc35893_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO218_AH11";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        prox {
+                                prox_tvk_mode: prox_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        hall {
+                                hall_tvk_mode: hall_tvk {
+                                        tvk_cfg {
+                                                ste,pins = "GPIO145_C13";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index aa3f02060fdd..0c1e8d871ed1 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -11,37 +11,57 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-family-pinctrl.dtsi"
 
 / {
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                button@1 {
-                        linux,code = <11>;
-                        label = "SFH7741 Proximity Sensor";
+        soc {
+                usb_per5@a03e0000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&musb_default_mode>;
+                        pinctrl-1 = <&musb_sleep_mode>;
                 };
-        };
 
-        soc {
                 uart@80120000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart0_default_mode>;
+                        pinctrl-1 = <&uart0_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80121000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart1_default_mode>;
+                        pinctrl-1 = <&uart1_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80007000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart2_default_mode>;
+                        pinctrl-1 = <&uart2_sleep_mode>;
                         status = "okay";
                 };
 
+                i2c@80004000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c0_default_mode>;
+                        pinctrl-1 = <&i2c0_sleep_mode>;
+                };
+
+                i2c@80122000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c1_default_mode>;
+                        pinctrl-1 = <&i2c1_sleep_mode>;
+                };
+
                 i2c@80128000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c2_default_mode>;
+                        pinctrl-1 = <&i2c2_sleep_mode>;
                         lp5521@33 {
                                 compatible = "national,lp5521";
                                 reg = <0x33>;
@@ -85,6 +105,12 @@
                         };
                 };
 
+                i2c@80110000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c3_default_mode>;
+                        pinctrl-1 = <&i2c3_sleep_mode>;
+                };
+
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
@@ -94,8 +120,9 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
                         vqmmc-supply = <&vmmci>;
-
-                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi0_default_mode>;
+                        pinctrl-1 = <&sdi0_sleep_mode>;
 
                         status = "okay";
                 };
@@ -105,6 +132,9 @@
                         arm,primecell-periphid = <0x10480180>;
                         max-frequency = <100000000>;
                         bus-width = <4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi1_default_mode>;
+                        pinctrl-1 = <&sdi1_sleep_mode>;
 
                         status = "okay";
                 };
@@ -115,6 +145,9 @@
                         max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi2_default_mode>;
+                        pinctrl-1 = <&sdi2_sleep_mode>;
 
                         status = "okay";
                 };
@@ -126,6 +159,9 @@
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi4_default_mode>;
+                        pinctrl-1 = <&sdi4_sleep_mode>;
 
                         status = "okay";
                 };
@@ -137,7 +173,21 @@
                         stericsson,audio-codec = <&codec>;
                 };
 
+                msp0: msp@80123000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp0_default_mode>;
+                        status = "okay";
+                };
+
                 msp1: msp@80124000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp1_default_mode>;
+                        status = "okay";
+                };
+
+                msp2: msp@80117000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp2_default_mode>;
                         status = "okay";
                 };
 
@@ -198,5 +248,11 @@
                                 };
                         };
                 };
+
+                mcde@a0350000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&lcd_default_mode>;
+                        pinctrl-1 = <&lcd_sleep_mode>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index b2cd7bc2752f..40f0ecdf9303 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -28,18 +28,20 @@
                                 reg = <0x33>;
                         };
 
-                        tc3589x@42 {
-                                compatible = "tc3589x";
+                        tc35892@42 {
+                                compatible = "toshiba,tc35892";
                                 reg = <0x42>;
                                 interrupt-parent = <&gpio6>;
                                 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&tc35892_hrefprev60_mode>;
 
                                 interrupt-controller;
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <1>;
 
                                 tc3589x_gpio: tc3589x_gpio {
                                         compatible = "tc3589x-gpio";
-                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                        interrupts = <0>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
@@ -49,11 +51,77 @@
                         };
                 };
 
+                ssp@80002000 {
+                        /*
+                         * On the first generation boards, this SSP/SPI port was connected
+                         * to the AB8500.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ssp0_hrefprev60_mode>;
+                };
+
+                // External Micro SD slot
+                sdi0_per1@80126000 {
+                        cd-gpios  = <&tc3589x_gpio 3 0x4>;
+                };
+
                 vmmci: regulator-gpio {
                         gpios = <&tc3589x_gpio 18 0x4>;
                         enable-gpio = <&tc3589x_gpio 17 0x4>;
+                };
+
+                pinctrl {
+                        /* Set this up using hogs */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ipgpio_hrefprev60_mode>;
 
-                        status = "okay";
+                        ssp0 {
+                                ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
+                                        hrefprev60_mux {
+                                                ste,function = "ssp0";
+                                                ste,pins = "ssp0_a_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+
+                                };
+                        };
+                        sdi0 {
+                                /* This additional pin needed on early MOP500 and HREFs previous to v60 */
+                                sdi0_default_mode: sdi0_default {
+                                        hrefprev60_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0dat31dir_a_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+
+                                };
+                        };
+                        tc35892 {
+                                tc35892_hrefprev60_mode: tc35892_hrefprev60 {
+                                        hrefprev60_cfg {
+                                                ste,pins = "GPIO217_AH12";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        ipgpio {
+                                 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
+                                        hrefprev60_mux {
+                                                ste,function = "ipgpio";
+                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
+                                        };
+                                        hrefprev60_cfg1 {
+                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                ste,config = <&in_pu>;
+                                        };
+                                 };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index aed511b47a9e..3b6d1181939b 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -16,55 +16,226 @@
         model = "ST-Ericsson HREF (v60+) platform with Device Tree";
         compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
 
-        gpio_keys {
-                button@1 {
-                        gpios = <&gpio5 25 0x4>;
-                };
-        };
-
         soc {
                 // External Micro SD slot
                 sdi0_per1@80126000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <4>;
-                        mmc-cap-sd-highspeed;
-                        mmc-cap-mmc-highspeed;
-                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
-
                         cd-gpios  = <&gpio2 31 0x4>; // 95
-
-                        status = "okay";
                 };
 
-                // WLAN SDIO channel
-                sdi1_per2@80118000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <4>;
-
-                        status = "okay";
-                };
-
-                // PoP:ed eMMC
-                sdi2_per3@80005000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
-
-                        status = "okay";
+                vmmci: regulator-gpio {
+                        gpios = <&gpio0 5 0x4>;
+                        enable-gpio = <&gpio5 9 0x4>;
                 };
 
-                // On-board eMMC
-                sdi4_per2@80114000 {
-                        arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <100000000>;
-                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
-                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                pinctrl {
+                        /*
+                         * Set this up using hogs, as time goes by and as seems fit, these
+                         * can be moved over to being controlled by respective device.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ipgpio_hrefv60_mode>,
+                                  <&accel_hrefv60_mode>,
+                                  <&magneto_hrefv60_mode>,
+                                  <&etm_hrefv60_mode>,
+                                  <&nahj_hrefv60_mode>,
+                                  <&nfc_hrefv60_mode>,
+                                  <&force_hrefv60_mode>,
+                                  <&dipro_hrefv60_mode>,
+                                  <&vaudio_hf_hrefv60_mode>,
+                                  <&gbf_hrefv60_mode>,
+                                  <&hdtv_hrefv60_mode>,
+                                  <&touch_hrefv60_mode>;
 
-                        status = "okay";
+                        sdi0 {
+                                /* SD card detect GPIO pin, extend default state */
+                                sdi0_default_mode: sdi0_default {
+                                        default_hrefv60_cfg1 {
+                                                ste,pins = "GPIO95_E8";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        ipgpio {
+                                /*
+                                 * XENON Flashgun on image processor GPIO (controlled from image
+                                 * processor firmware), mux in these image processor GPIO lines 0
+                                 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
+                                 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
+                                 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
+                                 */
+                                ipgpio_hrefv60_mode: ipgpio_hrefv60 {
+                                        hrefv60_mux {
+                                                ste,function = "ipgpio";
+                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
+                                        };
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                ste,config = <&in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO21_AB3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg3 {
+                                                ste,pins = "GPIO64_F3";
+                                                ste,config = <&out_lo>;
+                                        };
+                                };
+                        };
+                        accelerometer {
+                                accel_hrefv60_mode: accel_hrefv60 {
+                                        /* Accelerometer interrupt lines 1 & 2 */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO82_C1", "GPIO83_D3";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        magnetometer {
+                                magneto_hrefv60_mode: magneto_hrefv60 {
+                                        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO31_V3";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO32_V2";
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                };
+                        };
+                        etm {
+                                /*
+                                 * Drive D19-D23 for the ETM PTM trace interface low,
+                                 * (presumably pins are unconnected therefore grounded here,
+                                 * the "other alt C1" setting enables these pins)
+                                 */
+                                etm_hrefv60_mode: etm_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins =
+                                                "GPIO70_G5",
+                                                "GPIO71_G4",
+                                                "GPIO72_H4",
+                                                "GPIO73_H3",
+                                                "GPIO74_J3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        nahj {
+                                nahj_hrefv60_mode: nahj_hrefv60 {
+                                        /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO76_J2";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO216_AG12";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                 };
+                        };
+                        nfc {
+                                nfc_hrefv60_mode: nfc_hrefv60 {
+                                        /* NFC ENA and RESET to low, pulldown IRQ line */
+                                        hrefv60_cfg1 {
+                                                ste,pins =
+                                                "GPIO77_H1", /* NFC_ENA */
+                                                "GPIO142_C11"; /* NFC_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO144_B13"; /* NFC_IRQ */
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                 };
+                        };
+                        force {
+                                force_hrefv60_mode: force_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins =
+                                                "GPIO92_D6", /* FORCE_SENSING_RST */
+                                                "GPIO97_D9"; /* FORCE_SENSING_WU */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        dipro {
+                                dipro_hrefv60_mode: dipro_hrefv60 {
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO139_C9"; /* DIPRO_INT */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                 };
+                        };
+                        vaudio_hf {
+                                vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
+                                        /* Audio Amplifier HF enable GPIO */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                 };
+                        };
+                        gbf {
+                                gbf_hrefv60_mode: gbf_hrefv60 {
+                                        /*
+                                         * GBF (GPS, Bluetooth, FM-radio) interface,
+                                         * pull low to reset state
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        hdtv {
+                                hdtv_hrefv60_mode: hdtv_hrefv60 {
+                                        /* MSP : HDTV INTERFACE GPIO line */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO192_AJ27";
+                                                ste,config = <&gpio_in_pd>;
+                                        };
+                                 };
+                        };
+                        touch {
+                                touch_hrefv60_mode: touch_hrefv60 {
+                                        /*
+                                         * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
+                                         * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
+                                         * reset signals low.
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO143_D12", "GPIO146_D13";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO67_G2";
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        mcde {
+                                lcd_hrefv60_mode: lcd_hrefv60 {
+                                        /*
+                                         * Display Interface 1 uses GPIO 65 for RST (reset).
+                                         * Display Interface 2 uses GPIO 66 for RST (reset).
+                                         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
+                                         */
+                                        hrefv60_cfg1 {
+                                                ste,pins ="GPIO65_F1";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins ="GPIO66_G3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
index efddee9403c4..e6f22b266420 100644
--- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -31,17 +31,57 @@
                 ste,output = <OUTPUT_LOW>;
         };
 
+        gpio_in_pu: gpio_input_pull_up {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,input = <INPUT_PULLUP>;
+        };
+
+        gpio_in_pd: gpio_input_pull_down {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,input = <INPUT_PULLDOWN>;
+        };
+
         gpio_out_lo: gpio_output_low {
                 ste,gpio = <GPIOMODE_ENABLED>;
                 ste,output = <OUTPUT_LOW>;
         };
 
+        gpio_out_hi: gpio_output_high {
+                ste,gpio = <GPIOMODE_ENABLED>;
+                ste,output = <OUTPUT_HIGH>;
+        };
+
+        slpm_pdis: slpm_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_wkup_pdis: slpm_wkup_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_wkup_pdis_en: slpm_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
         slpm_in_pu: slpm_in_pu {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-input = <SLPM_INPUT_PULLUP>;
                 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
         };
 
+        slpm_in_pdis: slpm_in_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         slpm_in_wkup_pdis: slpm_in_wkup_pdis {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-input = <SLPM_DIR_INPUT>;
@@ -49,6 +89,20 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
+        slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-input = <SLPM_INPUT_PULLUP>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
         slpm_out_lo: slpm_out_lo {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-output = <SLPM_OUTPUT_LOW>;
@@ -68,6 +122,20 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        slpm_out_lo_pdis: slpm_out_lo_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
+        slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis {
+                ste,sleep = <SLPM_ENABLED>;
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         slpm_out_wkup_pdis: slpm_out_wkup_pdis {
                 ste,sleep = <SLPM_ENABLED>;
                 ste,sleep-output = <SLPM_DIR_OUTPUT>;
@@ -81,6 +149,18 @@
                 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
         };
 
+        in_wkup_pdis_en: in_wkup_pdis_en {
+                ste,sleep-input = <SLPM_DIR_INPUT>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
+        };
+
+        out_lo_wkup_pdis: out_lo_wkup_pdis {
+                ste,sleep-output = <SLPM_OUTPUT_LOW>;
+                ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
+                ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
+        };
+
         out_hi_wkup_pdis: out_hi_wkup_pdis {
                 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
                 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 16c3888b7b15..f557feb997f4 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -67,10 +67,6 @@
 
         /* Custom board node with GPIO pins to active etc */
         usb-s8815 {
-                /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
-                ethernet-gpio {
-                        gpios = <&gpio3 8 0x1>;
-                };
                 /* This will bias the MMC/SD card detect line */
                 mmcsd-gpio {
                         gpios = <&gpio3 16 0x1>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 79425e3836ce..5acc0449676a 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -769,14 +769,14 @@
                 #size-cells = <1>;
                 ranges;
 
-                vica: intc@0x10140000 {
+                vica: intc@10140000 {
                         compatible = "arm,versatile-vic";
                         interrupt-controller;
                         #interrupt-cells = <1>;
                         reg = <0x10140000 0x20>;
                 };
 
-                vicb: intc@0x10140020 {
+                vicb: intc@10140020 {
                         compatible = "arm,versatile-vic";
                         interrupt-controller;
                         #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index f0b39f835914..97d5d21b7db7 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-family-pinctrl.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -75,6 +76,8 @@
 
         leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpioled_snowball_mode>;
                 used-led {
                         label = "user_led";
                         gpios = <&gpio4 14 0x4>;
@@ -84,6 +87,11 @@
         };
 
         soc {
+                usb_per5@a03e0000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&musb_default_mode>;
+                        pinctrl-1 = <&musb_sleep_mode>;
+                };
 
                 sound {
                         compatible = "stericsson,snd-soc-mop500";
@@ -92,7 +100,21 @@
                         stericsson,audio-codec = <&codec>;
                 };
 
+                msp0: msp@80123000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp0_default_mode>;
+                        status = "okay";
+                };
+
                 msp1: msp@80124000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp1_default_mode>;
+                        status = "okay";
+                };
+
+                msp2: msp@80117000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&msp2_default_mode>;
                         status = "okay";
                 };
 
@@ -110,6 +132,8 @@
                                 interrupt-parent = <&gpio4>;
                                 vdd33a-supply = <&en_3v3_reg>;
                                 vddvario-supply = <&db8500_vape_reg>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&eth_snowball_mode>;
 
                                 reg-shift = <1>;
                                 reg-io-width = <2>;
@@ -122,10 +146,8 @@
                 };
 
                 vmmci: regulator-gpio {
-                        gpios = <&gpio6 25 0x4>;
-                        enable-gpio = <&gpio7 4 0x4>;
-
-                        status = "okay";
+                        gpios = <&gpio7 4 0x4>;
+                        enable-gpio = <&gpio6 25 0x4>;
                 };
 
                 // External Micro SD slot
@@ -136,6 +158,9 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
                         vqmmc-supply = <&vmmci>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi0_default_mode>;
+                        pinctrl-1 = <&sdi0_sleep_mode>;
 
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
@@ -143,6 +168,27 @@
                         status = "okay";
                 };
 
+                // WLAN SDIO channel
+                sdi1_per2@80118000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <100000000>;
+                        bus-width = <4>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi1_default_mode>;
+                        pinctrl-1 = <&sdi1_sleep_mode>;
+
+                        status = "okay";
+                };
+
+                // Unused PoP eMMC - register and put it to sleep by default */
+                sdi2_per3@80005000 {
+                        arm,primecell-periphid = <0x10480180>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&sdi2_sleep_mode>;
+
+                        status = "okay";
+                };
+
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
@@ -150,22 +196,63 @@
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdi4_default_mode>;
+                        pinctrl-1 = <&sdi4_sleep_mode>;
 
                         status = "okay";
                 };
 
                 uart@80120000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart0_default_mode>;
+                        pinctrl-1 = <&uart0_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80121000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart1_default_mode>;
+                        pinctrl-1 = <&uart1_sleep_mode>;
                         status = "okay";
                 };
 
                 uart@80007000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&uart2_default_mode>;
+                        pinctrl-1 = <&uart2_sleep_mode>;
                         status = "okay";
                 };
 
+                i2c@80004000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c0_default_mode>;
+                        pinctrl-1 = <&i2c0_sleep_mode>;
+                };
+
+                i2c@80122000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c1_default_mode>;
+                        pinctrl-1 = <&i2c1_sleep_mode>;
+                };
+
+                i2c@80128000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c2_default_mode>;
+                        pinctrl-1 = <&i2c2_sleep_mode>;
+                };
+
+                i2c@80110000 {
+                        pinctrl-names = "default","sleep";
+                        pinctrl-0 = <&i2c3_default_mode>;
+                        pinctrl-1 = <&i2c3_sleep_mode>;
+                };
+
+                ssp@80002000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ssp0_snowball_mode>;
+                };
+
                 cpufreq-cooling {
                         status = "okay";
                 };
@@ -266,5 +353,141 @@
                                 };
                         };
                 };
+
+                pinctrl {
+                        /*
+                         * Set this up using hogs, as time goes by and as seems fit, these
+                         * can be moved over to being controlled by respective device.
+                         */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&accel_snowball_mode>,
+                                  <&magneto_snowball_mode>,
+                                  <&gbf_snowball_mode>,
+                                  <&wlan_snowball_mode>;
+
+                        ethernet {
+                                /*
+                                 * Mux in "SM" which is used for the
+                                 * SMSC911x Ethernet adapter
+                                 */
+                                eth_snowball_mode: eth_snowball {
+                                        snowball_mux {
+                                                ste,function = "sm";
+                                                ste,pins = "sm_b_1";
+                                        };
+                                        /* LAN IRQ pin */
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO140_B11";
+                                                ste,config = <&in_nopull>;
+                                        };
+                                        /* LAN reset pin */
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO141_C12";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+
+                                };
+                        };
+                        sdi0 {
+                                sdi0_default_mode: sdi0_default {
+                                        snowball_mux {
+                                                ste,function = "mc0";
+                                                ste,pins = "mc0dat31dir_a_1";
+                                        };
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                ste,config = <&out_hi>;
+                                        };
+
+                                };
+                        };
+                        ssp0 {
+                                ssp0_snowball_mode: ssp0_snowball_default {
+                                        snowball_mux {
+                                                ste,function = "ssp0";
+                                                ste,pins = "ssp0_a_1";
+                                        };
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO144_B13"; /* FRM */
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                ste,config = <&in_pd>;
+                                        };
+                                        snowball_cfg3 {
+                                                ste,pins =
+                                                "GPIO146_D13", /* TXD */
+                                                "GPIO143_D12"; /* CLK */
+                                                ste,config = <&out_lo>;
+                                        };
+
+                                };
+                        };
+                        gpio_led {
+                                gpioled_snowball_mode: gpioled_default {
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO142_C11";
+                                                ste,config = <&gpio_out_hi>;
+                                        };
+
+                                };
+                        };
+                        accelerometer {
+                                accel_snowball_mode: accel_snowball {
+                                        /* Accelerometer lines */
+                                        snowball_cfg1 {
+                                                ste,pins =
+                                                "GPIO163_C20", /* ACCEL_IRQ1 */
+                                                "GPIO164_B21"; /* ACCEL_IRQ2 */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        magnetometer {
+                                magneto_snowball_mode: magneto_snowball {
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO165_C21"; /* MAG_DRDY */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                        gbf {
+                                gbf_snowball_mode: gbf_snowball {
+                                        /*
+                                         * GBF (GPS, Bluetooth, FM-radio) interface,
+                                         * pull low to reset state
+                                         */
+                                        snowball_cfg1 {
+                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                 };
+                        };
+                        wlan {
+                                wlan_snowball_mode: wlan_snowball {
+                                        /*
+                                         * Activate this mode with the WLAN chip.
+                                         * These are plain GPIO pins used by WLAN
+                                         */
+                                        snowball_cfg1 {
+                                                ste,pins =
+                                                "GPIO161_D21", /* WLAN_PMU_EN */
+                                                "GPIO215_AH13"; /* WLAN_ENA */
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        snowball_cfg2 {
+                                                ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
+                                                ste,config = <&gpio_in_pu>;
+                                        };
+                                };
+                        };
+                };
+
+                mcde@a0350000 {
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&lcd_default_mode>;
+                        pinctrl-1 = <&lcd_sleep_mode>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 8a1032c1ffc9..a9da4800daf0 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -307,7 +307,7 @@
                 clocks = <&i2c0_clk>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                ab3100: ab3100@0x48 {
+                ab3100: ab3100@48 {
                         compatible = "stericsson,ab3100";
                         reg = <0x48>;
                         interrupt-parent = <&vica>;
@@ -385,10 +385,10 @@
                 clocks = <&i2c1_clk>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                fwcam0: fwcam@0x10 {
+                fwcam0: fwcam@10 {
                         reg = <0x10>;
                 };
-                fwcam1: fwcam@0x5d {
+                fwcam1: fwcam@5d {
                         reg = <0x5d>;
                 };
         };
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b24d1e4..e56449d41481 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,24 @@
                                         };
                                 };
                         };
+
+                        sbc_i2c0 {
+                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        sbc_i2c1 {
+                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-front {
@@ -143,6 +161,24 @@
                                 reg             = <0x7000 0x100>;
                                 st,bank-name    = "PIO12";
                         };
+
+                        i2c0 {
+                                pinctrl_i2c0_default: i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                pinctrl_i2c1_default: i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8ded4b49..d9c7dd1d95a4 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
 #include "stih41x.dtsi"
 #include "stih415-clock.dtsi"
 #include "stih415-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
 
         L2: cache-controller {
@@ -83,5 +84,57 @@
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_sbc_serial1>;
                 };
+
+                i2c@fed40000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed40000 0x110>;
+                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fed41000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed41000 0x110>;
+                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c1_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe540000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe540000 0x110>;
+                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe541000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe541000 0x110>;
+                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c1_default>;
+
+                        status          = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c979262..b29ff4ba542c 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,24 @@
                                         };
                                 };
                         };
+
+                        sbc_i2c0 {
+                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        sbc_i2c1 {
+                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-front {
@@ -175,6 +193,23 @@
                                 };
                         };
 
+                        i2c0 {
+                                pinctrl_i2c0_default: i2c0-default {
+                                        st,pins {
+                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        i2c1 {
+                                pinctrl_i2c1_default: i2c1-default {
+                                        st,pins {
+                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326ea7d07..b7ab47b95816 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
         L2: cache-controller {
                 compatible = "arm,pl310-cache";
@@ -92,5 +93,57 @@
                         pinctrl-0       = <&pinctrl_sbc_serial1>;
                         clocks          = <&CLK_SYSIN>;
                 };
+
+                i2c@fed40000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed40000 0x110>;
+                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fed41000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfed41000 0x110>;
+                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_i2c1_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe540000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe540000 0x110>;
+                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c0_default>;
+
+                        status          = "disabled";
+                };
+
+                i2c@fe541000 {
+                        compatible      = "st,comms-ssc4-i2c";
+                        reg             = <0xfe541000 0x110>;
+                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks          = <&CLK_SYSIN>;
+                        clock-names     = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_i2c1_default>;
+
+                        status          = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2b8f5b..1e6aa92772f5 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -37,5 +37,14 @@
                         };
                 };
 
+                /* HDMI Tx I2C */
+                i2c@fed41000 {
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        i2c-min-scl-pulse-width-us = <0>;
+                        i2c-min-sda-pulse-width-us = <5>;
+
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e18143b1b..0ef0a69df8ea 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -38,5 +38,27 @@
                                 default-state = "off";
                         };
                 };
+
+                i2c@fed40000 {
+                        status = "okay";
+                };
+
+                /* HDMI Tx I2C */
+                i2c@fed41000 {
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        i2c-min-scl-pulse-width-us = <0>;
+                        i2c-min-sda-pulse-width-us = <5>;
+
+                        status = "okay";
+                };
+
+                i2c@fe540000 {
+                        status = "okay";
+                };
+
+                i2c@fe541000 {
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index eb4d73b6a090..d4b081d6a167 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -18,10 +18,6 @@
         model = "Mele A1000";
         compatible = "mele,a1000", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 425a7db898c5..b139ee6bcf99 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -17,15 +17,6 @@
         model = "Cubietech Cubieboard";
         compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
 
-        aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-        };
-
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b3ae51fa9372..3a1595f67823 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -18,10 +18,6 @@
         model = "Miniand Hackberry";
         compatible = "miniand,hackberry", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 0c1447c68059..70b3323caf1a 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -18,10 +18,6 @@
         model = "PineRiver Mini X-Plus";
         compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 uart0: serial@01c28000 {
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 319cc6b509da..040bb0eba152 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -15,6 +15,12 @@
 / {
         interrupt-parent = <&intc>;
 
+        aliases {
+                ethernet0 = &emac;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -66,6 +72,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -131,12 +160,11 @@
                                 "apb0_ir1", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -158,6 +186,126 @@
                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
                                 "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
         };
 
         soc@01c00000 {
@@ -266,11 +414,23 @@
                         reg = <0x01c20c90 0x10>;
                 };
 
+                rtc: rtc@01c20d00 {
+                        compatible = "allwinner,sun4i-rtc";
+                        reg = <0x01c20d00 0x20>;
+                        interrupts = <24>;
+                };
+
                 sid: eeprom@01c23800 {
                         compatible = "allwinner,sun4i-sid";
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index e674c94c7206..ea16054857a4 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -16,6 +16,10 @@
 / {
         interrupt-parent = <&intc>;
 
+        aliases {
+                ethernet0 = &emac;
+        };
+
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a8";
@@ -63,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -123,12 +150,11 @@
                                 "apb0_ir", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -147,6 +173,102 @@
                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
                                 "apb1_uart2", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -260,6 +382,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
new file mode 100644
index 000000000000..fe2ce0acdb06
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i-a13.dtsi"
+
+/ {
+        model = "Olimex A13-Olinuxino Micro";
+        compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
+
+        soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxinom: led_pins@0 {
+                                allwinner,pins = "PG9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart1: serial@01c28400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_pins_b>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinom>;
+
+                power {
+                        label = "a13-olinuxino-micro:green:power";
+                        gpios = <&pio 6 9 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 9e508dcc4245..a4ba5ff010cf 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -18,10 +18,6 @@
         model = "Olimex A13-Olinuxino";
         compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
 
-        chosen {
-                bootargs = "earlyprintk console=ttyS0,115200";
-        };
-
         soc@01c00000 {
                 pinctrl@01c20800 {
                         led_pins_olinuxino: led_pins@0 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 1ccd75d37f49..320335abfccd 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -125,12 +148,11 @@
                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                /* dummy is pll6 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {
@@ -227,6 +345,12 @@
                         reg = <0x01c23800 0x10>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <29>;
+                };
+
                 uart1: serial@01c28400 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28400 0x400>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 7f5878c2784a..5256ad9be52c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -212,6 +212,24 @@
                         };
                 };
 
+                ahb1_rst: reset@01c202c0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-ahb1-reset";
+                        reg = <0x01c202c0 0xc>;
+                };
+
+                apb1_rst: reset@01c202d0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x01c202d0 0x4>;
+                };
+
+                apb2_rst: reset@01c202d8 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x01c202d8 0x4>;
+                };
+
                 timer@01c20c00 {
                         compatible = "allwinner,sun4i-timer";
                         reg = <0x01c20c00 0xa0>;
@@ -235,6 +253,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 16>;
+                        resets = <&apb2_rst 16>;
                         status = "disabled";
                 };
 
@@ -245,6 +264,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 17>;
+                        resets = <&apb2_rst 17>;
                         status = "disabled";
                 };
 
@@ -255,6 +275,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 18>;
+                        resets = <&apb2_rst 18>;
                         status = "disabled";
                 };
 
@@ -265,6 +286,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 19>;
+                        resets = <&apb2_rst 19>;
                         status = "disabled";
                 };
 
@@ -275,6 +297,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 20>;
+                        resets = <&apb2_rst 20>;
                         status = "disabled";
                 };
 
@@ -285,6 +308,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&apb2_gates 21>;
+                        resets = <&apb2_rst 21>;
                         status = "disabled";
                 };
 
@@ -298,5 +322,15 @@
                         #interrupt-cells = <3>;
                         interrupts = <1 9 0xf04>;
                 };
+
+                cpucfg@01f01c00 {
+                        compatible = "allwinner,sun6i-a31-cpuconfig";
+                        reg = <0x01f01c00 0x300>;
+                };
+
+                prcm@01f01c00 {
+                        compatible = "allwinner,sun6i-a31-prcm";
+                        reg = <0x01f01400 0x200>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8a1009d6c829..f9dcb61a5305 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -33,6 +33,24 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0135039eff96..119f066f0d98 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -16,6 +16,10 @@
 / {
         interrupt-parent = <&gic>;
 
+        aliases {
+                ethernet0 = &emac;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -49,10 +53,11 @@
                         clock-frequency = <24000000>;
                 };
 
-                osc32k: osc32k {
+                osc32k: clk@0 {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                 };
 
                 pll1: pll1@01c20000 {
@@ -62,23 +67,34 @@
                         clocks = <&osc24M>;
                 };
 
-                /*
-                 * This is a dummy clock, to be used as placeholder on
-                 * other mux clocks when a specific parent clock is not
-                 * yet implemented. It should be dropped when the driver
-                 * is complete.
-                 */
-                pll6: pll6 {
+                pll4: pll4@01c20018 {
                         #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                 };
 
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-cpu-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
                 };
 
                 axi: axi@01c20054 {
@@ -137,7 +153,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -159,6 +175,162 @@
                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc3";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                pata_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "pata";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                ir1_clk: clk@01c200b4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir1";
+                };
+
+                spi3_clk: clk@01c200d4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200d4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi3";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
+
+                /*
+                 * Dummy clock used by output clocks
+                 */
+                osc24M_32k: clk@1 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <750>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "osc24M_32k";
+                };
+
+                clk_out_a: clk@01c201f0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f0 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_a";
+                };
+
+                clk_out_b: clk@01c201f4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-out-clk";
+                        reg = <0x01c201f4 0x4>;
+                        clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+                        clock-output-names = "clk_out_b";
+                };
         };
 
         soc@01c00000 {
@@ -246,6 +418,20 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        clk_out_a_pins_a: clk_out_a@0 {
+                                allwinner,pins = "PI12";
+                                allwinner,function = "clk_out_a";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        clk_out_b_pins_a: clk_out_b@0 {
+                                allwinner,pins = "PI13";
+                                allwinner,function = "clk_out_b";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -265,11 +451,23 @@
                         reg = <0x01c20c90 0x10>;
                 };
 
+                rtc: rtc@01c20d00 {
+                        compatible = "allwinner,sun7i-a20-rtc";
+                        reg = <0x01c20d00 0x20>;
+                        interrupts = <0 24 1>;
+                };
+
                 sid: eeprom@01c23800 {
                         compatible = "allwinner,sun7i-a20-sid";
                         reg = <0x01c23800 0x200>;
                 };
 
+                rtp: rtp@01c25000 {
+                        compatible = "allwinner,sun4i-ts";
+                        reg = <0x01c25000 0x100>;
+                        interrupts = <0 29 4>;
+                };
+
                 uart0: serial@01c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23b03a7..73aecfb57ccb 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -7,11 +7,42 @@
         model = "NVIDIA Tegra114 Dalmore evaluation board";
         compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps65913@58";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x40000000>;
         };
 
-        pinmux {
+        host1x@50000000 {
+                hdmi@54280000 {
+                        status = "okay";
+
+                        vdd-supply = <&vdd_hdmi_reg>;
+                        pll-supply = <&palmas_smps3_reg>;
+
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+
+                dsi@54300000 {
+                        status = "okay";
+
+                        panel@0 {
+                                compatible = "panasonic,vvx10f004b00",
+                                             "simple-panel";
+                                reg = <0>;
+
+                                power-supply = <&avdd_lcd_reg>;
+                                backlight = <&backlight>;
+                        };
+                };
+        };
+
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -19,41 +50,41 @@
                         clk1_out_pw4 {
                                 nvidia,pins = "clk1_out_pw4";
                                 nvidia,function = "extperiph1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap1_din_pn1 {
                                 nvidia,pins = "dap1_din_pn1";
                                 nvidia,function = "i2s0";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap1_dout_pn2 {
                                 nvidia,pins = "dap1_dout_pn2",
                                                 "dap1_fs_pn0",
                                                 "dap1_sclk_pn3";
                                 nvidia,function = "i2s0";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_din_pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap2_dout_pa5 {
                                 nvidia,pins = "dap2_dout_pa5",
                                                 "dap2_fs_pa2",
                                                 "dap2_sclk_pa3";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap4_din_pp5 {
                                 nvidia,pins = "dap4_din_pp5",
@@ -61,17 +92,17 @@
                                                 "dap4_fs_pp4",
                                                 "dap4_sclk_pp7";
                                 nvidia,function = "i2s3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dvfs_pwm_px0 {
                                 nvidia,pins = "dvfs_pwm_px0",
                                                 "dvfs_clk_px2";
                                 nvidia,function = "cldvfs";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_clk_py0 {
                                 nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +115,128 @@
                                                 "ulpi_data6_po7",
                                                 "ulpi_data7_po0";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_dir_py1 {
                                 nvidia,pins = "ulpi_dir_py1",
                                                 "ulpi_nxt_py2";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi_stp_py3 {
                                 nvidia,pins = "ulpi_stp_py3";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         cam_i2c_scl_pbb1 {
                                 nvidia,pins = "cam_i2c_scl_pbb1",
                                                 "cam_i2c_sda_pbb2";
                                 nvidia,function = "i2c3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         cam_mclk_pcc0 {
                                 nvidia,pins = "cam_mclk_pcc0",
                                                 "pbb0";
                                 nvidia,function = "vi_alt3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
-                                nvidia,lock = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                         };
                         gen2_i2c_scl_pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5",
                                                 "gen2_i2c_sda_pt6";
                                 nvidia,function = "i2c2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_a16_pj7 {
                                 nvidia,pins = "gmi_a16_pj7";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_a17_pb0 {
                                 nvidia,pins = "gmi_a17_pb0",
                                                 "gmi_a18_pb1";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_a19_pk7 {
                                 nvidia,pins = "gmi_a19_pk7";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad5_pg5 {
                                 nvidia,pins = "gmi_ad5_pg5",
                                                 "gmi_cs6_n_pi3",
                                                 "gmi_wr_n_pi0";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad6_pg6 {
                                 nvidia,pins = "gmi_ad6_pg6",
                                                 "gmi_ad7_pg7";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad12_ph4 {
                                 nvidia,pins = "gmi_ad12_ph4";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad9_ph1 {
                                 nvidia,pins = "gmi_ad9_ph1";
                                 nvidia,function = "pwm1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_cs1_n_pj2 {
                                 nvidia,pins = "gmi_cs1_n_pj2",
                                                 "gmi_oe_n_pi1";
                                 nvidia,function = "soc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk2_out_pw5 {
                                 nvidia,pins = "clk2_out_pw5";
                                 nvidia,function = "extperiph2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -214,23 +245,23 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc1_wp_n_pv3 {
                                 nvidia,pins = "sdmmc1_wp_n_pv3";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -242,16 +273,16 @@
                                                 "sdmmc3_clk_lb_out_pee4",
                                                 "sdmmc3_clk_lb_in_pee5";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc4_cmd_pt7 {
                                 nvidia,pins = "sdmmc4_cmd_pt7",
@@ -264,16 +295,16 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk_32k_out_pa0 {
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "blink";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col0_pq0 {
                                 nvidia,pins = "kb_col0_pq0",
@@ -283,265 +314,265 @@
                                                 "kb_row1_pr1",
                                                 "kb_row2_pr2";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap3_din_pp1 {
                                 nvidia,pins = "dap3_din_pp1",
                                                 "dap3_sclk_pp3";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pv0 {
                                 nvidia,pins = "pv0";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_row7_pr7 {
                                 nvidia,pins = "kb_row7_pr7";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row10_ps2 {
                                 nvidia,pins = "kb_row10_ps2";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row9_ps1 {
                                 nvidia,pins = "kb_row9_ps1";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pwr_i2c_scl_pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6",
                                                 "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         sys_clk_req_pz5 {
                                 nvidia,pins = "sys_clk_req_pz5";
                                 nvidia,function = "sysclk";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         core_pwr_req {
                                 nvidia,pins = "core_pwr_req";
                                 nvidia,function = "pwron";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         cpu_pwr_req {
                                 nvidia,pins = "cpu_pwr_req";
                                 nvidia,function = "cpu";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pwr_int_n {
                                 nvidia,pins = "pwr_int_n";
                                 nvidia,function = "pmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         reset_out_n {
                                 nvidia,pins = "reset_out_n";
                                 nvidia,function = "reset_out_n";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         clk3_out_pee0 {
                                 nvidia,pins = "clk3_out_pee0";
                                 nvidia,function = "extperiph3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gen1_i2c_scl_pc4 {
                                 nvidia,pins = "gen1_i2c_scl_pc4",
                                                 "gen1_i2c_sda_pc5";
                                 nvidia,function = "i2c1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_cts_n_pj5 {
                                 nvidia,pins = "uart2_cts_n_pj5";
                                 nvidia,function = "uartb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart2_rts_n_pj6 {
                                 nvidia,pins = "uart2_rts_n_pj6";
                                 nvidia,function = "uartb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart2_rxd_pc3 {
                                 nvidia,pins = "uart2_rxd_pc3";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart2_txd_pc2 {
                                 nvidia,pins = "uart2_txd_pc2";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         uart3_cts_n_pa1 {
                                 nvidia,pins = "uart3_cts_n_pa1",
                                                 "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         uart3_rts_n_pc0 {
                                 nvidia,pins = "uart3_rts_n_pc0",
                                                 "uart3_txd_pw6";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         owr {
                                 nvidia,pins = "owr";
                                 nvidia,function = "owr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         hdmi_cec_pee3 {
                                 nvidia,pins = "hdmi_cec_pee3";
                                 nvidia,function = "cec";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
                         ddc_scl_pv4 {
                                 nvidia,pins = "ddc_scl_pv4",
                                                 "ddc_sda_pv5";
                                 nvidia,function = "i2c4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,rcv-sel = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
                         };
                         spdif_in_pk6 {
                                 nvidia,pins = "spdif_in_pk6";
                                 nvidia,function = "usb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                         };
                         usb_vbus_en0_pn4 {
                                 nvidia,pins = "usb_vbus_en0_pn4";
                                 nvidia,function = "usb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
-                                nvidia,lock = <0>;
-                                nvidia,open-drain = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x6_aud_px6 {
                                 nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "spi6";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x4_aud_px4 {
                                 nvidia,pins = "gpio_x4_aud_px4",
                                                 "gpio_x7_aud_px7";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_x5_aud_px5 {
                                 nvidia,pins = "gpio_x5_aud_px5";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_w2_aud_pw2 {
                                 nvidia,pins = "gpio_w2_aud_pw2";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_w3_aud_pw3 {
                                 nvidia,pins = "gpio_w3_aud_pw3";
                                 nvidia,function = "spi6";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x1_aud_px1 {
                                 nvidia,pins = "gpio_x1_aud_px1";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_x3_aud_px3 {
                                 nvidia,pins = "gpio_x3_aud_px3";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         dap3_fs_pp0 {
                                 nvidia,pins = "dap3_fs_pp0";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         dap3_dout_pp2 {
                                 nvidia,pins = "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pv1 {
                                 nvidia,pins = "pv1";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         pbb3 {
                                 nvidia,pins = "pbb3",
@@ -549,25 +580,25 @@
                                                 "pbb6",
                                                 "pbb7";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pcc1 {
                                 nvidia,pins = "pcc1",
                                                 "pcc2";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_ad0_pg0 {
                                 nvidia,pins = "gmi_ad0_pg0",
                                                 "gmi_ad1_pg1";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad10_ph2 {
                                 nvidia,pins = "gmi_ad10_ph2",
@@ -576,17 +607,17 @@
                                                 "gmi_ad8_ph0",
                                                 "gmi_clk_pk1";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         gmi_ad2_pg2 {
                                 nvidia,pins = "gmi_ad2_pg2",
                                                 "gmi_ad3_pg3";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_adv_n_pk0 {
                                 nvidia,pins = "gmi_adv_n_pk0",
@@ -598,39 +629,39 @@
                                                 "gmi_iordy_pi5",
                                                 "gmi_wp_n_pc7";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         gmi_cs3_n_pk4 {
                                 nvidia,pins = "gmi_cs3_n_pk4";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         clk2_req_pcc5 {
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col3_pq3 {
                                 nvidia,pins = "kb_col3_pq3",
                                                 "kb_col6_pq6",
                                                 "kb_col7_pq7";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         kb_col5_pq5 {
                                 nvidia,pins = "kb_col5_pq5";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         kb_row3_pr3 {
                                 nvidia,pins = "kb_row3_pr3",
@@ -638,77 +669,77 @@
                                                 "kb_row6_pr6",
                                                 "kb_row8_ps0";
                                 nvidia,function = "kbc";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk3_req_pee1 {
                                 nvidia,pins = "clk3_req_pee1";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pu4 {
                                 nvidia,pins = "pu4";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         pu5 {
                                 nvidia,pins = "pu5",
                                                 "pu6";
                                 nvidia,function = "displayb";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         hdmi_int_pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
-                                nvidia,enable-input = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         clk1_req_pee2 {
                                 nvidia,pins = "clk1_req_pee2",
                                                 "usb_vbus_en1_pn5";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
-                                nvidia,enable-input = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <36>;
                                 nvidia,pull-up-strength = <20>;
-                                nvidia,slew-rate-rising = <2>;
-                                nvidia,slew-rate-falling = <2>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
                         };
                         drive_sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <22>;
                                 nvidia,pull-up-strength = <36>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                         };
                         drive_gma {
                                 nvidia,pins = "drive_gma";
-                                nvidia,high-speed-mode = <1>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <2>;
                                 nvidia,pull-up-strength = <1>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                                 nvidia,drive-type = <1>;
                         };
                 };
@@ -718,11 +749,15 @@
                 status = "okay";
         };
 
+        pwm@7000a000 {
+                status = "okay";
+        };
+
         i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
 
-                battery: smart-battery {
+                battery: smart-battery@b {
                         compatible = "ti,bq20z45", "sbs,sbs-battery";
                         reg = <0xb>;
                         battery-name = "battery";
@@ -731,7 +766,7 @@
                         power-supplies = <&charger>;
                 };
 
-                rt5640: rt5640 {
+                rt5640: rt5640@1c {
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
@@ -749,11 +784,15 @@
                 };
         };
 
+        hdmi_ddc: i2c@7000c700 {
+                status = "okay";
+        };
+
         i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
 
-                tps51632 {
+                tps51632@43 {
                         compatible = "ti,tps51632";
                         reg = <0x43>;
                         regulator-name = "vdd-cpu";
@@ -763,7 +802,7 @@
                         regulator-always-on;
                 };
 
-                tps65090 {
+                tps65090@48 {
                         compatible = "ti,tps65090";
                         reg = <0x48>;
                         interrupt-parent = <&gpio>;
@@ -806,7 +845,7 @@
                                         regulator-boot-on;
                                 };
 
-                                fet1 {
+                                vdd_bl_reg: fet1 {
                                         regulator-name = "vdd-lcd-bl";
                                 };
 
@@ -814,7 +853,7 @@
                                         regulator-name = "vdd-modem-3v3";
                                 };
 
-                                fet4 {
+                                avdd_lcd_reg: fet4 {
                                         regulator-name = "avdd-lcd";
                                 };
 
@@ -846,7 +885,7 @@
                         };
                 };
 
-                palmas: tps65913 {
+                palmas: tps65913@58 {
                         compatible = "ti,palmas";
                         reg = <0x58>;
                         interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
@@ -1046,7 +1085,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <500>;
@@ -1057,7 +1096,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        ahub {
+        ahub@70080000 {
                 i2s@70080400 {
                         status = "okay";
                 };
@@ -1084,12 +1123,23 @@
                 vbus-supply = <&usb3_vbus_reg>;
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 1 1000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -1150,16 +1200,6 @@
                         gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
                 };
 
-                lcd_bl_en_reg: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "lcd_bl_en";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
-                };
-
                 usb1_vbus_reg: regulator@3 {
                         compatible = "regulator-fixed";
                         reg = <3>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 8d42787c8ff1..389e987ec281 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra114-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -15,7 +16,113 @@
                 serial3 = &uartd;
         };
 
-        gic: interrupt-controller {
+        host1x@50000000 {
+                compatible = "nvidia,tegra114-host1x", "simple-bus";
+                reg = <0x50000000 0x00028000>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
+                resets = <&tegra_car 28>;
+                reset-names = "host1x";
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                ranges = <0x54000000 0x54000000 0x01000000>;
+
+                gr2d@54140000 {
+                        compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
+                        reg = <0x54140000 0x00040000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_GR2D>;
+                        resets = <&tegra_car 21>;
+                        reset-names = "2d";
+                };
+
+                gr3d@54180000 {
+                        compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
+                        reg = <0x54180000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_GR3D>;
+                        resets = <&tegra_car 24>;
+                        reset-names = "3d";
+                };
+
+                dc@54200000 {
+                        compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+                        reg = <0x54200000 0x00040000>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_DISP1>,
+                                 <&tegra_car TEGRA114_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 27>;
+                        reset-names = "dc";
+
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+
+                dc@54240000 {
+                        compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+                        reg = <0x54240000 0x00040000>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_DISP2>,
+                                 <&tegra_car TEGRA114_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 26>;
+                        reset-names = "dc";
+
+                        rgb {
+                                status = "disabled";
+                        };
+                };
+
+                hdmi@54280000 {
+                        compatible = "nvidia,tegra114-hdmi";
+                        reg = <0x54280000 0x00040000>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA114_CLK_HDMI>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+                        clock-names = "hdmi", "parent";
+                        resets = <&tegra_car 51>;
+                        reset-names = "hdmi";
+                        status = "disabled";
+                };
+
+                dsi@54300000 {
+                        compatible = "nvidia,tegra114-dsi";
+                        reg = <0x54300000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_DSIA>,
+                                 <&tegra_car TEGRA114_CLK_DSIALP>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+                        clock-names = "dsi", "lp", "parent";
+                        resets = <&tegra_car 48>;
+                        reset-names = "dsi";
+                        nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+                        status = "disabled";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                dsi@54400000 {
+                        compatible = "nvidia,tegra114-dsi";
+                        reg = <0x54400000 0x00040000>;
+                        clocks = <&tegra_car TEGRA114_CLK_DSIB>,
+                                 <&tegra_car TEGRA114_CLK_DSIBLP>,
+                                 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
+                        clock-names = "dsi", "lp", "parent";
+                        resets = <&tegra_car 82>;
+                        reset-names = "dsi";
+                        nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+                        status = "disabled";
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        gic: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
@@ -39,13 +146,14 @@
                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
+                #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra114-apbdma";
                 reg = <0x6000a000 0x1400>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -81,14 +189,17 @@
                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+                resets = <&tegra_car 34>;
+                reset-names = "dma";
+                #dma-cells = <1>;
         };
 
-        ahb: ahb {
+        ahb: ahb@6000c004 {
                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
                 reg = <0x6000c004 0x14c>;
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -105,7 +216,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra114-pinmux";
                 reg = <0x70000868 0x148         /* Pad control registers */
                        0x70003000 0x40c>;       /* Mux registers */
@@ -124,9 +235,12 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 8>;
-                status = "disabled";
                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+                resets = <&tegra_car 6>;
+                reset-names = "serial";
+                dmas = <&apbdma 8>, <&apbdma 8>;
+                dma-names = "rx", "tx";
+                status = "disabled";
         };
 
         uartb: serial@70006040 {
@@ -134,9 +248,12 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 9>;
-                status = "disabled";
                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+                resets = <&tegra_car 7>;
+                reset-names = "serial";
+                dmas = <&apbdma 9>, <&apbdma 9>;
+                dma-names = "rx", "tx";
+                status = "disabled";
         };
 
         uartc: serial@70006200 {
@@ -144,9 +261,12 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 10>;
-                status = "disabled";
                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+                resets = <&tegra_car 55>;
+                reset-names = "serial";
+                dmas = <&apbdma 10>, <&apbdma 10>;
+                dma-names = "rx", "tx";
+                status = "disabled";
         };
 
         uartd: serial@70006300 {
@@ -154,16 +274,21 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 19>;
-                status = "disabled";
                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+                resets = <&tegra_car 65>;
+                reset-names = "serial";
+                dmas = <&apbdma 19>, <&apbdma 19>;
+                dma-names = "rx", "tx";
+                status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
+                resets = <&tegra_car 17>;
+                reset-names = "pwm";
                 status = "disabled";
         };
 
@@ -175,6 +300,10 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
                 clock-names = "div-clk";
+                resets = <&tegra_car 12>;
+                reset-names = "i2c";
+                dmas = <&apbdma 21>, <&apbdma 21>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -186,6 +315,10 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
                 clock-names = "div-clk";
+                resets = <&tegra_car 54>;
+                reset-names = "i2c";
+                dmas = <&apbdma 22>, <&apbdma 22>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -197,6 +330,10 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
                 clock-names = "div-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
+                dmas = <&apbdma 23>, <&apbdma 23>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -208,6 +345,10 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
                 clock-names = "div-clk";
+                resets = <&tegra_car 103>;
+                reset-names = "i2c";
+                dmas = <&apbdma 26>, <&apbdma 26>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -219,6 +360,10 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
                 clock-names = "div-clk";
+                resets = <&tegra_car 47>;
+                reset-names = "i2c";
+                dmas = <&apbdma 24>, <&apbdma 24>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -226,11 +371,14 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d400 0x200>;
                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
                 clock-names = "spi";
+                resets = <&tegra_car 41>;
+                reset-names = "spi";
+                dmas = <&apbdma 15>, <&apbdma 15>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -238,11 +386,14 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d600 0x200>;
                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
                 clock-names = "spi";
+                resets = <&tegra_car 44>;
+                reset-names = "spi";
+                dmas = <&apbdma 16>, <&apbdma 16>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -250,11 +401,14 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d800 0x200>;
                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
                 clock-names = "spi";
+                resets = <&tegra_car 46>;
+                reset-names = "spi";
+                dmas = <&apbdma 17>, <&apbdma 17>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -262,11 +416,14 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000da00 0x200>;
                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
                 clock-names = "spi";
+                resets = <&tegra_car 68>;
+                reset-names = "spi";
+                dmas = <&apbdma 18>, <&apbdma 18>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -274,11 +431,14 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000dc00 0x200>;
                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
                 clock-names = "spi";
+                resets = <&tegra_car 104>;
+                reset-names = "spi";
+                dmas = <&apbdma 27>, <&apbdma 27>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -286,37 +446,42 @@
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000de00 0x200>;
                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
                 clock-names = "spi";
+                resets = <&tegra_car 105>;
+                reset-names = "spi";
+                dmas = <&apbdma 28>, <&apbdma 28>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra114-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
+                resets = <&tegra_car 36>;
+                reset-names = "kbc";
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
-        iommu {
+        iommu@70019010 {
                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
                 reg = <0x70019010 0x02c
                        0x700191f0 0x010
@@ -327,32 +492,45 @@
                 nvidia,ahb = <&ahb>;
         };
 
-        ahub {
+        ahub@70080000 {
                 compatible = "nvidia,tegra114-ahub";
                 reg = <0x70080000 0x200>,
                       <0x70080200 0x100>,
                       <0x70081000 0x200>;
                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
-                        <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
-                        <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
-                        <&apbdma 29>;
                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
-                         <&tegra_car TEGRA114_CLK_APBIF>,
-                         <&tegra_car TEGRA114_CLK_I2S0>,
-                         <&tegra_car TEGRA114_CLK_I2S1>,
-                         <&tegra_car TEGRA114_CLK_I2S2>,
-                         <&tegra_car TEGRA114_CLK_I2S3>,
-                         <&tegra_car TEGRA114_CLK_I2S4>,
-                         <&tegra_car TEGRA114_CLK_DAM0>,
-                         <&tegra_car TEGRA114_CLK_DAM1>,
-                         <&tegra_car TEGRA114_CLK_DAM2>,
-                         <&tegra_car TEGRA114_CLK_SPDIF_IN>,
-                         <&tegra_car TEGRA114_CLK_AMX>,
-                         <&tegra_car TEGRA114_CLK_ADX>;
-                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                         <&tegra_car TEGRA114_CLK_APBIF>;
+                clock-names = "d_audio", "apbif";
+                resets = <&tegra_car 106>, /* d_audio */
+                         <&tegra_car 107>, /* apbif */
+                         <&tegra_car 30>,  /* i2s0 */
+                         <&tegra_car 11>,  /* i2s1 */
+                         <&tegra_car 18>,  /* i2s2 */
+                         <&tegra_car 101>, /* i2s3 */
+                         <&tegra_car 102>, /* i2s4 */
+                         <&tegra_car 108>, /* dam0 */
+                         <&tegra_car 109>, /* dam1 */
+                         <&tegra_car 110>, /* dam2 */
+                         <&tegra_car 10>,  /* spdif */
+                         <&tegra_car 153>, /* amx */
+                         <&tegra_car 154>; /* adx */
+                reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
-                              "spdif_in", "amx", "adx";
+                              "spdif", "amx", "adx";
+                dmas = <&apbdma 1>, <&apbdma 1>,
+                       <&apbdma 2>, <&apbdma 2>,
+                       <&apbdma 3>, <&apbdma 3>,
+                       <&apbdma 4>, <&apbdma 4>,
+                       <&apbdma 6>, <&apbdma 6>,
+                       <&apbdma 7>, <&apbdma 7>,
+                       <&apbdma 12>, <&apbdma 12>,
+                       <&apbdma 13>, <&apbdma 13>,
+                       <&apbdma 14>, <&apbdma 14>,
+                       <&apbdma 29>, <&apbdma 29>;
+                dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+                            "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+                            "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+                            "rx9", "tx9";
                 ranges;
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -362,6 +540,8 @@
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+                        resets = <&tegra_car 30>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -370,6 +550,8 @@
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+                        resets = <&tegra_car 11>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -378,6 +560,8 @@
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+                        resets = <&tegra_car 18>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -386,6 +570,8 @@
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+                        resets = <&tegra_car 101>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -394,15 +580,26 @@
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+                        resets = <&tegra_car 102>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
         };
 
+        mipi: mipi@700e3000 {
+                compatible = "nvidia,tegra114-mipi";
+                reg = <0x700e3000 0x100>;
+                clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
+                #nvidia,mipi-calibrate-cells = <1>;
+        };
+
         sdhci@78000000 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000000 0x200>;
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+                resets = <&tegra_car 14>;
+                reset-names = "sdhci";
                 status = "disable";
         };
 
@@ -411,6 +608,8 @@
                 reg = <0x78000200 0x200>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+                resets = <&tegra_car 9>;
+                reset-names = "sdhci";
                 status = "disable";
         };
 
@@ -419,6 +618,8 @@
                 reg = <0x78000400 0x200>;
                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+                resets = <&tegra_car 69>;
+                reset-names = "sdhci";
                 status = "disable";
         };
 
@@ -427,6 +628,8 @@
                 reg = <0x78000600 0x200>;
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+                resets = <&tegra_car 15>;
+                reset-names = "sdhci";
                 status = "disable";
         };
 
@@ -436,6 +639,8 @@
                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
+                resets = <&tegra_car 22>;
+                reset-names = "usb";
                 nvidia,phy = <&phy1>;
                 status = "disabled";
         };
@@ -467,6 +672,8 @@
                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
+                resets = <&tegra_car 59>;
+                reset-names = "usb";
                 nvidia,phy = <&phy3>;
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 431d67a2b413..c6dcef513e5d 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1,19 +1,917 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra124.dtsi"
 
 / {
         model = "NVIDIA Tegra124 Venice2";
         compatible = "nvidia,venice2", "nvidia,tegra124";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/as3722@40";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x80000000>;
         };
 
+        pinmux: pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinmux_default>;
+
+                pinmux_default: common {
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2",
+                                              "dap1_fs_pn0",
+                                              "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5",
+                                              "dap2_fs_pa2",
+                                              "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0",
+                                              "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0",
+                                              "ulpi_nxt_py2",
+                                              "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                              "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                              "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4",
+                                              "pg5",
+                                              "pg6",
+                                              "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0",
+                                              "kb_row15_ps7",
+                                              "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0",
+                                              "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                              "sdmmc3_dat0_pb7",
+                                              "sdmmc3_dat1_pb6",
+                                              "sdmmc3_dat2_pb5",
+                                              "sdmmc3_dat3_pb4",
+                                              "sdmmc3_clk_lb_out_pee4",
+                                              "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7",
+                                              "sdmmc4_dat0_paa0",
+                                              "sdmmc4_dat1_paa1",
+                                              "sdmmc4_dat2_paa2",
+                                              "sdmmc4_dat3_paa3",
+                                              "sdmmc4_dat4_paa4",
+                                              "sdmmc4_dat5_paa5",
+                                              "sdmmc4_dat6_paa6",
+                                              "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                              "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "i2s3";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6",
+                                              "dap4_fs_pp4",
+                                              "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5",
+                                              "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1",
+                                              "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0",
+                                              "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7",
+                                              "pk7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0",
+                                              "pb1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "displaya_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <32>;
+                                nvidia,pull-up-strength = <42>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <20>;
+                                nvidia,pull-up-strength = <36>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_gma {
+                                nvidia,pins = "drive_gma";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <1>;
+                                nvidia,pull-up-strength = <2>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,drive-type = <1>;
+                        };
+                        als_irq_l {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        codec_irq_l {
+                                nvidia,pins = "ph4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd_bl_en {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        touch_irq_l {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        tpm_davint_l {
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_irq_l {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ts_reset_l {
+                                nvidia,pins = "pk4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ts_shdn_l {
+                                nvidia,pins = "pk1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_ap {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lid_open {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        en_vdd_sd {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ac_ok {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sensor_irq_l {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        wifi_en {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        wifi_rst_l {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "dap";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hp_det_l {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "spi3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                };
+        };
+
         serial@70006000 {
                 status = "okay";
         };
 
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
+
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                acodec: audio-codec@10 {
+                        compatible = "maxim,max98090";
+                        reg = <0x10>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                as3722: as3722@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+
+                                gpio1_2_4_7 {
+                                        pins = "gpio1", "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio3_6 {
+                                        pins = "gpio3", "gpio6";
+                                        bias-high-impedance;
+                                };
+
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "clk32k-out";
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd3-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd4-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd5-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo0-supply = <&as3722_sd2>;
+                                vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo2-5-7-supply = <&as3722_sd5>;
+                                vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo11-supply = <&vdd_ac_bat_reg>;
+
+                                sd0 {
+                                        regulator-name = "vdd-cpu";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "vdd-core";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <2500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <1>;
+                                };
+
+                                as3722_sd2: sd2 {
+                                        regulator-name = "vddio-ddr";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name = "vddio-ddr-2phase";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd4 {
+                                        regulator-name = "avdd-pex-sata";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                as3722_sd5: sd5 {
+                                        regulator-name = "vddio-sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                sd6 {
+                                        regulator-name = "vdd-gpu";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo0 {
+                                        regulator-name = "avdd_pll";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,external-control = <1>;
+                                };
+
+                                ldo1 {
+                                        regulator-name = "run-cam-1.8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "gen-avdd,vddio-hsic";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "vdd-rtc";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                ldo4 {
+                                        regulator-name = "vdd-cam";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo5 {
+                                        regulator-name = "vdd-cam-front";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo6 {
+                                        regulator-name = "vddio-sdmmc3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo7 {
+                                        regulator-name = "vdd-cam-rear";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo9 {
+                                        regulator-name = "vdd-touch";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "vdd-cam-af";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "vpp-fuse";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+
+        spi@7000d400 {
+                status = "okay";
+
+                cros-ec@0 {
+                        compatible = "google,cros-ec-spi";
+                        spi-max-frequency = <4000000>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+                        reg = <0>;
+
+                        google,cros-ec-spi-msg-delay = <2000>;
+
+                        cros-ec-keyb {
+                                compatible = "google,cros-ec-keyb";
+                                keypad,num-rows = <8>;
+                                keypad,num-columns = <13>;
+                                google,needs-ghost-filter;
+
+                                linux,keymap = <
+                                        MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
+                                        MATRIX_KEY(0x00, 0x02, KEY_F1)
+                                        MATRIX_KEY(0x00, 0x03, KEY_B)
+                                        MATRIX_KEY(0x00, 0x04, KEY_F10)
+                                        MATRIX_KEY(0x00, 0x06, KEY_N)
+                                        MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
+                                        MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
+
+                                        MATRIX_KEY(0x01, 0x01, KEY_ESC)
+                                        MATRIX_KEY(0x01, 0x02, KEY_F4)
+                                        MATRIX_KEY(0x01, 0x03, KEY_G)
+                                        MATRIX_KEY(0x01, 0x04, KEY_F7)
+                                        MATRIX_KEY(0x01, 0x06, KEY_H)
+                                        MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
+                                        MATRIX_KEY(0x01, 0x09, KEY_F9)
+                                        MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+
+                                        MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
+                                        MATRIX_KEY(0x02, 0x01, KEY_TAB)
+                                        MATRIX_KEY(0x02, 0x02, KEY_F3)
+                                        MATRIX_KEY(0x02, 0x03, KEY_T)
+                                        MATRIX_KEY(0x02, 0x04, KEY_F6)
+                                        MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
+                                        MATRIX_KEY(0x02, 0x06, KEY_Y)
+                                        MATRIX_KEY(0x02, 0x07, KEY_102ND)
+                                        MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
+                                        MATRIX_KEY(0x02, 0x09, KEY_F8)
+
+                                        MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
+                                        MATRIX_KEY(0x03, 0x02, KEY_F2)
+                                        MATRIX_KEY(0x03, 0x03, KEY_5)
+                                        MATRIX_KEY(0x03, 0x04, KEY_F5)
+                                        MATRIX_KEY(0x03, 0x06, KEY_6)
+                                        MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+                                        MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+
+                                        MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
+                                        MATRIX_KEY(0x04, 0x01, KEY_A)
+                                        MATRIX_KEY(0x04, 0x02, KEY_D)
+                                        MATRIX_KEY(0x04, 0x03, KEY_F)
+                                        MATRIX_KEY(0x04, 0x04, KEY_S)
+                                        MATRIX_KEY(0x04, 0x05, KEY_K)
+                                        MATRIX_KEY(0x04, 0x06, KEY_J)
+                                        MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
+                                        MATRIX_KEY(0x04, 0x09, KEY_L)
+                                        MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+                                        MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
+
+                                        MATRIX_KEY(0x05, 0x01, KEY_Z)
+                                        MATRIX_KEY(0x05, 0x02, KEY_C)
+                                        MATRIX_KEY(0x05, 0x03, KEY_V)
+                                        MATRIX_KEY(0x05, 0x04, KEY_X)
+                                        MATRIX_KEY(0x05, 0x05, KEY_COMMA)
+                                        MATRIX_KEY(0x05, 0x06, KEY_M)
+                                        MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
+                                        MATRIX_KEY(0x05, 0x08, KEY_SLASH)
+                                        MATRIX_KEY(0x05, 0x09, KEY_DOT)
+                                        MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
+
+                                        MATRIX_KEY(0x06, 0x01, KEY_1)
+                                        MATRIX_KEY(0x06, 0x02, KEY_3)
+                                        MATRIX_KEY(0x06, 0x03, KEY_4)
+                                        MATRIX_KEY(0x06, 0x04, KEY_2)
+                                        MATRIX_KEY(0x06, 0x05, KEY_8)
+                                        MATRIX_KEY(0x06, 0x06, KEY_7)
+                                        MATRIX_KEY(0x06, 0x08, KEY_0)
+                                        MATRIX_KEY(0x06, 0x09, KEY_9)
+                                        MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
+                                        MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
+                                        MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
+
+                                        MATRIX_KEY(0x07, 0x01, KEY_Q)
+                                        MATRIX_KEY(0x07, 0x02, KEY_E)
+                                        MATRIX_KEY(0x07, 0x03, KEY_R)
+                                        MATRIX_KEY(0x07, 0x04, KEY_W)
+                                        MATRIX_KEY(0x07, 0x05, KEY_I)
+                                        MATRIX_KEY(0x07, 0x06, KEY_U)
+                                        MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
+                                        MATRIX_KEY(0x07, 0x08, KEY_P)
+                                        MATRIX_KEY(0x07, 0x09, KEY_O)
+                                        MATRIX_KEY(0x07, 0x0b, KEY_UP)
+                                        MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
+                                >;
+                        };
+                };
+        };
+
         pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -24,4 +922,170 @@
                 nvidia,core-power-req-active-high;
                 nvidia,sys-clock-req-active-high;
         };
+
+        sdhci@700b0400 {
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                status = "okay";
+                bus-width = <4>;
+        };
+
+        sdhci@700b0600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        ahub@70300000 {
+                i2s@70301100 {
+                        status = "okay";
+                };
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_ac_bat_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_ac_bat";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                vdd_3v3_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_3v3_modem_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd-modem-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_hdmi_5v0_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd-hdmi-5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                };
+
+                vdd_bl_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd-bl";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
+                };
+
+                vdd_ts_sw_5v0: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_ts_sw";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
+                };
+
+                usb1_vbus_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        gpio-open-drain;
+                };
+
+                usb3_vbus_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        gpio-open-drain;
+                };
+
+                panel_3v3_reg: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "panel_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-max98090-venice2",
+                             "nvidia,tegra-audio-max98090";
+                nvidia,model = "NVIDIA Tegra Venice2";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPR",
+                        "Headphones", "HPL",
+                        "Speakers", "SPKR",
+                        "Speakers", "SPKL",
+                        "Mic Jack", "MICBIAS",
+                        "IN34", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&acodec>;
+
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..ec0698a8354a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,4 +1,6 @@
+#include <dt-bindings/clock/tegra124-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -28,6 +30,14 @@
                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_TIMER>;
+        };
+
+        tegra_car: clock@60006000 {
+                compatible = "nvidia,tegra124-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
         };
 
         gpio: gpio@6000d000 {
@@ -47,6 +57,53 @@
                 interrupt-controller;
         };
 
+        apbdma: dma@60020000 {
+                compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+                reg = <0x60020000 0x1400>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
+                resets = <&tegra_car 34>;
+                reset-names = "dma";
+                #dma-cells = <1>;
+        };
+
+        pinmux: pinmux@70000868 {
+                compatible = "nvidia,tegra124-pinmux";
+                reg = <0x70000868 0x164>,       /* Pad control registers */
+                      <0x70003000 0x434>;       /* Mux registers */
+        };
+
         /*
          * There are two serial driver i.e. 8250 based simple serial
          * driver and APB DMA based serial driver for higher baudrate
@@ -60,6 +117,11 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTA>;
+                resets = <&tegra_car 6>;
+                reset-names = "serial";
+                dmas = <&apbdma 8>, <&apbdma 8>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -68,6 +130,11 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTB>;
+                resets = <&tegra_car 7>;
+                reset-names = "serial";
+                dmas = <&apbdma 9>, <&apbdma 9>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -76,6 +143,11 @@
                 reg = <0x70006200 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTC>;
+                resets = <&tegra_car 55>;
+                reset-names = "serial";
+                dmas = <&apbdma 10>, <&apbdma 10>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -84,6 +156,11 @@
                 reg = <0x70006300 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTD>;
+                resets = <&tegra_car 65>;
+                reset-names = "serial";
+                dmas = <&apbdma 19>, <&apbdma 19>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -92,6 +169,201 @@
                 reg = <0x70006400 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_UARTE>;
+                resets = <&tegra_car 66>;
+                reset-names = "serial";
+                dmas = <&apbdma 20>, <&apbdma 20>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        pwm@7000a000 {
+                compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
+                reg = <0x7000a000 0x100>;
+                #pwm-cells = <2>;
+                clocks = <&tegra_car TEGRA124_CLK_PWM>;
+                resets = <&tegra_car 17>;
+                reset-names = "pwm";
+                status = "disabled";
+        };
+
+        i2c@7000c000 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c000 0x100>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C1>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 12>;
+                reset-names = "i2c";
+                dmas = <&apbdma 21>, <&apbdma 21>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c400 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c400 0x100>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C2>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 54>;
+                reset-names = "i2c";
+                dmas = <&apbdma 22>, <&apbdma 22>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c500 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c500 0x100>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C3>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
+                dmas = <&apbdma 23>, <&apbdma 23>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000c700 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000c700 0x100>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C4>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 103>;
+                reset-names = "i2c";
+                dmas = <&apbdma 26>, <&apbdma 26>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000d000 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000d000 0x100>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C5>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 47>;
+                reset-names = "i2c";
+                dmas = <&apbdma 24>, <&apbdma 24>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        i2c@7000d100 {
+                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+                reg = <0x7000d100 0x100>;
+                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_I2C6>;
+                clock-names = "div-clk";
+                resets = <&tegra_car 166>;
+                reset-names = "i2c";
+                dmas = <&apbdma 30>, <&apbdma 30>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d400 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d400 0x200>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC1>;
+                clock-names = "spi";
+                resets = <&tegra_car 41>;
+                reset-names = "spi";
+                dmas = <&apbdma 15>, <&apbdma 15>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d600 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d600 0x200>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC2>;
+                clock-names = "spi";
+                resets = <&tegra_car 44>;
+                reset-names = "spi";
+                dmas = <&apbdma 16>, <&apbdma 16>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000d800 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000d800 0x200>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC3>;
+                clock-names = "spi";
+                resets = <&tegra_car 46>;
+                reset-names = "spi";
+                dmas = <&apbdma 17>, <&apbdma 17>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000da00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000da00 0x200>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC4>;
+                clock-names = "spi";
+                resets = <&tegra_car 68>;
+                reset-names = "spi";
+                dmas = <&apbdma 18>, <&apbdma 18>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000dc00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000dc00 0x200>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC5>;
+                clock-names = "spi";
+                resets = <&tegra_car 104>;
+                reset-names = "spi";
+                dmas = <&apbdma 27>, <&apbdma 27>;
+                dma-names = "rx", "tx";
+                status = "disabled";
+        };
+
+        spi@7000de00 {
+                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+                reg = <0x7000de00 0x200>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&tegra_car TEGRA124_CLK_SBC6>;
+                clock-names = "spi";
+                resets = <&tegra_car 105>;
+                reset-names = "spi";
+                dmas = <&apbdma 28>, <&apbdma 28>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -99,11 +371,157 @@
                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_RTC>;
         };
 
         pmc@7000e400 {
                 compatible = "nvidia,tegra124-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
+        };
+
+        sdhci@700b0000 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0000 0x200>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
+                resets = <&tegra_car 14>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0200 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0200 0x200>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
+                resets = <&tegra_car 9>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0400 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0400 0x200>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
+                resets = <&tegra_car 69>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        sdhci@700b0600 {
+                compatible = "nvidia,tegra124-sdhci";
+                reg = <0x700b0600 0x200>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
+                resets = <&tegra_car 15>;
+                reset-names = "sdhci";
+                status = "disable";
+        };
+
+        ahub@70300000 {
+                compatible = "nvidia,tegra124-ahub";
+                reg = <0x70300000 0x200>,
+                      <0x70300800 0x800>,
+                      <0x70300200 0x600>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA124_CLK_APBIF>;
+                clock-names = "d_audio", "apbif";
+                resets = <&tegra_car 106>, /* d_audio */
+                         <&tegra_car 107>, /* apbif */
+                         <&tegra_car 30>,  /* i2s0 */
+                         <&tegra_car 11>,  /* i2s1 */
+                         <&tegra_car 18>,  /* i2s2 */
+                         <&tegra_car 101>, /* i2s3 */
+                         <&tegra_car 102>, /* i2s4 */
+                         <&tegra_car 108>, /* dam0 */
+                         <&tegra_car 109>, /* dam1 */
+                         <&tegra_car 110>, /* dam2 */
+                         <&tegra_car 10>,  /* spdif */
+                         <&tegra_car 153>, /* amx */
+                         <&tegra_car 185>, /* amx1 */
+                         <&tegra_car 154>, /* adx */
+                         <&tegra_car 180>, /* adx1 */
+                         <&tegra_car 186>, /* afc0 */
+                         <&tegra_car 187>, /* afc1 */
+                         <&tegra_car 188>, /* afc2 */
+                         <&tegra_car 189>, /* afc3 */
+                         <&tegra_car 190>, /* afc4 */
+                         <&tegra_car 191>; /* afc5 */
+                reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif", "amx", "amx1", "adx", "adx1",
+                              "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
+                dmas = <&apbdma 1>, <&apbdma 1>,
+                       <&apbdma 2>, <&apbdma 2>,
+                       <&apbdma 3>, <&apbdma 3>,
+                       <&apbdma 4>, <&apbdma 4>,
+                       <&apbdma 6>, <&apbdma 6>,
+                       <&apbdma 7>, <&apbdma 7>,
+                       <&apbdma 12>, <&apbdma 12>,
+                       <&apbdma 13>, <&apbdma 13>,
+                       <&apbdma 14>, <&apbdma 14>,
+                       <&apbdma 29>, <&apbdma 29>;
+                dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+                            "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
+                            "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
+                            "rx9", "tx9";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                tegra_i2s0: i2s@70301000 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301000 0x100>;
+                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S0>;
+                        resets = <&tegra_car 30>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s1: i2s@70301100 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301100 0x100>;
+                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S1>;
+                        resets = <&tegra_car 11>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s2: i2s@70301200 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301200 0x100>;
+                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S2>;
+                        resets = <&tegra_car 18>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s3: i2s@70301300 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301300 0x100>;
+                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S3>;
+                        resets = <&tegra_car 101>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
+
+                tegra_i2s4: i2s@70301400 {
+                        compatible = "nvidia,tegra124-i2s";
+                        reg = <0x70301400 0x100>;
+                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car TEGRA124_CLK_I2S4>;
+                        resets = <&tegra_car 102>;
+                        reset-names = "i2s";
+                        status = "disabled";
+                };
         };
 
         cpus {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index d5c9bca01232..8e0066ad9628 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -4,12 +4,17 @@
         model = "Toradex Colibri T20 512MB";
         compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         vdd-supply = <&hdmi_vdd_reg>;
                         pll-supply = <&hdmi_pll_reg>;
 
@@ -19,7 +24,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -27,20 +32,20 @@
                         audio_refclk {
                                 nvidia,pins = "cdev1";
                                 nvidia,function = "plla_out";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         crt {
                                 nvidia,pins = "crtp";
                                 nvidia,function = "crt";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         dap3 {
                                 nvidia,pins = "dap3";
                                 nvidia,function = "dap3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         displaya {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
@@ -50,155 +55,163 @@
                                         "lhs", "lpw0", "lpw2", "lsc0",
                                         "lsc1", "lsck", "lsda", "lspi", "lvs";
                                 nvidia,function = "displaya";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         gpio_dte {
                                 nvidia,pins = "dte";
                                 nvidia,function = "rsvd1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_gmi {
                                 nvidia,pins = "ata", "atc", "atd", "ate",
                                         "dap1", "dap2", "dap4", "gpu", "irrx",
                                         "irtx", "spia", "spib", "spic";
                                 nvidia,function = "gmi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_pta {
                                 nvidia,pins = "pta";
                                 nvidia,function = "rsvd4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         gpio_uac {
                                 nvidia,pins = "uac";
                                 nvidia,function = "rsvd2";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         hdint {
                                 nvidia,pins = "hdint";
                                 nvidia,function = "hdmi";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2c1 {
                                 nvidia,pins = "rm";
                                 nvidia,function = "i2c1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2c3 {
                                 nvidia,pins = "dtf";
                                 nvidia,function = "i2c3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2cddc {
                                 nvidia,pins = "ddc";
                                 nvidia,function = "i2c2";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         i2cp {
                                 nvidia,pins = "i2cp";
                                 nvidia,function = "i2cp";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         irda {
                                 nvidia,pins = "uad";
                                 nvidia,function = "irda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         nand {
                                 nvidia,pins = "kbca", "kbcc", "kbcd",
                                         "kbce", "kbcf";
                                 nvidia,function = "nand";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         owc {
                                 nvidia,pins = "owc";
                                 nvidia,function = "owr";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         pmc {
                                 nvidia,pins = "pmc";
                                 nvidia,function = "pwr_on";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         pwm {
                                 nvidia,pins = "sdb", "sdc", "sdd";
                                 nvidia,function = "pwm";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         sdio4 {
                                 nvidia,pins = "atb", "gma", "gme";
                                 nvidia,function = "sdio4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         spi1 {
                                 nvidia,pins = "spid", "spie", "spif";
                                 nvidia,function = "spi1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         spi4 {
                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
                                 nvidia,function = "spi4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         uarta {
                                 nvidia,pins = "sdio1";
                                 nvidia,function = "uarta";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         uartd {
                                 nvidia,pins = "gmc";
                                 nvidia,function = "uartd";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         ulpi {
                                 nvidia,pins = "uaa", "uab", "uda";
                                 nvidia,function = "ulpi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         ulpi_refclk {
                                 nvidia,pins = "cdev2";
                                 nvidia,function = "pllp_out4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         usb_gpio {
                                 nvidia,pins = "spig", "spih";
                                 nvidia,function = "spi2_alt";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         vi {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
                                 nvidia,function = "vi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         vi_sc {
                                 nvidia,pins = "csus";
                                 nvidia,function = "vi_sensor_clk";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                 };
         };
 
+        ac97: ac97@70002000 {
+                status = "okay";
+                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+                        GPIO_ACTIVE_HIGH>;
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
         };
@@ -225,15 +238,15 @@
                         #gpio-cells = <2>;
                         gpio-controller;
 
-                        sys-supply = <&vdd_5v0_reg>;
+                        sys-supply = <&vdd_3v3_reg>;
                         vin-sm0-supply = <&sys_reg>;
                         vin-sm1-supply = <&sys_reg>;
                         vin-sm2-supply = <&sys_reg>;
                         vinldo01-supply = <&sm2_reg>;
-                        vinldo23-supply = <&sm2_reg>;
-                        vinldo4-supply = <&sm2_reg>;
-                        vinldo678-supply = <&sm2_reg>;
-                        vinldo9-supply = <&sm2_reg>;
+                        vinldo23-supply = <&vdd_3v3_reg>;
+                        vinldo4-supply = <&vdd_3v3_reg>;
+                        vinldo678-supply = <&vdd_3v3_reg>;
+                        vinldo9-supply = <&vdd_3v3_reg>;
 
                         regulators {
                                 #address-cells = <1>;
@@ -250,8 +263,8 @@
                                         reg = <1>;
                                         regulator-compatible = "sm0";
                                         regulator-name = "vdd_sm0,vdd_core";
-                                        regulator-min-microvolt = <1275000>;
-                                        regulator-max-microvolt = <1275000>;
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
                                 };
 
@@ -259,8 +272,8 @@
                                         reg = <2>;
                                         regulator-compatible = "sm1";
                                         regulator-name = "vdd_sm1,vdd_cpu";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
                                         regulator-always-on;
                                 };
 
@@ -268,8 +281,8 @@
                                         reg = <3>;
                                         regulator-compatible = "sm2";
                                         regulator-name = "vdd_sm2,vin_ldo*";
-                                        regulator-min-microvolt = <3700000>;
-                                        regulator-max-microvolt = <3700000>;
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
                                         regulator-always-on;
                                 };
 
@@ -316,8 +329,8 @@
                                         reg = <10>;
                                         regulator-compatible = "ldo6";
                                         regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
                                 };
 
                                 hdmi_vdd_reg: regulator@11 {
@@ -362,7 +375,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
                 nvidia,cpu-pwr-off-time = <5000>;
@@ -442,14 +455,6 @@
                 };
         };
 
-        ac97: ac97 {
-                status = "okay";
-                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
-                        GPIO_ACTIVE_HIGH>;
-                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
-                        GPIO_ACTIVE_HIGH>;
-        };
-
         usb@c5004000 {
                 status = "okay";
                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
@@ -471,7 +476,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -479,37 +484,17 @@
                 };
         };
 
-        sound {
-                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
-                                 "nvidia,tegra-audio-wm9712";
-                nvidia,model = "Colibri T20 AC97 Audio";
-
-                nvidia,audio-routing =
-                        "Headphone", "HPOUTL",
-                        "Headphone", "HPOUTR",
-                        "LineIn", "LINEINL",
-                        "LineIn", "LINEINR",
-                        "Mic", "MIC1";
-
-                nvidia,ac97-controller = <&ac97>;
-
-                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
-                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
-                         <&tegra_car TEGRA20_CLK_CDEV1>;
-                clock-names = "pll_a", "pll_a_out0", "mclk";
-        };
-
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                vdd_5v0_reg: regulator@100 {
+                vdd_3v3_reg: regulator@100 {
                         compatible = "regulator-fixed";
                         reg = <100>;
-                        regulator-name = "vdd_5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
+                        regulator-name = "vdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
 
@@ -525,4 +510,24 @@
                         gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
                 };
         };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+                                 "nvidia,tegra-audio-wm9712";
+                nvidia,model = "Colibri T20 AC97 Audio";
+
+                nvidia,audio-routing =
+                        "Headphone", "HPOUTL",
+                        "Headphone", "HPOUTR",
+                        "LineIn", "LINEINL",
+                        "LineIn", "LINEINR",
+                        "Mic", "MIC1";
+
+                nvidia,ac97-controller = <&ac97>;
+
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab30e763..3fb1f50f6d46 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,17 +1,31 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Harmony evaluation board";
         compatible = "nvidia,harmony", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+
+                                nvidia,panel = <&panel>;
+                        };
+                };
+
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +37,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -184,50 +198,50 @@
                                         "gmb", "gmc", "gmd", "gme", "gpu7",
                                         "gpv", "i2cp", "pta", "rm", "slxa",
                                         "slxk", "spia", "spib", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
                                         "dtc", "dte", "dtf", "gpu", "sdio1",
                                         "slxc", "slxd", "spdi", "spdo", "spig",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "sdc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "owc", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
                                         "spie", "spih", "uaa", "uab", "uad",
                                         "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -237,12 +251,12 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
         };
@@ -255,6 +269,10 @@
                 status = "okay";
         };
 
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
+
         i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <400000>;
@@ -415,7 +433,124 @@
                 };
         };
 
-        pmc {
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <2>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+                                MATRIX_KEY(0x00, 0x03, KEY_S)
+                                MATRIX_KEY(0x00, 0x04, KEY_A)
+                                MATRIX_KEY(0x00, 0x05, KEY_Z)
+                                MATRIX_KEY(0x00, 0x07, KEY_FN)
+                                MATRIX_KEY(0x01, 0x07, KEY_MENU)
+                                MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
+                                MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
+                                MATRIX_KEY(0x03, 0x00, KEY_5)
+                                MATRIX_KEY(0x03, 0x01, KEY_4)
+                                MATRIX_KEY(0x03, 0x02, KEY_R)
+                                MATRIX_KEY(0x03, 0x03, KEY_E)
+                                MATRIX_KEY(0x03, 0x04, KEY_F)
+                                MATRIX_KEY(0x03, 0x05, KEY_D)
+                                MATRIX_KEY(0x03, 0x06, KEY_X)
+                                MATRIX_KEY(0x04, 0x00, KEY_7)
+                                MATRIX_KEY(0x04, 0x01, KEY_6)
+                                MATRIX_KEY(0x04, 0x02, KEY_T)
+                                MATRIX_KEY(0x04, 0x03, KEY_H)
+                                MATRIX_KEY(0x04, 0x04, KEY_G)
+                                MATRIX_KEY(0x04, 0x05, KEY_V)
+                                MATRIX_KEY(0x04, 0x06, KEY_C)
+                                MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+                                MATRIX_KEY(0x05, 0x00, KEY_9)
+                                MATRIX_KEY(0x05, 0x01, KEY_8)
+                                MATRIX_KEY(0x05, 0x02, KEY_U)
+                                MATRIX_KEY(0x05, 0x03, KEY_Y)
+                                MATRIX_KEY(0x05, 0x04, KEY_J)
+                                MATRIX_KEY(0x05, 0x05, KEY_N)
+                                MATRIX_KEY(0x05, 0x06, KEY_B)
+                                MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+                                MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+                                MATRIX_KEY(0x06, 0x01, KEY_0)
+                                MATRIX_KEY(0x06, 0x02, KEY_O)
+                                MATRIX_KEY(0x06, 0x03, KEY_I)
+                                MATRIX_KEY(0x06, 0x04, KEY_L)
+                                MATRIX_KEY(0x06, 0x05, KEY_K)
+                                MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+                                MATRIX_KEY(0x06, 0x07, KEY_M)
+                                MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+                                MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+                                MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+                                MATRIX_KEY(0x07, 0x07, KEY_MENU)
+                                MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
+                                MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
+                                MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
+                                MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
+                                MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+                                MATRIX_KEY(0x0B, 0x01, KEY_P)
+                                MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+                                MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+                                MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+                                MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+                                MATRIX_KEY(0x0C, 0x00, KEY_F10)
+                                MATRIX_KEY(0x0C, 0x01, KEY_F9)
+                                MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+                                MATRIX_KEY(0x0C, 0x03, KEY_3)
+                                MATRIX_KEY(0x0C, 0x04, KEY_2)
+                                MATRIX_KEY(0x0C, 0x05, KEY_UP)
+                                MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+                                MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+                                MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+                                MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+                                MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+                                MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+                                MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+                                MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+                                MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+                                MATRIX_KEY(0x0E, 0x00, KEY_F11)
+                                MATRIX_KEY(0x0E, 0x01, KEY_F12)
+                                MATRIX_KEY(0x0E, 0x02, KEY_F8)
+                                MATRIX_KEY(0x0E, 0x03, KEY_Q)
+                                MATRIX_KEY(0x0E, 0x04, KEY_F4)
+                                MATRIX_KEY(0x0E, 0x05, KEY_F3)
+                                MATRIX_KEY(0x0E, 0x06, KEY_1)
+                                MATRIX_KEY(0x0E, 0x07, KEY_F7)
+                                MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+                                MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+                                MATRIX_KEY(0x0F, 0x02, KEY_F5)
+                                MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+                                MATRIX_KEY(0x0F, 0x04, KEY_F1)
+                                MATRIX_KEY(0x0F, 0x05, KEY_F2)
+                                MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+                                MATRIX_KEY(0x0F, 0x07, KEY_F6)
+                                MATRIX_KEY(0x14, 0x00, KEY_KP7)
+                                MATRIX_KEY(0x15, 0x00, KEY_KP9)
+                                MATRIX_KEY(0x15, 0x01, KEY_KP8)
+                                MATRIX_KEY(0x15, 0x02, KEY_KP4)
+                                MATRIX_KEY(0x15, 0x04, KEY_KP1)
+                                MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+                                MATRIX_KEY(0x16, 0x02, KEY_KP6)
+                                MATRIX_KEY(0x16, 0x03, KEY_KP5)
+                                MATRIX_KEY(0x16, 0x04, KEY_KP3)
+                                MATRIX_KEY(0x16, 0x05, KEY_KP2)
+                                MATRIX_KEY(0x16, 0x07, KEY_KP0)
+                                MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+                                MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+                                MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+                                MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+                                MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+                                MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+                                MATRIX_KEY(0x1D, 0x04, KEY_END)
+                                MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
+                                MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+                                MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
+                                MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+                                MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+                                MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+                                MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
+        };
+
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -425,7 +560,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
                 status = "okay";
@@ -483,12 +618,23 @@
                 bus-width = <8>;
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -502,126 +648,18 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <2>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
-                linux,keymap = <0x00020011      /* KEY_W */
-                                0x0003001F      /* KEY_S */
-                                0x0004001E      /* KEY_A */
-                                0x0005002C      /* KEY_Z */
-                                0x000701D0      /* KEY_FN */
-                                0x0107008B      /* KEY_MENU */
-                                0x02060038      /* KEY_LEFTALT */
-                                0x02070064      /* KEY_RIGHTALT */
-                                0x03000006      /* KEY_5 */
-                                0x03010005      /* KEY_4 */
-                                0x03020013      /* KEY_R */
-                                0x03030012      /* KEY_E */
-                                0x03040021      /* KEY_F */
-                                0x03050020      /* KEY_D */
-                                0x0306002D      /* KEY_X */
-                                0x04000008      /* KEY_7 */
-                                0x04010007      /* KEY_6 */
-                                0x04020014      /* KEY_T */
-                                0x04030023      /* KEY_H */
-                                0x04040022      /* KEY_G */
-                                0x0405002F      /* KEY_V */
-                                0x0406002E      /* KEY_C */
-                                0x04070039      /* KEY_SPACE */
-                                0x0500000A      /* KEY_9 */
-                                0x05010009      /* KEY_8 */
-                                0x05020016      /* KEY_U */
-                                0x05030015      /* KEY_Y */
-                                0x05040024      /* KEY_J */
-                                0x05050031      /* KEY_N */
-                                0x05060030      /* KEY_B */
-                                0x0507002B      /* KEY_BACKSLASH */
-                                0x0600000C      /* KEY_MINUS */
-                                0x0601000B      /* KEY_0 */
-                                0x06020018      /* KEY_O */
-                                0x06030017      /* KEY_I */
-                                0x06040026      /* KEY_L */
-                                0x06050025      /* KEY_K */
-                                0x06060033      /* KEY_COMMA */
-                                0x06070032      /* KEY_M */
-                                0x0701000D      /* KEY_EQUAL */
-                                0x0702001B      /* KEY_RIGHTBRACE */
-                                0x0703001C      /* KEY_ENTER */
-                                0x0707008B      /* KEY_MENU */
-                                0x0804002A      /* KEY_LEFTSHIFT */
-                                0x08050036      /* KEY_RIGHTSHIFT */
-                                0x0905001D      /* KEY_LEFTCTRL */
-                                0x09070061      /* KEY_RIGHTCTRL */
-                                0x0B00001A      /* KEY_LEFTBRACE */
-                                0x0B010019      /* KEY_P */
-                                0x0B020028      /* KEY_APOSTROPHE */
-                                0x0B030027      /* KEY_SEMICOLON */
-                                0x0B040035      /* KEY_SLASH */
-                                0x0B050034      /* KEY_DOT */
-                                0x0C000044      /* KEY_F10 */
-                                0x0C010043      /* KEY_F9 */
-                                0x0C02000E      /* KEY_BACKSPACE */
-                                0x0C030004      /* KEY_3 */
-                                0x0C040003      /* KEY_2 */
-                                0x0C050067      /* KEY_UP */
-                                0x0C0600D2      /* KEY_PRINT */
-                                0x0C070077      /* KEY_PAUSE */
-                                0x0D00006E      /* KEY_INSERT */
-                                0x0D01006F      /* KEY_DELETE */
-                                0x0D030068      /* KEY_PAGEUP */
-                                0x0D04006D      /* KEY_PAGEDOWN */
-                                0x0D05006A      /* KEY_RIGHT */
-                                0x0D06006C      /* KEY_DOWN */
-                                0x0D070069      /* KEY_LEFT */
-                                0x0E000057      /* KEY_F11 */
-                                0x0E010058      /* KEY_F12 */
-                                0x0E020042      /* KEY_F8 */
-                                0x0E030010      /* KEY_Q */
-                                0x0E04003E      /* KEY_F4 */
-                                0x0E05003D      /* KEY_F3 */
-                                0x0E060002      /* KEY_1 */
-                                0x0E070041      /* KEY_F7 */
-                                0x0F000001      /* KEY_ESC */
-                                0x0F010029      /* KEY_GRAVE */
-                                0x0F02003F      /* KEY_F5 */
-                                0x0F03000F      /* KEY_TAB */
-                                0x0F04003B      /* KEY_F1 */
-                                0x0F05003C      /* KEY_F2 */
-                                0x0F06003A      /* KEY_CAPSLOCK */
-                                0x0F070040      /* KEY_F6 */
-                                0x14000047      /* KEY_KP7 */
-                                0x15000049      /* KEY_KP9 */
-                                0x15010048      /* KEY_KP8 */
-                                0x1502004B      /* KEY_KP4 */
-                                0x1504004F      /* KEY_KP1 */
-                                0x1601004E      /* KEY_KPSLASH */
-                                0x1602004D      /* KEY_KP6 */
-                                0x1603004C      /* KEY_KP5 */
-                                0x16040051      /* KEY_KP3 */
-                                0x16050050      /* KEY_KP2 */
-                                0x16070052      /* KEY_KP0 */
-                                0x1B010037      /* KEY_KPASTERISK */
-                                0x1B03004A      /* KEY_KPMINUS */
-                                0x1B04004E      /* KEY_KPPLUS */
-                                0x1B050053      /* KEY_KPDOT */
-                                0x1C050073      /* KEY_VOLUMEUP */
-                                0x1D030066      /* KEY_HOME */
-                                0x1D04006B      /* KEY_END */
-                                0x1D0500E1      /* KEY_BRIGHTNESSUP */
-                                0x1D060072      /* KEY_VOLUMEDOWN */
-                                0x1D0700E0      /* KEY_BRIGHTNESSDOWN */
-                                0x1E000045      /* KEY_NUMLOCK */
-                                0x1E010046      /* KEY_SCROLLLOCK */
-                                0x1E020071      /* KEY_MUTE */
-                                0x1F0400D6>;    /* KEY_QUESTION */
+        panel: panel {
+                compatible = "auo,b101aw03", "simple-panel";
+
+                power-supply = <&vdd_pnl_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+                backlight = <&backlight>;
         };
 
         regulators {
@@ -667,7 +705,7 @@
                         enable-active-high;
                 };
 
-                regulator@4 {
+                vdd_pnl_reg: regulator@4 {
                         compatible = "regulator-fixed";
                         reg = <4>;
                         regulator-name = "vdd_pnl";
@@ -677,7 +715,7 @@
                         enable-active-high;
                 };
 
-                regulator@5 {
+                vdd_bl_reg: regulator@5 {
                         compatible = "regulator-fixed";
                         reg = <5>;
                         regulator-name = "vdd_bl";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index f2222bd74eab..8cfb83f42e1f 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -6,61 +6,61 @@
         model = "Toradex Colibri T20 512MB on Iris";
         compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 state_default: pinmux {
                         hdint {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         i2cddc {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         sdio4 {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         uarta {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
                         uartd {
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
 
-        usb@c5000000 {
+        serial@70006000 {
                 status = "okay";
         };
 
-        usb-phy@c5000000 {
+        serial@70006300 {
                 status = "okay";
         };
 
-        usb@c5008000 {
+        i2c_ddc: i2c@7000c400 {
                 status = "okay";
         };
 
-        usb-phy@c5008000 {
+        usb@c5000000 {
                 status = "okay";
         };
 
-        serial@70006000 {
+        usb-phy@c5000000 {
                 status = "okay";
         };
 
-        serial@70006300 {
+        usb@c5008000 {
                 status = "okay";
         };
 
-        i2c_ddc: i2c@7000c400 {
+        usb-phy@c5008000 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 7580578903cf..6d3a4cbc36cc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,7 +6,7 @@
         model = "Avionic Design Medcom-Wide board";
         compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
 
-        pwm {
+        pwm@7000a000 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8d71fc9d8a2f..c7cd8e6802d7 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "Toshiba AC100 / Dynabook AZ";
         compatible = "compal,paz00", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -177,39 +183,39 @@
                                         "gpu", "gpu7", "gpv", "i2cp", "pta",
                                         "rm", "sdio1", "slxk", "spdo", "uac",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
                                         "dtc", "dte", "slxa", "slxc", "slxd",
                                         "spdi";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spia", "spib", "spid",
                                         "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "spic", "spig", "uaa", "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
                                         "spie", "spih", "uad", "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
@@ -218,23 +224,23 @@
                                         "ld13", "ld14", "ld15", "ld16", "ld17",
                                         "ldc", "ldi", "lhs", "lsc0", "lspi",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_lcsn {
                                 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
                                         "lm0", "lm1", "lpp", "lpw0", "lpw1",
                                         "lpw2", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "lvp1", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
         };
@@ -268,7 +274,7 @@
                 clock-frequency = <100000>;
         };
 
-        nvec {
+        nvec@7000c500 {
                 compatible = "nvidia,nvec";
                 reg = <0x7000c500 0x100>;
                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -280,6 +286,8 @@
                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
         };
 
         i2c@7000d000 {
@@ -415,7 +423,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -472,7 +480,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -486,7 +494,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index d7a358a6a647..29051a2ae0ae 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,8 +6,8 @@
         model = "Avionic Design Plutux board";
         compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 315aae26c3cd..a11b6e7b4759 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
         compatible = "nvidia,seaboard", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,53 +195,53 @@
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxd", "slxk", "spdi", "spdo", "uac",
                                         "uad", "uca", "ucb", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ate {
                                 nvidia,pins = "ate", "csus", "dap3",
                                         "gpv", "owc", "slxc", "spib", "spid",
                                         "spie";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "gmb", "slxa", "spia",
                                         "spig", "spih";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dte {
                                 nvidia,pins = "dte", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_kbca {
                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
                                         "kbce", "kbcf", "sdio1", "spic", "uaa",
                                         "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -245,22 +251,22 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <31>;
                                 nvidia,pull-up-strength = <31>;
-                                nvidia,slew-rate-rising = <3>;
-                                nvidia,slew-rate-falling = <3>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
                         };
                 };
 
@@ -386,6 +392,13 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                magnetometer@c {
+                        compatible = "ak,ak8975";
+                        reg = <0xc>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
+                };
+
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
@@ -507,16 +520,149 @@
                         compatible = "onnn,nct1008";
                         reg = <0x4c>;
                 };
+        };
 
-                magnetometer@c {
-                        compatible = "ak,ak8975";
-                        reg = <0xc>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
-                };
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <32>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,ghost-filter;
+                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+                linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+                                MATRIX_KEY(0x00, 0x03, KEY_S)
+                                MATRIX_KEY(0x00, 0x04, KEY_A)
+                                MATRIX_KEY(0x00, 0x05, KEY_Z)
+                                MATRIX_KEY(0x00, 0x07, KEY_FN)
+
+                                MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
+                                MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
+                                MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
+
+                                MATRIX_KEY(0x03, 0x00, KEY_5)
+                                MATRIX_KEY(0x03, 0x01, KEY_4)
+                                MATRIX_KEY(0x03, 0x02, KEY_R)
+                                MATRIX_KEY(0x03, 0x03, KEY_E)
+                                MATRIX_KEY(0x03, 0x04, KEY_F)
+                                MATRIX_KEY(0x03, 0x05, KEY_D)
+                                MATRIX_KEY(0x03, 0x06, KEY_X)
+
+                                MATRIX_KEY(0x04, 0x00, KEY_7)
+                                MATRIX_KEY(0x04, 0x01, KEY_6)
+                                MATRIX_KEY(0x04, 0x02, KEY_T)
+                                MATRIX_KEY(0x04, 0x03, KEY_H)
+                                MATRIX_KEY(0x04, 0x04, KEY_G)
+                                MATRIX_KEY(0x04, 0x05, KEY_V)
+                                MATRIX_KEY(0x04, 0x06, KEY_C)
+                                MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+
+                                MATRIX_KEY(0x05, 0x00, KEY_9)
+                                MATRIX_KEY(0x05, 0x01, KEY_8)
+                                MATRIX_KEY(0x05, 0x02, KEY_U)
+                                MATRIX_KEY(0x05, 0x03, KEY_Y)
+                                MATRIX_KEY(0x05, 0x04, KEY_J)
+                                MATRIX_KEY(0x05, 0x05, KEY_N)
+                                MATRIX_KEY(0x05, 0x06, KEY_B)
+                                MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+
+                                MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+                                MATRIX_KEY(0x06, 0x01, KEY_0)
+                                MATRIX_KEY(0x06, 0x02, KEY_O)
+                                MATRIX_KEY(0x06, 0x03, KEY_I)
+                                MATRIX_KEY(0x06, 0x04, KEY_L)
+                                MATRIX_KEY(0x06, 0x05, KEY_K)
+                                MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+                                MATRIX_KEY(0x06, 0x07, KEY_M)
+
+                                MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+                                MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+                                MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+                                MATRIX_KEY(0x07, 0x07, KEY_MENU)
+
+                                MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
+                                MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
+
+                                MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
+                                MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
+
+                                MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+                                MATRIX_KEY(0x0B, 0x01, KEY_P)
+                                MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+                                MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+                                MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+                                MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+
+                                MATRIX_KEY(0x0C, 0x00, KEY_F10)
+                                MATRIX_KEY(0x0C, 0x01, KEY_F9)
+                                MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+                                MATRIX_KEY(0x0C, 0x03, KEY_3)
+                                MATRIX_KEY(0x0C, 0x04, KEY_2)
+                                MATRIX_KEY(0x0C, 0x05, KEY_UP)
+                                MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+                                MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+
+                                MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+                                MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+                                MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+                                MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+                                MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+                                MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+                                MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+
+                                MATRIX_KEY(0x0E, 0x00, KEY_F11)
+                                MATRIX_KEY(0x0E, 0x01, KEY_F12)
+                                MATRIX_KEY(0x0E, 0x02, KEY_F8)
+                                MATRIX_KEY(0x0E, 0x03, KEY_Q)
+                                MATRIX_KEY(0x0E, 0x04, KEY_F4)
+                                MATRIX_KEY(0x0E, 0x05, KEY_F3)
+                                MATRIX_KEY(0x0E, 0x06, KEY_1)
+                                MATRIX_KEY(0x0E, 0x07, KEY_F7)
+
+                                MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+                                MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+                                MATRIX_KEY(0x0F, 0x02, KEY_F5)
+                                MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+                                MATRIX_KEY(0x0F, 0x04, KEY_F1)
+                                MATRIX_KEY(0x0F, 0x05, KEY_F2)
+                                MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+                                MATRIX_KEY(0x0F, 0x07, KEY_F6)
+
+                                /* Software Handled Function Keys */
+                                MATRIX_KEY(0x14, 0x00, KEY_KP7)
+
+                                MATRIX_KEY(0x15, 0x00, KEY_KP9)
+                                MATRIX_KEY(0x15, 0x01, KEY_KP8)
+                                MATRIX_KEY(0x15, 0x02, KEY_KP4)
+                                MATRIX_KEY(0x15, 0x04, KEY_KP1)
+
+                                MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+                                MATRIX_KEY(0x16, 0x02, KEY_KP6)
+                                MATRIX_KEY(0x16, 0x03, KEY_KP5)
+                                MATRIX_KEY(0x16, 0x04, KEY_KP3)
+                                MATRIX_KEY(0x16, 0x05, KEY_KP2)
+                                MATRIX_KEY(0x16, 0x07, KEY_KP0)
+
+                                MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+                                MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+                                MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+                                MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+
+                                MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+
+                                MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+                                MATRIX_KEY(0x1D, 0x04, KEY_END)
+                                MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
+                                MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+                                MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
+
+                                MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+                                MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+                                MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+
+                                MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -621,7 +767,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -635,7 +781,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
 
@@ -649,145 +795,6 @@
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <32>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,ghost-filter;
-                nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-                nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
-                linux,keymap = <0x00020011      /* KEY_W */
-                                0x0003001F      /* KEY_S */
-                                0x0004001E      /* KEY_A */
-                                0x0005002C      /* KEY_Z */
-                                0x000701d0      /* KEY_FN */
-
-                                0x0107007D      /* KEY_LEFTMETA */
-                                0x02060064      /* KEY_RIGHTALT */
-                                0x02070038      /* KEY_LEFTALT */
-
-                                0x03000006      /* KEY_5 */
-                                0x03010005      /* KEY_4 */
-                                0x03020013      /* KEY_R */
-                                0x03030012      /* KEY_E */
-                                0x03040021      /* KEY_F */
-                                0x03050020      /* KEY_D */
-                                0x0306002D      /* KEY_X */
-
-                                0x04000008      /* KEY_7 */
-                                0x04010007      /* KEY_6 */
-                                0x04020014      /* KEY_T */
-                                0x04030023      /* KEY_H */
-                                0x04040022      /* KEY_G */
-                                0x0405002F      /* KEY_V */
-                                0x0406002E      /* KEY_C */
-                                0x04070039      /* KEY_SPACE */
-
-                                0x0500000A      /* KEY_9 */
-                                0x05010009      /* KEY_8 */
-                                0x05020016      /* KEY_U */
-                                0x05030015      /* KEY_Y */
-                                0x05040024      /* KEY_J */
-                                0x05050031      /* KEY_N */
-                                0x05060030      /* KEY_B */
-                                0x0507002B      /* KEY_BACKSLASH */
-
-                                0x0600000C      /* KEY_MINUS */
-                                0x0601000B      /* KEY_0 */
-                                0x06020018      /* KEY_O */
-                                0x06030017      /* KEY_I */
-                                0x06040026      /* KEY_L */
-                                0x06050025      /* KEY_K */
-                                0x06060033      /* KEY_COMMA */
-                                0x06070032      /* KEY_M */
-
-                                0x0701000D      /* KEY_EQUAL */
-                                0x0702001B      /* KEY_RIGHTBRACE */
-                                0x0703001C      /* KEY_ENTER */
-                                0x0707008B      /* KEY_MENU */
-
-                                0x08040036      /* KEY_RIGHTSHIFT */
-                                0x0805002A      /* KEY_LEFTSHIFT */
-
-                                0x09050061      /* KEY_RIGHTCTRL */
-                                0x0907001D      /* KEY_LEFTCTRL */
-
-                                0x0B00001A      /* KEY_LEFTBRACE */
-                                0x0B010019      /* KEY_P */
-                                0x0B020028      /* KEY_APOSTROPHE */
-                                0x0B030027      /* KEY_SEMICOLON */
-                                0x0B040035      /* KEY_SLASH */
-                                0x0B050034      /* KEY_DOT */
-
-                                0x0C000044      /* KEY_F10 */
-                                0x0C010043      /* KEY_F9 */
-                                0x0C02000E      /* KEY_BACKSPACE */
-                                0x0C030004      /* KEY_3 */
-                                0x0C040003      /* KEY_2 */
-                                0x0C050067      /* KEY_UP */
-                                0x0C0600D2      /* KEY_PRINT */
-                                0x0C070077      /* KEY_PAUSE */
-
-                                0x0D00006E      /* KEY_INSERT */
-                                0x0D01006F      /* KEY_DELETE */
-                                0x0D030068      /* KEY_PAGEUP  */
-                                0x0D04006D      /* KEY_PAGEDOWN */
-                                0x0D05006A      /* KEY_RIGHT */
-                                0x0D06006C      /* KEY_DOWN */
-                                0x0D070069      /* KEY_LEFT */
-
-                                0x0E000057      /* KEY_F11 */
-                                0x0E010058      /* KEY_F12 */
-                                0x0E020042      /* KEY_F8 */
-                                0x0E030010      /* KEY_Q */
-                                0x0E04003E      /* KEY_F4 */
-                                0x0E05003D      /* KEY_F3 */
-                                0x0E060002      /* KEY_1 */
-                                0x0E070041      /* KEY_F7 */
-
-                                0x0F000001      /* KEY_ESC */
-                                0x0F010029      /* KEY_GRAVE */
-                                0x0F02003F      /* KEY_F5 */
-                                0x0F03000F      /* KEY_TAB */
-                                0x0F04003B      /* KEY_F1 */
-                                0x0F05003C      /* KEY_F2 */
-                                0x0F06003A      /* KEY_CAPSLOCK */
-                                0x0F070040      /* KEY_F6 */
-
-                                /* Software Handled Function Keys */
-                                0x14000047      /* KEY_KP7 */
-
-                                0x15000049      /* KEY_KP9 */
-                                0x15010048      /* KEY_KP8 */
-                                0x1502004B      /* KEY_KP4 */
-                                0x1504004F      /* KEY_KP1 */
-
-                                0x1601004E      /* KEY_KPSLASH */
-                                0x1602004D      /* KEY_KP6 */
-                                0x1603004C      /* KEY_KP5 */
-                                0x16040051      /* KEY_KP3 */
-                                0x16050050      /* KEY_KP2 */
-                                0x16070052      /* KEY_KP0 */
-
-                                0x1B010037      /* KEY_KPASTERISK */
-                                0x1B03004A      /* KEY_KPMINUS */
-                                0x1B04004E      /* KEY_KPPLUS */
-                                0x1B050053      /* KEY_KPDOT */
-
-                                0x1C050073      /* KEY_VOLUMEUP */
-
-                                0x1D030066      /* KEY_HOME */
-                                0x1D04006B      /* KEY_END */
-                                0x1D0500E0      /* KEY_BRIGHTNESSDOWN */
-                                0x1D060072      /* KEY_VOLUMEDOWN */
-                                0x1D0700E1      /* KEY_BRIGHTNESSUP */
-
-                                0x1E000045      /* KEY_NUMLOCK */
-                                0x1E010046      /* KEY_SCROLLLOCK */
-                                0x1E020071      /* KEY_MUTE */
-
-                                0x1F04008A>;    /* KEY_HELP */
-        };
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 7726dab3d08d..a1b0d965757f 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -4,12 +4,17 @@
         model = "Avionic Design Tamonten SOM";
         compatible = "ad,tamonten", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         vdd-supply = <&hdmi_vdd_reg>;
                         pll-supply = <&hdmi_pll_reg>;
 
@@ -19,7 +24,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -176,50 +181,50 @@
                                         "gmb", "gmc", "gmd", "gme", "gpu7",
                                         "gpv", "i2cp", "pta", "rm", "slxa",
                                         "slxk", "spia", "spib", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
                                         "dtc", "dte", "dtf", "gpu", "sdio1",
                                         "slxc", "slxd", "spdi", "spdo", "spig",
                                         "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
                                         "sdc";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "owc", "sdb";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
                                         "spie", "spih", "uaa", "uab", "uad",
                                         "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -229,12 +234,12 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                 };
 
@@ -457,7 +462,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
@@ -467,7 +472,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
         };
@@ -492,7 +497,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 3ada3cb67f07..890562c667fb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,8 +6,8 @@
         model = "Avionic Design Tamonten Evaluation Carrier";
         compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
                 };
         };
@@ -32,7 +32,7 @@
                 };
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 status = "okay";
 
                 pci@1,0 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 78deea5c0d21..216fa6d50c65 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "Compulab TrimSlice board";
         compatible = "compulab,trimslice", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000c500/rtc@56";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -191,49 +197,49 @@
                                         "dtb", "dtc", "dtd", "dte", "gmb",
                                         "gme", "i2cp", "pta", "slxc", "slxd",
                                         "spdi", "spdo", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_atb {
                                 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
                                         "gma", "gmc", "gmd", "gpu", "gpu7",
                                         "gpv", "sdio1", "slxa", "slxk", "uac";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_csus {
                                 nvidia,pins = "csus", "spia", "spib",
                                         "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ddc {
                                 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0", "pmc";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_irrx {
                                 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
                                         "kbcc", "kbcd", "kbce", "kbcf", "owc",
                                         "spic", "spie", "spig", "spih", "uaa",
                                         "uab", "uad", "uca", "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -243,17 +249,17 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         conf_spif {
                                 nvidia,pins = "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
@@ -301,7 +307,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <5000>;
                 nvidia,cpu-pwr-off-time = <5000>;
@@ -310,7 +316,7 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 status = "okay";
                 pex-clk-supply = <&pci_clk_reg>;
                 vdd-supply = <&pci_vdd_reg>;
@@ -366,7 +372,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -380,7 +386,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index aab872cd0530..571d12e6ac2d 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Ventana evaluation board";
         compatible = "nvidia,ventana", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x40000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,50 +195,50 @@
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxc", "slxd", "slxk", "spdi", "spdo",
                                         "uac", "uad", "uca", "ucb", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ate {
                                 nvidia,pins = "ate", "csus", "dap3", "gmd",
                                         "gpv", "owc", "spia", "spib", "spic",
                                         "spid", "spie", "spig";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "gmb", "slxa", "spih";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dte {
                                 nvidia,pins = "dte", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsck", "lsda", "lsdi", "lvp0";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_kbca {
                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
                                         "kbce", "kbcf", "sdio1", "uaa", "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -242,22 +248,22 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
                                         "lvp1", "lvs", "pmc", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <1>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <31>;
                                 nvidia,pull-up-strength = <31>;
-                                nvidia,slew-rate-rising = <3>;
-                                nvidia,slew-rate-falling = <3>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
                         };
                 };
 
@@ -492,7 +498,7 @@
                 };
         };
 
-        pmc {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -556,7 +562,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -570,7 +576,7 @@
                 power {
                         label = "Power";
                         gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d33a73cf167c..1843725785c9 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,17 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Whistler evaluation board";
         compatible = "nvidia,whistler", "nvidia,tegra20";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/max8907@3c";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x00000000 0x20000000>;
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000014 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -189,8 +195,8 @@
                                         "kbcf", "sdc", "sdd", "spie", "spig",
                                         "spih", "uaa", "uab", "uad", "uca",
                                         "ucb";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_atd {
                                 nvidia,pins = "atd", "ate", "cdev1", "csus",
@@ -198,54 +204,54 @@
                                         "dtf", "gpu", "gpu7", "gpv", "i2cp",
                                         "rm", "sdio1", "slxa", "slxc", "slxd",
                                         "slxk", "spdi", "spdo", "uac", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_cdev2 {
                                 nvidia,pins = "cdev2", "spia", "spib";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
                                         "pmcb", "pmcc", "pmcd", "xm2c",
                                         "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd",
                                         "spid", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_gme {
                                 nvidia,pins = "gme", "owc", "pta", "spic";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         conf_ls {
                                 nvidia,pins = "ls", "pmce";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         drive_dap1 {
                                 nvidia,pins = "drive_dap1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <1>;
-                                nvidia,low-power-mode = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
                                 nvidia,pull-down-strength = <0>;
                                 nvidia,pull-up-strength = <0>;
-                                nvidia,slew-rate-rising = <0>;
-                                nvidia,slew-rate-falling = <0>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                         };
                 };
         };
@@ -495,7 +501,20 @@
                 };
         };
 
-        pmc {
+        kbc@7000e200 {
+                status = "okay";
+                nvidia,debounce-delay-ms = <20>;
+                nvidia,repeat-delay-ms = <160>;
+                nvidia,kbc-row-pins = <0 1 2>;
+                nvidia,kbc-col-pins = <16 17>;
+                nvidia,wakeup-source;
+                linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
+                                MATRIX_KEY(0x01, 0x00, KEY_HOME)
+                                MATRIX_KEY(0x01, 0x01, KEY_BACK)
+                                MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
+        };
+
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <2000>;
@@ -543,7 +562,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -551,25 +570,12 @@
                 };
         };
 
-        kbc {
-                status = "okay";
-                nvidia,debounce-delay-ms = <20>;
-                nvidia,repeat-delay-ms = <160>;
-                nvidia,kbc-row-pins = <0 1 2>;
-                nvidia,kbc-col-pins = <16 17>;
-                nvidia,wakeup-source;
-                linux,keymap = <0x00000074      /* KEY_POWER */
-                                0x01000066      /* KEY_HOME */
-                                0x0101009E      /* KEY_BACK */
-                                0x0201008B>;    /* KEY_MENU */
-        };
-
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                usb0_vbus_reg: regulator {
+                usb0_vbus_reg: regulator@0 {
                         compatible = "regulator-fixed";
                         reg = <0>;
                         regulator-name = "usb0_vbus";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..480ecda3416b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra20-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -16,57 +17,71 @@
                 serial4 = &uarte;
         };
 
-        host1x {
+        host1x@50000000 {
                 compatible = "nvidia,tegra20-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+                resets = <&tegra_car 28>;
+                reset-names = "host1x";
 
                 #address-cells = <1>;
                 #size-cells = <1>;
 
                 ranges = <0x54000000 0x54000000 0x04000000>;
 
-                mpe {
+                mpe@54040000 {
                         compatible = "nvidia,tegra20-mpe";
                         reg = <0x54040000 0x00040000>;
                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
+                        resets = <&tegra_car 60>;
+                        reset-names = "mpe";
                 };
 
-                vi {
+                vi@54080000 {
                         compatible = "nvidia,tegra20-vi";
                         reg = <0x54080000 0x00040000>;
                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_VI>;
+                        resets = <&tegra_car 20>;
+                        reset-names = "vi";
                 };
 
-                epp {
+                epp@540c0000 {
                         compatible = "nvidia,tegra20-epp";
                         reg = <0x540c0000 0x00040000>;
                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
+                        resets = <&tegra_car 19>;
+                        reset-names = "epp";
                 };
 
-                isp {
+                isp@54100000 {
                         compatible = "nvidia,tegra20-isp";
                         reg = <0x54100000 0x00040000>;
                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
+                        resets = <&tegra_car 23>;
+                        reset-names = "isp";
                 };
 
-                gr2d {
+                gr2d@54140000 {
                         compatible = "nvidia,tegra20-gr2d";
                         reg = <0x54140000 0x00040000>;
                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+                        resets = <&tegra_car 21>;
+                        reset-names = "2d";
                 };
 
-                gr3d {
+                gr3d@54140000 {
                         compatible = "nvidia,tegra20-gr3d";
-                        reg = <0x54180000 0x00040000>;
+                        reg = <0x54140000 0x00040000>;
                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+                        resets = <&tegra_car 24>;
+                        reset-names = "3d";
                 };
 
                 dc@54200000 {
@@ -75,7 +90,9 @@
                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
                                  <&tegra_car TEGRA20_CLK_PLL_P>;
-                        clock-names = "disp1", "parent";
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 27>;
+                        reset-names = "dc";
 
                         rgb {
                                 status = "disabled";
@@ -88,24 +105,28 @@
                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
                                  <&tegra_car TEGRA20_CLK_PLL_P>;
-                        clock-names = "disp2", "parent";
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 26>;
+                        reset-names = "dc";
 
                         rgb {
                                 status = "disabled";
                         };
                 };
 
-                hdmi {
+                hdmi@54280000 {
                         compatible = "nvidia,tegra20-hdmi";
                         reg = <0x54280000 0x00040000>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
                         clock-names = "hdmi", "parent";
+                        resets = <&tegra_car 51>;
+                        reset-names = "hdmi";
                         status = "disabled";
                 };
 
-                tvo {
+                tvo@542c0000 {
                         compatible = "nvidia,tegra20-tvo";
                         reg = <0x542c0000 0x00040000>;
                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -113,10 +134,12 @@
                         status = "disabled";
                 };
 
-                dsi {
+                dsi@542c0000 {
                         compatible = "nvidia,tegra20-dsi";
-                        reg = <0x54300000 0x00040000>;
+                        reg = <0x542c0000 0x00040000>;
                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
+                        resets = <&tegra_car 48>;
+                        reset-names = "dsi";
                         status = "disabled";
                 };
         };
@@ -129,7 +152,7 @@
                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
         };
 
-        intc: interrupt-controller {
+        intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
                        0x50040100 0x0100>;
@@ -137,7 +160,7 @@
                 #interrupt-cells = <3>;
         };
 
-        cache-controller {
+        cache-controller@50043000 {
                 compatible = "arm,pl310-cache";
                 reg = <0x50043000 0x1000>;
                 arm,data-latency = <5 5 2>;
@@ -156,13 +179,14 @@
                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra20-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
+                #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -182,14 +206,17 @@
                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+                resets = <&tegra_car 34>;
+                reset-names = "dma";
+                #dma-cells = <1>;
         };
 
-        ahb {
+        ahb@6000c004 {
                 compatible = "nvidia,tegra20-ahb";
                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra20-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -205,7 +232,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000014 {
                 compatible = "nvidia,tegra20-pinmux";
                 reg = <0x70000014 0x10   /* Tri-state registers */
                        0x70000080 0x20   /* Mux registers */
@@ -213,17 +240,20 @@
                        0x70000868 0xa8>; /* Pad control registers */
         };
 
-        das {
+        das@70000c00 {
                 compatible = "nvidia,tegra20-das";
                 reg = <0x70000c00 0x80>;
         };
 
-        tegra_ac97: ac97 {
+        tegra_ac97: ac97@70002000 {
                 compatible = "nvidia,tegra20-ac97";
                 reg = <0x70002000 0x200>;
                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 12>;
                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
+                resets = <&tegra_car 3>;
+                reset-names = "ac97";
+                dmas = <&apbdma 12>, <&apbdma 12>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -231,8 +261,11 @@
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 2>;
                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+                resets = <&tegra_car 11>;
+                reset-names = "i2s";
+                dmas = <&apbdma 2>, <&apbdma 2>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -240,8 +273,11 @@
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 1>;
                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+                resets = <&tegra_car 18>;
+                reset-names = "i2s";
+                dmas = <&apbdma 1>, <&apbdma 1>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -257,8 +293,11 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 8>;
                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+                resets = <&tegra_car 6>;
+                reset-names = "serial";
+                dmas = <&apbdma 8>, <&apbdma 8>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -267,8 +306,11 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 9>;
                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+                resets = <&tegra_car 7>;
+                reset-names = "serial";
+                dmas = <&apbdma 9>, <&apbdma 9>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -277,8 +319,11 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 10>;
                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+                resets = <&tegra_car 55>;
+                reset-names = "serial";
+                dmas = <&apbdma 10>, <&apbdma 10>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -287,8 +332,11 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 19>;
                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+                resets = <&tegra_car 65>;
+                reset-names = "serial";
+                dmas = <&apbdma 19>, <&apbdma 19>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -297,20 +345,25 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 20>;
                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+                resets = <&tegra_car 66>;
+                reset-names = "serial";
+                dmas = <&apbdma 20>, <&apbdma 20>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
+                resets = <&tegra_car 17>;
+                reset-names = "pwm";
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,6 +379,10 @@
                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 12>;
+                reset-names = "i2c";
+                dmas = <&apbdma 21>, <&apbdma 21>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -333,10 +390,13 @@
                 compatible = "nvidia,tegra20-sflash";
                 reg = <0x7000c380 0x80>;
                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 11>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
+                resets = <&tegra_car 43>;
+                reset-names = "spi";
+                dmas = <&apbdma 11>, <&apbdma 11>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -349,6 +409,10 @@
                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 54>;
+                reset-names = "i2c";
+                dmas = <&apbdma 22>, <&apbdma 22>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -361,6 +425,10 @@
                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
+                dmas = <&apbdma 23>, <&apbdma 23>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -373,6 +441,10 @@
                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 47>;
+                reset-names = "i2c";
+                dmas = <&apbdma 24>, <&apbdma 24>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -380,10 +452,13 @@
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+                resets = <&tegra_car 41>;
+                reset-names = "spi";
+                dmas = <&apbdma 15>, <&apbdma 15>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -391,10 +466,13 @@
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+                resets = <&tegra_car 44>;
+                reset-names = "spi";
+                dmas = <&apbdma 16>, <&apbdma 16>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -402,10 +480,13 @@
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+                resets = <&tegra_car 46>;
+                reset-names = "spi";
+                dmas = <&apbdma 17>, <&apbdma 17>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -413,22 +494,27 @@
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+                resets = <&tegra_car 68>;
+                reset-names = "spi";
+                dmas = <&apbdma 18>, <&apbdma 18>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
+                resets = <&tegra_car 36>;
+                reset-names = "kbc";
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
@@ -442,7 +528,7 @@
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
-        iommu {
+        iommu@7000f024 {
                 compatible = "nvidia,tegra20-gart";
                 reg = <0x7000f024 0x00000018    /* controller registers */
                        0x58000000 0x02000000>;  /* GART aperture */
@@ -455,7 +541,7 @@
                 #size-cells = <0>;
         };
 
-        pcie-controller {
+        pcie-controller@80003000 {
                 compatible = "nvidia,tegra20-pcie";
                 device_type = "pci";
                 reg = <0x80003000 0x00000800   /* PADS registers */
@@ -478,9 +564,12 @@
 
                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
                          <&tegra_car TEGRA20_CLK_AFI>,
-                         <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
                          <&tegra_car TEGRA20_CLK_PLL_E>;
-                clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+                clock-names = "pex", "afi", "pll_e";
+                resets = <&tegra_car 70>,
+                         <&tegra_car 72>,
+                         <&tegra_car 74>;
+                reset-names = "pex", "afi", "pcie_x";
                 status = "disabled";
 
                 pci@1,0 {
@@ -517,6 +606,8 @@
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
+                resets = <&tegra_car 22>;
+                reset-names = "usb";
                 nvidia,needs-double-reset;
                 nvidia,phy = <&phy1>;
                 status = "disabled";
@@ -548,6 +639,8 @@
                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "ulpi";
                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
+                resets = <&tegra_car 58>;
+                reset-names = "usb";
                 nvidia,phy = <&phy2>;
                 status = "disabled";
         };
@@ -569,6 +662,8 @@
                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
+                resets = <&tegra_car 59>;
+                reset-names = "usb";
                 nvidia,phy = <&phy3>;
                 status = "disabled";
         };
@@ -597,6 +692,8 @@
                 reg = <0xc8000000 0x200>;
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+                resets = <&tegra_car 14>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -605,6 +702,8 @@
                 reg = <0xc8000200 0x200>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+                resets = <&tegra_car 9>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -613,6 +712,8 @@
                 reg = <0xc8000400 0x200>;
                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+                resets = <&tegra_car 69>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -621,6 +722,8 @@
                 reg = <0xc8000600 0x200>;
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+                resets = <&tegra_car 15>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad696e89f..e93fe45b7803 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -6,11 +6,16 @@
         model = "NVIDIA Tegra30 Beaver evaluation board";
         compatible = "nvidia,beaver", "nvidia,tegra30";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps65911@2d";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x7ff00000>;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 status = "okay";
                 pex-clk-supply = <&sys_3v3_pexs_reg>;
                 vdd-supply = <&ldo1_reg>;
@@ -31,8 +36,8 @@
                 };
         };
 
-        host1x {
-                hdmi {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&sys_3v3_reg>;
@@ -44,7 +49,7 @@
                 };
         };
 
-        pinmux {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -52,8 +57,8 @@
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins =   "sdmmc1_cmd_pz1",
@@ -62,14 +67,14 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins =   "sdmmc3_cmd_pa7",
@@ -78,15 +83,15 @@
                                                 "sdmmc3_dat2_pb5",
                                                 "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins =   "sdmmc4_clk_pcc4",
                                                 "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_dat0_paa0 {
                                 nvidia,pins =   "sdmmc4_dat0_paa0",
@@ -98,8 +103,8 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_fs_pa2 {
                                 nvidia,pins =   "dap2_fs_pa2",
@@ -107,18 +112,18 @@
                                                 "dap2_din_pa4",
                                                 "dap2_dout_pa5";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         pex_l1_prsnt_n_pdd4 {
                                 nvidia,pins =   "pex_l1_prsnt_n_pdd4",
                                                 "pex_l1_clkreq_n_pdd6";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                                 nvidia,pull-down-strength = <46>;
                                 nvidia,pull-up-strength = <42>;
                                 nvidia,slew-rate-rising = <1>;
@@ -159,7 +164,7 @@
                 status = "okay";
                 clock-frequency = <100000>;
 
-                rt5640: rt5640 {
+                rt5640: rt5640@1c {
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
@@ -168,19 +173,6 @@
                                 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
                 };
 
-                tps62361 {
-                        compatible = "ti,tps62361";
-                        reg = <0x60>;
-
-                        regulator-name = "tps62361-vout";
-                        regulator-min-microvolt = <500000>;
-                        regulator-max-microvolt = <1500000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        ti,vsel0-state-high;
-                        ti,vsel1-state-high;
-                };
-
                 pmic: tps65911@2d {
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
@@ -284,6 +276,19 @@
                                 };
                         };
                 };
+
+                tps62361@60 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
         };
 
         spi@7000da00 {
@@ -296,13 +301,7 @@
                 };
         };
 
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        pmc {
+        pmc@7000e400 {
                 status = "okay";
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -314,6 +313,12 @@
                 nvidia,sys-clock-req-active-high;
         };
 
+        ahub@70080000 {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000000 {
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -328,6 +333,15 @@
                 non-removable;
         };
 
+        usb@7d004000 {
+                status = "okay";
+        };
+
+        phy2: usb-phy@7d004000 {
+                vbus-supply = <&sys_3v3_reg>;
+                status = "okay";
+        };
+
         usb@7d008000 {
                 status = "okay";
         };
@@ -342,7 +356,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -350,6 +364,19 @@
                 };
         };
 
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                gpled1 {
+                        label = "LED1"; /* CR5A1 (blue) */
+                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+                };
+                gpled2 {
+                        label = "LED2"; /* CR4A2 (green) */
+                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -453,19 +480,6 @@
                 };
         };
 
-        gpio-leds {
-                compatible = "gpio-leds";
-
-                gpled1 {
-                        label = "LED1"; /* CR5A1 (blue) */
-                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
-                };
-                gpled2 {
-                        label = "LED2"; /* CR4A2 (green) */
-                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
-                };
-        };
-
         sound {
                 compatible = "nvidia,tegra-audio-rt5640-beaver",
                              "nvidia,tegra-audio-rt5640";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 1082c5ed90d1..c9bfedcca6ed 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -8,6 +8,13 @@
         model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
         compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
 
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                keep-power-in-suspend;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -83,12 +90,5 @@
                         gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
-
-        sdhci@78000400 {
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                keep-power-in-suspend;
-        };
 };
 
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index bf012bddaafb..fadf55e46b2b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -8,6 +8,13 @@
         model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
         compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
 
+        sdhci@78000400 {
+                status = "okay";
+                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                keep-power-in-suspend;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -95,11 +102,4 @@
                         gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
                 };
         };
-
-        sdhci@78000400 {
-                status = "okay";
-                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
-                bus-width = <4>;
-                keep-power-in-suspend;
-        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 5ea7dfa4d9fa..9104224124ee 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -27,11 +27,16 @@
         model = "NVIDIA Tegra30 Cardhu evaluation board";
         compatible = "nvidia,cardhu", "nvidia,tegra30";
 
+        aliases {
+                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc1 = "/rtc@7000e000";
+        };
+
         memory {
                 reg = <0x80000000 0x40000000>;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 status = "okay";
                 pex-clk-supply = <&pex_hvdd_3v3_reg>;
                 vdd-supply = <&ldo1_reg>;
@@ -51,7 +56,17 @@
                 };
         };
 
-        pinmux {
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+
+                                nvidia,panel = <&panel>;
+                        };
+                };
+        };
+
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
@@ -59,8 +74,8 @@
                         sdmmc1_clk_pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc1_cmd_pz1 {
                                 nvidia,pins =   "sdmmc1_cmd_pz1",
@@ -69,14 +84,14 @@
                                                 "sdmmc1_dat2_py5",
                                                 "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_clk_pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc3_cmd_pa7 {
                                 nvidia,pins =   "sdmmc3_cmd_pa7",
@@ -85,15 +100,15 @@
                                                 "sdmmc3_dat2_pb5",
                                                 "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_clk_pcc4 {
                                 nvidia,pins =   "sdmmc4_clk_pcc4",
                                                 "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdmmc4_dat0_paa0 {
                                 nvidia,pins =   "sdmmc4_dat0_paa0",
@@ -105,8 +120,8 @@
                                                 "sdmmc4_dat6_paa6",
                                                 "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         dap2_fs_pa2 {
                                 nvidia,pins =   "dap2_fs_pa2",
@@ -114,17 +129,17 @@
                                                 "dap2_din_pa4",
                                                 "dap2_dout_pa5";
                                 nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         sdio3 {
                                 nvidia,pins = "drive_sdio3";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                                 nvidia,pull-down-strength = <46>;
                                 nvidia,pull-up-strength = <42>;
-                                nvidia,slew-rate-rising = <1>;
-                                nvidia,slew-rate-falling = <1>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
                         };
                         uart3_txd_pw6 {
                                 nvidia,pins =   "uart3_txd_pw6",
@@ -132,8 +147,8 @@
                                                 "uart3_rts_n_pc0",
                                                 "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
@@ -147,7 +162,11 @@
                 status = "okay";
         };
 
-        i2c@7000c000 {
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        panelddc: i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
@@ -302,7 +321,7 @@
                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
                 };
 
-                tps62361 {
+                tps62361@60 {
                         compatible = "ti,tps62361";
                         reg = <0x60>;
 
@@ -326,13 +345,7 @@
                 };
         };
 
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        pmc {
+        pmc@7000e400 {
                 status = "okay";
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
@@ -344,6 +357,12 @@
                 nvidia,sys-clock-req-active-high;
         };
 
+        ahub@70080000 {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000000 {
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -367,12 +386,23 @@
                 status = "okay";
         };
 
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
         clocks {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg=<0>;
                         #clock-cells = <0>;
@@ -380,6 +410,16 @@
                 };
         };
 
+        panel: panel {
+                compatible = "chunghwa,claa101wb01", "simple-panel";
+                ddc-i2c-bus = <&panelddc>;
+
+                power-supply = <&vdd_pnl1_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
+
+                backlight = <&backlight>;
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2bd55cfd88ad..ed8e7700b46d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra30-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
@@ -16,7 +17,7 @@
                 serial4 = &uarte;
         };
 
-        pcie-controller {
+        pcie-controller@00003000 {
                 compatible = "nvidia,tegra30-pcie";
                 device_type = "pci";
                 reg = <0x00003000 0x00000800   /* PADS registers */
@@ -40,10 +41,13 @@
 
                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
                          <&tegra_car TEGRA30_CLK_AFI>,
-                         <&tegra_car TEGRA30_CLK_PCIEX>,
                          <&tegra_car TEGRA30_CLK_PLL_E>,
                          <&tegra_car TEGRA30_CLK_CML0>;
-                clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+                clock-names = "pex", "afi", "pll_e", "cml";
+                resets = <&tegra_car 70>,
+                         <&tegra_car 72>,
+                         <&tegra_car 74>;
+                reset-names = "pex", "afi", "pcie_x";
                 status = "disabled";
 
                 pci@1,0 {
@@ -86,59 +90,74 @@
                 };
         };
 
-        host1x {
+        host1x@50000000 {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+                resets = <&tegra_car 28>;
+                reset-names = "host1x";
 
                 #address-cells = <1>;
                 #size-cells = <1>;
 
                 ranges = <0x54000000 0x54000000 0x04000000>;
 
-                mpe {
+                mpe@54040000 {
                         compatible = "nvidia,tegra30-mpe";
                         reg = <0x54040000 0x00040000>;
                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
+                        resets = <&tegra_car 60>;
+                        reset-names = "mpe";
                 };
 
-                vi {
+                vi@54080000 {
                         compatible = "nvidia,tegra30-vi";
                         reg = <0x54080000 0x00040000>;
                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_VI>;
+                        resets = <&tegra_car 20>;
+                        reset-names = "vi";
                 };
 
-                epp {
+                epp@540c0000 {
                         compatible = "nvidia,tegra30-epp";
                         reg = <0x540c0000 0x00040000>;
                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
+                        resets = <&tegra_car 19>;
+                        reset-names = "epp";
                 };
 
-                isp {
+                isp@54100000 {
                         compatible = "nvidia,tegra30-isp";
                         reg = <0x54100000 0x00040000>;
                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
+                        resets = <&tegra_car 23>;
+                        reset-names = "isp";
                 };
 
-                gr2d {
+                gr2d@54140000 {
                         compatible = "nvidia,tegra30-gr2d";
                         reg = <0x54140000 0x00040000>;
                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        resets = <&tegra_car 21>;
+                        reset-names = "2d";
                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                 };
 
-                gr3d {
+                gr3d@54180000 {
                         compatible = "nvidia,tegra30-gr3d";
                         reg = <0x54180000 0x00040000>;
                         clocks = <&tegra_car TEGRA30_CLK_GR3D
                                   &tegra_car TEGRA30_CLK_GR3D2>;
                         clock-names = "3d", "3d2";
+                        resets = <&tegra_car 24>,
+                                 <&tegra_car 98>;
+                        reset-names = "3d", "3d2";
                 };
 
                 dc@54200000 {
@@ -147,7 +166,9 @@
                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
                                  <&tegra_car TEGRA30_CLK_PLL_P>;
-                        clock-names = "disp1", "parent";
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 27>;
+                        reset-names = "dc";
 
                         rgb {
                                 status = "disabled";
@@ -160,24 +181,28 @@
                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
                                  <&tegra_car TEGRA30_CLK_PLL_P>;
-                        clock-names = "disp2", "parent";
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 26>;
+                        reset-names = "dc";
 
                         rgb {
                                 status = "disabled";
                         };
                 };
 
-                hdmi {
+                hdmi@54280000 {
                         compatible = "nvidia,tegra30-hdmi";
                         reg = <0x54280000 0x00040000>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                         clock-names = "hdmi", "parent";
+                        resets = <&tegra_car 51>;
+                        reset-names = "hdmi";
                         status = "disabled";
                 };
 
-                tvo {
+                tvo@542c0000 {
                         compatible = "nvidia,tegra30-tvo";
                         reg = <0x542c0000 0x00040000>;
                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -185,10 +210,12 @@
                         status = "disabled";
                 };
 
-                dsi {
+                dsi@54300000 {
                         compatible = "nvidia,tegra30-dsi";
                         reg = <0x54300000 0x00040000>;
                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+                        resets = <&tegra_car 48>;
+                        reset-names = "dsi";
                         status = "disabled";
                 };
         };
@@ -201,7 +228,7 @@
                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
         };
 
-        intc: interrupt-controller {
+        intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0x50041000 0x1000
                        0x50040100 0x0100>;
@@ -209,7 +236,7 @@
                 #interrupt-cells = <3>;
         };
 
-        cache-controller {
+        cache-controller@50043000 {
                 compatible = "arm,pl310-cache";
                 reg = <0x50043000 0x1000>;
                 arm,data-latency = <6 6 2>;
@@ -230,13 +257,14 @@
                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
         };
 
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra30-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
+                #reset-cells = <1>;
         };
 
-        apbdma: dma {
+        apbdma: dma@6000a000 {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -272,14 +300,17 @@
                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+                resets = <&tegra_car 34>;
+                reset-names = "dma";
+                #dma-cells = <1>;
         };
 
-        ahb: ahb {
+        ahb: ahb@6000c004 {
                 compatible = "nvidia,tegra30-ahb";
                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
         };
 
-        gpio: gpio {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -296,7 +327,7 @@
                 interrupt-controller;
         };
 
-        pinmux: pinmux {
+        pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra30-pinmux";
                 reg = <0x70000868 0xd4    /* Pad control registers */
                        0x70003000 0x3e4>; /* Mux registers */
@@ -315,8 +346,11 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 8>;
                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+                resets = <&tegra_car 6>;
+                reset-names = "serial";
+                dmas = <&apbdma 8>, <&apbdma 8>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -325,8 +359,11 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 9>;
                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+                resets = <&tegra_car 7>;
+                reset-names = "serial";
+                dmas = <&apbdma 9>, <&apbdma 9>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -335,8 +372,11 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 10>;
                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+                resets = <&tegra_car 55>;
+                reset-names = "serial";
+                dmas = <&apbdma 10>, <&apbdma 10>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -345,8 +385,11 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 19>;
                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+                resets = <&tegra_car 65>;
+                reset-names = "serial";
+                dmas = <&apbdma 19>, <&apbdma 19>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -355,20 +398,25 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 20>;
                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+                resets = <&tegra_car 66>;
+                reset-names = "serial";
+                dmas = <&apbdma 20>, <&apbdma 20>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
-        pwm: pwm {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
+                resets = <&tegra_car 17>;
+                reset-names = "pwm";
                 status = "disabled";
         };
 
-        rtc {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -384,6 +432,10 @@
                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 12>;
+                reset-names = "i2c";
+                dmas = <&apbdma 21>, <&apbdma 21>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -396,6 +448,10 @@
                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 54>;
+                reset-names = "i2c";
+                dmas = <&apbdma 22>, <&apbdma 22>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -408,6 +464,10 @@
                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 67>;
+                reset-names = "i2c";
+                dmas = <&apbdma 23>, <&apbdma 23>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -419,7 +479,11 @@
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+                resets = <&tegra_car 103>;
+                reset-names = "i2c";
                 clock-names = "div-clk", "fast-clk";
+                dmas = <&apbdma 26>, <&apbdma 26>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -432,6 +496,10 @@
                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
+                resets = <&tegra_car 47>;
+                reset-names = "i2c";
+                dmas = <&apbdma 24>, <&apbdma 24>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -439,10 +507,13 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+                resets = <&tegra_car 41>;
+                reset-names = "spi";
+                dmas = <&apbdma 15>, <&apbdma 15>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -450,10 +521,13 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+                resets = <&tegra_car 44>;
+                reset-names = "spi";
+                dmas = <&apbdma 16>, <&apbdma 16>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -461,10 +535,13 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+                resets = <&tegra_car 46>;
+                reset-names = "spi";
+                dmas = <&apbdma 17>, <&apbdma 17>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -472,10 +549,13 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+                resets = <&tegra_car 68>;
+                reset-names = "spi";
+                dmas = <&apbdma 18>, <&apbdma 18>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -483,10 +563,13 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000dc00 0x200>;
                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+                resets = <&tegra_car 104>;
+                reset-names = "spi";
+                dmas = <&apbdma 27>, <&apbdma 27>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
@@ -494,29 +577,34 @@
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000de00 0x200>;
                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+                resets = <&tegra_car 106>;
+                reset-names = "spi";
+                dmas = <&apbdma 28>, <&apbdma 28>;
+                dma-names = "rx", "tx";
                 status = "disabled";
         };
 
-        kbc {
+        kbc@7000e200 {
                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
+                resets = <&tegra_car 36>;
+                reset-names = "kbc";
                 status = "disabled";
         };
 
-        pmc {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
-        memory-controller {
+        memory-controller@7000f000 {
                 compatible = "nvidia,tegra30-mc";
                 reg = <0x7000f000 0x010
                        0x7000f03c 0x1b4
@@ -525,7 +613,7 @@
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
-        iommu {
+        iommu@7000f010 {
                 compatible = "nvidia,tegra30-smmu";
                 reg = <0x7000f010 0x02c
                        0x7000f1f0 0x010
@@ -535,26 +623,34 @@
                 nvidia,ahb = <&ahb>;
         };
 
-        ahub {
+        ahub@70080000 {
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
                        0x70080200 0x100>;
                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-                nvidia,dma-request-selector = <&apbdma 1>;
                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
-                         <&tegra_car TEGRA30_CLK_APBIF>,
-                         <&tegra_car TEGRA30_CLK_I2S0>,
-                         <&tegra_car TEGRA30_CLK_I2S1>,
-                         <&tegra_car TEGRA30_CLK_I2S2>,
-                         <&tegra_car TEGRA30_CLK_I2S3>,
-                         <&tegra_car TEGRA30_CLK_I2S4>,
-                         <&tegra_car TEGRA30_CLK_DAM0>,
-                         <&tegra_car TEGRA30_CLK_DAM1>,
-                         <&tegra_car TEGRA30_CLK_DAM2>,
-                         <&tegra_car TEGRA30_CLK_SPDIF_IN>;
-                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                         <&tegra_car TEGRA30_CLK_APBIF>;
+                clock-names = "d_audio", "apbif";
+                resets = <&tegra_car 106>, /* d_audio */
+                         <&tegra_car 107>, /* apbif */
+                         <&tegra_car 30>,  /* i2s0 */
+                         <&tegra_car 11>,  /* i2s1 */
+                         <&tegra_car 18>,  /* i2s2 */
+                         <&tegra_car 101>, /* i2s3 */
+                         <&tegra_car 102>, /* i2s4 */
+                         <&tegra_car 108>, /* dam0 */
+                         <&tegra_car 109>, /* dam1 */
+                         <&tegra_car 110>, /* dam2 */
+                         <&tegra_car 10>;  /* spdif */
+                reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
-                              "spdif_in";
+                              "spdif";
+                dmas = <&apbdma 1>, <&apbdma 1>,
+                       <&apbdma 2>, <&apbdma 2>,
+                       <&apbdma 3>, <&apbdma 3>,
+                       <&apbdma 4>, <&apbdma 4>;
+                dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
+                            "rx3", "tx3";
                 ranges;
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -564,6 +660,8 @@
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+                        resets = <&tegra_car 30>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -572,6 +670,8 @@
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+                        resets = <&tegra_car 11>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -580,6 +680,8 @@
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+                        resets = <&tegra_car 18>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -588,6 +690,8 @@
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+                        resets = <&tegra_car 101>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
 
@@ -596,6 +700,8 @@
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+                        resets = <&tegra_car 102>;
+                        reset-names = "i2s";
                         status = "disabled";
                 };
         };
@@ -605,6 +711,8 @@
                 reg = <0x78000000 0x200>;
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+                resets = <&tegra_car 14>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -613,6 +721,8 @@
                 reg = <0x78000200 0x200>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+                resets = <&tegra_car 9>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -621,6 +731,8 @@
                 reg = <0x78000400 0x200>;
                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+                resets = <&tegra_car 69>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -629,6 +741,8 @@
                 reg = <0x78000600 0x200>;
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+                resets = <&tegra_car 15>;
+                reset-names = "sdhci";
                 status = "disabled";
         };
 
@@ -638,6 +752,8 @@
                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
+                resets = <&tegra_car 22>;
+                reset-names = "usb";
                 nvidia,needs-double-reset;
                 nvidia,phy = <&phy1>;
                 status = "disabled";
@@ -669,20 +785,33 @@
                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
                 reg = <0x7d004000 0x4000>;
                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                phy_type = "ulpi";
+                phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
+                resets = <&tegra_car 58>;
+                reset-names = "usb";
                 nvidia,phy = <&phy2>;
                 status = "disabled";
         };
 
         phy2: usb-phy@7d004000 {
                 compatible = "nvidia,tegra30-usb-phy";
-                reg = <0x7d004000 0x4000>;
-                phy_type = "ulpi";
+                reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
+                phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
                          <&tegra_car TEGRA30_CLK_PLL_U>,
-                         <&tegra_car TEGRA30_CLK_CDEV2>;
-                clock-names = "reg", "pll_u", "ulpi-link";
+                         <&tegra_car TEGRA30_CLK_USBD>;
+                clock-names = "reg", "pll_u", "utmi-pads";
+                nvidia,hssync-start-delay = <9>;
+                nvidia,idle-wait-delay = <17>;
+                nvidia,elastic-limit = <16>;
+                nvidia,term-range-adj = <6>;
+                nvidia,xcvr-setup = <51>;
+                nvidia.xcvr-setup-use-fuses;
+                nvidia,xcvr-lsfslew = <2>;
+                nvidia,xcvr-lsrslew = <2>;
+                nvidia,xcvr-hsslew = <32>;
+                nvidia,hssquelch-level = <2>;
+                nvidia,hsdiscon-level = <5>;
                 status = "disabled";
         };
 
@@ -692,6 +821,8 @@
                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
+                resets = <&tegra_car 59>;
+                reset-names = "usb";
                 nvidia,phy = <&phy3>;
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index e7f73b2e4550..8b67b19392ec 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,25 @@
 / {
         compatible = "xlnx,zynq-7000";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        clocks = <&clkc 3>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        clocks = <&clkc 3>;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a9-pmu";
                 interrupts = <0 5 4>, <0 6 4>;
@@ -65,6 +84,44 @@
                         interrupts = <0 50 4>;
                 };
 
+                gem0: ethernet@e000b000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000b000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 22 4>;
+                        clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
+                gem1: ethernet@e000c000 {
+                        compatible = "cdns,gem";
+                        reg = <0xe000c000 0x4000>;
+                        status = "disabled";
+                        interrupts = <0 45 4>;
+                        clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+                        clock-names = "pclk", "hclk", "tx_clk";
+                };
+
+                sdhci0: ps7-sdhci@e0100000 {
+                        compatible = "arasan,sdhci-8.9a";
+                        status = "disabled";
+                        clock-names = "clk_xin", "clk_ahb";
+                        clocks = <&clkc 21>, <&clkc 32>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <0 24 4>;
+                        reg = <0xe0100000 0x1000>;
+                } ;
+
+                sdhci1: ps7-sdhci@e0101000 {
+                        compatible = "arasan,sdhci-8.9a";
+                        status = "disabled";
+                        clock-names = "clk_xin", "clk_ahb";
+                        clocks = <&clkc 22>, <&clkc 33>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <0 47 4>;
+                        reg = <0xe0101000 0x1000>;
+                } ;
+
                 slcr: slcr@f8000000 {
                         compatible = "xlnx,zynq-slcr";
                         reg = <0xF8000000 0x1000>;
@@ -106,7 +163,6 @@
                         compatible = "cdns,ttc";
                         clocks = <&clkc 6>;
                         reg = <0xF8001000 0x1000>;
-                        clock-ranges;
                 };
 
                 ttc1: ttc1@f8002000 {
@@ -115,7 +171,6 @@
                         compatible = "cdns,ttc";
                         clocks = <&clkc 6>;
                         reg = <0xF8002000 0x1000>;
-                        clock-ranges;
                 };
                 scutimer: scutimer@f8f00600 {
                         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 21aea99a067b..c913f77a21eb 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -29,6 +29,15 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 79009e0b74b9..88f62c50382e 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -30,6 +30,15 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index d6acf2b1cdf4..82d7ef1a9a9c 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -30,6 +30,15 @@
 
 };
 
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii";
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
 &uart1 {
         status = "okay";
 };
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 001f4913799c..5114b68e99d5 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -257,7 +257,7 @@ static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t s
  */
 static int it8152_pci_platform_notify(struct device *dev)
 {
-        if (dev->bus == &pci_bus_type) {
+        if (dev_is_pci(dev)) {
                 if (dev->dma_mask)
                         *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
                 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
@@ -268,7 +268,7 @@ static int it8152_pci_platform_notify(struct device *dev)
 
 static int it8152_pci_platform_notify_remove(struct device *dev)
 {
-        if (dev->bus == &pci_bus_type)
+        if (dev_is_pci(dev))
                 dmabounce_unregister_dev(dev);
 
         return 0;
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index 26020a03f659..1e361abc29eb 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -35,8 +35,7 @@ void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
         unsigned long *poke = &mcpm_entry_early_pokes[cluster][cpu][0];
         poke[0] = poke_phys_addr;
         poke[1] = poke_val;
-        __cpuc_flush_dcache_area((void *)poke, 8);
-        outer_clean_range(__pa(poke), __pa(poke + 2));
+        __sync_cache_range_w(poke, 2 * sizeof(*poke));
 }
 
 static const struct mcpm_platform_ops *platform_ops;
@@ -167,7 +166,7 @@ void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster)
         dmb();
         mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN;
         sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu);
-        dsb_sev();
+        sev();
 }
 
 /*
@@ -183,7 +182,7 @@ void __mcpm_outbound_leave_critical(unsigned int cluster, int state)
         dmb();
         mcpm_sync.clusters[cluster].cluster = state;
         sync_cache_w(&mcpm_sync.clusters[cluster].cluster);
-        dsb_sev();
+        sev();
 }
 
 /*
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index ce922d0ea7aa..53c6a26b633d 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -66,7 +66,7 @@ static long __init sp804_get_clock_rate(struct clk *clk)
 
 static void __iomem *sched_clock_base;
 
-static u32 sp804_read(void)
+static u64 notrace sp804_read(void)
 {
         return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
 }
@@ -104,7 +104,7 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
 
         if (use_sched_clock) {
                 sched_clock_base = base;
-                setup_sched_clock(sp804_read, 32, rate);
+                sched_clock_register(sp804_read, 32, rate);
         }
 }
 
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index 1ce39940795d..cb26c62dc722 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A73A4=y
 CONFIG_MACH_APE6EVM=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index fae939d3d7f0..9287a62de830 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
@@ -105,6 +105,7 @@ CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FB_SH_MOBILE_HDMI=y
 CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_LOGO=y
@@ -130,6 +131,8 @@ CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_PWM=y
+CONFIG_PWM_RENESAS_TPU=y
 # CONFIG_DNOTIFY is not set
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 690e89273230..0b4e9b5210d8 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -22,7 +22,6 @@ CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
 CONFIG_MACH_AT91RM9200_DT=y
 CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 75502c4d222c..bf057719dab0 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -31,7 +31,6 @@ CONFIG_MACH_YL9200=y
 CONFIG_MACH_CPUAT91=y
 CONFIG_MACH_ECO920=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=100
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index 69b6928d3d9d..2cd832918e9c 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y
 CONFIG_MACH_CAM60=y
 CONFIG_MACH_SAM9_L9260=y
 CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_AT91SAM9G20EK=y
@@ -28,7 +27,6 @@ CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
 CONFIG_MACH_SNAPPER_9260=y
 CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
index 9d35cd81c611..f80e993b04ce 100644
--- a/arch/arm/configs/at91sam9261_9g10_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
 CONFIG_MACH_AT91SAM9G10EK=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 08166cd4e7d6..e181a50fd65a 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
 CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 7cf87856d63c..7b6f131cecd6 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -13,7 +13,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9RL=y
 CONFIG_MACH_AT91SAM9RLEK=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 34e9780e63ba..f43392dc2dcf 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -44,17 +44,26 @@ CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_NETWORK_SECMARK=y
-# CONFIG_WIRELESS is not set
+CONFIG_NETFILTER=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_ZD1211RW=y
+CONFIG_INPUT_EVDEV=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
@@ -71,15 +80,13 @@ CONFIG_FB=y
 CONFIG_FB_SIMPLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM2835=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_ONESHOT=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -88,6 +95,8 @@ CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_STAGING=y
+CONFIG_USB_DWC2=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
@@ -109,20 +118,20 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_UNUSED_SYMBOLS=y
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_LOCKUP_DETECTOR=y
 CONFIG_SCHED_TRACER=y
 CONFIG_STACK_TRACER=y
 CONFIG_FUNCTION_PROFILER=y
-CONFIG_DYNAMIC_DEBUG=y
+CONFIG_TEST_KSTRTOX=y
 CONFIG_KGDB=y
 CONFIG_KGDB_KDB=y
-CONFIG_TEST_KSTRTOX=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 287ac1d7aac7..2519d6de0640 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -29,11 +29,9 @@ CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 # CONFIG_COMPACTION is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
 CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
@@ -120,9 +118,14 @@ CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
 # CONFIG_FTRACE is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_CCITT=y
 CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_XZ_DEC=y
 CONFIG_AVERAGE=y
+CONFIG_PINCTRL_CAPRI=y
+CONFIG_WATCHDOG=y
+CONFIG_BCM_KONA_WDT=y
+CONFIG_BCM_KONA_WDT_DEBUG=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index b38cd107f82d..80cff50beb34 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7778=y
 CONFIG_MACH_BOCKW=y
 CONFIG_MEMORY_START=0x60000000
@@ -27,12 +27,12 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
-CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"
-CONFIG_CMDLINE_FORCE=y
+CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
@@ -44,8 +44,6 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -82,6 +80,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HWMON is not set
 CONFIG_I2C=y
 CONFIG_I2C_RCAR=y
+CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -108,11 +107,12 @@ CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RX8581=y
+CONFIG_DMADEVICES=y
+CONFIG_RCAR_HPB_DMAE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig
new file mode 100644
index 000000000000..f59fffb3d0c6
--- /dev/null
+++ b/arch/arm/configs/efm32_defconfig
@@ -0,0 +1,102 @@
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=12
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_UID16 is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MMU is not set
+CONFIG_ARCH_EFM32=y
+# CONFIG_KUSER_HELPERS is not set
+CONFIG_SET_MEM_PARAM=y
+CONFIG_DRAM_BASE=0x88000000
+CONFIG_DRAM_SIZE=0x00400000
+CONFIG_FLASH_MEM_BASE=0x8c000000
+CONFIG_FLASH_SIZE=0x01000000
+CONFIG_PREEMPT=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_XIP_KERNEL=y
+CONFIG_XIP_PHYS_ADDR=0x8c000000
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_COREDUMP is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK_RO=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_UCLINUX=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+CONFIG_KS8851=y
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_EFM32_UART=y
+CONFIG_SERIAL_EFM32_UART_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_EFM32=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_MTD=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index ad7dfbbafa45..dbe1f1c47bb0 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -13,7 +13,7 @@ CONFIG_S3C24XX_PWM=y
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_MACH_EXYNOS4_DT=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
+CONFIG_NR_CPUS=8
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -79,6 +79,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8997=y
 CONFIG_REGULATOR_MAX77686=y
+CONFIG_REGULATOR_S2MPS11=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_FB=y
diff --git a/arch/arm/configs/genmai_defconfig b/arch/arm/configs/genmai_defconfig
new file mode 100644
index 000000000000..aa0b704f48af
--- /dev/null
+++ b/arch/arm/configs/genmai_defconfig
@@ -0,0 +1,116 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE_LEGACY=y
+CONFIG_ARCH_R7S72100=y
+CONFIG_MACH_GENMAI=y
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_SH_ETH=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=10
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_DRM=y
+CONFIG_DRM_RCAR_DU=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hi3xxx_defconfig
new file mode 100644
index 000000000000..f186bdfa2369
--- /dev/null
+++ b/arch/arm/configs/hi3xxx_defconfig
@@ -0,0 +1,56 @@
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_LZMA=y
+CONFIG_ARCH_HI3xxx=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_DRM=y
+CONFIG_FB_SIMPLE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_PL330_DMA=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOCKUP_DETECTOR=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e958ebe79779..6309ee52ccfc 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -91,6 +91,7 @@ CONFIG_SMSC911X=y
 CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_IMX=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
@@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y
 CONFIG_MFD_MC13XXX_SPI=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8d0c5a018ed7..53e82c2523eb 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y
 CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MACH_IMX31_DT=y
+CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_SOC_IMX50=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
@@ -41,7 +43,7 @@ CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 # CONFIG_SCSI_PROC_FS is not set
@@ -118,6 +119,7 @@ CONFIG_SMC91X=y
 CONFIG_SMC911X=y
 CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_AT803X_PHY=y
 CONFIG_BRCMFMAC=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
@@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_EGALAX=y
 CONFIG_TOUCHSCREEN_MC13783=y
+CONFIG_TOUCHSCREEN_TSC2007=y
+CONFIG_TOUCHSCREEN_STMPE=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MMA8450=y
 CONFIG_SERIO_SERPORT=m
@@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y
 CONFIG_MFD_DA9052_I2C=y
 CONFIG_MFD_MC13XXX_SPI=y
 CONFIG_MFD_MC13XXX_I2C=y
+CONFIG_MFD_STMPE=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_ANATOP=y
 CONFIG_REGULATOR_DA9052=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
+CONFIG_REGULATOR_PFUZE100=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
 CONFIG_VIDEO_MX3=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 9943e5da74f1..4582e160feab 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -115,6 +115,8 @@ CONFIG_MTD_UBI=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -129,10 +131,25 @@ CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DEBUG=y
+CONFIG_USB_DWC3_VERBOSE=y
+CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DMADEVICES=y
+CONFIG_TI_EDMA=y
 CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_MEMORY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_WBUF_VERIFY=y
@@ -144,6 +161,8 @@ CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 CONFIG_NFSD_V3_ACL=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 0ae0eaebf6b2..2e762d94e94b 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -27,6 +27,7 @@ CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CPU_FREQ=y
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 825c16dee8a0..e248f49d5549 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
 # CONFIG_SWP_EMULATE is not set
@@ -29,7 +29,29 @@ CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_SH_ETH=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -45,10 +67,11 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 CONFIG_CONFIGFS_FS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 # CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 6c37f4a98eb8..e42ce3756af3 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_MACH_KZM9D=y
 CONFIG_MEMORY_START=0x40000000
@@ -32,6 +32,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 1ad028023a64..9934dbc23d64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KZM9G=y
 CONFIG_MEMORY_START=0x41000000
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 35bff5e0d57a..883443f8f4f3 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -12,7 +12,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_MACH_LAGER=y
 # CONFIG_SH_TIMER_TMU is not set
@@ -80,7 +80,7 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
-CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_RCAR=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
@@ -89,6 +89,7 @@ CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_DRM=y
 CONFIG_DRM_RCAR_DU=y
 # CONFIG_USB_SUPPORT is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 9fb11895b2e2..a61e1653fc5e 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_SH7372=y
 CONFIG_MACH_MACKEREL=y
 CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 5cc6360340b1..f21bd405cc2a 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
 CONFIG_MEMORY_START=0x60000000
@@ -30,12 +30,12 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
-CONFIG_CMDLINE_FORCE=y
+CONFIG_VFP=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
@@ -43,8 +43,6 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
@@ -61,7 +59,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_MICREL is not set
 # CONFIG_NET_VENDOR_NATSEMI is not set
 # CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC911X=y
 CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
@@ -106,11 +103,12 @@ CONFIG_USB_STORAGE=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_DMADEVICES=y
+CONFIG_RCAR_HPB_DMAE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
new file mode 100644
index 000000000000..a3cb76cfb828
--- /dev/null
+++ b/arch/arm/configs/moxart_defconfig
@@ -0,0 +1,149 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_MULTI_V4T=y
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_ARCH_MOXART=y
+CONFIG_MACH_UC7112LX=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETCONSOLE_DYNAMIC=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_ARM_MOXART_ETHER=y
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_MDIO_MOXART=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MOXART=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_MOXART_WDT=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI_MOXART=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MOXART=y
+CONFIG_DMADEVICES=y
+CONFIG_MOXART_DMA=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT3_FS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_PROVE_LOCKING=y
+CONFIG_DMA_API_DEBUG=y
+CONFIG_KGDB=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x98200000
+CONFIG_DEBUG_UART_VIRT=0xf9820000
+CONFIG_EARLY_PRINTK=y
+CONFIG_KEYS=y
+CONFIG_CRC32_BIT=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index 690b5f9c7462..c5858b9eb516 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -17,9 +17,10 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSM_DT=y
 CONFIG_ARCH_MSM8X60=y
 CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -29,7 +30,6 @@ CONFIG_CLEANCACHE=y
 CONFIG_CC_STACKPROTECTOR=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -62,7 +62,6 @@ CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_PHYLIB=y
 CONFIG_SLIP=y
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_MODE_SLIP6=y
@@ -81,13 +80,15 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
-CONFIG_SSBI=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
 CONFIG_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
@@ -101,7 +102,6 @@ CONFIG_SND_DYNAMIC_MINORS=y
 CONFIG_SND_SOC=y
 CONFIG_HID_BATTERY_STRENGTH=y
 CONFIG_USB=y
-CONFIG_USB_PHY=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
@@ -114,6 +114,10 @@ CONFIG_USB_GADGET_VBUS_DRAW=500
 CONFIG_NEW_LEDS=y
 CONFIG_RTC_CLASS=y
 CONFIG_STAGING=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8660=y
+CONFIG_MSM_MMCC_8960=y
+CONFIG_MSM_MMCC_8974=y
 CONFIG_MSM_IOMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
@@ -128,10 +132,10 @@ CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_CIFS=y
 CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_LOCKUP_DETECTOR=y
 # CONFIG_DETECT_HUNG_TASK is not set
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DYNAMIC_DEBUG=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c1df4e9db140..845bc745706b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1,14 +1,23 @@
+CONFIG_SYSVIPC=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BERLIN=y
+CONFIG_MACH_BERLIN_BG2=y
+CONFIG_MACH_BERLIN_BG2CD=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX51_DT=y
@@ -34,7 +43,7 @@ CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
-CONFIG_TEGRA_PCI=y
+CONFIG_ARCH_TEGRA_124_SOC=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
@@ -45,19 +54,55 @@ CONFIG_ARCH_VEXPRESS_CA9X4=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
+CONFIG_TRUSTED_FOUNDATIONS=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_PCI_TEGRA=y
 CONFIG_SMP=y
 CONFIG_HIGHPTE=y
+CONFIG_CMA=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
 CONFIG_OMAP_OCP2SCP=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_ICS932S401=y
+CONFIG_APDS9802ALS=y
+CONFIG_ISL29003=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_SCSI_MULTI_LUN=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_SATA_HIGHBANK=y
@@ -65,12 +110,30 @@ CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_MVNETA=y
 CONFIG_KS8851=y
+CONFIG_R8169=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
-CONFIG_MDIO_SUN4I=y
 CONFIG_TI_CPSW=y
+CONFIG_AT803X_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_BRCMFMAC=m
+CONFIG_RT2X00=m
+CONFIG_RT2800USB=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_SPEAR=y
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MPU3050=y
 CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -91,30 +154,83 @@ CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
 CONFIG_SERIAL_FSL_LPUART=y
 CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_ST_ASC=y
+CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_MV64XXX=y
 CONFIG_I2C_SIRF=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
+CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_TEGRA114=y
+CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
-CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_PALMAS=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TWL4030=y
-CONFIG_REGULATOR_GPIO=y
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_TPS65090=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_SENSORS_LM90=y
+CONFIG_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_SPI=y
+CONFIG_MFD_MAX8907=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_AB8500=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_PALMAS=y
 CONFIG_REGULATOR_TPS51632=y
 CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
 CONFIG_REGULATOR_VEXPRESS=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_DRM=y
-CONFIG_TEGRA_HOST1X=y
 CONFIG_DRM_TEGRA=y
+CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FB_WM8505=y
 CONFIG_FB_SIMPLE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_RT5640=y
+CONFIG_SND_SOC_TEGRA_WM8753=y
+CONFIG_SND_SOC_TEGRA_WM8903=y
+CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_SND_SOC_TEGRA_ALC5632=y
+CONFIG_SND_SOC_TEGRA_MAX98090=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
@@ -125,8 +241,6 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_AB8500_USB=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_OMAP_USB2=y
 CONFIG_OMAP_USB3=y
 CONFIG_SAMSUNG_USB2PHY=y
 CONFIG_SAMSUNG_USB3PHY=y
@@ -137,24 +251,32 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_MMC_SDHCI_SPEAR=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_MVSDIO=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
 CONFIG_EDAC_HIGHBANK_L2=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
+CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_DRV_TPS6586X=y
+CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_VT8500=y
+CONFIG_RTC_DRV_MV=y
 CONFIG_RTC_DRV_TEGRA=y
 CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
+CONFIG_MV_XOR=y
 CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STE_DMA40=y
 CONFIG_SIRF_DMA=y
@@ -164,15 +286,34 @@ CONFIG_IMX_SDMA=y
 CONFIG_IMX_DMA=y
 CONFIG_MXS_DMA=y
 CONFIG_DMA_OMAP=y
+CONFIG_STAGING=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_SENSORS_ISL29028=y
+CONFIG_MFD_NVEC=y
+CONFIG_KEYBOARD_NVEC=y
+CONFIG_SERIO_NVEC_PS2=y
+CONFIG_NVEC_POWER=y
+CONFIG_TEGRA_IOMMU_GART=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_AK8975=y
 CONFIG_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_PWM_VT8500=y
+CONFIG_OMAP_USB2=y
 CONFIG_EXT4_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
 CONFIG_LOCKUP_DETECTOR=y
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 594d706b641f..0f4511d2849f 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -55,6 +55,8 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PXA3xx=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
@@ -69,6 +71,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index bfa80a11e8c7..3a0b53d225e7 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -208,6 +208,8 @@ CONFIG_SND_DEBUG=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
 CONFIG_SND_OMAP_SOC=m
+CONFIG_SND_AM33XX_SOC_EVM=m
+CONFIG_SND_DAVINCI_SOC=m
 CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
 CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
 CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
@@ -222,6 +224,7 @@ CONFIG_USB_TEST=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_OMAP_USB2=y
 CONFIG_OMAP_USB3=y
+CONFIG_AM335X_PHY_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index f6e78f83c3c3..dc3881e07630 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_SOC_SAM_V7=y
 CONFIG_SOC_SAMA5D3=y
 CONFIG_MACH_SAMA5_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_UACCESS_WITH_MEMCPY=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 4934295bb4f0..00fe9e9710fd 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -29,6 +29,7 @@ CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
 CONFIG_ARCH_TEGRA_124_SOC=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_TRUSTED_FOUNDATIONS=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_TEGRA=y
@@ -36,8 +37,8 @@ CONFIG_PCIEPORTBUS=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
+CONFIG_CMA=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_KEXEC=y
@@ -63,7 +64,6 @@ CONFIG_INET_ESP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_OPTIMISTIC_DAD=y
 CONFIG_INET6_AH=y
@@ -85,7 +85,6 @@ CONFIG_RFKILL_GPIO=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_CMA=y
 CONFIG_DMA_CMA=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
@@ -114,6 +113,7 @@ CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -125,13 +125,13 @@ CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
+CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_PALMAS=y
@@ -143,6 +143,9 @@ CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_SPI=y
 CONFIG_MFD_MAX8907=y
 CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65090=y
@@ -151,6 +154,7 @@ CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_PALMAS=y
@@ -164,8 +168,8 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_DRM=y
-CONFIG_TEGRA_HOST1X=y
 CONFIG_DRM_TEGRA=y
+CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -187,6 +191,7 @@ CONFIG_SND_SOC_TEGRA_WM8753=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
 CONFIG_SND_SOC_TEGRA_ALC5632=y
+CONFIG_SND_SOC_TEGRA_MAX98090=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
@@ -199,10 +204,7 @@ CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_ONESHOT=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -211,6 +213,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TPS6586X=y
@@ -227,7 +230,6 @@ CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
 CONFIG_NVEC_POWER=y
 CONFIG_NVEC_PAZ00=y
-CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
@@ -256,16 +258,16 @@ CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SLAB=y
+CONFIG_DEBUG_VM=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_SLAB=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index c6ebc184bf68..65f77885c167 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -119,6 +119,7 @@ CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 2ba9e63d0f17..073541a50e23 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -1,5 +1,3 @@
-CONFIG_ARCH_VERSATILE=y
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -7,15 +5,16 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_VERSATILE=y
 CONFIG_MACH_VERSATILE_AB=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="root=1f03 mem=32M"
 CONFIG_FPE_NWFPE=y
 CONFIG_VFP=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -26,9 +25,7 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -37,10 +34,10 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_EEPROM_LEGACY=m
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
@@ -48,15 +45,14 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_ACORN_8x8=y
 CONFIG_SOUND=y
 CONFIG_SND=m
 CONFIG_SND_MIXER_OSS=m
@@ -64,6 +60,9 @@ CONFIG_SND_PCM_OSS=m
 CONFIG_SND_ARMAACI=m
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_EXT2_FS=y
 CONFIG_VFAT_FS=m
 CONFIG_JFFS2_FS=y
@@ -71,15 +70,14 @@ CONFIG_CRAMFS=y
 CONFIG_MINIX_FS=y
 CONFIG_ROMFS_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
+CONFIG_FONTS=y
+CONFIG_FONT_ACORN_8x8=y
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
new file mode 100644
index 000000000000..bb00ccf00d66
--- /dev/null
+++ b/arch/arm/firmware/Kconfig
@@ -0,0 +1,28 @@
+config ARCH_SUPPORTS_FIRMWARE
+        bool
+
+config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        bool
+        select ARCH_SUPPORTS_FIRMWARE
+
+menu "Firmware options"
+        depends on ARCH_SUPPORTS_FIRMWARE
+
+config TRUSTED_FOUNDATIONS
+        bool "Trusted Foundations secure monitor support"
+        depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        help
+          Some devices (including most Tegra-based consumer devices on the
+          market) are booted with the Trusted Foundations secure monitor
+          active, requiring some core operations to be performed by the secure
+          monitor instead of the kernel.
+
+          This option allows the kernel to invoke the secure monitor whenever
+          required on devices using Trusted Foundations. See
+          arch/arm/include/asm/trusted_foundations.h or the
+          tl,trusted-foundations device tree binding documentation for details
+          on how to use it.
+
+          Say n if you don't know what this is about.
+
+endmenu
diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile
new file mode 100644
index 000000000000..a71f16536b6c
--- /dev/null
+++ b/arch/arm/firmware/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TRUSTED_FOUNDATIONS)       += trusted_foundations.o
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
new file mode 100644
index 000000000000..ef1e3d8f4af0
--- /dev/null
+++ b/arch/arm/firmware/trusted_foundations.c
@@ -0,0 +1,81 @@
+/*
+ * Trusted Foundations support for ARM CPUs
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <asm/firmware.h>
+#include <asm/trusted_foundations.h>
+
+#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
+
+static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
+{
+        asm volatile(
+                ".arch_extension        sec\n\t"
+                "stmfd  sp!, {r4 - r11, lr}\n\t"
+                __asmeq("%0", "r0")
+                __asmeq("%1", "r1")
+                __asmeq("%2", "r2")
+                "mov    r3, #0\n\t"
+                "mov    r4, #0\n\t"
+                "smc    #0\n\t"
+                "ldmfd  sp!, {r4 - r11, pc}"
+                :
+                : "r" (type), "r" (arg1), "r" (arg2)
+                : "memory");
+}
+
+static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
+{
+        tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
+
+        return 0;
+}
+
+static const struct firmware_ops trusted_foundations_ops = {
+        .set_cpu_boot_addr = tf_set_cpu_boot_addr,
+};
+
+void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
+{
+        /*
+         * we are not using version information for now since currently
+         * supported SMCs are compatible with all TF releases
+         */
+        register_firmware_ops(&trusted_foundations_ops);
+}
+
+void of_register_trusted_foundations(void)
+{
+        struct device_node *node;
+        struct trusted_foundations_platform_data pdata;
+        int err;
+
+        node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
+        if (!node)
+                return;
+
+        err = of_property_read_u32(node, "tlm,version-major",
+                                   &pdata.version_major);
+        if (err != 0)
+                panic("Trusted Foundation: missing version-major property\n");
+        err = of_property_read_u32(node, "tlm,version-minor",
+                                   &pdata.version_minor);
+        if (err != 0)
+                panic("Trusted Foundation: missing version-minor property\n");
+        register_trusted_foundations(&pdata);
+}
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index c38b58c80202..3278afe2c3ab 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -34,3 +34,4 @@ generic-y += timex.h
 generic-y += trace_clock.h
 generic-y += unaligned.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index e691ec91e4d3..b2e298a90d76 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -254,25 +254,59 @@ static inline int constant_fls(int x)
 }
 
 /*
- * On ARMv5 and above those functions can be implemented around
- * the clz instruction for much better code efficiency.
+ * On ARMv5 and above those functions can be implemented around the
+ * clz instruction for much better code efficiency.  __clz returns
+ * the number of leading zeros, zero input will return 32, and
+ * 0x80000000 will return 0.
  */
+static inline unsigned int __clz(unsigned int x)
+{
+        unsigned int ret;
+
+        asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
 
+        return ret;
+}
+
+/*
+ * fls() returns zero if the input is zero, otherwise returns the bit
+ * position of the last set bit, where the LSB is 1 and MSB is 32.
+ */
 static inline int fls(int x)
 {
-        int ret;
-
         if (__builtin_constant_p(x))
                return constant_fls(x);
 
-        asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
-        ret = 32 - ret;
-        return ret;
+        return 32 - __clz(x);
+}
+
+/*
+ * __fls() returns the bit position of the last bit set, where the
+ * LSB is 0 and MSB is 31.  Zero input is undefined.
+ */
+static inline unsigned long __fls(unsigned long x)
+{
+        return fls(x) - 1;
+}
+
+/*
+ * ffs() returns zero if the input was zero, otherwise returns the bit
+ * position of the first set bit, where the LSB is 1 and MSB is 32.
+ */
+static inline int ffs(int x)
+{
+        return fls(x & -x);
+}
+
+/*
+ * __ffs() returns the bit position of the first bit set, where the
+ * LSB is 0 and MSB is 31.  Zero input is undefined.
+ */
+static inline unsigned long __ffs(unsigned long x)
+{
+        return ffs(x) - 1;
 }
 
-#define __fls(x) (fls(x) - 1)
-#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
-#define __ffs(x) (ffs(x) - 1)
 #define ffz(x) __ffs( ~(x) )
 
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index ee753f1749cd..e9a49fe0284e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -481,4 +481,9 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
         : : : "r0","r1","r2","r3","r4","r5","r6","r7", \
               "r9","r10","lr","memory" )
 
+int set_memory_ro(unsigned long addr, int numpages);
+int set_memory_rw(unsigned long addr, int numpages);
+int set_memory_x(unsigned long addr, int numpages);
+int set_memory_nx(unsigned long addr, int numpages);
+
 #endif
diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h
index 6dcc16430868..523315115478 100644
--- a/arch/arm/include/asm/checksum.h
+++ b/arch/arm/include/asm/checksum.h
@@ -87,19 +87,33 @@ static inline __wsum
 csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
                    unsigned short proto, __wsum sum)
 {
-        __asm__(
-        "adds   %0, %1, %2              @ csum_tcpudp_nofold    \n\
-        adcs    %0, %0, %3                                      \n"
+        u32 lenprot = len | proto << 16;
+        if (__builtin_constant_p(sum) && sum == 0) {
+                __asm__(
+                "adds   %0, %1, %2      @ csum_tcpudp_nofold0   \n\t"
 #ifdef __ARMEB__
-        "adcs   %0, %0, %4                                      \n"
+                "adcs   %0, %0, %3                              \n\t"
 #else
-        "adcs   %0, %0, %4, lsl #8                              \n"
+                "adcs   %0, %0, %3, ror #8                      \n\t"
 #endif
-        "adcs   %0, %0, %5                                      \n\
-        adc     %0, %0, #0"
-        : "=&r"(sum)
-        : "r" (sum), "r" (daddr), "r" (saddr), "r" (len), "Ir" (htons(proto))
-        : "cc");
+                "adc    %0, %0, #0"
+                : "=&r" (sum)
+                : "r" (daddr), "r" (saddr), "r" (lenprot)
+                : "cc");
+        } else {
+                __asm__(
+                "adds   %0, %1, %2      @ csum_tcpudp_nofold    \n\t"
+                "adcs   %0, %0, %3                              \n\t"
+#ifdef __ARMEB__
+                "adcs   %0, %0, %4                              \n\t"
+#else
+                "adcs   %0, %0, %4, ror #8                      \n\t"
+#endif
+                "adc    %0, %0, #0"
+                : "=&r"(sum)
+                : "r" (sum), "r" (daddr), "r" (saddr), "r" (lenprot)
+                : "cc");
+        }
         return sum;
 }       
 /*
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 80751c15c300..4e8a4b27d7c7 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -14,12 +14,14 @@
 
 #include <linux/slab.h>
 
+#ifndef CONFIG_COMMON_CLK
 #ifdef CONFIG_HAVE_MACH_CLKDEV
 #include <mach/clkdev.h>
 #else
 #define __clk_get(clk)  ({ 1; })
 #define __clk_put(clk)  do { } while (0)
 #endif
+#endif
 
 static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
 {
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 58b8c6a0ab1f..99084431d6ae 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -8,8 +8,8 @@
 #define MAX_DMA_ADDRESS 0xffffffffUL
 #else
 #define MAX_DMA_ADDRESS ({ \
-        extern unsigned long arm_dma_zone_size; \
-        arm_dma_zone_size ? \
+        extern phys_addr_t arm_dma_zone_size; \
+        arm_dma_zone_size && arm_dma_zone_size < (0x10000000 - PAGE_OFFSET) ? \
                 (PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
 #endif
 
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b5bfa2..6795ff743b3d 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
         unsigned long prefetch_ctrl;
         unsigned long pwr_ctrl;
         unsigned long ctrl;
+        unsigned long aux2_ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index fbeb39c869e9..8aa4cca74501 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -38,6 +38,12 @@
 #define isa_bus_to_virt phys_to_virt
 
 /*
+ * Atomic MMIO-wide IO modify
+ */
+extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
+extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
+
+/*
  * Generic IO read/write.  These perform native-endian accesses.  Note
  * that some architectures will want to re-define __raw_{read,write}w.
  */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 8a6f6db14ee4..098f7dd6d564 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -225,4 +225,7 @@ static inline int kvm_arch_dev_ioctl_check_extension(long ext)
 int kvm_perf_init(void);
 int kvm_perf_teardown(void);
 
+u64 kvm_arm_timer_get_reg(struct kvm_vcpu *, u64 regid);
+int kvm_arm_timer_set_reg(struct kvm_vcpu *, u64 regid, u64 value);
+
 #endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 77de4a41cc50..2d122adcdb22 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -140,6 +140,7 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
 }
 
 #define kvm_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
+#define kvm_virt_to_phys(x)             virt_to_idmap((unsigned long)(x))
 
 #endif  /* !__ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 2fe141fcc8d6..f98c7f32c9c8 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -22,18 +22,21 @@ struct map_desc {
 };
 
 /* types 0-3 are defined in asm/io.h */
-#define MT_UNCACHED             4
-#define MT_CACHECLEAN           5
-#define MT_MINICLEAN            6
-#define MT_LOW_VECTORS          7
-#define MT_HIGH_VECTORS         8
-#define MT_MEMORY               9
-#define MT_ROM                  10
-#define MT_MEMORY_NONCACHED     11
-#define MT_MEMORY_DTCM          12
-#define MT_MEMORY_ITCM          13
-#define MT_MEMORY_SO            14
-#define MT_MEMORY_DMA_READY     15
+enum {
+        MT_UNCACHED = 4,
+        MT_CACHECLEAN,
+        MT_MINICLEAN,
+        MT_LOW_VECTORS,
+        MT_HIGH_VECTORS,
+        MT_MEMORY_RWX,
+        MT_MEMORY_RW,
+        MT_ROM,
+        MT_MEMORY_RWX_NONCACHED,
+        MT_MEMORY_RW_DTCM,
+        MT_MEMORY_RWX_ITCM,
+        MT_MEMORY_RW_SO,
+        MT_MEMORY_DMA_READY,
+};
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index a98a2e112fae..680a83e94467 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -57,12 +57,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
 
-/*
- * Dummy implementation; always return 0.
- */
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
-        return 0;
+        return channel ? 15 : 14;
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 86a659a19526..dfff709fda3c 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -160,6 +160,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
         return (pmd_t *)pud;
 }
 
+#define pmd_large(pmd)          (pmd_val(pmd) & 2)
 #define pmd_bad(pmd)            (pmd_val(pmd) & 2)
 
 #define copy_pmd(pmdpd,pmdps)           \
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 4f9503908dca..03243f7eeddf 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -142,6 +142,7 @@
                                                  PMD_TYPE_TABLE)
 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
                                                  PMD_TYPE_SECT)
+#define pmd_large(pmd)          pmd_sect(pmd)
 
 #define pud_clear(pudp)                 \
         do {                            \
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 1571d126e9dd..7d59b524f2af 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -254,6 +254,8 @@ PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
 PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
 PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
 PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
+PTE_BIT_FUNC(mkexec,   &= ~L_PTE_XN);
+PTE_BIT_FUNC(mknexec,   |= L_PTE_XN);
 
 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
new file mode 100644
index 000000000000..3bd36e2c5f2e
--- /dev/null
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/*
+ * Support for the Trusted Foundations secure monitor.
+ *
+ * Trusted Foundation comes active on some ARM consumer devices (most
+ * Tegra-based devices sold on the market are concerned). Such devices can only
+ * perform some basic operations, like setting the CPU reset vector, through
+ * SMC calls to the secure monitor. The calls are completely specific to
+ * Trusted Foundations, and do *not* follow the SMC calling convention or the
+ * PSCI standard.
+ */
+
+#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H
+#define __ASM_ARM_TRUSTED_FOUNDATIONS_H
+
+#include <linux/kconfig.h>
+#include <linux/printk.h>
+#include <linux/bug.h>
+#include <linux/of.h>
+
+struct trusted_foundations_platform_data {
+        unsigned int version_major;
+        unsigned int version_minor;
+};
+
+#if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS)
+
+void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
+void of_register_trusted_foundations(void);
+
+#else /* CONFIG_TRUSTED_FOUNDATIONS */
+
+static inline void register_trusted_foundations(
+                                   struct trusted_foundations_platform_data *pd)
+{
+        /*
+         * If we try to register TF, this means the system needs it to continue.
+         * Its absence if thus a fatal error.
+         */
+        panic("No support for Trusted Foundations, stopping...\n");
+}
+
+static inline void of_register_trusted_foundations(void)
+{
+        /*
+         * If we find the target should enable TF but does not support it,
+         * fail as the system won't be able to do much anyway
+         */
+        if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
+                register_trusted_foundations(NULL);
+}
+#endif /* CONFIG_TRUSTED_FOUNDATIONS */
+
+#endif
diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h
index 4d52f92967a6..a6d0a29861e7 100644
--- a/arch/arm/include/asm/word-at-a-time.h
+++ b/arch/arm/include/asm/word-at-a-time.h
@@ -48,10 +48,14 @@ static inline unsigned long find_zero(unsigned long mask)
         return ret;
 }
 
-#ifdef CONFIG_DCACHE_WORD_ACCESS
-
 #define zero_bytemask(mask) (mask)
 
+#else   /* __ARMEB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+
 /*
  * Load an unaligned word from kernel space.
  *
@@ -73,7 +77,11 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
         "       bic     %2, %2, #0x3\n"
         "       ldr     %0, [%2]\n"
         "       lsl     %1, %1, #0x3\n"
+#ifndef __ARMEB__
         "       lsr     %0, %0, %1\n"
+#else
+        "       lsl     %0, %0, %1\n"
+#endif
         "       b       2b\n"
         "       .popsection\n"
         "       .pushsection __ex_table,\"a\"\n"
@@ -86,11 +94,5 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
         return ret;
 }
 
-
 #endif  /* DCACHE_WORD_ACCESS */
-
-#else   /* __ARMEB__ */
-#include <asm-generic/word-at-a-time.h>
-#endif
-
 #endif /* __ASM_ARM_WORD_AT_A_TIME_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 3759cacdd7f8..e0965abacb7d 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -117,6 +117,7 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
         return __set_phys_to_machine(pfn, mfn);
 }
 
-#define xen_remap(cookie, size) ioremap_cache((cookie), (size));
+#define xen_remap(cookie, size) ioremap_cache((cookie), (size))
+#define xen_unmap(cookie) iounmap((cookie))
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 29da84e183f4..42b823cd2d22 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -43,6 +43,14 @@
 #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
 #define IMX35_UART_BASE(n)      IMX35_UART_BASE_ADDR(n)
 
+#define IMX50_UART1_BASE_ADDR   0x53fbc000
+#define IMX50_UART2_BASE_ADDR   0x53fc0000
+#define IMX50_UART3_BASE_ADDR   0x5000c000
+#define IMX50_UART4_BASE_ADDR   0x53ff0000
+#define IMX50_UART5_BASE_ADDR   0x63f90000
+#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
+#define IMX50_UART_BASE(n)      IMX50_UART_BASE_ADDR(n)
+
 #define IMX51_UART1_BASE_ADDR   0x73fbc000
 #define IMX51_UART2_BASE_ADDR   0x73fc0000
 #define IMX51_UART3_BASE_ADDR   0x7000c000
@@ -85,6 +93,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX31)
 #elif defined(CONFIG_DEBUG_IMX35_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX35)
+#elif defined(CONFIG_DEBUG_IMX50_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX50)
 #elif defined(CONFIG_DEBUG_IMX51_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX51)
 #elif defined(CONFIG_DEBUG_IMX53_UART)
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index be6a720dd183..f98763f0bc17 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -46,10 +46,10 @@
 #define TEGRA_APB_MISC_GP_HIDREV        (TEGRA_APB_MISC_BASE + 0x804)
 
 /*
- * Must be 1MB-aligned since a 1MB mapping is used early on.
+ * Must be section-aligned since a section mapping is used early on.
  * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
  */
-#define UART_VIRTUAL_BASE               0xfe100000
+#define UART_VIRTUAL_BASE               0xfe800000
 
 #define checkuart(rp, rv, lhu, bit, uart) \
                 /* Load address of CLK_RST register */ \
@@ -156,28 +156,6 @@
 92:             and     \rv, \rp, #0xffffff     @ offset within 1MB section
                 add     \rv, \rv, #UART_VIRTUAL_BASE
                 str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
-                movw    \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
-                movt    \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
-                ldr     \rv, [\rv, #0]          @ Load HIDREV
-                ubfx    \rv, \rv, #8, #8        @ 15:8 are SoC version
-                cmp     \rv, #0x20              @ Tegra20?
-                moveq   \rv, #0x75              @ Tegra20 divisor
-                movne   \rv, #0xdd              @ Tegra30 divisor
-                str     \rv, [\tmp, #12]        @ Save divisor to scratch
-                /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
-                mov     \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
-                /* uart[UART_DLL] = div & 0xff; */
-                ldr     \rv, [\tmp, #12]
-                and     \rv, \rv, #0xff
-                str     \rv, [\rp, #UART_DLL << UART_SHIFT]
-                /* uart[UART_DLM] = div >> 8; */
-                ldr     \rv, [\tmp, #12]
-                lsr     \rv, \rv, #8
-                str     \rv, [\rp, #UART_DLM << UART_SHIFT]
-                /* uart[UART_LCR] = UART_LCR_WLEN8; */
-                mov     \rv, #UART_LCR_WLEN8
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
                 b       100f
 
                 .align
@@ -205,8 +183,8 @@
                 cmp     \rx, #0
                 beq     1002f
 1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
-                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
-                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                and     \rd, \rd, #UART_LSR_THRE
+                teq     \rd, #UART_LSR_THRE
                 bne     1001b
 1002:
                 .endm
@@ -225,7 +203,7 @@
 /*
  * Storage for the state maintained by the macros above.
  *
- * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
+ * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
  * That's because this header is included from multiple files, and we only
  * want a single copy of the data. In particular, the UART probing code above
  * assumes it's running using physical addresses. This is true when this file
@@ -247,6 +225,4 @@ tegra_uart_config:
         .word 0
         /* Debug UART virtual address */
         .word 0
-        /* Scratch space for debug macro */
-        .word 0
 #endif
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index c498b60c0505..ef0c8785ba16 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -119,6 +119,26 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_32_CRN_MASK         0x0000000000007800
 #define KVM_REG_ARM_32_CRN_SHIFT        11
 
+#define ARM_CP15_REG_SHIFT_MASK(x,n) \
+        (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
+
+#define __ARM_CP15_REG(op1,crn,crm,op2) \
+        (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
+        ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
+        ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
+        ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
+        ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
+
+#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
+
+#define __ARM_CP15_REG64(op1,crm) \
+        (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
+#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
+
+#define KVM_REG_ARM_TIMER_CTL           ARM_CP15_REG32(0, 14, 3, 1)
+#define KVM_REG_ARM_TIMER_CNT           ARM_CP15_REG64(1, 14) 
+#define KVM_REG_ARM_TIMER_CVAL          ARM_CP15_REG64(3, 14) 
+
 /* Normal registers are mapped as coprocessor 16. */
 #define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 #define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / 4)
@@ -143,6 +163,14 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_VFP_FPINST          0x1009
 #define KVM_REG_ARM_VFP_FPINST2         0x100A
 
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR       0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
 
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 1f031ddd0667..85e664b6a5f1 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -35,6 +35,8 @@ extern void __ucmpdi2(void);
 extern void __udivsi3(void);
 extern void __umodsi3(void);
 extern void __do_div64(void);
+extern void __bswapsi2(void);
+extern void __bswapdi2(void);
 
 extern void __aeabi_idiv(void);
 extern void __aeabi_idivmod(void);
@@ -114,6 +116,8 @@ EXPORT_SYMBOL(__ucmpdi2);
 EXPORT_SYMBOL(__udivsi3);
 EXPORT_SYMBOL(__umodsi3);
 EXPORT_SYMBOL(__do_div64);
+EXPORT_SYMBOL(__bswapsi2);
+EXPORT_SYMBOL(__bswapdi2);
 
 #ifdef CONFIG_AEABI
 EXPORT_SYMBOL(__aeabi_idiv);
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 34d5fd585bbb..f751714d52c1 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -33,7 +33,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 
 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 {
-        return alloc_bootmem_align(size, align);
+        return memblock_virt_alloc(size, align);
 }
 
 void __init arm_dt_memblock_reserve(void)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index b3fb8c9e1ff2..1879e8dd2acc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -451,9 +451,11 @@ __und_usr_thumb:
         .arch   armv6t2
 #endif
 2:      ldrht   r5, [r4]
+ARM_BE8(rev16   r5, r5)                         @ little endian instruction
         cmp     r5, #0xe800                     @ 32bit instruction if xx != 0
         blo     __und_usr_fault_16              @ 16bit undefined instruction
 3:      ldrht   r0, [r2]
+ARM_BE8(rev16   r0, r0)                         @ little endian instruction
         add     r2, r2, #2                      @ r2 is PC + 2, make it PC + 4
         str     r2, [sp, #S_PC]                 @ it's a 2x16bit instr, update
         orr     r0, r0, r5, lsl #16
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
index 52b26432c9a9..2260f1855820 100644
--- a/arch/arm/kernel/entry-v7m.S
+++ b/arch/arm/kernel/entry-v7m.S
@@ -14,8 +14,6 @@
 #include <asm/thread_notify.h>
 #include <asm/v7m.h>
 
-#include <mach/entry-macro.S>
-
 #include "entry-header.S"
 
 #ifdef CONFIG_TRACE_IRQFLAGS
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 8ff0ecdc637f..131a6ab5f355 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -385,7 +385,6 @@ out:
         return ret;
 
 out_unmap:
-        amba_set_drvdata(dev, NULL);
         iounmap(t->etb_regs);
 
 out_release:
@@ -398,8 +397,6 @@ static int etb_remove(struct amba_device *dev)
 {
         struct tracectx *t = amba_get_drvdata(dev);
 
-        amba_set_drvdata(dev, NULL);
-
         iounmap(t->etb_regs);
         t->etb_regs = NULL;
 
@@ -588,7 +585,6 @@ out:
         return ret;
 
 out_unmap:
-        amba_set_drvdata(dev, NULL);
         iounmap(t->etm_regs);
 
 out_release:
@@ -601,8 +597,6 @@ static int etm_remove(struct amba_device *dev)
 {
         struct tracectx *t = amba_get_drvdata(dev);
 
-        amba_set_drvdata(dev, NULL);
-
         iounmap(t->etm_regs);
         t->etm_regs = NULL;
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 32f317e5828a..914616e0bdcd 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -52,7 +52,8 @@
         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
 
         .macro  pgtbl, rd, phys
-        add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
+        add     \rd, \phys, #TEXT_OFFSET
+        sub     \rd, \rd, #PG_DIR_SIZE
         .endm
 
 /*
diff --git a/arch/arm/kernel/io.c b/arch/arm/kernel/io.c
index dcd5b4d86143..9203cf883330 100644
--- a/arch/arm/kernel/io.c
+++ b/arch/arm/kernel/io.c
@@ -1,6 +1,41 @@
 #include <linux/export.h>
 #include <linux/types.h>
 #include <linux/io.h>
+#include <linux/spinlock.h>
+
+static DEFINE_RAW_SPINLOCK(__io_lock);
+
+/*
+ * Generic atomic MMIO modify.
+ *
+ * Allows thread-safe access to registers shared by unrelated subsystems.
+ * The access is protected by a single MMIO-wide lock.
+ */
+void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set)
+{
+        unsigned long flags;
+        u32 value;
+
+        raw_spin_lock_irqsave(&__io_lock, flags);
+        value = readl_relaxed(reg) & ~mask;
+        value |= (set & mask);
+        writel_relaxed(value, reg);
+        raw_spin_unlock_irqrestore(&__io_lock, flags);
+}
+EXPORT_SYMBOL(atomic_io_modify_relaxed);
+
+void atomic_io_modify(void __iomem *reg, u32 mask, u32 set)
+{
+        unsigned long flags;
+        u32 value;
+
+        raw_spin_lock_irqsave(&__io_lock, flags);
+        value = readl_relaxed(reg) & ~mask;
+        value |= (set & mask);
+        writel(value, reg);
+        raw_spin_unlock_irqrestore(&__io_lock, flags);
+}
+EXPORT_SYMBOL(atomic_io_modify);
 
 /*
  * Copy data from IO memory space to "real" memory space.
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 987a7f5bce5f..b0df9761de6d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -334,7 +334,7 @@ static void __init cacheid_init(void)
                 cacheid = CACHEID_VIVT;
         }
 
-        printk("CPU: %s data cache, %s instruction cache\n",
+        pr_info("CPU: %s data cache, %s instruction cache\n",
                 cache_is_vivt() ? "VIVT" :
                 cache_is_vipt_aliasing() ? "VIPT aliasing" :
                 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
@@ -416,7 +416,7 @@ void notrace cpu_init(void)
         struct stack *stk = &stacks[cpu];
 
         if (cpu >= NR_CPUS) {
-                printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
+                pr_crit("CPU%u: bad primary CPU number\n", cpu);
                 BUG();
         }
 
@@ -484,7 +484,7 @@ void __init smp_setup_processor_id(void)
          */
         set_my_cpu_offset(0);
 
-        printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
+        pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
 }
 
 struct mpidr_hash mpidr_hash;
@@ -564,8 +564,8 @@ static void __init setup_processor(void)
          */
         list = lookup_processor_type(read_cpuid_id());
         if (!list) {
-                printk("CPU configuration botched (ID %08x), unable "
-                       "to continue.\n", read_cpuid_id());
+                pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
+                       read_cpuid_id());
                 while (1);
         }
 
@@ -585,9 +585,9 @@ static void __init setup_processor(void)
         cpu_cache = *list->cache;
 #endif
 
-        printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-               cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-               proc_arch[cpu_architecture()], cr_alignment);
+        pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+                cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
+                proc_arch[cpu_architecture()], cr_alignment);
 
         snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
                  list->arch_name, ENDIANNESS);
@@ -629,8 +629,8 @@ int __init arm_add_memory(u64 start, u64 size)
         u64 aligned_start;
 
         if (meminfo.nr_banks >= NR_BANKS) {
-                printk(KERN_CRIT "NR_BANKS too low, "
-                        "ignoring memory at 0x%08llx\n", (long long)start);
+                pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
+                        (long long)start);
                 return -EINVAL;
         }
 
@@ -643,14 +643,14 @@ int __init arm_add_memory(u64 start, u64 size)
 
 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
         if (aligned_start > ULONG_MAX) {
-                printk(KERN_CRIT "Ignoring memory at 0x%08llx outside "
-                       "32-bit physical address space\n", (long long)start);
+                pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
+                        (long long)start);
                 return -EINVAL;
         }
 
         if (aligned_start + size > ULONG_MAX) {
-                printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
-                        "32-bit physical address space\n", (long long)start);
+                pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
+                        (long long)start);
                 /*
                  * To ensure bank->start + bank->size is representable in
                  * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
@@ -660,6 +660,20 @@ int __init arm_add_memory(u64 start, u64 size)
         }
 #endif
 
+        if (aligned_start < PHYS_OFFSET) {
+                if (aligned_start + size <= PHYS_OFFSET) {
+                        pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
+                                aligned_start, aligned_start + size);
+                        return -EINVAL;
+                }
+
+                pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
+                        aligned_start, (u64)PHYS_OFFSET);
+
+                size -= PHYS_OFFSET - aligned_start;
+                aligned_start = PHYS_OFFSET;
+        }
+
         bank->start = aligned_start;
         bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
 
@@ -717,7 +731,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
         kernel_data.end     = virt_to_phys(_end - 1);
 
         for_each_memblock(memory, region) {
-                res = alloc_bootmem_low(sizeof(*res));
+                res = memblock_virt_alloc_low(sizeof(*res), 0);
                 res->name  = "System RAM";
                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
@@ -817,18 +831,17 @@ static void __init reserve_crashkernel(void)
         if (ret)
                 return;
 
-        ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+        ret = memblock_reserve(crash_base, crash_size);
         if (ret < 0) {
-                printk(KERN_WARNING "crashkernel reservation failed - "
-                       "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+                pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
+                        (unsigned long)crash_base);
                 return;
         }
 
-        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
-               "for crashkernel (System RAM: %ldMB)\n",
-               (unsigned long)(crash_size >> 20),
-               (unsigned long)(crash_base >> 20),
-               (unsigned long)(total_mem >> 20));
+        pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
+                (unsigned long)(crash_size >> 20),
+                (unsigned long)(crash_base >> 20),
+                (unsigned long)(total_mem >> 20));
 
         crashk_res.start = crash_base;
         crashk_res.end = crash_base + crash_size - 1;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index dc894ab3622b..b7b4c86e338b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -105,8 +105,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
         secondary_data.pgdir = get_arch_pgd(idmap_pgd);
         secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
 #endif
-        __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
-        outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
+        sync_cache_w(&secondary_data);
 
         /*
          * Now bring the CPU into our world.
@@ -294,6 +293,9 @@ void __ref cpu_die(void)
         if (smp_ops.cpu_die)
                 smp_ops.cpu_die(cpu);
 
+        pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n",
+                cpu);
+
         /*
          * Do not return to the idle loop - jump back to the secondary
          * cpu initialisation.  There's some initialisation which needs
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index f50f19e5c138..7a3be1d4d0b1 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -52,7 +52,7 @@ static struct map_desc dtcm_iomap[] __initdata = {
                 .virtual        = DTCM_OFFSET,
                 .pfn            = __phys_to_pfn(DTCM_OFFSET),
                 .length         = 0,
-                .type           = MT_MEMORY_DTCM
+                .type           = MT_MEMORY_RW_DTCM
         }
 };
 
@@ -61,7 +61,7 @@ static struct map_desc itcm_iomap[] __initdata = {
                 .virtual        = ITCM_OFFSET,
                 .pfn            = __phys_to_pfn(ITCM_OFFSET),
                 .length         = 0,
-                .type           = MT_MEMORY_ITCM
+                .type           = MT_MEMORY_RWX_ITCM,
         }
 };
 
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 85a87370f144..0bc94b1fd1ae 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -68,16 +68,16 @@ struct cpu_efficiency {
  * Processors that are not defined in the table,
  * use the default SCHED_POWER_SCALE value for cpu_scale.
  */
-struct cpu_efficiency table_efficiency[] = {
+static const struct cpu_efficiency table_efficiency[] = {
         {"arm,cortex-a15", 3891},
         {"arm,cortex-a7",  2048},
         {NULL, },
 };
 
-unsigned long *__cpu_capacity;
+static unsigned long *__cpu_capacity;
 #define cpu_capacity(cpu)       __cpu_capacity[cpu]
 
-unsigned long middle_capacity = 1;
+static unsigned long middle_capacity = 1;
 
 /*
  * Iterate all CPUs' descriptor in DT and compute the efficiency
@@ -89,7 +89,7 @@ unsigned long middle_capacity = 1;
  */
 static void __init parse_dt_topology(void)
 {
-        struct cpu_efficiency *cpu_eff;
+        const struct cpu_efficiency *cpu_eff;
         struct device_node *cn = NULL;
         unsigned long min_capacity = (unsigned long)(-1);
         unsigned long max_capacity = 0;
@@ -158,7 +158,7 @@ static void __init parse_dt_topology(void)
  * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
  * function returns directly for SMP system.
  */
-void update_cpu_power(unsigned int cpu)
+static void update_cpu_power(unsigned int cpu)
 {
         if (!cpu_capacity(cpu))
                 return;
@@ -185,7 +185,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
         return &cpu_topology[cpu].core_sibling;
 }
 
-void update_siblings_masks(unsigned int cpuid)
+static void update_siblings_masks(unsigned int cpuid)
 {
         struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
         int cpu;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 4636d56af2db..172ee18ff124 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -62,7 +62,7 @@ static void dump_mem(const char *, const char *, unsigned long, unsigned long);
 void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
 {
 #ifdef CONFIG_KALLSYMS
-        printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+        printk("[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
 #else
         printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
 #endif
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 2a700e00528d..1d8248ea5669 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/cpu.h>
+#include <linux/cpu_pm.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
@@ -137,6 +138,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
         if (ret)
                 goto out_free_stage2_pgd;
 
+        kvm_timer_init(kvm);
+
         /* Mark the initial VMID generation invalid */
         kvm->arch.vmid_gen = 0;
 
@@ -188,6 +191,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_IRQCHIP:
                 r = vgic_present;
                 break;
+        case KVM_CAP_DEVICE_CTRL:
         case KVM_CAP_USER_MEMORY:
         case KVM_CAP_SYNC_MMU:
         case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
@@ -339,6 +343,13 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 
 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 {
+        /*
+         * The arch-generic KVM code expects the cpu field of a vcpu to be -1
+         * if the vcpu is no longer assigned to a cpu.  This is used for the
+         * optimized make_all_cpus_request path.
+         */
+        vcpu->cpu = -1;
+
         kvm_arm_set_running_vcpu(NULL);
 }
 
@@ -462,6 +473,8 @@ static void update_vttbr(struct kvm *kvm)
 
 static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
 {
+        int ret;
+
         if (likely(vcpu->arch.has_run_once))
                 return 0;
 
@@ -471,22 +484,12 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
          * Initialize the VGIC before running a vcpu the first time on
          * this VM.
          */
-        if (irqchip_in_kernel(vcpu->kvm) &&
-            unlikely(!vgic_initialized(vcpu->kvm))) {
-                int ret = kvm_vgic_init(vcpu->kvm);
+        if (unlikely(!vgic_initialized(vcpu->kvm))) {
+                ret = kvm_vgic_init(vcpu->kvm);
                 if (ret)
                         return ret;
         }
 
-        /*
-         * Handle the "start in power-off" case by calling into the
-         * PSCI code.
-         */
-        if (test_and_clear_bit(KVM_ARM_VCPU_POWER_OFF, vcpu->arch.features)) {
-                *vcpu_reg(vcpu, 0) = KVM_PSCI_FN_CPU_OFF;
-                kvm_psci_call(vcpu);
-        }
-
         return 0;
 }
 
@@ -700,6 +703,24 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level,
         return -EINVAL;
 }
 
+static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
+                                         struct kvm_vcpu_init *init)
+{
+        int ret;
+
+        ret = kvm_vcpu_set_target(vcpu, init);
+        if (ret)
+                return ret;
+
+        /*
+         * Handle the "start in power-off" case by marking the VCPU as paused.
+         */
+        if (__test_and_clear_bit(KVM_ARM_VCPU_POWER_OFF, vcpu->arch.features))
+                vcpu->arch.pause = true;
+
+        return 0;
+}
+
 long kvm_arch_vcpu_ioctl(struct file *filp,
                          unsigned int ioctl, unsigned long arg)
 {
@@ -713,8 +734,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 if (copy_from_user(&init, argp, sizeof(init)))
                         return -EFAULT;
 
-                return kvm_vcpu_set_target(vcpu, &init);
-
+                return kvm_arch_vcpu_ioctl_vcpu_init(vcpu, &init);
         }
         case KVM_SET_ONE_REG:
         case KVM_GET_ONE_REG: {
@@ -772,7 +792,7 @@ static int kvm_vm_ioctl_set_device_addr(struct kvm *kvm,
         case KVM_ARM_DEVICE_VGIC_V2:
                 if (!vgic_present)
                         return -ENXIO;
-                return kvm_vgic_set_addr(kvm, type, dev_addr->addr);
+                return kvm_vgic_addr(kvm, type, &dev_addr->addr, true);
         default:
                 return -ENODEV;
         }
@@ -853,6 +873,33 @@ static struct notifier_block hyp_init_cpu_nb = {
         .notifier_call = hyp_init_cpu_notify,
 };
 
+#ifdef CONFIG_CPU_PM
+static int hyp_init_cpu_pm_notifier(struct notifier_block *self,
+                                    unsigned long cmd,
+                                    void *v)
+{
+        if (cmd == CPU_PM_EXIT) {
+                cpu_init_hyp_mode(NULL);
+                return NOTIFY_OK;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block hyp_init_cpu_pm_nb = {
+        .notifier_call = hyp_init_cpu_pm_notifier,
+};
+
+static void __init hyp_cpu_pm_init(void)
+{
+        cpu_pm_register_notifier(&hyp_init_cpu_pm_nb);
+}
+#else
+static inline void hyp_cpu_pm_init(void)
+{
+}
+#endif
+
 /**
  * Inits Hyp-mode on all online CPUs
  */
@@ -1013,6 +1060,8 @@ int kvm_arch_init(void *opaque)
                 goto out_err;
         }
 
+        hyp_cpu_pm_init();
+
         kvm_coproc_table_init();
         return 0;
 out_err:
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 20f8d97904af..2786eae10c0d 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -109,6 +109,83 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         return -EINVAL;
 }
 
+#ifndef CONFIG_KVM_ARM_TIMER
+
+#define NUM_TIMER_REGS 0
+
+static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        return 0;
+}
+
+static bool is_timer_reg(u64 index)
+{
+        return false;
+}
+
+int kvm_arm_timer_set_reg(struct kvm_vcpu *vcpu, u64 regid, u64 value)
+{
+        return 0;
+}
+
+u64 kvm_arm_timer_get_reg(struct kvm_vcpu *vcpu, u64 regid)
+{
+        return 0;
+}
+
+#else
+
+#define NUM_TIMER_REGS 3
+
+static bool is_timer_reg(u64 index)
+{
+        switch (index) {
+        case KVM_REG_ARM_TIMER_CTL:
+        case KVM_REG_ARM_TIMER_CNT:
+        case KVM_REG_ARM_TIMER_CVAL:
+                return true;
+        }
+        return false;
+}
+
+static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        if (put_user(KVM_REG_ARM_TIMER_CTL, uindices))
+                return -EFAULT;
+        uindices++;
+        if (put_user(KVM_REG_ARM_TIMER_CNT, uindices))
+                return -EFAULT;
+        uindices++;
+        if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices))
+                return -EFAULT;
+
+        return 0;
+}
+
+#endif
+
+static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        u64 val;
+        int ret;
+
+        ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
+        if (ret != 0)
+                return ret;
+
+        return kvm_arm_timer_set_reg(vcpu, reg->id, val);
+}
+
+static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        void __user *uaddr = (void __user *)(long)reg->addr;
+        u64 val;
+
+        val = kvm_arm_timer_get_reg(vcpu, reg->id);
+        return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id));
+}
+
 static unsigned long num_core_regs(void)
 {
         return sizeof(struct kvm_regs) / sizeof(u32);
@@ -121,7 +198,8 @@ static unsigned long num_core_regs(void)
  */
 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
 {
-        return num_core_regs() + kvm_arm_num_coproc_regs(vcpu);
+        return num_core_regs() + kvm_arm_num_coproc_regs(vcpu)
+                + NUM_TIMER_REGS;
 }
 
 /**
@@ -133,6 +211,7 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 {
         unsigned int i;
         const u64 core_reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE;
+        int ret;
 
         for (i = 0; i < sizeof(struct kvm_regs)/sizeof(u32); i++) {
                 if (put_user(core_reg | i, uindices))
@@ -140,6 +219,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
                 uindices++;
         }
 
+        ret = copy_timer_indices(vcpu, uindices);
+        if (ret)
+                return ret;
+        uindices += NUM_TIMER_REGS;
+
         return kvm_arm_copy_coproc_indices(vcpu, uindices);
 }
 
@@ -153,6 +237,9 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
                 return get_core_reg(vcpu, reg);
 
+        if (is_timer_reg(reg->id))
+                return get_timer_reg(vcpu, reg);
+
         return kvm_arm_coproc_get_reg(vcpu, reg);
 }
 
@@ -166,6 +253,9 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
                 return set_core_reg(vcpu, reg);
 
+        if (is_timer_reg(reg->id))
+                return set_timer_reg(vcpu, reg);
+
         return kvm_arm_coproc_set_reg(vcpu, reg);
 }
 
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index a92079011a83..0de91fc6de0f 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -26,8 +26,6 @@
 
 #include "trace.h"
 
-#include "trace.h"
-
 typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
 
 static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 580906989db1..7789857d1470 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -667,14 +667,16 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
                 gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
         } else {
                 /*
-                 * Pages belonging to VMAs not aligned to the PMD mapping
-                 * granularity cannot be mapped using block descriptors even
-                 * if the pages belong to a THP for the process, because the
-                 * stage-2 block descriptor will cover more than a single THP
-                 * and we loose atomicity for unmapping, updates, and splits
-                 * of the THP or other pages in the stage-2 block range.
+                 * Pages belonging to memslots that don't have the same
+                 * alignment for userspace and IPA cannot be mapped using
+                 * block descriptors even if the pages belong to a THP for
+                 * the process, because the stage-2 block descriptor will
+                 * cover more than a single THP and we loose atomicity for
+                 * unmapping, updates, and splits of the THP or other pages
+                 * in the stage-2 block range.
                  */
-                if (vma->vm_start & ~PMD_MASK)
+                if ((memslot->userspace_addr & ~PMD_MASK) !=
+                    ((memslot->base_gfn << PAGE_SHIFT) & ~PMD_MASK))
                         force_pte = true;
         }
         up_read(&current->mm->mmap_sem);
@@ -916,9 +918,9 @@ int kvm_mmu_init(void)
 {
         int err;
 
-        hyp_idmap_start = virt_to_phys(__hyp_idmap_text_start);
-        hyp_idmap_end = virt_to_phys(__hyp_idmap_text_end);
-        hyp_idmap_vector = virt_to_phys(__kvm_hyp_init);
+        hyp_idmap_start = kvm_virt_to_phys(__hyp_idmap_text_start);
+        hyp_idmap_end = kvm_virt_to_phys(__hyp_idmap_text_end);
+        hyp_idmap_vector = kvm_virt_to_phys(__kvm_hyp_init);
 
         if ((hyp_idmap_start ^ hyp_idmap_end) & PAGE_MASK) {
                 /*
@@ -945,7 +947,7 @@ int kvm_mmu_init(void)
                  */
                 kvm_flush_dcache_to_poc(init_bounce_page, len);
 
-                phys_base = virt_to_phys(init_bounce_page);
+                phys_base = kvm_virt_to_phys(init_bounce_page);
                 hyp_idmap_vector += phys_base - hyp_idmap_start;
                 hyp_idmap_start = phys_base;
                 hyp_idmap_end = phys_base + len;
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 0881bf169fbc..448f60e8d23c 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -54,15 +54,15 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
                 }
         }
 
-        if (!vcpu)
+        /*
+         * Make sure the caller requested a valid CPU and that the CPU is
+         * turned off.
+         */
+        if (!vcpu || !vcpu->arch.pause)
                 return KVM_PSCI_RET_INVAL;
 
         target_pc = *vcpu_reg(source_vcpu, 2);
 
-        wq = kvm_arch_vcpu_wq(vcpu);
-        if (!waitqueue_active(wq))
-                return KVM_PSCI_RET_INVAL;
-
         kvm_reset_vcpu(vcpu);
 
         /* Gracefully handle Thumb2 entry point */
@@ -79,6 +79,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
         vcpu->arch.pause = false;
         smp_mb();               /* Make sure the above is visible */
 
+        wq = kvm_arch_vcpu_wq(vcpu);
         wake_up_interruptible(wq);
 
         return KVM_PSCI_RET_SUCCESS;
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 47d7338561de..0573faab96ad 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -13,7 +13,7 @@ lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
                    ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
                    ucmpdi2.o lib1funcs.o div64.o                      \
                    io-readsb.o io-writesb.o io-readsl.o io-writesl.o  \
-                   call_with_stack.o
+                   call_with_stack.o bswapsdi2.o
 
 mmu-y   := clear_user.o copy_page.o getuser.o putuser.o
 
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index cd07b5814c23..4102be617fce 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -80,14 +80,14 @@ for_each_frame:	tst	frame, mask		@ Check for address exceptions
 
                 ldr     r1, [sv_pc, #-4]        @ if stmfd sp!, {args} exists,
                 ldr     r3, .Ldsi+4
-                teq     r3, r1, lsr #10
+                teq     r3, r1, lsr #11
                 ldreq   r0, [frame, #-8]        @ get sp
                 subeq   r0, r0, #4              @ point at the last arg
                 bleq    .Ldumpstm               @ dump saved registers
 
 1004:           ldr     r1, [sv_pc, #0]         @ if stmfd sp!, {..., fp, ip, lr, pc}
                 ldr     r3, .Ldsi               @ instruction exists,
-                teq     r3, r1, lsr #10
+                teq     r3, r1, lsr #11
                 subeq   r0, frame, #16
                 bleq    .Ldumpstm               @ dump saved registers
 
@@ -128,11 +128,11 @@ ENDPROC(c_backtrace)
                 beq     2f
                 add     r7, r7, #1
                 teq     r7, #6
-                moveq   r7, #1
-                moveq   r1, #'\n'
-                movne   r1, #' '
-                ldr     r3, [stack], #-4
-                mov     r2, reg
+                moveq   r7, #0
+                adr     r3, .Lcr
+                addne   r3, r3, #1              @ skip newline
+                ldr     r2, [stack], #-4
+                mov     r1, reg
                 adr     r0, .Lfp
                 bl      printk
 2:              subs    reg, reg, #1
@@ -142,11 +142,11 @@ ENDPROC(c_backtrace)
                 blne    printk
                 ldmfd   sp!, {instr, reg, stack, r7, pc}
 
-.Lfp:           .asciz  "%cr%d:%08x"
+.Lfp:           .asciz  " r%d:%08x%s"
 .Lcr:           .asciz  "\n"
 .Lbad:          .asciz  "Backtrace aborted due to bad frame pointer <%p>\n"
                 .align
-.Ldsi:          .word   0xe92dd800 >> 10        @ stmfd sp!, {... fp, ip, lr, pc}
-                .word   0xe92d0000 >> 10        @ stmfd sp!, {}
+.Ldsi:          .word   0xe92dd800 >> 11        @ stmfd sp!, {... fp, ip, lr, pc}
+                .word   0xe92d0000 >> 11        @ stmfd sp!, {}
 
 #endif
diff --git a/arch/arm/lib/bswapsdi2.S b/arch/arm/lib/bswapsdi2.S
new file mode 100644
index 000000000000..9fcdd154eff9
--- /dev/null
+++ b/arch/arm/lib/bswapsdi2.S
@@ -0,0 +1,36 @@
+#include <linux/linkage.h>
+
+#if __LINUX_ARM_ARCH__ >= 6
+ENTRY(__bswapsi2)
+        rev r0, r0
+        bx lr
+ENDPROC(__bswapsi2)
+
+ENTRY(__bswapdi2)
+        rev r3, r0
+        rev r0, r1
+        mov r1, r3
+        bx lr
+ENDPROC(__bswapdi2)
+#else
+ENTRY(__bswapsi2)
+        eor r3, r0, r0, ror #16
+        mov r3, r3, lsr #8
+        bic r3, r3, #0xff00
+        eor r0, r3, r0, ror #8
+        mov pc, lr
+ENDPROC(__bswapsi2)
+
+ENTRY(__bswapdi2)
+        mov ip, r1
+        eor r3, ip, ip, ror #16
+        eor r1, r0, r0, ror #16
+        mov r1, r1, lsr #8
+        mov r3, r3, lsr #8
+        bic r3, r3, #0xff00
+        bic r1, r1, #0xff00
+        eor r1, r1, r0, ror #8
+        eor r0, r3, ip, ror #8
+        mov pc, lr
+ENDPROC(__bswapdi2)
+#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 699b71e7f7ec..4f0e800e7e71 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,15 +1,33 @@
 if ARCH_AT91
 
+config HAVE_AT91_UTMI
+        bool
+
+config HAVE_AT91_USB_CLK
+        bool
+
 config HAVE_AT91_DBGU0
         bool
 
 config HAVE_AT91_DBGU1
         bool
 
+config AT91_USE_OLD_CLK
+        bool
+
 config AT91_PMC_UNIT
         bool
         default !ARCH_AT91X40
 
+config COMMON_CLK_AT91
+        bool
+        default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
+        select COMMON_CLK
+
+config OLD_CLK_AT91
+        bool
+        default AT91_PMC_UNIT && AT91_USE_OLD_CLK
+
 config AT91_SAM9_ALT_RESET
         bool
         default !ARCH_AT91X40
@@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET
 config AT91_SAM9_TIME
         bool
 
+config HAVE_AT91_SMD
+        bool
+
 config SOC_AT91SAM9
         bool
         select AT91_SAM9_TIME
@@ -61,13 +82,15 @@ comment "Atmel AT91 Processor"
 if SOC_SAM_V7
 config SOC_SAMA5D3
         bool "SAMA5D3 family"
-        depends on SOC_SAM_V7
         select SOC_SAMA5
         select HAVE_FB_ATMEL
         select HAVE_AT91_DBGU1
+        select HAVE_AT91_UTMI
+        select HAVE_AT91_SMD
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using one of Atmel's SAMA5D3 family SoC.
-          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
+          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
 endif
 
 if SOC_SAM_V4_V5
@@ -78,11 +101,15 @@ config SOC_AT91RM9200
         select HAVE_AT91_DBGU0
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_USB_CLK
 
 config SOC_AT91SAM9260
         bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
         select HAVE_AT91_DBGU0
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
           or AT91SAM9G20 SoC.
@@ -92,6 +119,8 @@ config SOC_AT91SAM9261
         select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
 
@@ -100,18 +129,25 @@ config SOC_AT91SAM9263
         select HAVE_AT91_DBGU1
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_USB_CLK
 
 config SOC_AT91SAM9RL
         bool "AT91SAM9RL"
         select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_UTMI
 
 config SOC_AT91SAM9G45
         bool "AT91SAM9G45 or AT91SAM9M10 families"
         select HAVE_AT91_DBGU1
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_UTMI
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
           This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +157,10 @@ config SOC_AT91SAM9X5
         select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_UTMI
+        select HAVE_AT91_SMD
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
           This means that your SAM9 name finishes with a '5' (except if it is
@@ -133,6 +173,8 @@ config SOC_AT91SAM9N12
         select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
         select SOC_AT91SAM9
+        select AT91_USE_OLD_CLK
+        select HAVE_AT91_USB_CLK
         help
           Select this if you are using Atmel's AT91SAM9N12 SoC.
 
@@ -172,12 +214,6 @@ config MACH_SAMA5_DT
 
 comment "AT91 Feature Selections"
 
-config AT91_PROGRAMMABLE_CLOCKS
-        bool "Programmable Clocks"
-        help
-          Select this if you need to program one or more of the PCK0..PCK3
-          programmable clock outputs.
-
 config AT91_SLOW_CLOCK
         bool "Suspend-to-RAM disables main oscillator"
         depends on SUSPEND
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index ca900be144ce..1f73e9b527da 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -12,26 +12,32 @@ config ARCH_AT91_NONE
 config ARCH_AT91RM9200
         bool "AT91RM9200"
         select SOC_AT91RM9200
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91SAM9260
         bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
         select SOC_AT91SAM9260
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261 or AT91SAM9G10"
         select SOC_AT91SAM9261
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
         select SOC_AT91SAM9263
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
         select SOC_AT91SAM9RL
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
         select SOC_AT91SAM9G45
+        select AT91_USE_OLD_CLK
 
 config ARCH_AT91X40
         bool "AT91x40"
@@ -176,12 +182,6 @@ config MACH_AFEB9260
           <svn://194.85.238.22/home/users/george/svn/arm9eb>
           <http://groups.google.com/group/arm9fpga-evolution-board>
 
-config MACH_QIL_A9260
-        bool "CALAO QIL-A9260 board"
-        help
-          Select this if you are using a Calao Systems QIL-A9260 Board.
-          <http://www.calao-systems.com>
-
 config MACH_CPU9260
         bool "Eukrea CPU9260 board"
         help
@@ -241,7 +241,7 @@ config MACH_PCONTROL_G20
         bool "PControl G20 CPU module"
         help
           Select this if you are using taskit's Stamp9G20 CPU module on this
-          carrier board, beeing the decentralized unit of a building automation
+          carrier board, being the decentralized unit of a building automation
           system; featuring nvram, eth-switch, iso-rs485, display, io
 
 config MACH_GSIA18S
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 90aab2d5a07f..78e9cec282f4 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m		:=
 obj-n           :=
 obj-            :=
 
-obj-$(CONFIG_AT91_PMC_UNIT)     += clock.o
+obj-$(CONFIG_OLD_CLK_AT91)      += clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
 obj-$(CONFIG_AT91_SAM9_TIME)    += at91sam926x_time.o
@@ -52,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_FLEXIBITY)    += board-flexibity.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 25805f2f6010..e47f5fd232f5 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,13 +12,13 @@
 
 #include <linux/module.h>
 #include <linux/reboot.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
-#include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
 
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d6a1fa85371d..6c821e562159 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -20,7 +21,6 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
-#include <mach/at91_pmc.h>
 
 #include "at91_aic.h"
 #include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 23ba1d8a1531..6276b4c1acfe 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -19,7 +20,6 @@
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
-#include <mach/at91_pmc.h>
 
 #include "at91_aic.h"
 #include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 7eccb0fc57bc..37b90f4b990c 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -18,7 +19,6 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
-#include <mach/at91_pmc.h>
 
 #include "at91_aic.h"
 #include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index bb392320a0dd..0f04ffe9c5a8 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
 static u32 pit_cycle;           /* write-once */
 static u32 pit_cnt;             /* access only w/system irq blocked */
 static void __iomem *pit_base_addr __read_mostly;
+static struct clk *mck;
 
 static inline unsigned int pit_read(unsigned int reg_offset)
 {
@@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void)
         if (!pit_base_addr)
                 goto node_err;
 
+        mck = of_clk_get(np, 0);
+
         /* Get the interrupts property */
         ret = irq_of_parse_and_map(np, 0);
         if (!ret) {
                 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+                if (!IS_ERR(mck))
+                        clk_put(mck);
                 goto ioremap_err;
         }
         at91sam926x_pit_irq.irq = ret;
@@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void)
         unsigned        bits;
         int             ret;
 
+        mck = ERR_PTR(-ENOENT);
+
         /* For device tree enabled device: initialize here */
         of_at91sam926x_pit_init();
 
@@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void)
          * Use our actual MCK to figure out how many MCK/16 ticks per
          * 1/HZ period (instead of a compile-time constant LATCH).
          */
-        pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+        if (IS_ERR(mck))
+                mck = clk_get(NULL, "mck");
+
+        if (IS_ERR(mck))
+                panic("AT91: PIT: Unable to get mck clk\n");
+        pit_rate = clk_get_rate(mck) / 16;
         pit_cycle = (pit_rate + HZ/2) / HZ;
         WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9405aa08b104..2f455ce35268 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
 
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 388ec3aec4b9..4ef088c62eab 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
 
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 0750ffb7e6b1..3651517abedf 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
@@ -19,7 +20,6 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
-#include <mach/at91_pmc.h>
 
 #include "at91_aic.h"
 #include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e8a2e075a1b8..3e8ec26e39dc 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
 
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include "board.h"
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index bf00d15d954d..075ec0576ada 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/clk-provider.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -26,6 +27,13 @@
 #include "at91_aic.h"
 #include "generic.h"
 
+static void __init sama5_dt_timer_init(void)
+{
+#if defined(CONFIG_COMMON_CLK)
+        of_clk_init(NULL);
+#endif
+        at91sam926x_pit_init();
+}
 
 static const struct of_device_id irq_of_match[] __initconst = {
 
@@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
 
 DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
         /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = sama5_dt_timer_init,
         .map_io         = at91_map_io,
         .handle_irq     = at91_aic5_handle_irq,
         .init_early     = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
deleted file mode 100644
index aa3bc9b0f150..000000000000
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-qil-a9260.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *  Copyright (C) 2007 Calao-systems
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/clk.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-
-#include "at91_aic.h"
-#include "at91_shdwc.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.000 MHz crystal */
-        at91_initialize(12000000);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if defined(CONFIG_RTC_DRV_M41T94)
-        {       /* M41T94 RTC */
-                .modalias       = "m41t94",
-                .chip_select    = 0,
-                .max_speed_hz   = 1 * 1000 * 1000,
-                .bus_num        = 0,
-        }
-#endif
-};
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA31,
-        .is_rmii        = 1,
-};
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Uboot & Kernel",
-                .offset = 0,
-                .size   = SZ_16M,
-        },
-        {
-                .name   = "Root FS",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        },
-        {
-                .name   = "FS",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        },
-};
-
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* USER PUSH BUTTON */
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB10,
-                .active_low     = 1,
-                .desc           = "user_pb",
-                .wakeup         = 1,
-        }
-};
-
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
-        at91_set_deglitch(AT91_PIN_PB10, 1);
-
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* user_led (green) */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PB21,
-                .active_low             = 0,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-
-        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* MMC */
-        at91_add_device_mci(0, &ek_mci0_data);
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* shutdown controller, wakeup button (5 msec low) */
-        at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
-                                | AT91_SHDW_RTTWKEN);
-}
-
-MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b2630a92f71..034529d801b2 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of_address.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <mach/hardware.h>
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include <asm/proc-fns.h>
@@ -330,8 +330,6 @@ EXPORT_SYMBOL(clk_get_rate);
 
 /*------------------------------------------------------------------------*/
 
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
-
 /*
  * For now, only the programmable clocks support reparenting (MCK could
  * do this too, with care) or rate changing (the PLLs could do this too,
@@ -459,8 +457,6 @@ static void __init init_programmable_clock(struct clk *clk)
         clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 }
 
-#endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
-
 /*------------------------------------------------------------------------*/
 
 #ifdef CONFIG_DEBUG_FS
@@ -577,12 +573,10 @@ int __init clk_register(struct clk *clk)
                 clk->parent = &mck;
                 clk->mode = pmc_sys_mode;
         }
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
         else if (clk_is_programmable(clk)) {
                 clk->mode = pmc_sys_mode;
                 init_programmable_clock(clk);
         }
-#endif
 
         at91_clk_add(clk);
 
@@ -884,6 +878,11 @@ static int __init at91_pmc_init(unsigned long main_clock)
 #if defined(CONFIG_OF)
 static struct of_device_id pmc_ids[] = {
         { .compatible = "atmel,at91rm9200-pmc" },
+        { .compatible = "atmel,at91sam9260-pmc" },
+        { .compatible = "atmel,at91sam9g45-pmc" },
+        { .compatible = "atmel,at91sam9n12-pmc" },
+        { .compatible = "atmel,at91sam9x5-pmc" },
+        { .compatible = "atmel,sama5d3-pmc" },
         { /*sentinel*/ }
 };
 
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 26dee3ce9397..631fa3b8c16d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void);
 extern void at91x40_timer_init(void);
 
  /* Clocks */
-#ifdef CONFIG_AT91_PMC_UNIT
+#ifdef CONFIG_OLD_CLK_AT91
 extern int __init at91_clock_init(unsigned long main_clock);
 extern int __init at91_dt_clock_init(void);
 #else
 static int inline at91_clock_init(unsigned long main_clock) { return 0; }
+static int inline at91_dt_clock_init(void) { return 0; }
 #endif
 struct device;
 
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
deleted file mode 100644
index c604cc69acb5..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_pmc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_pmc_base;
-
-#define at91_pmc_read(field) \
-        __raw_readl(at91_pmc_base + field)
-
-#define at91_pmc_write(field, value) \
-        __raw_writel(value, at91_pmc_base + field)
-#else
-.extern at91_pmc_base
-#endif
-
-#define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
-#define AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
-
-#define AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
-#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
-#define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
-#define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
-#define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
-#define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
-#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
-#define         AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
-#define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
-#define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
-
-#define AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
-#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
-#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
-#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
-#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
-
-#define AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
-#define         AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
-#define         AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
-#define         AT91_PMC_OSCOUNT        (0xff <<  8)            /* Main Oscillator Start-up Time */
-#define         AT91_PMC_KEY            (0x37 << 16)            /* MOR Writing Key */
-#define         AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
-#define         AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
-
-#define AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
-#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
-#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
-
-#define AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
-#define AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
-#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
-#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
-#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
-#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
-#define         AT91_PMC_MUL_GET(n)     ((n) >> 16 & 0x7ff)
-#define         AT91_PMC3_MUL           (0x7f  << 18)           /* PLL Multiplier [SAMA5 only] */
-#define         AT91_PMC3_MUL_GET(n)    ((n) >> 18 & 0x7f)
-#define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
-#define                 AT91_PMC_USBDIV_1               (0 << 28)
-#define                 AT91_PMC_USBDIV_2               (1 << 28)
-#define                 AT91_PMC_USBDIV_4               (2 << 28)
-#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
-
-#define AT91_PMC_MCKR           0x30                    /* Master Clock Register */
-#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
-#define                 AT91_PMC_CSS_SLOW               (0 << 0)
-#define                 AT91_PMC_CSS_MAIN               (1 << 0)
-#define                 AT91_PMC_CSS_PLLA               (2 << 0)
-#define                 AT91_PMC_CSS_PLLB               (3 << 0)
-#define                 AT91_PMC_CSS_UPLL               (3 << 0)        /* [some SAM9 only] */
-#define         PMC_PRES_OFFSET         2
-#define         AT91_PMC_PRES           (7 <<  PMC_PRES_OFFSET)         /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_2                 (1 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_4                 (2 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_8                 (3 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_16                (4 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_32                (5 << PMC_PRES_OFFSET)
-#define                 AT91_PMC_PRES_64                (6 << PMC_PRES_OFFSET)
-#define         PMC_ALT_PRES_OFFSET     4
-#define         AT91_PMC_ALT_PRES       (7 <<  PMC_ALT_PRES_OFFSET)             /* Master Clock Prescaler [alternate location] */
-#define                 AT91_PMC_ALT_PRES_1             (0 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_2             (1 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_4             (2 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_8             (3 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_16            (4 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_32            (5 << PMC_ALT_PRES_OFFSET)
-#define                 AT91_PMC_ALT_PRES_64            (6 << PMC_ALT_PRES_OFFSET)
-#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
-#define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
-#define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
-#define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
-#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9 only] */
-#define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
-#define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
-#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)        /* [some SAM9 only] */
-#define                 AT91SAM9_PMC_MDIV_3             (3 << 8)        /* [some SAM9 only] */
-#define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
-#define                 AT91_PMC_PDIV_1                 (0 << 12)
-#define                 AT91_PMC_PDIV_2                 (1 << 12)
-#define         AT91_PMC_PLLADIV2       (1 << 12)               /* PLLA divisor by 2 [some SAM9 only] */
-#define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
-#define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
-
-#define AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
-#define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
-#define                 AT91_PMC_USBS_PLLA              (0 << 0)
-#define                 AT91_PMC_USBS_UPLL              (1 << 0)
-#define                 AT91_PMC_USBS_PLLB              (1 << 0)        /* [AT91SAMN12 only] */
-#define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
-#define                 AT91_PMC_OHCIUSBDIV_1   (0x0 <<  8)
-#define                 AT91_PMC_OHCIUSBDIV_2   (0x1 <<  8)
-
-#define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
-#define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
-#define         AT91_PMC_SMD_DIV        (0x1f <<  8)            /* SMD input clock divider */
-#define         AT91_PMC_SMDDIV(n)      (((n) <<  8) & AT91_PMC_SMD_DIV)
-
-#define AT91_PMC_PCKR(n)        (0x40 + ((n) * 4))      /* Programmable Clock 0-N Registers */
-#define         AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)             /* Programmable Clock Source Selection [alternate length] */
-#define                 AT91_PMC_CSS_MASTER             (4 << 0)        /* [some SAM9 only] */
-#define         AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
-#define                 AT91_PMC_CSSMCK_CSS             (0 << 8)
-#define                 AT91_PMC_CSSMCK_MCK             (1 << 8)
-
-#define AT91_PMC_IER            0x60                    /* Interrupt Enable Register */
-#define AT91_PMC_IDR            0x64                    /* Interrupt Disable Register */
-#define AT91_PMC_SR             0x68                    /* Status Register */
-#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
-#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
-#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
-#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9] */
-#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define         AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
-#define         AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
-#define         AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
-#define AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
-
-#define AT91_PMC_PROT           0xe4                    /* Write Protect Mode Register [some SAM9] */
-#define         AT91_PMC_WPEN           (0x1  <<  0)            /* Write Protect Enable */
-#define         AT91_PMC_WPKEY          (0xffffff << 8)         /* Write Protect Key */
-#define         AT91_PMC_PROTKEY        (0x504d43 << 8)         /* Activation Code */
-
-#define AT91_PMC_WPSR           0xe8                    /* Write Protect Status Register [some SAM9] */
-#define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
-#define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
-
-#define AT91_PMC_PCER1          0x100                   /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
-#define AT91_PMC_PCDR1          0x104                   /* Peripheral Clock Enable Register 1 */
-#define AT91_PMC_PCSR1          0x108                   /* Peripheral Clock Enable Register 1 */
-
-#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9 and SAMA5] */
-#define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
-#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command (read=0, write=1) */
-#define         AT91_PMC_PCR_DIV(n)     ((n)  <<  16)           /* Divisor Value */
-#define                 AT91_PMC_PCR_DIV0       0x0                     /* Peripheral clock is MCK */
-#define                 AT91_PMC_PCR_DIV2       0x1                     /* Peripheral clock is MCK/2 */
-#define                 AT91_PMC_PCR_DIV4       0x2                     /* Peripheral clock is MCK/4 */
-#define                 AT91_PMC_PCR_DIV8       0x3                     /* Peripheral clock is MCK/8 */
-#define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index d3d7b993846b..86c71debab5b 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -53,6 +53,7 @@
 #define ARCH_EXID_SAMA5D33      0x00414300
 #define ARCH_EXID_SAMA5D34      0x00414301
 #define ARCH_EXID_SAMA5D35      0x00584300
+#define ARCH_EXID_SAMA5D36      0x00004301
 
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
@@ -105,7 +106,7 @@ enum at91_soc_subtype {
 
         /* SAMA5D3 */
         AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
-        AT91_SOC_SAMA5D35,
+        AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
 
         /* No subtype for this SoC */
         AT91_SOC_SUBTYPE_NONE,
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9986542e8060..590b52dea9f7 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include "at91_aic.h"
@@ -155,9 +155,6 @@ static int at91_pm_verify_clocks(void)
                 }
         }
 
-        if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS))
-                return 1;
-
         /* PCK0..PCK3 must be disabled, or configured to use clk32k */
         for (i = 0; i < 4; i++) {
                 u32 css;
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28ddf025..20018779bae7 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
  */
 
 #include <linux/linkage.h>
+#include <linux/clk/at91_pmc.h>
 #include <mach/hardware.h>
-#include <mach/at91_pmc.h>
 #include <mach/at91_ramc.h>
 
 
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 99a0a1d2b7dc..b26156bf15db 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -101,7 +101,7 @@ static void sam9_smc_cs_read(void __iomem *base,
         /* Pulse register */
         val = __raw_readl(base + AT91_SMC_PULSE);
 
-        config->nwe_setup = val & AT91_SMC_NWEPULSE;
+        config->nwe_pulse = val & AT91_SMC_NWEPULSE;
         config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
         config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
         config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index a28873fe3049..3d775d08de08 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,360 +9,19 @@
 
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/sama5d3.h>
-#include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
-#include "clock.h"
 #include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pid            = SAMA5D3_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pid            = SAMA5D3_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pid            = SAMA5D3_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
-        .name           = "pioD_clk",
-        .pid            = SAMA5D3_ID_PIOD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioE_clk = {
-        .name           = "pioE_clk",
-        .pid            = SAMA5D3_ID_PIOE,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pid            = SAMA5D3_ID_USART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pid            = SAMA5D3_ID_USART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pid            = SAMA5D3_ID_USART2,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pid            = SAMA5D3_ID_USART3,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart0_clk = {
-        .name           = "uart0_clk",
-        .pid            = SAMA5D3_ID_UART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart1_clk = {
-        .name           = "uart1_clk",
-        .pid            = SAMA5D3_ID_UART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pid            = SAMA5D3_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV8,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pid            = SAMA5D3_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV8,
-};
-static struct clk twi2_clk = {
-        .name           = "twi2_clk",
-        .pid            = SAMA5D3_ID_TWI2,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV8,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pid            = SAMA5D3_ID_HSMCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pid            = SAMA5D3_ID_HSMCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc2_clk = {
-        .name           = "mci2_clk",
-        .pid            = SAMA5D3_ID_HSMCI2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pid            = SAMA5D3_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pid            = SAMA5D3_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
-        .name           = "tcb0_clk",
-        .pid            = SAMA5D3_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk tcb1_clk = {
-        .name           = "tcb1_clk",
-        .pid            = SAMA5D3_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pid            = SAMA5D3_ID_ADC,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_op_clk = {
-        .name           = "adc_op_clk",
-        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 5000000,
-};
-static struct clk dma0_clk = {
-        .name           = "dma0_clk",
-        .pid            = SAMA5D3_ID_DMA0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
-        .name           = "dma1_clk",
-        .pid            = SAMA5D3_ID_DMA1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
-        .name           = "uhphs",
-        .pid            = SAMA5D3_ID_UHPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pid            = SAMA5D3_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* gmac only for sama5d33, sama5d34, sama5d35 */
-static struct clk macb0_clk = {
-        .name           = "macb0_clk",
-        .pid            = SAMA5D3_ID_GMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* emac only for sama5d31, sama5d35 */
-static struct clk macb1_clk = {
-        .name           = "macb1_clk",
-        .pid            = SAMA5D3_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* lcd only for sama5d31, sama5d33, sama5d34 */
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pid            = SAMA5D3_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* isi only for sama5d33, sama5d35 */
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pid            = SAMA5D3_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can0_clk = {
-        .name           = "can0_clk",
-        .pid            = SAMA5D3_ID_CAN0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk can1_clk = {
-        .name           = "can1_clk",
-        .pid            = SAMA5D3_ID_CAN1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pid            = SAMA5D3_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pid            = SAMA5D3_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV2,
-};
-static struct clk sha_clk = {
-        .name           = "sha_clk",
-        .pid            = SAMA5D3_ID_SHA,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .div            = AT91_PMC_PCR_DIV8,
-};
-static struct clk aes_clk = {
-        .name           = "aes_clk",
-        .pid            = SAMA5D3_ID_AES,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tdes_clk = {
-        .name           = "tdes_clk",
-        .pid            = SAMA5D3_ID_TDES,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &pioD_clk,
-        &pioE_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &usart3_clk,
-        &uart0_clk,
-        &uart1_clk,
-        &twi0_clk,
-        &twi1_clk,
-        &twi2_clk,
-        &mmc0_clk,
-        &mmc1_clk,
-        &mmc2_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &tcb0_clk,
-        &tcb1_clk,
-        &adc_clk,
-        &adc_op_clk,
-        &dma0_clk,
-        &dma1_clk,
-        &uhphs_clk,
-        &udphs_clk,
-        &macb0_clk,
-        &macb1_clk,
-        &lcdc_clk,
-        &isi_clk,
-        &can0_clk,
-        &can1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &sha_clk,
-        &aes_clk,
-        &tdes_clk,
-};
-
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
-        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
-        CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
-        CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
-        CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
-        CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
-        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
-        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
-        CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
-        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
-        CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
-        CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
-        CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
-        CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
-};
-
-static void __init sama5d3_register_clocks(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-}
-
-/* --------------------------------------------------------------------
  *  AT91SAM9x5 processor initialization
  * -------------------------------------------------------------------- */
 
@@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void)
 
 AT91_SOC_START(sama5d3)
         .map_io = sama5d3_map_io,
-        .register_clocks = sama5d3_register_clocks,
         .init = sama5d3_initialize,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 094b3459c288..f7ca97b7291e 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
 #include <linux/pm.h>
 #include <linux/of_address.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/clk/at91_pmc.h>
 
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -18,7 +19,6 @@
 #include <mach/hardware.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
 
 #include "at91_shdwc.h"
 #include "soc.h"
@@ -81,7 +81,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 
         desc->pfn = __phys_to_pfn(base);
         desc->length = length;
-        desc->type = MT_MEMORY_NONCACHED;
+        desc->type = MT_MEMORY_RWX_NONCACHED;
 
         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
                 base, length, desc->virtual);
@@ -233,6 +233,9 @@ static void __init soc_detect(u32 dbgu_base)
                 case ARCH_EXID_SAMA5D35:
                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
                         break;
+                case ARCH_EXID_SAMA5D36:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
+                        break;
                 }
         }
 }
@@ -275,6 +278,7 @@ static const char *soc_subtype_name[] = {
         [AT91_SOC_SAMA5D33]     = "sama5d33",
         [AT91_SOC_SAMA5D34]     = "sama5d34",
         [AT91_SOC_SAMA5D35]     = "sama5d35",
+        [AT91_SOC_SAMA5D36]     = "sama5d36",
         [AT91_SOC_SUBTYPE_NONE] = "None",
         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 };
@@ -491,7 +495,8 @@ void __init at91rm9200_dt_initialize(void)
         at91_dt_clock_init();
 
         /* Register the processor-specific clocks */
-        at91_boot_soc.register_clocks();
+        if (at91_boot_soc.register_clocks)
+                at91_boot_soc.register_clocks();
 
         at91_boot_soc.init();
 }
@@ -506,7 +511,8 @@ void __init at91_dt_initialize(void)
         at91_dt_clock_init();
 
         /* Register the processor-specific clocks */
-        at91_boot_soc.register_clocks();
+        if (at91_boot_soc.register_clocks)
+                at91_boot_soc.register_clocks();
 
         if (at91_boot_soc.init)
                 at91_boot_soc.init();
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 9fe6d88737ed..b1aa6a9b3bd1 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -25,6 +25,7 @@ config ARCH_BCM_MOBILE
         select TICK_ONESHOT
         select CACHE_L2X0
         select HAVE_ARM_ARCH_TIMER
+        select PINCTRL
         help
           This enables support for systems based on Broadcom mobile SoCs.
           It currently supports the 'BCM281XX' family, which includes
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
index 560045cafc34..d1f9612f8c15 100644
--- a/arch/arm/mach-bcm2835/Kconfig
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -12,4 +12,4 @@ config ARCH_BCM2835
         select PINCTRL_BCM2835
         help
           This enables support for the Broadcom BCM2835 SoC. This SoC is
-          use in the Raspberry Pi, and Roku 2 devices.
+          used in the Raspberry Pi and Roku 2 devices.
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
new file mode 100644
index 000000000000..7a02d222c378
--- /dev/null
+++ b/arch/arm/mach-berlin/Kconfig
@@ -0,0 +1,29 @@
+config ARCH_BERLIN
+        bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+        select ARM_GIC
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select COMMON_CLK
+        select DW_APB_ICTL
+        select DW_APB_TIMER_OF
+
+if ARCH_BERLIN
+
+menu "Marvell Berlin SoC variants"
+
+config MACH_BERLIN_BG2
+        bool "Marvell Armada 1500 (BG2)"
+        select CACHE_L2X0
+        select CPU_PJ4B
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
+
+config MACH_BERLIN_BG2CD
+        bool "Marvell Armada 1500-mini (BG2CD)"
+        select CACHE_L2X0
+        select CPU_V7
+        select HAVE_ARM_TWD if SMP
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile
new file mode 100644
index 000000000000..ab69fe956f49
--- /dev/null
+++ b/arch/arm/mach-berlin/Makefile
@@ -0,0 +1 @@
+obj-y += berlin.o
diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c
new file mode 100644
index 000000000000..025bcb5473eb
--- /dev/null
+++ b/arch/arm/mach-berlin/berlin.c
@@ -0,0 +1,39 @@
+/*
+ * Device Tree support for Marvell Berlin SoCs.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+
+static void __init berlin_init_machine(void)
+{
+        /*
+         * with DT probing for L2CCs, berlin_init_machine can be removed.
+         * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
+         */
+        l2x0_of_init(0x70c00000, 0xfeffffff);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const berlin_dt_compat[] = {
+        "marvell,berlin",
+        NULL,
+};
+
+DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
+        .dt_compat      = berlin_dt_compat,
+        .init_machine   = berlin_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 134641d688bb..a1935911e4f1 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -259,7 +259,7 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
         } while (1);
 }
 
-static u32 notrace clps711x_sched_clock_read(void)
+static u64 notrace clps711x_sched_clock_read(void)
 {
         return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
 }
@@ -366,7 +366,7 @@ void __init clps711x_timer_init(void)
         tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
         clps_writel(tmp, SYSCON1);
 
-        setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+        sched_clock_register(clps711x_sched_clock_read, 16, timl);
 
         clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
                               "clps711x_clocksource", timl, 300, 16,
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index fb77d1448fec..2001488a5ef2 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -61,8 +61,29 @@ static void __init clps711x_add_syscon(void)
                                                 &clps711x_syscon_res[i], 1);
 }
 
+static const struct resource clps711x_uart1_res[] __initconst = {
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR1, SZ_128),
+        DEFINE_RES_IRQ(IRQ_UTXINT1),
+        DEFINE_RES_IRQ(IRQ_URXINT1),
+};
+
+static const struct resource clps711x_uart2_res[] __initconst = {
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR2, SZ_128),
+        DEFINE_RES_IRQ(IRQ_UTXINT2),
+        DEFINE_RES_IRQ(IRQ_URXINT2),
+};
+
+static void __init clps711x_add_uart(void)
+{
+        platform_device_register_simple("clps711x-uart", 0, clps711x_uart1_res,
+                                        ARRAY_SIZE(clps711x_uart1_res));
+        platform_device_register_simple("clps711x-uart", 1, clps711x_uart2_res,
+                                        ARRAY_SIZE(clps711x_uart2_res));
+};
+
 void __init clps711x_devices_init(void)
 {
         clps711x_add_gpio();
         clps711x_add_syscon();
+        clps711x_add_uart();
 }
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index dc9a470ff9c5..985e5fd00fb2 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -133,7 +133,7 @@ EXPORT_SYMBOL(clk_get_rate);
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
         if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
+                return 0;
 
         if (clk->round_rate)
                 return clk->round_rate(clk, rate);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 0813b5167e05..115d5736da80 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -385,7 +385,7 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
         CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
         CLK(NULL,               "timer0",       &timerp64_0_clk),
-        CLK("watchdog",         NULL,           &timerp64_1_clk),
+        CLK("davinci-wdt",      NULL,           &timerp64_1_clk),
         CLK(NULL,               "arm_rom",      &arm_rom_clk),
         CLK(NULL,               "scr0_ss",      &scr0_ss_clk),
         CLK(NULL,               "scr1_ss",      &scr1_ss_clk),
@@ -1153,7 +1153,6 @@ static struct davinci_id da830_ids[] = {
 
 static struct davinci_gpio_platform_data da830_gpio_platform_data = {
         .ngpio = 128,
-        .intc_irq_num = DA830_N_CP_INTC_IRQ,
 };
 
 int __init da830_register_gpio(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 352984e1528a..2ab00434b2eb 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -443,7 +443,7 @@ static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "pll1_sysclk3", &pll1_sysclk3),
         CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
         CLK(NULL,               "timer0",       &timerp64_0_clk),
-        CLK("watchdog",         NULL,           &timerp64_1_clk),
+        CLK("davinci-wdt",      NULL,           &timerp64_1_clk),
         CLK(NULL,               "arm_rom",      &arm_rom_clk),
         CLK(NULL,               "tpcc0",        &tpcc0_clk),
         CLK(NULL,               "tptc0",        &tptc0_clk),
@@ -1283,7 +1283,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config
 
 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
         .ngpio = 144,
-        .intc_irq_num = DA850_N_CP_INTC_IRQ,
 };
 
 int __init da850_register_gpio(void)
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index d2bc574ae172..ed1928740b5f 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -32,7 +32,7 @@ static void __init da8xx_init_irq(void)
 
 static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
-        OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
+        OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL),
         OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
         OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL),
         OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL),
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 78829c513fdc..0486cdf28c8d 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -389,7 +389,7 @@ static struct resource da8xx_watchdog_resources[] = {
 };
 
 static struct platform_device da8xx_wdt_device = {
-        .name           = "watchdog",
+        .name           = "davinci-wdt",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
         .resource       = da8xx_watchdog_resources,
@@ -399,7 +399,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd)
 {
         struct device *dev;
 
-        dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
+        dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
         if (!dev) {
                 pr_err("%s: failed to find watchdog device\n", __func__);
                 return;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3996e98f52fb..5cf9a027dcc6 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -302,7 +302,7 @@ static struct resource wdt_resources[] = {
 };
 
 struct platform_device davinci_wdt_device = {
-        .name           = "watchdog",
+        .name           = "davinci-wdt",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(wdt_resources),
         .resource       = wdt_resources,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 6117fc644188..4668c0e19767 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -375,7 +375,7 @@ static struct clk_lookup dm355_clks[] = {
         CLK(NULL, "pwm3", &pwm3_clk),
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
-        CLK("watchdog", NULL, &timer2_clk),
+        CLK("davinci-wdt", NULL, &timer2_clk),
         CLK(NULL, "timer3", &timer3_clk),
         CLK(NULL, "rto", &rto_clk),
         CLK(NULL, "usb", &usb_clk),
@@ -901,7 +901,6 @@ static struct resource dm355_gpio_resources[] = {
 
 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
         .ngpio          = 104,
-        .intc_irq_num   = DAVINCI_N_AINTC_IRQ,
 };
 
 int __init dm355_gpio_register(void)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index d7c6f85d3fc9..b44b49e2801a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -473,7 +473,7 @@ static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "pwm3", &pwm3_clk),
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
-        CLK("watchdog", NULL, &timer2_clk),
+        CLK("davinci-wdt", NULL, &timer2_clk),
         CLK(NULL, "timer3", &timer3_clk),
         CLK(NULL, "usb", &usb_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
@@ -713,7 +713,6 @@ static struct resource dm365_gpio_resources[] = {
 
 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
         .ngpio          = 104,
-        .intc_irq_num   = DAVINCI_N_AINTC_IRQ,
         .gpio_unbanked  = 8,
 };
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 3ce47997bb46..5c3e0be95ef3 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -322,7 +322,7 @@ static struct clk_lookup dm644x_clks[] = {
         CLK(NULL, "pwm2", &pwm2_clk),
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
-        CLK("watchdog", NULL, &timer2_clk),
+        CLK("davinci-wdt", NULL, &timer2_clk),
         CLK(NULL, NULL, NULL),
 };
 
@@ -787,7 +787,6 @@ static struct resource dm644_gpio_resources[] = {
 
 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
         .ngpio          = 71,
-        .intc_irq_num   = DAVINCI_N_AINTC_IRQ,
 };
 
 int __init dm644x_gpio_register(void)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0e81fea65e7f..81768dd47096 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -356,7 +356,7 @@ static struct clk_lookup dm646x_clks[] = {
         CLK(NULL, "pwm1", &pwm1_clk),
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
-        CLK("watchdog", NULL, &timer2_clk),
+        CLK("davinci-wdt", NULL, &timer2_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
         CLK(NULL, "vpif0", &vpif0_clk),
         CLK(NULL, "vpif1", &vpif1_clk),
@@ -763,7 +763,6 @@ static struct resource dm646x_gpio_resources[] = {
 
 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
         .ngpio          = 43,
-        .intc_irq_num   = DAVINCI_N_AINTC_IRQ,
 };
 
 int __init dm646x_gpio_register(void)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 56c6eb5266ad..24ad30f32ae3 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -285,7 +285,7 @@ static struct clocksource clocksource_davinci = {
 /*
  * Overwrite weak default sched_clock with something more precise
  */
-static u32 notrace davinci_read_sched_clock(void)
+static u64 notrace davinci_read_sched_clock(void)
 {
         return timer32_read(&timers[TID_CLOCKSOURCE]);
 }
@@ -391,7 +391,7 @@ void __init davinci_timer_init(void)
                                     davinci_clock_tick_rate))
                 printk(err, clocksource_davinci.name);
 
-        setup_sched_clock(davinci_read_sched_clock, 32,
+        sched_clock_register(davinci_read_sched_clock, 32,
                           davinci_clock_tick_rate);
 
         /* setup clockevent */
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c122bcff9f7c..0d1a89298ece 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -162,7 +162,7 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init dove_rtc_init(void)
+static void __init dove_rtc_init(void)
 {
         orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
 }
@@ -257,18 +257,9 @@ void __init dove_timer_init(void)
 }
 
 /*****************************************************************************
- * Cryptographic Engines and Security Accelerator (CESA)
- ****************************************************************************/
-void __init dove_crypto_init(void)
-{
-        orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
-                          DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
-}
-
-/*****************************************************************************
  * XOR 0
  ****************************************************************************/
-void __init dove_xor0_init(void)
+static void __init dove_xor0_init(void)
 {
         orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
                         IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
@@ -277,7 +268,7 @@ void __init dove_xor0_init(void)
 /*****************************************************************************
  * XOR 1
  ****************************************************************************/
-void __init dove_xor1_init(void)
+static void __init dove_xor1_init(void)
 {
         orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
                         IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
diff --git a/arch/arm/mach-efm32/Makefile b/arch/arm/mach-efm32/Makefile
new file mode 100644
index 000000000000..3a74af7413e8
--- /dev/null
+++ b/arch/arm/mach-efm32/Makefile
@@ -0,0 +1 @@
+obj-y += dtmachine.o
diff --git a/arch/arm/mach-efm32/Makefile.boot b/arch/arm/mach-efm32/Makefile.boot
new file mode 100644
index 000000000000..eacfc3f5c33e
--- /dev/null
+++ b/arch/arm/mach-efm32/Makefile.boot
@@ -0,0 +1,3 @@
+# Empty file waiting for deletion once Makefile.boot isn't needed any more.
+# Patch waits for application at
+# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-efm32/dtmachine.c b/arch/arm/mach-efm32/dtmachine.c
new file mode 100644
index 000000000000..2367495193c1
--- /dev/null
+++ b/arch/arm/mach-efm32/dtmachine.c
@@ -0,0 +1,15 @@
+#include <linux/kernel.h>
+
+#include <asm/v7m.h>
+
+#include <asm/mach/arch.h>
+
+static const char *const efm32gg_compat[] __initconst = {
+        "efm32,dk3750",
+        NULL
+};
+
+DT_MACHINE_START(EFM32DT, "EFM32 (Device Tree Support)")
+        .dt_compat = efm32gg_compat,
+        .restart = armv7m_restart,
+MACHINE_END
diff --git a/arch/arm/mach-efm32/include/mach/entry-macro.S b/arch/arm/mach-efm32/include/mach/entry-macro.S
new file mode 100644
index 000000000000..322159d5ed91
--- /dev/null
+++ b/arch/arm/mach-efm32/include/mach/entry-macro.S
@@ -0,0 +1,4 @@
+/*
+ * Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any
+ * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next.
+ */
diff --git a/arch/arm/mach-efm32/include/mach/timex.h b/arch/arm/mach-efm32/include/mach/timex.h
new file mode 100644
index 000000000000..7a8b26da6599
--- /dev/null
+++ b/arch/arm/mach-efm32/include/mach/timex.h
@@ -0,0 +1,3 @@
+/*
+ * Empty file waiting for deletion once <mach/timex.h> isn't needed any more.
+ */
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 93e54fd4e3d5..bec570ae6494 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -5,6 +5,7 @@ menu "Cirrus EP93xx Implementation Options"
 config EP93XX_SOC_COMMON
         bool
         default y
+        select SOC_BUS
         select LEDS_GPIO_REGISTER
 
 config CRUNCH
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index d95ee28a616a..157ba88433c9 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -21,6 +21,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
+#include <linux/sys_soc.h>
 #include <linux/timex.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -44,6 +45,7 @@
 #include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
@@ -137,7 +139,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction ep93xx_timer_irq = {
         .name           = "ep93xx timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = ep93xx_timer_interrupt,
 };
 
@@ -925,8 +927,108 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev)
 }
 EXPORT_SYMBOL(ep93xx_ide_release_gpio);
 
-void __init ep93xx_init_devices(void)
+/*************************************************************************
+ * EP93xx Security peripheral
+ *************************************************************************/
+
+/*
+ * The Maverick Key is 256 bits of micro fuses blown at the factory during
+ * manufacturing to uniquely identify a part.
+ *
+ * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
+ */
+#define EP93XX_SECURITY_REG(x)          (EP93XX_SECURITY_BASE + (x))
+#define EP93XX_SECURITY_SECFLG          EP93XX_SECURITY_REG(0x2400)
+#define EP93XX_SECURITY_FUSEFLG         EP93XX_SECURITY_REG(0x2410)
+#define EP93XX_SECURITY_UNIQID          EP93XX_SECURITY_REG(0x2440)
+#define EP93XX_SECURITY_UNIQCHK         EP93XX_SECURITY_REG(0x2450)
+#define EP93XX_SECURITY_UNIQVAL         EP93XX_SECURITY_REG(0x2460)
+#define EP93XX_SECURITY_SECID1          EP93XX_SECURITY_REG(0x2500)
+#define EP93XX_SECURITY_SECID2          EP93XX_SECURITY_REG(0x2504)
+#define EP93XX_SECURITY_SECCHK1         EP93XX_SECURITY_REG(0x2520)
+#define EP93XX_SECURITY_SECCHK2         EP93XX_SECURITY_REG(0x2524)
+#define EP93XX_SECURITY_UNIQID2         EP93XX_SECURITY_REG(0x2700)
+#define EP93XX_SECURITY_UNIQID3         EP93XX_SECURITY_REG(0x2704)
+#define EP93XX_SECURITY_UNIQID4         EP93XX_SECURITY_REG(0x2708)
+#define EP93XX_SECURITY_UNIQID5         EP93XX_SECURITY_REG(0x270c)
+
+static char ep93xx_soc_id[33];
+
+static const char __init *ep93xx_get_soc_id(void)
 {
+        unsigned int id, id2, id3, id4, id5;
+
+        if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
+                return "bad Hamming code";
+
+        id = __raw_readl(EP93XX_SECURITY_UNIQID);
+        id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
+        id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
+        id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
+        id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
+
+        if (id != id2)
+                return "invalid";
+
+        snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
+                 "%08x%08x%08x%08x", id2, id3, id4, id5);
+
+        return ep93xx_soc_id;
+}
+
+static const char __init *ep93xx_get_soc_rev(void)
+{
+        int rev = ep93xx_chip_revision();
+
+        switch (rev) {
+        case EP93XX_CHIP_REV_D0:
+                return "D0";
+        case EP93XX_CHIP_REV_D1:
+                return "D1";
+        case EP93XX_CHIP_REV_E0:
+                return "E0";
+        case EP93XX_CHIP_REV_E1:
+                return "E1";
+        case EP93XX_CHIP_REV_E2:
+                return "E2";
+        default:
+                return "unknown";
+        }
+}
+
+static const char __init *ep93xx_get_machine_name(void)
+{
+        return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
+}
+
+static struct device __init *ep93xx_init_soc(void)
+{
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return NULL;
+
+        soc_dev_attr->machine = ep93xx_get_machine_name();
+        soc_dev_attr->family = "Cirrus Logic EP93xx";
+        soc_dev_attr->revision = ep93xx_get_soc_rev();
+        soc_dev_attr->soc_id = ep93xx_get_soc_id();
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->machine);
+                kfree(soc_dev_attr);
+                return NULL;
+        }
+
+        return soc_device_to_device(soc_dev);
+}
+
+struct device __init *ep93xx_init_devices(void)
+{
+        struct device *parent;
+
         /* Disallow access to MaverickCrunch initially */
         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
@@ -937,6 +1039,8 @@ void __init ep93xx_init_devices(void)
                                EP93XX_SYSCON_DEVCFG_GONIDE |
                                EP93XX_SYSCON_DEVCFG_HONIDE);
 
+        parent = ep93xx_init_soc();
+
         /* Get the GPIO working early, other devices need it */
         platform_device_register(&ep93xx_gpio_device);
 
@@ -949,6 +1053,8 @@ void __init ep93xx_init_devices(void)
         platform_device_register(&ep93xx_wdt_device);
 
         gpio_led_register_device(-1, &ep93xx_led_data);
+
+        return parent;
 }
 
 void ep93xx_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index e256e0baec2e..4c0bbd97f741 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -6,6 +6,7 @@
 
 #include <linux/reboot.h>
 
+struct device;
 struct i2c_gpio_platform_data;
 struct i2c_board_info;
 struct spi_board_info;
@@ -54,7 +55,7 @@ void ep93xx_register_ide(void);
 int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
 void ep93xx_ide_release_gpio(struct platform_device *pdev);
 
-void ep93xx_init_devices(void);
+struct device *ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
 
 void ep93xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0acb2a..4c414af75ef0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,6 +24,7 @@ config ARCH_EXYNOS4
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
+        select PM_GENERIC_DOMAINS if PM
         select S5P_DEV_MFC
         help
           Samsung EXYNOS4 SoCs based systems
@@ -48,7 +49,6 @@ config CPU_EXYNOS4210
         select ARCH_HAS_BANDGAP
         select ARM_CPU_SUSPEND if PM
         select PINCTRL_EXYNOS
-        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
@@ -61,7 +61,6 @@ config SOC_EXYNOS4212
         depends on ARCH_EXYNOS4
         select ARCH_HAS_BANDGAP
         select PINCTRL_EXYNOS
-        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
@@ -74,7 +73,6 @@ config SOC_EXYNOS4412
         depends on ARCH_EXYNOS4
         select ARCH_HAS_BANDGAP
         select PINCTRL_EXYNOS
-        select PM_GENERIC_DOMAINS if PM
         select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906ccefb..f18be40e5b21 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
+#include <linux/pm_domain.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
@@ -37,14 +38,13 @@
 #include <asm/mach/irq.h>
 #include <asm/cacheflush.h>
 
-#include <mach/regs-irq.h>
-#include <mach/regs-pmu.h>
-
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 
 #include "common.h"
+#include "regs-pmu.h"
+
 #define L2_AUX_VAL 0x7C470001
 #define L2_AUX_MASK 0xC200ffff
 
@@ -303,13 +303,18 @@ void __init exynos_cpuidle_init(void)
         platform_device_register(&exynos_cpuidle);
 }
 
+void __init exynos_cpufreq_init(void)
+{
+        platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+}
+
 void __init exynos_init_late(void)
 {
         if (of_machine_is_compatible("samsung,exynos5440"))
                 /* to be supported later */
                 return;
 
-        exynos_pm_late_initcall();
+        pm_genpd_poweroff_unused();
 }
 
 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index ff9b6a9419b0..f76967b1c551 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -22,16 +22,11 @@ void exynos_init_io(void);
 void exynos4_restart(enum reboot_mode mode, const char *cmd);
 void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_cpuidle_init(void);
+void exynos_cpufreq_init(void);
 void exynos_init_late(void);
 
 void exynos_firmware_init(void);
 
-#ifdef CONFIG_PM_GENERIC_DOMAINS
-int exynos_pm_late_initcall(void);
-#else
-static inline int exynos_pm_late_initcall(void) { return 0; }
-#endif
-
 extern struct smp_operations exynos_smp_ops;
 
 extern void exynos_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ddbfe8709fe7..f57cb91f02aa 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -22,13 +22,15 @@
 #include <asm/suspend.h>
 #include <asm/unified.h>
 #include <asm/cpuidle.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
+#include <mach/pm-core.h>
+#include <mach/map.h>
+
 #include "common.h"
+#include "regs-pmu.h"
 
 #define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                         S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
@@ -39,6 +41,25 @@
 
 #define S5P_CHECK_AFTR          0xFCBA0D10
 
+#define EXYNOS5_PWR_CTRL1                       (S5P_VA_CMU + 0x01020)
+#define EXYNOS5_PWR_CTRL2                       (S5P_VA_CMU + 0x01024)
+
+#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
+
 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index);
@@ -151,8 +172,8 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
 {
         int new_index = index;
 
-        /* This mode only can be entered when other core's are offline */
-        if (num_online_cpus() > 1)
+        /* AFTR can only be entered when cores other than CPU0 are offline */
+        if (num_online_cpus() > 1 || dev->cpu != 0)
                 new_index = drv->safe_state_index;
 
         if (new_index == 0)
@@ -214,10 +235,6 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
                 device->cpu = cpu_id;
 
-                /* Support IDLE only */
-                if (cpu_id != 0)
-                        device->state_count = 1;
-
                 ret = cpuidle_register_device(device);
                 if (ret) {
                         dev_err(&pdev->dev, "failed to register cpuidle device\n");
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index af90cfa2f826..5eead530c6f8 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -19,10 +19,10 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
-#include <mach/regs-pmu.h>
 #include <plat/cpu.h>
 
 #include "common.h"
+#include "regs-pmu.h"
 
 static inline void cpu_enter_lowpower_a9(void)
 {
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 2b00833b6641..dc0697c2fa92 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -19,7 +19,10 @@
 #define __ASM_ARCH_PM_CORE_H __FILE__
 
 #include <linux/of.h>
-#include <mach/regs-pmu.h>
+#include <mach/map.h>
+
+#define S5P_EINT_WAKEUP_MASK                    (S5P_VA_PMU + 0x0604)
+#define S5P_WAKEUP_MASK                         (S5P_VA_PMU + 0x0608)
 
 #ifdef CONFIG_PINCTRL_EXYNOS
 extern u32 exynos_get_eint_wake_mask(void);
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
deleted file mode 100644
index d36ad76ad6a4..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <plat/cpu.h>
-#include <mach/map.h>
-
-#define EXYNOS_CLKREG(x)                        (S5P_VA_CMU + (x))
-
-#define EXYNOS4_CLKDIV_LEFTBUS                  EXYNOS_CLKREG(0x04500)
-#define EXYNOS4_CLKDIV_STAT_LEFTBUS             EXYNOS_CLKREG(0x04600)
-#define EXYNOS4_CLKGATE_IP_LEFTBUS              EXYNOS_CLKREG(0x04800)
-
-#define EXYNOS4_CLKDIV_RIGHTBUS                 EXYNOS_CLKREG(0x08500)
-#define EXYNOS4_CLKDIV_STAT_RIGHTBUS            EXYNOS_CLKREG(0x08600)
-#define EXYNOS4_CLKGATE_IP_RIGHTBUS             EXYNOS_CLKREG(0x08800)
-
-#define EXYNOS4_EPLL_LOCK                       EXYNOS_CLKREG(0x0C010)
-#define EXYNOS4_VPLL_LOCK                       EXYNOS_CLKREG(0x0C020)
-
-#define EXYNOS4_EPLL_CON0                       EXYNOS_CLKREG(0x0C110)
-#define EXYNOS4_EPLL_CON1                       EXYNOS_CLKREG(0x0C114)
-#define EXYNOS4_VPLL_CON0                       EXYNOS_CLKREG(0x0C120)
-#define EXYNOS4_VPLL_CON1                       EXYNOS_CLKREG(0x0C124)
-
-#define EXYNOS4_CLKSRC_TOP0                     EXYNOS_CLKREG(0x0C210)
-#define EXYNOS4_CLKSRC_TOP1                     EXYNOS_CLKREG(0x0C214)
-#define EXYNOS4_CLKSRC_CAM                      EXYNOS_CLKREG(0x0C220)
-#define EXYNOS4_CLKSRC_TV                       EXYNOS_CLKREG(0x0C224)
-#define EXYNOS4_CLKSRC_MFC                      EXYNOS_CLKREG(0x0C228)
-#define EXYNOS4_CLKSRC_G3D                      EXYNOS_CLKREG(0x0C22C)
-#define EXYNOS4_CLKSRC_IMAGE                    EXYNOS_CLKREG(0x0C230)
-#define EXYNOS4_CLKSRC_LCD0                     EXYNOS_CLKREG(0x0C234)
-#define EXYNOS4_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x0C23C)
-#define EXYNOS4_CLKSRC_FSYS                     EXYNOS_CLKREG(0x0C240)
-#define EXYNOS4_CLKSRC_PERIL0                   EXYNOS_CLKREG(0x0C250)
-#define EXYNOS4_CLKSRC_PERIL1                   EXYNOS_CLKREG(0x0C254)
-
-#define EXYNOS4_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x0C310)
-#define EXYNOS4_CLKSRC_MASK_CAM                 EXYNOS_CLKREG(0x0C320)
-#define EXYNOS4_CLKSRC_MASK_TV                  EXYNOS_CLKREG(0x0C324)
-#define EXYNOS4_CLKSRC_MASK_LCD0                EXYNOS_CLKREG(0x0C334)
-#define EXYNOS4_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x0C33C)
-#define EXYNOS4_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x0C340)
-#define EXYNOS4_CLKSRC_MASK_PERIL0              EXYNOS_CLKREG(0x0C350)
-#define EXYNOS4_CLKSRC_MASK_PERIL1              EXYNOS_CLKREG(0x0C354)
-
-#define EXYNOS4_CLKDIV_TOP                      EXYNOS_CLKREG(0x0C510)
-#define EXYNOS4_CLKDIV_CAM                      EXYNOS_CLKREG(0x0C520)
-#define EXYNOS4_CLKDIV_TV                       EXYNOS_CLKREG(0x0C524)
-#define EXYNOS4_CLKDIV_MFC                      EXYNOS_CLKREG(0x0C528)
-#define EXYNOS4_CLKDIV_G3D                      EXYNOS_CLKREG(0x0C52C)
-#define EXYNOS4_CLKDIV_IMAGE                    EXYNOS_CLKREG(0x0C530)
-#define EXYNOS4_CLKDIV_LCD0                     EXYNOS_CLKREG(0x0C534)
-#define EXYNOS4_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x0C53C)
-#define EXYNOS4_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x0C540)
-#define EXYNOS4_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x0C544)
-#define EXYNOS4_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x0C548)
-#define EXYNOS4_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x0C54C)
-#define EXYNOS4_CLKDIV_PERIL0                   EXYNOS_CLKREG(0x0C550)
-#define EXYNOS4_CLKDIV_PERIL1                   EXYNOS_CLKREG(0x0C554)
-#define EXYNOS4_CLKDIV_PERIL2                   EXYNOS_CLKREG(0x0C558)
-#define EXYNOS4_CLKDIV_PERIL3                   EXYNOS_CLKREG(0x0C55C)
-#define EXYNOS4_CLKDIV_PERIL4                   EXYNOS_CLKREG(0x0C560)
-#define EXYNOS4_CLKDIV_PERIL5                   EXYNOS_CLKREG(0x0C564)
-#define EXYNOS4_CLKDIV2_RATIO                   EXYNOS_CLKREG(0x0C580)
-
-#define EXYNOS4_CLKDIV_STAT_TOP                 EXYNOS_CLKREG(0x0C610)
-#define EXYNOS4_CLKDIV_STAT_MFC                 EXYNOS_CLKREG(0x0C628)
-
-#define EXYNOS4_CLKGATE_SCLKCAM                 EXYNOS_CLKREG(0x0C820)
-#define EXYNOS4_CLKGATE_IP_CAM                  EXYNOS_CLKREG(0x0C920)
-#define EXYNOS4_CLKGATE_IP_TV                   EXYNOS_CLKREG(0x0C924)
-#define EXYNOS4_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x0C928)
-#define EXYNOS4_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x0C92C)
-#define EXYNOS4_CLKGATE_IP_IMAGE                (soc_is_exynos4210() ? \
-                                                EXYNOS_CLKREG(0x0C930) : \
-                                                EXYNOS_CLKREG(0x04930))
-#define EXYNOS4210_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x0C930)
-#define EXYNOS4212_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x04930)
-#define EXYNOS4_CLKGATE_IP_LCD0                 EXYNOS_CLKREG(0x0C934)
-#define EXYNOS4_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x0C940)
-#define EXYNOS4_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x0C94C)
-#define EXYNOS4_CLKGATE_IP_PERIL                EXYNOS_CLKREG(0x0C950)
-#define EXYNOS4_CLKGATE_IP_PERIR                (soc_is_exynos4210() ? \
-                                                EXYNOS_CLKREG(0x0C960) : \
-                                                EXYNOS_CLKREG(0x08960))
-#define EXYNOS4210_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x0C960)
-#define EXYNOS4212_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x08960)
-#define EXYNOS4_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x0C970)
-
-#define EXYNOS4_CLKSRC_MASK_DMC                 EXYNOS_CLKREG(0x10300)
-#define EXYNOS4_CLKSRC_DMC                      EXYNOS_CLKREG(0x10200)
-#define EXYNOS4_CLKDIV_DMC0                     EXYNOS_CLKREG(0x10500)
-#define EXYNOS4_CLKDIV_DMC1                     EXYNOS_CLKREG(0x10504)
-#define EXYNOS4_CLKDIV_STAT_DMC0                EXYNOS_CLKREG(0x10600)
-#define EXYNOS4_CLKDIV_STAT_DMC1                EXYNOS_CLKREG(0x10604)
-#define EXYNOS4_CLKGATE_IP_DMC                  EXYNOS_CLKREG(0x10900)
-
-#define EXYNOS4_DMC_PAUSE_CTRL                  EXYNOS_CLKREG(0x11094)
-#define EXYNOS4_DMC_PAUSE_ENABLE                (1 << 0)
-
-#define EXYNOS4_APLL_LOCK                       EXYNOS_CLKREG(0x14000)
-#define EXYNOS4_MPLL_LOCK                       (soc_is_exynos4210() ? \
-                                                EXYNOS_CLKREG(0x14004) :  \
-                                                EXYNOS_CLKREG(0x10008))
-#define EXYNOS4_APLL_CON0                       EXYNOS_CLKREG(0x14100)
-#define EXYNOS4_APLL_CON1                       EXYNOS_CLKREG(0x14104)
-#define EXYNOS4_MPLL_CON0                       (soc_is_exynos4210() ? \
-                                                EXYNOS_CLKREG(0x14108) : \
-                                                EXYNOS_CLKREG(0x10108))
-#define EXYNOS4_MPLL_CON1                       (soc_is_exynos4210() ? \
-                                                EXYNOS_CLKREG(0x1410C) : \
-                                                EXYNOS_CLKREG(0x1010C))
-
-#define EXYNOS4_CLKSRC_CPU                      EXYNOS_CLKREG(0x14200)
-#define EXYNOS4_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x14400)
-
-#define EXYNOS4_CLKDIV_CPU                      EXYNOS_CLKREG(0x14500)
-#define EXYNOS4_CLKDIV_CPU1                     EXYNOS_CLKREG(0x14504)
-#define EXYNOS4_CLKDIV_STATCPU                  EXYNOS_CLKREG(0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x14604)
-
-#define EXYNOS4_CLKGATE_SCLKCPU                 EXYNOS_CLKREG(0x14800)
-#define EXYNOS4_CLKGATE_IP_CPU                  EXYNOS_CLKREG(0x14900)
-
-#define EXYNOS4_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x18800)
-#define EXYNOS4_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x18804)
-
-#define EXYNOS4_APLL_LOCKTIME                   (0x1C20)        /* 300us */
-
-#define EXYNOS4_APLLCON0_ENABLE_SHIFT           (31)
-#define EXYNOS4_APLLCON0_LOCKED_SHIFT           (29)
-#define EXYNOS4_APLL_VAL_1000                   ((250 << 16) | (6 << 8) | 1)
-#define EXYNOS4_APLL_VAL_800                    ((200 << 16) | (6 << 8) | 1)
-
-#define EXYNOS4_EPLLCON0_ENABLE_SHIFT           (31)
-#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
-
-#define EXYNOS4_VPLLCON0_ENABLE_SHIFT           (31)
-#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
-
-#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT        (16)
-#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK     (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT          (0)
-#define EXYNOS4_CLKDIV_CPU0_CORE_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT        (4)
-#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT        (8)
-#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT        (12)
-#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT           (16)
-#define EXYNOS4_CLKDIV_CPU0_ATB_MASK            (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT       (20)
-#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK        (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT          (24)
-#define EXYNOS4_CLKDIV_CPU0_APLL_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT         28
-#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK          (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
-
-#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT          0
-#define EXYNOS4_CLKDIV_CPU1_COPY_MASK           (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
-#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT           4
-#define EXYNOS4_CLKDIV_CPU1_HPM_MASK            (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
-#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT         8
-#define EXYNOS4_CLKDIV_CPU1_CORES_MASK          (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
-
-#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT           (0)
-#define EXYNOS4_CLKDIV_DMC0_ACP_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT       (4)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT          (8)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT           (12)
-#define EXYNOS4_CLKDIV_DMC0_DMC_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT          (16)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT          (20)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT         (24)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK          (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT        (28)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK         (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT       (0)
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK        (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT           (4)
-#define EXYNOS4_CLKDIV_DMC1_C2C_MASK            (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT           (8)
-#define EXYNOS4_CLKDIV_DMC1_PWI_MASK            (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT       (12)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT         (16)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK          (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT           (24)
-#define EXYNOS4_CLKDIV_DMC1_DPM_MASK            (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
-
-#define EXYNOS4_CLKDIV_MFC_SHIFT                (0)
-#define EXYNOS4_CLKDIV_MFC_MASK                 (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
-
-#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT        (0)
-#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT        (4)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK         (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT        (8)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT        (12)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT        (16)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT    (20)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK     (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK  (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
-
-#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT           (0)
-#define EXYNOS4_CLKDIV_BUS_GDLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
-#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT           (4)
-#define EXYNOS4_CLKDIV_BUS_GPLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
-
-#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT          (0)
-#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT          (4)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT          (8)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT          (12)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
-
-/* Only for EXYNOS4210 */
-
-#define EXYNOS4210_CLKSRC_LCD1                  EXYNOS_CLKREG(0x0C238)
-#define EXYNOS4210_CLKSRC_MASK_LCD1             EXYNOS_CLKREG(0x0C338)
-#define EXYNOS4210_CLKDIV_LCD1                  EXYNOS_CLKREG(0x0C538)
-#define EXYNOS4210_CLKGATE_IP_LCD1              EXYNOS_CLKREG(0x0C938)
-
-/* Only for EXYNOS4212 */
-
-#define EXYNOS4_CLKDIV_CAM1                     EXYNOS_CLKREG(0x0C568)
-
-#define EXYNOS4_CLKDIV_STAT_CAM1                EXYNOS_CLKREG(0x0C668)
-
-#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
-#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
-
-/* For EXYNOS5250 */
-
-#define EXYNOS5_APLL_LOCK                       EXYNOS_CLKREG(0x00000)
-#define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
-#define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
-#define EXYNOS5_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x00400)
-#define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
-#define EXYNOS5_CLKDIV_CPU1                     EXYNOS_CLKREG(0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
-
-#define EXYNOS5_PWR_CTRL1                       EXYNOS_CLKREG(0x01020)
-#define EXYNOS5_PWR_CTRL2                       EXYNOS_CLKREG(0x01024)
-
-#define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
-#define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
-
-#define EXYNOS5_CLKGATE_IP_CORE                 EXYNOS_CLKREG(0x04900)
-
-#define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
-
-#define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
-#define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
-#define EXYNOS5_EPLL_CON2                       EXYNOS_CLKREG(0x10138)
-#define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
-#define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
-#define EXYNOS5_VPLL_CON2                       EXYNOS_CLKREG(0x10148)
-#define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
-
-#define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
-#define EXYNOS5_CLKSRC_TOP1                     EXYNOS_CLKREG(0x10214)
-#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
-#define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
-#define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
-#define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
-#define EXYNOS5_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x10240)
-#define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
-#define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
-#define EXYNOS5_CLKSRC_PERIC1                   EXYNOS_CLKREG(0x10254)
-#define EXYNOS5_SCLK_SRC_ISP                    EXYNOS_CLKREG(0x10270)
-
-#define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
-#define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
-#define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
-#define EXYNOS5_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x10334)
-#define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
-#define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
-#define EXYNOS5_CLKSRC_MASK_PERIC1              EXYNOS_CLKREG(0x10354)
-
-#define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
-#define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
-#define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
-#define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
-#define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
-#define EXYNOS5_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x10544)
-#define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
-#define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
-#define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
-#define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
-#define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
-#define EXYNOS5_CLKDIV_PERIC1                   EXYNOS_CLKREG(0x1055C)
-#define EXYNOS5_CLKDIV_PERIC2                   EXYNOS_CLKREG(0x10560)
-#define EXYNOS5_CLKDIV_PERIC3                   EXYNOS_CLKREG(0x10564)
-#define EXYNOS5_CLKDIV_PERIC4                   EXYNOS_CLKREG(0x10568)
-#define EXYNOS5_CLKDIV_PERIC5                   EXYNOS_CLKREG(0x1056C)
-#define EXYNOS5_SCLK_DIV_ISP                    EXYNOS_CLKREG(0x10580)
-
-#define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
-#define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
-#define EXYNOS5_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x0C804)
-#define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
-#define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
-#define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
-#define EXYNOS5_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x10930)
-#define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
-#define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
-#define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
-#define EXYNOS5_CLKGATE_IP_PERIC                EXYNOS_CLKREG(0x10950)
-#define EXYNOS5_CLKGATE_IP_PERIS                EXYNOS_CLKREG(0x10960)
-#define EXYNOS5_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x10980)
-
-#define EXYNOS5_BPLL_CON0                       EXYNOS_CLKREG(0x20110)
-#define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
-#define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
-
-#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
-
-#define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
-
-#define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
-
-/* Compatibility defines and inclusion */
-
-#include <mach/regs-pmu.h>
-
-#define S5P_EPLL_CON                            EXYNOS4_EPLL_CON0
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h
deleted file mode 100644
index f2b50506b9f6..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <linux/irqchip/arm-gic.h>
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 4603e6bd424b..d3e54b7644d7 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -22,6 +22,7 @@
 static void __init exynos4_dt_machine_init(void)
 {
         exynos_cpuidle_init();
+        exynos_cpufreq_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a70c1e..37ea261f0f6c 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -14,10 +14,10 @@
 #include <linux/io.h>
 
 #include <asm/mach/arch.h>
-#include <mach/regs-pmu.h>
 #include <plat/mfc.h>
 
 #include "common.h"
+#include "regs-pmu.h"
 
 static void __init exynos5_dt_machine_init(void)
 {
@@ -44,6 +44,7 @@ static void __init exynos5_dt_machine_init(void)
         }
 
         exynos_cpuidle_init();
+        exynos_cpufreq_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 58b43e6f9262..8ea02f63fed9 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -27,12 +27,11 @@
 #include <asm/firmware.h>
 
 #include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
 
 #include "common.h"
+#include "regs-pmu.h"
 
 extern void exynos4_secondary_startup(void);
 
@@ -64,8 +63,7 @@ static void write_pen_release(int val)
 {
         pen_release = val;
         smp_wmb();
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 }
 
 static void __iomem *scu_base_addr(void)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c679db577269..e00025bbbe89 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -29,14 +29,37 @@
 #include <plat/pll.h>
 #include <plat/regs-srom.h>
 
-#include <mach/regs-irq.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-pmu.h>
+#include <mach/map.h>
 #include <mach/pm-core.h>
 
 #include "common.h"
+#include "regs-pmu.h"
 
-static struct sleep_save exynos4_set_clksrc[] = {
+#define EXYNOS4_EPLL_LOCK                       (S5P_VA_CMU + 0x0C010)
+#define EXYNOS4_VPLL_LOCK                       (S5P_VA_CMU + 0x0C020)
+
+#define EXYNOS4_EPLL_CON0                       (S5P_VA_CMU + 0x0C110)
+#define EXYNOS4_EPLL_CON1                       (S5P_VA_CMU + 0x0C114)
+#define EXYNOS4_VPLL_CON0                       (S5P_VA_CMU + 0x0C120)
+#define EXYNOS4_VPLL_CON1                       (S5P_VA_CMU + 0x0C124)
+
+#define EXYNOS4_CLKSRC_MASK_TOP                 (S5P_VA_CMU + 0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM                 (S5P_VA_CMU + 0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV                  (S5P_VA_CMU + 0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0                (S5P_VA_CMU + 0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO              (S5P_VA_CMU + 0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS                (S5P_VA_CMU + 0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0              (S5P_VA_CMU + 0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1              (S5P_VA_CMU + 0x0C354)
+
+#define EXYNOS4_CLKSRC_MASK_DMC                 (S5P_VA_CMU + 0x10300)
+
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
+
+#define EXYNOS4210_CLKSRC_MASK_LCD1             (S5P_VA_CMU + 0x0C338)
+
+static const struct sleep_save exynos4_set_clksrc[] = {
         { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
         { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
         { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
@@ -48,7 +71,7 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
 };
 
-static struct sleep_save exynos4210_set_clksrc[] = {
+static const struct sleep_save exynos4210_set_clksrc[] = {
         { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
 };
 
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 1703593e366c..8fd24882f0b1 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -22,9 +22,10 @@
 #include <linux/of_platform.h>
 #include <linux/sched.h>
 
-#include <mach/regs-pmu.h>
 #include <plat/devs.h>
 
+#include "regs-pmu.h"
+
 /*
  * Exynos specific wrapper around the generic power domain
  */
@@ -183,9 +184,3 @@ static __init int exynos4_pm_init_power_domain(void)
         return 0;
 }
 arch_initcall(exynos4_pm_init_power_domain);
-
-int __init exynos_pm_late_initcall(void)
-{
-        pm_genpd_poweroff_unused();
-        return 0;
-}
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d688526258..05c7ce15322a 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -13,13 +13,14 @@
 #include <linux/kernel.h>
 #include <linux/bug.h>
 
-#include <mach/regs-clock.h>
+#include <plat/cpu.h>
 
 #include "common.h"
+#include "regs-pmu.h"
 
-static struct exynos_pmu_conf *exynos_pmu_config;
+static const struct exynos_pmu_conf *exynos_pmu_config;
 
-static struct exynos_pmu_conf exynos4210_pmu_config[] = {
+static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
         /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
@@ -95,7 +96,7 @@ static struct exynos_pmu_conf exynos4210_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
+static const struct exynos_pmu_conf exynos4x12_pmu_config[] = {
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
@@ -203,7 +204,7 @@ static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos_pmu_conf exynos4412_pmu_config[] = {
+static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
         { S5P_ARM_CORE2_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE2,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL2,                 { 0x0, 0x0, 0x0 } },
@@ -213,7 +214,7 @@ static struct exynos_pmu_conf exynos4412_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos_pmu_conf exynos5250_pmu_config[] = {
+static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
         /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
         { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
         { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
@@ -317,7 +318,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static void __iomem *exynos5_list_both_cnt_feed[] = {
+static void __iomem * const exynos5_list_both_cnt_feed[] = {
         EXYNOS5_ARM_CORE0_OPTION,
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_ARM_COMMON_OPTION,
@@ -331,7 +332,7 @@ static void __iomem *exynos5_list_both_cnt_feed[] = {
         EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
 
-static void __iomem *exynos5_list_diable_wfi_wfe[] = {
+static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_FSYS_ARM_OPTION,
         EXYNOS5_ISP_ARM_OPTION,
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 2cdb63e8ce5c..7c029ce27711 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -24,31 +24,16 @@
 #define S5P_CENTRAL_SEQ_OPTION                  S5P_PMUREG(0x0208)
 
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
-#define S5P_USE_STANDBY_WFI1                    (1 << 17)
-#define S5P_USE_STANDBYWFI_ISP_ARM              (1 << 18)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
-#define S5P_USE_STANDBY_WFE1                    (1 << 25)
-#define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
 #define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
 
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
-
-#define S5P_HDMI_PHY_CONTROL                    S5P_PMUREG(0x0700)
-#define S5P_HDMI_PHY_ENABLE                     (1 << 0)
-
-#define S5P_DAC_PHY_CONTROL                     S5P_PMUREG(0x070C)
-#define S5P_DAC_PHY_ENABLE                      (1 << 0)
 
 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
-#define S5P_INFORM2                             S5P_PMUREG(0x0808)
-#define S5P_INFORM3                             S5P_PMUREG(0x080C)
-#define S5P_INFORM4                             S5P_PMUREG(0x0810)
 #define S5P_INFORM5                             S5P_PMUREG(0x0814)
 #define S5P_INFORM6                             S5P_PMUREG(0x0818)
 #define S5P_INFORM7                             S5P_PMUREG(0x081C)
@@ -119,23 +104,8 @@
 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE0_CONFIGURATION             S5P_PMUREG(0x2000)
-#define S5P_ARM_CORE0_OPTION                    S5P_PMUREG(0x2008)
 #define S5P_ARM_CORE1_CONFIGURATION             S5P_PMUREG(0x2080)
 #define S5P_ARM_CORE1_STATUS                    S5P_PMUREG(0x2084)
-#define S5P_ARM_CORE1_OPTION                    S5P_PMUREG(0x2088)
-
-#define S5P_ARM_COMMON_OPTION                   S5P_PMUREG(0x2408)
-#define S5P_TOP_PWR_OPTION                      S5P_PMUREG(0x2C48)
-#define S5P_CAM_OPTION                          S5P_PMUREG(0x3C08)
-#define S5P_TV_OPTION                           S5P_PMUREG(0x3C28)
-#define S5P_MFC_OPTION                          S5P_PMUREG(0x3C48)
-#define S5P_G3D_OPTION                          S5P_PMUREG(0x3C68)
-#define S5P_LCD0_OPTION                         S5P_PMUREG(0x3C88)
-#define S5P_LCD1_OPTION                         S5P_PMUREG(0x3CA8)
-#define S5P_MAUDIO_OPTION                       S5P_PMUREG(0x3CC8)
-#define S5P_GPS_OPTION                          S5P_PMUREG(0x3CE8)
-#define S5P_GPS_ALIVE_OPTION                    S5P_PMUREG(0x3D08)
 
 #define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
@@ -145,28 +115,12 @@
 #define S5P_PAD_RET_EBIA_OPTION                 S5P_PMUREG(0x3188)
 #define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
 
-#define S5P_PMU_CAM_CONF                        S5P_PMUREG(0x3C00)
-#define S5P_PMU_TV_CONF                         S5P_PMUREG(0x3C20)
-#define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
-#define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
-#define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
-#define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
-
-#define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 #define S5P_INT_LOCAL_PWR_EN                    0x7
 
 #define S5P_CHECK_SLEEP                         0x00000BAD
 
 /* Only for EXYNOS4210 */
-#define S5P_USBDEVICE_PHY_CONTROL       S5P_PMUREG(0x0704)
-#define S5P_USBDEVICE_PHY_ENABLE        (1 << 0)
-
-#define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE          (1 << 0)
-
-#define S5P_PMU_SATA_PHY_CONTROL        S5P_PMUREG(0x0720)
-
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
 #define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
@@ -174,8 +128,6 @@
 #define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
 #define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
 
-#define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
-
 /* Only for EXYNOS4x12 */
 #define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
@@ -343,13 +295,9 @@
 #define EXYNOS5_TOP_PWR_OPTION                                  S5P_PMUREG(0x2C48)
 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION                           S5P_PMUREG(0x2CC8)
 #define EXYNOS5_JPEG_MEM_OPTION                                 S5P_PMUREG(0x2F48)
-#define EXYNOS5_GSCL_STATUS                                     S5P_PMUREG(0x4004)
-#define EXYNOS5_ISP_STATUS                                      S5P_PMUREG(0x4024)
 #define EXYNOS5_GSCL_OPTION                                     S5P_PMUREG(0x4008)
 #define EXYNOS5_ISP_OPTION                                      S5P_PMUREG(0x4028)
 #define EXYNOS5_MFC_OPTION                                      S5P_PMUREG(0x4048)
-#define EXYNOS5_G3D_CONFIGURATION                               S5P_PMUREG(0x4060)
-#define EXYNOS5_G3D_STATUS                                      S5P_PMUREG(0x4064)
 #define EXYNOS5_G3D_OPTION                                      S5P_PMUREG(0x4068)
 #define EXYNOS5_DISP1_OPTION                                    S5P_PMUREG(0x40A8)
 #define EXYNOS5_MAU_OPTION                                      S5P_PMUREG(0x40C8)
@@ -357,7 +305,6 @@
 #define EXYNOS5_USE_SC_FEEDBACK                                 (1 << 1)
 #define EXYNOS5_USE_SC_COUNTER                                  (1 << 0)
 
-#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL                     (1 << 2)
 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN                  (1 << 7)
 
 #define EXYNOS5_OPTION_USE_STANDBYWFE                           (1 << 24)
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index 0f2111a11315..fba55fb9f47d 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -85,6 +85,7 @@ config FOOTBRIDGE
 # Footbridge in host mode
 config FOOTBRIDGE_HOST
         bool
+        select ARCH_MIGHT_HAVE_PC_SERIO
 
 # Footbridge in addin mode
 config FOOTBRIDGE_ADDIN
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index e0091685fd48..9e8220e38398 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -143,11 +143,6 @@ static struct map_desc fb_common_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(DC21285_ARMCSR_BASE),
                 .length         = ARMCSR_SIZE,
                 .type           = MT_DEVICE,
-        }, {
-                .virtual        = XBUS_BASE,
-                .pfn            = __phys_to_pfn(0x40000000),
-                .length         = XBUS_SIZE,
-                .type           = MT_DEVICE,
         }
 };
 
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index 56607b3a773e..b911e5587ecf 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -10,3 +10,5 @@ extern void footbridge_init_irq(void);
 
 extern void isa_init_irq(unsigned int irq);
 extern void footbridge_restart(enum reboot_mode, const char *);
+
+extern void footbridge_sched_clock(void);
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 782f6c71fa0a..3971104d32d4 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/sched_clock.h>
 
 #include <asm/irq.h>
 
@@ -46,6 +47,16 @@ static struct clocksource cksrc_dc21285 = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static int ckevt_dc21285_set_next_event(unsigned long delta,
+        struct clock_event_device *c)
+{
+        *CSR_TIMER1_CLR = 0;
+        *CSR_TIMER1_LOAD = delta;
+        *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
+
+        return 0;
+}
+
 static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
         struct clock_event_device *c)
 {
@@ -58,7 +69,9 @@ static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
                                    TIMER_CNTL_DIV16;
                 break;
 
-        default:
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
                 *CSR_TIMER1_CNTL = 0;
                 break;
         }
@@ -66,9 +79,11 @@ static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
 
 static struct clock_event_device ckevt_dc21285 = {
         .name           = "dc21285_timer1",
-        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .features       = CLOCK_EVT_FEAT_PERIODIC |
+                          CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
         .irq            = IRQ_TIMER1,
+        .set_next_event = ckevt_dc21285_set_next_event,
         .set_mode       = ckevt_dc21285_set_mode,
 };
 
@@ -78,6 +93,10 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
 
         *CSR_TIMER1_CLR = 0;
 
+        /* Stop the timer if in one-shot mode */
+        if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
+                *CSR_TIMER1_CNTL = 0;
+
         ce->event_handler(ce);
 
         return IRQ_HANDLED;
@@ -105,3 +124,19 @@ void __init footbridge_timer_init(void)
         ce->cpumask = cpumask_of(smp_processor_id());
         clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
 }
+
+static u32 notrace footbridge_read_sched_clock(void)
+{
+        return ~*CSR_TIMER3_VALUE;
+}
+
+void __init footbridge_sched_clock(void)
+{
+        unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
+
+        *CSR_TIMER3_LOAD = 0;
+        *CSR_TIMER3_CLR = 0;
+        *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
+
+        setup_sched_clock(footbridge_read_sched_clock, 24, rate);
+}
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 1a7235fb52ac..aee8300f3490 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -4,6 +4,7 @@
  * EBSA285 machine fixup
  */
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/leds.h>
@@ -17,6 +18,11 @@
 
 /* LEDs */
 #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+#define XBUS_AMBER_L    BIT(0)
+#define XBUS_GREEN_L    BIT(1)
+#define XBUS_RED_L      BIT(2)
+#define XBUS_TOGGLE     BIT(7)
+
 struct ebsa285_led {
         struct led_classdev     cdev;
         u8                      mask;
@@ -36,6 +42,7 @@ static const struct {
 };
 
 static unsigned char hw_led_state;
+static void __iomem *xbus;
 
 static void ebsa285_led_set(struct led_classdev *cdev,
                 enum led_brightness b)
@@ -47,7 +54,7 @@ static void ebsa285_led_set(struct led_classdev *cdev,
                 hw_led_state |= led->mask;
         else
                 hw_led_state &= ~led->mask;
-        *XBUS_LEDS = hw_led_state;
+        writeb(hw_led_state, xbus);
 }
 
 static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
@@ -65,9 +72,13 @@ static int __init ebsa285_leds_init(void)
         if (!machine_is_ebsa285())
                 return -ENODEV;
 
+        xbus = ioremap(XBUS_CS2, SZ_4K);
+        if (!xbus)
+                return -ENOMEM;
+
         /* 3 LEDS all off */
-        hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
-        *XBUS_LEDS = hw_led_state;
+        hw_led_state = XBUS_AMBER_L | XBUS_GREEN_L | XBUS_RED_L;
+        writeb(hw_led_state, xbus);
 
         for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
                 struct ebsa285_led *led;
@@ -104,6 +115,7 @@ MACHINE_START(EBSA285, "EBSA285")
         .video_start    = 0x000a0000,
         .video_end      = 0x000bffff,
         .map_io         = footbridge_map_io,
+        .init_early     = footbridge_sched_clock,
         .init_irq       = footbridge_init_irq,
         .init_time      = footbridge_timer_init,
         .restart        = footbridge_restart,
diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
index e3d6ccac2162..02f6d7a706b1 100644
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -51,11 +51,7 @@
 #define PCIMEM_SIZE             0x01000000
 #define PCIMEM_BASE             MMU_IO(0xf0000000, 0x80000000)
 
-#define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
-#define XBUS_LED_AMBER          (1 << 0)
-#define XBUS_LED_GREEN          (1 << 1)
-#define XBUS_LED_RED            (1 << 2)
-#define XBUS_LED_TOGGLE         (1 << 8)
+#define XBUS_CS2                0x40012000
 
 #define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
 #define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
new file mode 100644
index 000000000000..8f4649b301b2
--- /dev/null
+++ b/arch/arm/mach-hisi/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_HI3xxx
+        bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_TIMER_SP804
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select CACHE_L2X0
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU
+        select HAVE_ARM_TWD
+        select HAVE_SMP
+        select PINCTRL
+        select PINCTRL_SINGLE
+        help
+          Support for Hisilicon Hi36xx/Hi37xx processor family
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
new file mode 100644
index 000000000000..6870058d0a48
--- /dev/null
+++ b/arch/arm/mach-hisi/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for Hisilicon processors family
+#
+
+obj-y   += hisilicon.o
+obj-$(CONFIG_SMP)               += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
new file mode 100644
index 000000000000..af23ec204538
--- /dev/null
+++ b/arch/arm/mach-hisi/core.h
@@ -0,0 +1,15 @@
+#ifndef __HISILICON_CORE_H
+#define __HISILICON_CORE_H
+
+#include <linux/reboot.h>
+
+extern void hi3xxx_set_cpu_jump(int cpu, void *jump_addr);
+extern int hi3xxx_get_cpu_jump(int cpu);
+extern void secondary_startup(void);
+extern struct smp_operations hi3xxx_smp_ops;
+
+extern void hi3xxx_cpu_die(unsigned int cpu);
+extern int hi3xxx_cpu_kill(unsigned int cpu);
+extern void hi3xxx_set_cpu(int cpu, bool enable);
+
+#endif
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
new file mode 100644
index 000000000000..741faf3e7100
--- /dev/null
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -0,0 +1,90 @@
+/*
+ * (Hisilicon's SoC based) flattened device tree enabled machine
+ *
+ * Copyright (c) 2012-2013 Hisilicon Ltd.
+ * Copyright (c) 2012-2013 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#include <asm/proc-fns.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "core.h"
+
+#define HI3620_SYSCTRL_PHYS_BASE                0xfc802000
+#define HI3620_SYSCTRL_VIRT_BASE                0xfe802000
+
+/*
+ * This table is only for optimization. Since ioremap() could always share
+ * the same mapping if it's defined as static IO mapping.
+ *
+ * Without this table, system could also work. The cost is some virtual address
+ * spaces wasted since ioremap() may be called multi times for the same
+ * IO space.
+ */
+static struct map_desc hi3620_io_desc[] __initdata = {
+        {
+                /* sysctrl */
+                .pfn            = __phys_to_pfn(HI3620_SYSCTRL_PHYS_BASE),
+                .virtual        = HI3620_SYSCTRL_VIRT_BASE,
+                .length         = 0x1000,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void __init hi3620_map_io(void)
+{
+        debug_ll_io_init();
+        iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
+}
+
+static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int offset;
+
+        np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+        if (!np) {
+                pr_err("failed to find hisilicon,sysctrl node\n");
+                return;
+        }
+        base = of_iomap(np, 0);
+        if (!base) {
+                pr_err("failed to map address in hisilicon,sysctrl node\n");
+                return;
+        }
+        if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
+                pr_err("failed to find reboot-offset property\n");
+                return;
+        }
+        writel_relaxed(0xdeadbeef, base + offset);
+
+        while (1)
+                cpu_do_idle();
+}
+
+static const char *hi3xxx_compat[] __initconst = {
+        "hisilicon,hi3620-hi4511",
+        NULL,
+};
+
+DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
+        .map_io         = hi3620_map_io,
+        .dt_compat      = hi3xxx_compat,
+        .smp            = smp_ops(hi3xxx_smp_ops),
+        .restart        = hi3xxx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
new file mode 100644
index 000000000000..b909854eee7f
--- /dev/null
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2013 Linaro Ltd.
+ * Copyright (c) 2013 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/cpu.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include "core.h"
+
+/* Sysctrl registers in Hi3620 SoC */
+#define SCISOEN                         0xc0
+#define SCISODIS                        0xc4
+#define SCPERPWREN                      0xd0
+#define SCPERPWRDIS                     0xd4
+#define SCCPUCOREEN                     0xf4
+#define SCCPUCOREDIS                    0xf8
+#define SCPERCTRL0                      0x200
+#define SCCPURSTEN                      0x410
+#define SCCPURSTDIS                     0x414
+
+/*
+ * bit definition in SCISOEN/SCPERPWREN/...
+ *
+ * CPU2_ISO_CTRL        (1 << 5)
+ * CPU3_ISO_CTRL        (1 << 6)
+ * ...
+ */
+#define CPU2_ISO_CTRL                   (1 << 5)
+
+/*
+ * bit definition in SCPERCTRL0
+ *
+ * CPU0_WFI_MASK_CFG    (1 << 28)
+ * CPU1_WFI_MASK_CFG    (1 << 29)
+ * ...
+ */
+#define CPU0_WFI_MASK_CFG               (1 << 28)
+
+/*
+ * bit definition in SCCPURSTEN/...
+ *
+ * CPU0_SRST_REQ_EN     (1 << 0)
+ * CPU1_SRST_REQ_EN     (1 << 1)
+ * ...
+ */
+#define CPU0_HPM_SRST_REQ_EN            (1 << 22)
+#define CPU0_DBG_SRST_REQ_EN            (1 << 12)
+#define CPU0_NEON_SRST_REQ_EN           (1 << 4)
+#define CPU0_SRST_REQ_EN                (1 << 0)
+
+enum {
+        HI3620_CTRL,
+        ERROR_CTRL,
+};
+
+static void __iomem *ctrl_base;
+static int id;
+
+static void set_cpu_hi3620(int cpu, bool enable)
+{
+        u32 val = 0;
+
+        if (enable) {
+                /* MTCMOS set */
+                if ((cpu == 2) || (cpu == 3))
+                        writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
+                                       ctrl_base + SCPERPWREN);
+                udelay(100);
+
+                /* Enable core */
+                writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
+
+                /* unreset */
+                val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+                        | CPU0_SRST_REQ_EN;
+                writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
+                /* reset */
+                val |= CPU0_HPM_SRST_REQ_EN;
+                writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
+
+                /* ISO disable */
+                if ((cpu == 2) || (cpu == 3))
+                        writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
+                                       ctrl_base + SCISODIS);
+                udelay(1);
+
+                /* WFI Mask */
+                val = readl_relaxed(ctrl_base + SCPERCTRL0);
+                val &= ~(CPU0_WFI_MASK_CFG << cpu);
+                writel_relaxed(val, ctrl_base + SCPERCTRL0);
+
+                /* Unreset */
+                val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+                        | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
+                writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
+        } else {
+                /* wfi mask */
+                val = readl_relaxed(ctrl_base + SCPERCTRL0);
+                val |= (CPU0_WFI_MASK_CFG << cpu);
+                writel_relaxed(val, ctrl_base + SCPERCTRL0);
+
+                /* disable core*/
+                writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
+
+                if ((cpu == 2) || (cpu == 3)) {
+                        /* iso enable */
+                        writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
+                                       ctrl_base + SCISOEN);
+                        udelay(1);
+                }
+
+                /* reset */
+                val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
+                        | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
+                writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
+
+                if ((cpu == 2) || (cpu == 3)) {
+                        /* MTCMOS unset */
+                        writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
+                                       ctrl_base + SCPERPWRDIS);
+                        udelay(100);
+                }
+        }
+}
+
+static int hi3xxx_hotplug_init(void)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+        if (node) {
+                ctrl_base = of_iomap(node, 0);
+                id = HI3620_CTRL;
+                return 0;
+        }
+        id = ERROR_CTRL;
+        return -ENOENT;
+}
+
+void hi3xxx_set_cpu(int cpu, bool enable)
+{
+        if (!ctrl_base) {
+                if (hi3xxx_hotplug_init() < 0)
+                        return;
+        }
+
+        if (id == HI3620_CTRL)
+                set_cpu_hi3620(cpu, enable);
+}
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        flush_cache_all();
+
+        /*
+         * Turn off coherency and L1 D-cache
+         */
+        asm volatile(
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, #0x40\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, #0x04\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+          : "=&r" (v)
+          : "r" (0)
+          : "cc");
+}
+
+void hi3xxx_cpu_die(unsigned int cpu)
+{
+        cpu_enter_lowpower();
+        hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
+        cpu_do_idle();
+
+        /* We should have never returned from idle */
+        panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+
+int hi3xxx_cpu_kill(unsigned int cpu)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(50);
+
+        while (hi3xxx_get_cpu_jump(cpu))
+                if (time_after(jiffies, timeout))
+                        return 0;
+        hi3xxx_set_cpu(cpu, false);
+        return 1;
+}
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
new file mode 100644
index 000000000000..471f1ee3be2b
--- /dev/null
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013 Linaro Ltd.
+ * Copyright (c) 2013 Hisilicon Limited.
+ * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#include "core.h"
+
+static void __iomem *ctrl_base;
+
+void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
+{
+        cpu = cpu_logical_map(cpu);
+        if (!cpu || !ctrl_base)
+                return;
+        writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
+}
+
+int hi3xxx_get_cpu_jump(int cpu)
+{
+        cpu = cpu_logical_map(cpu);
+        if (!cpu || !ctrl_base)
+                return 0;
+        return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
+}
+
+static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np = NULL;
+        unsigned long base = 0;
+        u32 offset = 0;
+        void __iomem *scu_base = NULL;
+
+        if (scu_a9_has_base()) {
+                base = scu_a9_get_base();
+                scu_base = ioremap(base, SZ_4K);
+                if (!scu_base) {
+                        pr_err("ioremap(scu_base) failed\n");
+                        return;
+                }
+                scu_enable(scu_base);
+                iounmap(scu_base);
+        }
+        if (!ctrl_base) {
+                np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+                if (!np) {
+                        pr_err("failed to find hisilicon,sysctrl node\n");
+                        return;
+                }
+                ctrl_base = of_iomap(np, 0);
+                if (!ctrl_base) {
+                        pr_err("failed to map address\n");
+                        return;
+                }
+                if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
+                        pr_err("failed to find smp-offset property\n");
+                        return;
+                }
+                ctrl_base += offset;
+        }
+}
+
+static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        hi3xxx_set_cpu(cpu, true);
+        hi3xxx_set_cpu_jump(cpu, secondary_startup);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        return 0;
+}
+
+struct smp_operations hi3xxx_smp_ops __initdata = {
+        .smp_prepare_cpus       = hi3xxx_smp_prepare_cpus,
+        .smp_boot_secondary     = hi3xxx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = hi3xxx_cpu_die,
+        .cpu_kill               = hi3xxx_cpu_kill,
+#endif
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7a6e6f710068..33567aa5880f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -3,7 +3,6 @@ config ARCH_MXC
         select ARCH_REQUIRE_GPIOLIB
         select ARM_CPU_SUSPEND if PM
         select ARM_PATCH_PHYS_VIRT
-        select AUTO_ZRELADDR if !ZBOOT_ROM
         select CLKSRC_MMIO
         select COMMON_CLK
         select GENERIC_ALLOCATOR
@@ -11,6 +10,7 @@ config ARCH_MXC
         select GENERIC_IRQ_CHIP
         select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
         select MULTI_IRQ_HANDLER
+        select PINCTRL
         select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
@@ -20,16 +20,6 @@ config ARCH_MXC
 menu "Freescale i.MX support"
         depends on ARCH_MXC
 
-config MXC_IRQ_PRIOR
-        bool "Use IRQ priority"
-        help
-          Select this if you want to use prioritized IRQ handling.
-          This feature prevents higher priority ISR to be interrupted
-          by lower priority IRQ.
-          This may be useful in embedded applications, where are strong
-          requirements for timing.
-          Say N here, unless you have a specialized requirement.
-
 config MXC_TZIC
         bool
 
@@ -109,6 +99,7 @@ config SOC_IMX25
         select ARCH_MXC_IOMUX_V3
         select CPU_ARM926T
         select MXC_AVIC
+        select PINCTRL_IMX25
 
 config SOC_IMX27
         bool
@@ -118,6 +109,7 @@ config SOC_IMX27
         select IMX_HAVE_IOMUX_V1
         select MACH_MX27
         select MXC_AVIC
+        select PINCTRL_IMX27
 
 config SOC_IMX31
         bool
@@ -133,6 +125,7 @@ config SOC_IMX35
         select HAVE_EPIT
         select MXC_AVIC
         select SMP_ON_UP if SMP
+        select PINCTRL
 
 config SOC_IMX5
         bool
@@ -145,7 +138,6 @@ config SOC_IMX5
 config  SOC_IMX51
         bool
         select HAVE_IMX_SRC
-        select PINCTRL
         select PINCTRL_IMX51
         select SOC_IMX5
 
@@ -619,6 +611,13 @@ config MACH_IMX31_DT
 
 comment "MX35 platforms:"
 
+config MACH_IMX35_DT
+        bool "Support i.MX35 platforms from device tree"
+        select SOC_IMX35
+        help
+          Include support for Freescale i.MX35 based platforms
+          using the device tree for discovery.
+
 config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
         select IMX_HAVE_PLATFORM_FLEXCAN
@@ -766,11 +765,19 @@ endchoice
 
 comment "Device tree only"
 
+config  SOC_IMX50
+        bool "i.MX50 support"
+        select HAVE_IMX_SRC
+        select PINCTRL_IMX50
+        select SOC_IMX5
+
+        help
+          This enables support for Freescale i.MX50 processor.
+
 config  SOC_IMX53
         bool "i.MX53 support"
         select HAVE_IMX_SRC
         select IMX_HAVE_PLATFORM_IMX2_WDT
-        select PINCTRL
         select PINCTRL_IMX53
         select SOC_IMX5
 
@@ -796,7 +803,6 @@ config SOC_IMX6Q
         select MFD_SYSCON
         select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
-        select PINCTRL
         select PINCTRL_IMX6Q
         select PL310_ERRATA_588369 if CACHE_PL310
         select PL310_ERRATA_727915 if CACHE_PL310
@@ -817,7 +823,6 @@ config SOC_IMX6SL
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select MFD_SYSCON
-        select PINCTRL
         select PINCTRL_IMX6SL
         select PL310_ERRATA_588369 if CACHE_PL310
         select PL310_ERRATA_727915 if CACHE_PL310
@@ -831,7 +836,6 @@ config SOC_VF610
         select CPU_V7
         select ARM_GIC
         select CLKSRC_OF
-        select PINCTRL
         select PINCTRL_VF610
         select VF_PIT_TIMER
         select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1789e2b31903..befcaf5d0574 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
 
 obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
@@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index e163ec7a8441..8d1df2e4b7ac 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -54,28 +54,6 @@
 static void __iomem *avic_base;
 static struct irq_domain *domain;
 
-#ifdef CONFIG_MXC_IRQ_PRIOR
-static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
-{
-        struct irq_data *d = irq_get_irq_data(irq);
-        unsigned int temp;
-        unsigned int mask = 0x0F << irq % 8 * 4;
-
-        irq = d->hwirq;
-
-        if (irq >= AVIC_NUM_IRQS)
-                return -EINVAL;
-
-        temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
-        temp &= ~mask;
-        temp |= prio & mask;
-
-        __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
-
-        return 0;
-}
-#endif
-
 #ifdef CONFIG_FIQ
 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 {
@@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 
 
 static struct mxc_extra_irq avic_extra_irq = {
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        .set_priority = avic_irq_set_priority,
-#endif
 #ifdef CONFIG_FIQ
         .set_irq_fiq = avic_set_irq_fiq,
 #endif
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index a63e415609a8..a2ecc006b322 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
 
         reg = readl(gate->reg);
 
-        if (((reg >> gate->bit_idx) & 3) == 3)
+        if (((reg >> gate->bit_idx) & 1) == 1)
                 return 1;
 
         return 0;
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 2193c834f55c..a4d5e425cd82 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = {
 static char hsp_div_532[] = { 4, 8, 3, 0 };
 static char hsp_div_400[] = { 3, 6, 3, 0 };
 
+static struct clk_onecell_data clk_data;
+
 static const char *std_sel[] = {"ppll", "arm"};
 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
 
@@ -286,3 +288,15 @@ int __init mx35_clocks_init(void)
 
         return 0;
 }
+
+static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
+{
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
+
+        mx35_clocks_init();
+
+        return 0;
+}
+CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index ce37af26ff8c..19fca1fdc6fe 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -12,11 +12,11 @@
 #include <linux/io.h>
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/of.h>
 #include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <dt-bindings/clock/imx5-clock.h>
 
 #include "crm-regs-imx5.h"
 #include "clk.h"
@@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_
 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
 
-
-enum imx5_clks {
-        dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
-        uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
-        emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
-        usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
-        tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
-        uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
-        gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
-        gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
-        esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
-        ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
-        ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
-        ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
-        vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
-        uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
-        esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
-        mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
-        ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
-        ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
-        periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
-        tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
-        esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
-        usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
-        pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
-        ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
-        usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
-        ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
-        ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
-        ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
-        ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
-        ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
-        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
-        can_sel, can1_serial_gate, can1_ipg_gate,
-        owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
-        cko1_sel, cko1_podf, cko1,
-        cko2_sel, cko2_podf, cko2,
-        srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
-        spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
-        spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
-        ocram, clk_max
-};
-
-static struct clk *clk[clk_max];
+static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
 
 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
@@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 {
         int i;
 
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
-        clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
-        clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
-        clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
-
-        clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
-                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
-        clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
-                                periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
-        clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
-                                main_bus_sel, ARRAY_SIZE(main_bus_sel));
-        clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
-                                per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
-        clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
-        clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
-        clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
-        clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
-                                per_root_sel, ARRAY_SIZE(per_root_sel));
-        clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
-        clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
-        clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
-        clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
-        clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
-        clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
-        clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
-        clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
-        clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
-        clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
-        clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
-        clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
-        clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
-
-        clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
-        clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
-        clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
-        clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
-        clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
-        clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
-
-        clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
-                                emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
-        clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
-        clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
-        clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
-        clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
-        clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
-                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-        clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
-        clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
-        clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
-        clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
-        clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
-                                usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-        clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
-        clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
-        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
-        clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
-        clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
-        clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
-        clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
-        clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
-        clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
-        clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
-        clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
-        clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
-        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
-        clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
-        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
-        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
-        clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
-        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
-        clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
-        clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
-        clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
-        clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
-        clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
-        clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
-        clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
-        clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
-        clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
-        clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
-        clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
-        clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
-        clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
-        clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
-        clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
-        clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
-        clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
-        clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
-        clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
-        clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
-        clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
-        clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
-        clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
-        clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
-        clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
-        clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
-        clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
-        clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
-        clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
-        clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
-        clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
-        clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
-        clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
-        clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
-        clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
-
-        clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
-        clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
-        clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
-        clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
-        clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
-        clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
-        clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
-        clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
-        clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
-        clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
-        clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
-        clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
-        clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
-        clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
-        clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
-        clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
-        clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
-        clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
-        clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
-        clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
-        clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
-        clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
-        clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
-        clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
-        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
-        clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
-        clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
-        clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
-        clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
-                                spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
-        clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
-        clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
+        clk[IMX5_CLK_DUMMY]             = imx_clk_fixed("dummy", 0);
+        clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", rate_ckil);
+        clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", rate_osc);
+        clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", rate_ckih1);
+        clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", rate_ckih2);
+
+        clk[IMX5_CLK_PERIPH_APM]        = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
+                                                periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
+        clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
+                                                main_bus_sel, ARRAY_SIZE(main_bus_sel));
+        clk[IMX5_CLK_PER_LP_APM]        = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
+                                                per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
+        clk[IMX5_CLK_PER_PRED1]         = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
+        clk[IMX5_CLK_PER_PRED2]         = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
+        clk[IMX5_CLK_PER_PODF]          = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
+        clk[IMX5_CLK_PER_ROOT]          = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
+                                                per_root_sel, ARRAY_SIZE(per_root_sel));
+        clk[IMX5_CLK_AHB]               = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
+        clk[IMX5_CLK_AHB_MAX]           = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
+        clk[IMX5_CLK_AIPS_TZ1]          = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
+        clk[IMX5_CLK_AIPS_TZ2]          = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
+        clk[IMX5_CLK_TMAX1]             = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
+        clk[IMX5_CLK_TMAX2]             = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
+        clk[IMX5_CLK_TMAX3]             = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
+        clk[IMX5_CLK_SPBA]              = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
+        clk[IMX5_CLK_IPG]               = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
+        clk[IMX5_CLK_AXI_A]             = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
+        clk[IMX5_CLK_AXI_B]             = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
+        clk[IMX5_CLK_UART_SEL]          = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
+                                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[IMX5_CLK_UART_PRED]         = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
+        clk[IMX5_CLK_UART_ROOT]         = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
+
+        clk[IMX5_CLK_ESDHC_A_SEL]       = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
+                                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[IMX5_CLK_ESDHC_B_SEL]       = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
+                                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[IMX5_CLK_ESDHC_A_PRED]      = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
+        clk[IMX5_CLK_ESDHC_A_PODF]      = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
+        clk[IMX5_CLK_ESDHC_B_PRED]      = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
+        clk[IMX5_CLK_ESDHC_B_PODF]      = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
+        clk[IMX5_CLK_ESDHC_C_SEL]       = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+        clk[IMX5_CLK_ESDHC_D_SEL]       = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
+
+        clk[IMX5_CLK_EMI_SEL]           = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
+                                                emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
+        clk[IMX5_CLK_EMI_SLOW_PODF]     = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
+        clk[IMX5_CLK_NFC_PODF]          = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
+        clk[IMX5_CLK_ECSPI_SEL]         = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
+                                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[IMX5_CLK_ECSPI_PRED]        = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
+        clk[IMX5_CLK_ECSPI_PODF]        = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
+        clk[IMX5_CLK_USBOH3_SEL]        = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
+                                                standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+        clk[IMX5_CLK_USBOH3_PRED]       = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
+        clk[IMX5_CLK_USBOH3_PODF]       = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
+        clk[IMX5_CLK_USB_PHY_PRED]      = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
+        clk[IMX5_CLK_USB_PHY_PODF]      = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
+        clk[IMX5_CLK_USB_PHY_SEL]       = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
+                                                usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
+        clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+        clk[IMX5_CLK_DI_PRED]           = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
+        clk[IMX5_CLK_IIM_GATE]          = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
+        clk[IMX5_CLK_UART1_IPG_GATE]    = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
+        clk[IMX5_CLK_UART1_PER_GATE]    = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
+        clk[IMX5_CLK_UART2_IPG_GATE]    = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
+        clk[IMX5_CLK_UART2_PER_GATE]    = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
+        clk[IMX5_CLK_UART3_IPG_GATE]    = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
+        clk[IMX5_CLK_UART3_PER_GATE]    = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
+        clk[IMX5_CLK_I2C1_GATE]         = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
+        clk[IMX5_CLK_I2C2_GATE]         = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
+        clk[IMX5_CLK_PWM1_IPG_GATE]     = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
+        clk[IMX5_CLK_PWM1_HF_GATE]      = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
+        clk[IMX5_CLK_PWM2_IPG_GATE]     = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
+        clk[IMX5_CLK_PWM2_HF_GATE]      = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
+        clk[IMX5_CLK_GPT_IPG_GATE]      = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
+        clk[IMX5_CLK_GPT_HF_GATE]       = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
+        clk[IMX5_CLK_FEC_GATE]          = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
+        clk[IMX5_CLK_USBOH3_GATE]       = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
+        clk[IMX5_CLK_USBOH3_PER_GATE]   = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
+        clk[IMX5_CLK_ESDHC1_IPG_GATE]   = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
+        clk[IMX5_CLK_ESDHC2_IPG_GATE]   = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
+        clk[IMX5_CLK_ESDHC3_IPG_GATE]   = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
+        clk[IMX5_CLK_ESDHC4_IPG_GATE]   = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
+        clk[IMX5_CLK_SSI1_IPG_GATE]     = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
+        clk[IMX5_CLK_SSI2_IPG_GATE]     = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
+        clk[IMX5_CLK_SSI3_IPG_GATE]     = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
+        clk[IMX5_CLK_ECSPI1_IPG_GATE]   = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
+        clk[IMX5_CLK_ECSPI1_PER_GATE]   = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
+        clk[IMX5_CLK_ECSPI2_IPG_GATE]   = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
+        clk[IMX5_CLK_ECSPI2_PER_GATE]   = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
+        clk[IMX5_CLK_CSPI_IPG_GATE]     = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
+        clk[IMX5_CLK_SDMA_GATE]         = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
+        clk[IMX5_CLK_EMI_FAST_GATE]     = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
+        clk[IMX5_CLK_EMI_SLOW_GATE]     = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
+        clk[IMX5_CLK_IPU_SEL]           = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
+        clk[IMX5_CLK_IPU_GATE]          = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
+        clk[IMX5_CLK_NFC_GATE]          = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
+        clk[IMX5_CLK_IPU_DI0_GATE]      = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
+        clk[IMX5_CLK_IPU_DI1_GATE]      = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
+        clk[IMX5_CLK_GPU3D_SEL]         = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
+        clk[IMX5_CLK_GPU2D_SEL]         = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
+        clk[IMX5_CLK_GPU3D_GATE]        = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
+        clk[IMX5_CLK_GARB_GATE]         = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
+        clk[IMX5_CLK_GPU2D_GATE]        = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
+        clk[IMX5_CLK_VPU_SEL]           = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
+        clk[IMX5_CLK_VPU_GATE]          = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
+        clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
+        clk[IMX5_CLK_UART4_IPG_GATE]    = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+        clk[IMX5_CLK_UART4_PER_GATE]    = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+        clk[IMX5_CLK_UART5_IPG_GATE]    = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+        clk[IMX5_CLK_UART5_PER_GATE]    = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
+        clk[IMX5_CLK_GPC_DVFS]          = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
+
+        clk[IMX5_CLK_SSI_APM]           = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
+        clk[IMX5_CLK_SSI1_ROOT_SEL]     = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[IMX5_CLK_SSI2_ROOT_SEL]     = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[IMX5_CLK_SSI3_ROOT_SEL]     = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
+        clk[IMX5_CLK_SSI_EXT1_SEL]      = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[IMX5_CLK_SSI_EXT2_SEL]      = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[IMX5_CLK_SSI_EXT1_COM_SEL]  = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
+        clk[IMX5_CLK_SSI_EXT2_COM_SEL]  = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
+        clk[IMX5_CLK_SSI1_ROOT_PRED]    = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
+        clk[IMX5_CLK_SSI1_ROOT_PODF]    = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
+        clk[IMX5_CLK_SSI2_ROOT_PRED]    = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
+        clk[IMX5_CLK_SSI2_ROOT_PODF]    = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
+        clk[IMX5_CLK_SSI_EXT1_PRED]     = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
+        clk[IMX5_CLK_SSI_EXT1_PODF]     = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
+        clk[IMX5_CLK_SSI_EXT2_PRED]     = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
+        clk[IMX5_CLK_SSI_EXT2_PODF]     = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
+        clk[IMX5_CLK_SSI1_ROOT_GATE]    = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
+        clk[IMX5_CLK_SSI2_ROOT_GATE]    = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
+        clk[IMX5_CLK_SSI3_ROOT_GATE]    = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
+        clk[IMX5_CLK_SSI_EXT1_GATE]     = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
+        clk[IMX5_CLK_SSI_EXT2_GATE]     = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
+        clk[IMX5_CLK_EPIT1_IPG_GATE]    = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
+        clk[IMX5_CLK_EPIT1_HF_GATE]     = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
+        clk[IMX5_CLK_EPIT2_IPG_GATE]    = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
+        clk[IMX5_CLK_EPIT2_HF_GATE]     = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
+        clk[IMX5_CLK_OWIRE_GATE]        = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
+        clk[IMX5_CLK_SRTC_GATE]         = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
+        clk[IMX5_CLK_PATA_GATE]         = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
+        clk[IMX5_CLK_SPDIF0_SEL]        = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[IMX5_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
+        clk[IMX5_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
+        clk[IMX5_CLK_SPDIF0_COM_SEL]    = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
+                                                spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_SPDIF0_GATE]       = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
+        clk[IMX5_CLK_SPDIF_IPG_GATE]    = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
+        clk[IMX5_CLK_SAHARA_IPG_GATE]   = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
+        clk[IMX5_CLK_SATA_REF]          = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
                         pr_err("i.MX5 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
-        clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
-        clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
-        clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
-        clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
-        clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
-        clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
-        clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
-        clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
-        clk_register_clkdev(clk[iim_gate], "iim", NULL);
-        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
-        clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
-        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
-        clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
-        clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
-        clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
-        clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
+        clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
+        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
+        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
+        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
+        clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
+        clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
+        clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
+        clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
+        clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
+        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
+        clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
+        clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
+        clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
+        clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
+        clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
+        clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
+        clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
+        clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
+        clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
+        clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
+        clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
 
         /* Set SDHC parents to be PLL2 */
-        clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
-        clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
+        clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
+        clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
 
         /* move usb phy clk to 24MHz */
-        clk_set_parent(clk[usb_phy_sel], clk[osc]);
-
-        clk_prepare_enable(clk[gpc_dvfs]);
-        clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
-        clk_prepare_enable(clk[aips_tz1]);
-        clk_prepare_enable(clk[aips_tz2]); /* fec */
-        clk_prepare_enable(clk[spba]);
-        clk_prepare_enable(clk[emi_fast_gate]); /* fec */
-        clk_prepare_enable(clk[emi_slow_gate]); /* eim */
-        clk_prepare_enable(clk[mipi_hsc1_gate]);
-        clk_prepare_enable(clk[mipi_hsc2_gate]);
-        clk_prepare_enable(clk[mipi_esc_gate]);
-        clk_prepare_enable(clk[mipi_hsp_gate]);
-        clk_prepare_enable(clk[tmax1]);
-        clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
-        clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
+        clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
+
+        clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
+        clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
+        clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
+        clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
+        clk_prepare_enable(clk[IMX5_CLK_SPBA]);
+        clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
+        clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
+        clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
+        clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
+        clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
+        clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
+        clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
+        clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
+        clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
 }
 
+static void __init mx50_clocks_init(struct device_node *np)
+{
+        void __iomem *base;
+        unsigned long r;
+        int i, irq;
+
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+
+        clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
+                                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+        clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+        clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
+        clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
+        clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+        clk[IMX5_CLK_USB_PHY1_GATE]     = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
+        clk[IMX5_CLK_USB_PHY2_GATE]     = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
+        clk[IMX5_CLK_I2C3_GATE]         = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+
+        clk[IMX5_CLK_CKO1_SEL]          = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
+                                                mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
+        clk[IMX5_CLK_CKO1_PODF]         = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
+        clk[IMX5_CLK_CKO1]              = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
+
+        clk[IMX5_CLK_CKO2_SEL]          = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
+                                                mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
+        clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
+        clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+
+        for (i = 0; i < ARRAY_SIZE(clk); i++)
+                if (IS_ERR(clk[i]))
+                        pr_err("i.MX50 clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clk[i]));
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        mx5_clocks_common_init(0, 0, 0, 0);
+
+        /* set SDHC root clock to 200MHZ*/
+        clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
+        clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
+
+        clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
+        imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
+        clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
+
+        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
+        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
+}
+CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
+
 int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
@@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         u32 val;
         struct device_node *np;
 
-        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
-        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
-        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
-        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
-                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
-        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
-                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
-        clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
-                                mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
-        clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
-                                mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
-        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
-        clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
-        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
-        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
-        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
-        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
-        clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
-        clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
-        clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
-        clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
-        clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
-        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
-                                mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
-        clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
-                                spdif_sel, ARRAY_SIZE(spdif_sel));
-        clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
-        clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
-        clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
-                                mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
-        clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
+        clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
+                                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+        clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                                                mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
+        clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                                                mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
+        clk[IMX5_CLK_TVE_EXT_SEL]       = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                                                mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_TVE_SEL]           = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
+                                                mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
+        clk[IMX5_CLK_TVE_GATE]          = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
+        clk[IMX5_CLK_TVE_PRED]          = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
+        clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+        clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
+        clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
+        clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+        clk[IMX5_CLK_USB_PHY_GATE]      = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
+        clk[IMX5_CLK_HSI2C_GATE]        = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
+        clk[IMX5_CLK_MIPI_HSC1_GATE]    = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
+        clk[IMX5_CLK_MIPI_HSC2_GATE]    = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
+        clk[IMX5_CLK_MIPI_ESC_GATE]     = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
+        clk[IMX5_CLK_MIPI_HSP_GATE]     = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+        clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                                mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
+        clk[IMX5_CLK_SPDIF1_SEL]        = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
+                                                spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[IMX5_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+        clk[IMX5_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
+        clk[IMX5_CLK_SPDIF1_COM_SEL]    = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
+                                                mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+        clk[IMX5_CLK_SPDIF1_GATE]       = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 
         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 
-        clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
-        clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
-        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
-        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
+        clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
+        clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
+        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
+        clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
 
         /* set the usboh3 parent to pll2_sw */
-        clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
+        clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
 
         /* set SDHC root clock to 166.25MHZ*/
-        clk_set_rate(clk[esdhc_a_podf], 166250000);
-        clk_set_rate(clk[esdhc_b_podf], 166250000);
+        clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
+        clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
 
         /* System timer */
         mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
 
-        clk_prepare_enable(clk[iim_gate]);
+        clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
         imx_print_silicon_rev("i.MX51", mx51_revision());
-        clk_disable_unprepare(clk[iim_gate]);
+        clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
 
         /*
          * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
@@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np)
         unsigned long r;
         void __iomem *base;
 
-        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
-        clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
-
-        clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
-        clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
-        clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
-                                mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
-        clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
-        clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
-        clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
-        clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
-                                mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
-        clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
-        clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
-        clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
-                                mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
-        clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
-                                mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
-        clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
-                                mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
-        clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
-        clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
-        clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
-        clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
-        clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
-        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
-        clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
-        clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
-        clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
-                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
-        clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
-        clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
-        clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
-        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
-        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
-        clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
-
-        clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
-                                mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
-        clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
-        clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
-
-        clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
-                                mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
-        clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
-        clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
-        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
-                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+        clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
+
+        clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
+                                                lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+        clk[IMX5_CLK_LDB_DI1_DIV_3_5]   = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clk[IMX5_CLK_LDB_DI1_DIV]       = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
+        clk[IMX5_CLK_LDB_DI1_SEL]       = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
+                                                mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_DI_PLL4_PODF]      = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
+        clk[IMX5_CLK_LDB_DI0_DIV_3_5]   = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clk[IMX5_CLK_LDB_DI0_DIV]       = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
+        clk[IMX5_CLK_LDB_DI0_SEL]       = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
+                                                mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_LDB_DI0_GATE]      = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
+        clk[IMX5_CLK_LDB_DI1_GATE]      = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
+        clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                                                mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
+        clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                                                mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
+        clk[IMX5_CLK_TVE_EXT_SEL]       = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                                                mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
+        clk[IMX5_CLK_TVE_GATE]          = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
+        clk[IMX5_CLK_TVE_PRED]          = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
+        clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+        clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
+        clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
+        clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+        clk[IMX5_CLK_USB_PHY1_GATE]     = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
+        clk[IMX5_CLK_USB_PHY2_GATE]     = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
+        clk[IMX5_CLK_CAN_SEL]           = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
+                                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
+        clk[IMX5_CLK_CAN1_SERIAL_GATE]  = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
+        clk[IMX5_CLK_CAN1_IPG_GATE]     = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+        clk[IMX5_CLK_OCRAM]             = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
+        clk[IMX5_CLK_CAN2_SERIAL_GATE]  = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
+        clk[IMX5_CLK_CAN2_IPG_GATE]     = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
+        clk[IMX5_CLK_I2C3_GATE]         = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+        clk[IMX5_CLK_SATA_GATE]         = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
+
+        clk[IMX5_CLK_CKO1_SEL]          = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
+                                                mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
+        clk[IMX5_CLK_CKO1_PODF]         = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
+        clk[IMX5_CLK_CKO1]              = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
+
+        clk[IMX5_CLK_CKO2_SEL]          = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
+                                                mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
+        clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
+        clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+        clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np)
 
         mx5_clocks_common_init(0, 0, 0, 0);
 
-        clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
-        clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
-        clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
+        clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
+        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
+        clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
 
         /* set SDHC root clock to 200MHZ*/
-        clk_set_rate(clk[esdhc_a_podf], 200000000);
-        clk_set_rate(clk[esdhc_b_podf], 200000000);
+        clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
+        clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
+
+        /* move can bus clk to 24MHz */
+        clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
 
-        clk_prepare_enable(clk[iim_gate]);
+        clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
         imx_print_silicon_rev("i.MX53", mx53_revision());
-        clk_disable_unprepare(clk[iim_gate]);
+        clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
 
-        r = clk_round_rate(clk[usboh3_per_gate], 54000000);
-        clk_set_rate(clk[usboh3_per_gate], r);
+        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
+        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
         base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 04cfd0fcb0e5..af2e582d2b74 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -114,7 +114,7 @@ static struct clk *clk[clk_max];
 static struct clk_onecell_data clk_data;
 
 static enum mx6q_clks const clks_init_on[] __initconst = {
-        mmdc_ch0_axi, rom, pll1_sys,
+        mmdc_ch0_axi, rom, arm,
 };
 
 static struct clk_div_table clk_enet_ref_table[] = {
@@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         if (ret)
                 pr_warn("failed to set up CLKO: %d\n", ret);
 
+        /* Audio-related clocks configuration */
+        clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+
         /* All existing boards with PCIe use LVDS1 */
         if (IS_ENABLED(CONFIG_PCI_IMX6))
                 clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index c0c4ef55e35b..3781a1853998 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -29,14 +29,14 @@ static const char const *periph_sels[]		= { "pre_periph_sel", "periph_clk2_podf"
 static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
 static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
 static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
-static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
+static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
 static const char const *perclk_sels[]          = { "ipg", "osc", };
 static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
 static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
 static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
 static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
 static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
-static const char const *audio_sels[]           = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char const *audio_sels[]           = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
 static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
 static const char const *uart_sels[]            = { "pll3_80m", "osc", };
 
@@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = {
         { }
 };
 
-static struct clk *clks[IMX6SL_CLK_CLK_END];
+static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
 
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
@@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
         /*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
         clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL4_AUDIO_DIV] =       clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1,   0, &imx_ccm_lock);
         clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
         clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
         clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
@@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_PWM3]         = imx_clk_gate2("pwm3",         "perclk",            base + 0x78, 20);
         clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
         clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
+        clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
         clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
         clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
         clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
@@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
                 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
         }
 
+        /* Audio-related clocks configuration */
+        clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
index e2ed4160f329..0b0f6f66ec56 100644
--- a/arch/arm/mach-imx/clk-pfd.c
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
+static int clk_pfd_is_enabled(struct clk_hw *hw)
+{
+        struct clk_pfd *pfd = to_clk_pfd(hw);
+
+        if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
+                return 0;
+
+        return 1;
+}
+
 static const struct clk_ops clk_pfd_ops = {
         .enable         = clk_pfd_enable,
         .disable        = clk_pfd_disable,
         .recalc_rate    = clk_pfd_recalc_rate,
         .round_rate     = clk_pfd_round_rate,
         .set_rate       = clk_pfd_set_rate,
+        .is_enabled     = clk_pfd_is_enabled,
 };
 
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index c1eaee346954..d21d14ca46c1 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -18,6 +18,11 @@
  *
  * PLL clock version 1, found on i.MX1/21/25/27/31/35
  */
+
+#define MFN_BITS        (10)
+#define MFN_SIGN        (BIT(MFN_BITS - 1))
+#define MFN_MASK        (MFN_SIGN - 1)
+
 struct clk_pllv1 {
         struct clk_hw   hw;
         void __iomem    *base;
@@ -25,6 +30,11 @@ struct clk_pllv1 {
 
 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
 
+static inline bool mfn_is_negative(unsigned int mfn)
+{
+        return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
+}
+
 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
                 unsigned long parent_rate)
 {
@@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
 
         /*
          * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-         * 2's complements number
+         * 2's complements number.
+         * On i.MX27 the bit 9 is the sign bit.
          */
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                mfn_abs = 0x400 - mfn;
+        if (mfn_is_negative(mfn)) {
+                if (cpu_is_mx27())
+                        mfn_abs = mfn & MFN_MASK;
+                else
+                        mfn_abs = BIT(MFN_BITS) - mfn;
+        }
 
         rate = parent_rate * 2;
         rate /= pd + 1;
@@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
 
         do_div(ll, mfd + 1);
 
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+        if (mfn_is_negative(mfn))
                 ll = -ll;
 
         ll = (rate * mfi) + ll;
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index b169a396d93b..ecd66d8e20b6 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
         clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
 
+        clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
+        clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
+        clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
+
         clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
         clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
         clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 24a7899e36a8..59c3b9b26bb4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx27_handle_irq avic_handle_irq
 #define imx31_handle_irq avic_handle_irq
 #define imx35_handle_irq avic_handle_irq
+#define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
 
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 818a1cc2fe45..e1e70ef7bc2d 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx31_dt_board_compat[] __initdata = {
+static const char *imx31_dt_board_compat[] __initconst = {
         "fsl,imx31",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
new file mode 100644
index 000000000000..9d48e0065a63
--- /dev/null
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27-dt.c
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "common.h"
+#include "mx35.h"
+
+static void __init imx35_dt_init(void)
+{
+        mxc_arch_reset_init_dt();
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             NULL, NULL);
+}
+
+static void __init imx35_irq_init(void)
+{
+        imx_init_l2cache();
+        mx35_init_irq();
+}
+
+static const char *imx35_dt_board_compat[] __initconst = {
+        "fsl,imx35",
+        NULL
+};
+
+DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
+        .map_io         = mx35_map_io,
+        .init_early     = imx35_init_early,
+        .init_irq       = imx35_irq_init,
+        .handle_irq     = imx35_handle_irq,
+        .init_machine   = imx35_dt_init,
+        .dt_compat      = imx35_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index bece8a65e6f0..0230d78d1413 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -29,7 +29,7 @@ static void __init imx51_dt_init(void)
         platform_device_register_full(&devinfo);
 }
 
-static const char *imx51_dt_board_compat[] __initdata = {
+static const char *imx51_dt_board_compat[] __initconst = {
         "fsl,imx51",
         NULL
 };
diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h
index 5b2dabba330f..6e3175dc0c0a 100644
--- a/arch/arm/mach-imx/irq-common.h
+++ b/arch/arm/mach-imx/irq-common.h
@@ -24,7 +24,6 @@
 
 struct mxc_extra_irq
 {
-        int (*set_priority)(unsigned char irq, unsigned char prio);
         int (*set_irq_fiq)(unsigned int irq, unsigned int type);
 };
 
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 771362d1fbee..65e4c53e1554 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -53,7 +53,7 @@ static const struct imxi2c_platform_data
 };
 
 #define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 2)
-static int tsc2007_get_pendown_state(void)
+static int tsc2007_get_pendown_state(struct device *dev)
 {
         return !gpio_get_value(TSC2007_IRQGPIO);
 }
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9b5ddf5bbd33..1fba2b8e983f 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -121,7 +121,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static int tsc2007_get_pendown_state(void)
+static int tsc2007_get_pendown_state(struct device *dev)
 {
         if (mx51_revision() < IMX_CHIP_REVISION_3_0)
                 return !gpio_get_value(TSC2007_IRQGPIO_REV2);
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
new file mode 100644
index 000000000000..77b77a92bb5d
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static void __init imx50_dt_init(void)
+{
+        mxc_arch_reset_init_dt();
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *imx50_dt_board_compat[] __initconst = {
+        "fsl,imx50",
+        NULL
+};
+
+DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
+        .map_io         = mx53_map_io,
+        .init_irq       = mx53_init_irq,
+        .handle_irq     = imx50_handle_irq,
+        .init_machine   = imx50_dt_init,
+        .dt_compat      = imx50_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index c9c4d8d96931..65850908a4b4 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -31,7 +31,7 @@ static void __init imx53_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx53_dt_board_compat[] __initdata = {
+static const char *imx53_dt_board_compat[] __initconst = {
         "fsl,imx53",
         NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d0cfb225ec9a..76e5db4fce35 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -13,6 +13,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/cpu.h>
+#include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -23,6 +24,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pm_opp.h>
+#include <linux/pci.h>
 #include <linux/phy.h>
 #include <linux/reboot.h>
 #include <linux/regmap.h>
@@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
         return 0;
 }
 
+/*
+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
+ * as they are used for slots1-7 PERST#
+ */
+static void ventana_pciesw_early_fixup(struct pci_dev *dev)
+{
+        u32 dw;
+
+        if (!of_machine_is_compatible("gw,ventana"))
+                return;
+
+        if (dev->devfn != 0)
+                return;
+
+        pci_read_config_dword(dev, 0x62c, &dw);
+        dw |= 0xaaa8; // GPIO1-7 outputs
+        pci_write_config_dword(dev, 0x62c, dw);
+
+        pci_read_config_dword(dev, 0x644, &dw);
+        dw |= 0xfe;   // GPIO1-7 output high
+        pci_write_config_dword(dev, 0x644, dw);
+
+        msleep(100);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
+
 static int ar8031_phy_fixup(struct phy_device *dev)
 {
         u16 val;
@@ -103,6 +133,39 @@ static int ar8031_phy_fixup(struct phy_device *dev)
 
 #define PHY_ID_AR8031   0x004dd074
 
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+        u16 val;
+
+        /* Ar803x phy SmartEEE feature cause link status generates glitch,
+         * which cause ethernet link down/up issue, so disable SmartEEE
+         */
+        phy_write(dev, 0xd, 0x3);
+        phy_write(dev, 0xe, 0x805d);
+        phy_write(dev, 0xd, 0x4003);
+
+        val = phy_read(dev, 0xe);
+        phy_write(dev, 0xe, val & ~(1 << 8));
+
+        /*
+         * Enable 125MHz clock from CLK_25M on the AR8031.  This
+         * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
+         * Also, introduce a tx clock delay.
+         *
+         * This is the same as is the AR8031 fixup.
+         */
+        ar8031_phy_fixup(dev);
+
+        /*check phy power*/
+        val = phy_read(dev, 0x0);
+        if (val & BMCR_PDOWN)
+                phy_write(dev, 0x0, val & ~BMCR_PDOWN);
+
+        return 0;
+}
+
+#define PHY_ID_AR8035 0x004dd072
+
 static void __init imx6q_enet_phy_init(void)
 {
         if (IS_BUILTIN(CONFIG_PHYLIB)) {
@@ -112,6 +175,8 @@ static void __init imx6q_enet_phy_init(void)
                                 ksz9031rn_phy_fixup);
                 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
                                 ar8031_phy_fixup);
+                phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
+                                ar8035_phy_fixup);
         }
 }
 
@@ -243,7 +308,7 @@ static void __init imx6q_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6q_dt_compat[] __initdata = {
+static const char *imx6q_dt_compat[] __initconst = {
         "fsl,imx6dl",
         "fsl,imx6q",
         NULL,
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 2f952e3fcf89..0f4fd4c0ab8e 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void)
         }
 }
 
+static void __init imx6sl_init_late(void)
+{
+        /* imx6sl reuses imx6q cpufreq driver */
+        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
+                platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
+}
+
 static void __init imx6sl_init_machine(void)
 {
         struct device *parent;
@@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6sl_dt_compat[] __initdata = {
+static const char *imx6sl_dt_compat[] __initconst = {
         "fsl,imx6sl",
         NULL,
 };
@@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
         .map_io         = debug_ll_io_init,
         .init_irq       = imx6sl_init_irq,
         .init_machine   = imx6sl_init_machine,
+        .init_late      = imx6sl_init_late,
         .dt_compat      = imx6sl_dt_compat,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 6f424eced181..b3738e616f19 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -236,32 +236,26 @@ static struct mc13xxx_led_platform_data moboard_led[] = {
         {
                 .id = MC13783_LED_R1,
                 .name = "coreboard-led-4:red",
-                .max_current = 2,
         },
         {
                 .id = MC13783_LED_G1,
                 .name = "coreboard-led-4:green",
-                .max_current = 2,
         },
         {
                 .id = MC13783_LED_B1,
                 .name = "coreboard-led-4:blue",
-                .max_current = 2,
         },
         {
                 .id = MC13783_LED_R2,
                 .name = "coreboard-led-5:red",
-                .max_current = 3,
         },
         {
                 .id = MC13783_LED_G2,
                 .name = "coreboard-led-5:green",
-                .max_current = 3,
         },
         {
                 .id = MC13783_LED_B2,
                 .name = "coreboard-led-5:blue",
-                .max_current = 3,
         },
 };
 
@@ -271,8 +265,14 @@ static struct mc13xxx_leds_platform_data moboard_leds = {
         .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0),
         .led_control[1] = MC13783_LED_C1_SLEWLIM,
         .led_control[2] = MC13783_LED_C2_SLEWLIM,
-        .led_control[3] = MC13783_LED_C3_PERIOD(0),
-        .led_control[4] = MC13783_LED_C3_PERIOD(0),
+        .led_control[3] = MC13783_LED_C3_PERIOD(0) |
+                          MC13783_LED_C3_CURRENT_R1(2) |
+                          MC13783_LED_C3_CURRENT_G1(2) |
+                          MC13783_LED_C3_CURRENT_B1(2),
+        .led_control[4] = MC13783_LED_C4_PERIOD(0) |
+                          MC13783_LED_C4_CURRENT_R2(3) |
+                          MC13783_LED_C4_CURRENT_G2(3) |
+                          MC13783_LED_C4_CURRENT_B2(3),
 };
 
 static struct mc13xxx_buttons_platform_data moboard_buttons = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index c5f95674e9b7..bf3ac51d5aca 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -249,7 +249,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
                           "imx-mmc-detect", data);
         if (ret)
                 printk(KERN_ERR
-                        "pca100: Failed to reuest irq for sd/mmc detection\n");
+                        "pca100: Failed to request irq for sd/mmc detection\n");
 
         return ret;
 }
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index af0cb8a9dc48..2d8aef5a6efa 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -26,7 +26,7 @@ static void __init vf610_init_irq(void)
         irqchip_init();
 }
 
-static const char *vf610_dt_compat[] __initdata = {
+static const char *vf610_dt_compat[] __initconst = {
         "fsl,vf610",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index d1d52600f458..4c112021aa4e 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -89,15 +89,7 @@ void __init imx51_init_early(void)
 
 void __init imx53_init_early(void)
 {
-        struct device_node *np;
-        void __iomem *base;
-
         mxc_set_cpu_type(MXC_CPU_MX53);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        mxc_iomux_v3_init(base);
         imx_src_init();
 }
 
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 1f24c1fdfea4..5b57c17c06bd 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -92,8 +92,7 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
          * secondary cores when booting them.
          */
         asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
-        __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
-        outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
+        sync_cache_w(&g_diag_reg);
 }
 
 struct smp_operations  imx_smp_ops __initdata = {
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index aecd9f8037e0..9d47adc078aa 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
         }
 
         /*
-         * Unmask the always pending IOMUXC interrupt #32 as wakeup source to
-         * deassert dsm_request signal, so that we can ensure dsm_request
-         * is not asserted when we're going to write CLPCR register to set LPM.
-         * After setting up LPM bits, we need to mask this wakeup source.
+         * ERR007265: CCM: When improper low-power sequence is used,
+         * the SoC enters low power mode before the ARM core executes WFI.
+         *
+         * Software workaround:
+         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+         *    by setting IOMUX_GPR1_GINT.
+         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+         *    Low-Power mode.
+         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+         *    is set (set bits 0-1 of CCM_CLPCR).
          */
         iomuxc_irq_desc = irq_to_desc(32);
         imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
@@ -219,6 +225,8 @@ void __init imx6q_pm_init(void)
         WARN_ON(!ccm_base);
 
         /*
+         * This is for SW workaround step #1 of ERR007265, see comments
+         * in imx6q_set_lpm for details of this errata.
          * Force IOMUXC irq pending, so that the interrupt to GPC can be
          * used to deassert dsm_request signal when the signal gets
          * asserted unexpectedly.
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 9b6638aadeaa..1a3a5f615770 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -111,7 +111,7 @@ static void gpt_irq_acknowledge(void)
 
 static void __iomem *sched_clock_reg;
 
-static u32 notrace mxc_read_sched_clock(void)
+static u64 notrace mxc_read_sched_clock(void)
 {
         return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 }
@@ -123,7 +123,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 
         sched_clock_reg = reg;
 
-        setup_sched_clock(mxc_read_sched_clock, 32, c);
+        sched_clock_register(mxc_read_sched_clock, 32, c);
         return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
                         clocksource_mmio_readl_up);
 }
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d50dc2dbfd89..17c0fe627435 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -63,6 +63,9 @@
 
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
+/* Base address to the external bus interface */
+static void __iomem *ebi_base;
+
 
 /*
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@@ -72,15 +75,11 @@ void __iomem *ap_syscon_base;
  * just for now).
  */
 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
-#define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
-#define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
 
 /*
  * Logical      Physical
  * ef000000                     Cache flush
- * f1000000     10000000        Core module registers
  * f1100000     11000000        System controller registers
- * f1200000     12000000        EBI registers
  * f1300000     13000000        Counter/Timer
  * f1400000     14000000        Interrupt controller
  * f1600000     16000000        UART 0
@@ -91,16 +90,6 @@ void __iomem *ap_syscon_base;
 
 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
         {
-                .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
                 .length         = SZ_4K,
@@ -174,9 +163,6 @@ device_initcall(irq_syscore_init);
 /*
  * Flash handling.
  */
-#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
-#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
-
 static int ap_flash_init(struct platform_device *dev)
 {
         u32 tmp;
@@ -184,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev)
         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 
-        tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
-        writel(tmp, EBI_CSR1);
+        tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
+                INTEGRATOR_EBI_WRITE_ENABLE;
+        writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 
-        if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
-                writel(0xa05f, EBI_LOCK);
-                writel(tmp, EBI_CSR1);
-                writel(0, EBI_LOCK);
+        if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
+              & INTEGRATOR_EBI_WRITE_ENABLE)) {
+                writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
+                writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
+                writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
         }
         return 0;
 }
@@ -202,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev)
         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 
-        tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
-        writel(tmp, EBI_CSR1);
+        tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
+                ~INTEGRATOR_EBI_WRITE_ENABLE;
+        writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 
-        if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
-                writel(0xa05f, EBI_LOCK);
-                writel(tmp, EBI_CSR1);
-                writel(0, EBI_LOCK);
+        if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
+            INTEGRATOR_EBI_WRITE_ENABLE) {
+                writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
+                writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
+                writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
         }
 }
 
@@ -277,7 +267,7 @@ struct amba_pl010_data ap_uart_data = {
 
 static unsigned long timer_reload;
 
-static u32 notrace integrator_read_sched_clock(void)
+static u64 notrace integrator_read_sched_clock(void)
 {
         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
@@ -298,7 +288,7 @@ static void integrator_clocksource_init(unsigned long inrate,
 
         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
                         rate, 200, 16, clocksource_mmio_readl_down);
-        setup_sched_clock(integrator_read_sched_clock, 16, rate);
+        sched_clock_register(integrator_read_sched_clock, 16, rate);
 }
 
 static void __iomem * clkevt_base;
@@ -475,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = {
         { },
 };
 
+static const struct of_device_id ebi_match[] = {
+        { .compatible = "arm,external-bus-interface"},
+        { },
+};
+
 static void __init ap_init_of(void)
 {
         unsigned long sc_dec;
         struct device_node *root;
         struct device_node *syscon;
+        struct device_node *ebi;
         struct device *parent;
         struct soc_device *soc_dev;
         struct soc_device_attribute *soc_dev_attr;
@@ -495,10 +491,16 @@ static void __init ap_init_of(void)
         syscon = of_find_matching_node(root, ap_syscon_match);
         if (!syscon)
                 return;
+        ebi = of_find_matching_node(root, ebi_match);
+        if (!ebi)
+                return;
 
         ap_syscon_base = of_iomap(syscon, 0);
         if (!ap_syscon_base)
                 return;
+        ebi_base = of_iomap(ebi, 0);
+        if (!ebi_base)
+                return;
 
         ap_sc_id = readl(ap_syscon_base);
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4fc0a195de01..a3ef961e4a93 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -65,8 +65,6 @@ static void __iomem *intcp_con_base;
 /*
  * Logical      Physical
  * f1000000     10000000        Core module registers
- * f1100000     11000000        System controller registers
- * f1200000     12000000        EBI registers
  * f1300000     13000000        Counter/Timer
  * f1400000     14000000        Interrupt controller
  * f1600000     16000000        UART 0
@@ -74,7 +72,6 @@ static void __iomem *intcp_con_base;
  * f1a00000     1a000000        Debug LEDs
  * fc900000     c9000000        GPIO
  * fca00000     ca000000        SIC
- * fcb00000     cb000000        CP system control
  */
 
 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
@@ -84,11 +81,6 @@ static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 177cd073a83b..77e1ff057303 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
 #include <mach/hardware.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -176,11 +177,35 @@ static struct platform_device em7210_serial_device = {
         .resource       = &em7210_uart_resource,
 };
 
+#define EM7210_HARDWARE_POWER 0
+
 void em7210_power_off(void)
 {
-        *IOP3XX_GPOE &= 0xfe;
-        *IOP3XX_GPOD |= 0x01;
+        int ret;
+
+        ret = gpio_direction_output(EM7210_HARDWARE_POWER, 1);
+        if (ret)
+                pr_crit("could not drive power off GPIO high\n");
+}
+
+static int __init em7210_request_gpios(void)
+{
+        int ret;
+
+        if (!machine_is_em7210())
+                return 0;
+
+        ret = gpio_request(EM7210_HARDWARE_POWER, "power");
+        if (ret) {
+                pr_err("could not request power off GPIO\n");
+                return 0;
+        }
+
+        pm_power_off = em7210_power_off;
+
+        return 0;
 }
+device_initcall(em7210_request_gpios);
 
 static void __init em7210_init_machine(void)
 {
@@ -194,9 +219,6 @@ static void __init em7210_init_machine(void)
 
         i2c_register_board_info(0, em7210_i2c_devices,
                 ARRAY_SIZE(em7210_i2c_devices));
-
-
-        pm_power_off = em7210_power_off;
 }
 
 MACHINE_START(EM7210, "Lanner EM7210")
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 6d6bde3e15fa..200970d56f6d 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -326,7 +326,7 @@ static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t s
  */
 static int ixp4xx_pci_platform_notify(struct device *dev)
 {
-        if(dev->bus == &pci_bus_type) {
+        if (dev_is_pci(dev)) {
                 *dev->dma_mask =  SZ_64M - 1;
                 dev->coherent_dma_mask = SZ_64M - 1;
                 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
@@ -336,9 +336,9 @@ static int ixp4xx_pci_platform_notify(struct device *dev)
 
 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
 {
-        if(dev->bus == &pci_bus_type) {
+        if (dev_is_pci(dev))
                 dmabounce_unregister_dev(dev);
-        }
+
         return 0;
 }
 
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 9edaf4734fa8..6d68aed6548a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -475,7 +475,7 @@ void __init ixp4xx_sys_init(void)
 /*
  * sched_clock()
  */
-static u32 notrace ixp4xx_read_sched_clock(void)
+static u64 notrace ixp4xx_read_sched_clock(void)
 {
         return *IXP4XX_OSTS;
 }
@@ -493,7 +493,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 EXPORT_SYMBOL(ixp4xx_timer_freq);
 static void __init ixp4xx_clocksource_init(void)
 {
-        setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
+        sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
 
         clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
                         ixp4xx_clocksource_read);
@@ -560,7 +560,7 @@ static void __init ixp4xx_clockevent_init(void)
 
 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if ( 1 && mode == REBOOT_SOFT) {
+        if (mode == REBOOT_SOFT) {
                 /* Jump into ROM at address 0 */
                 soft_restart(0);
         } else {
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index f20c53e75ed9..90a708fef541 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -10,7 +10,8 @@ config ARCH_KEYSTONE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_ERRATA_798181 if SMP
         select COMMON_CLK_KEYSTONE
-        select TI_EDMA
+        select ARCH_SUPPORTS_BIG_ENDIAN
+        select ZONE_DMA if ARM_LPAE
         help
           Support for boards based on the Texas Instruments Keystone family of
           SoCs.
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index b661c5c2870a..6e6bb7d5ea30 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -41,6 +41,7 @@ static void __init keystone_init(void)
         if (WARN_ON(!keystone_rstctrl))
                 pr_warn("ti,keystone-reset iomap error\n");
 
+        keystone_pm_runtime_init();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -68,6 +69,9 @@ void keystone_restart(enum reboot_mode mode, const char *cmd)
 }
 
 DT_MACHINE_START(KEYSTONE, "Keystone")
+#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
+        .dma_zone_size  = SZ_2G,
+#endif
         .smp            = smp_ops(keystone_smp_ops),
         .init_machine   = keystone_init,
         .dt_compat      = keystone_match,
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
index 60bef9dedb12..cd04a1c14de8 100644
--- a/arch/arm/mach-keystone/keystone.h
+++ b/arch/arm/mach-keystone/keystone.h
@@ -18,6 +18,7 @@
 extern struct smp_operations keystone_smp_ops;
 extern void secondary_startup(void);
 extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
+extern int keystone_pm_runtime_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c
index 29625232e954..ca79ddac38bc 100644
--- a/arch/arm/mach-keystone/pm_domain.c
+++ b/arch/arm/mach-keystone/pm_domain.c
@@ -74,9 +74,7 @@ int __init keystone_pm_runtime_init(void)
         if (!np)
                 return 0;
 
-        of_clk_init(NULL);
         pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
 
         return 0;
 }
-subsys_initcall(keystone_pm_runtime_init);
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 9caa4fe95913..78188159484d 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -10,55 +10,21 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_net.h>
 #include <linux/of_platform.h>
-#include <linux/clk-provider.h>
 #include <linux/dma-mapping.h>
 #include <linux/irqchip.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
-#include <linux/platform_data/usb-ehci-orion.h>
-#include <plat/irq.h>
 #include <plat/common.h>
 #include "common.h"
 
-/*
- * There are still devices that doesn't know about DT yet.  Get clock
- * gates here and add a clock lookup alias, so that old platform
- * devices still work.
-*/
-
-static void __init kirkwood_legacy_clk_init(void)
-{
-
-        struct device_node *np = of_find_compatible_node(
-                NULL, NULL, "marvell,kirkwood-gating-clock");
-        struct of_phandle_args clkspec;
-        struct clk *clk;
-
-        clkspec.np = np;
-        clkspec.args_count = 1;
-
-        /*
-         * The ethernet interfaces forget the MAC address assigned by
-         * u-boot if the clocks are turned off. Until proper DT support
-         * is available we always enable them for now.
-         */
-        clkspec.args[0] = CGC_BIT_GE0;
-        clk = of_clk_get_from_provider(&clkspec);
-        clk_prepare_enable(clk);
-
-        clkspec.args[0] = CGC_BIT_GE1;
-        clk = of_clk_get_from_provider(&clkspec);
-        clk_prepare_enable(clk);
-}
-
 #define MV643XX_ETH_MAC_ADDR_LOW        0x0414
 #define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
 
@@ -140,7 +106,7 @@ eth_fixup_skip:
 
 static void __init kirkwood_dt_init(void)
 {
-        pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+        pr_info("Kirkwood: %s.\n", kirkwood_id());
 
         /*
          * Disable propagation of mbus errors to the CPU local bus,
@@ -156,8 +122,6 @@ static void __init kirkwood_dt_init(void)
 
         kirkwood_cpufreq_init();
         kirkwood_cpuidle_init();
-        /* Setup clocks for legacy devices */
-        kirkwood_legacy_clk_init();
 
         kirkwood_pm_init();
         kirkwood_dt_eth_fixup();
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
index 8783a7184e73..c6ab8d9303a5 100644
--- a/arch/arm/mach-kirkwood/pm.c
+++ b/arch/arm/mach-kirkwood/pm.c
@@ -18,6 +18,7 @@
 #include <linux/suspend.h>
 #include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include "common.h"
 
 static void __iomem *ddr_operation_base;
 
@@ -65,9 +66,8 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = {
         .valid = kirkwood_pm_valid_standby,
 };
 
-int __init kirkwood_pm_init(void)
+void __init kirkwood_pm_init(void)
 {
         ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
         suspend_set_ops(&kirkwood_suspend_ops);
-        return 0;
 }
diff --git a/arch/arm/mach-ks8695/include/mach/gpio.h b/arch/arm/mach-ks8695/include/mach/gpio.h
deleted file mode 100644
index f5fda36e4512..000000000000
--- a/arch/arm/mach-ks8695/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/gpio.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_GPIO_H_
-#define __ASM_ARCH_GPIO_H_
-
-/*
- * Map IRQ number to GPIO line.
- */
-extern int irq_to_gpio(unsigned int irq);
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
deleted file mode 100644
index a544e962a818..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_GPIO_LPC32XX_H
-#define __MACH_GPIO_LPC32XX_H
-
-/*
- * Note!
- * Muxed GP pins need to be setup to the GP state in the board level
- * code prior to using this driver.
- * GPI pins : 28xP3 group
- * GPO pins : 24xP3 group
- * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
- */
-
-#define LPC32XX_GPIO_P0_MAX 8
-#define LPC32XX_GPIO_P1_MAX 24
-#define LPC32XX_GPIO_P2_MAX 13
-#define LPC32XX_GPIO_P3_MAX 6
-#define LPC32XX_GPI_P3_MAX 29
-#define LPC32XX_GPO_P3_MAX 24
-
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
-#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
-#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
-#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* __MACH_GPIO_LPC32XX_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
deleted file mode 100644
index 0052e7a76179..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include "gpio-lpc32xx.h"
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index e54f87ec2e4a..34932e0e31fa 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -36,6 +36,7 @@
 #include <linux/clk.h>
 #include <linux/mtd/lpc32xx_slc.h>
 #include <linux/mtd/lpc32xx_mlc.h>
+#include <linux/platform_data/gpio-lpc32xx.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -44,7 +45,6 @@
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <mach/board.h>
-#include <mach/gpio-lpc32xx.h>
 #include "common.h"
 
 /*
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdda8346a26..ebdba87b9671 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -136,4 +136,7 @@ config USB_EHCI_MV_U2O
         help
           Enables support for OTG controller which can be switched to host mode.
 
+config MMP_SRAM
+        bool
+
 endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 9b702a1dc7b0..98f0f6388e44 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -7,7 +7,8 @@ obj-y				+= common.o devices.o time.o
 # SoC support
 obj-$(CONFIG_CPU_PXA168)        += pxa168.o
 obj-$(CONFIG_CPU_PXA910)        += pxa910.o
-obj-$(CONFIG_CPU_MMP2)          += mmp2.o sram.o
+obj-$(CONFIG_CPU_MMP2)          += mmp2.o
+obj-$(CONFIG_MMP_SRAM)          += sram.o
 
 ifeq ($(CONFIG_COMMON_CLK), )
 obj-y                           += clock.o
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 7ac41e83cfef..024022d91fe3 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -61,7 +61,7 @@ static inline uint32_t timer_read(void)
         return __raw_readl(mmp_timer_base + TMR_CVWR(1));
 }
 
-static u32 notrace mmp_read_sched_clock(void)
+static u64 notrace mmp_read_sched_clock(void)
 {
         return timer_read();
 }
@@ -195,7 +195,7 @@ void __init timer_init(int irq)
 {
         timer_config();
 
-        setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
+        sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
 
         ckevt.cpumask = cpumask_of(0);
 
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
new file mode 100644
index 000000000000..ba470d64493b
--- /dev/null
+++ b/arch/arm/mach-moxart/Kconfig
@@ -0,0 +1,31 @@
+config ARCH_MOXART
+        bool "MOXA ART SoC" if ARCH_MULTI_V4T
+        select CPU_FA526
+        select ARM_DMA_MEM_BUFFERABLE
+        select DMA_OF
+        select USE_OF
+        select CLKSRC_OF
+        select CLKSRC_MMIO
+        select HAVE_CLK
+        select COMMON_CLK
+        select GENERIC_IRQ_CHIP
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_CLOCKEVENTS
+        select PHYLIB if NETDEVICES
+        help
+          Say Y here if you want to run your kernel on hardware with a
+          MOXA ART SoC.
+          The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
+          192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
+          Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
+
+if ARCH_MOXART
+
+config MACH_UC7112LX
+        bool "MOXA UC-7112-LX"
+        depends on ARCH_MOXART
+        help
+          Say Y here if you intend to run this kernel on a MOXA
+          UC-7112-LX embedded computer.
+
+endif
diff --git a/arch/arm/mach-moxart/Makefile b/arch/arm/mach-moxart/Makefile
new file mode 100644
index 000000000000..fa022eb10ca1
--- /dev/null
+++ b/arch/arm/mach-moxart/Makefile
@@ -0,0 +1,3 @@
+# Object file lists.
+
+obj-$(CONFIG_MACH_UC7112LX)     += moxart.o
diff --git a/arch/arm/mach-moxart/moxart.c b/arch/arm/mach-moxart/moxart.c
new file mode 100644
index 000000000000..86b6d9b57c54
--- /dev/null
+++ b/arch/arm/mach-moxart/moxart.c
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-moxart/moxart.c
+ *
+ * (C) Copyright 2013, Jonas Jensen <jonas.jensen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 2586c2865874..9625cf378931 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,12 +1,50 @@
+config ARCH_MSM
+        bool
+
+config ARCH_MSM_DT
+        bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
+        select ARCH_MSM
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for Qualcomm's devicetree based MSM systems.
+
 if ARCH_MSM
 
-comment "Qualcomm MSM SoC Type"
+menu "Qualcomm MSM SoC Selection"
         depends on ARCH_MSM_DT
 
+config ARCH_MSM8X60
+        bool "Enable support for MSM8X60"
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_SMP
+        select MSM_SCM if SMP
+        select MSM_TIMER
+
+config ARCH_MSM8960
+        bool "Enable support for MSM8960"
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_SMP
+        select MSM_SCM if SMP
+        select MSM_TIMER
+
+config ARCH_MSM8974
+        bool "Enable support for MSM8974"
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_SMP
+        select MSM_SCM if SMP
+
+endmenu
+
 choice
         prompt "Qualcomm MSM SoC Type"
         default ARCH_MSM7X00A
-        depends on !ARCH_MSM_DT
+        depends on ARCH_MSM_NODT
 
 config ARCH_MSM7X00A
         bool "MSM7x00A / MSM7x01A"
@@ -16,6 +54,7 @@ config ARCH_MSM7X00A
         select MACH_TROUT if !MACH_HALIBUT
         select MSM_PROC_COMM
         select MSM_SMD
+        select MSM_TIMER
         select MSM_SMD_PKG3
 
 config ARCH_MSM7X30
@@ -27,6 +66,7 @@ config ARCH_MSM7X30
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select MSM_SMD
+        select MSM_TIMER
         select MSM_VIC
 
 config ARCH_QSD8X50
@@ -38,32 +78,11 @@ config ARCH_QSD8X50
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select MSM_SMD
+        select MSM_TIMER
         select MSM_VIC
 
 endchoice
 
-config ARCH_MSM8X60
-        bool "MSM8X60"
-        select ARM_GIC
-        select CPU_V7
-        select GPIO_MSM_V2
-        select HAVE_SMP
-        select MSM_SCM if SMP
-
-config ARCH_MSM8960
-        bool "MSM8960"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select GPIO_MSM_V2
-        select MSM_SCM if SMP
-
-config ARCH_MSM_DT
-        def_bool y
-        depends on (ARCH_MSM8X60 || ARCH_MSM8960)
-        select SPARSE_IRQ
-        select USE_OF
-
 config MSM_HAS_DEBUG_UART_HS
         bool
 
@@ -80,7 +99,7 @@ config  MSM_VIC
         bool
 
 menu "Qualcomm MSM Board Type"
-        depends on !ARCH_MSM_DT
+        depends on ARCH_MSM_NODT
 
 config MACH_HALIBUT
         depends on ARCH_MSM
@@ -128,10 +147,13 @@ config MSM_SMD
 
 config MSM_GPIOMUX
         bool
-        depends on !ARCH_MSM_DT
         help
           Support for MSM V1 TLMM GPIOMUX architecture.
 
 config MSM_SCM
         bool
+
+config MSM_TIMER
+        bool
+
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 7ed4c1b2bdd2..8e307a10d3c3 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,5 +1,5 @@
-obj-y += timer.o
-obj-y += clock.o
+obj-$(CONFIG_MSM_TIMER) += timer.o
+obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c
index 16e6183ac9f1..1f11d93e700e 100644
--- a/arch/arm/mach-msm/board-dt.c
+++ b/arch/arm/mach-msm/board-dt.c
@@ -26,7 +26,16 @@ static const char * const msm_dt_match[] __initconst = {
         NULL
 };
 
+static const char * const apq8074_dt_match[] __initconst = {
+        "qcom,apq8074-dragonboard",
+        NULL
+};
+
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
         .smp = smp_ops(msm_smp_ops),
         .dt_compat = msm_dt_match,
 MACHINE_END
+
+DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .dt_compat = apq8074_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index f9af5a46e8b6..46de789ad3ae 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -30,6 +30,7 @@
 #include <asm/memory.h>
 #include <asm/setup.h>
 
+#include <mach/clk.h>
 #include <mach/msm_iomap.h>
 #include <mach/dma.h>
 
@@ -60,10 +61,44 @@ static int hsusb_phy_init_seq[] = {
         -1
 };
 
+static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
+{
+        int ret;
+
+        if (assert) {
+                ret = clk_reset(link_clk, CLK_RESET_ASSERT);
+                if (ret)
+                        pr_err("usb hs_clk assert failed\n");
+        } else {
+                ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
+                if (ret)
+                        pr_err("usb hs_clk deassert failed\n");
+        }
+        return ret;
+}
+
+static int hsusb_phy_clk_reset(struct clk *phy_clk)
+{
+        int ret;
+
+        ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
+        if (ret) {
+                pr_err("usb phy clk assert failed\n");
+                return ret;
+        }
+        usleep_range(10000, 12000);
+        ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
+        if (ret)
+                pr_err("usb phy clk deassert failed\n");
+        return ret;
+}
+
 static struct msm_otg_platform_data msm_otg_pdata = {
         .phy_init_seq           = hsusb_phy_init_seq,
         .mode                   = USB_PERIPHERAL,
         .otg_control            = OTG_PHY_CONTROL,
+        .link_clk_reset         = hsusb_link_clk_reset,
+        .phy_clk_reset          = hsusb_phy_clk_reset,
 };
 
 struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 5f933bc50783..9169ec324a43 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -31,6 +31,7 @@
 #include <mach/irqs.h>
 #include <mach/sirc.h>
 #include <mach/vreg.h>
+#include <mach/clk.h>
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
 #include "devices.h"
@@ -81,10 +82,44 @@ static int hsusb_phy_init_seq[] = {
         -1
 };
 
+static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
+{
+        int ret;
+
+        if (assert) {
+                ret = clk_reset(link_clk, CLK_RESET_ASSERT);
+                if (ret)
+                        pr_err("usb hs_clk assert failed\n");
+        } else {
+                ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
+                if (ret)
+                        pr_err("usb hs_clk deassert failed\n");
+        }
+        return ret;
+}
+
+static int hsusb_phy_clk_reset(struct clk *phy_clk)
+{
+        int ret;
+
+        ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
+        if (ret) {
+                pr_err("usb phy clk assert failed\n");
+                return ret;
+        }
+        usleep_range(10000, 12000);
+        ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
+        if (ret)
+                pr_err("usb phy clk deassert failed\n");
+        return ret;
+}
+
 static struct msm_otg_platform_data msm_otg_pdata = {
         .phy_init_seq           = hsusb_phy_init_seq,
         .mode                   = USB_PERIPHERAL,
         .otg_control            = OTG_PHY_CONTROL,
+        .link_clk_reset         = hsusb_link_clk_reset,
+        .phy_clk_reset          = hsusb_phy_clk_reset,
 };
 
 static struct platform_device *devices[] __initdata = {
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index ccf6621bc664..015d544aa017 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  *
  */
+#define pr_fmt(fmt) "%s: " fmt, __func__
 
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -68,12 +69,11 @@ static void __init trout_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-#ifdef CONFIG_MMC
-        rc = trout_init_mmc(system_rev);
-        if (rc)
-                printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc);
-#endif
-
+        if (IS_ENABLED(CONFIG_MMC)) {
+                rc = trout_init_mmc(system_rev);
+                if (rc)
+                        pr_crit("MMC init failure (%d)\n", rc);
+        }
 }
 
 static struct map_desc trout_io_desc[] __initdata = {
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 3f06edcdd0ce..f10a1f58fde9 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -99,8 +99,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * "cpu" is Linux's internal ID.
          */
         pen_release = cpu_logical_map(cpu);
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 
         /*
          * Send the secondary CPU a soft interrupt, thereby causing
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1e9c3383daba..fd1644987534 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -187,7 +187,7 @@ static struct notifier_block msm_timer_cpu_nb = {
         .notifier_call = msm_timer_cpu_notify,
 };
 
-static notrace u32 msm_sched_clock_read(void)
+static u64 notrace msm_sched_clock_read(void)
 {
         return msm_clocksource.read(&msm_clocksource);
 }
@@ -229,7 +229,7 @@ err:
         res = clocksource_register_hz(cs, dgt_hz);
         if (res)
                 pr_err("clocksource_register failed\n");
-        setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
+        sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
 }
 
 #ifdef CONFIG_OF
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h
deleted file mode 100644
index 77e1b843e768..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/asm-arm/mach-mv78xx0/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 2d04f0e21870..878aebe98dcc 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
 
-obj-y                            += system-controller.o
+obj-y                            += system-controller.o mvebu-soc-id.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
 obj-$(CONFIG_ARCH_MVEBU)         += coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index e2acff98e750..f6c9d1d85c14 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -21,6 +21,7 @@
 #include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
+#include <linux/slab.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -28,6 +29,7 @@
 #include "armada-370-xp.h"
 #include "common.h"
 #include "coherency.h"
+#include "mvebu-soc-id.h"
 
 static void __init armada_370_xp_map_io(void)
 {
@@ -45,8 +47,38 @@ static void __init armada_370_xp_timer_and_clk_init(void)
 #endif
 }
 
+static void __init i2c_quirk(void)
+{
+        struct device_node *np;
+        u32 dev, rev;
+
+        /*
+         * Only revisons more recent than A0 support the offload
+         * mechanism. We can exit only if we are sure that we can
+         * get the SoC revision and it is more recent than A0.
+         */
+        if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV)
+                return;
+
+        for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
+                struct property *new_compat;
+
+                new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
+
+                new_compat->name = kstrdup("compatible", GFP_KERNEL);
+                new_compat->length = sizeof("marvell,mv78230-a0-i2c");
+                new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
+                                                GFP_KERNEL);
+
+                of_update_property(np, new_compat);
+        }
+        return;
+}
+
 static void __init armada_370_xp_dt_init(void)
 {
+        if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
+                i2c_quirk();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c612b2c4ed6c..237c86b83390 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -18,8 +18,12 @@
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
 
+#define ARMADA_XP_MAX_CPUS 4
+
 void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
 void armada_xp_mpic_smp_cpu_init(void);
+void armada_xp_secondary_startup(void);
+extern struct smp_operations armada_xp_smp_ops;
 #endif
 
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 58adf2fd9cfc..4e9d58148ca7 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,6 +27,7 @@
 #include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
 #include "armada-370-xp.h"
+#include "coherency.h"
 
 unsigned long coherency_phys_base;
 static void __iomem *coherency_base;
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index df33ad8a6c08..760226c41353 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,7 +14,9 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
 
-int set_cpu_coherent(int cpu_id, int smp_group_id);
+extern unsigned long coherency_phys_base;
+
+int set_cpu_coherent(unsigned int cpu_id, int smp_group_id);
 int coherency_init(void);
 
 #endif  /* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index e366010e1d91..55449c487c9e 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,18 +15,10 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
-#define ARMADA_XP_MAX_CPUS 4
-
 #include <linux/reboot.h>
 
 void mvebu_restart(enum reboot_mode mode, const char *cmd);
 
-void armada_370_xp_init_irq(void);
-void armada_370_xp_handle_irq(struct pt_regs *regs);
-
 void armada_xp_cpu_die(unsigned int cpu);
-int armada_370_xp_coherency_init(void);
-int armada_370_xp_pmsu_init(void);
-void armada_xp_secondary_startup(void);
-extern struct smp_operations armada_xp_smp_ops;
+
 #endif
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
index b228b6a80c85..d95e91047168 100644
--- a/arch/arm/mach-mvebu/hotplug.c
+++ b/arch/arm/mach-mvebu/hotplug.c
@@ -15,6 +15,7 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <asm/proc-fns.h>
+#include "common.h"
 
 /*
  * platform-specific code to shutdown a CPU
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
new file mode 100644
index 000000000000..f3b325f6cbd4
--- /dev/null
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -0,0 +1,119 @@
+/*
+ * ID and revision information for mvebu SoCs
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * All the mvebu SoCs have information related to their variant and
+ * revision that can be read from the PCI control register. This is
+ * done before the PCI initialization to avoid any conflict. Once the
+ * ID and revision are retrieved, the mapping is freed.
+ */
+
+#define pr_fmt(fmt) "mvebu-soc-id: " fmt
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include "mvebu-soc-id.h"
+
+#define PCIE_DEV_ID_OFF         0x0
+#define PCIE_DEV_REV_OFF        0x8
+
+#define SOC_ID_MASK         0xFFFF0000
+#define SOC_REV_MASK        0xFF
+
+static u32 soc_dev_id;
+static u32 soc_rev;
+static bool is_id_valid;
+
+static const struct of_device_id mvebu_pcie_of_match_table[] = {
+        { .compatible = "marvell,armada-xp-pcie", },
+        { .compatible = "marvell,armada-370-pcie", },
+        {},
+};
+
+int mvebu_get_soc_id(u32 *dev, u32 *rev)
+{
+        if (is_id_valid) {
+                *dev = soc_dev_id;
+                *rev = soc_rev;
+                return 0;
+        } else
+                return -1;
+}
+
+static int __init mvebu_soc_id_init(void)
+{
+        struct device_node *np;
+        int ret = 0;
+        void __iomem *pci_base;
+        struct clk *clk;
+        struct device_node *child;
+
+        np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
+        if (!np)
+                return ret;
+
+        /*
+         * ID and revision are available from any port, so we
+         * just pick the first one
+         */
+        child = of_get_next_child(np, NULL);
+        if (child == NULL) {
+                pr_err("cannot get pci node\n");
+                ret = -ENOMEM;
+                goto clk_err;
+        }
+
+        clk = of_clk_get_by_name(child, NULL);
+        if (IS_ERR(clk)) {
+                pr_err("cannot get clock\n");
+                ret = -ENOMEM;
+                goto clk_err;
+        }
+
+        ret = clk_prepare_enable(clk);
+        if (ret) {
+                pr_err("cannot enable clock\n");
+                goto clk_err;
+        }
+
+        pci_base = of_iomap(child, 0);
+        if (pci_base == NULL) {
+                pr_err("cannot map registers\n");
+                ret = -ENOMEM;
+                goto res_ioremap;
+        }
+
+        /* SoC ID */
+        soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
+
+        /* SoC revision */
+        soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
+
+        is_id_valid = true;
+
+        pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
+
+        iounmap(pci_base);
+
+res_ioremap:
+        clk_disable_unprepare(clk);
+
+clk_err:
+        of_node_put(child);
+        of_node_put(np);
+
+        return ret;
+}
+core_initcall(mvebu_soc_id_init);
+
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h
new file mode 100644
index 000000000000..31654252fe35
--- /dev/null
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.h
@@ -0,0 +1,32 @@
+/*
+ * Marvell EBU SoC ID and revision definitions.
+ *
+ * Copyright (C) 2014 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MVEBU_SOC_ID_H
+#define __LINUX_MVEBU_SOC_ID_H
+
+/* Armada XP ID */
+#define MV78230_DEV_ID      0x7823
+#define MV78260_DEV_ID      0x7826
+#define MV78460_DEV_ID      0x7846
+
+/* Armada XP Revision */
+#define MV78XX0_A0_REV      0x1
+#define MV78XX0_B0_REV      0x2
+
+#ifdef CONFIG_ARCH_MVEBU
+int mvebu_get_soc_id(u32 *dev, u32 *rev);
+#else
+static inline int mvebu_get_soc_id(u32 *dev, u32 *rev)
+{
+        return -1;
+}
+#endif
+
+#endif /* __LINUX_MVEBU_SOC_ID_H */
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index ff69c2df298b..a6da03f5b24e 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -46,7 +46,7 @@ static struct clk *__init get_cpu_clk(int cpu)
         return cpu_clk;
 }
 
-void __init set_secondary_cpus_clock(void)
+static void __init set_secondary_cpus_clock(void)
 {
         int thiscpu, cpu;
         unsigned long rate;
@@ -94,7 +94,7 @@ static void __init armada_xp_smp_init_cpus(void)
         set_smp_cross_call(armada_mpic_send_doorbell);
 }
 
-void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
+static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
 {
         struct device_node *node;
         struct resource res;
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 27fc4f049474..d71ef53107c4 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/smp.h>
 #include <asm/smp_plat.h>
+#include "pmsu.h"
 
 static void __iomem *pmsu_mp_base;
 static void __iomem *pmsu_reset_base;
@@ -58,7 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr)
 }
 #endif
 
-int __init armada_370_xp_pmsu_init(void)
+static int __init armada_370_xp_pmsu_init(void)
 {
         struct device_node *np;
 
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 5175083cdb34..a7fb89a5b5d9 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -27,6 +27,7 @@
 #include <linux/of_address.h>
 #include <linux/io.h>
 #include <linux/reboot.h>
+#include "common.h"
 
 static void __iomem *system_controller_base;
 
@@ -39,14 +40,14 @@ struct mvebu_system_controller {
 };
 static struct mvebu_system_controller *mvebu_sc;
 
-const struct mvebu_system_controller armada_370_xp_system_controller = {
+static const struct mvebu_system_controller armada_370_xp_system_controller = {
         .rstoutn_mask_offset = 0x60,
         .system_soft_reset_offset = 0x64,
         .rstoutn_mask_reset_out_en = 0x1,
         .system_soft_reset = 0x1,
 };
 
-const struct mvebu_system_controller orion_system_controller = {
+static const struct mvebu_system_controller orion_system_controller = {
         .rstoutn_mask_offset = 0x108,
         .system_soft_reset_offset = 0x10c,
         .rstoutn_mask_reset_out_en = 0x4,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index cce2c9dfb5d1..4a1065e41e9c 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -110,38 +110,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
 }
 
 /*
- * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects
- * to simply request an IRQ passed as a resource. So the GPIO pin needs
- * to be requested by this hog and set as input.
- */
-static int __init cpu8815_eth_init(void)
-{
-        struct device_node *eth;
-        int gpio, irq, err;
-
-        eth = of_find_node_by_path("/usb-s8815/ethernet-gpio");
-        if (!eth) {
-                pr_info("could not find any ethernet GPIO\n");
-                return 0;
-        }
-        gpio = of_get_gpio(eth, 0);
-        err = gpio_request(gpio, "eth_irq");
-        if (err) {
-                pr_info("failed to request ethernet GPIO\n");
-                return -ENODEV;
-        }
-        err = gpio_direction_input(gpio);
-        if (err) {
-                pr_info("failed to set ethernet GPIO as input\n");
-                return -ENODEV;
-        }
-        irq = gpio_to_irq(gpio);
-        pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq);
-        return 0;
-}
-device_initcall(cpu8815_eth_init);
-
-/*
  * This GPIO pin turns on a line that is used to detect card insertion
  * on this board.
  */
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
index 45e5ac707cbb..2c263051dc51 100644
--- a/arch/arm/mach-omap1/include/mach/usb.h
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -8,43 +8,7 @@
 #define is_usb0_device(config)  0
 #endif
 
-struct omap_usb_config {
-        /* Configure drivers according to the connectors on your board:
-         *  - "A" connector (rectagular)
-         *      ... for host/OHCI use, set "register_host".
-         *  - "B" connector (squarish) or "Mini-B"
-         *      ... for device/gadget use, set "register_dev".
-         *  - "Mini-AB" connector (very similar to Mini-B)
-         *      ... for OTG use as device OR host, initialize "otg"
-         */
-        unsigned        register_host:1;
-        unsigned        register_dev:1;
-        u8              otg;    /* port number, 1-based:  usb1 == 2 */
-
-        u8              hmc_mode;
-
-        /* implicitly true if otg:  host supports remote wakeup? */
-        u8              rwc;
-
-        /* signaling pins used to talk to transceiver on usbN:
-         *  0 == usbN unused
-         *  2 == usb0-only, using internal transceiver
-         *  3 == 3 wire bidirectional
-         *  4 == 4 wire bidirectional
-         *  6 == 6 wire unidirectional (or TLL)
-         */
-        u8              pins[3];
-
-        struct platform_device *udc_device;
-        struct platform_device *ohci_device;
-        struct platform_device *otg_device;
-
-        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
-        u32 (*usb1_init)(unsigned nwires);
-        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
-
-        int (*ocpi_enable)(void);
-};
+#include <linux/platform_data/usb-omap1.h>
 
 void omap_otg_init(struct omap_usb_config *config);
 
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 6b5f298d6638..a7588cfd0286 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -181,7 +181,7 @@ static __init void omap_init_mpu_timer(unsigned long rate)
  * ---------------------------------------------------------------------------
  */
 
-static u32 notrace omap_mpu_read_sched_clock(void)
+static u64 notrace omap_mpu_read_sched_clock(void)
 {
         return ~omap_mpu_timer_read(1);
 }
@@ -193,7 +193,7 @@ static void __init omap_init_clocksource(unsigned long rate)
                         "%s: can't register clocksource!\n";
 
         omap_mpu_timer_start(1, ~0, 1);
-        setup_sched_clock(omap_mpu_read_sched_clock, 32, rate);
+        sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
 
         if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
                         300, 32, clocksource_mmio_readl_down))
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df166161..653b489479e0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,6 +76,16 @@ config SOC_AM43XX
         select ARM_GIC
         select MACH_OMAP_GENERIC
 
+config SOC_DRA7XX
+        bool "TI DRA7XX"
+        depends on ARCH_MULTI_V7
+        select ARCH_OMAP2PLUS
+        select ARM_CPU_SUSPEND if PM
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_SMP
+        select HAVE_ARM_ARCH_TIMER
+
 config ARCH_OMAP2PLUS
         bool
         select ARCH_HAS_BANDGAP
@@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER
         depends on SOC_OMAP5 || SOC_DRA7XX
         default y
 
-config SOC_DRA7XX
-        bool "TI DRA7XX"
-        select ARM_ARCH_TIMER
-        select CPU_V7
-        select ARM_GIC
-        select HAVE_SMP
-        select COMMON_CLK
-
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
@@ -192,19 +194,6 @@ config MACH_OMAP2_TUSB6010
         depends on ARCH_OMAP2 && SOC_OMAP2420
         default y if MACH_NOKIA_N8X0
 
-config MACH_OMAP_H4
-        bool "OMAP 2420 H4 board"
-        depends on SOC_OMAP2420
-        default y
-        select OMAP_DEBUG_DEVICES
-        select OMAP_PACKAGE_ZAF
-
-config MACH_OMAP_2430SDP
-        bool "OMAP 2430 SDP board"
-        depends on SOC_OMAP2430
-        default y
-        select OMAP_PACKAGE_ZAC
-
 config MACH_OMAP3_BEAGLE
         bool "OMAP3 BEAGLE board"
         depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index adcef406ff0a..e6eec6f72fd3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5)			+= omap4-restart.o
 obj-$(CONFIG_SOC_DRA7XX)                += omap4-restart.o
 
 # Pin multiplexing
-obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
-obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
 
 # SMS/SDRC
@@ -132,6 +130,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
 obj-$(CONFIG_SOC_AM43XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -186,12 +185,14 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)                += cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX)                += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_AM43XX)                += $(clock-common) dpll3xxx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
@@ -237,8 +238,6 @@ obj-$(CONFIG_SOC_OMAP2420)		+= msdi.o
 
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o pdata-quirks.o
-obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
-obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
 obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
deleted file mode 100644
index c711ad6ac067..000000000000
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-2430sdp.c
- *
- * Copyright (C) 2006 Texas Instruments
- *
- * Modified from mach-omap2/board-generic.c
- *
- * Initial Code : Based on a patch from Komal Shah and Richard Woodruff
- * Updated the Code for 2430 SDP : Syed Mohammed Khasim
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mmc/host.h>
-#include <linux/delay.h>
-#include <linux/i2c/twl.h>
-#include <linux/regulator/machine.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/usb/phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "gpmc.h"
-#include "gpmc-smc91x.h"
-
-#include <video/omapdss.h>
-#include <video/omap-panel-data.h>
-
-#include "mux.h"
-#include "hsmmc.h"
-#include "common-board-devices.h"
-
-#define SDP2430_CS0_BASE        0x04000000
-#define SECONDARY_LCD_GPIO              147
-
-static struct mtd_partition sdp2430_partitions[] = {
-        /* bootloader (U-Boot, etc) in first sector */
-        {
-                .name           = "bootloader",
-                .offset         = 0,
-                .size           = SZ_256K,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-         },
-        /* bootloader params in the next sector */
-        {
-                .name           = "params",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_128K,
-                .mask_flags     = 0,
-         },
-        /* kernel */
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_2M,
-                .mask_flags     = 0
-        },
-        /* file system */
-        {
-                .name           = "filesystem",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = 0
-        }
-};
-
-static struct physmap_flash_data sdp2430_flash_data = {
-        .width          = 2,
-        .parts          = sdp2430_partitions,
-        .nr_parts       = ARRAY_SIZE(sdp2430_partitions),
-};
-
-static struct resource sdp2430_flash_resource = {
-        .start          = SDP2430_CS0_BASE,
-        .end            = SDP2430_CS0_BASE + SZ_64M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device sdp2430_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev = {
-                .platform_data  = &sdp2430_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &sdp2430_flash_resource,
-};
-
-/* LCD */
-#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO        91
-#define SDP2430_LCD_PANEL_ENABLE_GPIO           154
-
-static const struct display_timing sdp2430_lcd_videomode = {
-        .pixelclock     = { 0, 5400000, 0 },
-
-        .hactive = { 0, 240, 0 },
-        .hfront_porch = { 0, 3, 0 },
-        .hback_porch = { 0, 39, 0 },
-        .hsync_len = { 0, 3, 0 },
-
-        .vactive = { 0, 320, 0 },
-        .vfront_porch = { 0, 2, 0 },
-        .vback_porch = { 0, 7, 0 },
-        .vsync_len = { 0, 1, 0 },
-
-        .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
-                DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static struct panel_dpi_platform_data sdp2430_lcd_pdata = {
-        .name                   = "lcd",
-        .source                 = "dpi.0",
-
-        .data_lines             = 16,
-
-        .display_timing         = &sdp2430_lcd_videomode,
-
-        .enable_gpio            = SDP2430_LCD_PANEL_ENABLE_GPIO,
-        .backlight_gpio         = SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
-};
-
-static struct platform_device sdp2430_lcd_device = {
-        .name                   = "panel-dpi",
-        .id                     = 0,
-        .dev.platform_data      = &sdp2430_lcd_pdata,
-};
-
-static struct omap_dss_board_info sdp2430_dss_data = {
-        .default_display_name = "lcd",
-};
-
-static struct platform_device *sdp2430_devices[] __initdata = {
-        &sdp2430_flash_device,
-        &sdp2430_lcd_device,
-};
-
-#if IS_ENABLED(CONFIG_SMC91X)
-
-static struct omap_smc91x_platform_data board_smc91x_data = {
-        .cs             = 5,
-        .gpio_irq       = 149,
-        .flags          = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
-                                IORESOURCE_IRQ_LOWLEVEL,
-
-};
-
-static void __init board_smc91x_init(void)
-{
-        omap_mux_init_gpio(149, OMAP_PIN_INPUT);
-        gpmc_smc91x_init(&board_smc91x_data);
-}
-
-#else
-
-static inline void board_smc91x_init(void)
-{
-}
-
-#endif
-
-static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-
-/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-static struct regulator_init_data sdp2430_vmmc1 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp2430_vmmc1_supplies),
-        .consumer_supplies      = &sdp2430_vmmc1_supplies[0],
-};
-
-static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
-};
-
-static struct twl4030_platform_data sdp2430_twldata = {
-        /* platform_data for children goes here */
-        .gpio           = &sdp2430_gpio_data,
-        .vmmc1          = &sdp2430_vmmc1,
-};
-
-static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("isp1301_omap", 0x2D),
-                .flags = I2C_CLIENT_WAKE,
-        },
-};
-
-static int __init omap2430_i2c_init(void)
-{
-        sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
-        omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
-                        ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-        omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
-                        &sdp2430_twldata);
-        return 0;
-}
-
-static struct omap2_hsmmc_info mmc[] __initdata = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .ext_clock      = 1,
-        },
-        {}      /* Terminator */
-};
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-
-static void __init omap_2430sdp_init(void)
-{
-        omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-
-        omap2430_i2c_init();
-
-        platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap_hsmmc_init(mmc);
-
-        omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
-        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
-        usb_musb_init(NULL);
-
-        board_smc91x_init();
-
-        /* Turn off secondary LCD backlight */
-        gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
-                         "Secondary LCD backlight");
-
-        omap_display_init(&sdp2430_dss_data);
-}
-
-MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
-        /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap243x_map_io,
-        .init_early     = omap2430_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = omap_2430sdp_init,
-        .init_late      = omap2430_init_late,
-        .init_time      = omap2_sync32k_timer_init,
-        .restart        = omap2xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 8d972ff18c56..8e3daa11602b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -78,6 +78,7 @@ MACHINE_END
 
 #ifdef CONFIG_ARCH_OMAP3
 static const char *omap3_boards_compat[] __initdata = {
+        "ti,omap3430",
         "ti,omap3",
         NULL,
 };
@@ -173,6 +174,8 @@ MACHINE_END
 
 #ifdef CONFIG_ARCH_OMAP4
 static const char *omap4_boards_compat[] __initdata = {
+        "ti,omap4460",
+        "ti,omap4430",
         "ti,omap4",
         NULL,
 };
@@ -193,6 +196,8 @@ MACHINE_END
 
 #ifdef CONFIG_SOC_OMAP5
 static const char *omap5_boards_compat[] __initdata = {
+        "ti,omap5432",
+        "ti,omap5430",
         "ti,omap5",
         NULL,
 };
@@ -213,6 +218,7 @@ MACHINE_END
 
 #ifdef CONFIG_SOC_AM43XX
 static const char *am43_boards_compat[] __initdata = {
+        "ti,am4372",
         "ti,am43",
         NULL,
 };
@@ -230,6 +236,7 @@ MACHINE_END
 
 #ifdef CONFIG_SOC_DRA7XX
 static const char *dra7xx_boards_compat[] __initdata = {
+        "ti,dra7xx",
         "ti,dra7",
         NULL,
 };
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
deleted file mode 100644
index f7808349a734..000000000000
--- a/arch/arm/mach-omap2/board-h4.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-h4.c
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Paul Mundt <paul.mundt@nokia.com>
- *
- * Modified from mach-omap/omap1/board-generic.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/delay.h>
-#include <linux/workqueue.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
-#include <linux/input.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/mfd/menelaus.h>
-#include <linux/omap-dma.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <video/omapdss.h>
-#include <video/omap-panel-data.h>
-
-#include "common.h"
-#include "mux.h"
-#include "control.h"
-#include "gpmc.h"
-#include "gpmc-smc91x.h"
-
-#define H4_FLASH_CS     0
-
-#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
-static const uint32_t board_matrix_keys[] = {
-        KEY(0, 0, KEY_LEFT),
-        KEY(1, 0, KEY_RIGHT),
-        KEY(2, 0, KEY_A),
-        KEY(3, 0, KEY_B),
-        KEY(4, 0, KEY_C),
-        KEY(0, 1, KEY_DOWN),
-        KEY(1, 1, KEY_UP),
-        KEY(2, 1, KEY_E),
-        KEY(3, 1, KEY_F),
-        KEY(4, 1, KEY_G),
-        KEY(0, 2, KEY_ENTER),
-        KEY(1, 2, KEY_I),
-        KEY(2, 2, KEY_J),
-        KEY(3, 2, KEY_K),
-        KEY(4, 2, KEY_3),
-        KEY(0, 3, KEY_M),
-        KEY(1, 3, KEY_N),
-        KEY(2, 3, KEY_O),
-        KEY(3, 3, KEY_P),
-        KEY(4, 3, KEY_Q),
-        KEY(0, 4, KEY_R),
-        KEY(1, 4, KEY_4),
-        KEY(2, 4, KEY_T),
-        KEY(3, 4, KEY_U),
-        KEY(4, 4, KEY_ENTER),
-        KEY(0, 5, KEY_V),
-        KEY(1, 5, KEY_W),
-        KEY(2, 5, KEY_L),
-        KEY(3, 5, KEY_S),
-        KEY(4, 5, KEY_ENTER),
-};
-
-static const struct matrix_keymap_data board_keymap_data = {
-        .keymap                 = board_matrix_keys,
-        .keymap_size            = ARRAY_SIZE(board_matrix_keys),
-};
-
-static unsigned int board_keypad_row_gpios[] = {
-        88, 89, 124, 11, 6, 96
-};
-
-static unsigned int board_keypad_col_gpios[] = {
-        90, 91, 100, 36, 12, 97, 98
-};
-
-static struct matrix_keypad_platform_data board_keypad_platform_data = {
-        .keymap_data    = &board_keymap_data,
-        .row_gpios      = board_keypad_row_gpios,
-        .num_row_gpios  = ARRAY_SIZE(board_keypad_row_gpios),
-        .col_gpios      = board_keypad_col_gpios,
-        .num_col_gpios  = ARRAY_SIZE(board_keypad_col_gpios),
-        .active_low     = 1,
-
-        .debounce_ms            = 20,
-        .col_scan_delay_us      = 5,
-};
-
-static struct platform_device board_keyboard = {
-        .name   = "matrix-keypad",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &board_keypad_platform_data,
-        },
-};
-static void __init board_mkp_init(void)
-{
-        omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
-        omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
-        omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
-        omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
-        if (omap_has_menelaus()) {
-                omap_mux_init_signal("sdrc_a14.gpio0",
-                        OMAP_PULL_ENA | OMAP_PULL_UP);
-                omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
-                omap_mux_init_signal("gpio_98", 0);
-                board_keypad_row_gpios[5] = 0;
-                board_keypad_col_gpios[2] = 15;
-                board_keypad_col_gpios[6] = 18;
-        } else {
-                omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
-                omap_mux_init_signal("gpio_100", 0);
-                omap_mux_init_signal("gpio_98", 0);
-        }
-        omap_mux_init_signal("gpio_90", 0);
-        omap_mux_init_signal("gpio_91", 0);
-        omap_mux_init_signal("gpio_36", 0);
-        omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
-        omap_mux_init_signal("gpio_97", 0);
-
-        platform_device_register(&board_keyboard);
-}
-#else
-static inline void board_mkp_init(void)
-{
-}
-#endif
-
-static struct mtd_partition h4_partitions[] = {
-        /* bootloader (U-Boot, etc) in first sector */
-        {
-              .name             = "bootloader",
-              .offset           = 0,
-              .size             = SZ_128K,
-              .mask_flags       = MTD_WRITEABLE, /* force read-only */
-        },
-        /* bootloader params in the next sector */
-        {
-              .name             = "params",
-              .offset           = MTDPART_OFS_APPEND,
-              .size             = SZ_128K,
-              .mask_flags       = 0,
-        },
-        /* kernel */
-        {
-              .name             = "kernel",
-              .offset           = MTDPART_OFS_APPEND,
-              .size             = SZ_2M,
-              .mask_flags       = 0
-        },
-        /* file system */
-        {
-              .name             = "filesystem",
-              .offset           = MTDPART_OFS_APPEND,
-              .size             = MTDPART_SIZ_FULL,
-              .mask_flags       = 0
-        }
-};
-
-static struct physmap_flash_data h4_flash_data = {
-        .width          = 2,
-        .parts          = h4_partitions,
-        .nr_parts       = ARRAY_SIZE(h4_partitions),
-};
-
-static struct resource h4_flash_resource = {
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device h4_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &h4_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &h4_flash_resource,
-};
-
-static const struct display_timing cm_t35_lcd_videomode = {
-        .pixelclock     = { 0, 6250000, 0 },
-
-        .hactive = { 0, 240, 0 },
-        .hfront_porch = { 0, 15, 0 },
-        .hback_porch = { 0, 60, 0 },
-        .hsync_len = { 0, 15, 0 },
-
-        .vactive = { 0, 320, 0 },
-        .vfront_porch = { 0, 1, 0 },
-        .vback_porch = { 0, 1, 0 },
-        .vsync_len = { 0, 1, 0 },
-
-        .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
-                DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
-        .name                   = "lcd",
-        .source                 = "dpi.0",
-
-        .data_lines             = 16,
-
-        .display_timing         = &cm_t35_lcd_videomode,
-
-        .enable_gpio            = -1,
-        .backlight_gpio         = -1,
-};
-
-static struct platform_device cm_t35_lcd_device = {
-        .name                   = "panel-dpi",
-        .id                     = 0,
-        .dev.platform_data      = &cm_t35_lcd_pdata,
-};
-
-static struct platform_device *h4_devices[] __initdata = {
-        &h4_flash_device,
-        &cm_t35_lcd_device,
-};
-
-static struct omap_dss_board_info h4_dss_data = {
-        .default_display_name = "lcd",
-};
-
-/* 2420 Sysboot setup (2430 is different) */
-static u32 get_sysboot_value(void)
-{
-        return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
-                (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
-                 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
-                 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
-}
-
-/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
- *
- * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
- *  correctly.  The macro needs to look at production_id not just hawkeye.
- */
-static u32 is_gpmc_muxed(void)
-{
-        u32 mux;
-        mux = get_sysboot_value();
-        if ((mux & 0xF) == 0xd)
-                return 1;       /* NAND config (could be either) */
-        if (mux & 0x2)          /* if mux'ed */
-                return 1;
-        else
-                return 0;
-}
-
-#if IS_ENABLED(CONFIG_SMC91X)
-
-static struct omap_smc91x_platform_data board_smc91x_data = {
-        .cs             = 1,
-        .gpio_irq       = 92,
-        .flags          = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
-};
-
-static void __init board_smc91x_init(void)
-{
-        if (is_gpmc_muxed())
-                board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
-
-        omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
-        gpmc_smc91x_init(&board_smc91x_data);
-}
-
-#else
-
-static inline void board_smc91x_init(void)
-{
-}
-
-#endif
-
-static void __init h4_init_flash(void)
-{
-        unsigned long base;
-
-        if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
-                printk("Can't request GPMC CS for flash\n");
-                return;
-        }
-        h4_flash_resource.start = base;
-        h4_flash_resource.end   = base + SZ_64M - 1;
-}
-
-static struct at24_platform_data m24c01 = {
-        .byte_len       = SZ_1K / 8,
-        .page_size      = 16,
-};
-
-static struct i2c_board_info __initdata h4_i2c_board_info[] = {
-        {
-                I2C_BOARD_INFO("isp1301_omap", 0x2d),
-        },
-        {       /* EEPROM on mainboard */
-                I2C_BOARD_INFO("24c01", 0x52),
-                .platform_data  = &m24c01,
-        },
-        {       /* EEPROM on cpu card */
-                I2C_BOARD_INFO("24c01", 0x57),
-                .platform_data  = &m24c01,
-        },
-};
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-
-static void __init omap_h4_init(void)
-{
-        omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
-
-        /*
-         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
-         * if not needed.
-         */
-
-        board_mkp_init();
-        h4_i2c_board_info[0].irq = gpio_to_irq(125);
-        i2c_register_board_info(1, h4_i2c_board_info,
-                        ARRAY_SIZE(h4_i2c_board_info));
-
-        platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        h4_init_flash();
-        board_smc91x_init();
-
-        omap_display_init(&h4_dss_data);
-}
-
-MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
-        /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap242x_map_io,
-        .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = omap_h4_init,
-        .init_late      = omap2420_init_late,
-        .init_time      = omap2_sync32k_timer_init,
-        .restart        = omap2xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 827d15009a86..aead77a4bc6d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -21,7 +21,6 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
-#include <linux/platform_data/i2c-cbus-gpio.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 #include <linux/mfd/menelaus.h>
@@ -32,8 +31,7 @@
 
 #include "common.h"
 #include "mmc.h"
-
-#include "mux.h"
+#include "soc.h"
 #include "gpmc-onenand.h"
 
 #define TUSB6010_ASYNC_CS       1
@@ -42,44 +40,30 @@
 #define TUSB6010_GPIO_ENABLE    0
 #define TUSB6010_DMACHAN        0x3f
 
-#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE)
-static struct i2c_cbus_platform_data n8x0_cbus_data = {
-        .clk_gpio = 66,
-        .dat_gpio = 65,
-        .sel_gpio = 64,
-};
+#define NOKIA_N810_WIMAX        (1 << 2)
+#define NOKIA_N810              (1 << 1)
+#define NOKIA_N800              (1 << 0)
 
-static struct platform_device n8x0_cbus_device = {
-        .name   = "i2c-cbus-gpio",
-        .id     = 3,
-        .dev    = {
-                .platform_data = &n8x0_cbus_data,
-        },
-};
+static u32 board_caps;
 
-static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = {
-        {
-                I2C_BOARD_INFO("retu-mfd", 0x01),
-        },
-};
+#define board_is_n800()         (board_caps & NOKIA_N800)
+#define board_is_n810()         (board_caps & NOKIA_N810)
+#define board_is_n810_wimax()   (board_caps & NOKIA_N810_WIMAX)
 
-static void __init n8x0_cbus_init(void)
+static void board_check_revision(void)
 {
-        const int retu_irq_gpio = 108;
+        if (of_have_populated_dt()) {
+                if (of_machine_is_compatible("nokia,n800"))
+                        board_caps = NOKIA_N800;
+                else if (of_machine_is_compatible("nokia,n810"))
+                        board_caps = NOKIA_N810;
+                else if (of_machine_is_compatible("nokia,n810-wimax"))
+                        board_caps = NOKIA_N810_WIMAX;
+        }
 
-        if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
-                return;
-        irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
-        n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio);
-        i2c_register_board_info(3, n8x0_i2c_board_info_3,
-                                ARRAY_SIZE(n8x0_i2c_board_info_3));
-        platform_device_register(&n8x0_cbus_device);
-}
-#else /* CONFIG_I2C_CBUS_GPIO */
-static void __init n8x0_cbus_init(void)
-{
+        if (!board_caps)
+                pr_err("Unknown board\n");
 }
-#endif /* CONFIG_I2C_CBUS_GPIO */
 
 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 /*
@@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
         },
 };
 
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
-
-static struct mtd_partition onenand_partitions[] = {
-        {
-                .name           = "bootloader",
-                .offset         = 0,
-                .size           = 0x20000,
-                .mask_flags     = MTD_WRITEABLE,        /* Force read-only */
-        },
-        {
-                .name           = "config",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 0x60000,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 0x200000,
-        },
-        {
-                .name           = "initfs",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 0x400000,
-        },
-        {
-                .name           = "rootfs",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct omap_onenand_platform_data board_onenand_data[] = {
-        {
-                .cs             = 0,
-                .gpio_irq       = 26,
-                .parts          = onenand_partitions,
-                .nr_parts       = ARRAY_SIZE(onenand_partitions),
-                .flags          = ONENAND_SYNC_READ,
-        }
-};
-#endif
-
 #if defined(CONFIG_MENELAUS) &&                                         \
         (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
 
@@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev,
 static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
                               int vdd)
 {
-        if (machine_is_nokia_n800() || slot == 0)
+        if (board_is_n800() || slot == 0)
                 return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
 
         n810_set_power_emmc(dev, power_on);
@@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
 {
         int bit, *openp, index;
 
-        if (machine_is_nokia_n800()) {
+        if (board_is_n800()) {
                 bit = 1 << 1;
                 openp = &slot2_cover_open;
                 index = 1;
@@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev)
         if (r < 0)
                 return r;
 
-        if (machine_is_nokia_n800())
+        if (board_is_n800())
                 vs2sel = 0;
         else
                 vs2sel = 2;
@@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev)
         if (r < 0)
                 return r;
 
-        if (machine_is_nokia_n800()) {
+        if (board_is_n800()) {
                 bit = 1 << 1;
                 openp = &slot2_cover_open;
         } else {
@@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev)
 {
         int vs2sel;
 
-        if (machine_is_nokia_n800())
+        if (board_is_n800())
                 vs2sel = 0;
         else
                 vs2sel = 2;
@@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
 
         gpio_free(N8X0_SLOT_SWITCH_GPIO);
 
-        if (machine_is_nokia_n810()) {
+        if (board_is_n810()) {
                 gpio_free(N810_EMMC_VSD_GPIO);
                 gpio_free(N810_EMMC_VIO_GPIO);
         }
@@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
  * MMC controller2 is not in use.
  */
 static struct omap_mmc_platform_data mmc1_data = {
-        .nr_slots                       = 2,
+        .nr_slots                       = 0,
         .switch_slot                    = n8x0_mmc_switch_slot,
         .init                           = n8x0_mmc_late_init,
         .cleanup                        = n8x0_mmc_cleanup,
@@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void)
 {
         int err;
 
-        if (machine_is_nokia_n810()) {
+        if (board_is_n810()) {
                 mmc1_data.slots[0].name = "external";
 
                 /*
@@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void)
         if (err)
                 return;
 
-        if (machine_is_nokia_n810()) {
+        if (board_is_n810()) {
                 err = gpio_request_array(n810_emmc_gpios,
                                          ARRAY_SIZE(n810_emmc_gpios));
                 if (err) {
@@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void)
                 }
         }
 
+        mmc1_data.nr_slots = 2;
         mmc_data[0] = &mmc1_data;
-        omap242x_init_mmc(mmc_data);
 }
 #else
-
+static struct omap_mmc_platform_data mmc1_data;
 void __init n8x0_mmc_init(void)
 {
 }
@@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
         },
 };
 
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* I2S codec port pins for McBSP block */
-        OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
-        OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-static struct omap_device_pad serial2_pads[] __initdata = {
-        {
-                .name   = "uart3_rx_irrx.uart3_rx_irrx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_MUX_MODE0,
-                .idle   = OMAP_MUX_MODE3        /* Mux as GPIO for idle */
-        },
-};
-
-static inline void board_serial_init(void)
+static int __init n8x0_late_initcall(void)
 {
-        struct omap_board_data bdata;
-
-        bdata.flags = 0;
-        bdata.pads = NULL;
-        bdata.pads_cnt = 0;
-
-        bdata.id = 0;
-        omap_serial_init_port(&bdata, NULL);
-
-        bdata.id = 1;
-        omap_serial_init_port(&bdata, NULL);
-
-        bdata.id = 2;
-        bdata.pads = serial2_pads;
-        bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
-        omap_serial_init_port(&bdata, NULL);
-}
+        if (!board_caps)
+                return -ENODEV;
 
-#else
+        n8x0_mmc_init();
+        n8x0_usb_init();
 
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
+        return 0;
 }
+omap_late_initcall(n8x0_late_initcall);
 
-#endif
-
-static void __init n8x0_init_machine(void)
+/*
+ * Legacy init pdata init for n8x0. Note that we want to follow the
+ * I2C bus numbering starting at 0 for device tree like other omaps.
+ */
+void * __init n8x0_legacy_init(void)
 {
-        omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
-        /* FIXME: add n810 spi devices */
+        board_check_revision();
         spi_register_board_info(n800_spi_board_info,
                                 ARRAY_SIZE(n800_spi_board_info));
-        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
-                              ARRAY_SIZE(n8x0_i2c_board_info_1));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        if (machine_is_nokia_n810())
-                i2c_register_board_info(2, n810_i2c_board_info_2,
+        i2c_register_board_info(0, n8x0_i2c_board_info_1,
+                                ARRAY_SIZE(n8x0_i2c_board_info_1));
+        if (board_is_n810())
+                i2c_register_board_info(1, n810_i2c_board_info_2,
                                         ARRAY_SIZE(n810_i2c_board_info_2));
-        board_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        gpmc_onenand_init(board_onenand_data);
-        n8x0_mmc_init();
-        n8x0_usb_init();
-        n8x0_cbus_init();
-}
 
-MACHINE_START(NOKIA_N800, "Nokia N800")
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap242x_map_io,
-        .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = n8x0_init_machine,
-        .init_late      = omap2420_init_late,
-        .init_time      = omap2_sync32k_timer_init,
-        .restart        = omap2xxx_restart,
-MACHINE_END
-
-MACHINE_START(NOKIA_N810, "Nokia N810")
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap242x_map_io,
-        .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = n8x0_init_machine,
-        .init_late      = omap2420_init_late,
-        .init_time      = omap2_sync32k_timer_init,
-        .restart        = omap2xxx_restart,
-MACHINE_END
-
-MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap242x_map_io,
-        .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
-        .handle_irq     = omap2_intc_handle_irq,
-        .init_machine   = n8x0_init_machine,
-        .init_late      = omap2420_init_late,
-        .init_time      = omap2_sync32k_timer_init,
-        .restart        = omap2xxx_restart,
-MACHINE_END
+        return &mmc1_data;
+}
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index f093af17f5e6..8760bbe3baab 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -760,7 +760,14 @@ static struct regulator_init_data rx51_vintdig = {
         },
 };
 
+static const char * const si4713_supply_names[] = {
+        "vio",
+        "vdd",
+};
+
 static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
+        .supplies       = ARRAY_SIZE(si4713_supply_names),
+        .supply_names   = si4713_supply_names,
         .gpio_reset     = RX51_FMTX_RESET_GPIO,
 };
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30ee812f..000000000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT          0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT          1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-        "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-        "virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-               AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-               AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-               AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-               0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-        "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_core_ck,
-        },
-        .dpll_data      = &dpll_core_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-        "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-        .recalc_rate    = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_core_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-                   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-        .hw = {
-                .clk    = &dpll_mpu_ck,
-        },
-        .dpll_data      = &dpll_mpu_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-                   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-        .hw = {
-                .clk    = &dpll_ddr_ck,
-        },
-        .dpll_data      = &dpll_ddr_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-                   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-                        0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-        .hw = {
-                .clk    = &dpll_disp_ck,
-        },
-        .dpll_data      = &dpll_disp_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-                   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
-        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
-        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-        .flags          = DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_per_ck,
-        },
-        .dpll_data      = &dpll_per_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-                   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-                        &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-                        &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-                        &dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                        1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-                        8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-        "dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-        "dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk rng_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
-DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-        "clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-        .hw     = {
-                .clk    = &clkdiv32k_ick,
-        },
-        .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL_SHIFT,
-        .clkdm_name     = "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-                0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-                AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = &tclkin_ck, .rates = div_1_2_rates },
-        { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-        "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-        "clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-        .hw     = {
-                .clk    = &timer1_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer1_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-        { .parent = &tclkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-        "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-        .hw     = {
-                .clk    = &timer2_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-        .hw     = {
-                .clk    = &timer3_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-        .hw     = {
-                .clk    = &timer4_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-        .hw     = {
-                .clk    = &timer5_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-        .hw     = {
-                .clk    = &timer6_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-        .hw     = {
-                .clk    = &timer7_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-                        "dpll_core_m5_ck",
-                        &dpll_core_m5_ck,
-                        0x0,
-                        1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-        "dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-        .hw     = {
-                .clk    = &cpsw_cpts_rft_clk,
-        },
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .clksel         = cpsw_cpts_rft_clkmux_sel,
-        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-        "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-        .hw     = {
-                .clk    = &gpio0_dbclk_mux_ck,
-        },
-        .clkdm_name     = "l4_wkup_clkdm",
-        .clksel         = gpio0_dbclk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-                AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO1_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO2_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO3_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-        "l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-        { .parent = &l3_gclk, .rates = div_1_0_rates },
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-        .hw     = {
-                .clk    = &pruss_ocp_gclk,
-        },
-        .clkdm_name     = "pruss_ocp_clkdm",
-        .clksel         = pruss_ocp_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-        "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-        .hw     = {
-                .clk    = &lcd_gclk,
-        },
-        .clkdm_name     = "lcdc_clkdm",
-        .clksel         = lcd_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-                        gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-        "dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-        { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-        .hw     = {
-                .clk    = &gfx_fclk_clksel_ck,
-        },
-        .clksel         = gfx_clksel_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
-        .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-        { .div = 1, .val = 0, },
-        { .div = 2, .val = 1, },
-        { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-                         &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-                         AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-                         0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-        "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-        "lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-        { .parent = &clk_32768_ck, .rates = div_1_0_rates },
-        { .parent = &l3_gclk, .rates = div_1_1_rates },
-        { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-        { .parent = &lcd_gclk, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-        .hw     = {
-                .clk    = &sysclkout_pre_ck,
-        },
-        .clksel         = sysclkout_pre_sel,
-        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
-        .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-        { .div = 1, .val = 0, },
-        { .div = 2, .val = 1, },
-        { .div = 3, .val = 2, },
-        { .div = 4, .val = 3, },
-        { .div = 5, .val = 4, },
-        { .div = 6, .val = 5, },
-        { .div = 7, .val = 6, },
-        { .div = 8, .val = 7, },
-        { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-                         0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-                         AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-                AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-        "clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-        .hw     = {
-                .clk    = &wdt1_fck,
-        },
-        .clkdm_name     = "l4_wkup_clkdm",
-        .clksel         = wdt_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-        "dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS0_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS1_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS2_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-        "dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-               AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-               AM33XX_TRC_PMD_CLKSEL_SHIFT,
-               AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-                   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-                   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-                   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-                   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck),
-        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck),
-        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck),
-        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck),
-        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck),
-        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck),
-        CLK(NULL,       "tclkin_ck",            &tclkin_ck),
-        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck),
-        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck),
-        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck),
-        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck),
-        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck),
-        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck),
-        CLK("cpu0",     NULL,                   &dpll_mpu_ck),
-        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck),
-        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck),
-        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck),
-        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck),
-        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck),
-        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck),
-        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck),
-        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck),
-        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck),
-        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck),
-        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck),
-        CLK(NULL,       "cefuse_fck",           &cefuse_fck),
-        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck),
-        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick),
-        CLK(NULL,       "dcan0_fck",            &dcan0_fck),
-        CLK("481cc000.d_can",   NULL,           &dcan0_fck),
-        CLK(NULL,       "dcan1_fck",            &dcan1_fck),
-        CLK("481d0000.d_can",   NULL,           &dcan1_fck),
-        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
-        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
-        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
-        CLK(NULL,       "mmu_fck",              &mmu_fck),
-        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
-        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
-        CLK(NULL,       "sha0_fck",             &sha0_fck),
-        CLK(NULL,       "aes0_fck",             &aes0_fck),
-        CLK(NULL,       "rng_fck",              &rng_fck),
-        CLK(NULL,       "timer1_fck",           &timer1_fck),
-        CLK(NULL,       "timer2_fck",           &timer2_fck),
-        CLK(NULL,       "timer3_fck",           &timer3_fck),
-        CLK(NULL,       "timer4_fck",           &timer4_fck),
-        CLK(NULL,       "timer5_fck",           &timer5_fck),
-        CLK(NULL,       "timer6_fck",           &timer6_fck),
-        CLK(NULL,       "timer7_fck",           &timer7_fck),
-        CLK(NULL,       "usbotg_fck",           &usbotg_fck),
-        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck),
-        CLK(NULL,       "wdt1_fck",             &wdt1_fck),
-        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk),
-        CLK(NULL,       "l3_gclk",              &l3_gclk),
-        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
-        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk),
-        CLK(NULL,       "l3s_gclk",             &l3s_gclk),
-        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk),
-        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk),
-        CLK(NULL,       "clk_24mhz",            &clk_24mhz),
-        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck),
-        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk),
-        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk),
-        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck),
-        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk),
-        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk),
-        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk),
-        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk),
-        CLK(NULL,       "lcd_gclk",             &lcd_gclk),
-        CLK(NULL,       "mmc_clk",              &mmc_clk),
-        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck),
-        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck),
-        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck),
-        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
-        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
-        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
-        CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
-        CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
-        CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
-        CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
-        CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
-        CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
-        CLK(NULL,       "clkout2_ck",           &clkout2_ck),
-        CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
-        CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
-        CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-        "dpll_ddr_m2_ck",
-        "dpll_mpu_m2_ck",
-        "l3_gclk",
-        "l4hs_gclk",
-        "l4fw_gclk",
-        "l4ls_gclk",
-        "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-        if (soc_is_am33xx())
-                cpu_mask = RATE_IN_AM33XX;
-
-        omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-        omap2_clk_disable_autoidle_all();
-
-        omap2_clk_enable_init_clocks(enable_init_clks,
-                                     ARRAY_SIZE(enable_init_clks));
-
-        /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-         *    physically present, in such a case HWMOD enabling of
-         *    clock would be failure with default parent. And timer
-         *    probe thinks clock is already enabled, this leads to
-         *    crash upon accessing timer 3 & 6 registers in probe.
-         *    Fix by setting parent of both these timers to master
-         *    oscillator clock.
-         */
-
-        clk_set_parent(&timer3_fck, &sys_clkin_ck);
-        clk_set_parent(&timer6_fck, &sys_clkin_ck);
-        /*
-         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-         * the design/spec, so as a result, for example, timer which supposed
-         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-         * not expected by any use-case, so change WDT1 clock source to PRCM
-         * 32KHz clock.
-         */
-        clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index ec0dc0b1755e..000000000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1735 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Mike Turquette (mturquette@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ                          98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ                          960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-                OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-                OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-        "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-        "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-        "virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-               OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-               OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-               NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-               OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
-        .clk_ref        = &abe_dpll_refclk_mux_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .m4xen_mask     = OMAP4430_DPLL_REGM4XEN_MASK,
-        .lpmode_mask    = OMAP4430_DPLL_LPMODE_EN_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-        "abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap4_dpll_regm4xen_recalc,
-        .round_rate     = &omap4_dpll_regm4xen_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-        .hw = {
-                .clk = &dpll_abe_ck,
-        },
-        .dpll_data      = &dpll_abe_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-        "dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-        .recalc_rate    = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_abe_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-        .set_rate       = &omap2_clksel_set_rate,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-                        0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-                   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-                   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-                   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-                   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-               OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-               0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-        "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-        .hw = {
-                .clk = &dpll_core_ck,
-        },
-        .dpll_data      = &dpll_core_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-        "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_core_x2_ck,
-        },
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_CORE,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-                        2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-                   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-                   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-                   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-                   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-                   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-                        0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-                   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-        "dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-                         OMAP4430_CM_DIV_M3_DPLL_CORE,
-                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-                         OMAP4430_CM_DIV_M3_DPLL_CORE,
-                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
-        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-        "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-        .hw = {
-                .clk = &dpll_iva_ck,
-        },
-        .dpll_data      = &dpll_iva_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-        "dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_iva_x2_ck,
-        },
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-        "sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-        .hw = {
-                .clk = &dpll_mpu_ck,
-        },
-        .dpll_data      = &dpll_mpu_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_MPU,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-                        &dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
-        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-        "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-        .hw = {
-                .clk = &dpll_per_ck,
-        },
-        .dpll_data      = &dpll_per_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-        "dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_per_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-        "dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-                         OMAP4430_CM_DIV_M3_DPLL_PER,
-                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-                         OMAP4430_CM_DIV_M3_DPLL_PER,
-                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-                        &dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
-        .clk_bypass     = &usb_hs_clk_div_ck,
-        .flags          = DPLL_J_TYPE,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
-        .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
-        .max_multiplier = 4095,
-        .max_divider    = 256,
-        .min_divider    = 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-        "sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-        .hw = {
-                .clk = &dpll_usb_ck,
-        },
-        .dpll_data      = &dpll_usb_dd,
-        .clkdm_name     = "l3_init_clkdm",
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-        "dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-        .hw = {
-                .clk = &dpll_usb_clkdcoldo_ck,
-        },
-        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-                  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_USB,
-                          OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-        "div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-                        1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-        { .div = 4, .val = 0 },
-        { .div = 8, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-                         NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 4, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-                         NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 4, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-                         NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-        { .div = 1, .val = 0 },
-        { .div = 8, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-                         0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-                         OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-                         0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-                   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-                   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-                        0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 1, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-                         OMAP4430_CM1_ABE_AESS_CLKCTRL,
-                         OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-                         OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-                         0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-                        0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-                   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-                   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-        "sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-                  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-        { .div = 8, .val = 0 },
-        { .div = 16, .val = 1 },
-        { .div = 32, .val = 2 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                         0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                         OMAP4430_CLKSEL_24_25_SHIFT,
-                         OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-                         NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-                0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-        "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-        "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-                    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-                    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
-                CLK_SET_RATE_PARENT,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-                   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-                   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-        "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-                    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-                    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-                   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-                   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-        "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-                    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-        "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-        "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-        "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-        "func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-        "mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-                    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
-        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-        "func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-                    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-                    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-                &pad_slimbus_core_clks_ck, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-        "syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-        "func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-        .hw = {
-                .clk = &usb_host_fs_fck,
-        },
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-                  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-        "init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-               OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-        "init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-               OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-                &dpll_usb_m2_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-                &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-                &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-                &dpll_usb_m2_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-        "utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-               OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-                OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-                OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-        { .div = 14, .val = 0 },
-        { .div = 18, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-                         OMAP4430_CM_WKUP_USIM_CLKCTRL,
-                         OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-                         0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-                0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-        "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-               OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-               OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-               OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-                   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-                   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-                   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-        "pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-        .init           = &omap2_init_clk_clkdm,
-        .enable         = &omap2_clkops_enable_clkdm,
-        .disable        = &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-        .hw = {
-                .clk = &trace_clk_div_ck,
-        },
-        .clkdm_name     = "emu_sys_clkdm",
-        .clksel         = trace_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-                  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-        "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-        "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-        "auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-        CLK(NULL,       "div_ts_ck",                    &div_ts_ck),
-        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck),
-        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck),
-        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck),
-        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck),
-        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck),
-        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk),
-        CLK(NULL,       "slimbus_clk",                  &slimbus_clk),
-        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck),
-        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck),
-        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck),
-        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck),
-        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck),
-        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck),
-        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck),
-        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck),
-        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck),
-        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck),
-        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck),
-        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck),
-        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck),
-        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck),
-        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck),
-        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck),
-        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck),
-        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck),
-        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck),
-        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk),
-        CLK(NULL,       "abe_clk",                      &abe_clk),
-        CLK(NULL,       "aess_fclk",                    &aess_fclk),
-        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck),
-        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck),
-        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck),
-        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck),
-        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck),
-        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck),
-        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck),
-        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck),
-        CLK(NULL,       "div_core_ck",                  &div_core_ck),
-        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk),
-        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk),
-        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck),
-        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck),
-        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck),
-        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck),
-        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck),
-        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck),
-        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck),
-        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck),
-        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck),
-        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck),
-        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck),
-        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck),
-        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck),
-        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck),
-        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck),
-        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck),
-        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck),
-        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck),
-        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck),
-        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck),
-        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck),
-        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck),
-        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck),
-        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck),
-        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck),
-        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck),
-        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk),
-        CLK(NULL,       "func_24m_clk",                 &func_24m_clk),
-        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk),
-        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk),
-        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk),
-        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk),
-        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk),
-        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk),
-        CLK(NULL,       "l3_div_ck",                    &l3_div_ck),
-        CLK(NULL,       "l4_div_ck",                    &l4_div_ck),
-        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck),
-        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck),
-        CLK("smp_twd",  NULL,                           &mpu_periphclk),
-        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk),
-        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk),
-        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck),
-        CLK(NULL,       "aes1_fck",                     &aes1_fck),
-        CLK(NULL,       "aes2_fck",                     &aes2_fck),
-        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck),
-        CLK(NULL,       "func_dmic_abe_gfclk",          &func_dmic_abe_gfclk),
-        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk),
-        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk),
-        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk),
-        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk),
-        CLK(NULL,       "dss_fck",                      &dss_fck),
-        CLK("omapdss_dss",      "ick",                  &dss_fck),
-        CLK(NULL,       "fdif_fck",                     &fdif_fck),
-        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk),
-        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk),
-        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk),
-        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk),
-        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk),
-        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk),
-        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux),
-        CLK(NULL,       "hsi_fck",                      &hsi_fck),
-        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk),
-        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck),
-        CLK(NULL,       "func_mcasp_abe_gfclk",         &func_mcasp_abe_gfclk),
-        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp1_gfclk",            &func_mcbsp1_gfclk),
-        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp2_gfclk",            &func_mcbsp2_gfclk),
-        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp3_gfclk",            &func_mcbsp3_gfclk),
-        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck),
-        CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
-        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
-        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
-        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
-        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
-        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
-        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2),
-        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk),
-        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1),
-        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0),
-        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk),
-        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck),
-        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck),
-        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck),
-        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux),
-        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux),
-        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux),
-        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux),
-        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux),
-        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux),
-        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux),
-        CLK(NULL,       "timer6_sync_mux",              &timer6_sync_mux),
-        CLK(NULL,       "timer7_sync_mux",              &timer7_sync_mux),
-        CLK(NULL,       "timer8_sync_mux",              &timer8_sync_mux),
-        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck),
-        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck),
-        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk),
-        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk),
-        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk),
-        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk),
-        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck),
-        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck),
-        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk),
-        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk),
-        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick),
-        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick),
-        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k),
-        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk),
-        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk),
-        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick),
-        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick),
-        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick),
-        CLK(NULL,       "usim_ck",                      &usim_ck),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk),
-        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck),
-        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck),
-        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck),
-        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck),
-        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck),
-        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck),
-        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck),
-        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck),
-        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck),
-        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck),
-        CLK("50000000.gpmc",    "fck",                  &dummy_ck),
-        CLK("omap_i2c.1",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.2",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.3",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.4",       "ick",                  &dummy_ck),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck),
-        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck),
-        CLK(NULL,       "uart1_ick",                    &dummy_ck),
-        CLK(NULL,       "uart2_ick",                    &dummy_ck),
-        CLK(NULL,       "uart3_ick",                    &dummy_ck),
-        CLK(NULL,       "uart4_ick",                    &dummy_ck),
-        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck),
-        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck),
-        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck),
-        CLK("omap_wdt", "ick",                          &dummy_ck),
-        CLK(NULL,       "timer_32k_ck", &sys_32k_ck),
-        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-        int rc;
-
-        if (cpu_is_omap443x()) {
-                cpu_mask = RATE_IN_4430;
-                omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-        } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-                cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-                omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-                if (cpu_is_omap447x())
-                        pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-        } else {
-                return 0;
-        }
-
-        omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-        omap2_clk_disable_autoidle_all();
-
-        /*
-         * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
-         * when its in bypass. So always lock USB before ABE DPLL.
-         */
-        /*
-         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-         * domain can transition to retention state when not in use.
-         */
-        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-        /*
-         * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-         * state when turning the ABE clock domain. Workaround this by
-         * locking the ABE DPLL on boot.
-         * Lock the ABE DPLL in any case to avoid issues with audio.
-         */
-        rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-        if (!rc)
-                rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6fdf046..7ee26108ac0d 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
 {
         u32 v;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= ~clk->clksel_mask;
         v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 
-        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+        v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
 }
 
 /**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
         if (!clk->clksel || !clk->clksel_mask)
                 return 0;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= clk->clksel_mask;
         v >>= __ffs(clk->clksel_mask);
 
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
         WARN((!clk->clksel || !clk->clksel_mask),
              "clock: %s: attempt to call on a non-clksel clock", clk_name);
 
-        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
         r >>= __ffs(clk->clksel_mask);
 
         for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230f8948..47f9562ca7aa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
         if (!dd)
                 return -EINVAL;
 
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
                 return 0;
 
         /* Return bypass rate if DPLL is bypassed */
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
                         return __clk_get_rate(dd->clk_bypass);
         }
 
-        v = __raw_readl(dd->mult_div1_reg);
+        v = omap2_clk_readl(clk, dd->mult_div1_reg);
         dpll_mult = v & dd->mult_mask;
         dpll_mult >>= __ffs(dd->mult_mask);
         dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03ce3e2..333f0a666171 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
 /* XXX */
 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
 {
-        u32 v, r;
+        u32 v;
+        void __iomem *r;
 
-        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+        r = (__force void __iomem *)
+                ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-        v = __raw_readl((__force void __iomem *)r);
+        v = omap2_clk_readl(clk, r);
         v |= (1 << clk->enable_bit);
-        __raw_writel(v, (__force void __iomem *)r);
+        omap2_clk_writel(v, clk, r);
 }
 
 /* XXX */
 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
 {
-        u32 v, r;
+        u32 v;
+        void __iomem *r;
 
-        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+        r = (__force void __iomem *)
+                ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-        v = __raw_readl((__force void __iomem *)r);
+        v = omap2_clk_readl(clk, r);
         v &= ~(1 << clk->enable_bit);
-        __raw_writel(v, (__force void __iomem *)r);
+        omap2_clk_writel(v, clk, r);
 }
 
 /* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c7c5d31e9082..591581a66532 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
 #include <linux/clk-private.h>
 #include <asm/cpu.h>
 
-
 #include <trace/events/power.h>
 
 #include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
 static bool clkdm_control = true;
 
 static LIST_HEAD(clk_hw_omap_clocks);
+void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+        if (clk->flags & MEMMAP_ADDRESSING) {
+                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+                writel_relaxed(val, clk_memmaps[r->index] + r->offset);
+        } else {
+                writel_relaxed(val, reg);
+        }
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+        u32 val;
+
+        if (clk->flags & MEMMAP_ADDRESSING) {
+                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+                val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+        } else {
+                val = readl_relaxed(reg);
+        }
+
+        return val;
+}
 
 /*
  * Used for clocks that have the same value as the parent clock,
@@ -87,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 
 /**
  * _wait_idlest_generic - wait for a module to leave the idle state
+ * @clk: module clock to wait for (needed for register offsets)
  * @reg: virtual address of module IDLEST register
  * @mask: value to mask against to determine if the module is active
  * @idlest: idle state indicator (0 or 1) for the clock
@@ -98,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
  * elapsed.  XXX Deprecated - should be moved into drivers for the
  * individual IP block that the IDLEST register exists in.
  */
-static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
-                                const char *name)
+static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
+                                u32 mask, u8 idlest, const char *name)
 {
         int i = 0, ena = 0;
 
         ena = (idlest) ? 0 : mask;
 
-        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+        omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
                           MAX_MODULE_ENABLE_WAIT, i);
 
         if (i < MAX_MODULE_ENABLE_WAIT)
@@ -138,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
         /* Not all modules have multiple clocks that their IDLEST depends on */
         if (clk->ops->find_companion) {
                 clk->ops->find_companion(clk, &companion_reg, &other_bit);
-                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
                         return;
         }
 
@@ -146,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
         r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
         if (r) {
                 /* IDLEST register not in the CM module */
-                _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
-                                     __clk_get_name(clk->hw.clk));
+                _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
+                                     idlest_val, __clk_get_name(clk->hw.clk));
         } else {
                 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
         };
@@ -309,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
         }
 
         /* FIXME should not have INVERT_ENABLE bit here */
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
                 v &= ~(1 << clk->enable_bit);
         else
                 v |= (1 << clk->enable_bit);
-        __raw_writel(v, clk->enable_reg);
-        v = __raw_readl(clk->enable_reg); /* OCP barrier */
+        omap2_clk_writel(v, clk, clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
 
         if (clk->ops && clk->ops->find_idlest)
                 _omap2_module_wait_ready(clk);
@@ -353,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
                 return;
         }
 
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
                 v |= (1 << clk->enable_bit);
         else
                 v &= ~(1 << clk->enable_bit);
-        __raw_writel(v, clk->enable_reg);
+        omap2_clk_writel(v, clk, clk->enable_reg);
         /* No OCP barrier needed here since it is a disable operation */
 
         if (clkdm_control && clk->clkdm)
@@ -454,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         u32 v;
 
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
 
         if (clk->flags & INVERT_ENABLE)
                 v ^= BIT(clk->enable_bit);
@@ -520,6 +545,9 @@ int omap2_clk_enable_autoidle_all(void)
         list_for_each_entry(c, &clk_hw_omap_clocks, node)
                 if (c->ops && c->ops->allow_idle)
                         c->ops->allow_idle(c);
+
+        of_ti_clk_allow_autoidle_all();
+
         return 0;
 }
 
@@ -539,6 +567,9 @@ int omap2_clk_disable_autoidle_all(void)
         list_for_each_entry(c, &clk_hw_omap_clocks, node)
                 if (c->ops && c->ops->deny_idle)
                         c->ops->deny_idle(c);
+
+        of_ti_clk_deny_autoidle_all();
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc82c92..bda767a9dea8 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 struct omap_clk {
         u16                             cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
         }
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)      \
         static struct clk _name = {                             \
@@ -178,141 +178,6 @@ struct clksel {
         const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *                      omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *                       omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        struct clk              *clk_bypass;
-        struct clk              *clk_ref;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        unsigned long           last_rounded_rate;
-        u16                     last_rounded_m;
-        u8                      last_rounded_m4xen;
-        u8                      last_rounded_lpmode;
-        u16                     max_multiplier;
-        u8                      last_rounded_n;
-        u8                      min_divider;
-        u16                     max_divider;
-        u8                      modes;
-        void __iomem            *autoidle_reg;
-        void __iomem            *idlest_reg;
-        u32                     autoidle_mask;
-        u32                     freqsel_mask;
-        u32                     idlest_mask;
-        u32                     dco_mask;
-        u32                     sddiv_mask;
-        u32                     lpmode_mask;
-        u32                     m4xen_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-        u8                      flags;
-};
-
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- *     bits share the same register.  This flag allows the
- *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- *     should be used.  This is a temporary solution - a better approach
- *     would be to associate clock type-specific data with the clock,
- *     similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 1)
-#define CLOCK_NO_IDLE_PARENT    (1 << 2)
-#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2          (1 << 5)
-
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-        struct clk_hw           hw;
-        struct list_head        node;
-        unsigned long           fixed_rate;
-        u8                      fixed_div;
-        void __iomem            *enable_reg;
-        u8                      enable_bit;
-        u8                      flags;
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-        const char              *clkdm_name;
-        struct clockdomain      *clkdm;
-        const struct clk_hw_omap_ops    *ops;
-};
-
 struct clk_hw_omap_ops {
         void                    (*find_idlest)(struct clk_hw_omap *oclk,
                                         void __iomem **idlest_reg,
@@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 #define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
 #define OMAP4XXX_EN_DPLL_LOCKED                 0x7
 
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP     0x1
-#define DPLL_LOW_POWER_BYPASS   0x5
-#define DPLL_LOCKED             0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE             0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-                        unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-                                    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-                                unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-                                    unsigned long target_rate,
-                                    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,29 +238,25 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
                                    void __iomem **other_reg,
                                    u8 *other_bit);
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
                                 void __iomem **idlest_reg,
                                 u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                                const char *core_ck_name,
                                const char *mpu_ck_name);
 
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
+
 extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
@@ -433,19 +271,12 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
@@ -460,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
 
+extern void __iomem *clk_memmaps[];
+
 extern int am33xx_clk_init(void);
 
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index bbd6a3f717e6..91ccb962e09e 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
         struct clk_divider *parent;
         struct clk_hw *parent_hw;
         u32 dummy_v, orig_v;
+        struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
         int ret;
 
         /* Clear PWRDN bit of HSDIVIDER */
@@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 
         /* Restore the dividers */
         if (!ret) {
-                orig_v = __raw_readl(parent->reg);
+                orig_v = omap2_clk_readl(omap_clk, parent->reg);
                 dummy_v = orig_v;
 
                 /* Write any other value different from the Read value */
                 dummy_v ^= (1 << parent->shift);
-                __raw_writel(dummy_v, parent->reg);
+                omap2_clk_writel(dummy_v, omap_clk, parent->reg);
 
                 /* Write the original divider */
-                __raw_writel(orig_v, parent->reg);
+                omap2_clk_writel(orig_v, omap_clk, parent->reg);
         }
 
         return ret;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a882ae..78d9f562e3ce 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,11 +9,8 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 
 int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
-                                        unsigned long parent_rate);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
                                         unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
 
 extern struct clk *sdrc_ick_p;
 extern struct clk *arm_fck_p;
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 72bb41b3fd25..f338177e6900 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,5 +10,6 @@ struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                        struct ads7846_platform_data *board_pdata);
+void *n8x0_legacy_init(void);
 
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index e30ef6797c63..a6aae300542c 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -62,11 +62,17 @@ static inline int omap3_pm_init(void)
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
 int omap4_pm_init(void);
+int omap4_pm_init_early(void);
 #else
 static inline int omap4_pm_init(void)
 {
         return 0;
 }
+
+static inline int omap4_pm_init_early(void)
+{
+        return 0;
+}
 #endif
 
 #ifdef CONFIG_OMAP_MUX
@@ -236,6 +242,7 @@ static inline void __iomem *omap4_get_scu_base(void)
 
 extern void __init gic_init_irq(void);
 extern void gic_dist_disable(void);
+extern void gic_dist_enable(void);
 extern bool gic_dist_disabled(void);
 extern void gic_timer_retrigger(void);
 extern void omap_smc1(u32 fn, u32 arg);
@@ -293,6 +300,7 @@ static inline void omap4_cpu_resume(void)
 #endif
 
 void pdata_quirks_init(struct of_device_id *);
+void omap_auxdata_legacy_init(struct device *dev);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
 
 struct omap_sdrc_params;
@@ -305,7 +313,7 @@ struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
 /* SoC specific clock initializer */
-extern int (*omap_clk_init)(void);
+int omap_clk_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4c8982ae9529..4c158c838d40 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -80,6 +80,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
                         int index)
 {
         struct idle_statedata *cx = state_ptr + index;
+        u32 mpuss_can_lose_context = 0;
 
         /*
          * CPU0 has to wait and stay ON until CPU1 is OFF state.
@@ -104,6 +105,9 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
                 }
         }
 
+        mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
+                                 (cx->mpu_logic_state == PWRDM_POWER_OFF);
+
         /*
          * Call idle CPU PM enter notifier chain so that
          * VFP and per CPU interrupt context is saved.
@@ -118,9 +122,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
                  * Call idle CPU cluster PM enter notifier chain
                  * to save GIC and wakeupgen context.
                  */
-                if ((cx->mpu_state == PWRDM_POWER_RET) &&
-                        (cx->mpu_logic_state == PWRDM_POWER_OFF))
-                                cpu_cluster_pm_enter();
+                if (mpuss_can_lose_context)
+                        cpu_cluster_pm_enter();
         }
 
         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
@@ -128,9 +131,23 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
 
         /* Wakeup CPU1 only if it is not offlined */
         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
+
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
+                    mpuss_can_lose_context)
+                        gic_dist_disable();
+
                 clkdm_wakeup(cpu_clkdm[1]);
                 omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
                 clkdm_allow_idle(cpu_clkdm[1]);
+
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
+                    mpuss_can_lose_context) {
+                        while (gic_dist_disabled()) {
+                                udelay(1);
+                                cpu_relax();
+                        }
+                        gic_timer_retrigger();
+                }
         }
 
         /*
@@ -143,8 +160,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
          * Call idle CPU cluster PM exit notifier chain
          * to restore GIC and wakeupgen context.
          */
-        if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
-                (cx->mpu_logic_state == PWRDM_POWER_OFF))
+        if (dev->cpu == 0 && mpuss_can_lose_context)
                 cpu_cluster_pm_exit();
 
 fail:
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296cfcace..3185ced807c9 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
 
         dd = clk->dpll_data;
 
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= ~dd->enable_mask;
         v |= clken_bits << __ffs(dd->enable_mask);
-        __raw_writel(v, dd->control_reg);
+        omap2_clk_writel(v, clk, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
 
         state <<= __ffs(dd->idlest_mask);
 
-        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
-               i < MAX_DPLL_WAIT_TRIES) {
+        while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
+                != state) && i < MAX_DPLL_WAIT_TRIES) {
                 i++;
                 udelay(1);
         }
@@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
         state <<= __ffs(dd->idlest_mask);
 
         /* Check if already locked */
-        if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
+        if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
                 goto done;
 
         ai = omap3_dpll_autoidle_read(clk);
@@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
          * only since freqsel field is no longer present on other devices.
          */
         if (cpu_is_omap343x()) {
-                v = __raw_readl(dd->control_reg);
+                v = omap2_clk_readl(clk, dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
-                __raw_writel(v, dd->control_reg);
+                omap2_clk_writel(v, clk, dd->control_reg);
         }
 
         /* Set DPLL multiplier, divider */
-        v = __raw_readl(dd->mult_div1_reg);
+        v = omap2_clk_readl(clk, dd->mult_div1_reg);
         v &= ~(dd->mult_mask | dd->div1_mask);
         v |= dd->last_rounded_m << __ffs(dd->mult_mask);
         v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
@@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
                 v |= sd_div << __ffs(dd->sddiv_mask);
         }
 
-        __raw_writel(v, dd->mult_div1_reg);
+        omap2_clk_writel(v, clk, dd->mult_div1_reg);
 
         /* Set 4X multiplier and low-power mode */
         if (dd->m4xen_mask || dd->lpmode_mask) {
-                v = __raw_readl(dd->control_reg);
+                v = omap2_clk_readl(clk, dd->control_reg);
 
                 if (dd->m4xen_mask) {
                         if (dd->last_rounded_m4xen)
@@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
                                 v &= ~dd->lpmode_mask;
                 }
 
-                __raw_writel(v, dd->control_reg);
+                omap2_clk_writel(v, clk, dd->control_reg);
         }
 
         /* We let the clock framework set the other output dividers later */
@@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
         if (!dd->autoidle_reg)
                 return -EINVAL;
 
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= dd->autoidle_mask;
         v >>= __ffs(dd->autoidle_mask);
 
@@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
          * by writing 0x5 instead of 0x1.  Add some mechanism to
          * optionally enter this mode.
          */
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
+        omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
         if (!dd->autoidle_reg)
                 return;
 
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
+        omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
         struct clk_hw_omap *pclk = NULL;
         struct clk *parent;
 
+        if (!parent_rate)
+                return 0;
+
         /* Walk up the parents of clk, looking for a DPLL */
         do {
                 do {
@@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 
         WARN_ON(!dd->enable_mask);
 
-        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
                 rate = parent_rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d28b0f726715..52f9438b92f2 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= mask;
         v >>= __ffs(mask);
 
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         /* Clear the bit to allow gatectrl */
         v &= ~mask;
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         /* Set the bit to deny gatectrl */
         v |= mask;
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
         rate = omap2_get_dpll_rate(clk);
 
         /* regm4xen adds a multiplier of 4 to DPLL calculations */
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         if (v & OMAP4430_DPLL_REGM4XEN_MASK)
                 rate *= OMAP4430_REGM4XEN_MULT;
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 662c7fd633cc..174caecc3186 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
         return 1;
 }
 
+/* This function will go away once the device-tree convertion is complete */
+static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
+                            struct gpmc_settings *s)
+{
+        /* Enable RD PIN Monitoring Reg */
+        if (gpmc_nand_data->dev_ready) {
+                s->wait_on_read = true;
+                s->wait_on_write = true;
+        }
+
+        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                s->device_width = GPMC_DEVWIDTH_16BIT;
+        else
+                s->device_width = GPMC_DEVWIDTH_8BIT;
+}
+
 int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
@@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
+        }
 
-                if (gpmc_nand_data->of_node) {
-                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
-                } else {
-                        /* Enable RD PIN Monitoring Reg */
-                        if (gpmc_nand_data->dev_ready) {
-                                s.wait_on_read = true;
-                                s.wait_on_write = true;
-                        }
-                }
-
-                s.device_nand = true;
+        if (gpmc_nand_data->of_node)
+                gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+        else
+                gpmc_set_legacy(gpmc_nand_data, &s);
 
-                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                        s.device_width = GPMC_DEVWIDTH_16BIT;
-                else
-                        s.device_width = GPMC_DEVWIDTH_8BIT;
+        s.device_nand = true;
 
-                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
-                if (err < 0)
-                        goto out_free_cs;
+        err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+        if (err < 0)
+                goto out_free_cs;
 
-                err = gpmc_configure(GPMC_CONFIG_WP, 0);
-                if (err < 0)
-                        goto out_free_cs;
-        }
+        err = gpmc_configure(GPMC_CONFIG_WP, 0);
+        if (err < 0)
+                goto out_free_cs;
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cd22262a2cc0..d408b15b4fbf 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
 #include "prm44xx.h"
 
 /*
- * omap_clk_init: points to a function that does the SoC-specific
+ * omap_clk_soc_init: points to a function that does the SoC-specific
  * clock initializations
  */
-int (*omap_clk_init)(void);
+static int (*omap_clk_soc_init)(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -244,7 +244,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                 .virtual        = OMAP4_SRAM_VA,
                 .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
                 .length         = PAGE_SIZE,
-                .type           = MT_MEMORY_SO,
+                .type           = MT_MEMORY_RW_SO,
         },
 #endif
 
@@ -282,7 +282,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
                 .virtual        = OMAP4_SRAM_VA,
                 .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
                 .length         = PAGE_SIZE,
-                .type           = MT_MEMORY_SO,
+                .type           = MT_MEMORY_RW_SO,
         },
 #endif
 };
@@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
         omap242x_clockdomains_init();
         omap2420_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap2420_clk_init;
+        omap_clk_soc_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
         omap243x_clockdomains_init();
         omap2430_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap2430_clk_init;
+        omap_clk_soc_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -482,27 +482,35 @@ void __init omap3_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap3xxx_clk_init;
+        omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap35xx_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap3630_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3630_dt_clk_init;
 }
 
 void __init am35xx_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = am35xx_dt_clk_init;
 }
 
 void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap3xxx_clk_init;
+        if (of_have_populated_dt())
+                omap_clk_soc_init = ti81xx_dt_clk_init;
+        else
+                omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -581,7 +592,7 @@ void __init am33xx_init_early(void)
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = am33xx_clk_init;
+        omap_clk_soc_init = am33xx_dt_clk_init;
 }
 
 void __init am33xx_init_late(void)
@@ -606,6 +617,7 @@ void __init am43xx_init_early(void)
         am43xx_clockdomains_init();
         am43xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = am43xx_dt_clk_init;
 }
 
 void __init am43xx_init_late(void)
@@ -629,13 +641,14 @@ void __init omap4430_init_early(void)
         omap_cm_base_init();
         omap4xxx_check_revision();
         omap4xxx_check_features();
+        omap4_pm_init_early();
         omap44xx_prm_init();
         omap44xx_voltagedomains_init();
         omap44xx_powerdomains_init();
         omap44xx_clockdomains_init();
         omap44xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap4xxx_clk_init;
+        omap_clk_soc_init = omap4xxx_dt_clk_init;
 }
 
 void __init omap4430_init_late(void)
@@ -666,6 +679,7 @@ void __init omap5_init_early(void)
         omap54xx_clockdomains_init();
         omap54xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
@@ -691,6 +705,7 @@ void __init dra7xx_init_early(void)
         dra7xx_clockdomains_init();
         dra7xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = dra7xx_dt_clk_init;
 }
 
 void __init dra7xx_init_late(void)
@@ -710,3 +725,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                 _omap2_init_reprogram_sdrc();
         }
 }
+
+int __init omap_clk_init(void)
+{
+        int ret = 0;
+
+        if (!omap_clk_soc_init)
+                return 0;
+
+        ret = of_prcm_init();
+        if (!ret)
+                ret = omap_clk_soc_init();
+
+        return ret;
+}
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index c52d8b4a3e91..828e0db3d943 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh)
 
         return 0;
 }
-
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
-
-static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
-                                    *mmc_controller)
-{
-        if ((mmc_controller->slots[0].switch_pin > 0) && \
-                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
-                                        OMAP_PIN_INPUT_PULLUP);
-        if ((mmc_controller->slots[0].gpio_wp > 0) && \
-                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
-                                        OMAP_PIN_INPUT_PULLUP);
-
-        omap_mux_init_signal("sdmmc_cmd", 0);
-        omap_mux_init_signal("sdmmc_clki", 0);
-        omap_mux_init_signal("sdmmc_clko", 0);
-        omap_mux_init_signal("sdmmc_dat0", 0);
-        omap_mux_init_signal("sdmmc_dat_dir0", 0);
-        omap_mux_init_signal("sdmmc_cmd_dir", 0);
-        if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
-                omap_mux_init_signal("sdmmc_dat1", 0);
-                omap_mux_init_signal("sdmmc_dat2", 0);
-                omap_mux_init_signal("sdmmc_dat3", 0);
-                omap_mux_init_signal("sdmmc_dat_dir1", 0);
-                omap_mux_init_signal("sdmmc_dat_dir2", 0);
-                omap_mux_init_signal("sdmmc_dat_dir3", 0);
-        }
-
-        /*
-         * Use internal loop-back in MMC/SDIO Module Input Clock
-         * selection
-         */
-        if (mmc_controller->slots[0].internal_clock) {
-                u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-                v |= (1 << 24);
-                omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-        }
-}
-
-void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-{
-        struct platform_device *pdev;
-        struct omap_hwmod *oh;
-        int id = 0;
-        char *oh_name = "msdi1";
-        char *dev_name = "mmci-omap";
-
-        if (!mmc_data[0]) {
-                pr_err("%s fails: Incomplete platform data\n", __func__);
-                return;
-        }
-
-        omap242x_mmc_mux(mmc_data[0]);
-
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("Could not look up %s\n", oh_name);
-                return;
-        }
-        pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
-                                 sizeof(struct omap_mmc_platform_data));
-        if (IS_ERR(pdev))
-                WARN(1, "Can'd build omap_device for %s:%s.\n",
-                                        dev_name, oh->name);
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 16f78a990d04..a722330d4d53 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,8 +7,6 @@
  * published by the Free Software Foundation.
  */
 
-#include "mux2420.h"
-#include "mux2430.h"
 #include "mux34xx.h"
 
 #define OMAP_MUX_TERMINATOR     0xffff
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
deleted file mode 100644
index cf6de0971c6c..000000000000
--- a/arch/arm/mach-omap2/mux2420.c
+++ /dev/null
@@ -1,690 +0,0 @@
-/*
- * Copyright (C) 2010 Nokia
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "mux.h"
-
-#ifdef CONFIG_OMAP_MUX
-
-#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)               \
-{                                                                       \
-        .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .gpio           = (g),                                          \
-        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
-}
-
-#else
-
-#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)               \
-{                                                                       \
-        .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .gpio           = (g),                                          \
-}
-
-#endif
-
-#define _OMAP2420_BALLENTRY(M0, bb, bt)                                 \
-{                                                                       \
-        .reg_offset     = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .balls          = { bb, bt },                                   \
-}
-
-/*
- * Superset of all mux modes for omap2420
- */
-static struct omap_mux __initdata omap2420_muxmodes[] = {
-        _OMAP2420_MUXENTRY(CAM_D0, 54,
-                "cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
-                NULL, NULL, "etk_d2", NULL),
-        _OMAP2420_MUXENTRY(CAM_D1, 53,
-                "cam_d1", "hw_dbg3", "sti_din", "gpio_53",
-                NULL, NULL, "etk_d3", NULL),
-        _OMAP2420_MUXENTRY(CAM_D2, 52,
-                "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
-                NULL, NULL, "etk_d4", NULL),
-        _OMAP2420_MUXENTRY(CAM_D3, 51,
-                "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
-                NULL, NULL, "etk_d5", NULL),
-        _OMAP2420_MUXENTRY(CAM_D4, 50,
-                "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
-                NULL, NULL, "etk_d6", NULL),
-        _OMAP2420_MUXENTRY(CAM_D5, 49,
-                "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
-                NULL, NULL, "etk_d7", NULL),
-        _OMAP2420_MUXENTRY(CAM_D6, 0,
-                "cam_d6", "hw_dbg8", NULL, NULL,
-                NULL, NULL, "etk_d8", NULL),
-        _OMAP2420_MUXENTRY(CAM_D7, 0,
-                "cam_d7", "hw_dbg9", NULL, NULL,
-                NULL, NULL, "etk_d9", NULL),
-        _OMAP2420_MUXENTRY(CAM_D8, 54,
-                "cam_d8", "hw_dbg10", NULL, "gpio_54",
-                NULL, NULL, "etk_d10", NULL),
-        _OMAP2420_MUXENTRY(CAM_D9, 53,
-                "cam_d9", "hw_dbg11", NULL, "gpio_53",
-                NULL, NULL, "etk_d11", NULL),
-        _OMAP2420_MUXENTRY(CAM_HS, 55,
-                "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
-                NULL, NULL, "etk_d1", NULL),
-        _OMAP2420_MUXENTRY(CAM_LCLK, 57,
-                "cam_lclk", NULL, "mcbsp_clks", "gpio_57",
-                NULL, NULL, "etk_c1", NULL),
-        _OMAP2420_MUXENTRY(CAM_VS, 56,
-                "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
-                NULL, NULL, "etk_d0", NULL),
-        _OMAP2420_MUXENTRY(CAM_XCLK, 0,
-                "cam_xclk", NULL, "sti_clk", NULL,
-                NULL, NULL, "etk_c2", NULL),
-        _OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
-                "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA10, 40,
-                "dss_data10", NULL, NULL, "gpio_40",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA11, 41,
-                "dss_data11", NULL, NULL, "gpio_41",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA12, 42,
-                "dss_data12", NULL, NULL, "gpio_42",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA13, 43,
-                "dss_data13", NULL, NULL, "gpio_43",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA14, 44,
-                "dss_data14", NULL, NULL, "gpio_44",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA15, 45,
-                "dss_data15", NULL, NULL, "gpio_45",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA16, 46,
-                "dss_data16", NULL, NULL, "gpio_46",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA17, 47,
-                "dss_data17", NULL, NULL, "gpio_47",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA8, 38,
-                "dss_data8", NULL, NULL, "gpio_38",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(DSS_DATA9, 39,
-                "dss_data9", NULL, NULL, "gpio_39",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
-                "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
-                "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_FS, 114,
-                "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
-                "eac_ac_mclk", NULL, NULL, "gpio_117",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_RST, 118,
-                "eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
-                "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
-                "eac_bt_din", NULL, NULL, "gpio_73",
-                NULL, NULL, "etk_d9", NULL),
-        _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
-                "eac_bt_dout", NULL, "sti_clk", "gpio_74",
-                NULL, NULL, "etk_d8", NULL),
-        _OMAP2420_MUXENTRY(EAC_BT_FS, 72,
-                "eac_bt_fs", NULL, NULL, "gpio_72",
-                NULL, NULL, "etk_d10", NULL),
-        _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
-                "eac_bt_sclk", NULL, NULL, "gpio_71",
-                NULL, NULL, "etk_d11", NULL),
-        _OMAP2420_MUXENTRY(GPIO_119, 119,
-                "gpio_119", NULL, "sti_din", "gpio_119",
-                NULL, "sys_boot0", "etk_d12", NULL),
-        _OMAP2420_MUXENTRY(GPIO_120, 120,
-                "gpio_120", NULL, "sti_dout", "gpio_120",
-                "cam_d9", "sys_boot1", "etk_d13", NULL),
-        _OMAP2420_MUXENTRY(GPIO_121, 121,
-                "gpio_121", NULL, NULL, "gpio_121",
-                "jtag_emu2", "sys_boot2", "etk_d14", NULL),
-        _OMAP2420_MUXENTRY(GPIO_122, 122,
-                "gpio_122", NULL, NULL, "gpio_122",
-                "jtag_emu3", "sys_boot3", "etk_d15", NULL),
-        _OMAP2420_MUXENTRY(GPIO_124, 124,
-                "gpio_124", NULL, NULL, "gpio_124",
-                NULL, "sys_boot5", NULL, NULL),
-        _OMAP2420_MUXENTRY(GPIO_125, 125,
-                "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPIO_36, 36,
-                "gpio_36", NULL, NULL, "gpio_36",
-                NULL, "sys_boot4", NULL, NULL),
-        _OMAP2420_MUXENTRY(GPIO_62, 62,
-                "gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPIO_6, 6,
-                "gpio_6", "tv_detpulse", NULL, "gpio_6",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A10, 3,
-                "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A1, 12,
-                "gpmc_a1", "dss_data18", NULL, "gpio_12",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A2, 11,
-                "gpmc_a2", "dss_data19", NULL, "gpio_11",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A3, 10,
-                "gpmc_a3", "dss_data20", NULL, "gpio_10",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A4, 9,
-                "gpmc_a4", "dss_data21", NULL, "gpio_9",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A5, 8,
-                "gpmc_a5", "dss_data22", NULL, "gpio_8",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A6, 7,
-                "gpmc_a6", "dss_data23", NULL, "gpio_7",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A7, 6,
-                "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A8, 5,
-                "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_A9, 4,
-                "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_CLK, 21,
-                "gpmc_clk", NULL, NULL, "gpio_21",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D10, 18,
-                "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D11, 17,
-                "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D12, 16,
-                "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D13, 15,
-                "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D14, 14,
-                "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D15, 13,
-                "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D8, 20,
-                "gpmc_d8", NULL, NULL, "gpio_20",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_D9, 19,
-                "gpmc_d9", "ssi2_wake", NULL, "gpio_19",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NBE0, 29,
-                "gpmc_nbe0", NULL, NULL, "gpio_29",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NBE1, 30,
-                "gpmc_nbe1", NULL, NULL, "gpio_30",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS1, 22,
-                "gpmc_ncs1", NULL, NULL, "gpio_22",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS2, 23,
-                "gpmc_ncs2", NULL, NULL, "gpio_23",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS3, 24,
-                "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS4, 25,
-                "gpmc_ncs4", NULL, NULL, "gpio_25",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS5, 26,
-                "gpmc_ncs5", NULL, NULL, "gpio_26",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS6, 27,
-                "gpmc_ncs6", NULL, NULL, "gpio_27",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NCS7, 28,
-                "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_NWP, 31,
-                "gpmc_nwp", NULL, NULL, "gpio_31",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
-                "gpmc_wait1", NULL, NULL, "gpio_33",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
-                "gpmc_wait2", NULL, NULL, "gpio_34",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
-                "gpmc_wait3", NULL, NULL, "gpio_35",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(HDQ_SIO, 101,
-                "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(I2C2_SCL, 99,
-                "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(I2C2_SDA, 100,
-                "i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(JTAG_EMU0, 127,
-                "jtag_emu0", NULL, NULL, "gpio_127",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(JTAG_EMU1, 126,
-                "jtag_emu1", NULL, NULL, "gpio_126",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
-                "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
-                "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_DR, 95,
-                "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_DX, 94,
-                "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
-                "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
-                "spi2_ncs1", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
-                "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
-                "mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP2_DR, 11,
-                "mcbsp2_dr", NULL, "dss_data22", "gpio_11",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
-                "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_CLKI, 59,
-                "sdmmc_clki", "ms_clki", NULL, "gpio_59",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_CLKO, 0,
-                "sdmmc_clko", "ms_clko", NULL, NULL,
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
-                "sdmmc_cmd_dir", NULL, NULL, "gpio_8",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_CMD, 0,
-                "sdmmc_cmd", "ms_bs", NULL, NULL,
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
-                "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT0, 0,
-                "sdmmc_dat0", "ms_dat0", NULL, NULL,
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
-                "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT1, 75,
-                "sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
-                "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT2, 76,
-                "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
-                "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(MMC_DAT3, 77,
-                "sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SDRC_A12, 2,
-                "sdrc_a12", NULL, NULL, "gpio_2",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SDRC_A13, 1,
-                "sdrc_a13", NULL, NULL, "gpio_1",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SDRC_A14, 0,
-                "sdrc_a14", NULL, NULL, "gpio_0",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SDRC_CKE1, 38,
-                "sdrc_cke1", NULL, NULL, "gpio_38",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SDRC_NCS1, 37,
-                "sdrc_ncs1", NULL, NULL, "gpio_37",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_CLK, 81,
-                "spi1_clk", NULL, NULL, "gpio_81",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_NCS0, 84,
-                "spi1_ncs0", NULL, NULL, "gpio_84",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_NCS1, 85,
-                "spi1_ncs1", NULL, NULL, "gpio_85",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_NCS2, 86,
-                "spi1_ncs2", NULL, NULL, "gpio_86",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_NCS3, 87,
-                "spi1_ncs3", NULL, NULL, "gpio_87",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_SIMO, 82,
-                "spi1_simo", NULL, NULL, "gpio_82",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI1_SOMI, 83,
-                "spi1_somi", NULL, NULL, "gpio_83",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI2_CLK, 88,
-                "spi2_clk", NULL, NULL, "gpio_88",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI2_NCS0, 91,
-                "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI2_SIMO, 89,
-                "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SPI2_SOMI, 90,
-                "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
-                "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
-                "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
-                "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
-                "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
-                "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
-                "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SSI1_WAKE, 66,
-                "ssi1_wake", "eac_md_fs", NULL, "gpio_66",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
-                "sys_clkout", NULL, NULL, "gpio_123",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
-                "sys_clkreq", NULL, NULL, "gpio_52",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(SYS_NIRQ, 60,
-                "sys_nirq", NULL, NULL, "gpio_60",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART1_CTS, 32,
-                "uart1_cts", NULL, "dss_data18", "gpio_32",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART1_RTS, 8,
-                "uart1_rts", NULL, "dss_data19", "gpio_8",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART1_RX, 10,
-                "uart1_rx", NULL, "dss_data21", "gpio_10",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART1_TX, 9,
-                "uart1_tx", NULL, "dss_data20", "gpio_9",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART2_CTS, 67,
-                "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART2_RTS, 68,
-                "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART2_RX, 70,
-                "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART2_TX, 69,
-                "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
-                "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
-                "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
-                "uart3_rx_irrx", NULL, NULL, "gpio_105",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
-                "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_DAT, 112,
-                "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
-                "uart2_tx", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_PUEN, 106,
-                "usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_RCV, 109,
-                "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
-                "uart2_cts", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_SE0, 111,
-                "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
-                "uart2_rx", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_TXEN, 110,
-                "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_VM, 108,
-                "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
-                "uart2_rx", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(USB0_VP, 107,
-                "usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
-                "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
-                "vlynq_nla", NULL, NULL, "gpio_58",
-                "cam_d6", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
-                "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
-                "cam_d7", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
-                "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
-                "cam_d8", NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
-                "vlynq_tx0", "usb2_txen", NULL, "gpio_17",
-                NULL, NULL, NULL, NULL),
-        _OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
-                "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
-                NULL, NULL, NULL, NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 447-pin POP package
- */
-#ifdef CONFIG_DEBUG_FS
-static struct omap_ball __initdata omap2420_pop_ball[] = {
-        _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
-        _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
-        _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
-        _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
-        _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
-        _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
-        _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
-        _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
-        _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
-        _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
-        _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
-        _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
-        _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
-        _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
-        _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
-        _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
-        _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
-        _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
-        _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
-        _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
-        _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
-        _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
-        _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
-        _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
-        _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
-        _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
-        _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
-        _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
-        _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
-        _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
-        _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
-        _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
-        _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
-        _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
-        _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
-        _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
-        _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
-        _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
-        _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
-        _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
-        _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
-        _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
-        _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
-        _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
-        _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
-        _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
-        _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
-        _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
-        _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
-        _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
-        _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
-        _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
-        _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
-        _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
-        _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
-        _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
-        _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
-        _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
-        _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
-        _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
-        _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
-        _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
-        _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
-        _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
-        _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
-        _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
-        _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
-        _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
-        _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
-        _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
-        _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
-        _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
-        _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
-        _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
-        _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
-        _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
-        _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
-        _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
-        _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
-        _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
-        _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
-        _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
-        _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
-        _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
-        _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
-        _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
-        _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
-        _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
-        _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
-        _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
-        _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
-        _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
-        _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
-        _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
-        _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
-        _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
-        _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
-        _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
-        _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
-        _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
-        _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
-        _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
-        _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
-        _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
-        _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
-        _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
-        _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap2420_pop_ball        NULL
-#endif
-
-int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
-{
-        struct omap_ball *package_balls = NULL;
-
-        switch (flags & OMAP_PACKAGE_MASK) {
-        case OMAP_PACKAGE_ZAC:
-                package_balls = omap2420_pop_ball;
-                break;
-        case OMAP_PACKAGE_ZAF:
-                /* REVISIT: Please add data */
-        default:
-                pr_warning("%s: No ball data available for omap2420 package\n",
-                                __func__);
-        }
-
-        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
-                             OMAP2420_CONTROL_PADCONF_MUX_PBASE,
-                             OMAP2420_CONTROL_PADCONF_MUX_SIZE,
-                             omap2420_muxmodes, NULL, board_subset,
-                             package_balls);
-}
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
deleted file mode 100644
index 0f555aa847b5..000000000000
--- a/arch/arm/mach-omap2/mux2420.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define OMAP2420_CONTROL_PADCONF_MUX_PBASE                      0x48000030LU
-
-#define OMAP2420_MUX(mode0, mux_value)                                  \
-{                                                                       \
-        .reg_offset     = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET),  \
-        .value          = (mux_value),                                  \
-}
-
-/*
- * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
- *
- * Extracted from the TRM.  Add 0x48000030 to these values to get the
- * absolute addresses.  The name in the macro is the mode-0 name of
- * the pin.  NOTE: These registers are 8-bits wide.
- */
-#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET                        0x000
-#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET                        0x001
-#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET                        0x002
-#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET                        0x003
-#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET                        0x004
-#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET                        0x005
-#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET                        0x006
-#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET                         0x007
-#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET                         0x008
-#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET                         0x009
-#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET                         0x00a
-#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET                         0x00b
-#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET                         0x00c
-#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET                         0x00d
-#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET                         0x00e
-#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET                         0x00f
-#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET                         0x010
-#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET                        0x021
-#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET                        0x022
-#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET                        0x023
-#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET                        0x024
-#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET                        0x025
-#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET                        0x026
-#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET                        0x027
-#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET                        0x028
-#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET                        0x029
-#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET                        0x02a
-#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET                        0x02b
-#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET                        0x02c
-#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET                        0x02d
-#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET                        0x02e
-#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET                        0x02f
-#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET                        0x030
-#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET                        0x031
-#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET                        0x032
-#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET                        0x033
-#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET                        0x034
-#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET                        0x035
-#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET                        0x036
-#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET                         0x037
-#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET                         0x038
-#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET                         0x039
-#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET                         0x03a
-#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET                         0x03b
-#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET                         0x03c
-#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET                         0x03d
-#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET                         0x03e
-#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET                         0x03f
-#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET                         0x040
-#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET                        0x041
-#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET                         0x042
-#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET                         0x043
-#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET                         0x044
-#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET                         0x045
-#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET                         0x046
-#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET                         0x047
-#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET                         0x048
-#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET                         0x049
-#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET                         0x04a
-#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET                        0x04b
-#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET                        0x04c
-#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET                        0x04d
-#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET                        0x04e
-#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET                        0x04f
-#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET                        0x050
-#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET                         0x051
-#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET                         0x052
-#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET                         0x053
-#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET                         0x054
-#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET                         0x055
-#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET                         0x056
-#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET                         0x057
-#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET                         0x058
-#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET                         0x059
-#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET                         0x05a
-#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET                        0x05b
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET                       0x05c
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET                       0x05d
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET                       0x05e
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET                       0x05f
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET                       0x060
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET                       0x061
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET                       0x062
-#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET                       0x063
-#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET                   0x064
-#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET                        0x065
-#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET                        0x066
-#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET                       0x067
-#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET                       0x068
-#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET                        0x069
-#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET                      0x06a
-#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET                      0x06b
-#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET                      0x06c
-#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET                      0x06d
-#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET                        0x06e
-#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET                       0x06f
-#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET                       0x070
-#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET                       0x071
-#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET                       0x072
-#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET                       0x073
-#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET                       0x074
-#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET                       0x075
-#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET                        0x076
-#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET                        0x077
-#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET                        0x078
-#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET                        0x079
-#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET                        0x07a
-#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET                       0x07f
-#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET                       0x080
-#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET                       0x081
-#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET                       0x082
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET                       0x083
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET                       0x084
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET                       0x085
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET                       0x086
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET                       0x087
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET                       0x088
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET                       0x089
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET                       0x08a
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET                       0x08b
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET                       0x08c
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET                      0x08d
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET                      0x08e
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET                      0x08f
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET                      0x090
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET                      0x091
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET                      0x092
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET                      0x093
-#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET                      0x094
-#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET                       0x095
-#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET                       0x096
-#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET                        0x097
-#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET                        0x098
-#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET                       0x099
-#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET                     0x09a
-#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET                         0x09b
-#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET                       0x09c
-#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET                       0x09d
-#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET                      0x09e
-#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET                          0x09f
-#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET                          0x0a0
-#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET                          0x0a1
-#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET                          0x0a2
-#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET                          0x0a3
-#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET                          0x0a4
-#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET                          0x0a5
-#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET                          0x0a6
-#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET                          0x0a7
-#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET                          0x0a8
-#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET                          0x0a9
-#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET                          0x0aa
-#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET                        0x0ab
-#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET                        0x0ac
-#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET                     0x0ad
-#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET                    0x0ae
-#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET                     0x0af
-#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET                         0x0b0
-#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET                     0x0b1
-#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET                    0x0b2
-#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET                     0x0b3
-#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET                       0x0b4
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET                       0x0b5
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET                       0x0b6
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET                       0x0b7
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET                       0x0b8
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET                       0x0b9
-#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET                       0x0ba
-#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET                       0x0bb
-#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET                       0x0bc
-#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET                        0x0bd
-#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET                        0x0be
-#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET                     0x0bf
-#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET                       0x0c0
-#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET                      0x0c1
-#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET                     0x0c2
-#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET                        0x0c3
-#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET                         0x0c4
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET                        0x0c5
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET                        0x0c6
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET                        0x0c7
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET                        0x0c8
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET                    0x0c9
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET                    0x0ca
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET                    0x0cb
-#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET                    0x0cc
-#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET                     0x0cd
-#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET                        0x0ce
-#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET                        0x0cf
-#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET                       0x0d0
-#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET                       0x0d1
-#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET                       0x0d2
-#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET                       0x0d3
-#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET                       0x0d4
-#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET                       0x0d5
-#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET                        0x0d6
-#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET                       0x0d7
-#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET                       0x0d8
-#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET                       0x0d9
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET                     0x0da
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET                      0x0db
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET                       0x0dc
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET                       0x0dd
-#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET                      0x0de
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET                      0x0df
-#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET                     0x0e0
-#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET                        0x0e1
-#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET                        0x0e2
-#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET                        0x0e3
-#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET                        0x0e4
-#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET                         0x0e5
-#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET                  0x0e6
-#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET                    0x0e7
-#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET                   0x0e8
-#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET                   0x0e9
-#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET                         0x0ea
-#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET                         0x0eb
-#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET                         0x0ec
-#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET                       0x0ed
-#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET                         0x0ee
-#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET                         0x0ef
-#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET                        0x0f0
-#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET                       0x0f1
-#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET                        0x0f2
-#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET                        0x0f3
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET                     0x0f4
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET                       0x0f5
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET                      0x0f6
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET                     0x0f7
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET                     0x0f8
-#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET                      0x0f9
-#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET                   0x0fa
-#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET                    0x0fb
-#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET                        0x0fc
-#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET                          0x0fd
-#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET                        0x0fe
-#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET                        0x0ff
-#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET                        0x100
-#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET                        0x101
-#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET                         0x102
-#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET                      0x103
-#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET                     0x104
-#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET                         0x105
-#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET                      0x106
-#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET                      0x107
-#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET                          0x108
-#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET                        0x109
-#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET                        0x10a
-#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET                       0x10b
-#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET                       0x10c
-#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET                      0x10d
-#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET                        0x10e
-#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET                       0x10f
-#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET                        0x110
-#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET                        0x111
-#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET                        0x112
-
-#define OMAP2420_CONTROL_PADCONF_MUX_SIZE                       \
-                (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
deleted file mode 100644
index 4185f92553db..000000000000
--- a/arch/arm/mach-omap2/mux2430.c
+++ /dev/null
@@ -1,793 +0,0 @@
-/*
- * Copyright (C) 2010 Nokia
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "mux.h"
-
-#ifdef CONFIG_OMAP_MUX
-
-#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)               \
-{                                                                       \
-        .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .gpio           = (g),                                          \
-        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
-}
-
-#else
-
-#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)               \
-{                                                                       \
-        .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .gpio           = (g),                                          \
-}
-
-#endif
-
-#define _OMAP2430_BALLENTRY(M0, bb, bt)                                 \
-{                                                                       \
-        .reg_offset     = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),     \
-        .balls          = { bb, bt },                                   \
-}
-
-/*
- * Superset of all mux modes for omap2430
- */
-static struct omap_mux __initdata omap2430_muxmodes[] = {
-        _OMAP2430_MUXENTRY(CAM_D0, 133,
-                "cam_d0", "hw_dbg0", "sti_dout", "gpio_133",
-                NULL, NULL, "etk_d2", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D10, 146,
-                "cam_d10", NULL, NULL, "gpio_146",
-                NULL, NULL, "etk_d12", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D11, 145,
-                "cam_d11", NULL, NULL, "gpio_145",
-                NULL, NULL, "etk_d13", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D1, 132,
-                "cam_d1", "hw_dbg1", "sti_din", "gpio_132",
-                NULL, NULL, "etk_d3", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D2, 129,
-                "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129",
-                NULL, NULL, "etk_d4", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D3, 128,
-                "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128",
-                NULL, NULL, "etk_d5", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D4, 143,
-                "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143",
-                NULL, NULL, "etk_d6", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D5, 112,
-                "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112",
-                NULL, NULL, "etk_d7", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D6, 137,
-                "cam_d6", "hw_dbg6", NULL, "gpio_137",
-                NULL, NULL, "etk_d8", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D7, 136,
-                "cam_d7", "hw_dbg7", NULL, "gpio_136",
-                NULL, NULL, "etk_d9", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D8, 135,
-                "cam_d8", "hw_dbg8", NULL, "gpio_135",
-                NULL, NULL, "etk_d10", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_D9, 134,
-                "cam_d9", "hw_dbg9", NULL, "gpio_134",
-                NULL, NULL, "etk_d11", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_HS, 11,
-                "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11",
-                NULL, NULL, "etk_d1", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_LCLK, 0,
-                "cam_lclk", NULL, "mcbsp_clks", NULL,
-                NULL, NULL, "etk_c1", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_VS, 12,
-                "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12",
-                NULL, NULL, "etk_d0", "safe_mode"),
-        _OMAP2430_MUXENTRY(CAM_XCLK, 0,
-                "cam_xclk", NULL, "sti_clk", NULL,
-                NULL, NULL, "etk_c2", NULL),
-        _OMAP2430_MUXENTRY(DSS_ACBIAS, 48,
-                "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA0, 40,
-                "dss_data0", "uart1_cts", NULL, "gpio_40",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA10, 128,
-                "dss_data10", "sdi_data1n", NULL, "gpio_128",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA11, 129,
-                "dss_data11", "sdi_data1p", NULL, "gpio_129",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA12, 130,
-                "dss_data12", "sdi_data2n", NULL, "gpio_130",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA13, 131,
-                "dss_data13", "sdi_data2p", NULL, "gpio_131",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA14, 132,
-                "dss_data14", "sdi_data3n", NULL, "gpio_132",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA15, 133,
-                "dss_data15", "sdi_data3p", NULL, "gpio_133",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA16, 46,
-                "dss_data16", NULL, NULL, "gpio_46",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA17, 47,
-                "dss_data17", NULL, NULL, "gpio_47",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA1, 41,
-                "dss_data1", "uart1_rts", NULL, "gpio_41",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA2, 42,
-                "dss_data2", "uart1_tx", NULL, "gpio_42",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA3, 43,
-                "dss_data3", "uart1_rx", NULL, "gpio_43",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA4, 44,
-                "dss_data4", "uart3_rx_irrx", NULL, "gpio_44",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA5, 45,
-                "dss_data5", "uart3_tx_irtx", NULL, "gpio_45",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA6, 144,
-                "dss_data6", NULL, NULL, "gpio_144",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA7, 147,
-                "dss_data7", NULL, NULL, "gpio_147",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA8, 38,
-                "dss_data8", NULL, NULL, "gpio_38",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_DATA9, 39,
-                "dss_data9", NULL, NULL, "gpio_39",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(DSS_HSYNC, 110,
-                "dss_hsync", NULL, NULL, "gpio_110",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_113, 113,
-                "gpio_113", "mcbsp2_clkx", NULL, "gpio_113",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_114, 114,
-                "gpio_114", "mcbsp2_fsx", NULL, "gpio_114",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_115, 115,
-                "gpio_115", "mcbsp2_dr", NULL, "gpio_115",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_116, 116,
-                "gpio_116", "mcbsp2_dx", NULL, "gpio_116",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_128, 128,
-                "gpio_128", NULL, "sti_din", "gpio_128",
-                NULL, "sys_boot0", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_129, 129,
-                "gpio_129", NULL, "sti_dout", "gpio_129",
-                NULL, "sys_boot1", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_130, 130,
-                "gpio_130", NULL, NULL, "gpio_130",
-                "jtag_emu2", "sys_boot2", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_131, 131,
-                "gpio_131", NULL, NULL, "gpio_131",
-                "jtag_emu3", "sys_boot3", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_132, 132,
-                "gpio_132", NULL, NULL, "gpio_132",
-                NULL, "sys_boot4", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_133, 133,
-                "gpio_133", NULL, NULL, "gpio_133",
-                NULL, "sys_boot5", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_134, 134,
-                "gpio_134", "ccp_datn", NULL, "gpio_134",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_135, 135,
-                "gpio_135", "ccp_datp", NULL, "gpio_135",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_136, 136,
-                "gpio_136", "ccp_clkn", NULL, "gpio_136",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_137, 137,
-                "gpio_137", "ccp_clkp", NULL, "gpio_137",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_138, 138,
-                "gpio_138", "spi3_clk", NULL, "gpio_138",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_139, 139,
-                "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_140, 140,
-                "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140",
-                NULL, NULL, "etk_d14", "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_141, 141,
-                "gpio_141", "spi3_somi", NULL, "gpio_141",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_142, 142,
-                "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142",
-                NULL, NULL, "etk_d15", "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_148, 148,
-                "gpio_148", "mcbsp5_fsx", NULL, "gpio_148",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_149, 149,
-                "gpio_149", "mcbsp5_dx", NULL, "gpio_149",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_150, 150,
-                "gpio_150", "mcbsp5_dr", NULL, "gpio_150",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_151, 151,
-                "gpio_151", "sys_pwrok", NULL, "gpio_151",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_152, 152,
-                "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_153, 153,
-                "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_154, 154,
-                "gpio_154", "mcbsp5_clkx", NULL, "gpio_154",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_63, 63,
-                "gpio_63", "mcbsp4_clkx", NULL, "gpio_63",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_78, 78,
-                "gpio_78", NULL, "uart2_rts", "gpio_78",
-                "uart3_rts_sd", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_79, 79,
-                "gpio_79", "secure_indicator", "uart2_tx", "gpio_79",
-                "uart3_tx_irtx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_7, 7,
-                "gpio_7", NULL, "uart2_cts", "gpio_7",
-                "uart3_cts_rctx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPIO_80, 80,
-                "gpio_80", NULL, "uart2_rx", "gpio_80",
-                "uart3_rx_irrx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A10, 3,
-                "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A1, 31,
-                "gpmc_a1", NULL, NULL, "gpio_31",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A2, 30,
-                "gpmc_a2", NULL, NULL, "gpio_30",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A3, 29,
-                "gpmc_a3", NULL, NULL, "gpio_29",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A4, 49,
-                "gpmc_a4", NULL, NULL, "gpio_49",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A5, 53,
-                "gpmc_a5", NULL, NULL, "gpio_53",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A6, 52,
-                "gpmc_a6", NULL, NULL, "gpio_52",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A7, 6,
-                "gpmc_a7", NULL, NULL, "gpio_6",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A8, 5,
-                "gpmc_a8", NULL, NULL, "gpio_5",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_A9, 4,
-                "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_CLK, 21,
-                "gpmc_clk", NULL, NULL, "gpio_21",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D10, 18,
-                "gpmc_d10", NULL, NULL, "gpio_18",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D11, 57,
-                "gpmc_d11", NULL, NULL, "gpio_57",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D12, 77,
-                "gpmc_d12", NULL, NULL, "gpio_77",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D13, 76,
-                "gpmc_d13", NULL, NULL, "gpio_76",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D14, 55,
-                "gpmc_d14", NULL, NULL, "gpio_55",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D15, 54,
-                "gpmc_d15", NULL, NULL, "gpio_54",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D8, 20,
-                "gpmc_d8", NULL, NULL, "gpio_20",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_D9, 19,
-                "gpmc_d9", NULL, NULL, "gpio_19",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS1, 22,
-                "gpmc_ncs1", NULL, NULL, "gpio_22",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS2, 23,
-                "gpmc_ncs2", NULL, NULL, "gpio_23",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS3, 24,
-                "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS4, 25,
-                "gpmc_ncs4", NULL, NULL, "gpio_25",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS5, 26,
-                "gpmc_ncs5", NULL, NULL, "gpio_26",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS6, 27,
-                "gpmc_ncs6", NULL, NULL, "gpio_27",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_NCS7, 28,
-                "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_WAIT1, 33,
-                "gpmc_wait1", NULL, NULL, "gpio_33",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_WAIT2, 34,
-                "gpmc_wait2", NULL, NULL, "gpio_34",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(GPMC_WAIT3, 35,
-                "gpmc_wait3", NULL, NULL, "gpio_35",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(HDQ_SIO, 101,
-                "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
-                "uart3_rx_irrx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(I2C1_SCL, 50,
-                "i2c1_scl", NULL, NULL, "gpio_50",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(I2C1_SDA, 51,
-                "i2c1_sda", NULL, NULL, "gpio_51",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(I2C2_SCL, 99,
-                "i2c2_scl", NULL, NULL, "gpio_99",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(I2C2_SDA, 100,
-                "i2c2_sda", NULL, NULL, "gpio_100",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(JTAG_EMU0, 127,
-                "jtag_emu0", "secure_indicator", NULL, "gpio_127",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(JTAG_EMU1, 126,
-                "jtag_emu1", NULL, NULL, "gpio_126",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92,
-                "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98,
-                "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_DR, 95,
-                "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_DX, 94,
-                "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_FSR, 93,
-                "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93",
-                "spi2_cs1", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP1_FSX, 97,
-                "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147,
-                "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP2_DR, 144,
-                "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71,
-                "mcbsp3_clkx", NULL, NULL, "gpio_71",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP3_DR, 73,
-                "mcbsp3_dr", NULL, NULL, "gpio_73",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP3_DX, 74,
-                "mcbsp3_dx", NULL, "sti_clk", "gpio_74",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP3_FSX, 72,
-                "mcbsp3_fsx", NULL, NULL, "gpio_72",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(MCBSP_CLKS, 96,
-                "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0,
-                "sdmmc1_clko", "ms_clko", NULL, NULL,
-                NULL, "hw_dbg9", "hw_dbg3", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_CMD, 0,
-                "sdmmc1_cmd", "ms_bs", NULL, NULL,
-                NULL, "hw_dbg8", "hw_dbg2", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0,
-                "sdmmc1_dat0", "ms_dat0", NULL, NULL,
-                NULL, "hw_dbg7", "hw_dbg1", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75,
-                "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75",
-                NULL, "hw_dbg6", "hw_dbg0", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0,
-                "sdmmc1_dat2", "ms_dat2", NULL, NULL,
-                NULL, "hw_dbg5", "hw_dbg10", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0,
-                "sdmmc1_dat3", "ms_dat3", NULL, NULL,
-                NULL, "hw_dbg4", "hw_dbg11", "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13,
-                "sdmmc2_clko", NULL, NULL, "gpio_13",
-                NULL, "spi3_clk", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_CMD, 15,
-                "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15",
-                NULL, "spi3_simo", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16,
-                "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16",
-                NULL, "spi3_somi", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58,
-                "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17,
-                "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17",
-                NULL, "spi3_cs1", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14,
-                "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14",
-                NULL, "spi3_cs0", NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDRC_A12, 2,
-                "sdrc_a12", NULL, NULL, "gpio_2",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDRC_A13, 1,
-                "sdrc_a13", NULL, NULL, "gpio_1",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDRC_A14, 0,
-                "sdrc_a14", NULL, NULL, "gpio_0",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDRC_CKE1, 36,
-                "sdrc_cke1", NULL, NULL, "gpio_36",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SDRC_NCS1, 37,
-                "sdrc_ncs1", NULL, NULL, "gpio_37",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_CLK, 81,
-                "spi1_clk", NULL, NULL, "gpio_81",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_CS0, 84,
-                "spi1_cs0", NULL, NULL, "gpio_84",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_CS1, 85,
-                "spi1_cs1", NULL, NULL, "gpio_85",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_CS2, 86,
-                "spi1_cs2", NULL, NULL, "gpio_86",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_CS3, 87,
-                "spi1_cs3", "spi2_cs1", NULL, "gpio_87",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_SIMO, 82,
-                "spi1_simo", NULL, NULL, "gpio_82",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI1_SOMI, 83,
-                "spi1_somi", NULL, NULL, "gpio_83",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI2_CLK, 88,
-                "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI2_CS0, 91,
-                "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI2_SIMO, 89,
-                "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SPI2_SOMI, 90,
-                "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62,
-                "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59,
-                "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64,
-                "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60,
-                "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65,
-                "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61,
-                "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SSI1_WAKE, 66,
-                "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SYS_CLKOUT, 111,
-                "sys_clkout", NULL, NULL, "gpio_111",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118,
-                "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SYS_NIRQ0, 56,
-                "sys_nirq0", NULL, NULL, "gpio_56",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(SYS_NIRQ1, 125,
-                "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART1_CTS, 32,
-                "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32",
-                "mcbsp5_clkx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART1_RTS, 8,
-                "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8",
-                "mcbsp5_fsx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART1_RX, 10,
-                "uart1_rx", "sdi_stp", "dss_data21", "gpio_10",
-                "mcbsp5_dr", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART1_TX, 9,
-                "uart1_tx", "sdi_den", "dss_data20", "gpio_9",
-                "mcbsp5_dx", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART2_CTS, 67,
-                "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART2_RTS, 68,
-                "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART2_RX, 70,
-                "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART2_TX, 69,
-                "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102,
-                "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART3_RTS_SD, 103,
-                "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105,
-                "uart3_rx_irrx", NULL, NULL, "gpio_105",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104,
-                "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_CLK, 120,
-                "usb0hs_clk", NULL, NULL, "gpio_120",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA0, 0,
-                "usb0hs_data0", "uart3_tx_irtx", NULL, NULL,
-                "usb0_txen", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA1, 0,
-                "usb0hs_data1", "uart3_rx_irrx", NULL, NULL,
-                "usb0_dat", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA2, 0,
-                "usb0hs_data2", "uart3_rts_sd", NULL, NULL,
-                "usb0_se0", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA3, 106,
-                "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106",
-                "usb0_puen", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA4, 107,
-                "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107",
-                "usb0_vp", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA5, 108,
-                "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108",
-                "usb0_vm", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA6, 109,
-                "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109",
-                "usb0_rcv", NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DATA7, 124,
-                "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_DIR, 121,
-                "usb0hs_dir", NULL, NULL, "gpio_121",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_NXT, 123,
-                "usb0hs_nxt", NULL, NULL, "gpio_123",
-                NULL, NULL, NULL, "safe_mode"),
-        _OMAP2430_MUXENTRY(USB0HS_STP, 122,
-                "usb0hs_stp", NULL, NULL, "gpio_122",
-                NULL, NULL, NULL, "safe_mode"),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for POP package
- * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
- */
-#ifdef CONFIG_DEBUG_FS
-static struct omap_ball __initdata omap2430_pop_ball[] = {
-        _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
-        _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
-        _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
-        _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL),
-        _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL),
-        _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL),
-        _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL),
-        _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL),
-        _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL),
-        _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL),
-        _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL),
-        _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL),
-        _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL),
-        _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL),
-        _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL),
-        _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL),
-        _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL),
-        _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL),
-        _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL),
-        _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL),
-        _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL),
-        _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL),
-        _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL),
-        _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL),
-        _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL),
-        _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL),
-        _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL),
-        _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL),
-        _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL),
-        _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL),
-        _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL),
-        _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL),
-        _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL),
-        _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL),
-        _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL),
-        _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL),
-        _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL),
-        _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL),
-        _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL),
-        _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL),
-        _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL),
-        _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL),
-        _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL),
-        _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL),
-        _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL),
-        _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL),
-        _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL),
-        _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL),
-        _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL),
-        _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL),
-        _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL),
-        _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"),
-        _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"),
-        _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"),
-        _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"),
-        _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"),
-        _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"),
-        _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"),
-        _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"),
-        _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"),
-        _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"),
-        _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL),
-        _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL),
-        _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL),
-        _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL),
-        _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL),
-        _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL),
-        _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"),
-        _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL),
-        _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL),
-        _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL),
-        _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL),
-        _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL),
-        _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL),
-        _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL),
-        _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL),
-        _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL),
-        _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL),
-        _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL),
-        _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL),
-        _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL),
-        _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL),
-        _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL),
-        _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL),
-        _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL),
-        _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL),
-        _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL),
-        _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"),
-        _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"),
-        _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"),
-        _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"),
-        _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"),
-        _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL),
-        _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL),
-        _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL),
-        _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL),
-        _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL),
-        _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL),
-        _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL),
-        _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL),
-        _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL),
-        _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL),
-        _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL),
-        _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL),
-        _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL),
-        _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL),
-        _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL),
-        _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL),
-        _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL),
-        _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL),
-        _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL),
-        _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL),
-        _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL),
-        _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL),
-        _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL),
-        _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL),
-        _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL),
-        _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL),
-        _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL),
-        _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL),
-        _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL),
-        _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL),
-        _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL),
-        _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL),
-        _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL),
-        _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL),
-        _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap2430_pop_ball        NULL
-#endif
-
-int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
-{
-        struct omap_ball *package_balls = NULL;
-
-        switch (flags & OMAP_PACKAGE_MASK) {
-        case OMAP_PACKAGE_ZAC:
-                package_balls = omap2430_pop_ball;
-                break;
-        default:
-                pr_warning("%s: No ball data available for omap2420 package\n",
-                                __func__);
-        }
-
-        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
-                             OMAP2430_CONTROL_PADCONF_MUX_PBASE,
-                             OMAP2430_CONTROL_PADCONF_MUX_SIZE,
-                             omap2430_muxmodes, NULL, board_subset,
-                             package_balls);
-}
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
deleted file mode 100644
index 9fd93149ebd9..000000000000
--- a/arch/arm/mach-omap2/mux2430.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define OMAP2430_CONTROL_PADCONF_MUX_PBASE                      0x49002030LU
-
-#define OMAP2430_MUX(mode0, mux_value)                                  \
-{                                                                       \
-        .reg_offset     = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET),  \
-        .value          = (mux_value),                                  \
-}
-
-/*
- * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
- *
- * Extracted from the TRM.  Add 0x49002030 to these values to get the
- * absolute addresses.  The name in the macro is the mode-0 name of
- * the pin.  NOTE: These registers are 8-bits wide.
- *
- * Note that these defines use SDMMC instead of MMC for compatibility
- * with signal names used in 3630.
- */
-#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET                0x000
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET               0x001
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET               0x002
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET               0x003
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET               0x004
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET               0x005
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET               0x006
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET               0x007
-#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET               0x008
-#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET           0x009
-#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET            0x00a
-#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET                0x00b
-#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET           0x00c
-#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET               0x00d
-#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET                0x00e
-#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET              0x00f
-#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET              0x010
-#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET              0x011
-#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET              0x012
-#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET                0x013
-#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET               0x014
-#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET               0x015
-#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET               0x016
-#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET               0x017
-#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET               0x018
-#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET               0x019
-#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET               0x01a
-#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET                0x01b
-#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET                0x01c
-#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET                0x01d
-#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET                0x01e
-#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET                0x01f
-#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET               0x020
-#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET               0x021
-#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET               0x022
-#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET               0x023
-#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET                0x024
-#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET                0x025
-#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET                0x026
-#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET                0x027
-#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET                0x028
-#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET                0x029
-#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET                0x02a
-#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET                 0x02b
-#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET                 0x02c
-#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET                 0x02d
-#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET                 0x02e
-#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET                 0x02f
-#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET                 0x030
-#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET                 0x031
-#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET                 0x032
-#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET                 0x033
-#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET                 0x034
-#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET                0x035
-#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET                0x036
-#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET                0x037
-#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET                0x038
-#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET                0x039
-#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET                0x03a
-#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET                0x03b
-#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET                0x03c
-#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET                0x03d
-#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET                0x03e
-#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET                0x03f
-#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET                0x040
-#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET                0x041
-#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET                0x042
-#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET                0x043
-#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET                0x044
-#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET                0x045
-#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET                0x046
-#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET                0x047
-#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET                0x048
-#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET                0x049
-#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET                0x04a
-#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET                 0x04b
-#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET                 0x04c
-#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET                 0x04d
-#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET                 0x04e
-#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET                 0x04f
-#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET                 0x050
-#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET                 0x051
-#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET                 0x052
-#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET                 0x053
-#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET                 0x054
-#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET                0x055
-#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET                 0x056
-#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET                 0x057
-#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET                 0x058
-#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET                 0x059
-#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET                 0x05a
-#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET                 0x05b
-#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET                 0x05c
-#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET                 0x05d
-#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET                 0x05e
-#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET                0x05f
-#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET                0x060
-#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET                0x061
-#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET                0x062
-#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET                0x063
-#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET                0x064
-#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET                 0x065
-#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET                 0x066
-#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET                 0x067
-#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET                 0x068
-#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET                 0x069
-#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET                 0x06a
-#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET                 0x06b
-#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET                 0x06c
-#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET                 0x06d
-#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET                 0x06e
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET               0x06f
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET               0x070
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET               0x071
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET               0x072
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET               0x073
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET               0x074
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET               0x075
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET               0x076
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET               0x077
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET               0x078
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET              0x079
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET              0x07a
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET              0x07b
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET              0x07c
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET              0x07d
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET              0x07e
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET              0x07f
-#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET              0x080
-#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET               0x081
-#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET               0x082
-#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET                0x083
-#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET                0x084
-#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET               0x085
-#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET             0x086
-#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET                0x087
-#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET               0x088
-#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET               0x089
-#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET              0x08a
-#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET           0x08b
-#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET            0x08c
-#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET               0x08d
-#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET               0x08e
-#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET               0x08f
-#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET                0x090
-#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET                0x091
-#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET                0x092
-#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET                0x093
-#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET                 0x094
-#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET              0x095
-#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET             0x096
-#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET                0x097
-#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET              0x098
-#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET              0x099
-#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET                0x09a
-#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET                0x09b
-#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET               0x09c
-#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET               0x09d
-#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET              0x09e
-#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET                0x09f
-#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET               0x0a0
-#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET                0x0a1
-#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET                0x0a2
-#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET                0x0a3
-#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET                  0x0a4
-#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET                  0x0a5
-#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET                  0x0a6
-#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET                  0x0a7
-#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET                  0x0a8
-#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET                  0x0a9
-#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET                  0x0aa
-#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET                  0x0ab
-#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET                  0x0ac
-#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET                  0x0ad
-#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET                  0x0ae
-#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET                  0x0af
-#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET                0x0b0
-#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET                0x0b1
-#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET                 0x0b2
-#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET                 0x0b3
-#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET                0x0b4
-#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET                0x0b5
-#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET                0x0b6
-#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET                0x0b7
-#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET                0x0b8
-#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET                0x0b9
-#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET                0x0ba
-#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET                0x0bb
-#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET                0x0bc
-#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET                0x0bd
-#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET                0x0be
-#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET                0x0bf
-#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET                0x0c0
-#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET                0x0c1
-#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET                0x0c2
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET             0x0c3
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET              0x0c4
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET             0x0c5
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET             0x0c6
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET             0x0c7
-#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET             0x0c8
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET             0x0c9
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET             0x0ca
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET              0x0cb
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET             0x0cc
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET             0x0cd
-#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET             0x0ce
-#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET               0x0cf
-#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET               0x0d0
-#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET                0x0d1
-#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET                0x0d2
-#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET             0x0d3
-#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET              0x0d4
-#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET               0x0d5
-#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET               0x0d6
-#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET             0x0d7
-#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET            0x0d8
-#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET             0x0d9
-#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET             0x0da
-#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET                 0x0db
-#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET            0x0dc
-#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET             0x0dd
-#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET               0x0de
-#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET                0x0df
-#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET               0x0e0
-#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET               0x0e1
-#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET                0x0e2
-#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET                0x0e3
-#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET                0x0e4
-#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET                0x0e5
-#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET                0x0e6
-#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET               0x0e7
-#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET               0x0e8
-#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET                0x0e9
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET             0x0ea
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET              0x0eb
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET               0x0ec
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET               0x0ed
-#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET              0x0ee
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET              0x0ef
-#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET             0x0f0
-#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET                0x0f1
-#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET                0x0f2
-#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET                0x0f3
-#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET                0x0f4
-#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET                 0x0f5
-#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET          0x0f6
-#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET            0x0f7
-#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET           0x0f8
-#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET           0x0f9
-#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET                  0x0fa
-#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET                 0x0fb
-#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET                 0x0fc
-#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET                 0x0fd
-#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET                0x0fe
-#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET                0x0ff
-#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET                0x100
-#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET                0x101
-#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET         0x102
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET            0x103
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET            0x104
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET            0x105
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET            0x106
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET            0x107
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET            0x108
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET            0x109
-#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET              0x10a
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET              0x10b
-#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET              0x10c
-#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET              0x10d
-#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET            0x10e
-#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET                  0x10f
-#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET                 0x110
-#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET                 0x111
-#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET                  0x112
-#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET               0x113
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET               0x114
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET               0x115
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET               0x116
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET               0x117
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET               0x118
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET               0x119
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET               0x11a
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET               0x11b
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET               0x11c
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET               0x11d
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET              0x11e
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET              0x11f
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET              0x120
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET              0x121
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET              0x122
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET              0x123
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET              0x124
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET              0x125
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET              0x126
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET              0x127
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET              0x128
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET              0x129
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET              0x12a
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET              0x12b
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET              0x12c
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET              0x12d
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET              0x12e
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET              0x12f
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET              0x130
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET              0x131
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET              0x132
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET              0x133
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET              0x134
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET              0x135
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET              0x136
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET              0x137
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET              0x138
-#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET              0x139
-#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET              0x13a
-#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET              0x13b
-#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET           0x13c
-#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET             0x13d
-#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET             0x13e
-#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET            0x13f
-#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET                0x140
-#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET                0x141
-#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET              0x142
-#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET              0x143
-#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET              0x144
-#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET              0x145
-#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET              0x146
-#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET               0x147
-#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET               0x148
-#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET               0x149
-#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET               0x14a
-#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET              0x14b
-#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET               0x14c
-#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET               0x14d
-#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET              0x14e
-#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET              0x14f
-#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET              0x150
-#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET               0x151
-#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET              0x152
-#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET               0x153
-
-#define OMAP2430_CONTROL_PADCONF_MUX_SIZE                       \
-                (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index f991016e2a6a..667915d236f3 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -271,6 +271,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
         else
                 omap_pm_ops.finish_suspend(save_state);
 
+        if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
+                gic_dist_enable();
+
         /*
          * Restore the CPUx power state to ON otherwise CPUx
          * power domain can transitions to programmed low power
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 75e95d4fb448..17550aa39d0f 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -39,8 +39,6 @@
 
 #define OMAP5_CORE_COUNT        0x2
 
-u16 pm44xx_errata;
-
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -217,10 +215,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
         if (scu_base)
                 scu_enable(scu_base);
 
-        if (cpu_is_omap446x()) {
+        if (cpu_is_omap446x())
                 startup_addr = omap4460_secondary_startup;
-                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
-        }
 
         /*
          * Write the address of secondary startup routine into the
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c0ab9b26be3d..6cd3f3772ecf 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -87,7 +87,7 @@ void __init omap_barriers_init(void)
         dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
         dram_io_desc[0].pfn = __phys_to_pfn(paddr);
         dram_io_desc[0].length = size;
-        dram_io_desc[0].type = MT_MEMORY_SO;
+        dram_io_desc[0].type = MT_MEMORY_RW_SO;
         iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
         dram_sync = (void __iomem *) dram_io_desc[0].virtual;
         sram_sync = (void __iomem *) OMAP4_SRAM_VA;
@@ -127,6 +127,12 @@ void gic_dist_disable(void)
                 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
 }
 
+void gic_dist_enable(void)
+{
+        if (gic_dist_base_addr)
+                __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
+}
+
 bool gic_dist_disabled(void)
 {
         return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e0a398cf28d8..01ef59def44b 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -36,6 +36,7 @@
 #include <linux/of.h>
 #include <linux/notifier.h>
 
+#include "common.h"
 #include "soc.h"
 #include "omap_device.h"
 #include "omap_hwmod.h"
@@ -204,6 +205,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
         case BUS_NOTIFY_ADD_DEVICE:
                 if (pdev->dev.of_node)
                         omap_device_build_from_dt(pdev);
+                omap_auxdata_legacy_init(dev);
                 /* fall through */
         default:
                 od = to_omap_device(pdev);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8a1b5e0bad40..42d81885c700 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
         if (oh->clkdm) {
                 return oh->clkdm;
         } else if (oh->_clk) {
+                if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+                        return NULL;
                 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
                 return  clk->clkdm;
         }
@@ -1576,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
         if (!oh->clkdm) {
                 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
                         oh->name, oh->clkdm_name);
-                return -EINVAL;
+                return 0;
         }
 
         pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -2791,9 +2793,7 @@ static int __init _alloc_links(struct omap_hwmod_link **ml,
         sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
 
         *sl = NULL;
-        *ml = alloc_bootmem(sz);
-
-        memset(*ml, 0, sz);
+        *ml = memblock_virt_alloc(sz, 0);
 
         *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
 
@@ -2912,9 +2912,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
         pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
                  __func__, sz, max_ls);
 
-        linkspace = alloc_bootmem(sz);
-
-        memset(linkspace, 0, sz);
+        linkspace = memblock_virt_alloc(sz, 0);
 
         return 0;
 }
@@ -4235,6 +4233,7 @@ void __init omap_hwmod_init(void)
                 soc_ops.assert_hardreset = _omap2_assert_hardreset;
                 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
         } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
                 soc_ops.enable_module = _omap4_enable_module;
                 soc_ops.disable_module = _omap4_disable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d8b9d60f854f..2f15979c2e9c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 /* I2C1 */
 static struct omap_hwmod omap2420_i2c1_hwmod = {
         .name           = "i2c1",
-        .mpu_irqs       = omap2_i2c1_mpu_irqs,
-        .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2c1_fck",
         .prcm           = {
                 .omap2 = {
@@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
 /* I2C2 */
 static struct omap_hwmod omap2420_i2c2_hwmod = {
         .name           = "i2c2",
-        .mpu_irqs       = omap2_i2c2_mpu_irqs,
-        .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2c2_fck",
         .prcm           = {
                 .omap2 = {
@@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = {
         .info           = omap2420_mailbox_info,
 };
 
-static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
-        { .name = "iva", .irq = 34 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2420_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap2xxx_mailbox_hwmod_class,
-        .mpu_irqs       = omap2420_mailbox_irqs,
         .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
@@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 };
 
 /* mcbsp1 */
-static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        { .name = "tx", .irq = 59 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 60 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp1_irqs,
-        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
         .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
@@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 };
 
 /* mcbsp2 */
-static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-        { .name = "tx", .irq = 62 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 63 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp2_irqs,
-        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
@@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 };
 
 /* msdi1 */
-static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
-        { .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
-        { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap2420_msdi1_hwmod = {
         .name           = "msdi1",
         .class          = &omap2420_msdi_hwmod_class,
-        .mpu_irqs       = omap2420_msdi1_irqs,
-        .sdma_reqs      = omap2420_msdi1_sdma_reqs,
         .main_clk       = "mmc_fck",
         .prcm           = {
                 .omap2 = {
@@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = {
 /* HDQ1W/1-wire */
 static struct omap_hwmod omap2420_hdq1w_hwmod = {
         .name           = "hdq1w",
-        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
         .main_clk       = "hdq_fck",
         .prcm           = {
                 .omap2 = {
@@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_i2c1_hwmod,
         .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_i2c2_hwmod,
         .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
-        {
-                .pa_start       = 0x48028000,
-                .pa_end         = 0x48028000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_timer1_hwmod,
         .clk            = "gpt1_ick",
-        .addr           = omap2420_timer1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48022000,
-                .pa_end         = 0x4802207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_wd_timer2_hwmod,
         .clk            = "mpu_wdt_ick",
-        .addr           = omap2420_wd_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
-        {
-                .pa_start       = 0x48018000,
-                .pa_end         = 0x480181ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio1_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2420_gpio1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio2 */
-static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
-        {
-                .pa_start       = 0x4801a000,
-                .pa_end         = 0x4801a1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio2_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2420_gpio2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio3 */
-static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
-        {
-                .pa_start       = 0x4801c000,
-                .pa_end         = 0x4801c1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio3_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2420_gpio3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio4 */
-static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
-        {
-                .pa_start       = 0x4801e000,
-                .pa_end         = 0x4801e1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio4_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2420_gpio4_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mailbox_hwmod,
-        .addr           = omap2_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
-        .addr           = omap2_mcbsp1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
-        .addr           = omap2xxx_mcbsp2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c000 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 /* l4_core -> msdi1 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_msdi1_hwmod,
         .clk            = "mmc_ick",
-        .addr           = omap2420_msdi1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_hdq1w_hwmod,
         .clk            = "hdq_ick",
-        .addr           = omap2_hdq1w_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
 
 
 /* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x48004000,
-                .pa_end         = 0x4800401f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
-        {
-                .pa_start       = 0x6800a000,
-                .pa_end         = 0x6800afff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
         .clk            = "sync_32k_ick",
-        .addr           = omap2420_counter_32k_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
         .master         = &omap2xxx_l3_main_hwmod,
         .slave          = &omap2xxx_gpmc_hwmod,
         .clk            = "core_l3_ck",
-        .addr           = omap2420_gpmc_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 5b9083461dc5..6d1b60902179 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 static struct omap_hwmod omap2430_i2c1_hwmod = {
         .name           = "i2c1",
         .flags          = HWMOD_16BIT_REG,
-        .mpu_irqs       = omap2_i2c1_mpu_irqs,
-        .sdma_reqs      = omap2_i2c1_sdma_reqs,
         .main_clk       = "i2chs1_fck",
         .prcm           = {
                 .omap2 = {
@@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
 static struct omap_hwmod omap2430_i2c2_hwmod = {
         .name           = "i2c2",
         .flags          = HWMOD_16BIT_REG,
-        .mpu_irqs       = omap2_i2c2_mpu_irqs,
-        .sdma_reqs      = omap2_i2c2_sdma_reqs,
         .main_clk       = "i2chs2_fck",
         .prcm           = {
                 .omap2 = {
@@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
 };
 
 /* gpio5 */
-static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
-        { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_gpio5_hwmod = {
         .name           = "gpio5",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap243x_gpio5_irqs,
         .main_clk       = "gpio5_fck",
         .prcm           = {
                 .omap2 = {
@@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = {
         .info           = omap2430_mailbox_info,
 };
 
-static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
-        { .irq = 26 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap2xxx_mailbox_hwmod_class,
-        .mpu_irqs       = omap2430_mailbox_irqs,
         .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
@@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 };
 
 /* mcspi3 */
-static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
-        { .irq = 91 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
-        { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
-        { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
-        { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
-        { .dma_req = -1 }
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
         .num_chipselect = 2,
 };
 
 static struct omap_hwmod omap2430_mcspi3_hwmod = {
         .name           = "mcspi3",
-        .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
-        .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
         .main_clk       = "mcspi3_fck",
         .prcm           = {
                 .omap2 = {
@@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = {
 };
 
 /* usb_otg_hs */
-static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
-
-        { .name = "mc", .irq = 92 + OMAP_INTC_START, },
-        { .name = "dma", .irq = 93 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         .name           = "usb_otg_hs",
-        .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
         .main_clk       = "usbhs_ick",
         .prcm           = {
                 .omap2 = {
@@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 };
 
 /* mcbsp1 */
-static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
-        { .name = "tx",         .irq = 59 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 60 + OMAP_INTC_START, },
-        { .name = "ovr",        .irq = 61 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 64 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap2430_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2430_mcbsp1_irqs,
-        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
         .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
@@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
 };
 
 /* mcbsp2 */
-static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
-        { .name = "tx",         .irq = 62 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 63 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 16 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap2430_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2430_mcbsp2_irqs,
-        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
         .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
@@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
 };
 
 /* mcbsp3 */
-static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
-        { .name = "tx",         .irq = 89 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 90 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 17 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap2430_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2430_mcbsp3_irqs,
-        .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
         .main_clk       = "mcbsp3_fck",
         .prcm           = {
                 .omap2 = {
@@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
 };
 
 /* mcbsp4 */
-static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
-        { .name = "tx",         .irq = 54 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 55 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 18 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
-        { .name = "rx", .dma_req = 20 },
-        { .name = "tx", .dma_req = 19 },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap2430_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2430_mcbsp4_irqs,
-        .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
         .main_clk       = "mcbsp4_fck",
         .prcm           = {
                 .omap2 = {
@@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
 };
 
 /* mcbsp5 */
-static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
-        { .name = "tx",         .irq = 81 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 82 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 19 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
-        { .name = "rx", .dma_req = 22 },
-        { .name = "tx", .dma_req = 21 },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
         .name           = "mcbsp5",
         .class          = &omap2430_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2430_mcbsp5_irqs,
-        .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
         .main_clk       = "mcbsp5_fck",
         .prcm           = {
                 .omap2 = {
@@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 };
 
 /* MMC/SD/SDIO1 */
-static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
-        { .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
-        { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
         { .role = "dbck", .clk = "mmchsdb1_fck" },
 };
@@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
 static struct omap_hwmod omap2430_mmc1_hwmod = {
         .name           = "mmc1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2430_mmc1_mpu_irqs,
-        .sdma_reqs      = omap2430_mmc1_sdma_reqs,
         .opt_clks       = omap2430_mmc1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
         .main_clk       = "mmchs1_fck",
@@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
 };
 
 /* MMC/SD/SDIO2 */
-static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
-        { .irq = 86 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
-        { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
         { .role = "dbck", .clk = "mmchsdb2_fck" },
 };
@@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
 static struct omap_hwmod omap2430_mmc2_hwmod = {
         .name           = "mmc2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2430_mmc2_mpu_irqs,
-        .sdma_reqs      = omap2430_mmc2_sdma_reqs,
         .opt_clks       = omap2430_mmc2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
         .main_clk       = "mmchs2_fck",
@@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
 /* HDQ1W/1-wire */
 static struct omap_hwmod omap2430_hdq1w_hwmod = {
         .name           = "hdq1w",
-        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
         .main_clk       = "hdq_fck",
         .prcm           = {
                 .omap2 = {
@@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_i2c1_hwmod,
         .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_i2c2_hwmod,
         .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
-        {
-                .pa_start       = OMAP243X_HS_BASE,
-                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /*  l4_core ->usbhsotg  interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_usbhsotg_hwmod,
         .clk            = "usb_l4_ick",
-        .addr           = omap2430_usbhsotg_addrs,
         .user           = OCP_USER_MPU,
 };
 
@@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mmc1_hwmod,
         .clk            = "mmchs1_ick",
-        .addr           = omap2430_mmc1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mmc2_hwmod,
         .clk            = "mmchs2_ick",
-        .addr           = omap2430_mmc2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcspi3_hwmod,
         .clk            = "mcspi3_ick",
-        .addr           = omap2430_mcspi3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
-        {
-                .pa_start       = 0x49018000,
-                .pa_end         = 0x49018000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_timer1_hwmod,
         .clk            = "gpt1_ick",
-        .addr           = omap2430_timer1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x49016000,
-                .pa_end         = 0x4901607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_wd_timer2_hwmod,
         .clk            = "mpu_wdt_ick",
-        .addr           = omap2430_wd_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
-        {
-                .pa_start       = 0x4900C000,
-                .pa_end         = 0x4900C1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio1_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2430_gpio1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio2 */
-static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
-        {
-                .pa_start       = 0x4900E000,
-                .pa_end         = 0x4900E1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio2_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2430_gpio2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio3 */
-static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
-        {
-                .pa_start       = 0x49010000,
-                .pa_end         = 0x490101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio3_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2430_gpio3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_wkup -> gpio4 */
-static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
-        {
-                .pa_start       = 0x49012000,
-                .pa_end         = 0x490121ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_gpio4_hwmod,
         .clk            = "gpios_ick",
-        .addr           = omap2430_gpio4_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_core -> gpio5 */
-static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
-        {
-                .pa_start       = 0x480B6000,
-                .pa_end         = 0x480B61ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_gpio5_hwmod,
         .clk            = "gpio5_ick",
-        .addr           = omap2430_gpio5_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mailbox_hwmod,
-        .addr           = omap2_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
-        .addr           = omap2_mcbsp1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
-        .addr           = omap2xxx_mcbsp2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808C000,
-                .pa_end         = 0x4808C0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_core -> mcbsp3 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcbsp3_hwmod,
         .clk            = "mcbsp3_ick",
-        .addr           = omap2430_mcbsp3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808E000,
-                .pa_end         = 0x4808E0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_core -> mcbsp4 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcbsp4_hwmod,
         .clk            = "mcbsp4_ick",
-        .addr           = omap2430_mcbsp4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_core -> mcbsp5 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_mcbsp5_hwmod,
         .clk            = "mcbsp5_ick",
-        .addr           = omap2430_mcbsp5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2430_hdq1w_hwmod,
         .clk            = "hdq_ick",
-        .addr           = omap2_hdq1w_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
 
 /* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x49020000,
-                .pa_end         = 0x4902001f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
-        {
-                .pa_start       = 0x6e000000,
-                .pa_end         = 0x6e000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
         .clk            = "sync_32k_ick",
-        .addr           = omap2430_counter_32k_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
         .master         = &omap2xxx_l3_main_hwmod,
         .slave          = &omap2xxx_gpmc_hwmod,
         .clk            = "core_l3_ck",
-        .addr           = omap2430_gpmc_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5fd40d4a989e..656861c29d5c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -20,142 +20,6 @@
 
 #include "omap_hwmod_common_data.h"
 
-static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART1_BASE,
-                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART2_BASE,
-                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
-        {
-                .pa_start       = OMAP2_UART3_BASE,
-                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4802a000,
-                .pa_end         = 0x4802a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48078000,
-                .pa_end         = 0x48078000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x4807a000,
-                .pa_end         = 0x4807a000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x4807c000,
-                .pa_end         = 0x4807c000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4807e000,
-                .pa_end         = 0x4807e000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x48080000,
-                .pa_end         = 0x48080000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x48082000,
-                .pa_end         = 0x48082000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x48084000,
-                .pa_end         = 0x48084000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48076000,
-                .pa_end         = 0x480760ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
-        {
-                .pa_start       = 0x480a0000,
-                .pa_end         = 0x480a004f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
-        {
-                .pa_start       = 0x480a4000,
-                .pa_end         = 0x480a4000 + 0x64 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
-        {
-                .pa_start       = 0x480a6000,
-                .pa_end         = 0x480a6000 + 0x50 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /*
  * Common interconnect data
  */
@@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
                 .omap2 = {
                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
                         .flags  = OMAP_FIREWALL_L3,
-                }
+                },
         },
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_uart1_hwmod,
         .clk            = "uart1_ick",
-        .addr           = omap2xxx_uart1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_uart2_hwmod,
         .clk            = "uart2_ick",
-        .addr           = omap2xxx_uart2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_uart3_hwmod,
         .clk            = "uart3_ick",
-        .addr           = omap2xxx_uart3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_mcspi1_hwmod,
         .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_mcspi2_hwmod,
         .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer2_hwmod,
         .clk            = "gpt2_ick",
-        .addr           = omap2xxx_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer3_hwmod,
         .clk            = "gpt3_ick",
-        .addr           = omap2xxx_timer3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer4_hwmod,
         .clk            = "gpt4_ick",
-        .addr           = omap2xxx_timer4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer5_hwmod,
         .clk            = "gpt5_ick",
-        .addr           = omap2xxx_timer5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer6_hwmod,
         .clk            = "gpt6_ick",
-        .addr           = omap2xxx_timer6_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer7_hwmod,
         .clk            = "gpt7_ick",
-        .addr           = omap2xxx_timer7_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer8_hwmod,
         .clk            = "gpt8_ick",
-        .addr           = omap2xxx_timer8_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer9_hwmod,
         .clk            = "gpt9_ick",
-        .addr           = omap2xxx_timer9_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer10_hwmod,
         .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer11_hwmod,
         .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_timer12_hwmod,
         .clk            = "gpt12_ick",
-        .addr           = omap2xxx_timer12_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
                         .flags  = OMAP_FIREWALL_L4,
-                }
+                },
         },
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
                         .flags  = OMAP_FIREWALL_L4,
-                }
+                },
         },
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
                         .flags  = OMAP_FIREWALL_L4,
-                }
+                },
         },
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
                 .omap2 = {
                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
                         .flags  = OMAP_FIREWALL_L4,
-                }
+                },
         },
         .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_rng_hwmod,
         .clk            = "rng_ick",
-        .addr           = omap2_rng_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_sham_hwmod,
         .clk            = "sha_ick",
-        .addr           = omap2xxx_sham_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
         .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2xxx_aes_hwmod,
         .clk            = "aes_ick",
-        .addr           = omap2xxx_aes_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index d23c77fadb31..8821b9d6bae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,14 +20,9 @@
 #include "prm-regbits-24xx.h"
 #include "wd_timer.h"
 
-struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
-        { .irq = 48 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
         { .name = "dispc", .dma_req = 5 },
-        { .dma_req = -1 }
+        { .dma_req = -1, },
 };
 
 /*
@@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 };
 
 /* MPU */
-static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
-        { .name = "pmu", .irq = 3 + OMAP_INTC_START },
-        { .irq = -1 }
-};
-
 struct omap_hwmod omap2xxx_mpu_hwmod = {
         .name           = "mpu",
-        .mpu_irqs       = omap2xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
 };
@@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
         .name           = "timer1",
-        .mpu_irqs       = omap2_timer1_mpu_irqs,
         .main_clk       = "gpt1_fck",
         .prcm           = {
                 .omap2 = {
@@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
 
 struct omap_hwmod omap2xxx_timer2_hwmod = {
         .name           = "timer2",
-        .mpu_irqs       = omap2_timer2_mpu_irqs,
         .main_clk       = "gpt2_fck",
         .prcm           = {
                 .omap2 = {
@@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
 
 struct omap_hwmod omap2xxx_timer3_hwmod = {
         .name           = "timer3",
-        .mpu_irqs       = omap2_timer3_mpu_irqs,
         .main_clk       = "gpt3_fck",
         .prcm           = {
                 .omap2 = {
@@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
 
 struct omap_hwmod omap2xxx_timer4_hwmod = {
         .name           = "timer4",
-        .mpu_irqs       = omap2_timer4_mpu_irqs,
         .main_clk       = "gpt4_fck",
         .prcm           = {
                 .omap2 = {
@@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
 
 struct omap_hwmod omap2xxx_timer5_hwmod = {
         .name           = "timer5",
-        .mpu_irqs       = omap2_timer5_mpu_irqs,
         .main_clk       = "gpt5_fck",
         .prcm           = {
                 .omap2 = {
@@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
 
 struct omap_hwmod omap2xxx_timer6_hwmod = {
         .name           = "timer6",
-        .mpu_irqs       = omap2_timer6_mpu_irqs,
         .main_clk       = "gpt6_fck",
         .prcm           = {
                 .omap2 = {
@@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
 
 struct omap_hwmod omap2xxx_timer7_hwmod = {
         .name           = "timer7",
-        .mpu_irqs       = omap2_timer7_mpu_irqs,
         .main_clk       = "gpt7_fck",
         .prcm           = {
                 .omap2 = {
@@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
 
 struct omap_hwmod omap2xxx_timer8_hwmod = {
         .name           = "timer8",
-        .mpu_irqs       = omap2_timer8_mpu_irqs,
         .main_clk       = "gpt8_fck",
         .prcm           = {
                 .omap2 = {
@@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
 
 struct omap_hwmod omap2xxx_timer9_hwmod = {
         .name           = "timer9",
-        .mpu_irqs       = omap2_timer9_mpu_irqs,
         .main_clk       = "gpt9_fck",
         .prcm           = {
                 .omap2 = {
@@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
 
 struct omap_hwmod omap2xxx_timer10_hwmod = {
         .name           = "timer10",
-        .mpu_irqs       = omap2_timer10_mpu_irqs,
         .main_clk       = "gpt10_fck",
         .prcm           = {
                 .omap2 = {
@@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
 
 struct omap_hwmod omap2xxx_timer11_hwmod = {
         .name           = "timer11",
-        .mpu_irqs       = omap2_timer11_mpu_irqs,
         .main_clk       = "gpt11_fck",
         .prcm           = {
                 .omap2 = {
@@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
 
 struct omap_hwmod omap2xxx_timer12_hwmod = {
         .name           = "timer12",
-        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
         .main_clk       = "gpt12_fck",
         .prcm           = {
                 .omap2 = {
@@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 
 struct omap_hwmod omap2xxx_uart1_hwmod = {
         .name           = "uart1",
-        .mpu_irqs       = omap2_uart1_mpu_irqs,
-        .sdma_reqs      = omap2_uart1_sdma_reqs,
         .main_clk       = "uart1_fck",
         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
         .prcm           = {
@@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
 
 struct omap_hwmod omap2xxx_uart2_hwmod = {
         .name           = "uart2",
-        .mpu_irqs       = omap2_uart2_mpu_irqs,
-        .sdma_reqs      = omap2_uart2_sdma_reqs,
         .main_clk       = "uart2_fck",
         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
         .prcm           = {
@@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
 
 struct omap_hwmod omap2xxx_uart3_hwmod = {
         .name           = "uart3",
-        .mpu_irqs       = omap2_uart3_mpu_irqs,
-        .sdma_reqs      = omap2_uart3_sdma_reqs,
         .main_clk       = "uart3_fck",
         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
         .prcm           = {
@@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
                 },
         },
         .flags          = HWMOD_NO_IDLEST,
-        .dev_attr       = &omap2_3_dss_dispc_dev_attr
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 };
 
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
@@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 struct omap_hwmod omap2xxx_gpio1_hwmod = {
         .name           = "gpio1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio1_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
 struct omap_hwmod omap2xxx_gpio2_hwmod = {
         .name           = "gpio2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio2_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
 struct omap_hwmod omap2xxx_gpio3_hwmod = {
         .name           = "gpio3",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio3_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
 struct omap_hwmod omap2xxx_gpio4_hwmod = {
         .name           = "gpio4",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio4_irqs,
         .main_clk       = "gpios_fck",
         .prcm           = {
                 .omap2 = {
@@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 
 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
         .name           = "mcspi1",
-        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
         .main_clk       = "mcspi1_fck",
         .prcm           = {
                 .omap2 = {
@@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 
 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
         .name           = "mcspi2",
-        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
         .main_clk       = "mcspi2_fck",
         .prcm           = {
                 .omap2 = {
@@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 };
 
 /* gpmc */
-static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
-        { .irq = 20 + OMAP_INTC_START, },
-        { .irq = -1 }
-};
-
 struct omap_hwmod omap2xxx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &omap2xxx_gpmc_hwmod_class,
-        .mpu_irqs       = omap2xxx_gpmc_irqs,
         .main_clk       = "gpmc_fck",
         /*
          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
@@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
         .sysc           = &omap2_rng_sysc,
 };
 
-static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
-        { .irq = 52 + OMAP_INTC_START, },
-        { .irq = -1 }
-};
-
 struct omap_hwmod omap2xxx_rng_hwmod = {
         .name           = "rng",
-        .mpu_irqs       = omap2_rng_mpu_irqs,
         .main_clk       = "l4_ck",
         .prcm           = {
                 .omap2 = {
@@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = {
         .sysc   = &omap2_sham_sysc,
 };
 
-static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
-        { .irq = 51 + OMAP_INTC_START, },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
-        { .name = "rx", .dma_req = 13 },
-        { .dma_req = -1 }
-};
-
 struct omap_hwmod omap2xxx_sham_hwmod = {
         .name           = "sham",
-        .mpu_irqs       = omap2_sham_mpu_irqs,
-        .sdma_reqs      = omap2_sham_sdma_chs,
         .main_clk       = "l4_ck",
         .prcm           = {
                 .omap2 = {
@@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = {
         .sysc   = &omap2_aes_sysc,
 };
 
-static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
-        { .name = "tx", .dma_req = 9 },
-        { .name = "rx", .dma_req = 10 },
-        { .dma_req = -1 }
-};
-
 struct omap_hwmod omap2xxx_aes_hwmod = {
         .name           = "aes",
-        .sdma_reqs      = omap2_aes_sdma_chs,
         .main_clk       = "l4_ck",
         .prcm           = {
                 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 6e04ff7065e1..2c38c6b0ee03 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -18,9 +18,6 @@
 #include "common.h"
 #include "display.h"
 
-/* Common address space across OMAP2xxx */
-extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
-
 /* Common address space across OMAP2xxx/3xxx */
 extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
 extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
@@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
 extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
 
 /* Common IP block data across OMAP2xxx */
-extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
-extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
 extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
 extern struct omap_hwmod omap2xxx_l3_main_hwmod;
 extern struct omap_hwmod omap2xxx_l4_core_hwmod;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 39f020c982e8..3d5b24dcd9a4 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/clk.h>
+#include <linux/davinci_emac.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -16,6 +17,7 @@
 
 #include <linux/platform_data/pinctrl-single.h>
 
+#include "am35xx.h"
 #include "common.h"
 #include "common-board-devices.h"
 #include "dss-common.h"
@@ -26,6 +28,9 @@ struct pdata_init {
         void (*fn)(void);
 };
 
+struct of_dev_auxdata omap_auxdata_lookup[];
+static struct twl4030_gpio_platform_data twl_gpio_auxdata;
+
 /*
  * Create alias for USB host PHY clock.
  * Remove this when clock phandle can be provided via DT
@@ -68,6 +73,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock,
 }
 #endif
 
+#ifdef CONFIG_MACH_NOKIA_N8X0
+static void __init omap2420_n8x0_legacy_init(void)
+{
+        omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
+}
+#else
+#define omap2420_n8x0_legacy_init       NULL
+#endif
+
 #ifdef CONFIG_ARCH_OMAP3
 static void __init hsmmc2_internal_input_clk(void)
 {
@@ -78,6 +92,33 @@ static void __init hsmmc2_internal_input_clk(void)
         omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
 }
 
+static int omap3_sbc_t3730_twl_callback(struct device *dev,
+                                           unsigned gpio,
+                                           unsigned ngpio)
+{
+        int res;
+
+        res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
+                               "wlan rst");
+        if (res)
+                return res;
+
+        gpio_export(gpio, 0);
+
+        return 0;
+}
+
+static void __init omap3_sbc_t3730_twl_init(void)
+{
+        twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback;
+}
+
+static void __init omap3_sbc_t3730_legacy_init(void)
+{
+        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
+        omap_ads7846_init(1, 57, 0, NULL);
+}
+
 static void __init omap3_igep0020_legacy_init(void)
 {
         omap3_igep2_display_init_of();
@@ -92,6 +133,42 @@ static void __init omap3_zoom_legacy_init(void)
 {
         legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
 }
+
+static void am35xx_enable_emac_int(void)
+{
+        u32 v;
+
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+              AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
+}
+
+static void am35xx_disable_emac_int(void)
+{
+        u32 v;
+
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
+}
+
+static struct emac_platform_data am35xx_emac_pdata = {
+        .interrupt_enable       = am35xx_enable_emac_int,
+        .interrupt_disable      = am35xx_disable_emac_int,
+};
+
+static void __init am3517_evm_legacy_init(void)
+{
+        u32 v;
+
+        v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        v &= ~AM35XX_CPGMACSS_SW_RST;
+        omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
+        omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
+}
 #endif /* CONFIG_ARCH_OMAP3 */
 
 #ifdef CONFIG_ARCH_OMAP4
@@ -125,10 +202,48 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
         pcs_pdata.rearm = rearm;
 }
 
+/*
+ * GPIOs for TWL are initialized by the I2C bus and need custom
+ * handing until DSS has device tree bindings.
+ */
+void omap_auxdata_legacy_init(struct device *dev)
+{
+        if (dev->platform_data)
+                return;
+
+        if (strcmp("twl4030-gpio", dev_name(dev)))
+                return;
+
+        dev->platform_data = &twl_gpio_auxdata;
+}
+
+/*
+ * Few boards still need auxdata populated before we populate
+ * the dev entries in of_platform_populate().
+ */
+static struct pdata_init auxdata_quirks[] __initdata = {
+#ifdef CONFIG_SOC_OMAP2420
+        { "nokia,n800", omap2420_n8x0_legacy_init, },
+        { "nokia,n810", omap2420_n8x0_legacy_init, },
+        { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_twl_init, },
+#endif
+        { /* sentinel */ },
+};
+
 struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
+#ifdef CONFIG_MACH_NOKIA_N8X0
+        OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
+#endif
 #ifdef CONFIG_ARCH_OMAP3
         OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
         OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
+        /* Only on am3517 */
+        OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
+        OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
+                       &am35xx_emac_pdata),
 #endif
 #ifdef CONFIG_ARCH_OMAP4
         OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
@@ -137,14 +252,20 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
         { /* sentinel */ },
 };
 
+/*
+ * Few boards still need to initialize some legacy devices with
+ * platform data until the drivers support device tree.
+ */
 static struct pdata_init pdata_quirks[] __initdata = {
 #ifdef CONFIG_ARCH_OMAP3
+        { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
         { "nokia,omap3-n900", hsmmc2_internal_input_clk, },
         { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
         { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
         { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
         { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
         { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
+        { "ti,am3517-evm", am3517_evm_legacy_init, },
 #endif
 #ifdef CONFIG_ARCH_OMAP4
         { "ti,omap4-sdp", omap4_sdp_legacy_init, },
@@ -156,14 +277,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
         { /* sentinel */ },
 };
 
-void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
+static void pdata_quirks_check(struct pdata_init *quirks)
 {
-        struct pdata_init *quirks = pdata_quirks;
-
-        omap_sdrc_init(NULL, NULL);
-        of_platform_populate(NULL, omap_dt_match_table,
-                             omap_auxdata_lookup, NULL);
-
         while (quirks->compatible) {
                 if (of_machine_is_compatible(quirks->compatible)) {
                         if (quirks->fn)
@@ -173,3 +288,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
                 quirks++;
         }
 }
+
+void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
+{
+        omap_sdrc_init(NULL, NULL);
+        pdata_quirks_check(auxdata_quirks);
+        of_platform_populate(NULL, omap_dt_match_table,
+                             omap_auxdata_lookup, NULL);
+        pdata_quirks_check(pdata_quirks);
+}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 82f0698933d8..eefb30cfcabd 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -24,6 +24,8 @@
 #include "powerdomain.h"
 #include "pm.h"
 
+u16 pm44xx_errata;
+
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
@@ -199,6 +201,19 @@ static inline int omap4_init_static_deps(void)
 }
 
 /**
+ * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
+ *
+ * Initializes basic stuff for power management functionality.
+ */
+int __init omap4_pm_init_early(void)
+{
+        if (cpu_is_omap446x())
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+
+        return 0;
+}
+
+/**
  * omap4_pm_init - Init routine for OMAP4+ devices
  *
  * Initializes all powerdomain and clockdomain target states
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6667cf..623db40fdbbd 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
 # endif
 
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174ad1b6..b4c4ab9c8044 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 #include "soc.h"
 #include "prm2xxx_3xxx.h"
@@ -30,6 +34,7 @@
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "common.h"
+#include "clock.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
 
         return 0;
 }
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+        { .compatible = "ti,am3-prcm" },
+        { .compatible = "ti,am3-scrm" },
+        { .compatible = "ti,am4-prcm" },
+        { .compatible = "ti,am4-scrm" },
+        { .compatible = "ti,omap3-prm" },
+        { .compatible = "ti,omap3-cm" },
+        { .compatible = "ti,omap3-scrm" },
+        { .compatible = "ti,omap4-cm1" },
+        { .compatible = "ti,omap4-prm" },
+        { .compatible = "ti,omap4-cm2" },
+        { .compatible = "ti,omap4-scrm" },
+        { .compatible = "ti,omap5-prm" },
+        { .compatible = "ti,omap5-cm-core-aon" },
+        { .compatible = "ti,omap5-scrm" },
+        { .compatible = "ti,omap5-cm-core" },
+        { .compatible = "ti,dra7-prm" },
+        { .compatible = "ti,dra7-cm-core-aon" },
+        { .compatible = "ti,dra7-cm-core" },
+        { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+        .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(void __iomem *reg)
+{
+        return omap2_clk_readl(&memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, void __iomem *reg)
+{
+        omap2_clk_writel(val, &memmap_dummy_ck, reg);
+}
+
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+        .clk_readl = prm_clk_readl,
+        .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+        struct device_node *np;
+        void __iomem *mem;
+        int memmap_index = 0;
+
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+
+        for_each_matching_node(np, omap_prcm_dt_match_table) {
+                mem = of_iomap(np, 0);
+                clk_memmaps[memmap_index] = mem;
+                ti_dt_clk_init_provider(np, memmap_index);
+                memmap_index++;
+        }
+
+        ti_dt_clockdomains_setup();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0ada5e..74044aaf438b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -379,7 +379,7 @@ static struct clocksource clocksource_gpt = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static u32 notrace dmtimer_read_sched_clock(void)
+static u64 notrace dmtimer_read_sched_clock(void)
 {
         if (clksrc.reserved)
                 return __omap_dm_timer_read_counter(&clksrc,
@@ -471,7 +471,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
         __omap_dm_timer_load_start(&clksrc,
                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
                                    OMAP_TIMER_NONPOSTED);
-        setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
+        sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 
         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
                 pr_err("Could not register clocksource %s\n",
@@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
                                clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
+        omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
@@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void)			\
                                 clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
+        omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index b91002ca92f3..c134a826070a 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -21,7 +21,7 @@
 #include <plat/irq.h>
 #include "common.h"
 
-struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
+static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
         OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
                        NULL),
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 91a5852b44f3..3f1de1111e0f 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -24,7 +24,6 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
-#include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -135,7 +134,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 /*****************************************************************************
  * SPI
  ****************************************************************************/
-void __init orion5x_spi_init()
+void __init orion5x_spi_init(void)
 {
         orion_spi_init(SPI_PHYS_BASE);
 }
@@ -185,7 +184,7 @@ static void __init orion5x_crypto_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-void __init orion5x_wdt_init(void)
+static void __init orion5x_wdt_init(void)
 {
         orion_wdt_init();
 }
@@ -246,7 +245,7 @@ void orion5x_setup_wins(void)
 
 int orion5x_tclk;
 
-int __init orion5x_find_tclk(void)
+static int __init orion5x_find_tclk(void)
 {
         u32 dev, rev;
 
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4b2aefd1d961..dc01c4ffc9a8 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init);
  * PCI
  ****************************************************************************/
 
-void __init db88f5281_pci_preinit(void)
+static void __init db88f5281_pci_preinit(void)
 {
         int pin;
 
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 30a192b9c517..9654b0cc5892 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -16,6 +16,7 @@
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
+#include "common.h"
 
 static int __initdata gpio0_irqs[4] = {
         IRQ_ORION5X_GPIO_0_7,
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 7fab67053030..87a12d6930ff 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -240,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
                                  ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
                                  ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
-                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
                                  ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
                                  ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
-                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
 #define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index b1cf68493ffc..b576ef5f18a1 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -108,7 +108,7 @@ static struct platform_device rd88f5182_gpio_leds = {
  * PCI
  ****************************************************************************/
 
-void __init rd88f5182_pci_preinit(void)
+static void __init rd88f5182_pci_preinit(void)
 {
         int pin;
 
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 7e9064844698..6208d125c1b9 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = {
 #define TSP2_PCI_SLOT0_OFFS             7
 #define TSP2_PCI_SLOT0_IRQ_PIN          11
 
-void __init tsp2_pci_preinit(void)
+static void __init tsp2_pci_preinit(void)
 {
         int pin;
 
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e90c0618fdad..9136797addb2 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = {
 #define QNAP_TS209_PCI_SLOT0_IRQ_PIN    6
 #define QNAP_TS209_PCI_SLOT1_IRQ_PIN    7
 
-void __init qnap_ts209_pci_preinit(void)
+static void __init qnap_ts209_pci_preinit(void)
 {
         int pin;
 
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index e960855d32ac..db16dae441e2 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -57,7 +57,7 @@ static struct map_desc ts78xx_io_desc[] __initdata = {
         },
 };
 
-void __init ts78xx_map_io(void)
+static void __init ts78xx_map_io(void)
 {
         orion5x_map_io();
         iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 3dbcb1ab6e37..e358b0736dea 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -106,8 +106,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * "cpu" is Linux's internal ID.
          */
         pen_release = cpu_logical_map(cpu);
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 
         /*
          * Send the secondary CPU SEV, thereby causing the boot monitor to read
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index ffa6d811aad8..12fb0f4ae359 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -293,8 +293,7 @@ static int am200_setup_irq(struct fb_info *info)
         int ret;
 
         ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq,
-                                IRQF_DISABLED|IRQF_TRIGGER_FALLING,
-                                "AM200", info->par);
+                                IRQF_TRIGGER_FALLING, "AM200", info->par);
         if (ret)
                 dev_err(&am200_device->dev, "request_irq failed: %d\n", ret);
 
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index 3dfec1ec462d..c9f309ae88c5 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -241,8 +241,7 @@ static int am300_setup_irq(struct fb_info *info)
         struct broadsheetfb_par *par = info->par;
 
         ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq,
-                                IRQF_DISABLED|IRQF_TRIGGER_RISING,
-                                "AM300", par);
+                                IRQF_TRIGGER_RISING, "AM300", par);
         if (ret)
                 dev_err(&am300_device->dev, "request_irq failed: %d\n", ret);
 
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 8eb4e23c561d..6915a9f6b3a3 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -564,8 +564,7 @@ static int em_x270_mci_init(struct device *dev,
         }
 
         err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int,
-                              IRQF_DISABLED | IRQF_TRIGGER_RISING |
-                              IRQF_TRIGGER_FALLING,
+                              IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                               "MMC card detect", data);
         if (err) {
                 dev_err(dev, "can't request MMC card detect IRQ: %d\n", err);
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index b6cc1816463e..0eecd83c624e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -235,8 +235,6 @@ static const struct of_device_id intc_ids[] __initconst = {
 void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
 {
         struct device_node *node;
-        const struct of_device_id *of_id;
-        struct pxa_intc_conf *conf;
         struct resource res;
         int n, ret;
 
@@ -245,8 +243,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
                 pr_err("Failed to find interrupt controller in arch-pxa\n");
                 return;
         }
-        of_id = of_match_node(intc_ids, node);
-        conf = of_id->data;
 
         ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
                                    &pxa_internal_irq_nr);
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index fab30d666cc7..a9761c293028 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -634,7 +634,7 @@ static struct platform_device bq24022 = {
 static int magician_mci_init(struct device *dev,
                                 irq_handler_t detect_irq, void *data)
 {
-        return request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED,
+        return request_irq(IRQ_MAGICIAN_SD, detect_irq, 0,
                            "mmc card detect", data);
 }
 
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 08ccc0718f31..78b84c0dfc79 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -401,7 +401,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
          */
         MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
 
-        err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
+        err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, 0,
                              "MMC card detect", data);
         if (err)
                 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 9a4e470f162b..2897da2a5df6 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -327,7 +327,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
 {
         int err;
 
-        err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
+        err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0,
                              "MMC card detect", data);
         if (err)
                 printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 0a36d3585f26..051a6555cbf9 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -860,18 +860,18 @@ static int sharpsl_pm_probe(struct platform_device *pdev)
 
         /* Register interrupt handlers */
         irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin);
-        if (request_irq(irq, sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+        if (request_irq(irq, sharpsl_ac_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
                 dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
         }
 
         irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock);
-        if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+        if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
                 dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
         }
 
         if (sharpsl_pm.machinfo->gpio_fatal) {
                 irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal);
-                if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
                         dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                 }
         }
@@ -879,7 +879,7 @@ static int sharpsl_pm_probe(struct platform_device *pdev)
         if (sharpsl_pm.machinfo->batfull_irq) {
                 /* Register interrupt handler. */
                 irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull);
-                if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
                         dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                 }
         }
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 9aa852a8fab9..fca174e3865d 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -33,7 +33,7 @@
  * calls to sched_clock() which should always be the case in practice.
  */
 
-static u32 notrace pxa_read_sched_clock(void)
+static u64 notrace pxa_read_sched_clock(void)
 {
         return readl_relaxed(OSCR);
 }
@@ -137,7 +137,7 @@ static struct clock_event_device ckevt_pxa_osmr0 = {
 
 static struct irqaction pxa_ost0_irq = {
         .name           = "ost0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = pxa_ost0_interrupt,
         .dev_id         = &ckevt_pxa_osmr0,
 };
@@ -149,7 +149,7 @@ void __init pxa_timer_init(void)
         writel_relaxed(0, OIER);
         writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
-        setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
+        sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
 
         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index c58043462acd..872dcb20e757 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -332,8 +332,7 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int,
         int err;
 
         err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
-                          IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                          "MMC card detect", data);
+                          IRQF_TRIGGER_RISING, "MMC card detect", data);
         if (err) {
                 printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request"
                                                 "MMC card detect IRQ\n");
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 8f1d327e0cd1..d876431d64c0 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -180,27 +180,6 @@ config CPU_LLSERIAL_S3C2440
           Selected if there is an S3C2440 (or register compatible) serial
           low-level implementation needed
 
-# gpio configurations
-
-config S3C24XX_GPIO_EXTRA
-        int
-        default 128 if S3C24XX_GPIO_EXTRA128
-        default 64 if S3C24XX_GPIO_EXTRA64
-        default 16 if ARCH_H1940
-        default 0
-
-config S3C24XX_GPIO_EXTRA64
-        bool
-        help
-          Add an extra 64 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-
-config S3C24XX_GPIO_EXTRA128
-        bool
-        help
-          Add an extra 128 gpio numbers to the available GPIO pool. This is
-          available for boards that need extra gpios for external devices.
-
 config S3C24XX_PLL
         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
         depends on ARM_S3C24XX_CPUFREQ
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 404444dd3840..e9fbcc91c5c0 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -37,8 +37,8 @@
 #include <asm/irq.h>
 
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/leds-s3c24xx.h>
-
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index 4a65cba3295d..a8dafc174fe3 100644
--- a/arch/arm/mach-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -742,7 +742,7 @@ int s3c2410_dma_request(enum dma_ch channel,
                 chan->irq_claimed = 1;
                 local_irq_restore(flags);
 
-                err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
+                err = request_irq(chan->irq, s3c2410_dma_irq, 0,
                                   client->name, (void *)chan);
 
                 local_irq_save(flags);
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index 5b98bfd1df43..b4d14b864367 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -19,8 +19,10 @@
 #include <linux/gpio.h>
 #include <linux/rfkill.h>
 
+#include <plat/gpio-cfg.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include "h1940.h"
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h
index 14591563ca70..528fcdc4f63e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h
@@ -14,16 +14,8 @@
  * devices that need GPIO.
  */
 
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H __FILE__
-
-#ifdef CONFIG_CPU_S3C244X
-#define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
-#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
-#define ARCH_NR_GPIOS   (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
-#else
-#define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
-#endif
+#ifndef GPIO_SAMSUNG_S3C24XX_H
+#define GPIO_SAMSUNG_S3C24XX_H
 
 /*
  * GPIO sizes for various SoCs:
@@ -31,17 +23,17 @@
  *   2410 2412 2440 2443 2416
  *             2442
  *   ---- ---- ---- ---- ----
- * A  23   22   25   16   25
- * B  11   11   11   11   9
- * C  16   15   16   16   16
+ * A  23   22   25   16   27
+ * B  11   11   11   11   11
+ * C  16   16   16   16   16
  * D  16   16   16   16   16
  * E  16   16   16   16   16
  * F  8    8    8    8    8
  * G  16   16   16   16   8
- * H  11   11   9    15   15
+ * H  11   11   11   15   15
  * J  --   --   13   16   --
  * K  --   --   --   --   16
- * L  --   --   --   15   7
+ * L  --   --   --   15   14
  * M  --   --   --   2    2
  */
 
@@ -101,8 +93,6 @@ enum s3c_gpio_number {
 #define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
 #define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
 
-#include <plat/gpio-cfg.h>
-
 #ifdef CONFIG_CPU_S3C244X
 #define S3C_GPIO_END    (S3C2410_GPJ(0) + 32)
 #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
@@ -111,4 +101,4 @@ enum s3c_gpio_number {
 #define S3C_GPIO_END    (S3C2410_GPH(0) + 32)
 #endif
 
-#endif /* __MACH_GPIO_H */
+#endif /* GPIO_SAMSUNG_S3C24XX_H */
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index e27b5c91b3db..284ea1f44205 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -52,6 +52,7 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index c1fb6c37867f..2a16f8fb3584 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -35,6 +35,7 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 6dfeeb7ef469..6beab674c147 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -36,6 +36,7 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 22d6ae926d91..981ba1eb9fdc 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -48,6 +48,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 13d8d073675a..d9170e9f8ccd 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -75,6 +75,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-irq.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 952b6a040d1f..de0832181d8c 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -54,6 +54,7 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 43c23e220f5b..67cb8e948b7e 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -38,6 +38,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 #include <mach/fb.h>
+#include <mach/gpio-samsung.h>
 
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 4a18d49a63e0..1f1559713d8b 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -42,6 +42,7 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mmc-s3cmci.h>
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 2cb46c37c920..997684f17930 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -36,6 +36,7 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 01f4354206f9..575d28c9e6c6 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -37,6 +37,7 @@
 
 //#include <asm/debug-ll.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 #include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index 45e74363aaa9..33afb9190091 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -20,6 +20,7 @@
 #include <linux/i2c/tps65010.h>
 
 #include <plat/cpu-freq.h>
+#include <mach/gpio-samsung.h>
 
 #define OSIRIS_GPIO_DVS S3C2410_GPB(5)
 
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 58d6fbe5bf1f..f84f2a4c0c6d 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -50,6 +50,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include "common.h"
 #include "osiris.h"
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index f8feaeadb55a..b534b76812e3 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -54,6 +54,7 @@
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 034b7fe45c49..0a5456cda1bc 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -51,6 +51,7 @@
 #include <mach/fb.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -58,6 +59,7 @@
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
+#include <plat/gpio-cfg.h>
 
 #include "common.h"
 #include "h1940.h"
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 3bc6231d0a1f..b36edce8b2b8 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -43,6 +43,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index c9d31ef28dd1..f5bc721217e3 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -39,6 +39,7 @@
 
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/gpio-samsung.h>
 #include <mach/fb.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index f88e672ad1e4..12023cae4378 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -38,6 +38,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-s3c2443-clock.h>
+#include <mach/gpio-samsung.h>
 
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 42e7187fed60..755df489a45f 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -40,6 +40,7 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 2d82c4f116cd..20e481d8a33a 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -33,7 +33,9 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index caa5b7211380..052ca23393a7 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -39,6 +39,7 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-irq.h>
+#include <mach/gpio-samsung.h>
 
 #include <asm/mach/time.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 34676d1d5fec..ffb92cbca08c 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -30,6 +30,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 9ef3ccfbe196..8e01b4f2df35 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -42,6 +42,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 5f9d6569475d..03d379f1fc52 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -29,6 +29,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <asm/irq.h>
 
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 6819961f6b19..2c8adc028538 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -37,6 +37,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <linux/atomic.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index b6c71918b25c..886c2147062b 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -29,6 +29,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
index 7b4f33332d19..1852696ca16e 100644
--- a/arch/arm/mach-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c24xx/setup-i2c.c
@@ -19,6 +19,7 @@ struct platform_device;
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
index f65cb3ef16ce..c99b0f664db7 100644
--- a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 #include <plat/gpio-cfg.h>
 
 void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
index 4e11affce3a8..46466d20257e 100644
--- a/arch/arm/mach-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c24xx/setup-ts.c
@@ -15,7 +15,9 @@
 
 struct platform_device; /* don't need the contents */
 
+#include <plat/gpio-cfg.h>
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 
 /**
  * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index 2ed2e32430dc..b70aa66efebe 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -29,6 +29,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio-samsung.h>
 #include <asm/irq.h>
 
 #include <linux/platform_data/usb-ohci-s3c2410.h>
@@ -78,8 +79,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
 
         if (on) {
                 ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
-                                  IRQF_DISABLED | IRQF_TRIGGER_RISING |
-                                   IRQF_TRIGGER_FALLING,
+                                  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                   "USB Over-current", info);
                 if (ret != 0) {
                         printk(KERN_ERR "failed to request usb oc irq\n");
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2cb8dc55b50e..64f04e6f9c31 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,9 +17,10 @@ config CPU_S3C6410
         help
           Enable S3C6410 CPU support
 
-config S3C64XX_DMA
-        bool "S3C64XX DMA"
-        select S3C_DMA
+config S3C64XX_PL080
+        bool "S3C64XX DMA using generic PL08x driver"
+        select AMBA_PL08X
+        select SAMSUNG_DMADEV
 
 config S3C64XX_SETUP_SDHCI
         bool
@@ -192,7 +193,6 @@ config SMDK6410_WM1190_EV1
         select MFD_WM8350_I2C
         select REGULATOR
         select REGULATOR_WM8350
-        select SAMSUNG_GPIO_EXTRA64
         help
           The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
           and audio daughtercard for the Samsung SMDK6410 reference
@@ -208,7 +208,6 @@ config SMDK6410_WM1192_EV1
         select MFD_WM831X_I2C
         select REGULATOR
         select REGULATOR_WM831X
-        select SAMSUNG_GPIO_EXTRA64
         help
           The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC
           daughtercard for the Samsung SMDK6410 reference platform.
@@ -294,7 +293,6 @@ config MACH_WLF_CRAGG_6410
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
-        select SAMSUNG_GPIO_EXTRA128
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
 
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 6faedcffce04..58069a702a43 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 
 # DMA support
 
-obj-$(CONFIG_S3C64XX_DMA)       += dma.o
+obj-$(CONFIG_S3C64XX_PL080)     += pl080.o
 
 # Device support
 
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 7a3ce4c39e5f..76ab595d849b 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -41,6 +41,7 @@
 #include <mach/map.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index bd3bd562011e..7043e7a3a67e 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void);
 static inline int s3c64xx_pm_late_initcall(void) { return 0; }
 #endif
 
+#ifdef CONFIG_S3C64XX_PL080
+extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
+extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/crag6410.h b/arch/arm/mach-s3c64xx/crag6410.h
index 4c3c9994fc2c..7bc66682687e 100644
--- a/arch/arm/mach-s3c64xx/crag6410.h
+++ b/arch/arm/mach-s3c64xx/crag6410.h
@@ -11,7 +11,7 @@
 #ifndef MACH_CRAG6410_H
 #define MACH_CRAG6410_H
 
-#include <linux/gpio.h>
+#include <mach/gpio-samsung.h>
 
 #define GLENFARCLAS_PMIC_IRQ_BASE       IRQ_BOARD_START
 
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index e367e87bbc29..ff780a8d8366 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -22,6 +22,7 @@
 #include <plat/devs.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
deleted file mode 100644
index 7e22c2113816..000000000000
--- a/arch/arm/mach-s3c64xx/dma.c
+++ /dev/null
@@ -1,762 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/dma.c
- *
- * Copyright 2009 Openmoko, Inc.
- * Copyright 2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX DMA core
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/*
- * NOTE: Code in this file is not used when booting with Device Tree support.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/dmapool.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/amba/pl080.h>
-#include <linux/of.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include "regs-sys.h"
-
-/* dma channel state information */
-
-struct s3c64xx_dmac {
-        struct device           dev;
-        struct clk              *clk;
-        void __iomem            *regs;
-        struct s3c2410_dma_chan *channels;
-        enum dma_ch              chanbase;
-};
-
-/* pool to provide LLI buffers */
-static struct dma_pool *dma_pool;
-
-/* Debug configuration and code */
-
-static unsigned char debug_show_buffs = 0;
-
-static void dbg_showchan(struct s3c2410_dma_chan *chan)
-{
-        pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
-                 chan->number,
-                 readl(chan->regs + PL080_CH_SRC_ADDR),
-                 readl(chan->regs + PL080_CH_DST_ADDR),
-                 readl(chan->regs + PL080_CH_LLI),
-                 readl(chan->regs + PL080_CH_CONTROL),
-                 readl(chan->regs + PL080S_CH_CONTROL2),
-                 readl(chan->regs + PL080S_CH_CONFIG));
-}
-
-static void show_lli(struct pl080s_lli *lli)
-{
-        pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
-                 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
-                 lli->control0, lli->control1);
-}
-
-static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
-{
-        struct s3c64xx_dma_buff *ptr;
-        struct s3c64xx_dma_buff *end;
-
-        pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
-                 chan->number, chan->next, chan->curr, chan->end);
-
-        ptr = chan->next;
-        end = chan->end;
-
-        if (debug_show_buffs) {
-                for (; ptr != NULL; ptr = ptr->next) {
-                        pr_debug("DMA%d: %08x ",
-                                 chan->number, ptr->lli_dma);
-                        show_lli(ptr->lli);
-                }
-        }
-}
-
-/* End of Debug */
-
-static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
-{
-        struct s3c2410_dma_chan *chan;
-        unsigned int start, offs;
-
-        start = 0;
-
-        if (channel >= DMACH_PCM1_TX)
-                start = 8;
-
-        for (offs = 0; offs < 8; offs++) {
-                chan = &s3c2410_chans[start + offs];
-                if (!chan->in_use)
-                        goto found;
-        }
-
-        return NULL;
-
-found:
-        s3c_dma_chan_map[channel] = chan;
-        return chan;
-}
-
-int s3c2410_dma_config(enum dma_ch channel, int xferunit)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-
-        if (chan == NULL)
-                return -EINVAL;
-
-        switch (xferunit) {
-        case 1:
-                chan->hw_width = 0;
-                break;
-        case 2:
-                chan->hw_width = 1;
-                break;
-        case 4:
-                chan->hw_width = 2;
-                break;
-        default:
-                printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_config);
-
-static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
-                                 struct pl080s_lli *lli,
-                                 dma_addr_t data, int size)
-{
-        dma_addr_t src, dst;
-        u32 control0, control1;
-
-        switch (chan->source) {
-        case DMA_FROM_DEVICE:
-                src = chan->dev_addr;
-                dst = data;
-                control0 = PL080_CONTROL_SRC_AHB2;
-                control0 |= PL080_CONTROL_DST_INCR;
-                break;
-
-        case DMA_TO_DEVICE:
-                src = data;
-                dst = chan->dev_addr;
-                control0 = PL080_CONTROL_DST_AHB2;
-                control0 |= PL080_CONTROL_SRC_INCR;
-                break;
-        default:
-                BUG();
-        }
-
-        /* note, we do not currently setup any of the burst controls */
-
-        control1 = size >> chan->hw_width;      /* size in no of xfers */
-        control0 |= PL080_CONTROL_PROT_SYS;     /* always in priv. mode */
-        control0 |= PL080_CONTROL_TC_IRQ_EN;    /* always fire IRQ */
-        control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
-        control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
-
-        lli->src_addr = src;
-        lli->dst_addr = dst;
-        lli->next_lli = 0;
-        lli->control0 = control0;
-        lli->control1 = control1;
-}
-
-static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
-                                struct pl080s_lli *lli)
-{
-        void __iomem *regs = chan->regs;
-
-        pr_debug("%s: LLI %p => regs\n", __func__, lli);
-        show_lli(lli);
-
-        writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
-        writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
-        writel(lli->next_lli, regs + PL080_CH_LLI);
-        writel(lli->control0, regs + PL080_CH_CONTROL);
-        writel(lli->control1, regs + PL080S_CH_CONTROL2);
-}
-
-static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
-{
-        struct s3c64xx_dmac *dmac = chan->dmac;
-        u32 config;
-        u32 bit = chan->bit;
-
-        dbg_showchan(chan);
-
-        pr_debug("%s: clearing interrupts\n", __func__);
-
-        /* clear interrupts */
-        writel(bit, dmac->regs + PL080_TC_CLEAR);
-        writel(bit, dmac->regs + PL080_ERR_CLEAR);
-
-        pr_debug("%s: starting channel\n", __func__);
-
-        config = readl(chan->regs + PL080S_CH_CONFIG);
-        config |= PL080_CONFIG_ENABLE;
-        config &= ~PL080_CONFIG_HALT;
-
-        pr_debug("%s: writing config %08x\n", __func__, config);
-        writel(config, chan->regs + PL080S_CH_CONFIG);
-
-        return 0;
-}
-
-static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
-{
-        u32 config;
-        int timeout;
-
-        pr_debug("%s: stopping channel\n", __func__);
-
-        dbg_showchan(chan);
-
-        config = readl(chan->regs + PL080S_CH_CONFIG);
-        config |= PL080_CONFIG_HALT;
-        writel(config, chan->regs + PL080S_CH_CONFIG);
-
-        timeout = 1000;
-        do {
-                config = readl(chan->regs + PL080S_CH_CONFIG);
-                pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
-                if (config & PL080_CONFIG_ACTIVE)
-                        udelay(10);
-                else
-                        break;
-                } while (--timeout > 0);
-
-        if (config & PL080_CONFIG_ACTIVE) {
-                printk(KERN_ERR "%s: channel still active\n", __func__);
-                return -EFAULT;
-        }
-
-        config = readl(chan->regs + PL080S_CH_CONFIG);
-        config &= ~PL080_CONFIG_ENABLE;
-        writel(config, chan->regs + PL080S_CH_CONFIG);
-
-        return 0;
-}
-
-static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
-                                         struct s3c64xx_dma_buff *buf,
-                                         enum s3c2410_dma_buffresult result)
-{
-        if (chan->callback_fn != NULL)
-                (chan->callback_fn)(chan, buf->pw, 0, result);
-}
-
-static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
-{
-        dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
-        kfree(buff);
-}
-
-static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
-{
-        struct s3c64xx_dma_buff *buff, *next;
-        u32 config;
-
-        dbg_showchan(chan);
-
-        pr_debug("%s: flushing channel\n", __func__);
-
-        config = readl(chan->regs + PL080S_CH_CONFIG);
-        config &= ~PL080_CONFIG_ENABLE;
-        writel(config, chan->regs + PL080S_CH_CONFIG);
-
-        /* dump all the buffers associated with this channel */
-
-        for (buff = chan->curr; buff != NULL; buff = next) {
-                next = buff->next;
-                pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
-
-                s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
-                s3c64xx_dma_freebuff(buff);
-        }
-
-        chan->curr = chan->next = chan->end = NULL;
-
-        return 0;
-}
-
-int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-
-        WARN_ON(!chan);
-        if (!chan)
-                return -EINVAL;
-
-        switch (op) {
-        case S3C2410_DMAOP_START:
-                return s3c64xx_dma_start(chan);
-
-        case S3C2410_DMAOP_STOP:
-                return s3c64xx_dma_stop(chan);
-
-        case S3C2410_DMAOP_FLUSH:
-                return s3c64xx_dma_flush(chan);
-
-        /* believe PAUSE/RESUME are no-ops */
-        case S3C2410_DMAOP_PAUSE:
-        case S3C2410_DMAOP_RESUME:
-        case S3C2410_DMAOP_STARTED:
-        case S3C2410_DMAOP_TIMEOUT:
-                return 0;
-        }
-
-        return -ENOENT;
-}
-EXPORT_SYMBOL(s3c2410_dma_ctrl);
-
-/* s3c2410_dma_enque
- *
- */
-
-int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
-                        dma_addr_t data, int size)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-        struct s3c64xx_dma_buff *next;
-        struct s3c64xx_dma_buff *buff;
-        struct pl080s_lli *lli;
-        unsigned long flags;
-        int ret;
-
-        WARN_ON(!chan);
-        if (!chan)
-                return -EINVAL;
-
-        buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC);
-        if (!buff) {
-                printk(KERN_ERR "%s: no memory for buffer\n", __func__);
-                return -ENOMEM;
-        }
-
-        lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma);
-        if (!lli) {
-                printk(KERN_ERR "%s: no memory for lli\n", __func__);
-                ret = -ENOMEM;
-                goto err_buff;
-        }
-
-        pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
-                 __func__, buff, data, lli, (u32)buff->lli_dma, size);
-
-        buff->lli = lli;
-        buff->pw = id;
-
-        s3c64xx_dma_fill_lli(chan, lli, data, size);
-
-        local_irq_save(flags);
-
-        if ((next = chan->next) != NULL) {
-                struct s3c64xx_dma_buff *end = chan->end;
-                struct pl080s_lli *endlli = end->lli;
-
-                pr_debug("enquing onto channel\n");
-
-                end->next = buff;
-                endlli->next_lli = buff->lli_dma;
-
-                if (chan->flags & S3C2410_DMAF_CIRCULAR) {
-                        struct s3c64xx_dma_buff *curr = chan->curr;
-                        lli->next_lli = curr->lli_dma;
-                }
-
-                if (next == chan->curr) {
-                        writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
-                        chan->next = buff;
-                }
-
-                show_lli(endlli);
-                chan->end = buff;
-        } else {
-                pr_debug("enquing onto empty channel\n");
-
-                chan->curr = buff;
-                chan->next = buff;
-                chan->end = buff;
-
-                s3c64xx_lli_to_regs(chan, lli);
-        }
-
-        local_irq_restore(flags);
-
-        show_lli(lli);
-
-        dbg_showchan(chan);
-        dbg_showbuffs(chan);
-        return 0;
-
-err_buff:
-        kfree(buff);
-        return ret;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_enqueue);
-
-
-int s3c2410_dma_devconfig(enum dma_ch channel,
-                          enum dma_data_direction source,
-                          unsigned long devaddr)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-        u32 peripheral;
-        u32 config = 0;
-
-        pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
-                 __func__, channel, source, devaddr, chan);
-
-        WARN_ON(!chan);
-        if (!chan)
-                return -EINVAL;
-
-        peripheral = (chan->peripheral & 0xf);
-        chan->source = source;
-        chan->dev_addr = devaddr;
-
-        pr_debug("%s: peripheral %d\n", __func__, peripheral);
-
-        switch (source) {
-        case DMA_FROM_DEVICE:
-                config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
-                config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
-                break;
-        case DMA_TO_DEVICE:
-                config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
-                config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
-                break;
-        default:
-                printk(KERN_ERR "%s: bad source\n", __func__);
-                return -EINVAL;
-        }
-
-        /* allow TC and ERR interrupts */
-        config |= PL080_CONFIG_TC_IRQ_MASK;
-        config |= PL080_CONFIG_ERR_IRQ_MASK;
-
-        pr_debug("%s: config %08x\n", __func__, config);
-
-        writel(config, chan->regs + PL080S_CH_CONFIG);
-
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_devconfig);
-
-
-int s3c2410_dma_getposition(enum dma_ch channel,
-                            dma_addr_t *src, dma_addr_t *dst)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-
-        WARN_ON(!chan);
-        if (!chan)
-                return -EINVAL;
-
-        if (src != NULL)
-                *src = readl(chan->regs + PL080_CH_SRC_ADDR);
-
-        if (dst != NULL)
-                *dst = readl(chan->regs + PL080_CH_DST_ADDR);
-
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_getposition);
-
-/* s3c2410_request_dma
- *
- * get control of an dma channel
-*/
-
-int s3c2410_dma_request(enum dma_ch channel,
-                        struct s3c2410_dma_client *client,
-                        void *dev)
-{
-        struct s3c2410_dma_chan *chan;
-        unsigned long flags;
-
-        pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
-                 channel, client->name, dev);
-
-        local_irq_save(flags);
-
-        chan = s3c64xx_dma_map_channel(channel);
-        if (chan == NULL) {
-                local_irq_restore(flags);
-                return -EBUSY;
-        }
-
-        dbg_showchan(chan);
-
-        chan->client = client;
-        chan->in_use = 1;
-        chan->peripheral = channel;
-        chan->flags = 0;
-
-        local_irq_restore(flags);
-
-        /* need to setup */
-
-        pr_debug("%s: channel initialised, %p\n", __func__, chan);
-
-        return chan->number | DMACH_LOW_LEVEL;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_request);
-
-/* s3c2410_dma_free
- *
- * release the given channel back to the system, will stop and flush
- * any outstanding transfers, and ensure the channel is ready for the
- * next claimant.
- *
- * Note, although a warning is currently printed if the freeing client
- * info is not the same as the registrant's client info, the free is still
- * allowed to go through.
-*/
-
-int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
-{
-        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-        unsigned long flags;
-
-        if (chan == NULL)
-                return -EINVAL;
-
-        local_irq_save(flags);
-
-        if (chan->client != client) {
-                printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
-                       channel, chan->client, client);
-        }
-
-        /* sort out stopping and freeing the channel */
-
-
-        chan->client = NULL;
-        chan->in_use = 0;
-
-        if (!(channel & DMACH_LOW_LEVEL))
-                s3c_dma_chan_map[channel] = NULL;
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_dma_free);
-
-static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
-{
-        struct s3c64xx_dmac *dmac = pw;
-        struct s3c2410_dma_chan *chan;
-        enum s3c2410_dma_buffresult res;
-        u32 tcstat, errstat;
-        u32 bit;
-        int offs;
-
-        tcstat = readl(dmac->regs + PL080_TC_STATUS);
-        errstat = readl(dmac->regs + PL080_ERR_STATUS);
-
-        for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
-                struct s3c64xx_dma_buff *buff;
-
-                if (!(errstat & bit) && !(tcstat & bit))
-                        continue;
-
-                chan = dmac->channels + offs;
-                res = S3C2410_RES_ERR;
-
-                if (tcstat & bit) {
-                        writel(bit, dmac->regs + PL080_TC_CLEAR);
-                        res = S3C2410_RES_OK;
-                }
-
-                if (errstat & bit)
-                        writel(bit, dmac->regs + PL080_ERR_CLEAR);
-
-                /* 'next' points to the buffer that is next to the
-                 * currently active buffer.
-                 * For CIRCULAR queues, 'next' will be same as 'curr'
-                 * when 'end' is the active buffer.
-                 */
-                buff = chan->curr;
-                while (buff && buff != chan->next
-                                && buff->next != chan->next)
-                        buff = buff->next;
-
-                if (!buff)
-                        BUG();
-
-                if (buff == chan->next)
-                        buff = chan->end;
-
-                s3c64xx_dma_bufffdone(chan, buff, res);
-
-                /* Free the node and update curr, if non-circular queue */
-                if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) {
-                        chan->curr = buff->next;
-                        s3c64xx_dma_freebuff(buff);
-                }
-
-                /* Update 'next' */
-                buff = chan->next;
-                if (chan->next == chan->end) {
-                        chan->next = chan->curr;
-                        if (!(chan->flags & S3C2410_DMAF_CIRCULAR))
-                                chan->end = NULL;
-                } else {
-                        chan->next = buff->next;
-                }
-        }
-
-        return IRQ_HANDLED;
-}
-
-static struct bus_type dma_subsys = {
-        .name           = "s3c64xx-dma",
-        .dev_name       = "s3c64xx-dma",
-};
-
-static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
-                             int irq, unsigned int base)
-{
-        struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
-        struct s3c64xx_dmac *dmac;
-        char clkname[16];
-        void __iomem *regs;
-        void __iomem *regptr;
-        int err, ch;
-
-        dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
-        if (!dmac) {
-                printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
-                return -ENOMEM;
-        }
-
-        dmac->dev.id = chno / 8;
-        dmac->dev.bus = &dma_subsys;
-
-        err = device_register(&dmac->dev);
-        if (err) {
-                printk(KERN_ERR "%s: failed to register device\n", __func__);
-                goto err_alloc;
-        }
-
-        regs = ioremap(base, 0x200);
-        if (!regs) {
-                printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
-                err = -ENXIO;
-                goto err_dev;
-        }
-
-        snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id);
-
-        dmac->clk = clk_get(NULL, clkname);
-        if (IS_ERR(dmac->clk)) {
-                printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
-                err = PTR_ERR(dmac->clk);
-                goto err_map;
-        }
-
-        clk_prepare_enable(dmac->clk);
-
-        dmac->regs = regs;
-        dmac->chanbase = chbase;
-        dmac->channels = chptr;
-
-        err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
-        if (err < 0) {
-                printk(KERN_ERR "%s: failed to get irq\n", __func__);
-                goto err_clk;
-        }
-
-        regptr = regs + PL080_Cx_BASE(0);
-
-        for (ch = 0; ch < 8; ch++, chptr++) {
-                pr_debug("%s: registering DMA %d (%p)\n",
-                         __func__, chno + ch, regptr);
-
-                chptr->bit = 1 << ch;
-                chptr->number = chno + ch;
-                chptr->dmac = dmac;
-                chptr->regs = regptr;
-                regptr += PL080_Cx_STRIDE;
-        }
-
-        /* for the moment, permanently enable the controller */
-        writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
-
-        printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
-               irq, regs, chno, chno+8);
-
-        return 0;
-
-err_clk:
-        clk_disable_unprepare(dmac->clk);
-        clk_put(dmac->clk);
-err_map:
-        iounmap(regs);
-err_dev:
-        device_unregister(&dmac->dev);
-err_alloc:
-        kfree(dmac);
-        return err;
-}
-
-static int __init s3c64xx_dma_init(void)
-{
-        int ret;
-
-        /* This driver is not supported when booting with device tree. */
-        if (of_have_populated_dt())
-                return -ENODEV;
-
-        printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
-
-        dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
-        if (!dma_pool) {
-                printk(KERN_ERR "%s: failed to create pool\n", __func__);
-                return -ENOMEM;
-        }
-
-        ret = subsys_system_register(&dma_subsys, NULL);
-        if (ret) {
-                printk(KERN_ERR "%s: failed to create subsys\n", __func__);
-                return -ENOMEM;
-        }
-
-        /* Set all DMA configuration to be DMA, not SDMA */
-        writel(0xffffff, S3C64XX_SDMA_SEL);
-
-        /* Register standard DMA controllers */
-        s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
-        s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
-
-        return 0;
-}
-
-arch_initcall(s3c64xx_dma_init);
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98cf0e4c..059b1fc85037 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -11,51 +11,48 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
-#define S3C_DMA_CHANNELS        (16)
+#define S3C64XX_DMA_CHAN(name)          ((unsigned long)(name))
+
+/* DMA0/SDMA0 */
+#define DMACH_UART0             S3C64XX_DMA_CHAN("uart0_tx")
+#define DMACH_UART0_SRC2        S3C64XX_DMA_CHAN("uart0_rx")
+#define DMACH_UART1             S3C64XX_DMA_CHAN("uart1_tx")
+#define DMACH_UART1_SRC2        S3C64XX_DMA_CHAN("uart1_rx")
+#define DMACH_UART2             S3C64XX_DMA_CHAN("uart2_tx")
+#define DMACH_UART2_SRC2        S3C64XX_DMA_CHAN("uart2_rx")
+#define DMACH_UART3             S3C64XX_DMA_CHAN("uart3_tx")
+#define DMACH_UART3_SRC2        S3C64XX_DMA_CHAN("uart3_rx")
+#define DMACH_PCM0_TX           S3C64XX_DMA_CHAN("pcm0_tx")
+#define DMACH_PCM0_RX           S3C64XX_DMA_CHAN("pcm0_rx")
+#define DMACH_I2S0_OUT          S3C64XX_DMA_CHAN("i2s0_tx")
+#define DMACH_I2S0_IN           S3C64XX_DMA_CHAN("i2s0_rx")
+#define DMACH_SPI0_TX           S3C64XX_DMA_CHAN("spi0_tx")
+#define DMACH_SPI0_RX           S3C64XX_DMA_CHAN("spi0_rx")
+#define DMACH_HSI_I2SV40_TX     S3C64XX_DMA_CHAN("i2s2_tx")
+#define DMACH_HSI_I2SV40_RX     S3C64XX_DMA_CHAN("i2s2_rx")
+
+/* DMA1/SDMA1 */
+#define DMACH_PCM1_TX           S3C64XX_DMA_CHAN("pcm1_tx")
+#define DMACH_PCM1_RX           S3C64XX_DMA_CHAN("pcm1_rx")
+#define DMACH_I2S1_OUT          S3C64XX_DMA_CHAN("i2s1_tx")
+#define DMACH_I2S1_IN           S3C64XX_DMA_CHAN("i2s1_rx")
+#define DMACH_SPI1_TX           S3C64XX_DMA_CHAN("spi1_tx")
+#define DMACH_SPI1_RX           S3C64XX_DMA_CHAN("spi1_rx")
+#define DMACH_AC97_PCMOUT       S3C64XX_DMA_CHAN("ac97_out")
+#define DMACH_AC97_PCMIN        S3C64XX_DMA_CHAN("ac97_in")
+#define DMACH_AC97_MICIN        S3C64XX_DMA_CHAN("ac97_mic")
+#define DMACH_PWM               S3C64XX_DMA_CHAN("pwm")
+#define DMACH_IRDA              S3C64XX_DMA_CHAN("irda")
+#define DMACH_EXTERNAL          S3C64XX_DMA_CHAN("external")
+#define DMACH_SECURITY_RX       S3C64XX_DMA_CHAN("sec_rx")
+#define DMACH_SECURITY_TX       S3C64XX_DMA_CHAN("sec_tx")
 
-/* see mach-s3c2410/dma.h for notes on dma channel numbers */
-
-/* Note, for the S3C64XX architecture we keep the DMACH_
- * defines in the order they are allocated to [S]DMA0/[S]DMA1
- * so that is easy to do DHACH_ -> DMA controller conversion
- */
 enum dma_ch {
-        /* DMA0/SDMA0 */
-        DMACH_UART0 = 0,
-        DMACH_UART0_SRC2,
-        DMACH_UART1,
-        DMACH_UART1_SRC2,
-        DMACH_UART2,
-        DMACH_UART2_SRC2,
-        DMACH_UART3,
-        DMACH_UART3_SRC2,
-        DMACH_PCM0_TX,
-        DMACH_PCM0_RX,
-        DMACH_I2S0_OUT,
-        DMACH_I2S0_IN,
-        DMACH_SPI0_TX,
-        DMACH_SPI0_RX,
-        DMACH_HSI_I2SV40_TX,
-        DMACH_HSI_I2SV40_RX,
+        DMACH_MAX = 32
+};
 
-        /* DMA1/SDMA1 */
-        DMACH_PCM1_TX = 16,
-        DMACH_PCM1_RX,
-        DMACH_I2S1_OUT,
-        DMACH_I2S1_IN,
-        DMACH_SPI1_TX,
-        DMACH_SPI1_RX,
-        DMACH_AC97_PCMOUT,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_MICIN,
-        DMACH_PWM,
-        DMACH_IRDA,
-        DMACH_EXTERNAL,
-        DMACH_RES1,
-        DMACH_RES2,
-        DMACH_SECURITY_RX,      /* SDMA1 only */
-        DMACH_SECURITY_TX,      /* SDMA1 only */
-        DMACH_MAX               /* the end */
+struct s3c2410_dma_client {
+        char    *name;
 };
 
 static inline bool samsung_dma_has_circular(void)
@@ -65,67 +62,10 @@ static inline bool samsung_dma_has_circular(void)
 
 static inline bool samsung_dma_is_dmadev(void)
 {
-        return false;
+        return true;
 }
-#define S3C2410_DMAF_CIRCULAR           (1 << 0)
-
-#include <plat/dma.h>
-
-#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
-
-struct s3c64xx_dma_buff;
-
-/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
- * @next: Pointer to next buffer in queue or ring.
- * @pw: Client provided identifier
- * @lli: Pointer to hardware descriptor this buffer is associated with.
- * @lli_dma: Hardare address of the descriptor.
- */
-struct s3c64xx_dma_buff {
-        struct s3c64xx_dma_buff *next;
-
-        void                    *pw;
-        struct pl080s_lli       *lli;
-        dma_addr_t               lli_dma;
-};
-
-struct s3c64xx_dmac;
-
-struct s3c2410_dma_chan {
-        unsigned char            number;      /* number of this dma channel */
-        unsigned char            in_use;      /* channel allocated */
-        unsigned char            bit;         /* bit for enable/disable/etc */
-        unsigned char            hw_width;
-        unsigned char            peripheral;
-
-        unsigned int             flags;
-        enum dma_data_direction  source;
-
-
-        dma_addr_t              dev_addr;
-
-        struct s3c2410_dma_client *client;
-        struct s3c64xx_dmac     *dmac;          /* pointer to controller */
-
-        void __iomem            *regs;
-
-        /* cdriver callbacks */
-        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
-        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
-
-        /* buffer list and information */
-        struct s3c64xx_dma_buff *curr;          /* current dma buffer */
-        struct s3c64xx_dma_buff *next;          /* next buffer to load */
-        struct s3c64xx_dma_buff *end;           /* end of queue */
-
-        /* note, when channel is running in circular mode, curr is the
-         * first buffer enqueued, end is the last and curr is where the
-         * last buffer-done event is set-at. The buffers are not freed
-         * and the last buffer hardware descriptor points back to the
-         * first.
-         */
-};
 
-#include <plat/dma-core.h>
+#include <linux/amba/pl08x.h>
+#include <plat/dma-ops.h>
 
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h
index 8b540c42d5dd..9c81fac3b2d5 100644
--- a/arch/arm/mach-s3c64xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c6400/include/mach/gpio.h
- *
+/*
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
@@ -12,6 +11,9 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef GPIO_SAMSUNG_S3C64XX_H
+#define GPIO_SAMSUNG_S3C64XX_H
+
 /* GPIO bank sizes */
 #define S3C64XX_GPIO_A_NR       (8)
 #define S3C64XX_GPIO_B_NR       (7)
@@ -88,6 +90,5 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the GPQ() range */
 #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
 
-#define BOARD_NR_GPIOS  (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
+#endif /* GPIO_SAMSUNG_S3C64XX_H */
 
-#define ARCH_NR_GPIOS   (GPIO_BOARD_START + BOARD_NR_GPIOS)
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index d266dd5f7060..ddeb0e51a962 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 #include <plat/samsung-time.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 758e31b26550..3df3c372ee1f 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -48,8 +48,8 @@
 #include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
-
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/regs-serial.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 614a03a92cf7..0431016925b9 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -35,6 +35,7 @@
 
 #include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/gpio-samsung.h>
 #include <plat/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 58d46a3d7b78..8d553a418e1c 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -30,13 +30,16 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/mmc-sdhci-s3c.h>
 #include <plat/regs-serial.h>
+#include <plat/sdhci.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
@@ -214,6 +217,13 @@ static struct platform_device mini6410_lcd_powerdev = {
         .dev.platform_data      = &mini6410_lcd_power_data,
 };
 
+static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
+        .max_width              = 4,
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S3C64XX_GPN(10),
+        .ext_cd_gpio_invert     = true,
+};
+
 static struct platform_device *mini6410_devices[] __initdata = {
         &mini6410_device_eth,
         &s3c_device_hsmmc0,
@@ -321,6 +331,7 @@ static void __init mini6410_machine_init(void)
 
         s3c_nand_set_platdata(&mini6410_nand_info);
         s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
+        s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
         s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 8bed37b3d5ac..5152026f0e19 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -31,6 +31,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/adc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index a6b338fd0470..6e72bd5c1d0c 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -25,6 +25,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -106,7 +107,7 @@ static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on)
 
         if (on) {
                 ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)),
-                                  smartq_usb_host_ocirq, IRQF_DISABLED |
+                                  smartq_usb_host_ocirq,
                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                   "USB host overcurrent", info);
                 if (ret != 0)
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 8aca5daf3d05..dec4c08e834f 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -23,6 +23,7 @@
 #include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index a052e107c0b4..27b322069c7d 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -23,6 +23,7 @@
 #include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 27381cfcabbe..150f55fb9e33 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <mach/gpio-samsung.h>
 #include <plat/samsung-time.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d5ea938cc9a1..43261d24a0a5 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -57,6 +57,7 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c
new file mode 100644
index 000000000000..901a984bddc2
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/pl080.c
@@ -0,0 +1,244 @@
+/*
+ * Samsung's S3C64XX generic DMA support using amba-pl08x driver.
+ *
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl080.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include "regs-sys.h"
+
+static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
+{
+        return cd->min_signal;
+}
+
+static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch)
+{
+}
+
+/*
+ * DMA0
+ */
+
+static struct pl08x_channel_data s3c64xx_dma0_info[] = {
+        {
+                .bus_id = "uart0_tx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart0_rx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "pcm0_tx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "pcm0_rx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s0_tx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s0_rx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "spi0_tx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "spi0_rx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s2_tx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s2_rx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .periph_buses = PL08X_AHB2,
+        }
+};
+
+struct pl08x_platform_data s3c64xx_dma0_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl_memcpy =
+                        (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
+                        PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_xfer_signal = pl08x_get_xfer_signal,
+        .put_xfer_signal = pl08x_put_xfer_signal,
+        .slave_channels = s3c64xx_dma0_info,
+        .num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0,
+                        0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
+
+/*
+ * DMA1
+ */
+
+static struct pl08x_channel_data s3c64xx_dma1_info[] = {
+        {
+                .bus_id = "pcm1_tx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "pcm1_rx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s1_tx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s1_rx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "spi1_tx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "spi1_rx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ac97_out",
+                .min_signal = 6,
+                .max_signal = 6,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ac97_in",
+                .min_signal = 7,
+                .max_signal = 7,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ac97_mic",
+                .min_signal = 8,
+                .max_signal = 8,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "pwm",
+                .min_signal = 9,
+                .max_signal = 9,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 10,
+                .max_signal = 10,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "external",
+                .min_signal = 11,
+                .max_signal = 11,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+
+struct pl08x_platform_data s3c64xx_dma1_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl_memcpy =
+                        (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
+                        PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_xfer_signal = pl08x_get_xfer_signal,
+        .put_xfer_signal = pl08x_put_xfer_signal,
+        .slave_channels = s3c64xx_dma1_info,
+        .num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0,
+                        0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
+
+static int __init s3c64xx_pl080_init(void)
+{
+        /* Set all DMA configuration to be DMA, not SDMA */
+        writel(0xffffff, S3C64XX_SDMA_SEL);
+
+        if (of_have_populated_dt())
+                return 0;
+
+        amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
+        amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
+
+        return 0;
+}
+arch_initcall(s3c64xx_pl080_init);
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 8cdb824a3b43..b5a66986a529 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -28,6 +28,7 @@
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
+#include <mach/gpio-samsung.h>
 
 #include "regs-gpio-memport.h"
 #include "regs-modem.h"
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 2cf80026c58d..9d17bff12d4d 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -19,6 +19,7 @@
 
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c64xx_fb_gpio_setup_24bpp(void)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c
index 40666ba8d607..4b8c1cfdd1fc 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c0.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c0.c
@@ -20,6 +20,7 @@ struct platform_device; /* don't need the contents */
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c
index 3fdb24c4e62a..cd1df71ee13b 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c1.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c1.c
@@ -20,6 +20,7 @@ struct platform_device; /* don't need the contents */
 
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
index 648d8b85bf6b..689fb72e715c 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -17,6 +17,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 #include <linux/platform_data/ata-samsung_cf.h>
 
 void s3c64xx_ide_setup_gpio(void)
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
index 1d4d0ee9e870..6ad9a89dfddf 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -13,6 +13,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/keypad.h>
+#include <mach/gpio-samsung.h>
 
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
index 6eac071afae2..f426b7a16c16 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
@@ -20,6 +20,7 @@
 
 #include <plat/gpio-cfg.h>
 #include <plat/sdhci.h>
+#include <mach/gpio-samsung.h>
 
 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index 4dc53450d715..5fd1a315c901 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -10,6 +10,7 @@
 
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
 int s3c64xx_spi0_cfg_gpio(void)
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index c9808c684152..8443a27bca2f 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -75,12 +75,143 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
 
 EXPORT_SYMBOL(ASSABET_BCR_frob);
 
+/*
+ * The codec reset goes to three devices, so we need to release
+ * the rest when any one of these requests it.  However, that
+ * causes the ADV7171 to consume around 100mA - more than half
+ * the LCD-blanked power.
+ *
+ * With the ADV7171, LCD and backlight enabled, we go over
+ * budget on the MAX846 Li-Ion charger, and if no Li-Ion battery
+ * is connected, the Assabet crashes.
+ */
+#define RST_UCB1X00 (1 << 0)
+#define RST_UDA1341 (1 << 1)
+#define RST_ADV7171 (1 << 2)
+
+#define SDA GPIO_GPIO(15)
+#define SCK GPIO_GPIO(18)
+#define MOD GPIO_GPIO(17)
+
+static void adv7171_start(void)
+{
+        GPSR = SCK;
+        udelay(1);
+        GPSR = SDA;
+        udelay(2);
+        GPCR = SDA;
+}
+
+static void adv7171_stop(void)
+{
+        GPSR = SCK;
+        udelay(2);
+        GPSR = SDA;
+        udelay(1);
+}
+
+static void adv7171_send(unsigned byte)
+{
+        unsigned i;
+
+        for (i = 0; i < 8; i++, byte <<= 1) {
+                GPCR = SCK;
+                udelay(1);
+                if (byte & 0x80)
+                        GPSR = SDA;
+                else
+                        GPCR = SDA;
+                udelay(1);
+                GPSR = SCK;
+                udelay(1);
+        }
+        GPCR = SCK;
+        udelay(1);
+        GPSR = SDA;
+        udelay(1);
+        GPDR &= ~SDA;
+        GPSR = SCK;
+        udelay(1);
+        if (GPLR & SDA)
+                printk(KERN_WARNING "No ACK from ADV7171\n");
+        udelay(1);
+        GPCR = SCK | SDA;
+        udelay(1);
+        GPDR |= SDA;
+        udelay(1);
+}
+
+static void adv7171_write(unsigned reg, unsigned val)
+{
+        unsigned gpdr = GPDR;
+        unsigned gplr = GPLR;
+
+        ASSABET_BCR = BCR_value | ASSABET_BCR_AUDIO_ON;
+        udelay(100);
+
+        GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */
+        GPDR = (GPDR | SCK | MOD) & ~SDA;
+        udelay(10);
+        if (!(GPLR & SDA))
+                printk(KERN_WARNING "Something dragging SDA down?\n");
+        GPDR |= SDA;
+
+        adv7171_start();
+        adv7171_send(0x54);
+        adv7171_send(reg);
+        adv7171_send(val);
+        adv7171_stop();
+
+        /* Restore GPIO state for L3 bus */
+        GPSR = gplr & (SDA | SCK | MOD);
+        GPCR = (~gplr) & (SDA | SCK | MOD);
+        GPDR = gpdr;
+}
+
+static void adv7171_sleep(void)
+{
+        /* Put the ADV7171 into sleep mode */
+        adv7171_write(0x04, 0x40);
+}
+
+static unsigned codec_nreset;
+
+static void assabet_codec_reset(unsigned mask, int set)
+{
+        unsigned long flags;
+        bool old;
+
+        local_irq_save(flags);
+        old = !codec_nreset;
+        if (set)
+                codec_nreset &= ~mask;
+        else
+                codec_nreset |= mask;
+
+        if (old != !codec_nreset) {
+                if (codec_nreset) {
+                        ASSABET_BCR_set(ASSABET_BCR_NCODEC_RST);
+                        adv7171_sleep();
+                } else {
+                        ASSABET_BCR_clear(ASSABET_BCR_NCODEC_RST);
+                }
+        }
+        local_irq_restore(flags);
+}
+
 static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
 {
-        if (state == UCB_RST_PROBE)
-                ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
+        int set = state == UCB_RST_REMOVE || state == UCB_RST_SUSPEND ||
+                state == UCB_RST_PROBE_FAIL;
+        assabet_codec_reset(RST_UCB1X00, set);
 }
 
+void assabet_uda1341_reset(int set)
+{
+        assabet_codec_reset(RST_UDA1341, set);
+}
+EXPORT_SYMBOL(assabet_uda1341_reset);
+
 
 /*
  * Assabet flash support code.
@@ -155,12 +286,9 @@ static int assabet_irda_set_power(struct device *dev, unsigned int state)
                 0
         };
 
-        if (state < 4) {
-                state = bcr_state[state];
-                ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1|
-                                           ASSABET_BCR_IRDA_MD0));
-                ASSABET_BCR_set(state);
-        }
+        if (state < 4)
+                ASSABET_BCR_frob(ASSABET_BCR_IRDA_MD1 | ASSABET_BCR_IRDA_MD0,
+                                 bcr_state[state]);
         return 0;
 }
 
@@ -180,6 +308,7 @@ static struct irda_platform_data assabet_irda_data = {
 static struct ucb1x00_plat_data assabet_ucb1x00_data = {
         .reset          = assabet_ucb1x00_reset,
         .gpio_base      = -1,
+        .can_wakeup     = 1,
 };
 
 static struct mcp_plat_data assabet_mcp_data = {
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index 172ebd0ee0a2..9fa6a990cf03 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -33,6 +33,13 @@ struct clk clk_##_name = {				\
 
 static DEFINE_SPINLOCK(clocks_lock);
 
+/* Dummy clk routine to build generic kernel parts that may be using them */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
 static void clk_gpio27_enable(struct clk *clk)
 {
         /*
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 7fb96ebdc0fb..831a15824ec8 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -27,6 +27,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/timer.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/pda_power.h>
 
@@ -242,10 +244,43 @@ struct platform_device collie_locomo_device = {
         .resource       = locomo_resources,
 };
 
+static struct gpio_keys_button collie_gpio_keys[] = {
+        {
+                .type   = EV_PWR,
+                .code   = KEY_RESERVED,
+                .gpio   = COLLIE_GPIO_ON_KEY,
+                .desc   = "On key",
+                .wakeup = 1,
+                .active_low = 1,
+        },
+        {
+                .type   = EV_PWR,
+                .code   = KEY_WAKEUP,
+                .gpio   = COLLIE_GPIO_WAKEUP,
+                .desc   = "Sync",
+                .wakeup = 1,
+                .active_low = 1,
+        },
+};
+
+static struct gpio_keys_platform_data collie_gpio_keys_data = {
+        .buttons        = collie_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(collie_gpio_keys),
+};
+
+static struct platform_device collie_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &collie_gpio_keys_data,
+        },
+};
+
 static struct platform_device *devices[] __initdata = {
         &collie_locomo_device,
         &colliescoop_device,
         &collie_power_device,
+        &collie_gpio_keys_device,
 };
 
 static struct mtd_partition collie_partitions[] = {
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index b8f2b151539b..daa27c474c13 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -28,15 +28,35 @@
 /*
  * helper for sa1100fb
  */
+static struct gpio h3100_lcd_gpio[] = {
+        { H3100_GPIO_LCD_3V_ON, GPIOF_OUT_INIT_LOW, "LCD 3V" },
+        { H3XXX_EGPIO_LCD_ON, GPIOF_OUT_INIT_LOW, "LCD ON" },
+};
+
+static bool h3100_lcd_request(void)
+{
+        static bool h3100_lcd_ok;
+        int rc;
+
+        if (h3100_lcd_ok)
+                return true;
+
+        rc = gpio_request_array(h3100_lcd_gpio, ARRAY_SIZE(h3100_lcd_gpio));
+        if (rc)
+                pr_err("%s: can't request GPIOs\n", __func__);
+        else
+                h3100_lcd_ok = true;
+
+        return h3100_lcd_ok;
+}
+
 static void h3100_lcd_power(int enable)
 {
-        if (!gpio_request(H3XXX_EGPIO_LCD_ON, "LCD ON")) {
-                gpio_set_value(H3100_GPIO_LCD_3V_ON, enable);
-                gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
-                gpio_free(H3XXX_EGPIO_LCD_ON);
-        } else {
-                pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
-        }
+        if (!h3100_lcd_request())
+                return;
+
+        gpio_set_value(H3100_GPIO_LCD_3V_ON, enable);
+        gpio_set_value(H3XXX_EGPIO_LCD_ON, enable);
 }
 
 static struct sa1100fb_mach_info h3100_lcd_info = {
@@ -69,6 +89,11 @@ static void __init h3100_map_io(void)
 /*
  * This turns the IRDA power on or off on the Compaq H3100
  */
+static struct gpio h3100_irda_gpio[] = {
+        { H3100_GPIO_IR_ON,     GPIOF_OUT_INIT_LOW, "IrDA power" },
+        { H3100_GPIO_IR_FSEL,   GPIOF_OUT_INIT_LOW, "IrDA fsel" },
+};
+
 static int h3100_irda_set_power(struct device *dev, unsigned int state)
 {
         gpio_set_value(H3100_GPIO_IR_ON, state);
@@ -80,18 +105,27 @@ static void h3100_irda_set_speed(struct device *dev, unsigned int speed)
         gpio_set_value(H3100_GPIO_IR_FSEL, !(speed < 4000000));
 }
 
+static int h3100_irda_startup(struct device *dev)
+{
+        return gpio_request_array(h3100_irda_gpio, sizeof(h3100_irda_gpio));
+}
+
+static void h3100_irda_shutdown(struct device *dev)
+{
+        return gpio_free_array(h3100_irda_gpio, sizeof(h3100_irda_gpio));
+}
+
 static struct irda_platform_data h3100_irda_data = {
         .set_power      = h3100_irda_set_power,
         .set_speed      = h3100_irda_set_speed,
+        .startup        = h3100_irda_startup,
+        .shutdown       = h3100_irda_shutdown,
 };
 
 static struct gpio_default_state h3100_default_gpio[] = {
-        { H3100_GPIO_IR_ON,     GPIO_MODE_OUT0, "IrDA power" },
-        { H3100_GPIO_IR_FSEL,   GPIO_MODE_OUT0, "IrDA fsel" },
         { H3XXX_GPIO_COM_DCD,   GPIO_MODE_IN,   "COM DCD" },
         { H3XXX_GPIO_COM_CTS,   GPIO_MODE_IN,   "COM CTS" },
         { H3XXX_GPIO_COM_RTS,   GPIO_MODE_OUT0, "COM RTS" },
-        { H3100_GPIO_LCD_3V_ON, GPIO_MODE_OUT0, "LCD 3v" },
 };
 
 static void __init h3100_mach_init(void)
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index b8dc5bd22623..a663e7230141 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -28,35 +28,39 @@
 /*
  * helper for sa1100fb
  */
+static struct gpio h3600_lcd_gpio[] = {
+        { H3XXX_EGPIO_LCD_ON,   GPIOF_OUT_INIT_LOW,     "LCD power" },
+        { H3600_EGPIO_LCD_PCI,  GPIOF_OUT_INIT_LOW,     "LCD control" },
+        { H3600_EGPIO_LCD_5V_ON, GPIOF_OUT_INIT_LOW,    "LCD 5v" },
+        { H3600_EGPIO_LVDD_ON,  GPIOF_OUT_INIT_LOW,     "LCD 9v/-6.5v" },
+};
+
+static bool h3600_lcd_request(void)
+{
+        static bool h3600_lcd_ok;
+        int rc;
+
+        if (h3600_lcd_ok)
+                return true;
+
+        rc = gpio_request_array(h3600_lcd_gpio, ARRAY_SIZE(h3600_lcd_gpio));
+        if (rc)
+                pr_err("%s: can't request GPIOs\n", __func__);
+        else
+                h3600_lcd_ok = true;
+
+        return h3600_lcd_ok;
+}
+
 static void h3600_lcd_power(int enable)
 {
-        if (gpio_request(H3XXX_EGPIO_LCD_ON, "LCD power")) {
-                pr_err("%s: can't request H3XXX_EGPIO_LCD_ON\n", __func__);
-                goto err1;
-        }
-        if (gpio_request(H3600_EGPIO_LCD_PCI, "LCD control")) {
-                pr_err("%s: can't request H3XXX_EGPIO_LCD_PCI\n", __func__);
-                goto err2;
-        }
-        if (gpio_request(H3600_EGPIO_LCD_5V_ON, "LCD 5v")) {
-                pr_err("%s: can't request H3XXX_EGPIO_LCD_5V_ON\n", __func__);
-                goto err3;
-        }
-        if (gpio_request(H3600_EGPIO_LVDD_ON, "LCD 9v/-6.5v")) {
-                pr_err("%s: can't request H3600_EGPIO_LVDD_ON\n", __func__);
-                goto err4;
-        }
+        if (!h3600_lcd_request())
+                return;
 
         gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
         gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
         gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
         gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
-
-        gpio_free(H3600_EGPIO_LVDD_ON);
-err4:   gpio_free(H3600_EGPIO_LCD_5V_ON);
-err3:   gpio_free(H3600_EGPIO_LCD_PCI);
-err2:   gpio_free(H3XXX_EGPIO_LCD_ON);
-err1:   return;
 }
 
 static const struct sa1100fb_rgb h3600_rgb_16 = {
@@ -93,6 +97,11 @@ static void __init h3600_map_io(void)
 /*
  * This turns the IRDA power on or off on the Compaq H3600
  */
+static struct gpio h3600_irda_gpio[] = {
+        { H3600_EGPIO_IR_ON,    GPIOF_OUT_INIT_LOW, "IrDA power" },
+        { H3600_EGPIO_IR_FSEL,  GPIOF_OUT_INIT_LOW, "IrDA fsel" },
+};
+
 static int h3600_irda_set_power(struct device *dev, unsigned int state)
 {
         gpio_set_value(H3600_EGPIO_IR_ON, state);
@@ -106,29 +115,12 @@ static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
 
 static int h3600_irda_startup(struct device *dev)
 {
-        int err = gpio_request(H3600_EGPIO_IR_ON, "IrDA power");
-        if (err)
-                goto err1;
-        err = gpio_direction_output(H3600_EGPIO_IR_ON, 0);
-        if (err)
-                goto err2;
-        err = gpio_request(H3600_EGPIO_IR_FSEL, "IrDA fsel");
-        if (err)
-                goto err2;
-        err = gpio_direction_output(H3600_EGPIO_IR_FSEL, 0);
-        if (err)
-                goto err3;
-        return 0;
-
-err3:   gpio_free(H3600_EGPIO_IR_FSEL);
-err2:   gpio_free(H3600_EGPIO_IR_ON);
-err1:   return err;
+        return gpio_request_array(h3600_irda_gpio, sizeof(h3600_irda_gpio));
 }
 
 static void h3600_irda_shutdown(struct device *dev)
 {
-        gpio_free(H3600_EGPIO_IR_ON);
-        gpio_free(H3600_EGPIO_IR_FSEL);
+        return gpio_free_array(h3600_irda_gpio, sizeof(h3600_irda_gpio));
 }
 
 static struct irda_platform_data h3600_irda_data = {
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 307391488c22..c23fcdb047a5 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -39,8 +39,8 @@ extern unsigned long SCR_value;
 
 #define ASSABET_BCR_CF_PWR      (1<<0)  /* Compact Flash Power (1 = 3.3v, 0 = off) */
 #define ASSABET_BCR_CF_RST      (1<<1)  /* Compact Flash Reset (1 = power up reset) */
-#define ASSABET_BCR_GFX_RST     (1<<1)  /* Graphics Accelerator Reset (0 = hold reset) */
-#define ASSABET_BCR_CODEC_RST   (1<<2)  /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
+#define ASSABET_BCR_NGFX_RST    (1<<1)  /* Graphics Accelerator Reset (0 = hold reset) */
+#define ASSABET_BCR_NCODEC_RST  (1<<2)  /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
 #define ASSABET_BCR_IRDA_FSEL   (1<<3)  /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
 #define ASSABET_BCR_IRDA_MD0    (1<<4)  /* Range/Power select */
 #define ASSABET_BCR_IRDA_MD1    (1<<5)  /* Range/Power select */
@@ -69,6 +69,8 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
 #define ASSABET_BCR_frob(x,y)   do { } while (0)
 #endif
 
+extern void assabet_uda1341_reset(int set);
+
 #define ASSABET_BCR_set(x)      ASSABET_BCR_frob((x), (x))
 #define ASSABET_BCR_clear(x)    ASSABET_BCR_frob((x), 0)
 
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 713c86cd3d64..6fd4acb8f187 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -20,7 +20,7 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 
-static u32 notrace sa1100_read_sched_clock(void)
+static u64 notrace sa1100_read_sched_clock(void)
 {
         return readl_relaxed(OSCR);
 }
@@ -122,7 +122,7 @@ void __init sa1100_timer_init(void)
         writel_relaxed(0, OIER);
         writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
-        setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
+        sched_clock_register(sa1100_read_sched_clock, 32, 3686400);
 
         ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
 
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a4a4b75109b2..338640631e08 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,10 @@
+config ARCH_SHMOBILE
+        bool
+
 config ARCH_SHMOBILE_MULTI
-        bool "SH-Mobile Series" if ARCH_MULTI_V7
+        bool "Renesas ARM SoCs" if ARCH_MULTI_V7
         depends on MMU
+        select ARCH_SHMOBILE
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
@@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
         select HAVE_SMP
         select ARM_GIC
         select MIGHT_HAVE_CACHE_L2X0
+        select MIGHT_HAVE_PCI
         select NO_IOPORT
         select PINCTRL
         select ARCH_REQUIRE_GPIOLIB
@@ -15,24 +20,47 @@ config ARCH_SHMOBILE_MULTI
 
 if ARCH_SHMOBILE_MULTI
 
-comment "SH-Mobile System Type"
+comment "Renesas ARM SoCs System Type"
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
 
-comment "SH-Mobile Board Type"
+config ARCH_R7S72100
+        bool "RZ/A1H (R7S72100)"
+
+config ARCH_R8A7790
+        bool "R-Car H2 (R8A77900)"
+        select RENESAS_IRQC
+
+config ARCH_R8A7791
+        bool "R-Car M2 (R8A77910)"
+        select RENESAS_IRQC
+
+comment "Renesas ARM SoCs Board Type"
+
+config MACH_GENMAI
+        bool "Genmai board"
+        depends on ARCH_R7S72100
+
+config MACH_KOELSCH
+        bool "Koelsch board"
+        depends on ARCH_R8A7791
 
 config MACH_KZM9D
         bool "KZM9D board"
         depends on ARCH_EMEV2
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
-comment "SH-Mobile System Configuration"
+config MACH_LAGER
+        bool "Lager board"
+        depends on ARCH_R8A7790
+
+comment "Renesas ARM SoCs System Configuration"
 endif
 
-if ARCH_SHMOBILE
+if ARCH_SHMOBILE_LEGACY
 
-comment "SH-Mobile System Type"
+comment "Renesas ARM SoCs System Type"
 
 config ARCH_SH7372
         bool "SH-Mobile AP4 (SH7372)"
@@ -92,28 +120,36 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
+        select MIGHT_HAVE_PCI
         select SH_CLK_CPG
         select RENESAS_IRQC
 
 config ARCH_R8A7791
         bool "R-Car M2 (R8A77910)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
+        select MIGHT_HAVE_PCI
         select SH_CLK_CPG
+        select RENESAS_IRQC
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
+        select MIGHT_HAVE_PCI
+        select USE_OF
+        select AUTO_ZRELADDR
 
 config ARCH_R7S72100
         bool "RZ/A1H (R7S72100)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
         select SH_CLK_CPG
 
-comment "SH-Mobile Board Type"
+comment "Renesas ARM SoCs Board Type"
 
 config MACH_APE6EVM
         bool "APE6EVM board"
@@ -190,6 +226,17 @@ config MACH_GENMAI
         depends on ARCH_R7S72100
         select USE_OF
 
+config MACH_GENMAI_REFERENCE
+        bool "Genmai board - Reference Device Tree Implementation"
+        depends on ARCH_R7S72100
+        select USE_OF
+        ---help---
+           Use reference implementation of Genmai board support
+           which makes use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 config MACH_MARZEN
         bool "MARZEN board"
         depends on ARCH_R8A7779
@@ -215,27 +262,11 @@ config MACH_LAGER
         depends on ARCH_R8A7790
         select USE_OF
 
-config MACH_LAGER_REFERENCE
-        bool "Lager board - Reference Device Tree Implementation"
-        depends on ARCH_R8A7790
-        select USE_OF
-        ---help---
-           Use reference implementation of Lager board support
-           which makes use of device tree at the expense
-           of not supporting a number of devices.
-
-           This is intended to aid developers
-
 config MACH_KOELSCH
         bool "Koelsch board"
         depends on ARCH_R8A7791
         select USE_OF
-
-config MACH_KZM9D
-        bool "KZM9D board"
-        depends on ARCH_EMEV2
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select USE_OF
+        select MICREL_PHY if SH_ETH
 
 config MACH_KZM9G
         bool "KZM-A9-GT board"
@@ -261,7 +292,7 @@ config MACH_KZM9G_REFERENCE
 
            This is intended to aid developers
 
-comment "SH-Mobile System Configuration"
+comment "Renesas ARM SoCs System Configuration"
 
 config CPU_HAS_INTEVT
         bool
@@ -274,7 +305,7 @@ source "drivers/sh/Kconfig"
 
 endif
 
-if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI
+if ARCH_SHMOBILE
 
 menu "Timer and clock configuration"
 
@@ -286,8 +317,8 @@ config SHMOBILE_TIMER_HZ
           Allows the configuration of the timer frequency. It is customary
           to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
           case of low timer frequencies other values may be more suitable.
-          SH-Mobile systems using a 32768 Hz RCLK for clock events may want
-          to select a HZ value such as 128 that can evenly divide RCLK.
+          Renesas ARM SoC systems using a 32768 Hz RCLK for clock events may
+          want to select a HZ value such as 128 that can evenly divide RCLK.
           A HZ value that does not divide evenly may cause timer drift.
 
 config SH_TIMER_CMT
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 51db2bcafabf..fe7d4ff706e4 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -56,7 +56,10 @@ obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
 
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
+obj-$(CONFIG_MACH_GENMAI)       += board-genmai-reference.o
+obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d-reference.o
+obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)    += board-ape6evm-reference.o
@@ -64,14 +67,13 @@ obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai.o
+obj-$(CONFIG_MACH_GENMAI_REFERENCE)     += board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
-obj-$(CONFIG_MACH_LAGER_REFERENCE)      += board-lager-reference.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch.o
-obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 391d72a5536c..99455ecafa05 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -6,13 +6,12 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
-loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000
+loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000
+loadaddr-$(CONFIG_MACH_GENMAI_REFERENCE) += 0x08008000
 loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
-loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
-loadaddr-$(CONFIG_MACH_LAGER_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
 loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 0fa068e30a30..fe071a9130b7 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -168,7 +168,7 @@ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
 };
 
 static const struct resource mmcif0_resources[] __initconst = {
-        DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"),
+        DEFINE_RES_MEM(0xee200000, 0x100),
         DEFINE_RES_IRQ(gic_spi(169)),
 };
 
@@ -179,7 +179,7 @@ static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
 };
 
 static const struct resource sdhi0_resources[] __initconst = {
-        DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"),
+        DEFINE_RES_MEM(0xee100000, 0x100),
         DEFINE_RES_IRQ(gic_spi(165)),
 };
 
@@ -191,7 +191,7 @@ static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
 };
 
 static const struct resource sdhi1_resources[] __initconst = {
-        DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"),
+        DEFINE_RES_MEM(0xee120000, 0x100),
         DEFINE_RES_IRQ(gic_spi(166)),
 };
 
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 8ea87bd45c33..93533e2710a8 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -423,7 +423,7 @@ static struct platform_pwm_backlight_data pwm_backlight_data = {
         .max_brightness = 255,
         .dft_brightness = 255,
         .pwm_period_ns = 33333, /* 30kHz */
-        .enable_gpio = -1,
+        .enable_gpio = 61,
 };
 
 static struct platform_device pwm_backlight_device = {
@@ -963,7 +963,7 @@ static struct resource fsi_resources[] = {
         [0] = {
                 .name   = "FSI",
                 .start  = 0xfe1f0000,
-                .end    = 0xfe1f8400 - 1,
+                .end    = 0xfe1f0400 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -1210,9 +1210,6 @@ static void __init eva_init(void)
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
-        /* LCDC0 */
-        gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-
         /* GETHER */
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index ae88fdad4b3a..027373f8de82 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -19,7 +19,6 @@
  */
 
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <mach/common.h>
 #include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
@@ -28,27 +27,19 @@
  *      see board-bock.c for checking detail of dip-switch
  */
 
-static const struct pinctrl_map bockw_pinctrl_map[] = {
-        /* SCIF0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
-                                  "scif0_data_a", "scif0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
-                                  "scif0_ctrl", "scif0"),
-};
-
 #define FPGA    0x18200000
 #define IRQ0MR  0x30
 #define COMCTLR 0x101c
+
+#define PFC     0xfffc0000
+#define PUPR4   0x110
 static void __init bockw_init(void)
 {
-        static void __iomem *fpga;
+        void __iomem *fpga;
+        void __iomem *pfc;
 
         r8a7778_clock_init();
         r8a7778_init_irq_extpin_dt(1);
-
-        pinctrl_register_mappings(bockw_pinctrl_map,
-                                  ARRAY_SIZE(bockw_pinctrl_map));
-        r8a7778_pinmux_init();
         r8a7778_add_dt_devices();
 
         fpga = ioremap_nocache(FPGA, SZ_1M);
@@ -63,6 +54,19 @@ static void __init bockw_init(void)
                 u16 val = ioread16(fpga + IRQ0MR);
                 val &= ~(1 << 4); /* enable SMSC911x */
                 iowrite16(val, fpga + IRQ0MR);
+
+                iounmap(fpga);
+        }
+
+        pfc = ioremap_nocache(PFC, 0x200);
+        if (pfc) {
+                /*
+                 * FIXME
+                 *
+                 * SDHI CD/WP pin needs pull-up
+                 */
+                iowrite32(ioread32(pfc + PUPR4) | (3 << 26), pfc + PUPR4);
+                iounmap(pfc);
         }
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 3c4995aebd22..c475220545f2 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -25,6 +25,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mtd/partitions.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/camera-rcar.h>
 #include <linux/platform_data/usb-rcar-phy.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
@@ -116,6 +117,11 @@ static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
 };
 
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
 static struct smsc911x_platform_config smsc911x_data __initdata = {
         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
@@ -271,7 +277,6 @@ static struct resource mmc_resources[] __initdata = {
 
 static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = {
         .sup_pclk       = 0,
-        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
         .caps           = MMC_CAP_4_BIT_DATA |
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NEEDS_POLL,
@@ -328,11 +333,11 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
         RSND_SSI_UNUSED, /* SSI 1 */
         RSND_SSI_UNUSED, /* SSI 2 */
         RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY),
-        RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG),
+        RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
         RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY),
         RSND_SSI_SET(0, 0, gic_iid(0x86), 0),
         RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY),
-        RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG),
+        RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
 };
 
 static struct rsnd_scu_platform_info rsnd_scu[9] = {
@@ -614,6 +619,10 @@ static void __init bockw_init(void)
                 &usb_phy_platform_data,
                 sizeof(struct rcar_phy_platform_data));
 
+        regulator_register_fixed(0, dummy_supplies,
+                                 ARRAY_SIZE(dummy_supplies));
+        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 
         /* for SMSC */
         fpga = ioremap_nocache(FPGA, SZ_1M);
@@ -629,9 +638,6 @@ static void __init bockw_init(void)
                 val &= ~(1 << 4); /* enable SMSC911x */
                 iowrite16(val, fpga + IRQ0MR);
 
-                regulator_register_fixed(0, dummy_supplies,
-                                         ARRAY_SIZE(dummy_supplies));
-
                 platform_device_register_resndata(
                         &platform_bus, "smsc911x", -1,
                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
new file mode 100644
index 000000000000..7630c1053e32
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-genmai-reference.c
@@ -0,0 +1,49 @@
+/*
+ * Genmai board support
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <mach/common.h>
+#include <mach/r7s72100.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static void __init genmai_add_standard_devices(void)
+{
+#ifdef CONFIG_COMMON_CLK
+        of_clk_init(NULL);
+#else
+        r7s72100_clock_init();
+#endif
+        r7s72100_add_dt_devices();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const genmai_boards_compat_dt[] __initconst = {
+        "renesas,genmai-reference",
+        NULL,
+};
+
+DT_MACHINE_START(GENMAI_DT, "genmai")
+        .init_early     = r7s72100_init_early,
+        .init_machine   = genmai_add_standard_devices,
+        .dt_compat      = genmai_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
new file mode 100644
index 000000000000..652b59268416
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -0,0 +1,79 @@
+/*
+ * Koelsch board support - Reference DT implementation
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <mach/common.h>
+#include <mach/rcar-gen2.h>
+#include <mach/r8a7791.h>
+#include <asm/mach/arch.h>
+
+static void __init koelsch_add_standard_devices(void)
+{
+#ifdef CONFIG_COMMON_CLK
+        /*
+         * This is a really crude hack to provide clkdev support to the SCIF
+         * and CMT devices until they get moved to DT.
+         */
+        static const char * const scif_names[] = {
+                "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifa2",
+                "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scifa3",
+                "scifa4", "scifa5",
+        };
+        struct clk *clk;
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
+                clk = clk_get(NULL, scif_names[i]);
+                if (clk) {
+                        clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
+                        clk_put(clk);
+                }
+        }
+
+        clk = clk_get(NULL, "cmt0");
+        if (clk) {
+                clk_register_clkdev(clk, NULL, "sh_cmt.0");
+                clk_put(clk);
+        }
+#else
+        r8a7791_clock_init();
+#endif
+        r8a7791_add_dt_devices();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const koelsch_boards_compat_dt[] __initconst = {
+        "renesas,koelsch",
+        "renesas,koelsch-reference",
+        NULL,
+};
+
+DT_MACHINE_START(KOELSCH_DT, "koelsch")
+        .smp            = smp_ops(r8a7791_smp_ops),
+        .init_early     = r8a7791_init_early,
+        .init_time      = rcar_gen2_timer_init,
+        .init_machine   = koelsch_add_standard_devices,
+        .init_late      = shmobile_init_late,
+        .dt_compat      = koelsch_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index ace1711a6cd8..de7cc64b1f37 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -19,18 +19,205 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/phy.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/platform_data/rcar-du.h>
 #include <linux/platform_device.h>
+#include <linux/sh_eth.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/r8a7791.h>
 #include <mach/rcar-gen2.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* DU */
+static struct rcar_du_encoder_data koelsch_du_encoders[] = {
+        {
+                .type = RCAR_DU_ENCODER_NONE,
+                .output = RCAR_DU_OUTPUT_LVDS0,
+                .connector.lvds.panel = {
+                        .width_mm = 210,
+                        .height_mm = 158,
+                        .mode = {
+                                .clock = 65000,
+                                .hdisplay = 1024,
+                                .hsync_start = 1048,
+                                .hsync_end = 1184,
+                                .htotal = 1344,
+                                .vdisplay = 768,
+                                .vsync_start = 771,
+                                .vsync_end = 777,
+                                .vtotal = 806,
+                                .flags = 0,
+                        },
+                },
+        },
+};
+
+static const struct rcar_du_platform_data koelsch_du_pdata __initconst = {
+        .encoders = koelsch_du_encoders,
+        .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
+};
+
+static const struct resource du_resources[] __initconst = {
+        DEFINE_RES_MEM(0xfeb00000, 0x40000),
+        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
+        DEFINE_RES_IRQ(gic_spi(256)),
+        DEFINE_RES_IRQ(gic_spi(268)),
+};
+
+static void __init koelsch_add_du_device(void)
+{
+        struct platform_device_info info = {
+                .name = "rcar-du-r8a7791",
+                .id = -1,
+                .res = du_resources,
+                .num_res = ARRAY_SIZE(du_resources),
+                .data = &koelsch_du_pdata,
+                .size_data = sizeof(koelsch_du_pdata),
+                .dma_mask = DMA_BIT_MASK(32),
+        };
+
+        platform_device_register_full(&info);
+}
+
+/* Ether */
+static const struct sh_eth_plat_data ether_pdata __initconst = {
+        .phy                    = 0x1,
+        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
+        .phy_interface          = PHY_INTERFACE_MODE_RMII,
+        .ether_link_active_low  = 1,
+};
+
+static const struct resource ether_resources[] __initconst = {
+        DEFINE_RES_MEM(0xee700000, 0x400),
+        DEFINE_RES_IRQ(gic_spi(162)),
+};
+
+/* LEDS */
+static struct gpio_led koelsch_leds[] = {
+        {
+                .name           = "led8",
+                .gpio           = RCAR_GP_PIN(2, 21),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led7",
+                .gpio           = RCAR_GP_PIN(2, 20),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led6",
+                .gpio           = RCAR_GP_PIN(2, 19),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+};
+
+static const struct gpio_led_platform_data koelsch_leds_pdata __initconst = {
+        .leds           = koelsch_leds,
+        .num_leds       = ARRAY_SIZE(koelsch_leds),
+};
+
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d, ...) \
+        { .code = c, .gpio = g, .desc = d, .active_low = 1, \
+          .wakeup = 1, .debounce_interval = 20 }
+
+static struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_4,         RCAR_GP_PIN(5, 3),      "SW2-pin4"),
+        GPIO_KEY(KEY_3,         RCAR_GP_PIN(5, 2),      "SW2-pin3"),
+        GPIO_KEY(KEY_2,         RCAR_GP_PIN(5, 1),      "SW2-pin2"),
+        GPIO_KEY(KEY_1,         RCAR_GP_PIN(5, 0),      "SW2-pin1"),
+        GPIO_KEY(KEY_G,         RCAR_GP_PIN(7, 6),      "SW36"),
+        GPIO_KEY(KEY_F,         RCAR_GP_PIN(7, 5),      "SW35"),
+        GPIO_KEY(KEY_E,         RCAR_GP_PIN(7, 4),      "SW34"),
+        GPIO_KEY(KEY_D,         RCAR_GP_PIN(7, 3),      "SW33"),
+        GPIO_KEY(KEY_C,         RCAR_GP_PIN(7, 2),      "SW32"),
+        GPIO_KEY(KEY_B,         RCAR_GP_PIN(7, 1),      "SW31"),
+        GPIO_KEY(KEY_A,         RCAR_GP_PIN(7, 0),      "SW30"),
+};
+
+static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static const struct pinctrl_map koelsch_pinctrl_map[] = {
+        /* DU */
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
+                                  "du_rgb666", "du"),
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
+                                  "du_sync", "du"),
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
+                                  "du_clk_out_0", "du"),
+        /* Ether */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
+                                  "eth_link", "eth"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
+                                  "eth_mdio", "eth"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
+                                  "eth_rmii", "eth"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
+                                  "intc_irq0", "intc"),
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
+                                  "scif0_data_d", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7791",
+                                  "scif1_data_d", "scif1"),
+};
+
 static void __init koelsch_add_standard_devices(void)
 {
         r8a7791_clock_init();
+        pinctrl_register_mappings(koelsch_pinctrl_map,
+                                  ARRAY_SIZE(koelsch_pinctrl_map));
+        r8a7791_pinmux_init();
         r8a7791_add_standard_devices();
+        platform_device_register_resndata(&platform_bus, "r8a7791-ether", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          &ether_pdata, sizeof(ether_pdata));
+        platform_device_register_data(&platform_bus, "leds-gpio", -1,
+                                      &koelsch_leds_pdata,
+                                      sizeof(koelsch_leds_pdata));
+        platform_device_register_data(&platform_bus, "gpio-keys", -1,
+                                      &koelsch_keys_pdata,
+                                      sizeof(koelsch_keys_pdata));
+
+        koelsch_add_du_device();
+}
+
+/*
+ * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
+ * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
+ * 14-15. We have to set them back to 01 from the default 00 value each time
+ * the PHY is reset. It's also important because the PHY's LED0 signal is
+ * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
+ * bounce on and off after each packet, which we apparently want to avoid.
+ */
+static int koelsch_ksz8041_fixup(struct phy_device *phydev)
+{
+        u16 phyctrl1 = phy_read(phydev, 0x1e);
+
+        phyctrl1 &= ~0xc000;
+        phyctrl1 |= 0x4000;
+        return phy_write(phydev, 0x1e, phyctrl1);
+}
+
+static void __init koelsch_init(void)
+{
+        koelsch_add_standard_devices();
+
+        if (IS_ENABLED(CONFIG_PHYLIB))
+                phy_register_fixup_for_id("r8a7791-ether-ff:01",
+                                          koelsch_ksz8041_fixup);
 }
 
 static const char * const koelsch_boards_compat_dt[] __initconst = {
@@ -41,7 +228,8 @@ static const char * const koelsch_boards_compat_dt[] __initconst = {
 DT_MACHINE_START(KOELSCH_DT, "koelsch")
         .smp            = smp_ops(r8a7791_smp_ops),
         .init_early     = r8a7791_init_early,
-        .init_machine   = koelsch_add_standard_devices,
         .init_time      = rcar_gen2_timer_init,
+        .init_machine   = koelsch_init,
+        .init_late      = shmobile_init_late,
         .dt_compat      = koelsch_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
deleted file mode 100644
index 30c2cc695b12..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * kzm9d board support
- *
- * Copyright (C) 2012  Renesas Solutions Corp.
- * Copyright (C) 2012  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <mach/common.h>
-#include <mach/emev2.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-
-/* Ether */
-static struct resource smsc911x_resources[] = {
-        [0] = {
-                .start  = 0x20000000,
-                .end    = 0x2000ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = EMEV2_GPIO_IRQ(1),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_platdata = {
-        .flags          = SMSC911X_USE_32BIT,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-};
-
-static struct platform_device smsc91x_device = {
-        .name   = "smsc911x",
-        .id     = -1,
-        .dev    = {
-                  .platform_data = &smsc911x_platdata,
-                },
-        .num_resources  = ARRAY_SIZE(smsc911x_resources),
-        .resource       = smsc911x_resources,
-};
-
-static struct platform_device *kzm9d_devices[] __initdata = {
-        &smsc91x_device,
-};
-
-void __init kzm9d_add_standard_devices(void)
-{
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        emev2_add_standard_devices();
-
-        platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
-}
-
-static const char *kzm9d_boards_compat_dt[] __initdata = {
-        "renesas,kzm9d",
-        NULL,
-};
-
-DT_MACHINE_START(KZM9D_DT, "kzm9d")
-        .smp            = smp_ops(emev2_smp_ops),
-        .map_io         = emev2_map_io,
-        .init_early     = emev2_init_delay,
-        .init_machine   = kzm9d_add_standard_devices,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = kzm9d_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 1a1a4a888632..a6e271d92af0 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -18,21 +18,53 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/of_platform.h>
+#include <mach/common.h>
+#include <mach/rcar-gen2.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
 static void __init lager_add_standard_devices(void)
 {
-        /* clocks are setup late during boot in the case of DT */
+#ifdef CONFIG_COMMON_CLK
+        /*
+         * This is a really crude hack to provide clkdev support to the SCIF
+         * and CMT devices until they get moved to DT.
+         */
+        static const char * const scif_names[] = {
+                "scifa0", "scifa1", "scifb0", "scifb1",
+                "scifb2", "scifa2", "scif0", "scif1",
+                "hscif0", "hscif1",
+        };
+        struct clk *clk;
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
+                clk = clk_get(NULL, scif_names[i]);
+                if (clk) {
+                        clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
+                        clk_put(clk);
+                }
+        }
+
+        clk = clk_get(NULL, "cmt0");
+        if (clk) {
+                clk_register_clkdev(clk, NULL, "sh_cmt.0");
+                clk_put(clk);
+        }
+#else
         r8a7790_clock_init();
+#endif
 
         r8a7790_add_dt_devices();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
+        "renesas,lager",
         "renesas,lager-reference",
         NULL,
 };
@@ -42,5 +74,6 @@ DT_MACHINE_START(LAGER_DT, "lager")
         .init_early     = r8a7790_init_early,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_add_standard_devices,
+        .init_late      = shmobile_init_late,
         .dt_compat      = lager_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index e0406fd37390..f20c10a18543 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -31,7 +31,9 @@
 #include <linux/platform_data/rcar-du.h>
 #include <linux/platform_device.h>
 #include <linux/phy.h>
+#include <linux/regulator/driver.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
 #include <mach/common.h>
@@ -39,6 +41,11 @@
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/mtd.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 
 /* DU */
 static struct rcar_du_encoder_data lager_du_encoders[] = {
@@ -120,7 +127,8 @@ static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
 
 /* GPIO KEY */
 #define GPIO_KEY(c, g, d, ...) \
-        { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+        { .code = c, .gpio = g, .desc = d, .active_low = 1, \
+          .wakeup = 1, .debounce_interval = 20 }
 
 static struct gpio_keys_button gpio_buttons[] = {
         GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
@@ -140,6 +148,71 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
         REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
 };
 
+/*
+ * SDHI regulator macro
+ *
+ ** FIXME**
+ * Lager board vqmmc is provided via DA9063 PMIC chip,
+ * and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
+ * but, it doesn't have regulator support at this point.
+ * It uses gpio-regulator for vqmmc as quick-hack.
+ */
+#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin)                          \
+static struct regulator_consumer_supply vcc_sdhi##idx##_consumer =      \
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx);               \
+                                                                        \
+static struct regulator_init_data vcc_sdhi##idx##_init_data = {         \
+        .constraints = {                                                \
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,              \
+        },                                                              \
+        .consumer_supplies      = &vcc_sdhi##idx##_consumer,            \
+        .num_consumer_supplies  = 1,                                    \
+};                                                                      \
+                                                                        \
+static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
+        .supply_name    = "SDHI" #idx "Vcc",                            \
+        .microvolts     = 3300000,                                      \
+        .gpio           = vdd_pin,                                      \
+        .enable_high    = 1,                                            \
+        .init_data      = &vcc_sdhi##idx##_init_data,                   \
+};                                                                      \
+                                                                        \
+static struct regulator_consumer_supply vccq_sdhi##idx##_consumer =     \
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx);              \
+                                                                        \
+static struct regulator_init_data vccq_sdhi##idx##_init_data = {        \
+        .constraints = {                                                \
+                .input_uV       = 3300000,                              \
+                .min_uV         = 1800000,                              \
+                .max_uV         = 3300000,                              \
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |            \
+                                  REGULATOR_CHANGE_STATUS,              \
+        },                                                              \
+        .consumer_supplies      = &vccq_sdhi##idx##_consumer,           \
+        .num_consumer_supplies  = 1,                                    \
+};                                                                      \
+                                                                        \
+static struct gpio vccq_sdhi##idx##_gpio =                              \
+        { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx };            \
+                                                                        \
+static struct gpio_regulator_state vccq_sdhi##idx##_states[] = {        \
+        { .value = 1800000, .gpios = 0 },                               \
+        { .value = 3300000, .gpios = 1 },                               \
+};                                                                      \
+                                                                        \
+static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
+        .supply_name    = "vqmmc",                                      \
+        .gpios          = &vccq_sdhi##idx##_gpio,                       \
+        .nr_gpios       = 1,                                            \
+        .states         = vccq_sdhi##idx##_states,                      \
+        .nr_states      = ARRAY_SIZE(vccq_sdhi##idx##_states),          \
+        .type           = REGULATOR_VOLTAGE,                            \
+        .init_data      = &vccq_sdhi##idx##_init_data,                  \
+};
+
+SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
+SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
+
 /* MMCIF */
 static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
         .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
@@ -148,7 +221,7 @@ static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
 };
 
 static const struct resource mmcif1_resources[] __initconst = {
-        DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"),
+        DEFINE_RES_MEM(0xee220000, 0x80),
         DEFINE_RES_IRQ(gic_spi(170)),
 };
 
@@ -165,6 +238,59 @@ static const struct resource ether_resources[] __initconst = {
         DEFINE_RES_IRQ(gic_spi(162)),
 };
 
+/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
+static struct mtd_partition spi_flash_part[] = {
+        /* Reserved for user loader program, read-only */
+        {
+                .name = "loader",
+                .offset = 0,
+                .size = SZ_256K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        /* Reserved for user program, read-only */
+        {
+                .name = "user",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_4M,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        /* All else is writable (e.g. JFFS2) */
+        {
+                .name = "flash",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+                .mask_flags = 0,
+        },
+};
+
+static struct flash_platform_data spi_flash_data = {
+        .name           = "m25p80",
+        .parts          = spi_flash_part,
+        .nr_parts       = ARRAY_SIZE(spi_flash_part),
+        .type           = "s25fl512s",
+};
+
+static const struct rspi_plat_data qspi_pdata __initconst = {
+        .num_chipselect = 1,
+};
+
+static const struct spi_board_info spi_info[] __initconst = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &spi_flash_data,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 0,
+                .chip_select            = 0,
+        },
+};
+
+/* QSPI resource */
+static const struct resource qspi_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe6b10000, 0x1000),
+        DEFINE_RES_IRQ(gic_spi(184)),
+};
+
 static const struct pinctrl_map lager_pinctrl_map[] = {
         /* DU (CN10: ARGB0, CN13: LVDS) */
         PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
@@ -197,6 +323,9 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
 
 static void __init lager_add_standard_devices(void)
 {
+        int fixed_regulator_idx = 0;
+        int gpio_regulator_idx = 0;
+
         r8a7790_clock_init();
 
         pinctrl_register_mappings(lager_pinctrl_map,
@@ -210,7 +339,8 @@ static void __init lager_add_standard_devices(void)
         platform_device_register_data(&platform_bus, "gpio-keys", -1,
                                       &lager_keys_pdata,
                                       sizeof(lager_keys_pdata));
-        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+        regulator_register_always_on(fixed_regulator_idx++,
+                                     "fixed-3.3V", fixed3v3_power_consumers,
                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
         platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
                                           mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
@@ -222,6 +352,22 @@ static void __init lager_add_standard_devices(void)
                                           &ether_pdata, sizeof(ether_pdata));
 
         lager_add_du_device();
+
+        platform_device_register_resndata(&platform_bus, "qspi", 0,
+                                          qspi_resources,
+                                          ARRAY_SIZE(qspi_resources),
+                                          &qspi_pdata, sizeof(qspi_pdata));
+        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
+
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
+                                      &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
+                                      &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
+
+        platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
+                                      &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
+        platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
+                                      &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
 }
 
 /*
@@ -260,5 +406,6 @@ DT_MACHINE_START(LAGER_DT, "lager")
         .init_early     = r8a7790_init_early,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_init,
+        .init_late      = shmobile_init_late,
         .dt_compat      = lager_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index e721d2ccceae..3aba0372f630 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -41,6 +41,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/gpio_backlight.h>
 #include <linux/pm_clock.h>
 #include <linux/regulator/fixed.h>
@@ -548,9 +549,9 @@ static void __init hdmi_init_pm_clock(void)
                  clk_get_rate(&sh7372_pllc2_clk));
 
         rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
-        if (rate < 0) {
+        if (rate <= 0) {
                 pr_err("Cannot get suitable rate: %ld\n", rate);
-                ret = rate;
+                ret = -EINVAL;
                 goto out;
         }
 
@@ -1311,6 +1312,10 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
+static unsigned long pin_pulldown_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0),
+};
+
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
         /* ADXL34X */
         PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
@@ -1396,17 +1401,19 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
         /* USBHS0 */
         PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
                                   "usb0_vbus", "usb0"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                      "usb0_vbus", pin_pulldown_conf),
         /* USBHS1 */
         PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
                                   "usb1_vbus", "usb1"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                      "usb1_vbus", pin_pulldown_conf),
         PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
                                   "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
 #define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define GPIO_PORT167CR  IOMEM(0xE60520A7)
-#define GPIO_PORT168CR  IOMEM(0xE60520A8)
 #define SRCR4           IOMEM(0xe61580bc)
 #define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
@@ -1446,12 +1453,6 @@ static void __init mackerel_init(void)
 
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
-        /* USBHS0 */
-        gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
-
-        /* USBHS1 */
-        gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-
         /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index da1352f5f71b..d832a4477b4b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -29,6 +29,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/camera-rcar.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/rcar-du.h>
 #include <linux/platform_data/usb-rcar-phy.h>
@@ -259,10 +260,30 @@ static struct platform_device leds_device = {
         },
 };
 
+/* VIN */
 static struct rcar_vin_platform_data vin_platform_data __initdata = {
         .flags  = RCAR_VIN_BT656,
 };
 
+#define MARZEN_VIN(idx)                                         \
+static struct resource vin##idx##_resources[] __initdata = {    \
+        DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),    \
+        DEFINE_RES_IRQ(gic_iid(0x5f + (idx))),                  \
+};                                                              \
+                                                                \
+static struct platform_device_info vin##idx##_info __initdata = { \
+        .parent         = &platform_bus,                        \
+        .name           = "r8a7779-vin",                        \
+        .id             = idx,                                  \
+        .res            = vin##idx##_resources,                 \
+        .num_res        = ARRAY_SIZE(vin##idx##_resources),     \
+        .dma_mask       = DMA_BIT_MASK(32),                     \
+        .data           = &vin_platform_data,                   \
+        .size_data      = sizeof(vin_platform_data),            \
+}
+MARZEN_VIN(1);
+MARZEN_VIN(3);
+
 #define MARZEN_CAMERA(idx)                                      \
 static struct i2c_board_info camera##idx##_info = {             \
         I2C_BOARD_INFO("adv7180", 0x20 + (idx)),                \
@@ -326,8 +347,6 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
                                   "sdhi0_cd", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
-                                  "sdhi0_wp", "sdhi0"),
         /* SMSC */
         PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
                                   "intc_irq1_b", "intc"),
@@ -367,8 +386,8 @@ static void __init marzen_init(void)
         r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
 
         r8a7779_add_standard_devices();
-        r8a7779_add_vin_device(1, &vin_platform_data);
-        r8a7779_add_vin_device(3, &vin_platform_data);
+        platform_device_register_full(&vin1_info);
+        platform_device_register_full(&vin3_info);
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
         marzen_add_du_device();
 }
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index 4aba20ca127e..e6ab0cd5b286 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -27,6 +27,7 @@
 #define FRQCR2          0xfcfe0014
 #define STBCR3          0xfcfe0420
 #define STBCR4          0xfcfe0424
+#define STBCR9          0xfcfe0438
 
 #define PLL_RATE 30
 
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
                                         | CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
+enum {  MSTP97, MSTP96, MSTP95, MSTP94,
+        MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
         MSTP33, MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
+        [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
+        [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
+        [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
         [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
         [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
         [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
@@ -170,6 +176,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 
         /* MSTP clocks */
+        CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
+
+        /* ICK */
         CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
         CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
         CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 571409b611d3..7348d58f500e 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -584,15 +584,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
-        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
         CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
         CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c826bca4024e..dd989f93498f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -585,22 +585,23 @@ static struct clk_lookup lookups[] = {
 
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
+        CLKDEV_DEV_ID("fe1f0000.sound",         &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sd",            &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sd",            &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmc",           &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
         CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
-        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sd",            &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index fb6af83858e3..9783945f8bc7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
 };
 
 enum {
+        MSTP531, MSTP530,
+        MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
         MSTP331,
         MSTP323, MSTP322, MSTP321,
         MSTP311, MSTP310,
@@ -129,6 +131,15 @@ enum {
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
+        [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
+        [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
+        [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
+        [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
+        [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
+        [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
+        [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
+        [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
         [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
         [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
         [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
@@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = {
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
+        CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
         CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
         CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
@@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
         CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
         CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
         CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
         CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
+        CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
         CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
         CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
+        CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
 
         CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
@@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
         CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
         CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
+        CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
+        CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
+        CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
+        CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
+        CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
+        CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
+        CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
+        CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
+        CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
 };
 
 void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1f7080fab0a5..f1fb89b76786 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
         CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
         CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
         CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
         CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
         CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
+        CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
         CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
         CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
+        CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
         CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
 };
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a64f965c7da1..f44987a92ad4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -53,6 +53,7 @@
 #define SMSTPCR7 0xe615014c
 #define SMSTPCR8 0xe6150990
 #define SMSTPCR9 0xe6150994
+#define SMSTPCR10 0xe6150998
 
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
@@ -77,7 +78,7 @@ static struct sh_clk_ops followparent_clk_ops = {
 };
 
 static struct clk main_clk = {
-        /* .parent will be set r8a73a4_clock_init */
+        /* .parent will be set r8a7790_clock_init */
         .ops    = &followparent_clk_ops,
 };
 
@@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+        MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
+        MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
         MSTP931, MSTP930, MSTP929, MSTP928,
+        MSTP917,
         MSTP813,
         MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
         MSTP717, MSTP716,
+        MSTP704,
         MSTP522,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -194,10 +199,22 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
-        [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
-        [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
-        [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
+        [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
+        [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
+        [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
+        [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
+        [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
+        [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
+        [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  9, 0), /* SSI6 */
+        [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  8, 0), /* SSI7 */
+        [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  7, 0), /* SSI8 */
+        [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  6, 0), /* SSI9 */
+        [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  5, 0), /* SSI ALL */
+        [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
+        [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
+        [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
+        [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
+        [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
         [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
         [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
         [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
         [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
         [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
         [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
 
         /* MSTP */
-        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
-        CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
-        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
-        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
-        CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
+        CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -278,24 +292,50 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
         CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
         CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
         CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
         CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
-        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
-        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
+        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+
+        /* ICK */
+        CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
+        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
+        CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
+        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
+        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
+        CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
+        CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
+        CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
+        CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
+        CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
+        CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
+        CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
+        CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
+        CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
+        CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
+        CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
+
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
@@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void)
                 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
                 break;
         case MD(14):
-                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
                 break;
         case MD(13) | MD(14):
-                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
                 break;
         }
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index c9a26f16ce5b..f5461262ee25 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk,			pll1_clk,	1, 12);
 SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
 SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
 
 static struct clk *main_clks[] = {
         &extal_clk,
@@ -116,12 +117,15 @@ static struct clk *main_clks[] = {
         &rclk_clk,
         &mp_clk,
         &cp_clk,
+        &zx_clk,
 };
 
 /* MSTP */
 enum {
-        MSTP721, MSTP720,
+        MSTP813,
+        MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
         MSTP719, MSTP718, MSTP715, MSTP714,
+        MSTP522,
         MSTP216, MSTP207, MSTP206,
         MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
         MSTP124,
@@ -129,12 +133,17 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+        [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
+        [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
+        [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
         [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
         [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
         [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
         [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
+        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
         [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &hp_clk),
 
         /* MSTP */
+        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
+        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
+        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
@@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
 };
 
 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 5390c6bbbc02..28489978b09c 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -504,10 +504,6 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
         CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
         CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
@@ -574,6 +570,11 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
         CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
 
+        /* ICK */
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
         CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
                       &div6_reparent_clks[DIV6_HDMI]),
         CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index c92c023f0d27..23edf8360c27 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -625,12 +625,6 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
         CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
         CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
-        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
-        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -658,18 +652,19 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
+        CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
-        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
-        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
-        CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
-        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */
@@ -680,6 +675,14 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
         CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+
+        /* ICK */
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
+        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
 };
 
 void __init sh73a0_clock_init(void)
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index c2eb7568d9be..fcb142a14e07 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -3,12 +3,7 @@
 
 extern void emev2_map_io(void);
 extern void emev2_init_delay(void);
-extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
-
-#define EMEV2_GPIO_BASE 200
-#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
-
 extern struct smp_operations emev2_smp_ops;
 
 #endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 441886c9714b..f4076a50e970 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -20,13 +20,50 @@
 #define __ASM_R8A7778_H__
 
 #include <linux/sh_eth.h>
-#include <linux/platform_data/camera-rcar.h>
 
 /* HPB-DMA slave IDs */
 enum {
         HPBDMA_SLAVE_DUMMY,
         HPBDMA_SLAVE_SDHI0_TX,
         HPBDMA_SLAVE_SDHI0_RX,
+        HPBDMA_SLAVE_SSI0_TX,
+        HPBDMA_SLAVE_SSI0_RX,
+        HPBDMA_SLAVE_SSI1_TX,
+        HPBDMA_SLAVE_SSI1_RX,
+        HPBDMA_SLAVE_SSI2_TX,
+        HPBDMA_SLAVE_SSI2_RX,
+        HPBDMA_SLAVE_SSI3_TX,
+        HPBDMA_SLAVE_SSI3_RX,
+        HPBDMA_SLAVE_SSI4_TX,
+        HPBDMA_SLAVE_SSI4_RX,
+        HPBDMA_SLAVE_SSI5_TX,
+        HPBDMA_SLAVE_SSI5_RX,
+        HPBDMA_SLAVE_SSI6_TX,
+        HPBDMA_SLAVE_SSI6_RX,
+        HPBDMA_SLAVE_SSI7_TX,
+        HPBDMA_SLAVE_SSI7_RX,
+        HPBDMA_SLAVE_SSI8_TX,
+        HPBDMA_SLAVE_SSI8_RX,
+        HPBDMA_SLAVE_HPBIF0_TX,
+        HPBDMA_SLAVE_HPBIF0_RX,
+        HPBDMA_SLAVE_HPBIF1_TX,
+        HPBDMA_SLAVE_HPBIF1_RX,
+        HPBDMA_SLAVE_HPBIF2_TX,
+        HPBDMA_SLAVE_HPBIF2_RX,
+        HPBDMA_SLAVE_HPBIF3_TX,
+        HPBDMA_SLAVE_HPBIF3_RX,
+        HPBDMA_SLAVE_HPBIF4_TX,
+        HPBDMA_SLAVE_HPBIF4_RX,
+        HPBDMA_SLAVE_HPBIF5_TX,
+        HPBDMA_SLAVE_HPBIF5_RX,
+        HPBDMA_SLAVE_HPBIF6_TX,
+        HPBDMA_SLAVE_HPBIF6_RX,
+        HPBDMA_SLAVE_HPBIF7_TX,
+        HPBDMA_SLAVE_HPBIF7_RX,
+        HPBDMA_SLAVE_HPBIF8_TX,
+        HPBDMA_SLAVE_HPBIF8_RX,
+        HPBDMA_SLAVE_USBFUNC_TX,
+        HPBDMA_SLAVE_USBFUNC_RX,
 };
 
 extern void r8a7778_add_standard_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 17af34ed89c8..b40e13631f6a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -3,8 +3,6 @@
 
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
-#include <linux/sh_eth.h>
-#include <linux/platform_data/camera-rcar.h>
 
 /* HPB-DMA slave IDs */
 enum {
@@ -13,8 +11,6 @@ enum {
         HPBDMA_SLAVE_SDHI0_RX,
 };
 
-struct platform_device;
-
 struct r8a7779_pm_ch {
         unsigned long chan_offs;
         unsigned int chan_bit;
@@ -40,9 +36,6 @@ extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
-extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
-extern void r8a7779_add_vin_device(int idx,
-                                   struct rcar_vin_platform_data *pdata);
 extern void r8a7779_init_late(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
index 051ead3c286e..200fa699f730 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -4,6 +4,7 @@
 void r8a7791_add_standard_devices(void);
 void r8a7791_add_dt_devices(void);
 void r8a7791_clock_init(void);
+void r8a7791_pinmux_init(void);
 void r8a7791_init_early(void);
 extern struct smp_operations r8a7791_smp_ops;
 
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 3ad531caf4f0..c8f2a1a69a52 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,24 +16,15 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/clk-provider.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/gpio-em.h>
 #include <linux/of_platform.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 static struct map_desc emev2_io_desc[] __initdata = {
 #ifdef CONFIG_SMP
@@ -52,150 +43,20 @@ void __init emev2_map_io(void)
         iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
 }
 
-/* UART */
-static struct resource uart0_resources[] = {
-        DEFINE_RES_MEM(0xe1020000, 0x38),
-        DEFINE_RES_IRQ(40),
-};
-
-static struct resource uart1_resources[] = {
-        DEFINE_RES_MEM(0xe1030000, 0x38),
-        DEFINE_RES_IRQ(41),
-};
-
-static struct resource uart2_resources[] = {
-        DEFINE_RES_MEM(0xe1040000, 0x38),
-        DEFINE_RES_IRQ(42),
-};
-
-static struct resource uart3_resources[] = {
-        DEFINE_RES_MEM(0xe1050000, 0x38),
-        DEFINE_RES_IRQ(43),
-};
-
-#define emev2_register_uart(idx)                                        \
-        platform_device_register_simple("serial8250-em", idx,           \
-                                        uart##idx##_resources,          \
-                                        ARRAY_SIZE(uart##idx##_resources))
-
-/* STI */
-static struct resource sti_resources[] = {
-        DEFINE_RES_MEM(0xe0180000, 0x54),
-        DEFINE_RES_IRQ(157),
-};
-
-#define emev2_register_sti()                                    \
-        platform_device_register_simple("em_sti", 0,            \
-                                        sti_resources,          \
-                                        ARRAY_SIZE(sti_resources))
-
-/* GIO */
-static struct gpio_em_config gio0_config = {
-        .gpio_base = 0,
-        .irq_base = EMEV2_GPIO_IRQ(0),
-        .number_of_pins = 32,
-};
-
-static struct resource gio0_resources[] = {
-        DEFINE_RES_MEM(0xe0050000, 0x2c),
-        DEFINE_RES_MEM(0xe0050040, 0x20),
-        DEFINE_RES_IRQ(99),
-        DEFINE_RES_IRQ(100),
-};
-
-static struct gpio_em_config gio1_config = {
-        .gpio_base = 32,
-        .irq_base = EMEV2_GPIO_IRQ(32),
-        .number_of_pins = 32,
-};
-
-static struct resource gio1_resources[] = {
-        DEFINE_RES_MEM(0xe0050080, 0x2c),
-        DEFINE_RES_MEM(0xe00500c0, 0x20),
-        DEFINE_RES_IRQ(101),
-        DEFINE_RES_IRQ(102),
-};
-
-static struct gpio_em_config gio2_config = {
-        .gpio_base = 64,
-        .irq_base = EMEV2_GPIO_IRQ(64),
-        .number_of_pins = 32,
-};
-
-static struct resource gio2_resources[] = {
-        DEFINE_RES_MEM(0xe0050100, 0x2c),
-        DEFINE_RES_MEM(0xe0050140, 0x20),
-        DEFINE_RES_IRQ(103),
-        DEFINE_RES_IRQ(104),
-};
-
-static struct gpio_em_config gio3_config = {
-        .gpio_base = 96,
-        .irq_base = EMEV2_GPIO_IRQ(96),
-        .number_of_pins = 32,
-};
-
-static struct resource gio3_resources[] = {
-        DEFINE_RES_MEM(0xe0050180, 0x2c),
-        DEFINE_RES_MEM(0xe00501c0, 0x20),
-        DEFINE_RES_IRQ(105),
-        DEFINE_RES_IRQ(106),
-};
-
-static struct gpio_em_config gio4_config = {
-        .gpio_base = 128,
-        .irq_base = EMEV2_GPIO_IRQ(128),
-        .number_of_pins = 31,
-};
-
-static struct resource gio4_resources[] = {
-        DEFINE_RES_MEM(0xe0050200, 0x2c),
-        DEFINE_RES_MEM(0xe0050240, 0x20),
-        DEFINE_RES_IRQ(107),
-        DEFINE_RES_IRQ(108),
-};
-
-#define emev2_register_gio(idx)                                         \
-        platform_device_register_resndata(&platform_bus, "em_gio",      \
-                                          idx, gio##idx##_resources,    \
-                                          ARRAY_SIZE(gio##idx##_resources), \
-                                          &gio##idx##_config,           \
-                                          sizeof(struct gpio_em_config))
-
-static struct resource pmu_resources[] = {
-        DEFINE_RES_IRQ(152),
-        DEFINE_RES_IRQ(153),
-};
-
-#define emev2_register_pmu()                                    \
-        platform_device_register_simple("arm-pmu", -1,          \
-                                        pmu_resources,          \
-                                        ARRAY_SIZE(pmu_resources))
-
-void __init emev2_add_standard_devices(void)
-{
-        if (!IS_ENABLED(CONFIG_COMMON_CLK))
-                emev2_clock_init();
-
-        emev2_register_uart(0);
-        emev2_register_uart(1);
-        emev2_register_uart(2);
-        emev2_register_uart(3);
-        emev2_register_sti();
-        emev2_register_gio(0);
-        emev2_register_gio(1);
-        emev2_register_gio(2);
-        emev2_register_gio(3);
-        emev2_register_gio(4);
-        emev2_register_pmu();
-}
-
 void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
 
-#ifdef CONFIG_USE_OF
+static void __init emev2_add_standard_devices_dt(void)
+{
+#ifdef CONFIG_COMMON_CLK
+        of_clk_init(NULL);
+#else
+        emev2_clock_init();
+#endif
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
 
 static const char *emev2_boards_compat_dt[] __initdata = {
         "renesas,emev2",
@@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
         .init_early     = emev2_init_delay,
+        .init_machine   = emev2_add_standard_devices_dt,
+        .init_late      = shmobile_init_late,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
-
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d4eb509a1c87..9c0b3a9d5f7a 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,52 +22,76 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r7s72100.h>
 #include <asm/mach/arch.h>
 
-#define SCIF_DATA(index, baseaddr, irq)                                 \
-[index] = {                                                             \
+#define R7S72100_SCIF(index, baseaddr, irq)                             \
+static const struct plat_sci_port scif##index##_platform_data = {       \
         .type           = PORT_SCIF,                                    \
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,               \
         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
-        .scbrr_algo_id  = SCBRR_ALGO_2,                                 \
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
                           SCSCR_REIE,                                   \
-        .mapbase        = baseaddr,                                     \
-        .irqs           = { irq + 1, irq + 2, irq + 3, irq },           \
-}
+};                                                                      \
+                                                                        \
+static struct resource scif##index##_resources[] = {                    \
+        DEFINE_RES_MEM(baseaddr, 0x100),                                \
+        DEFINE_RES_IRQ(irq + 1),                                        \
+        DEFINE_RES_IRQ(irq + 2),                                        \
+        DEFINE_RES_IRQ(irq + 3),                                        \
+        DEFINE_RES_IRQ(irq),                                            \
+}                                                                       \
+
+R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
+R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
+R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
+R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
+R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
+R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
+R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
+R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
 
-enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 };
+#define r7s72100_register_scif(index)                                          \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 
-static const struct plat_sci_port scif[] __initconst = {
-        SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */
-        SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */
-        SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */
-        SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */
-        SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */
-        SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
-        SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
-        SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
+
+static struct sh_timer_config mtu2_0_platform_data __initdata = {
+        .name = "MTU2_0",
+        .timer_bit = 0,
+        .channel_offset = -0x80,
+        .clockevent_rating = 200,
 };
 
-static inline void r7s72100_register_scif(int idx)
-{
-        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
-                                      sizeof(struct plat_sci_port));
-}
+static struct resource mtu2_0_resources[] __initdata = {
+        DEFINE_RES_MEM(0xfcff0300, 0x27),
+        DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
+};
+
+#define r7s72100_register_mtu2(idx)                                     \
+        platform_device_register_resndata(&platform_bus, "sh_mtu2",     \
+                                          idx, mtu2_##idx##_resources,  \
+                                          ARRAY_SIZE(mtu2_##idx##_resources), \
+                                          &mtu2_##idx##_platform_data,  \
+                                          sizeof(struct sh_timer_config))
 
 void __init r7s72100_add_dt_devices(void)
 {
-        r7s72100_register_scif(SCIF0);
-        r7s72100_register_scif(SCIF1);
-        r7s72100_register_scif(SCIF2);
-        r7s72100_register_scif(SCIF3);
-        r7s72100_register_scif(SCIF4);
-        r7s72100_register_scif(SCIF5);
-        r7s72100_register_scif(SCIF6);
-        r7s72100_register_scif(SCIF7);
+        r7s72100_register_scif(0);
+        r7s72100_register_scif(1);
+        r7s72100_register_scif(2);
+        r7s72100_register_scif(3);
+        r7s72100_register_scif(4);
+        r7s72100_register_scif(5);
+        r7s72100_register_scif(6);
+        r7s72100_register_scif(7);
+        r7s72100_register_mtu2(0);
 }
 
 void __init r7s72100_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b0f2749071be..cd36f8078325 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
                                         ARRAY_SIZE(pfc_resources));
 }
 
-#define SCIF_COMMON(scif_type, baseaddr, irq)                   \
+#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq)   \
+static struct plat_sci_port scif##index##_platform_data = {     \
         .type           = scif_type,                            \
-        .mapbase        = baseaddr,                             \
         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
-        .scbrr_algo_id  = SCBRR_ALGO_4,                         \
-        .irqs           = SCIx_IRQ_MUXED(irq)
-
-#define SCIFA_DATA(index, baseaddr, irq)                \
-[index] = {                                             \
-        SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
-        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
+        .scscr          = _scscr,                               \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
 }
 
-#define SCIFB_DATA(index, baseaddr, irq)        \
-[index] = {                                     \
-        SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
-        .scscr = SCSCR_RE | SCSCR_TE,           \
-}
+#define R8A73A4_SCIFA(index, baseaddr, irq)     \
+        R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
+                     index, baseaddr, irq)
 
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
+#define R8A73A4_SCIFB(index, baseaddr, irq)     \
+        R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
+                     index, baseaddr, irq)
 
-static const struct plat_sci_port scif[] = {
-        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
-        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
-        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
-        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
-        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
-        SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
-};
+R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
+R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
+R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
+R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
+R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
+R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
 
-static inline void r8a73a4_register_scif(int idx)
-{
-        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
-                                      sizeof(struct plat_sci_port));
-}
+#define r8a73a4_register_scif(index)                                           \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 
 static const struct renesas_irqc_config irqc0_data = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
 
 void __init r8a73a4_add_dt_devices(void)
 {
-        r8a73a4_register_scif(SCIFA0);
-        r8a73a4_register_scif(SCIFA1);
-        r8a73a4_register_scif(SCIFB0);
-        r8a73a4_register_scif(SCIFB1);
-        r8a73a4_register_scif(SCIFB2);
-        r8a73a4_register_scif(SCIFB3);
+        r8a73a4_register_scif(0);
+        r8a73a4_register_scif(1);
+        r8a73a4_register_scif(2);
+        r8a73a4_register_scif(3);
+        r8a73a4_register_scif(4);
+        r8a73a4_register_scif(5);
         r8a7790_register_cmt(10);
 }
 
@@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = {
 
 static struct resource dma_resources[] = {
         DEFINE_RES_MEM(0xe6700020, 0x89e0),
-        DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
+        DEFINE_RES_IRQ(gic_spi(220)),
         {
                 /* IRQ for channels 0-19 */
                 .start  = gic_spi(200),
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index b7d4b2c3bc29..8f3c68101d59 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
         },
 };
 
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(100)),
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(101)),
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(102)),
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(103)),
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(104)),
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(105)),
-};
-
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-
-/* SCIFA6 */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6cc0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(106)),
-};
-
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-
-/* SCIFA7 */
-static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xe6cd0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(107)),
-};
-
-static struct platform_device scif7_device = {
-        .name           = "sh-sci",
-        .id             = 7,
-        .dev            = {
-                .platform_data  = &scif7_platform_data,
-        },
-};
-
-/* SCIFB */
-static struct plat_sci_port scifb_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(108)),
-};
+/* SCIF */
+#define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
+static struct plat_sci_port scif##index##_platform_data = {     \
+        .type           = scif_type,                            \
+        .flags          = UPF_BOOT_AUTOCONF,                    \
+        .scscr          = SCSCR_RE | SCSCR_TE,                  \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
+};                                                              \
+                                                                \
+static struct platform_device scif##index##_device = {          \
+        .name           = "sh-sci",                             \
+        .id             = index,                                \
+        .resource       = scif##index##_resources,              \
+        .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
+        .dev            = {                                     \
+                .platform_data  = &scif##index##_platform_data, \
+        },                                                      \
+}
 
-static struct platform_device scifb_device = {
-        .name           = "sh-sci",
-        .id             = 8,
-        .dev            = {
-                .platform_data  = &scifb_platform_data,
-        },
-};
+R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
+R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
+R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
+R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
+R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
+R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
+R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
+R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
+R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 
 /* CMT */
 static struct sh_timer_config cmt10_platform_data = {
@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
         &scif5_device,
         &scif6_device,
         &scif7_device,
-        &scifb_device,
+        &scif8_device,
         &cmt10_device,
 };
 
@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
         rmobile_add_device_to_domain("A3SP",    &scif5_device);
         rmobile_add_device_to_domain("A3SP",    &scif6_device);
         rmobile_add_device_to_domain("A3SP",    &scif7_device);
-        rmobile_add_device_to_domain("A3SP",    &scifb_device);
+        rmobile_add_device_to_domain("A3SP",    &scif8_device);
         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 03fcc5974ef9..6d694526e4ca 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -44,24 +44,31 @@
 #include <asm/hardware/cache-l2x0.h>
 
 /* SCIF */
-#define SCIF_INFO(baseaddr, irq)                                \
-{                                                               \
-        .mapbase        = baseaddr,                             \
+#define R8A7778_SCIF(index, baseaddr, irq)                      \
+static struct plat_sci_port scif##index##_platform_data = {     \
         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
-        .scbrr_algo_id  = SCBRR_ALGO_2,                         \
         .type           = PORT_SCIF,                            \
-        .irqs           = SCIx_IRQ_MUXED(irq),                  \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
 }
 
-static struct plat_sci_port scif_platform_data[] __initdata = {
-        SCIF_INFO(0xffe40000, gic_iid(0x66)),
-        SCIF_INFO(0xffe41000, gic_iid(0x67)),
-        SCIF_INFO(0xffe42000, gic_iid(0x68)),
-        SCIF_INFO(0xffe43000, gic_iid(0x69)),
-        SCIF_INFO(0xffe44000, gic_iid(0x6a)),
-        SCIF_INFO(0xffe45000, gic_iid(0x6b)),
-};
+R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
+R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
+R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
+R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
+R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
+R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
+
+#define r8a7778_register_scif(index)                                           \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 
 /* TMU */
 static struct resource sh_tmu0_resources[] __initdata = {
@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
 
 void __init r8a7778_add_dt_devices(void)
 {
-        int i;
-
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
         if (base) {
@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
         }
 #endif
 
-        for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
-                platform_device_register_data(&platform_bus, "sh-sci", i,
-                                              &scif_platform_data[i],
-                                              sizeof(struct plat_sci_port));
-
+        r8a7778_register_scif(0);
+        r8a7778_register_scif(1);
+        r8a7778_register_scif(2);
+        r8a7778_register_scif(3);
+        r8a7778_register_scif(4);
+        r8a7778_register_scif(5);
         r8a7778_register_tmu(0);
         r8a7778_register_tmu(1);
 }
@@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void)
 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)  /* SDHI0 */
 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI  0       /* SDHI0 */
 
+#define HPBDMA_SSI(_id)                         \
+{                                               \
+        .id     = HPBDMA_SLAVE_SSI## _id ##_TX, \
+        .addr   = 0xffd91008 + (_id * 0x40),    \
+        .dcr    = HPB_DMAE_DCR_CT |             \
+                  HPB_DMAE_DCR_DIP |            \
+                  HPB_DMAE_DCR_SPDS_32BIT |     \
+                  HPB_DMAE_DCR_DMDL |           \
+                  HPB_DMAE_DCR_DPDS_32BIT,      \
+        .port   = _id + (_id << 8),             \
+        .dma_ch = (28 + _id),                   \
+}, {                                            \
+        .id     = HPBDMA_SLAVE_SSI## _id ##_RX, \
+        .addr   = 0xffd9100c + (_id * 0x40),    \
+        .dcr    = HPB_DMAE_DCR_CT |             \
+                  HPB_DMAE_DCR_DIP |            \
+                  HPB_DMAE_DCR_SMDL |           \
+                  HPB_DMAE_DCR_SPDS_32BIT |     \
+                  HPB_DMAE_DCR_DPDS_32BIT,      \
+        .port   = _id + (_id << 8),             \
+        .dma_ch = (28 + _id),                   \
+}
+
+#define HPBDMA_HPBIF(_id)                               \
+{                                                       \
+        .id     = HPBDMA_SLAVE_HPBIF## _id ##_TX,       \
+        .addr   = 0xffda0000 + (_id * 0x1000),          \
+        .dcr    = HPB_DMAE_DCR_CT |                     \
+                  HPB_DMAE_DCR_DIP |                    \
+                  HPB_DMAE_DCR_SPDS_32BIT |             \
+                  HPB_DMAE_DCR_DMDL |                   \
+                  HPB_DMAE_DCR_DPDS_32BIT,              \
+        .port   = 0x1111,                               \
+        .dma_ch = (28 + _id),                           \
+}, {                                                    \
+        .id     = HPBDMA_SLAVE_HPBIF## _id ##_RX,       \
+        .addr   = 0xffda0000 + (_id * 0x1000),          \
+        .dcr    = HPB_DMAE_DCR_CT |                     \
+                  HPB_DMAE_DCR_DIP |                    \
+                  HPB_DMAE_DCR_SMDL |                   \
+                  HPB_DMAE_DCR_SPDS_32BIT |             \
+                  HPB_DMAE_DCR_DPDS_32BIT,              \
+        .port   = 0x1111,                               \
+        .dma_ch = (28 + _id),                           \
+}
+
 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
         {
                 .id     = HPBDMA_SLAVE_SDHI0_TX,
@@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
                 .port   = 0x0D0C,
                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
                 .dma_ch = 22,
+        }, {
+                .id     = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
+                .addr   = 0xffe60018,
+                .dcr    = HPB_DMAE_DCR_SPDS_32BIT |
+                          HPB_DMAE_DCR_DMDL |
+                          HPB_DMAE_DCR_DPDS_32BIT,
+                .port   = 0x0000,
+                .dma_ch = 14,
+        }, {
+                .id     = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
+                .addr   = 0xffe6001c,
+                .dcr    = HPB_DMAE_DCR_SMDL |
+                          HPB_DMAE_DCR_SPDS_32BIT |
+                          HPB_DMAE_DCR_DPDS_32BIT,
+                .port   = 0x0101,
+                .dma_ch = 15,
         },
+
+        HPBDMA_SSI(0),
+        HPBDMA_SSI(1),
+        HPBDMA_SSI(2),
+        HPBDMA_SSI(3),
+        HPBDMA_SSI(4),
+        HPBDMA_SSI(5),
+        HPBDMA_SSI(6),
+        HPBDMA_SSI(7),
+        HPBDMA_SSI(8),
+
+        HPBDMA_HPBIF(0),
+        HPBDMA_HPBIF(1),
+        HPBDMA_HPBIF(2),
+        HPBDMA_HPBIF(3),
+        HPBDMA_HPBIF(4),
+        HPBDMA_HPBIF(5),
+        HPBDMA_HPBIF(6),
+        HPBDMA_HPBIF(7),
+        HPBDMA_HPBIF(8),
 };
 
 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
+        HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
+        HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
+        HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
 };
 
 static struct hpb_dmae_pdata dma_platform_data __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 13049e9d691c..8e860b36997a 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 }
 
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe40000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe41000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe42000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xffe43000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xffe44000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xffe45000,
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
-};
+/* SCIF */
+#define R8A7779_SCIF(index, baseaddr, irq)                      \
+static struct plat_sci_port scif##index##_platform_data = {     \
+        .type           = PORT_SCIF,                            \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
+};                                                              \
+                                                                \
+static struct platform_device scif##index##_device = {          \
+        .name           = "sh-sci",                             \
+        .id             = index,                                \
+        .resource       = scif##index##_resources,              \
+        .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
+        .dev            = {                                     \
+                .platform_data  = &scif##index##_platform_data, \
+        },                                                      \
+}
 
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
+R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
+R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
+R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
+R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
+R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
+R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 
 /* TMU */
 static struct sh_timer_config tmu00_platform_data = {
@@ -598,45 +526,6 @@ static struct platform_device ohci1_device = {
         .resource       = ohci1_resources,
 };
 
-/* Ether */
-static struct resource ether_resources[] __initdata = {
-        {
-                .start  = 0xfde00000,
-                .end    = 0xfde003ff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = gic_iid(0xb4),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-#define R8A7779_VIN(idx) \
-static struct resource vin##idx##_resources[] __initdata = {            \
-        DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),            \
-        DEFINE_RES_IRQ(gic_iid(0x5f + (idx))),                          \
-};                                                                      \
-                                                                        \
-static struct platform_device_info vin##idx##_info __initdata = {       \
-        .parent         = &platform_bus,                                \
-        .name           = "r8a7779-vin",                                \
-        .id             = idx,                                          \
-        .res            = vin##idx##_resources,                         \
-        .num_res        = ARRAY_SIZE(vin##idx##_resources),             \
-        .dma_mask       = DMA_BIT_MASK(32),                             \
-}
-
-R8A7779_VIN(0);
-R8A7779_VIN(1);
-R8A7779_VIN(2);
-R8A7779_VIN(3);
-
-static struct platform_device_info *vin_info_table[] __initdata = {
-        &vin0_info,
-        &vin1_info,
-        &vin2_info,
-        &vin3_info,
-};
-
 /* HPB-DMA */
 
 /* Asynchronous mode register bits */
@@ -825,24 +714,6 @@ void __init r8a7779_add_standard_devices(void)
         r8a7779_register_hpb_dmae();
 }
 
-void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
-{
-        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          pdata, sizeof(*pdata));
-}
-
-void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
-{
-        BUG_ON(id < 0 || id > 3);
-
-        vin_info_table[id]->data = pdata;
-        vin_info_table[id]->size_data = sizeof(*pdata);
-
-        platform_device_register_full(vin_info_table[id]);
-}
-
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c47bcebbcb00..6ab37aa1e919 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -34,6 +34,10 @@ static const struct resource pfc_resources[] __initconst = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
 };
 
+#define r8a7790_register_pfc()                                          \
+        platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
+                                        ARRAY_SIZE(pfc_resources))
+
 #define R8A7790_GPIO(idx)                                               \
 static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
         DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
@@ -63,73 +67,87 @@ R8A7790_GPIO(5);
                 &r8a7790_gpio##idx##_platform_data,                     \
                 sizeof(r8a7790_gpio##idx##_platform_data))
 
+static struct resource i2c_resources[] __initdata = {
+        /* I2C0 */
+        DEFINE_RES_MEM(0xE6508000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(287)),
+        /* I2C1 */
+        DEFINE_RES_MEM(0xE6518000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(288)),
+        /* I2C2 */
+        DEFINE_RES_MEM(0xE6530000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(286)),
+        /* I2C3 */
+        DEFINE_RES_MEM(0xE6540000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(290)),
+
+};
+
+#define r8a7790_register_i2c(idx)               \
+        platform_device_register_simple(        \
+                "i2c-rcar_gen2", idx,           \
+                i2c_resources + (2 * idx), 2);  \
+
 void __init r8a7790_pinmux_init(void)
 {
-        platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
-                                        ARRAY_SIZE(pfc_resources));
+        r8a7790_register_pfc();
         r8a7790_register_gpio(0);
         r8a7790_register_gpio(1);
         r8a7790_register_gpio(2);
         r8a7790_register_gpio(3);
         r8a7790_register_gpio(4);
         r8a7790_register_gpio(5);
+        r8a7790_register_i2c(0);
+        r8a7790_register_i2c(1);
+        r8a7790_register_i2c(2);
+        r8a7790_register_i2c(3);
 }
 
-#define SCIF_COMMON(scif_type, baseaddr, irq)                   \
-        .type           = scif_type,                            \
-        .mapbase        = baseaddr,                             \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
-        .irqs           = SCIx_IRQ_MUXED(irq)
-
-#define SCIFA_DATA(index, baseaddr, irq)                \
-[index] = {                                             \
-        SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
-        .scbrr_algo_id  = SCBRR_ALGO_4,                 \
-        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
-}
-
-#define SCIFB_DATA(index, baseaddr, irq)        \
-[index] = {                                     \
-        SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
-        .scbrr_algo_id  = SCBRR_ALGO_4,         \
-        .scscr = SCSCR_RE | SCSCR_TE,           \
-}
-
-#define SCIF_DATA(index, baseaddr, irq)         \
-[index] = {                                             \
-        SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
-        .scbrr_algo_id  = SCBRR_ALGO_2,                 \
-        .scscr = SCSCR_RE | SCSCR_TE,   \
-}
-
-#define HSCIF_DATA(index, baseaddr, irq)                \
-[index] = {                                             \
-        SCIF_COMMON(PORT_HSCIF, baseaddr, irq),         \
-        .scbrr_algo_id  = SCBRR_ALGO_6,                 \
-        .scscr = SCSCR_RE | SCSCR_TE,   \
+#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)         \
+static struct plat_sci_port scif##index##_platform_data = {             \
+        .type           = scif_type,                                    \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
+        .scscr          = _scscr,                                       \
+};                                                                      \
+                                                                        \
+static struct resource scif##index##_resources[] = {                    \
+        DEFINE_RES_MEM(baseaddr, 0x100),                                \
+        DEFINE_RES_IRQ(irq),                                            \
 }
 
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
-       HSCIF0, HSCIF1 };
-
-static const struct plat_sci_port scif[] __initconst = {
-        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
-        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
-        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
-        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
-        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
-        SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
-        SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
-        SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
-        HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
-        HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
-};
-
-static inline void r8a7790_register_scif(int idx)
-{
-        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
-                                      sizeof(struct plat_sci_port));
-}
+#define R8A7790_SCIF(index, baseaddr, irq)                              \
+        __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE,                  \
+                       index, baseaddr, irq)
+
+#define R8A7790_SCIFA(index, baseaddr, irq)                             \
+        __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0,    \
+                       index, baseaddr, irq)
+
+#define R8A7790_SCIFB(index, baseaddr, irq)                             \
+        __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE,                 \
+                       index, baseaddr, irq)
+
+#define R8A7790_HSCIF(index, baseaddr, irq)                             \
+        __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE,                 \
+                       index, baseaddr, irq)
+
+R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
+R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
+R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
+R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
+R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
+R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
+R8A7790_SCIF(6,  0xe6e60000, gic_spi(152)); /* SCIF0 */
+R8A7790_SCIF(7,  0xe6e68000, gic_spi(153)); /* SCIF1 */
+R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
+R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
+
+#define r8a7790_register_scif(index)                                           \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 
 static const struct renesas_irqc_config irqc0_data __initconst = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
@@ -182,16 +200,16 @@ static const struct resource cmt00_resources[] __initconst = {
 
 void __init r8a7790_add_dt_devices(void)
 {
-        r8a7790_register_scif(SCIFA0);
-        r8a7790_register_scif(SCIFA1);
-        r8a7790_register_scif(SCIFB0);
-        r8a7790_register_scif(SCIFB1);
-        r8a7790_register_scif(SCIFB2);
-        r8a7790_register_scif(SCIFA2);
-        r8a7790_register_scif(SCIF0);
-        r8a7790_register_scif(SCIF1);
-        r8a7790_register_scif(HSCIF0);
-        r8a7790_register_scif(HSCIF1);
+        r8a7790_register_scif(0);
+        r8a7790_register_scif(1);
+        r8a7790_register_scif(2);
+        r8a7790_register_scif(3);
+        r8a7790_register_scif(4);
+        r8a7790_register_scif(5);
+        r8a7790_register_scif(6);
+        r8a7790_register_scif(7);
+        r8a7790_register_scif(8);
+        r8a7790_register_scif(9);
         r8a7790_register_cmt(00);
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d9393d61ee27..e28404e43860 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -22,6 +22,7 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
@@ -31,66 +32,101 @@
 #include <mach/rcar-gen2.h>
 #include <asm/mach/arch.h>
 
-#define SCIF_COMMON(scif_type, baseaddr, irq)                   \
-        .type           = scif_type,                            \
-        .mapbase        = baseaddr,                             \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
-        .irqs           = SCIx_IRQ_MUXED(irq)
-
-#define SCIFA_DATA(index, baseaddr, irq)                \
-[index] = {                                             \
-        SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
-        .scbrr_algo_id  = SCBRR_ALGO_4,                 \
-        .scscr = SCSCR_RE | SCSCR_TE,   \
-}
-
-#define SCIFB_DATA(index, baseaddr, irq)        \
-[index] = {                                     \
-        SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
-        .scbrr_algo_id  = SCBRR_ALGO_4,         \
-        .scscr = SCSCR_RE | SCSCR_TE,           \
-}
+static const struct resource pfc_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe6060000, 0x250),
+};
 
-#define SCIF_DATA(index, baseaddr, irq)         \
-[index] = {                                             \
-        SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
-        .scbrr_algo_id  = SCBRR_ALGO_2,                 \
-        .scscr = SCSCR_RE | SCSCR_TE,   \
+#define r8a7791_register_pfc()                                          \
+        platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
+                                        ARRAY_SIZE(pfc_resources))
+
+#define R8A7791_GPIO(idx, base, nr)                                     \
+static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
+        DEFINE_RES_MEM((base), 0x50),                                   \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static const struct gpio_rcar_config                                    \
+r8a7791_gpio##idx##_platform_data __initconst = {                       \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = (nr),                                         \
+        .pctl_name      = "pfc-r8a7791",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+
+R8A7791_GPIO(0, 0xe6050000, 32);
+R8A7791_GPIO(1, 0xe6051000, 32);
+R8A7791_GPIO(2, 0xe6052000, 32);
+R8A7791_GPIO(3, 0xe6053000, 32);
+R8A7791_GPIO(4, 0xe6054000, 32);
+R8A7791_GPIO(5, 0xe6055000, 32);
+R8A7791_GPIO(6, 0xe6055400, 32);
+R8A7791_GPIO(7, 0xe6055800, 26);
+
+#define r8a7791_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7791_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7791_gpio##idx##_resources),              \
+                &r8a7791_gpio##idx##_platform_data,                     \
+                sizeof(r8a7791_gpio##idx##_platform_data))
+
+void __init r8a7791_pinmux_init(void)
+{
+        r8a7791_register_pfc();
+        r8a7791_register_gpio(0);
+        r8a7791_register_gpio(1);
+        r8a7791_register_gpio(2);
+        r8a7791_register_gpio(3);
+        r8a7791_register_gpio(4);
+        r8a7791_register_gpio(5);
+        r8a7791_register_gpio(6);
+        r8a7791_register_gpio(7);
 }
 
-#define HSCIF_DATA(index, baseaddr, irq)                \
-[index] = {                                             \
-        SCIF_COMMON(PORT_HSCIF, baseaddr, irq),         \
-        .scbrr_algo_id  = SCBRR_ALGO_6,                 \
-        .scscr = SCSCR_RE | SCSCR_TE,   \
+#define __R8A7791_SCIF(scif_type, index, baseaddr, irq)                 \
+static struct plat_sci_port scif##index##_platform_data = {             \
+        .type           = scif_type,                                    \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
+        .scscr          = SCSCR_RE | SCSCR_TE,                          \
+};                                                                      \
+                                                                        \
+static struct resource scif##index##_resources[] = {                    \
+        DEFINE_RES_MEM(baseaddr, 0x100),                                \
+        DEFINE_RES_IRQ(irq),                                            \
 }
 
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
-        SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
-
-static const struct plat_sci_port scif[] __initconst = {
-        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
-        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
-        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
-        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
-        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
-        SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
-        SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
-        SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
-        SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
-        SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
-        SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
-        SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
-        SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
-        SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
-        SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
-};
-
-static inline void r8a7791_register_scif(int idx)
-{
-        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
-                                      sizeof(struct plat_sci_port));
-}
+#define R8A7791_SCIF(index, baseaddr, irq)                              \
+        __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
+
+#define R8A7791_SCIFA(index, baseaddr, irq)                             \
+        __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
+
+#define R8A7791_SCIFB(index, baseaddr, irq)                             \
+        __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
+
+R8A7791_SCIFA(0,  0xe6c40000, gic_spi(144)); /* SCIFA0 */
+R8A7791_SCIFA(1,  0xe6c50000, gic_spi(145)); /* SCIFA1 */
+R8A7791_SCIFB(2,  0xe6c20000, gic_spi(148)); /* SCIFB0 */
+R8A7791_SCIFB(3,  0xe6c30000, gic_spi(149)); /* SCIFB1 */
+R8A7791_SCIFB(4,  0xe6ce0000, gic_spi(150)); /* SCIFB2 */
+R8A7791_SCIFA(5,  0xe6c60000, gic_spi(151)); /* SCIFA2 */
+R8A7791_SCIF(6,   0xe6e60000, gic_spi(152)); /* SCIF0 */
+R8A7791_SCIF(7,   0xe6e68000, gic_spi(153)); /* SCIF1 */
+R8A7791_SCIF(8,   0xe6e58000, gic_spi(22)); /* SCIF2 */
+R8A7791_SCIF(9,   0xe6ea8000, gic_spi(23)); /* SCIF3 */
+R8A7791_SCIF(10,  0xe6ee0000, gic_spi(24)); /* SCIF4 */
+R8A7791_SCIF(11,  0xe6ee8000, gic_spi(25)); /* SCIF5 */
+R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
+R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
+R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
+
+#define r8a7791_register_scif(index)                                           \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 
 static const struct sh_timer_config cmt00_platform_data __initconst = {
         .name = "CMT00",
@@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = {
                                           &irqc##idx##_data,            \
                                           sizeof(struct renesas_irqc_config))
 
+static const struct resource thermal_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe61f0000, 0x14),
+        DEFINE_RES_MEM(0xe61f0100, 0x38),
+        DEFINE_RES_IRQ(gic_spi(69)),
+};
+
+#define r8a7791_register_thermal()                                      \
+        platform_device_register_simple("rcar_thermal", -1,             \
+                                        thermal_resources,              \
+                                        ARRAY_SIZE(thermal_resources))
+
 void __init r8a7791_add_dt_devices(void)
 {
-        r8a7791_register_scif(SCIFA0);
-        r8a7791_register_scif(SCIFA1);
-        r8a7791_register_scif(SCIFB0);
-        r8a7791_register_scif(SCIFB1);
-        r8a7791_register_scif(SCIFB2);
-        r8a7791_register_scif(SCIFA2);
-        r8a7791_register_scif(SCIF0);
-        r8a7791_register_scif(SCIF1);
-        r8a7791_register_scif(SCIF2);
-        r8a7791_register_scif(SCIF3);
-        r8a7791_register_scif(SCIF4);
-        r8a7791_register_scif(SCIF5);
-        r8a7791_register_scif(SCIFA3);
-        r8a7791_register_scif(SCIFA4);
-        r8a7791_register_scif(SCIFA5);
+        r8a7791_register_scif(0);
+        r8a7791_register_scif(1);
+        r8a7791_register_scif(2);
+        r8a7791_register_scif(3);
+        r8a7791_register_scif(4);
+        r8a7791_register_scif(5);
+        r8a7791_register_scif(6);
+        r8a7791_register_scif(7);
+        r8a7791_register_scif(8);
+        r8a7791_register_scif(9);
+        r8a7791_register_scif(10);
+        r8a7791_register_scif(11);
+        r8a7791_register_scif(12);
+        r8a7791_register_scif(13);
+        r8a7791_register_scif(14);
         r8a7791_register_cmt(00);
 }
 
@@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void)
 {
         r8a7791_add_dt_devices();
         r8a7791_register_irqc(0);
+        r8a7791_register_thermal();
 }
 
 void __init r8a7791_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5734c24bf6c7..69ccc6c6fd33 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk/shmobile.h>
 #include <linux/clocksource.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
 
 void __init rcar_gen2_timer_init(void)
 {
-#ifdef CONFIG_ARM_ARCH_TIMER
+#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
         u32 mode = rcar_gen2_read_mode_pins();
+#endif
+#ifdef CONFIG_ARM_ARCH_TIMER
         void __iomem *base;
         int extal_mhz = 0;
         u32 freq;
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
         /* Remap "armgcnt address map" space */
         base = ioremap(0xe6080000, PAGE_SIZE);
 
-        /* Update registers with correct frequency */
-        iowrite32(freq, base + CNTFID0);
-        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+        /*
+         * Update the timer if it is either not running, or is not at the
+         * right frequency. The timer is only configurable in secure mode
+         * so this avoids an abort if the loader started the timer and
+         * entered the kernel in non-secure mode.
+         */
+
+        if ((ioread32(base + CNTCR) & 1) == 0 ||
+            ioread32(base + CNTFID0) != freq) {
+                /* Update registers with correct frequency */
+                iowrite32(freq, base + CNTFID0);
+                asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+                /* make sure arch timer is started by setting bit 0 of CNTCR */
+                iowrite32(1, base + CNTCR);
+        }
 
-        /* make sure arch timer is started by setting bit 0 of CNTCR */
-        iowrite32(1, base + CNTCR);
         iounmap(base);
 #endif /* CONFIG_ARM_ARCH_TIMER */
 
+#ifdef CONFIG_COMMON_CLK
+        rcar_gen2_clocks_init(mode);
+#endif
         clocksource_of_init();
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 311878391e18..27301278c208 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
         platform_device_register(&sh7372_pfc_device);
 }
 
-/* SCIFA0 */
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
-                            evt2irq(0x0c00), evt2irq(0x0c00) },
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-/* SCIFA1 */
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
-                            evt2irq(0x0c20), evt2irq(0x0c20) },
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-/* SCIFA2 */
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
-                            evt2irq(0x0c40), evt2irq(0x0c40) },
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-/* SCIFA3 */
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
-                            evt2irq(0x0c60), evt2irq(0x0c60) },
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-/* SCIFA4 */
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
-                            evt2irq(0x0d20), evt2irq(0x0d20) },
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-/* SCIFA5 */
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
-                            evt2irq(0x0d40), evt2irq(0x0d40) },
-};
-
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-
-/* SCIFB */
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
-                            evt2irq(0x0d60), evt2irq(0x0d60) },
-};
+/* SCIF */
+#define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
+static struct plat_sci_port scif##index##_platform_data = {     \
+        .type           = scif_type,                            \
+        .flags          = UPF_BOOT_AUTOCONF,                    \
+        .scscr          = SCSCR_RE | SCSCR_TE,                  \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
+};                                                              \
+                                                                \
+static struct platform_device scif##index##_device = {          \
+        .name           = "sh-sci",                             \
+        .id             = index,                                \
+        .resource       = scif##index##_resources,              \
+        .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
+        .dev            = {                                     \
+                .platform_data  = &scif##index##_platform_data, \
+        },                                                      \
+}
 
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
+SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
+SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
+SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
+SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
+SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
+SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
+SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 
 /* CMT */
 static struct sh_timer_config cmt2_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 22de17417fd7..f74ab530c71d 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
                                         ARRAY_SIZE(pfc_resources));
 }
 
-static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe6c40000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(72), gic_spi(72),
-                            gic_spi(72), gic_spi(72) },
-};
-
-static struct platform_device scif0_device = {
-        .name           = "sh-sci",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &scif0_platform_data,
-        },
-};
-
-static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe6c50000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(73), gic_spi(73),
-                            gic_spi(73), gic_spi(73) },
-};
-
-static struct platform_device scif1_device = {
-        .name           = "sh-sci",
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &scif1_platform_data,
-        },
-};
-
-static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe6c60000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(74), gic_spi(74),
-                            gic_spi(74), gic_spi(74) },
-};
-
-static struct platform_device scif2_device = {
-        .name           = "sh-sci",
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &scif2_platform_data,
-        },
-};
-
-static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe6c70000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(75), gic_spi(75),
-                            gic_spi(75), gic_spi(75) },
-};
-
-static struct platform_device scif3_device = {
-        .name           = "sh-sci",
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &scif3_platform_data,
-        },
-};
-
-static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe6c80000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(78), gic_spi(78),
-                            gic_spi(78), gic_spi(78) },
-};
-
-static struct platform_device scif4_device = {
-        .name           = "sh-sci",
-        .id             = 4,
-        .dev            = {
-                .platform_data  = &scif4_platform_data,
-        },
-};
-
-static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe6cb0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(79), gic_spi(79),
-                            gic_spi(79), gic_spi(79) },
-};
-
-static struct platform_device scif5_device = {
-        .name           = "sh-sci",
-        .id             = 5,
-        .dev            = {
-                .platform_data  = &scif5_platform_data,
-        },
-};
-
-static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe6cc0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(156), gic_spi(156),
-                            gic_spi(156), gic_spi(156) },
-};
-
-static struct platform_device scif6_device = {
-        .name           = "sh-sci",
-        .id             = 6,
-        .dev            = {
-                .platform_data  = &scif6_platform_data,
-        },
-};
-
-static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xe6cd0000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFA,
-        .irqs           = { gic_spi(143), gic_spi(143),
-                            gic_spi(143), gic_spi(143) },
-};
-
-static struct platform_device scif7_device = {
-        .name           = "sh-sci",
-        .id             = 7,
-        .dev            = {
-                .platform_data  = &scif7_platform_data,
-        },
-};
-
-static struct plat_sci_port scif8_platform_data = {
-        .mapbase        = 0xe6c30000,
-        .flags          = UPF_BOOT_AUTOCONF,
-        .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIFB,
-        .irqs           = { gic_spi(80), gic_spi(80),
-                            gic_spi(80), gic_spi(80) },
-};
+/* SCIF */
+#define SH73A0_SCIF(scif_type, index, baseaddr, irq)            \
+static struct plat_sci_port scif##index##_platform_data = {     \
+        .type           = scif_type,                            \
+        .flags          = UPF_BOOT_AUTOCONF,                    \
+        .scscr          = SCSCR_RE | SCSCR_TE,                  \
+};                                                              \
+                                                                \
+static struct resource scif##index##_resources[] = {            \
+        DEFINE_RES_MEM(baseaddr, 0x100),                        \
+        DEFINE_RES_IRQ(irq),                                    \
+};                                                              \
+                                                                \
+static struct platform_device scif##index##_device = {          \
+        .name           = "sh-sci",                             \
+        .id             = index,                                \
+        .resource       = scif##index##_resources,              \
+        .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
+        .dev            = {                                     \
+                .platform_data  = &scif##index##_platform_data, \
+        },                                                      \
+}
 
-static struct platform_device scif8_device = {
-        .name           = "sh-sci",
-        .id             = 8,
-        .dev            = {
-                .platform_data  = &scif8_platform_data,
-        },
-};
+SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
+SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
+SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
+SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
+SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
+SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
+SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
+SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
+SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
 
 static struct sh_timer_config cmt10_platform_data = {
         .name = "CMT10",
@@ -273,7 +144,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
+        [0] = DEFINE_RES_MEM(0xfff60008, 0xc),
         [1] = {
                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                 .flags  = IORESOURCE_IRQ,
@@ -298,7 +169,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
+        [0] = DEFINE_RES_MEM(0xfff60014, 0xc),
         [1] = {
                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                 .flags  = IORESOURCE_IRQ,
@@ -316,7 +187,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
+        [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
         [1] = {
                 .start  = gic_spi(167),
                 .end    = gic_spi(170),
@@ -325,7 +196,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
+        [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
         [1] = {
                 .start  = gic_spi(51),
                 .end    = gic_spi(54),
@@ -334,7 +205,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
+        [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
         [1] = {
                 .start  = gic_spi(171),
                 .end    = gic_spi(174),
@@ -343,7 +214,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
+        [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
         [1] = {
                 .start  = gic_spi(183),
                 .end    = gic_spi(186),
@@ -352,7 +223,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
+        [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
         [1] = {
                 .start  = gic_spi(187),
                 .end    = gic_spi(190),
@@ -722,7 +593,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
+        DEFINE_RES_MEM(0xfe951000, 0x100),
 };
 
 static const char * const ipmmu_dev_names[] = {
diff --git a/arch/arm/mach-shmobile/sh-gpio.h b/arch/arm/mach-shmobile/sh-gpio.h
index e834763ac2a5..2c4141413db9 100644
--- a/arch/arm/mach-shmobile/sh-gpio.h
+++ b/arch/arm/mach-shmobile/sh-gpio.h
@@ -26,23 +26,4 @@ static inline void __init gpio_direction_none(void __iomem * addr)
         __raw_writeb(0x00, addr);
 }
 
-static inline void __init gpio_request_pullup(void __iomem * addr)
-{
-        u8 data = __raw_readb(addr);
-
-        data &= 0x0F;
-        data |= 0xC0;
-        __raw_writeb(data, addr);
-}
-
-static inline void __init gpio_request_pulldown(void __iomem * addr)
-{
-        u8 data = __raw_readb(addr);
-
-        data &= 0x0F;
-        data |= 0xA0;
-
-        __raw_writeb(data, addr);
-}
-
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index dce50d983a8e..fa2c33ffac04 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -31,8 +31,7 @@ static void write_pen_release(int val)
 {
         pen_release = val;
         smp_wmb();
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 }
 
 static DEFINE_SPINLOCK(boot_lock);
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index bce0d4277f71..b9d6cad8669b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,7 +1,9 @@
 config ARCH_SUNXI
         bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+        select ARCH_HAS_RESET_CONTROLLER
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
+        select ARM_PSCI
         select CLKSRC_MMIO
         select CLKSRC_OF
         select COMMON_CLK
@@ -10,6 +12,7 @@ config ARCH_SUNXI
         select HAVE_SMP
         select PINCTRL
         select PINCTRL_SUNXI
+        select RESET_CONTROLLER
         select SPARSE_IRQ
         select SUN4I_TIMER
         select SUN5I_HSTIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc3ff9f..d9397202d6ec 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
new file mode 100644
index 000000000000..9e5ac4756cbb
--- /dev/null
+++ b/arch/arm/mach-sunxi/common.h
@@ -0,0 +1,19 @@
+/*
+ * Core functions for Allwinner SoCs
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_SUNXI_COMMON_H_
+#define __ARCH_SUNXI_COMMON_H_
+
+void sun6i_secondary_startup(void);
+extern struct smp_operations sun6i_smp_ops;
+
+#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..a10d494fb37b
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,9 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+
+ENTRY(sun6i_secondary_startup)
+        msr     cpsr_fsxc, #0xd3
+        b       secondary_startup
+ENDPROC(sun6i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 000000000000..7b141d8342a1
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,124 @@
+/*
+ * SMP support for Allwinner SoCs
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code
+ *  Copyright (C) 2012-2013 Allwinner Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/smp.h>
+
+#include "common.h"
+
+#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu)    ((cpu) * 0x40 + 0x64)
+#define CPUCFG_CPU_RST_CTRL_REG(cpu)            (((cpu) + 1) * 0x40)
+#define CPUCFG_CPU_CTRL_REG(cpu)                (((cpu) + 1) * 0x40 + 0x04)
+#define CPUCFG_CPU_STATUS_REG(cpu)              (((cpu) + 1) * 0x40 + 0x08)
+#define CPUCFG_GEN_CTRL_REG                     0x184
+#define CPUCFG_PRIVATE0_REG                     0x1a4
+#define CPUCFG_PRIVATE1_REG                     0x1a8
+#define CPUCFG_DBG_CTL0_REG                     0x1e0
+#define CPUCFG_DBG_CTL1_REG                     0x1e4
+
+#define PRCM_CPU_PWROFF_REG                     0x100
+#define PRCM_CPU_PWR_CLAMP_REG(cpu)             (((cpu) * 4) + 0x140)
+
+static void __iomem *cpucfg_membase;
+static void __iomem *prcm_membase;
+
+static DEFINE_SPINLOCK(cpu_lock);
+
+static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
+        if (!node) {
+                pr_err("Missing A31 PRCM node in the device tree\n");
+                return;
+        }
+
+        prcm_membase = of_iomap(node, 0);
+        if (!prcm_membase) {
+                pr_err("Couldn't map A31 PRCM registers\n");
+                return;
+        }
+
+        node = of_find_compatible_node(NULL, NULL,
+                                       "allwinner,sun6i-a31-cpuconfig");
+        if (!node) {
+                pr_err("Missing A31 CPU config node in the device tree\n");
+                return;
+        }
+
+        cpucfg_membase = of_iomap(node, 0);
+        if (!cpucfg_membase)
+                pr_err("Couldn't map A31 CPU config registers\n");
+
+}
+
+static int sun6i_smp_boot_secondary(unsigned int cpu,
+                                    struct task_struct *idle)
+{
+        u32 reg;
+        int i;
+
+        if (!(prcm_membase && cpucfg_membase))
+                return -EFAULT;
+
+        spin_lock(&cpu_lock);
+
+        /* Set CPU boot address */
+        writel(virt_to_phys(sun6i_secondary_startup),
+               cpucfg_membase + CPUCFG_PRIVATE0_REG);
+
+        /* Assert the CPU core in reset */
+        writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+        /* Assert the L1 cache in reset */
+        reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+        writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+
+        /* Disable external debug access */
+        reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+        writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+
+        /* Power up the CPU */
+        for (i = 0; i <= 8; i++)
+                writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
+        mdelay(10);
+
+        /* Clear CPU power-off gating */
+        reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
+        writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
+        mdelay(1);
+
+        /* Deassert the CPU core reset */
+        writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+        /* Enable back the external debug accesses */
+        reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+        writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+
+        spin_unlock(&cpu_lock);
+
+        return 0;
+}
+
+struct smp_operations sun6i_smp_ops __initdata = {
+        .smp_prepare_cpus       = sun6i_smp_prepare_cpus,
+        .smp_boot_secondary     = sun6i_smp_boot_secondary,
+};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 61d3a387f01c..aeea6ceea725 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,6 +10,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -23,6 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
+#include "common.h"
+
 #define SUN4I_WATCHDOG_CTRL_REG         0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART             BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG         0x04
@@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = {
         NULL,
 };
 
+extern void __init sun6i_reset_init(void);
+static void __init sun6i_timer_init(void)
+{
+        of_clk_init(NULL);
+        sun6i_reset_init();
+        clocksource_of_init();
+}
+
 DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
         .init_machine   = sunxi_dt_init,
+        .init_time      = sun6i_timer_init,
         .dt_compat      = sun6i_board_dt_compat,
         .restart        = sun6i_restart,
+        .smp            = smp_ops(sun6i_smp_ops),
 MACHINE_END
 
 static const char * const sun7i_board_dt_compat[] = {
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 09e740f58b27..b1232d8be6f5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,6 +2,7 @@ config ARCH_TEGRA
         bool "NVIDIA Tegra" if ARCH_MULTI_V7
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
         select ARM_GIC
         select CLKSRC_MMIO
         select CLKSRC_OF
@@ -14,6 +15,8 @@ config ARCH_TEGRA
         select MIGHT_HAVE_CACHE_L2X0
         select MIGHT_HAVE_PCI
         select PINCTRL
+        select ARCH_HAS_RESET_CONTROLLER
+        select RESET_CONTROLLER
         select SOC_BUS
         select SPARSE_IRQ
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
@@ -63,6 +66,7 @@ config ARCH_TEGRA_124_SOC
         bool "Enable support for Tegra124 family"
         select ARM_L1_CACHE_SHIFT_6
         select HAVE_ARM_ARCH_TIMER
+        select PINCTRL_TEGRA124
         help
           Support for NVIDIA Tegra T124 processor family, based on the
           ARM CortexA15MP CPU
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 06f024070dab..e4dec9fcb084 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/platform_device.h>
+#include <linux/gpio/driver.h>
 #include <linux/rfkill-gpio.h>
 #include "board.h"
 
@@ -36,7 +37,17 @@ static struct platform_device wifi_rfkill_device = {
         },
 };
 
+static struct gpiod_lookup_table wifi_gpio_lookup = {
+        .dev_id = "rfkill_gpio",
+        .table = {
+                GPIO_LOOKUP_IDX("tegra-gpio", 25, NULL, 0, 0),
+                GPIO_LOOKUP_IDX("tegra-gpio", 85, NULL, 1, 0),
+                { },
+        },
+};
+
 void __init tegra_paz00_wifikill_init(void)
 {
+        gpiod_add_lookup_table(&wifi_gpio_lookup);
         platform_device_register(&wifi_rfkill_device);
 }
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 3a9c1f1c219d..c9ac23b385be 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/random.h>
+#include <linux/clk.h>
 #include <linux/tegra-soc.h>
 
 #include "fuse.h"
@@ -54,6 +55,7 @@ int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
 int tegra_soc_speedo_id;
 enum tegra_revision tegra_revision;
 
+static struct clk *fuse_clk;
 static int tegra_fuse_spare_bit;
 static void (*tegra_init_speedo_data)(void);
 
@@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
         [TEGRA_REVISION_A04]     = "A04",
 };
 
+static void tegra_fuse_enable_clk(void)
+{
+        if (IS_ERR(fuse_clk))
+                fuse_clk = clk_get_sys(NULL, "fuse");
+        if (IS_ERR(fuse_clk))
+                return;
+        clk_prepare_enable(fuse_clk);
+}
+
+static void tegra_fuse_disable_clk(void)
+{
+        if (IS_ERR(fuse_clk))
+                return;
+        clk_disable_unprepare(fuse_clk);
+}
+
 u32 tegra_fuse_readl(unsigned long offset)
 {
         return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
@@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset)
 
 bool tegra_spare_fuse(int bit)
 {
-        return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+        bool ret;
+
+        tegra_fuse_enable_clk();
+
+        ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+
+        tegra_fuse_disable_clk();
+
+        return ret;
 }
 
 static enum tegra_revision tegra_get_revision(u32 id)
@@ -113,10 +139,14 @@ static void tegra_get_process_id(void)
 {
         u32 reg;
 
+        tegra_fuse_enable_clk();
+
         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
         tegra_cpu_process_id = (reg >> 6) & 3;
         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
         tegra_core_process_id = (reg >> 12) & 3;
+
+        tegra_fuse_disable_clk();
 }
 
 u32 tegra_read_chipid(void)
@@ -159,6 +189,15 @@ void __init tegra_init_fuse(void)
         reg |= 1 << 28;
         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
+        /*
+         * Enable FUSE clock. This needs to be hardcoded because the clock
+         * subsystem is not active during early boot.
+         */
+        reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+        reg |= 1 << 7;
+        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+        fuse_clk = ERR_PTR(-EINVAL);
+
         reg = tegra_fuse_readl(FUSE_SKU_INFO);
         randomness[0] = reg;
         tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 26b1c2ad0ceb..ee79808e93a3 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -19,6 +19,7 @@
 #ifndef __MACH_TEGRA_IOMAP_H
 #define __MACH_TEGRA_IOMAP_H
 
+#include <asm/pgtable.h>
 #include <asm/sizes.h>
 
 #define TEGRA_IRAM_BASE                 0x40000000
@@ -115,27 +116,26 @@
  * two 256MB io windows (that actually only use about 64KB
  * at the start of each).
  *
- * We will just map the first 1MB of each window (to minimize
+ * We will just map the first MMU section of each window (to minimize
  * pt entries needed) and provide a macro to transform physical
  * io addresses to an appropriate void __iomem *.
- *
  */
 
 #define IO_IRAM_PHYS    0x40000000
 #define IO_IRAM_VIRT    IOMEM(0xFE400000)
 #define IO_IRAM_SIZE    SZ_256K
 
-#define IO_CPU_PHYS     0x50040000
-#define IO_CPU_VIRT     IOMEM(0xFE000000)
+#define IO_CPU_PHYS     0x50040000
+#define IO_CPU_VIRT     IOMEM(0xFE440000)
 #define IO_CPU_SIZE     SZ_16K
 
 #define IO_PPSB_PHYS    0x60000000
 #define IO_PPSB_VIRT    IOMEM(0xFE200000)
-#define IO_PPSB_SIZE    SZ_1M
+#define IO_PPSB_SIZE    SECTION_SIZE
 
 #define IO_APB_PHYS     0x70000000
-#define IO_APB_VIRT     IOMEM(0xFE300000)
-#define IO_APB_SIZE     SZ_1M
+#define IO_APB_VIRT     IOMEM(0xFE000000)
+#define IO_APB_SIZE     SECTION_SIZE
 
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 85d28e756bb7..3d0c537d9b94 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -25,6 +25,7 @@
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/reset.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/clk/tegra.h>
@@ -33,6 +34,10 @@
 #include "fuse.h"
 #include "iomap.h"
 
+#define DPD_SAMPLE              0x020
+#define  DPD_SAMPLE_ENABLE      (1 << 0)
+#define  DPD_SAMPLE_DISABLE     (0 << 0)
+
 #define PWRGATE_TOGGLE          0x30
 #define  PWRGATE_TOGGLE_START   (1 << 8)
 
@@ -40,6 +45,19 @@
 
 #define PWRGATE_STATUS          0x38
 
+#define IO_DPD_REQ              0x1b8
+#define  IO_DPD_REQ_CODE_IDLE   (0 << 30)
+#define  IO_DPD_REQ_CODE_OFF    (1 << 30)
+#define  IO_DPD_REQ_CODE_ON     (2 << 30)
+#define  IO_DPD_REQ_CODE_MASK   (3 << 30)
+
+#define IO_DPD_STATUS           0x1bc
+#define IO_DPD2_REQ             0x1c0
+#define IO_DPD2_STATUS          0x1c4
+#define SEL_DPD_TIM             0x1c8
+
+#define GPU_RG_CNTRL            0x2d4
+
 static int tegra_num_powerdomains;
 static int tegra_num_cpu_domains;
 static const u8 *tegra_cpu_domains;
@@ -58,6 +76,13 @@ static const u8 tegra114_cpu_domains[] = {
         TEGRA_POWERGATE_CPU3,
 };
 
+static const u8 tegra124_cpu_domains[] = {
+        TEGRA_POWERGATE_CPU0,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
 static DEFINE_SPINLOCK(tegra_powergate_lock);
 
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -108,6 +133,7 @@ int tegra_powergate_power_off(int id)
 
         return tegra_powergate_set(id, false);
 }
+EXPORT_SYMBOL(tegra_powergate_power_off);
 
 int tegra_powergate_is_powered(int id)
 {
@@ -128,12 +154,23 @@ int tegra_powergate_remove_clamping(int id)
                 return -EINVAL;
 
         /*
+         * The Tegra124 GPU has a separate register (with different semantics)
+         * to remove clamps.
+         */
+        if (tegra_chip_id == TEGRA124) {
+                if (id == TEGRA_POWERGATE_3D) {
+                        pmc_write(0, GPU_RG_CNTRL);
+                        return 0;
+                }
+        }
+
+        /*
          * Tegra 2 has a bug where PCIE and VDE clamping masks are
          * swapped relatively to the partition ids
          */
-        if (id ==  TEGRA_POWERGATE_VDEC)
+        if (id == TEGRA_POWERGATE_VDEC)
                 mask = (1 << TEGRA_POWERGATE_PCIE);
-        else if (id == TEGRA_POWERGATE_PCIE)
+        else if (id == TEGRA_POWERGATE_PCIE)
                 mask = (1 << TEGRA_POWERGATE_VDEC);
         else
                 mask = (1 << id);
@@ -142,13 +179,15 @@ int tegra_powergate_remove_clamping(int id)
 
         return 0;
 }
+EXPORT_SYMBOL(tegra_powergate_remove_clamping);
 
 /* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk)
+int tegra_powergate_sequence_power_up(int id, struct clk *clk,
+                                        struct reset_control *rst)
 {
         int ret;
 
-        tegra_periph_reset_assert(clk);
+        reset_control_assert(rst);
 
         ret = tegra_powergate_power_on(id);
         if (ret)
@@ -165,7 +204,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
                 goto err_clamp;
 
         udelay(10);
-        tegra_periph_reset_deassert(clk);
+        reset_control_deassert(rst);
 
         return 0;
 
@@ -202,6 +241,11 @@ int __init tegra_powergate_init(void)
                 tegra_num_cpu_domains = 4;
                 tegra_cpu_domains = tegra114_cpu_domains;
                 break;
+        case TEGRA124:
+                tegra_num_powerdomains = 25;
+                tegra_num_cpu_domains = 4;
+                tegra_cpu_domains = tegra124_cpu_domains;
+                break;
         default:
                 /* Unknown Tegra variant. Disable powergating */
                 tegra_num_powerdomains = 0;
@@ -243,12 +287,36 @@ static const char * const powergate_name_t30[] = {
 };
 
 static const char * const powergate_name_t114[] = {
-        [TEGRA_POWERGATE_CPU]   = "cpu0",
+        [TEGRA_POWERGATE_CPU]   = "crail",
+        [TEGRA_POWERGATE_3D]    = "3d",
+        [TEGRA_POWERGATE_VENC]  = "venc",
+        [TEGRA_POWERGATE_VDEC]  = "vdec",
+        [TEGRA_POWERGATE_MPE]   = "mpe",
+        [TEGRA_POWERGATE_HEG]   = "heg",
+        [TEGRA_POWERGATE_CPU1]  = "cpu1",
+        [TEGRA_POWERGATE_CPU2]  = "cpu2",
+        [TEGRA_POWERGATE_CPU3]  = "cpu3",
+        [TEGRA_POWERGATE_CELP]  = "celp",
+        [TEGRA_POWERGATE_CPU0]  = "cpu0",
+        [TEGRA_POWERGATE_C0NC]  = "c0nc",
+        [TEGRA_POWERGATE_C1NC]  = "c1nc",
+        [TEGRA_POWERGATE_DIS]   = "dis",
+        [TEGRA_POWERGATE_DISB]  = "disb",
+        [TEGRA_POWERGATE_XUSBA] = "xusba",
+        [TEGRA_POWERGATE_XUSBB] = "xusbb",
+        [TEGRA_POWERGATE_XUSBC] = "xusbc",
+};
+
+static const char * const powergate_name_t124[] = {
+        [TEGRA_POWERGATE_CPU]   = "crail",
         [TEGRA_POWERGATE_3D]    = "3d",
         [TEGRA_POWERGATE_VENC]  = "venc",
+        [TEGRA_POWERGATE_PCIE]  = "pcie",
         [TEGRA_POWERGATE_VDEC]  = "vdec",
+        [TEGRA_POWERGATE_L2]    = "l2",
         [TEGRA_POWERGATE_MPE]   = "mpe",
         [TEGRA_POWERGATE_HEG]   = "heg",
+        [TEGRA_POWERGATE_SATA]  = "sata",
         [TEGRA_POWERGATE_CPU1]  = "cpu1",
         [TEGRA_POWERGATE_CPU2]  = "cpu2",
         [TEGRA_POWERGATE_CPU3]  = "cpu3",
@@ -256,11 +324,14 @@ static const char * const powergate_name_t114[] = {
         [TEGRA_POWERGATE_CPU0]  = "cpu0",
         [TEGRA_POWERGATE_C0NC]  = "c0nc",
         [TEGRA_POWERGATE_C1NC]  = "c1nc",
+        [TEGRA_POWERGATE_SOR]   = "sor",
         [TEGRA_POWERGATE_DIS]   = "dis",
         [TEGRA_POWERGATE_DISB]  = "disb",
         [TEGRA_POWERGATE_XUSBA] = "xusba",
         [TEGRA_POWERGATE_XUSBB] = "xusbb",
         [TEGRA_POWERGATE_XUSBC] = "xusbc",
+        [TEGRA_POWERGATE_VIC]   = "vic",
+        [TEGRA_POWERGATE_IRAM]  = "iram",
 };
 
 static int powergate_show(struct seq_file *s, void *data)
@@ -307,6 +378,9 @@ int __init tegra_powergate_debugfs_init(void)
         case TEGRA114:
                 powergate_name = powergate_name_t114;
                 break;
+        case TEGRA124:
+                powergate_name = powergate_name_t124;
+                break;
         }
 
         if (powergate_name) {
@@ -320,3 +394,120 @@ int __init tegra_powergate_debugfs_init(void)
 }
 
 #endif
+
+static int tegra_io_rail_prepare(int id, unsigned long *request,
+                                 unsigned long *status, unsigned int *bit)
+{
+        unsigned long rate, value;
+        struct clk *clk;
+
+        *bit = id % 32;
+
+        /*
+         * There are two sets of 30 bits to select IO rails, but bits 30 and
+         * 31 are control bits rather than IO rail selection bits.
+         */
+        if (id > 63 || *bit == 30 || *bit == 31)
+                return -EINVAL;
+
+        if (id < 32) {
+                *status = IO_DPD_STATUS;
+                *request = IO_DPD_REQ;
+        } else {
+                *status = IO_DPD2_STATUS;
+                *request = IO_DPD2_REQ;
+        }
+
+        clk = clk_get_sys(NULL, "pclk");
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        rate = clk_get_rate(clk);
+        clk_put(clk);
+
+        pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
+
+        /* must be at least 200 ns, in APB (PCLK) clock cycles */
+        value = DIV_ROUND_UP(1000000000, rate);
+        value = DIV_ROUND_UP(200, value);
+        pmc_write(value, SEL_DPD_TIM);
+
+        return 0;
+}
+
+static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
+                              unsigned long val, unsigned long timeout)
+{
+        unsigned long value;
+
+        timeout = jiffies + msecs_to_jiffies(timeout);
+
+        while (time_after(timeout, jiffies)) {
+                value = pmc_read(offset);
+                if ((value & mask) == val)
+                        return 0;
+
+                usleep_range(250, 1000);
+        }
+
+        return -ETIMEDOUT;
+}
+
+static void tegra_io_rail_unprepare(void)
+{
+        pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
+}
+
+int tegra_io_rail_power_on(int id)
+{
+        unsigned long request, status, value;
+        unsigned int bit, mask;
+        int err;
+
+        err = tegra_io_rail_prepare(id, &request, &status, &bit);
+        if (err < 0)
+                return err;
+
+        mask = 1 << bit;
+
+        value = pmc_read(request);
+        value |= mask;
+        value &= ~IO_DPD_REQ_CODE_MASK;
+        value |= IO_DPD_REQ_CODE_OFF;
+        pmc_write(value, request);
+
+        err = tegra_io_rail_poll(status, mask, 0, 250);
+        if (err < 0)
+                return err;
+
+        tegra_io_rail_unprepare();
+
+        return 0;
+}
+
+int tegra_io_rail_power_off(int id)
+{
+        unsigned long request, status, value;
+        unsigned int bit, mask;
+        int err;
+
+        err = tegra_io_rail_prepare(id, &request, &status, &bit);
+        if (err < 0)
+                return err;
+
+        mask = 1 << bit;
+
+        value = pmc_read(request);
+        value |= mask;
+        value &= ~IO_DPD_REQ_CODE_MASK;
+        value |= IO_DPD_REQ_CODE_ON;
+        pmc_write(value, request);
+
+        err = tegra_io_rail_poll(status, mask, mask, 250);
+        if (err < 0)
+                return err;
+
+        tegra_io_rail_unprepare();
+
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 568f5bbf979d..146fe8e0ae7c 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -21,6 +21,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/firmware.h>
 
 #include "iomap.h"
 #include "irammap.h"
@@ -33,26 +34,18 @@
 
 static bool is_enabled;
 
-static void __init tegra_cpu_reset_handler_enable(void)
+static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
 {
-        void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
         void __iomem *evp_cpu_reset =
                 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
         void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
         u32 reg;
 
-        BUG_ON(is_enabled);
-        BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
-
-        memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
-                        tegra_cpu_reset_handler_size);
-
         /*
          * NOTE: This must be the one and only write to the EVP CPU reset
          *       vector in the entire system.
          */
-        writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
-                        evp_cpu_reset);
+        writel(reset_address, evp_cpu_reset);
         wmb();
         reg = readl(evp_cpu_reset);
 
@@ -66,8 +59,33 @@ static void __init tegra_cpu_reset_handler_enable(void)
                 writel(reg, sb_ctrl);
                 wmb();
         }
+}
+
+static void __init tegra_cpu_reset_handler_enable(void)
+{
+        void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
+        const u32 reset_address = TEGRA_IRAM_RESET_BASE +
+                                                tegra_cpu_reset_handler_offset;
+        int err;
+
+        BUG_ON(is_enabled);
+        BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
 
-        is_enabled = true;
+        memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
+                        tegra_cpu_reset_handler_size);
+
+        err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
+        switch (err) {
+        case -ENOSYS:
+                tegra_cpu_reset_handler_set(reset_address);
+                /* pass-through */
+        case 0:
+                is_enabled = true;
+                break;
+        default:
+                pr_crit("Cannot set CPU reset handler: %d\n", err);
+                BUG();
+        }
 }
 
 void __init tegra_cpu_reset_handler_init(void)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 73368176c6e8..303a285d80fd 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -40,6 +40,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
+#include <asm/trusted_foundations.h>
 
 #include "apbio.h"
 #include "board.h"
@@ -60,15 +61,13 @@
  * kernel is loaded. The data is declared here rather than debug-macro.S so
  * that multiple inclusions of debug-macro.S point at the same data.
  */
-u32 tegra_uart_config[4] = {
+u32 tegra_uart_config[3] = {
         /* Debug UART initialization required */
         1,
         /* Debug UART physical address */
         0,
         /* Debug UART virtual address */
         0,
-        /* Scratch space for debug macro */
-        0,
 };
 
 static void __init tegra_init_cache(void)
@@ -90,6 +89,7 @@ static void __init tegra_init_cache(void)
 
 static void __init tegra_init_early(void)
 {
+        of_register_trusted_foundations();
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_cpu_reset_handler_init();
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bf40cd478fe9..0493a845b6bc 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -69,9 +69,9 @@ static int __init __u300_init_boardpower(struct platform_device *pdev)
                 return -ENODEV;
         }
         regmap = syscon_node_to_regmap(syscon_np);
-        if (!regmap) {
+        if (IS_ERR(regmap)) {
                 pr_crit("U300: could not locate syscon regmap\n");
-                return -ENODEV;
+                return PTR_ERR(regmap);
         }
 
         main_power_15 = regulator_get(&pdev->dev, "vana15");
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 9a5f9fb352ce..fe08fd34c0ce 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -184,11 +184,13 @@
 #define U300_TIMER_APP_CRC                                      (0x100)
 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 
-#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
-#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
-
 static void __iomem *u300_timer_base;
 
+struct u300_clockevent_data {
+        struct clock_event_device cevd;
+        unsigned ticks_per_jiffy;
+};
+
 /*
  * The u300_set_mode() function is always called first, if we
  * have oneshot timer active, the oneshot scheduling function
@@ -197,6 +199,9 @@ static void __iomem *u300_timer_base;
 static void u300_set_mode(enum clock_event_mode mode,
                           struct clock_event_device *evt)
 {
+        struct u300_clockevent_data *cevdata =
+                container_of(evt, struct u300_clockevent_data, cevd);
+
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 /* Disable interrupts on GPT1 */
@@ -209,7 +214,7 @@ static void u300_set_mode(enum clock_event_mode mode,
                  * Set the periodic mode to a certain number of ticks per
                  * jiffy.
                  */
-                writel(TICKS_PER_JIFFY,
+                writel(cevdata->ticks_per_jiffy,
                        u300_timer_base + U300_TIMER_APP_GPT1TC);
                 /*
                  * Set continuous mode, so the timer keeps triggering
@@ -305,20 +310,23 @@ static int u300_set_next_event(unsigned long cycles,
         return 0;
 }
 
-
-/* Use general purpose timer 1 as clock event */
-static struct clock_event_device clockevent_u300_1mhz = {
-        .name           = "GPT1",
-        .rating         = 300, /* Reasonably fast and accurate clock event */
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_next_event = u300_set_next_event,
-        .set_mode       = u300_set_mode,
+static struct u300_clockevent_data u300_clockevent_data = {
+        /* Use general purpose timer 1 as clock event */
+        .cevd = {
+                .name           = "GPT1",
+                /* Reasonably fast and accurate clock event */
+                .rating         = 300,
+                .features       = CLOCK_EVT_FEAT_PERIODIC |
+                        CLOCK_EVT_FEAT_ONESHOT,
+                .set_next_event = u300_set_next_event,
+                .set_mode       = u300_set_mode,
+        },
 };
 
 /* Clock event timer interrupt handler */
 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = &clockevent_u300_1mhz;
+        struct clock_event_device *evt = &u300_clockevent_data.cevd;
         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 
         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
@@ -341,7 +349,7 @@ static struct irqaction u300_timer_irq = {
  * stamp. (Inspired by OMAP implementation.)
  */
 
-static u32 notrace u300_read_sched_clock(void)
+static u64 notrace u300_read_sched_clock(void)
 {
         return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
@@ -379,7 +387,9 @@ static void __init u300_timer_init_of(struct device_node *np)
         clk_prepare_enable(clk);
         rate = clk_get_rate(clk);
 
-        setup_sched_clock(u300_read_sched_clock, 32, rate);
+        u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
+
+        sched_clock_register(u300_read_sched_clock, 32, rate);
 
         u300_delay_timer.read_current_timer = &u300_read_current_timer;
         u300_delay_timer.freq = rate;
@@ -428,7 +438,7 @@ static void __init u300_timer_init_of(struct device_node *np)
                 pr_err("timer: failed to initialize U300 clock source\n");
 
         /* Configure and register the clockevent */
-        clockevents_config_and_register(&clockevent_u300_1mhz, rate,
+        clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
                                         1, 0xffffffff);
 
         /*
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 616b96e86ad4..d05ba759da30 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,10 +2,10 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y                           := cpu.o devices.o id.o timer.o pm.o
+obj-y                           := cpu.o id.o timer.o pm.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
-obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_MOP500)       += board-mop500.o board-mop500-sdi.o \
+obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o
+obj-$(CONFIG_MACH_MOP500)       += board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-pins.o \
                                 board-mop500-audio.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 154e15f59702..9309ad4cbd09 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,16 +7,13 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/platform_data/dma-ste-dma40.h>
 
-#include "devices.h"
 #include "irqs.h"
 #include <linux/platform_data/asoc-ux500-msp.h>
 
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
-#include "devices-db8500.h"
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
@@ -31,7 +28,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
 };
 
 struct msp_i2s_platform_data msp0_platform_data = {
-        .id = MSP_I2S_0,
+        .id = 0,
         .msp_i2s_dma_rx = &msp0_dma_rx,
         .msp_i2s_dma_tx = &msp0_dma_tx,
 };
@@ -49,7 +46,7 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
 };
 
 struct msp_i2s_platform_data msp1_platform_data = {
-        .id = MSP_I2S_1,
+        .id = 1,
         .msp_i2s_dma_rx = NULL,
         .msp_i2s_dma_tx = &msp1_dma_tx,
 };
@@ -69,13 +66,13 @@ static struct stedma40_chan_cfg msp2_dma_tx = {
 };
 
 struct msp_i2s_platform_data msp2_platform_data = {
-        .id = MSP_I2S_2,
+        .id = 2,
         .msp_i2s_dma_rx = &msp2_dma_rx,
         .msp_i2s_dma_tx = &msp2_dma_tx,
 };
 
 struct msp_i2s_platform_data msp3_platform_data = {
-        .id             = MSP_I2S_3,
+        .id             = 3,
         .msp_i2s_dma_rx = &msp1_dma_rx,
         .msp_i2s_dma_tx = NULL,
 };
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0efb1560fc35..f63619b69113 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -10,94 +10,18 @@
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 
 #include <asm/mach-types.h>
 
 #include "board-mop500.h"
 
-enum custom_pin_cfg_t {
-        PINS_FOR_DEFAULT,
-        PINS_FOR_U9500,
-};
-
-static enum custom_pin_cfg_t pinsfor;
-
 /* These simply sets bias for pins */
 #define BIAS(a,b) static unsigned long a[] = { b }
 
-BIAS(pd, PIN_PULL_DOWN);
-BIAS(in_nopull, PIN_INPUT_NOPULL);
-BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
-BIAS(in_pu, PIN_INPUT_PULLUP);
-BIAS(in_pd, PIN_INPUT_PULLDOWN);
-BIAS(out_hi, PIN_OUTPUT_HIGH);
-BIAS(out_lo, PIN_OUTPUT_LOW);
-BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
-
 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
 
-/* These also force them into GPIO mode */
-BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
-BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
-BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
-BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
-/* Sleep modes */
-BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
-BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
-        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_ENABLED);
-BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_DISABLED);
-BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
-        PIN_SLPM_PDIS_DISABLED);
-
-/* We use these to define hog settings that are always done on boot */
-#define DB8500_MUX_HOG(group,func) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
-#define DB8500_PIN_HOG(pin,conf) \
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-
-/* These are default states associated with device and changed runtime */
-#define DB8500_MUX(group,func,dev) \
-        PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
-#define DB8500_PIN(pin,conf,dev) \
-        PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
-#define DB8500_PIN_IDLE(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
-                            pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
-#define DB8500_MUX_STATE(group, func, dev, state) \
-        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
-#define DB8500_PIN_STATE(pin, conf, dev, state) \
-        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
-
 #define AB8500_MUX_HOG(group, func) \
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
 #define AB8500_PIN_HOG(pin, conf) \
@@ -344,725 +268,8 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = {
         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 };
 
-/* Pin control settings */
-static struct pinctrl_map __initdata mop500_family_pinmap[] = {
-        /*
-         * uMSP0, mux in 4 pins, regular placement of RX/TX
-         * explicitly set the pins to no pull
-         */
-        DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
-        DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
-        DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
-        DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
-        DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
-        DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
-        /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
-        DB8500_MUX_HOG("msp2_a_1", "msp2"),
-        DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
-        DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
-        DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
-        DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
-        /*
-         * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
-         * pull-up
-         * TODO: is this really correct? Snowball doesn't have a LCD.
-         */
-        DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
-        DB8500_PIN_HOG("GPIO68_E1", in_pu),
-        DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
-        /*
-         * STMPE1601/tc35893 keypad IRQ GPIO 218
-         * TODO: set for snowball and HREF really??
-         */
-        DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
-        /*
-         * UART0, we do not mux in u0 here.
-         * uart-0 pins gpio configuration should be kept intact to prevent
-         * a glitch in tx line when the tty dev is opened. Later these pins
-         * are configured by uart driver
-         */
-        DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
-        DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
-        DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
-        DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
-        /*
-         * Mux in UART2 on altfunction C and set pull-ups.
-         * TODO: is this used on U8500 variants and Snowball really?
-         * The setting on GPIO31 conflicts with magnetometer use on hrefv60
-         */
-        /* default state for UART2 */
-        DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
-        DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
-        DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
-        /* Sleep state for UART2 */
-        DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
-        DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
-        /*
-         * The following pin sets were known as "runtime pins" before being
-         * converted to the pinctrl model. Here we model them as "default"
-         * states.
-         */
-        /* Mux in UART0 after initialization */
-        DB8500_MUX("u0_a_1", "u0", "uart0"),
-        DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
-        DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
-        DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
-        DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
-        /* Sleep state for UART0 */
-        DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
-        /* Mux in UART1 after initialization */
-        DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
-        DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
-        DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
-        /* Sleep state for UART1 */
-        DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
-        DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
-        /* MSP1 for ALSA codec */
-        DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
-        DB8500_MUX_HOG("msp1_a_1", "msp1"),
-        DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
-        DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
-        /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
-        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
-        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
-        /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
-        DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
-        DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
-        /* LCD VSI1 sleep state */
-        DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
-        /* Mux in i2c0 block, default state */
-        DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
-        /* i2c0 sleep state */
-        DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
-        /* Mux in i2c1 block, default state  */
-        DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
-        /* i2c1 sleep state */
-        DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
-        /* Mux in i2c2 block, default state  */
-        DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
-        /* i2c2 sleep state */
-        DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
-        /* Mux in i2c3 block, default state  */
-        DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
-        /* i2c3 sleep state */
-        DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
-        DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
-        /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
-        DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
-        DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
-        DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
-        DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
-        DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
-        DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
-        DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
-        DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
-        DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
-        DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
-        DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
-        /* SDI0 sleep state */
-        DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
-        DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
-
-        /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
-        DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
-        DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
-        DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
-        DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
-        DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
-        DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
-        DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
-        DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
-        /* SDI1 sleep state */
-        DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
-
-        /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
-        DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
-        DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
-        DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
-        DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
-        DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
-        DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
-        DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
-        DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
-        DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
-        DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
-        DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
-        DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
-        /* SDI2 sleep state */
-        DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
-        DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
-
-        /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
-        DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
-        DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
-        DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
-        DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
-        DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
-        DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
-        DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
-        DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
-        DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
-        DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
-        DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
-        DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
-        /*SDI4 sleep state */
-        DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
-        DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
-        DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
-        DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
-        DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
-        DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
-
-        /* Mux in USB pins, drive STP high */
-        /* USB default state */
-        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
-        /* USB sleep state */
-        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
-        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
-        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
-        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
-        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
-        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
-        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
-        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
-        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
-        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
-        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
-        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
-
-        /* Mux in SPI2 pins on the "other C1" altfunction */
-        DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
-        DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
-        DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
-        DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
-        DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
-        /* SPI2 idle state */
-        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
-        /* SPI2 sleep state */
-        DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
-
-        /* ske default state */
-        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
-        DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
-        /* ske sleep state */
-        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
-
-        /* STM APE pins states */
-        DB8500_MUX_STATE("stmape_c_1", "stmape",
-                "stm", "ape_mipi34"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "ape_mipi34"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "ape_mipi34"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "ape_mipi34"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "ape_mipi34"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "ape_mipi34"), /* dat0 */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "ape_mipi34_sleep"), /* dat0 */
-
-        DB8500_MUX_STATE("stmape_oc1_1", "stmape",
-                "stm", "ape_microsd"),
-        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
-                "stm", "ape_microsd"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
-                "stm", "ape_microsd"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
-                "stm", "ape_microsd"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
-                "stm", "ape_microsd"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
-                "stm", "ape_microsd"), /* dat3 */
-
-        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
-                "stm", "ape_microsd_sleep"), /* dat3 */
-
-        /*  STM Modem pins states */
-        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
-                "stm", "mod_mipi34"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_mipi34"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_mipi34"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "mod_mipi34"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "mod_mipi34"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "mod_mipi34"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "mod_mipi34"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "mod_mipi34"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_mipi34"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_mipi34"), /* uartmod tx */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_mipi34_sleep"), /* uartmod tx */
-
-        DB8500_MUX_STATE("stmmod_b_1", "stmmod",
-                "stm", "mod_microsd"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_microsd"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_microsd"),
-        DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
-                "stm", "mod_microsd"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
-                "stm", "mod_microsd"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
-                "stm", "mod_microsd"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
-                "stm", "mod_microsd"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
-                "stm", "mod_microsd"), /* dat3 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_microsd"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_microsd"), /* uartmod tx */
-
-        DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_microsd_sleep"), /* uartmod tx */
-
-        /*  STM dual Modem/APE pins state */
-        DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("stmape_c_2", "stmape",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
-                "stm", "mod_mipi34_ape_mipi60"),
-        DB8500_PIN_STATE("GPIO70_G5", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", in_pu,
-                "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", out_lo,
-                "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
-        DB8500_PIN_STATE("GPIO155_C19", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* clk */
-        DB8500_PIN_STATE("GPIO156_C17", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
-        DB8500_PIN_STATE("GPIO157_A18", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
-        DB8500_PIN_STATE("GPIO158_C18", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
-        DB8500_PIN_STATE("GPIO159_B19", in_nopull,
-                "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
-
-        DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
-        DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
-        DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
-        DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
-        DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
-        DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
-        DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
-        DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
-                "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
-};
-
-/*
- * These are specifically for the MOP500 and HREFP (pre-v60) version of the
- * board, which utilized a TC35892 GPIO expander instead of using a lot of
- * on-chip pins as the HREFv60 and later does.
- */
-static struct pinctrl_map __initdata mop500_pinmap[] = {
-        /* Mux in SSP0, pull down RXD pin */
-        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        DB8500_PIN_HOG("GPIO145_C13", pd),
-        /*
-         * XENON Flashgun on image processor GPIO (controlled from image
-         * processor firmware), mux in these image processor GPIO lines 0
-         * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
-         * the pins.
-         */
-        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
-        DB8500_PIN_HOG("GPIO6_AF6", in_pu),
-        DB8500_PIN_HOG("GPIO7_AG5", in_pu),
-        /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
-        DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
-        /* Mux in UART1 and set the pull-ups */
-        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
-        DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
-        /*
-         * Runtime stuff: make it possible to mux in the SKE keypad
-         * and bias the pins
-         */
-        /* ske default state */
-        DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
-        DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
-        /* ske sleep state */
-        DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
-        DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
-        DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
-        DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
-        DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
-        DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
-        DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
-        DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
-        DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
-        DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
-        DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
-        DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
-        DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
-        DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
-        DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
-        DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
-
-        /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
-        DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
-        DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
-};
-
-/*
- * The HREFv60 series of platforms is using available pins on the DB8500
- * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
- * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
- */
-static struct pinctrl_map __initdata hrefv60_pinmap[] = {
-        /* Drive WLAN_ENA low */
-        DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
-        /*
-         * XENON Flashgun on image processor GPIO (controlled from image
-         * processor firmware), mux in these image processor GPIO lines 0
-         * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
-         * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
-         * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
-         */
-        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
-        DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
-        DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
-        DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
-        DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
-        DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
-        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
-        DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
-        DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
-        /*
-         * Display Interface 1 uses GPIO 65 for RST (reset).
-         * Display Interface 2 uses GPIO 66 for RST (reset).
-         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
-         */
-        DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
-        DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
-        /*
-         * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
-         * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
-         * reset signals low.
-         */
-        DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
-        DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
-        DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
-        /*
-         * Drive D19-D23 for the ETM PTM trace interface low,
-         * (presumably pins are unconnected therefore grounded here,
-         * the "other alt C1" setting enables these pins)
-         */
-        DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
-        DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
-        /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
-        DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
-        DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
-        /* NFC ENA and RESET to low, pulldown IRQ line */
-        DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
-        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
-        DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
-        /*
-         * SKE keyboard partly on alt A and partly on "Other alt C1"
-         * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
-         * rows of 6 keys, then pull up force sensing interrup and
-         * drive reset and force sensing WU low.
-         */
-        DB8500_MUX_HOG("kp_a_1", "kp"),
-        DB8500_MUX_HOG("kp_oc1_1", "kp"),
-        DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
-        DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
-        DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
-        DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
-        DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
-        DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
-        DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
-        DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
-        DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
-        DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
-        DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
-        /* DiPro Sensor interrupt */
-        DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
-        /* Audio Amplifier HF enable */
-        DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
-        /* GBF interface, pull low to reset state */
-        DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
-        /* MSP : HDTV INTERFACE GPIO line */
-        DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
-        /* Accelerometer interrupt lines */
-        DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
-        DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
-        /* SD card detect GPIO pin */
-        DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
-        /*
-         * Runtime stuff
-         * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
-         * etc.
-         */
-        DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
-        DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
-        DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
-};
-
-static struct pinctrl_map __initdata u9500_pinmap[] = {
-        /* Mux in UART1 (just RX/TX) and set the pull-ups */
-        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        DB8500_PIN_HOG("GPIO4_AH6", in_pu),
-        DB8500_PIN_HOG("GPIO5_AG6", out_hi),
-        /* WLAN_IRQ line */
-        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
-        /* HSI */
-        DB8500_MUX_HOG("hsir_a_1", "hsi"),
-        DB8500_MUX_HOG("hsit_a_2", "hsi"),
-        DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
-        DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
-        DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
-        DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
-        DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
-        DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
-        DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
-        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
-};
-
-static struct pinctrl_map __initdata u8500_pinmap[] = {
-        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
-        DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
-};
-
-static struct pinctrl_map __initdata snowball_pinmap[] = {
-        /* Mux in SSP0 connected to AB8500, pull down RXD pin */
-        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        DB8500_PIN_HOG("GPIO145_C13", pd),
-        /* Always drive the MC0 DAT31DIR line high on these boards */
-        DB8500_PIN_HOG("GPIO21_AB3", out_hi),
-        /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
-        DB8500_MUX_HOG("sm_b_1", "sm"),
-        /* User LED */
-        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
-        /* Drive RSTn_LAN high */
-        DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
-        /*  Accelerometer/Magnetometer */
-        DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
-        DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
-        DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
-        /* WLAN/GBF */
-        DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
-        DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
-        DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
-        DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
-};
-
-/*
- * passing "pinsfor=" in kernel cmdline allows for custom
- * configuration of GPIOs on u8500 derived boards.
- */
-static int __init early_pinsfor(char *p)
-{
-        pinsfor = PINS_FOR_DEFAULT;
-
-        if (strcmp(p, "u9500-21") == 0)
-                pinsfor = PINS_FOR_U9500;
-
-        return 0;
-}
-early_param("pinsfor", early_pinsfor);
-
-int pins_for_u9500(void)
-{
-        if (pinsfor == PINS_FOR_U9500)
-                return 1;
-
-        return 0;
-}
-
-static void __init mop500_href_family_pinmaps_init(void)
-{
-        switch (pinsfor) {
-        case PINS_FOR_U9500:
-                pinctrl_register_mappings(u9500_pinmap,
-                                          ARRAY_SIZE(u9500_pinmap));
-                break;
-        case PINS_FOR_DEFAULT:
-                pinctrl_register_mappings(u8500_pinmap,
-                                          ARRAY_SIZE(u8500_pinmap));
-        default:
-                break;
-        }
-}
-
 void __init mop500_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(mop500_pinmap,
-                                  ARRAY_SIZE(mop500_pinmap));
-        mop500_href_family_pinmaps_init();
         if (machine_is_u8520())
                 pinctrl_register_mappings(ab8505_pinmap,
                                           ARRAY_SIZE(ab8505_pinmap));
@@ -1073,23 +280,12 @@ void __init mop500_pinmaps_init(void)
 
 void __init snowball_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(snowball_pinmap,
-                                  ARRAY_SIZE(snowball_pinmap));
-        pinctrl_register_mappings(u8500_pinmap,
-                                  ARRAY_SIZE(u8500_pinmap));
         pinctrl_register_mappings(ab8500_pinmap,
                                   ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init hrefv60_pinmaps_init(void)
 {
-        pinctrl_register_mappings(mop500_family_pinmap,
-                                  ARRAY_SIZE(mop500_family_pinmap));
-        pinctrl_register_mappings(hrefv60_pinmap,
-                                  ARRAY_SIZE(hrefv60_pinmap));
-        mop500_href_family_pinmaps_init();
         pinctrl_register_mappings(ab8500_pinmap,
                                   ARRAY_SIZE(ab8500_pinmap));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 0dc44c683427..a4e139aa2441 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -30,20 +30,6 @@ struct regulator_init_data gpio_en_3v3_regulator = {
        .consumer_supplies = gpio_en_3v3_consumers,
 };
 
-static struct regulator_consumer_supply sdi0_reg_consumers[] = {
-        REGULATOR_SUPPLY("vqmmc", "sdi0"),
-};
-
-struct regulator_init_data sdi0_reg_init_data = {
-        .constraints = {
-                .min_uV         = 1800000,
-                .max_uV         = 2900000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdi0_reg_consumers),
-        .consumer_supplies      = sdi0_reg_consumers,
-};
-
 /*
  * TPS61052 regulator
  */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 039f5132c370..9bece38fe933 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,7 +18,6 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
 extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
 extern struct regulator_init_data tps61052_regulator;
 extern struct regulator_init_data gpio_en_3v3_regulator;
-extern struct regulator_init_data sdi0_reg_init_data;
 
 void mop500_regulator_init(void);
 
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 26600a1c5319..fcbf3a13a539 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -14,10 +14,8 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 
 #include <asm/mach-types.h>
-#include "devices.h"
 
 #include "db8500-regs.h"
-#include "devices-db8500.h"
 #include "board-mop500.h"
 #include "ste-dma40-db8500.h"
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
deleted file mode 100644
index 514d40b625a4..000000000000
--- a/arch/arm/mach-ux500/board-mop500.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2008-2012 ST-Ericsson
- *
- * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_data/db8500_thermal.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl022.h>
-#include <linux/mfd/abx500/ab8500.h>
-#include <linux/regulator/ab8500.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/driver.h>
-#include <linux/mfd/tps6105x.h>
-#include <linux/platform_data/leds-lp55xx.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/platform_data/dma-ste-dma40.h>
-
-#include <asm/mach-types.h>
-
-#include "setup.h"
-#include "devices.h"
-#include "irqs.h"
-
-#include "ste-dma40-db8500.h"
-#include "db8500-regs.h"
-#include "devices-db8500.h"
-#include "board-mop500.h"
-#include "board-mop500-regulators.h"
-
-struct ab8500_platform_data ab8500_platdata = {
-        .irq_base       = MOP500_AB8500_IRQ_BASE,
-        .regulator      = &ab8500_regulator_plat_data,
-};
-
-#ifdef CONFIG_STE_DMA40
-static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type = DB8500_DMA_DEV8_SSP0,
-};
-
-static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV8_SSP0,
-};
-#endif
-
-struct pl022_ssp_controller ssp0_plat = {
-        .bus_id = 0,
-#ifdef CONFIG_STE_DMA40
-        .enable_dma = 1,
-        .dma_filter = stedma40_filter,
-        .dma_rx_param = &ssp0_dma_cfg_rx,
-        .dma_tx_param = &ssp0_dma_cfg_tx,
-#else
-        .enable_dma = 0,
-#endif
-        /* on this platform, gpio 31,142,144,214 &
-         * 224 are connected as chip selects
-         */
-        .num_chipselect = 5,
-};
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 511d6febbe99..d48e8662c676 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data;
 extern struct msp_i2s_platform_data msp1_platform_data;
 extern struct msp_i2s_platform_data msp2_platform_data;
 extern struct msp_i2s_platform_data msp3_platform_data;
-extern struct pl022_ssp_controller ssp0_plat;
 
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 12c7e5c03ea4..bc8a6183560d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -21,21 +21,32 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/regulator/machine.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/random.h>
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
 
 #include "setup.h"
-#include "devices.h"
 #include "irqs.h"
 
-#include "devices-db8500.h"
-#include "db8500-regs.h"
+#include "board-mop500-regulators.h"
 #include "board-mop500.h"
+#include "db8500-regs.h"
 #include "id.h"
 
+struct ab8500_platform_data ab8500_platdata = {
+        .irq_base       = MOP500_AB8500_IRQ_BASE,
+        .regulator      = &ab8500_regulator_plat_data,
+};
+
+struct prcmu_pdata db8500_prcmu_pdata = {
+        .ab_platdata    = &ab8500_platdata,
+        .ab_irq         = IRQ_DB8500_AB8500,
+        .irq_base       = IRQ_PRCMU_BASE,
+        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
+        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
+};
+
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
@@ -159,17 +170,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
         OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
                         NULL),
-        /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
-                "pinctrl-db8500", NULL),
         {},
 };
 
 static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
-        /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                         &db8500_prcmu_pdata),
         {},
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index f84d4397896b..d11ac4bf336c 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -25,7 +25,6 @@
 #include <asm/mach/map.h>
 
 #include "setup.h"
-#include "devices.h"
 
 #include "board-mop500.h"
 #include "db8500-regs.h"
@@ -64,12 +63,7 @@ void __init ux500_init_irq(void)
         } else
                 ux500_unknown_soc();
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt())
-                irqchip_init();
-        else
-#endif
-                gic_init(0, 29, dist_base, cpu_base);
+        irqchip_init();
 
         /*
          * Init clocks here so that they are available for system timer
@@ -79,16 +73,11 @@ void __init ux500_init_irq(void)
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
 
-                if (of_have_populated_dt())
-                        u8500_of_clk_init(U8500_CLKRST1_BASE,
-                                          U8500_CLKRST2_BASE,
-                                          U8500_CLKRST3_BASE,
-                                          U8500_CLKRST5_BASE,
-                                          U8500_CLKRST6_BASE);
-                else
-                        u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
-                                       U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
-                                       U8500_CLKRST6_BASE);
+                u8500_of_clk_init(U8500_CLKRST1_BASE,
+                                  U8500_CLKRST2_BASE,
+                                  U8500_CLKRST3_BASE,
+                                  U8500_CLKRST5_BASE,
+                                  U8500_CLKRST6_BASE);
         } else if (cpu_is_u9540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
deleted file mode 100644
index c59f89d058ff..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl022.h>
-#include <linux/mfd/dbx500-prcmu.h>
-
-#include "setup.h"
-#include "irqs.h"
-
-#include "db8500-regs.h"
-#include "devices-db8500.h"
-
-struct prcmu_pdata db8500_prcmu_pdata = {
-        .ab_platdata    = &ab8500_platdata,
-        .ab_irq         = IRQ_DB8500_AB8500,
-        .irq_base       = IRQ_PRCMU_BASE,
-        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
-        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
-};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
deleted file mode 100644
index b8ffc9979bb2..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL), version 2.
- */
-
-#ifndef __DEVICES_DB8500_H
-#define __DEVICES_DB8500_H
-
-#include "irqs.h"
-#include "db8500-regs.h"
-
-struct platform_device;
-
-extern struct ab8500_platform_data ab8500_platdata;
-extern struct prcmu_pdata db8500_prcmu_pdata;
-
-#endif
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
deleted file mode 100644
index 0f9e52b95935..000000000000
--- a/arch/arm/mach-ux500/devices.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/amba/bus.h>
-
-#include "setup.h"
-
-#include "db8500-regs.h"
-
-void __init amba_add_devices(struct amba_device *devs[], int num)
-{
-        int i;
-
-        for (i = 0; i < num; i++) {
-                struct amba_device *d = devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-}
diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h
deleted file mode 100644
index 5bca7c605cd6..000000000000
--- a/arch/arm/mach-ux500/devices.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#ifndef __ASM_ARCH_DEVICES_H__
-#define __ASM_ARCH_DEVICES_H__
-
-struct platform_device;
-struct amba_device;
-
-extern struct amba_device ux500_pl031_device;
-
-#endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 1f296e796a4f..a44967f3168c 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -38,8 +38,7 @@ static void write_pen_release(int val)
 {
         pen_release = val;
         smp_wmb();
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 }
 
 static void __iomem *scu_base_addr(void)
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
index 1a468f0fd22e..b80a9a2e356e 100644
--- a/arch/arm/mach-ux500/pm.c
+++ b/arch/arm/mach-ux500/pm.c
@@ -3,6 +3,8 @@
  * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
  *         ST-Ericsson.
  * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
+ * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro.
+ *
  * License terms: GNU General Public License (GPL) version 2
  *
  */
@@ -11,6 +13,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/suspend.h>
 #include <linux/platform_data/arm-ux500-pm.h>
 
 #include "db8500-regs.h"
@@ -152,6 +155,27 @@ int prcmu_copy_gic_settings(void)
         return 0;
 }
 
+#ifdef CONFIG_SUSPEND
+static int ux500_suspend_enter(suspend_state_t state)
+{
+        cpu_do_idle();
+        return 0;
+}
+
+static int ux500_suspend_valid(suspend_state_t state)
+{
+        return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
+}
+
+static const struct platform_suspend_ops ux500_suspend_ops = {
+        .enter        = ux500_suspend_enter,
+        .valid        = ux500_suspend_valid,
+};
+#define UX500_SUSPEND_OPS       (&ux500_suspend_ops)
+#else
+#define UX500_SUSPEND_OPS       NULL
+#endif
+
 void __init ux500_pm_init(u32 phy_base, u32 size)
 {
         prcmu_base = ioremap(phy_base, size);
@@ -164,4 +188,7 @@ void __init ux500_pm_init(u32 phy_base, u32 size)
          * This will make sure that the GIC is correctly configured.
          */
         prcmu_gic_recouple();
+
+        /* Set up ux500 suspend callbacks. */
+        suspend_set_ops(UX500_SUSPEND_OPS);
 }
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index bdb356498a74..2dea8b59d222 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -19,17 +19,11 @@
 void ux500_restart(enum reboot_mode mode, const char *cmd);
 
 void __init ux500_map_io(void);
-extern void __init u8500_map_io(void);
-
-extern struct device * __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
 
 extern struct device *ux500_soc_device_init(const char *soc_id);
 
-struct amba_device;
-extern void __init amba_add_devices(struct amba_device *devs[], int num);
-
 extern void ux500_timer_init(void);
 
 #define __IO_DEV_DESC(x, sz)    {               \
@@ -43,7 +37,7 @@ extern void ux500_timer_init(void);
         .virtual        = IO_ADDRESS(x),        \
         .pfn            = __phys_to_pfn(x),     \
         .length         = sz,                   \
-        .type           = MT_MEMORY,            \
+        .type           = MT_MEMORY_RWX,                \
 }
 
 extern struct smp_operations ux500_smp_ops;
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 05a4ff78b3bd..87efda0aa348 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -10,40 +10,12 @@
 #include <linux/clocksource.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
-
-#include <asm/smp_twd.h>
 
 #include "setup.h"
-#include "irqs.h"
 
 #include "db8500-regs.h"
 #include "id.h"
 
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
-                              U8500_TWD_BASE, IRQ_LOCALTIMER);
-
-static void __init ux500_twd_init(void)
-{
-        struct twd_local_timer *twd_local_timer;
-        int err;
-
-        /* Use this to switch local timer base if changed in new ASICs */
-        twd_local_timer = &u8500_twd_local_timer;
-
-        if (of_have_populated_dt())
-                clocksource_of_init();
-        else {
-                err = twd_local_timer_register(twd_local_timer);
-                if (err)
-                        pr_err("twd_local_timer_register failed %d\n", err);
-        }
-}
-#else
-#define ux500_twd_init()        do { } while(0)
-#endif
-
 const static struct of_device_id prcmu_timer_of_match[] __initconst = {
         { .compatible = "stericsson,db8500-prcmu-timer-4", },
         { },
@@ -51,54 +23,26 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = {
 
 void __init ux500_timer_init(void)
 {
-        void __iomem *mtu_timer_base;
         void __iomem *prcmu_timer_base;
         void __iomem *tmp_base;
         struct device_node *np;
 
-        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
-                mtu_timer_base = __io_address(U8500_MTU0_BASE);
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
-        } else {
+        else
                 ux500_unknown_soc();
-        }
 
-        /* TODO: Once MTU has been DT:ed place code above into else. */
-        if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
-                np = of_find_matching_node(NULL, prcmu_timer_of_match);
-                if (!np)
-#endif
-                        goto dt_fail;
+        np = of_find_matching_node(NULL, prcmu_timer_of_match);
+        if (!np)
+                goto dt_fail;
 
-                tmp_base = of_iomap(np, 0);
-                if (!tmp_base)
-                        goto dt_fail;
+        tmp_base = of_iomap(np, 0);
+        if (!tmp_base)
+                goto dt_fail;
 
-                prcmu_timer_base = tmp_base;
-        }
+        prcmu_timer_base = tmp_base;
 
 dt_fail:
-        /* Doing it the old fashioned way. */
-
-        /*
-         * Here we register the timerblocks active in the system.
-         * Localtimers (twd) is started when both cpu is up and running.
-         * MTU register a clocksource, clockevent and sched_clock.
-         * Since the MTU is located in the VAPE power domain
-         * it will be cleared in sleep which makes it unsuitable.
-         * We however need it as a timer tick (clockevent)
-         * during boot to calibrate delay until twd is started.
-         * RTC-RTT have problems as timer tick during boot since it is
-         * depending on delay which is not yet calibrated. RTC-RTT is in the
-         * always-on powerdomain and is used as clockevent instead of twd when
-         * sleeping.
-         * The PRCMU timer 4 register a clocksource and
-         * sched_clock with higher rating then MTU since is always-on.
-         *
-         */
-        if (!of_have_populated_dt())
-                nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
         clksrc_dbx500_prcmu_init(prcmu_timer_base);
-        ux500_twd_init();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3b0572f30d56..a335126ae18f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -570,6 +570,16 @@ static struct pl061_platform_data gpio1_plat_data = {
         .irq_base       = IRQ_GPIO1_START,
 };
 
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = IRQ_GPIO2_START,
+};
+
+static struct pl061_platform_data gpio3_plat_data = {
+        .gpio_base      = 24,
+        .irq_base       = IRQ_GPIO3_START,
+};
+
 static struct pl022_ssp_controller ssp0_plat_data = {
         .bus_id = 0,
         .enable_dma = 0,
@@ -596,6 +606,8 @@ static struct pl022_ssp_controller ssp0_plat_data = {
 #define WATCHDOG_IRQ    { IRQ_WDOGINT }
 #define GPIO0_IRQ       { IRQ_GPIOINT0 }
 #define GPIO1_IRQ       { IRQ_GPIOINT1 }
+#define GPIO2_IRQ       { IRQ_GPIOINT2 }
+#define GPIO3_IRQ       { IRQ_GPIOINT3 }
 #define RTC_IRQ         { IRQ_RTCINT }
 
 /*
@@ -622,6 +634,8 @@ APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
+APB_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
+APB_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
@@ -641,6 +655,8 @@ static struct amba_device *amba_devs[] __initdata = {
         &wdog_device,
         &gpio0_device,
         &gpio1_device,
+        &gpio2_device,
+        &gpio3_device,
         &rtc_device,
         &sci0_device,
         &ssp0_device,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 611d140c8695..9a53d0bd9144 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -47,27 +47,11 @@ static struct mmci_platform_data mmc1_plat_data = {
         .gpio_cd        = -1,
 };
 
-static struct pl061_platform_data gpio2_plat_data = {
-        .gpio_base      = 16,
-        .irq_base       = IRQ_GPIO2_START,
-};
-
-static struct pl061_platform_data gpio3_plat_data = {
-        .gpio_base      = 24,
-        .irq_base       = IRQ_GPIO3_START,
-};
-
 #define UART3_IRQ       { IRQ_SIC_UART3 }
 #define SCI1_IRQ        { IRQ_SIC_SCI3 }
 #define MMCI1_IRQ       { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
 
 /*
- * These devices are connected via the core APB bridge
- */
-#define GPIO2_IRQ       { IRQ_GPIOINT2 }
-#define GPIO3_IRQ       { IRQ_GPIOINT3 }
-
-/*
  * These devices are connected via the DMA APB bridge
  */
 
@@ -76,14 +60,9 @@ APB_DEVICE(uart3, "fpga:09", UART3,    NULL);
 APB_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 APB_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 
-/* DevChip Primecells */
-APB_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
-APB_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart3_device,
-        &gpio2_device,
-        &gpio3_device,
         &sci1_device,
         &mmc1_device,
 };
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 9a7bd137c8fd..1db2a5ca9ab8 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -25,6 +25,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -39,11 +41,6 @@
 
 void __iomem *zynq_scu_base;
 
-static struct of_device_id zynq_of_bus_ids[] __initdata = {
-        { .compatible = "simple-bus", },
-        {}
-};
-
 static struct platform_device zynq_cpuidle_device = {
         .name = "cpuidle-zynq",
 };
@@ -59,7 +56,7 @@ static void __init zynq_init_machine(void)
          */
         l2x0_of_init(0x02060000, 0xF0F0FFFF);
 
-        of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         platform_device_register(&zynq_cpuidle_device);
 }
@@ -97,6 +94,12 @@ static void __init zynq_map_io(void)
         zynq_scu_map_io();
 }
 
+static void __init zynq_irq_init(void)
+{
+        gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+        irqchip_init();
+}
+
 static void zynq_system_reset(enum reboot_mode mode, const char *cmd)
 {
         zynq_slcr_system_reset();
@@ -110,6 +113,7 @@ static const char * const zynq_dt_match[] = {
 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
         .smp            = smp_ops(zynq_smp_ops),
         .map_io         = zynq_map_io,
+        .init_irq       = zynq_irq_init,
         .init_machine   = zynq_init_machine,
         .init_time      = zynq_timer_init,
         .dt_compat      = zynq_dt_match,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 3040d219570f..c22c92cea8cb 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,8 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
+void zynq_secondary_startup(void);
+
 extern int zynq_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index d4cd5f34fe5c..57a32869f0aa 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -18,5 +18,9 @@ zynq_secondary_trampoline_jump:
         .word   /* cpu 1 */
 .globl zynq_secondary_trampoline_end
 zynq_secondary_trampoline_end:
-
 ENDPROC(zynq_secondary_trampoline)
+
+ENTRY(zynq_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(zynq_secondary_startup)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 689fbbc3d9c8..abc82ef085c1 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -39,11 +39,6 @@ int zynq_cpun_start(u32 address, int cpu)
         u32 trampoline_code_size = &zynq_secondary_trampoline_end -
                                                 &zynq_secondary_trampoline;
 
-        if (cpu > ncores) {
-                pr_warn("CPU No. is not available in the system\n");
-                return -1;
-        }
-
         /* MS: Expectation that SLCR are directly map and accessible */
         /* Not possible to jump to non aligned address */
         if (!(address & 3) && (!address || (address >= trampoline_code_size))) {
@@ -95,7 +90,7 @@ EXPORT_SYMBOL(zynq_cpun_start);
 static int zynq_boot_secondary(unsigned int cpu,
                                                 struct task_struct *idle)
 {
-        return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
+        return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
 }
 
 /*
@@ -114,23 +109,23 @@ static void __init zynq_smp_init_cpus(void)
 
 static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int i;
-
-        /*
-         * Initialise the present map, which describes the set of CPUs
-         * actually populated at the present time.
-         */
-        for (i = 0; i < max_cpus; i++)
-                set_cpu_present(i, true);
-
         scu_enable(zynq_scu_base);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static int zynq_cpu_kill(unsigned cpu)
+{
+        zynq_slcr_cpu_stop(cpu);
+        return 1;
+}
+#endif
+
 struct smp_operations zynq_smp_ops __initdata = {
         .smp_init_cpus          = zynq_smp_init_cpus,
         .smp_prepare_cpus       = zynq_smp_prepare_cpus,
         .smp_boot_secondary     = zynq_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = zynq_platform_cpu_die,
+        .cpu_kill               = zynq_cpu_kill,
 #endif
 };
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ecfe6e53f6e0..7f39ce2f841f 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -12,6 +12,7 @@ ifneq ($(CONFIG_MMU),y)
 obj-y                           += nommu.o
 endif
 
+obj-$(CONFIG_ARM_PTDUMP)        += dump.o
 obj-$(CONFIG_MODULES)           += proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 447da6ffadd5..7abde2ce8973 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-tauros3.h"
 #include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE         32
@@ -767,6 +768,14 @@ static void aurora_save(void)
         l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 }
 
+static void __init tauros3_save(void)
+{
+        l2x0_saved_regs.aux2_ctrl =
+                readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
+        l2x0_saved_regs.prefetch_ctrl =
+                readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+}
+
 static void l2x0_resume(void)
 {
         if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
@@ -821,6 +830,18 @@ static void aurora_resume(void)
         }
 }
 
+static void tauros3_resume(void)
+{
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+                writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+                               l2x0_base + TAUROS3_AUX2_CTRL);
+                writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+                               l2x0_base + L2X0_PREFETCH_CTRL);
+        }
+
+        l2x0_resume();
+}
+
 static void __init aurora_broadcast_l2_commands(void)
 {
         __u32 u;
@@ -906,6 +927,15 @@ static const struct l2x0_of_data aurora_no_outer_data = {
         },
 };
 
+static const struct l2x0_of_data tauros3_data = {
+        .setup = NULL,
+        .save  = tauros3_save,
+        /* Tauros3 broadcasts L1 cache operations to L2 */
+        .outer_cache = {
+                .resume      = tauros3_resume,
+        },
+};
+
 static const struct l2x0_of_data bcm_l2x0_data = {
         .setup = pl310_of_setup,
         .save  = pl310_save,
@@ -922,17 +952,19 @@ static const struct l2x0_of_data bcm_l2x0_data = {
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
-        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
-        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
         { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
-        { .compatible = "marvell,aurora-system-cache",
-          .data = (void *)&aurora_no_outer_data},
-        { .compatible = "marvell,aurora-outer-cache",
-          .data = (void *)&aurora_with_outer_data},
-        { .compatible = "brcm,bcm11351-a2-pl310-cache",
-          .data = (void *)&bcm_l2x0_data},
+        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
         { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
           .data = (void *)&bcm_l2x0_data},
+        { .compatible = "brcm,bcm11351-a2-pl310-cache",
+          .data = (void *)&bcm_l2x0_data},
+        { .compatible = "marvell,aurora-outer-cache",
+          .data = (void *)&aurora_with_outer_data},
+        { .compatible = "marvell,aurora-system-cache",
+          .data = (void *)&aurora_no_outer_data},
+        { .compatible = "marvell,tauros3-cache",
+          .data = (void *)&tauros3_data },
         {}
 };
 
diff --git a/arch/arm/mm/cache-tauros3.h b/arch/arm/mm/cache-tauros3.h
new file mode 100644
index 000000000000..02c0a97cbc02
--- /dev/null
+++ b/arch/arm/mm/cache-tauros3.h
@@ -0,0 +1,41 @@
+/*
+ * Marvell Tauros3 cache controller includes
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
+#define __ASM_ARM_HARDWARE_TAUROS3_H
+
+/*
+ * Marvell Tauros3 L2CC is compatible with PL310 r0p0
+ * but with PREFETCH_CTRL (r2p0) and an additional event counter.
+ * Also, there is AUX2_CTRL for some Marvell specific control.
+ */
+
+#define TAUROS3_EVENT_CNT2_CFG          0x224
+#define TAUROS3_EVENT_CNT2_VAL          0x228
+#define TAUROS3_INV_ALL                 0x780
+#define TAUROS3_CLEAN_ALL               0x784
+#define TAUROS3_AUX2_CTRL               0x820
+
+/* Registers shifts and masks */
+#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN    (1 << 2)
+
+#endif
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index b5c467a65c27..778bcf88ee79 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -146,18 +146,18 @@ flush_levels:
         ldr     r7, =0x7fff
         ands    r7, r7, r1, lsr #13             @ extract max number of the index size
 loop1:
-        mov     r9, r4                          @ create working copy of max way size
+        mov     r9, r7                          @ create working copy of max index
 loop2:
- ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
- THUMB( lsl     r6, r9, r5              )
+ ARM(   orr     r11, r10, r4, lsl r5    )       @ factor way and cache number into r11
+ THUMB( lsl     r6, r4, r5              )
  THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
- ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
- THUMB( lsl     r6, r7, r2              )
+ ARM(   orr     r11, r11, r9, lsl r2    )       @ factor index number into r11
+ THUMB( lsl     r6, r9, r2              )
  THUMB( orr     r11, r11, r6            )       @ factor index number into r11
         mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
-        subs    r9, r9, #1                      @ decrement the way
+        subs    r9, r9, #1                      @ decrement the index
         bge     loop2
-        subs    r7, r7, #1                      @ decrement the index
+        subs    r4, r4, #1                      @ decrement the way
         bge     loop1
 skip:
         add     r10, r10, #2                    @ increment cache number
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 84e6f772e204..6eb97b3a7481 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -36,8 +36,8 @@
  * The context ID is used by debuggers and trace logic, and
  * should be unique within all running processes.
  *
- * In big endian operation, the two 32 bit words are swapped if accesed by
- * non 64-bit operations.
+ * In big endian operation, the two 32 bit words are swapped if accessed
+ * by non-64-bit operations.
  */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
 #define NUM_USER_ASIDS          ASID_FIRST_VERSION
@@ -78,20 +78,21 @@ void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
 #endif
 
 #ifdef CONFIG_ARM_LPAE
-static void cpu_set_reserved_ttbr0(void)
-{
-        /*
-         * Set TTBR0 to swapper_pg_dir which contains only global entries. The
-         * ASID is set to 0.
-         */
-        cpu_set_ttbr(0, __pa(swapper_pg_dir));
-        isb();
-}
+/*
+ * With LPAE, the ASID and page tables are updated atomicly, so there is
+ * no need for a reserved set of tables (the active ASID tracking prevents
+ * any issues across a rollover).
+ */
+#define cpu_set_reserved_ttbr0()
 #else
 static void cpu_set_reserved_ttbr0(void)
 {
         u32 ttb;
-        /* Copy TTBR1 into TTBR0 */
+        /*
+         * Copy TTBR1 into TTBR0.
+         * This points at swapper_pg_dir, which contains only global
+         * entries so any speculative walks are perfectly safe.
+         */
         asm volatile(
         "       mrc     p15, 0, %0, c2, c0, 1           @ read TTBR1\n"
         "       mcr     p15, 0, %0, c2, c0, 0           @ set TTBR0\n"
@@ -179,6 +180,7 @@ static int is_reserved_asid(u64 asid)
 
 static u64 new_context(struct mm_struct *mm, unsigned int cpu)
 {
+        static u32 cur_idx = 1;
         u64 asid = atomic64_read(&mm->context.id);
         u64 generation = atomic64_read(&asid_generation);
 
@@ -193,10 +195,13 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
                  * Allocate a free ASID. If we can't find one, take a
                  * note of the currently active ASIDs and mark the TLBs
                  * as requiring flushes. We always count from ASID #1,
-                 * as we reserve ASID #0 to switch via TTBR0 and indicate
-                 * rollover events.
+                 * as we reserve ASID #0 to switch via TTBR0 and to
+                 * avoid speculative page table walks from hitting in
+                 * any partial walk caches, which could be populated
+                 * from overlapping level-1 descriptors used to map both
+                 * the module area and the userspace stack.
                  */
-                asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
+                asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
                 if (asid == NUM_USER_ASIDS) {
                         generation = atomic64_add_return(ASID_FIRST_VERSION,
                                                          &asid_generation);
@@ -204,6 +209,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
                         asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                 }
                 __set_bit(asid, asid_map);
+                cur_idx = asid;
                 asid |= generation;
                 cpumask_clear(mm_cpumask(mm));
         }
@@ -221,8 +227,9 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
                 __check_vmalloc_seq(mm);
 
         /*
-         * Required during context switch to avoid speculative page table
-         * walking with the wrong TTBR.
+         * We cannot update the pgd and the ASID atomicly with classic
+         * MMU, so switch exclusively to global mappings to avoid
+         * speculative page table walking with the wrong TTBR.
          */
         cpu_set_reserved_ttbr0();
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f61a5707823a..1a77450e728a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -376,7 +376,7 @@ void __init init_dma_coherent_pool_size(unsigned long size)
 static int __init atomic_pool_init(void)
 {
         struct dma_pool *pool = &atomic_pool;
-        pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
+        pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
         gfp_t gfp = GFP_KERNEL | GFP_DMA;
         unsigned long nr_pages = pool->size >> PAGE_SHIFT;
         unsigned long *bitmap;
@@ -624,7 +624,7 @@ static void __free_from_contiguous(struct device *dev, struct page *page,
         if (PageHighMem(page))
                 __dma_free_remap(cpu_addr, size);
         else
-                __dma_remap(page, size, pgprot_kernel);
+                __dma_remap(page, size, PAGE_KERNEL);
         dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
 }
 
@@ -1351,7 +1351,7 @@ static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
             dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
 {
-        pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
+        pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
         struct page **pages;
         void *addr = NULL;
 
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
new file mode 100644
index 000000000000..2b3a56414271
--- /dev/null
+++ b/arch/arm/mm/dump.c
@@ -0,0 +1,345 @@
+/*
+ * Debug helper to dump the current kernel pagetables of the system
+ * so that we can see what the various memory ranges are set to.
+ *
+ * Derived from x86 implementation:
+ * (C) Copyright 2008 Intel Corporation
+ *
+ * Author: Arjan van de Ven <arjan@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/seq_file.h>
+
+#include <asm/fixmap.h>
+#include <asm/pgtable.h>
+
+struct addr_marker {
+        unsigned long start_address;
+        const char *name;
+};
+
+static struct addr_marker address_markers[] = {
+        { MODULES_VADDR,        "Modules" },
+        { PAGE_OFFSET,          "Kernel Mapping" },
+        { 0,                    "vmalloc() Area" },
+        { VMALLOC_END,          "vmalloc() End" },
+        { FIXADDR_START,        "Fixmap Area" },
+        { CONFIG_VECTORS_BASE,  "Vectors" },
+        { CONFIG_VECTORS_BASE + PAGE_SIZE * 2, "Vectors End" },
+        { -1,                   NULL },
+};
+
+struct pg_state {
+        struct seq_file *seq;
+        const struct addr_marker *marker;
+        unsigned long start_address;
+        unsigned level;
+        u64 current_prot;
+};
+
+struct prot_bits {
+        u64             mask;
+        u64             val;
+        const char      *set;
+        const char      *clear;
+};
+
+static const struct prot_bits pte_bits[] = {
+        {
+                .mask   = L_PTE_USER,
+                .val    = L_PTE_USER,
+                .set    = "USR",
+                .clear  = "   ",
+        }, {
+                .mask   = L_PTE_RDONLY,
+                .val    = L_PTE_RDONLY,
+                .set    = "ro",
+                .clear  = "RW",
+        }, {
+                .mask   = L_PTE_XN,
+                .val    = L_PTE_XN,
+                .set    = "NX",
+                .clear  = "x ",
+        }, {
+                .mask   = L_PTE_SHARED,
+                .val    = L_PTE_SHARED,
+                .set    = "SHD",
+                .clear  = "   ",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_UNCACHED,
+                .set    = "SO/UNCACHED",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_BUFFERABLE,
+                .set    = "MEM/BUFFERABLE/WC",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_WRITETHROUGH,
+                .set    = "MEM/CACHED/WT",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_WRITEBACK,
+                .set    = "MEM/CACHED/WBRA",
+#ifndef CONFIG_ARM_LPAE
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_MINICACHE,
+                .set    = "MEM/MINICACHE",
+#endif
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_WRITEALLOC,
+                .set    = "MEM/CACHED/WBWA",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_DEV_SHARED,
+                .set    = "DEV/SHARED",
+#ifndef CONFIG_ARM_LPAE
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_DEV_NONSHARED,
+                .set    = "DEV/NONSHARED",
+#endif
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_DEV_WC,
+                .set    = "DEV/WC",
+        }, {
+                .mask   = L_PTE_MT_MASK,
+                .val    = L_PTE_MT_DEV_CACHED,
+                .set    = "DEV/CACHED",
+        },
+};
+
+static const struct prot_bits section_bits[] = {
+#ifndef CONFIG_ARM_LPAE
+        /* These are approximate */
+        {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = 0,
+                .set    = "    ro",
+        }, {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = PMD_SECT_AP_WRITE,
+                .set    = "    RW",
+        }, {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = PMD_SECT_AP_READ,
+                .set    = "USR ro",
+        }, {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .set    = "USR RW",
+#else
+        {
+                .mask   = PMD_SECT_USER,
+                .val    = PMD_SECT_USER,
+                .set    = "USR",
+        }, {
+                .mask   = PMD_SECT_RDONLY,
+                .val    = PMD_SECT_RDONLY,
+                .set    = "ro",
+                .clear  = "RW",
+#endif
+        }, {
+                .mask   = PMD_SECT_XN,
+                .val    = PMD_SECT_XN,
+                .set    = "NX",
+                .clear  = "x ",
+        }, {
+                .mask   = PMD_SECT_S,
+                .val    = PMD_SECT_S,
+                .set    = "SHD",
+                .clear  = "   ",
+        },
+};
+
+struct pg_level {
+        const struct prot_bits *bits;
+        size_t num;
+        u64 mask;
+};
+
+static struct pg_level pg_level[] = {
+        {
+        }, { /* pgd */
+        }, { /* pud */
+        }, { /* pmd */
+                .bits   = section_bits,
+                .num    = ARRAY_SIZE(section_bits),
+        }, { /* pte */
+                .bits   = pte_bits,
+                .num    = ARRAY_SIZE(pte_bits),
+        },
+};
+
+static void dump_prot(struct pg_state *st, const struct prot_bits *bits, size_t num)
+{
+        unsigned i;
+
+        for (i = 0; i < num; i++, bits++) {
+                const char *s;
+
+                if ((st->current_prot & bits->mask) == bits->val)
+                        s = bits->set;
+                else
+                        s = bits->clear;
+
+                if (s)
+                        seq_printf(st->seq, " %s", s);
+        }
+}
+
+static void note_page(struct pg_state *st, unsigned long addr, unsigned level, u64 val)
+{
+        static const char units[] = "KMGTPE";
+        u64 prot = val & pg_level[level].mask;
+
+        if (addr < USER_PGTABLES_CEILING)
+                return;
+
+        if (!st->level) {
+                st->level = level;
+                st->current_prot = prot;
+                seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+        } else if (prot != st->current_prot || level != st->level ||
+                   addr >= st->marker[1].start_address) {
+                const char *unit = units;
+                unsigned long delta;
+
+                if (st->current_prot) {
+                        seq_printf(st->seq, "0x%08lx-0x%08lx   ",
+                                   st->start_address, addr);
+
+                        delta = (addr - st->start_address) >> 10;
+                        while (!(delta & 1023) && unit[1]) {
+                                delta >>= 10;
+                                unit++;
+                        }
+                        seq_printf(st->seq, "%9lu%c", delta, *unit);
+                        if (pg_level[st->level].bits)
+                                dump_prot(st, pg_level[st->level].bits, pg_level[st->level].num);
+                        seq_printf(st->seq, "\n");
+                }
+
+                if (addr >= st->marker[1].start_address) {
+                        st->marker++;
+                        seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+                }
+                st->start_address = addr;
+                st->current_prot = prot;
+                st->level = level;
+        }
+}
+
+static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
+{
+        pte_t *pte = pte_offset_kernel(pmd, 0);
+        unsigned long addr;
+        unsigned i;
+
+        for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
+                addr = start + i * PAGE_SIZE;
+                note_page(st, addr, 4, pte_val(*pte));
+        }
+}
+
+static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
+{
+        pmd_t *pmd = pmd_offset(pud, 0);
+        unsigned long addr;
+        unsigned i;
+
+        for (i = 0; i < PTRS_PER_PMD; i++, pmd++) {
+                addr = start + i * PMD_SIZE;
+                if (pmd_none(*pmd) || pmd_large(*pmd) || !pmd_present(*pmd))
+                        note_page(st, addr, 3, pmd_val(*pmd));
+                else
+                        walk_pte(st, pmd, addr);
+        }
+}
+
+static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
+{
+        pud_t *pud = pud_offset(pgd, 0);
+        unsigned long addr;
+        unsigned i;
+
+        for (i = 0; i < PTRS_PER_PUD; i++, pud++) {
+                addr = start + i * PUD_SIZE;
+                if (!pud_none(*pud)) {
+                        walk_pmd(st, pud, addr);
+                } else {
+                        note_page(st, addr, 2, pud_val(*pud));
+                }
+        }
+}
+
+static void walk_pgd(struct seq_file *m)
+{
+        pgd_t *pgd = swapper_pg_dir;
+        struct pg_state st;
+        unsigned long addr;
+        unsigned i, pgdoff = USER_PGTABLES_CEILING / PGDIR_SIZE;
+
+        memset(&st, 0, sizeof(st));
+        st.seq = m;
+        st.marker = address_markers;
+
+        pgd += pgdoff;
+
+        for (i = pgdoff; i < PTRS_PER_PGD; i++, pgd++) {
+                addr = i * PGDIR_SIZE;
+                if (!pgd_none(*pgd)) {
+                        walk_pud(&st, pgd, addr);
+                } else {
+                        note_page(&st, addr, 1, pgd_val(*pgd));
+                }
+        }
+
+        note_page(&st, 0, 0, 0);
+}
+
+static int ptdump_show(struct seq_file *m, void *v)
+{
+        walk_pgd(m);
+        return 0;
+}
+
+static int ptdump_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ptdump_show, NULL);
+}
+
+static const struct file_operations ptdump_fops = {
+        .open           = ptdump_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int ptdump_init(void)
+{
+        struct dentry *pe;
+        unsigned i, j;
+
+        for (i = 0; i < ARRAY_SIZE(pg_level); i++)
+                if (pg_level[i].bits)
+                        for (j = 0; j < pg_level[i].num; j++)
+                                pg_level[i].mask |= pg_level[i].bits[j].mask;
+
+        address_markers[2].start_address = VMALLOC_START;
+
+        pe = debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
+                                 &ptdump_fops);
+        return pe ? 0 : -ENOMEM;
+}
+__initcall(ptdump_init);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 3e8f106ee5fe..804d61566a53 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -92,9 +92,6 @@ void show_mem(unsigned int filter)
         printk("Mem-info:\n");
         show_free_areas(filter);
 
-        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
-                return;
-
         for_each_bank (i, mi) {
                 struct membank *bank = &mi->bank[i];
                 unsigned int pfn1, pfn2;
@@ -145,58 +142,6 @@ static void __init find_limits(unsigned long *min, unsigned long *max_low,
         *max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]);
 }
 
-static void __init arm_bootmem_init(unsigned long start_pfn,
-        unsigned long end_pfn)
-{
-        struct memblock_region *reg;
-        unsigned int boot_pages;
-        phys_addr_t bitmap;
-        pg_data_t *pgdat;
-
-        /*
-         * Allocate the bootmem bitmap page.  This must be in a region
-         * of memory which has already been mapped.
-         */
-        boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
-        bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES,
-                                __pfn_to_phys(end_pfn));
-
-        /*
-         * Initialise the bootmem allocator, handing the
-         * memory banks over to bootmem.
-         */
-        node_set_online(0);
-        pgdat = NODE_DATA(0);
-        init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
-
-        /* Free the lowmem regions from memblock into bootmem. */
-        for_each_memblock(memory, reg) {
-                unsigned long start = memblock_region_memory_base_pfn(reg);
-                unsigned long end = memblock_region_memory_end_pfn(reg);
-
-                if (end >= end_pfn)
-                        end = end_pfn;
-                if (start >= end)
-                        break;
-
-                free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT);
-        }
-
-        /* Reserve the lowmem memblock reserved regions in bootmem. */
-        for_each_memblock(reserved, reg) {
-                unsigned long start = memblock_region_reserved_base_pfn(reg);
-                unsigned long end = memblock_region_reserved_end_pfn(reg);
-
-                if (end >= end_pfn)
-                        end = end_pfn;
-                if (start >= end)
-                        break;
-
-                reserve_bootmem(__pfn_to_phys(start),
-                                (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT);
-        }
-}
-
 #ifdef CONFIG_ZONE_DMA
 
 phys_addr_t arm_dma_zone_size __read_mostly;
@@ -236,7 +181,7 @@ void __init setup_dma_zone(const struct machine_desc *mdesc)
 #endif
 }
 
-static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
+static void __init zone_sizes_init(unsigned long min, unsigned long max_low,
         unsigned long max_high)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
@@ -345,10 +290,11 @@ void __init arm_memblock_init(struct meminfo *mi,
 #endif
 #ifdef CONFIG_BLK_DEV_INITRD
         /* FDT scan will populate initrd_start */
-        if (initrd_start) {
+        if (initrd_start && !phys_initrd_size) {
                 phys_initrd_start = __virt_to_phys(initrd_start);
                 phys_initrd_size = initrd_end - initrd_start;
         }
+        initrd_start = initrd_end = 0;
         if (phys_initrd_size &&
             !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
                 pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
@@ -384,7 +330,6 @@ void __init arm_memblock_init(struct meminfo *mi,
         dma_contiguous_reserve(min(arm_dma_limit, arm_lowmem_limit));
 
         arm_memblock_steal_permitted = false;
-        memblock_allow_resize();
         memblock_dump_all();
 }
 
@@ -392,12 +337,11 @@ void __init bootmem_init(void)
 {
         unsigned long min, max_low, max_high;
 
+        memblock_allow_resize();
         max_low = max_high = 0;
 
         find_limits(&min, &max_low, &max_high);
 
-        arm_bootmem_init(min, max_low);
-
         /*
          * Sparsemem tries to allocate bootmem in memory_present(),
          * so must be done after the fixed reservations
@@ -414,7 +358,7 @@ void __init bootmem_init(void)
          * the sparse mem_map arrays initialized by sparse_init()
          * for memmap_init_zone(), otherwise all PFNs are invalid.
          */
-        arm_bootmem_free(min, max_low, max_high);
+        zone_sizes_init(min, max_low, max_high);
 
         /*
          * This doesn't seem to be used by the Linux memory manager any
@@ -461,7 +405,7 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
          * free the section of the memmap array.
          */
         if (pg < pgend)
-                free_bootmem(pg, pgend - pg);
+                memblock_free_early(pg, pgend - pg);
 }
 
 /*
@@ -587,7 +531,7 @@ void __init mem_init(void)
         extern u32 itcm_end;
 #endif
 
-        max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
+        set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
 
         /* this will put all unused low memory onto the freelists */
         free_unused_memmap(&meminfo);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index f123d6eb074b..f9c32ba73544 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -392,9 +392,9 @@ __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
         unsigned int mtype;
 
         if (cached)
-                mtype = MT_MEMORY;
+                mtype = MT_MEMORY_RWX;
         else
-                mtype = MT_MEMORY_NONCACHED;
+                mtype = MT_MEMORY_RWX_NONCACHED;
 
         return __arm_ioremap_caller(phys_addr, size, mtype,
                         __builtin_return_address(0));
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 580ef2de82d7..4f08c133cc25 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -22,6 +22,7 @@
 #include <asm/cputype.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
+#include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
@@ -287,36 +288,43 @@ static struct mem_type mem_types[] = {
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_USER,
         },
-        [MT_MEMORY] = {
+        [MT_MEMORY_RWX] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
+        [MT_MEMORY_RW] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                             L_PTE_XN,
+                .prot_l1   = PMD_TYPE_TABLE,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+                .domain    = DOMAIN_KERNEL,
+        },
         [MT_ROM] = {
                 .prot_sect = PMD_TYPE_SECT,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_NONCACHED] = {
+        [MT_MEMORY_RWX_NONCACHED] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_MT_BUFFERABLE,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_DTCM] = {
+        [MT_MEMORY_RW_DTCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_ITCM] = {
+        [MT_MEMORY_RWX_ITCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_SO] = {
+        [MT_MEMORY_RW_SO] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_MT_UNCACHED | L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
@@ -325,7 +333,8 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_DMA_READY] = {
-                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -337,6 +346,44 @@ const struct mem_type *get_mem_type(unsigned int type)
 }
 EXPORT_SYMBOL(get_mem_type);
 
+#define PTE_SET_FN(_name, pteop) \
+static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
+                        void *data) \
+{ \
+        pte_t pte = pteop(*ptep); \
+\
+        set_pte_ext(ptep, pte, 0); \
+        return 0; \
+} \
+
+#define SET_MEMORY_FN(_name, callback) \
+int set_memory_##_name(unsigned long addr, int numpages) \
+{ \
+        unsigned long start = addr; \
+        unsigned long size = PAGE_SIZE*numpages; \
+        unsigned end = start + size; \
+\
+        if (start < MODULES_VADDR || start >= MODULES_END) \
+                return -EINVAL;\
+\
+        if (end < MODULES_VADDR || end >= MODULES_END) \
+                return -EINVAL; \
+\
+        apply_to_page_range(&init_mm, start, size, callback, NULL); \
+        flush_tlb_kernel_range(start, end); \
+        return 0;\
+}
+
+PTE_SET_FN(ro, pte_wrprotect)
+PTE_SET_FN(rw, pte_mkwrite)
+PTE_SET_FN(x, pte_mkexec)
+PTE_SET_FN(nx, pte_mknexec)
+
+SET_MEMORY_FN(ro, pte_set_ro)
+SET_MEMORY_FN(rw, pte_set_rw)
+SET_MEMORY_FN(x, pte_set_x)
+SET_MEMORY_FN(nx, pte_set_nx)
+
 /*
  * Adjust the PMD section entries according to the CPU in use.
  */
@@ -410,6 +457,9 @@ static void __init build_mem_type_table(void)
                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
+
+                        /* Also setup NX memory mapping */
+                        mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
                 }
                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
                         /*
@@ -487,11 +537,13 @@ static void __init build_mem_type_table(void)
                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-                        mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                        mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-                        mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
                 }
         }
 
@@ -502,15 +554,15 @@ static void __init build_mem_type_table(void)
         if (cpu_arch >= CPU_ARCH_ARMv6) {
                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
                         /* Non-cacheable Normal is XCB = 001 */
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
                                 PMD_SECT_BUFFERED;
                 } else {
                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
                                 PMD_SECT_TEX(1);
                 }
         } else {
-                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
+                mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
         }
 
 #ifdef CONFIG_ARM_LPAE
@@ -543,10 +595,12 @@ static void __init build_mem_type_table(void)
 
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
-        mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
-        mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
+        mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
+        mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
+        mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
+        mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
-        mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
+        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
         mem_types[MT_ROM].prot_sect |= cp->pmd;
 
         switch (cp->pmd) {
@@ -1296,6 +1350,8 @@ static void __init kmap_init(void)
 static void __init map_lowmem(void)
 {
         struct memblock_region *reg;
+        unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
+        unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
 
         /* Map all the lowmem memory banks. */
         for_each_memblock(memory, reg) {
@@ -1308,12 +1364,40 @@ static void __init map_lowmem(void)
                 if (start >= end)
                         break;
 
-                map.pfn = __phys_to_pfn(start);
-                map.virtual = __phys_to_virt(start);
-                map.length = end - start;
-                map.type = MT_MEMORY;
+                if (end < kernel_x_start || start >= kernel_x_end) {
+                        map.pfn = __phys_to_pfn(start);
+                        map.virtual = __phys_to_virt(start);
+                        map.length = end - start;
+                        map.type = MT_MEMORY_RWX;
 
-                create_mapping(&map);
+                        create_mapping(&map);
+                } else {
+                        /* This better cover the entire kernel */
+                        if (start < kernel_x_start) {
+                                map.pfn = __phys_to_pfn(start);
+                                map.virtual = __phys_to_virt(start);
+                                map.length = kernel_x_start - start;
+                                map.type = MT_MEMORY_RW;
+
+                                create_mapping(&map);
+                        }
+
+                        map.pfn = __phys_to_pfn(kernel_x_start);
+                        map.virtual = __phys_to_virt(kernel_x_start);
+                        map.length = kernel_x_end - kernel_x_start;
+                        map.type = MT_MEMORY_RWX;
+
+                        create_mapping(&map);
+
+                        if (kernel_x_end < end) {
+                                map.pfn = __phys_to_pfn(kernel_x_end);
+                                map.virtual = __phys_to_virt(kernel_x_end);
+                                map.length = end - kernel_x_end;
+                                map.type = MT_MEMORY_RW;
+
+                                create_mapping(&map);
+                        }
+                }
         }
 }
 
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 1046b373d1ae..249379535be2 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -23,7 +23,7 @@
 #define __pgd_alloc()   kmalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL)
 #define __pgd_free(pgd) kfree(pgd)
 #else
-#define __pgd_alloc()   (pgd_t *)__get_free_pages(GFP_KERNEL, 2)
+#define __pgd_alloc()   (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_REPEAT, 2)
 #define __pgd_free(pgd) free_pages((unsigned long)pgd, 2)
 #endif
 
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 29606bd75f3f..d70b73364a3f 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -54,7 +54,7 @@ static struct clocksource iop_clocksource = {
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
-static u32 notrace iop_read_sched_clock(void)
+static u64 notrace iop_read_sched_clock(void)
 {
         return 0xffffffffu - read_tcr1();
 }
@@ -142,7 +142,7 @@ void __init iop_init_time(unsigned long tick_rate)
 {
         u32 timer_ctl;
 
-        setup_sched_clock(iop_read_sched_clock, 32, tick_rate);
+        sched_clock_register(iop_read_sched_clock, 32, tick_rate);
 
         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
         iop_tick_rate = tick_rate;
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index d9bc98eb2a6b..384a776d8eb2 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -38,7 +38,7 @@
  */
 static void __iomem *sync32k_cnt_reg;
 
-static u32 notrace omap_32k_read_sched_clock(void)
+static u64 notrace omap_32k_read_sched_clock(void)
 {
         return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
 }
@@ -115,7 +115,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
                 return ret;
         }
 
-        setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+        sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
         register_persistent_clock(NULL, omap_read_persistent_clock);
         pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
 
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c66d163d7a2a..830ff07f3385 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -22,6 +22,7 @@
 #include <linux/platform_data/dma-mv_xor.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <mach/bridge-regs.h>
+#include <plat/common.h>
 
 /* Create a clkdev entry for a given device/clk */
 void __init orion_clkdev_add(const char *con_id, const char *dev_id,
@@ -256,7 +257,7 @@ static __init void ge_complete(
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
+static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
 
 static struct resource orion_ge00_shared_resources[] = {
         {
@@ -322,7 +323,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
 /*****************************************************************************
  * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
+static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
 
 static struct resource orion_ge01_shared_resources[] = {
         {
@@ -373,7 +374,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
 /*****************************************************************************
  * GE10
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
+static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
 
 static struct resource orion_ge10_shared_resources[] = {
         {
@@ -422,7 +423,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
 /*****************************************************************************
  * GE11
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
+static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
 
 static struct resource orion_ge11_shared_resources[] = {
         {
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index c492e1b3dfdb..807df142444b 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -15,8 +15,51 @@
 #include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <asm/exception.h>
 #include <plat/irq.h>
 #include <plat/orion-gpio.h>
+#include <mach/bridge-regs.h>
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ *
+ * Notes:
+ * - this is prepared for Kirkwood and Dove only, update
+ *   accordingly if you add Orion5x or MV78x00.
+ * - Orion5x uses different macro names and has only one
+ *   set of CAUSE/MASK registers.
+ * - MV78x00 uses the same macro names but has a third
+ *   set of CAUSE/MASK registers.
+ *
+ */
+
+static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
+
+asmlinkage void
+__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+
+        stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
+        stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
+        if (stat) {
+                unsigned int hwirq = __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+        stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
+        stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
+        if (stat) {
+                unsigned int hwirq = 32 + __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+}
+#endif
 
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
@@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
                                IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        set_handle_irq(orion_legacy_handle_irq);
+#endif
 }
 
 #ifdef CONFIG_OF
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 9d2b2ac74938..261258f717fc 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -17,6 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/sched_clock.h>
+#include <plat/time.h>
 
 /*
  * MBus bridge block registers.
@@ -60,7 +61,7 @@ static u32 ticks_per_jiffy;
  * at least 7.5ns (133MHz TCLK).
  */
 
-static u32 notrace orion_read_sched_clock(void)
+static u64 notrace orion_read_sched_clock(void)
 {
         return ~readl(timer_base + TIMER0_VAL_OFF);
 }
@@ -174,7 +175,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction orion_timer_irq = {
         .name           = "orion_tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .flags          = IRQF_TIMER,
         .handler        = orion_timer_interrupt
 };
 
@@ -201,7 +202,7 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
         /*
          * Set scale and timer for sched_clock.
          */
-        setup_sched_clock(orion_read_sched_clock, 32, tclk);
+        sched_clock_register(orion_read_sched_clock, 32, tclk);
 
         /*
          * Setup free-running clocksource timer (interrupts
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 79ef102e3b2b..054fc5a1a11c 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -377,7 +377,7 @@ int __init pxa_init_dma(int irq, int num_ch)
                 spin_lock_init(&dma_channels[i].lock);
         }
 
-        ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
+        ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL);
         if (ret) {
                 printk (KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
                 kfree(dma_channels);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6d95d60276d6..58645a58d0d8 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -24,7 +24,6 @@ config PLAT_S5P
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
         select SAMSUNG_CLKSRC if !COMMON_CLK
-        select SAMSUNG_GPIOLIB_4BIT
         help
           Base platform code for Samsung's S5P series SoC.
 
@@ -115,13 +114,6 @@ config S5P_GPIO_INT
 
 # options for gpio configuration support
 
-config SAMSUNG_GPIOLIB_4BIT
-        bool
-        help
-          GPIOlib file contains the 4 bit modification functions for gpio
-          configuration. GPIOlib shall be compiled only for S3C64XX and S5P
-          series of processors.
-
 config S5P_GPIO_DRVSTR
         bool
         help
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 99a3590f0349..ac07e871f6a7 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1468,6 +1468,8 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
 #if defined(CONFIG_PL330_DMA)
         pd.filter = pl330_filter;
+#elif defined(CONFIG_S3C64XX_PL080)
+        pd.filter = pl08x_filter_id;
 #elif defined(CONFIG_S3C24XX_DMAC)
         pd.filter = s3c24xx_dma_filter;
 #endif
@@ -1509,8 +1511,10 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.num_cs = num_cs;
         pd.src_clk_nr = src_clk_nr;
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
-#ifdef CONFIG_PL330_DMA
+#if defined(CONFIG_PL330_DMA)
         pd.filter = pl330_filter;
+#elif defined(CONFIG_S3C64XX_PL080)
+        pd.filter = pl08x_filter_id;
 #endif
 
         s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
@@ -1550,8 +1554,10 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.num_cs = num_cs;
         pd.src_clk_nr = src_clk_nr;
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
-#ifdef CONFIG_PL330_DMA
+#if defined(CONFIG_PL330_DMA)
         pd.filter = pl330_filter;
+#elif defined(CONFIG_S3C64XX_PL080)
+        pd.filter = pl08x_filter_id;
 #endif
 
         s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index ec0d731b0e7b..886326ee6f6c 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -18,6 +18,12 @@
 
 #include <mach/dma.h>
 
+#if defined(CONFIG_PL330_DMA)
+#define dma_filter pl330_filter
+#elif defined(CONFIG_S3C64XX_PL080)
+#define dma_filter pl08x_filter_id
+#endif
+
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
                                 struct samsung_dma_req *param,
                                 struct device *dev, char *ch_name)
@@ -30,7 +36,7 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
         if (dev->of_node)
                 return (unsigned)dma_request_slave_channel(dev, ch_name);
         else
-                return (unsigned)dma_request_channel(mask, pl330_filter,
+                return (unsigned)dma_request_channel(mask, dma_filter,
                                                         (void *)dma_ch);
 }
 
diff --git a/arch/arm/plat-samsung/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
deleted file mode 100644
index 535d06a35628..000000000000
--- a/arch/arm/plat-samsung/include/plat/fiq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/fiq.h
- *
- * Copyright (c) 2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU FIQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 6bc1a8f471e3..ff6063f0d5ea 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -101,8 +101,8 @@ struct pm_uart_save {
 /* helper functions to save/restore lists of registers. */
 
 extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
 
 #ifdef CONFIG_SAMSUNG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h b/arch/arm/plat-samsung/include/plat/regs-ata.h
deleted file mode 100644
index f5df92fdae26..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-ata.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/regs-ata.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Samsung CF-ATA register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_REGS_ATA_H
-#define __ASM_PLAT_REGS_ATA_H __FILE__
-
-#define S3C_CFATA_REG(x)        (x)
-
-#define S3C_CFATA_MUX           S3C_CFATA_REG(0x0)
-
-#define S3C_ATA_CTRL            S3C_CFATA_REG(0x0)
-#define S3C_ATA_STATUS          S3C_CFATA_REG(0x4)
-#define S3C_ATA_CMD             S3C_CFATA_REG(0x8)
-#define S3C_ATA_SWRST           S3C_CFATA_REG(0xc)
-#define S3C_ATA_IRQ             S3C_CFATA_REG(0x10)
-#define S3C_ATA_IRQ_MSK         S3C_CFATA_REG(0x14)
-#define S3C_ATA_CFG             S3C_CFATA_REG(0x18)
-
-#define S3C_ATA_MDMA_TIME       S3C_CFATA_REG(0x28)
-#define S3C_ATA_PIO_TIME        S3C_CFATA_REG(0x2c)
-#define S3C_ATA_UDMA_TIME       S3C_CFATA_REG(0x30)
-#define S3C_ATA_XFR_NUM         S3C_CFATA_REG(0x34)
-#define S3C_ATA_XFR_CNT         S3C_CFATA_REG(0x38)
-#define S3C_ATA_TBUF_START      S3C_CFATA_REG(0x3c)
-#define S3C_ATA_TBUF_SIZE       S3C_CFATA_REG(0x40)
-#define S3C_ATA_SBUF_START      S3C_CFATA_REG(0x44)
-#define S3C_ATA_SBUF_SIZE       S3C_CFATA_REG(0x48)
-#define S3C_ATA_CADR_TBUF       S3C_CFATA_REG(0x4c)
-#define S3C_ATA_CADR_SBUF       S3C_CFATA_REG(0x50)
-#define S3C_ATA_PIO_DTR         S3C_CFATA_REG(0x54)
-#define S3C_ATA_PIO_FED         S3C_CFATA_REG(0x58)
-#define S3C_ATA_PIO_SCR         S3C_CFATA_REG(0x5c)
-#define S3C_ATA_PIO_LLR         S3C_CFATA_REG(0x60)
-#define S3C_ATA_PIO_LMR         S3C_CFATA_REG(0x64)
-#define S3C_ATA_PIO_LHR         S3C_CFATA_REG(0x68)
-#define S3C_ATA_PIO_DVR         S3C_CFATA_REG(0x6c)
-#define S3C_ATA_PIO_CSD         S3C_CFATA_REG(0x70)
-#define S3C_ATA_PIO_DAD         S3C_CFATA_REG(0x74)
-#define S3C_ATA_PIO_READY       S3C_CFATA_REG(0x78)
-#define S3C_ATA_PIO_RDATA       S3C_CFATA_REG(0x7c)
-
-#define S3C_CFATA_MUX_TRUEIDE   0x01
-
-#define S3C_ATA_CFG_SWAP        0x40
-#define S3C_ATA_CFG_IORDYEN     0x02
-
-#endif /* __ASM_PLAT_REGS_ATA_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h
deleted file mode 100644
index 238efea7b9e4..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-nand.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
- *      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 NAND register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND
-
-
-#define S3C2410_NFREG(x) (x)
-
-#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
-#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
-#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
-#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
-#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
-#define S3C2410_NFECC   S3C2410_NFREG(0x14)
-
-#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
-#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
-#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
-#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
-#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
-#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
-#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
-#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
-#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
-#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
-#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
-#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
-#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
-#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
-#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
-
-#define S3C2412_NFSBLK          S3C2410_NFREG(0x20)
-#define S3C2412_NFEBLK          S3C2410_NFREG(0x24)
-#define S3C2412_NFSTAT          S3C2410_NFREG(0x28)
-#define S3C2412_NFMECC_ERR0     S3C2410_NFREG(0x2C)
-#define S3C2412_NFMECC_ERR1     S3C2410_NFREG(0x30)
-#define S3C2412_NFMECC0         S3C2410_NFREG(0x34)
-#define S3C2412_NFMECC1         S3C2410_NFREG(0x38)
-#define S3C2412_NFSECC          S3C2410_NFREG(0x3C)
-
-#define S3C2410_NFCONF_EN          (1<<15)
-#define S3C2410_NFCONF_512BYTE     (1<<14)
-#define S3C2410_NFCONF_4STEP       (1<<13)
-#define S3C2410_NFCONF_INITECC     (1<<12)
-#define S3C2410_NFCONF_nFCE        (1<<11)
-#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY        (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8       (0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16      (1<<0)
-#define S3C2440_NFCONF_ADVFLASH         (1<<3)
-#define S3C2440_NFCONF_TACLS(x)         ((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x)        ((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x)        ((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT        (1<<13)
-#define S3C2440_NFCONT_SOFTLOCK         (1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN    (1<<10)
-#define S3C2440_NFCONT_RNBINT_EN        (1<<9)
-#define S3C2440_NFCONT_RN_FALLING       (1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK    (1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK     (1<<5)
-#define S3C2440_NFCONT_INITECC          (1<<4)
-#define S3C2440_NFCONT_nFCE             (1<<1)
-#define S3C2440_NFCONT_ENABLE           (1<<0)
-
-#define S3C2440_NFSTAT_READY            (1<<0)
-#define S3C2440_NFSTAT_nCE              (1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE       (1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS   (1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT         (1<<31)
-#define S3C2412_NFCONF_ECCCLKCON        (1<<30)
-#define S3C2412_NFCONF_ECC_MLC          (1<<24)
-#define S3C2412_NFCONF_TACLS_MASK       (7<<12) /* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR       (1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT        (1<<17)
-#define S3C2412_NFCONT_SOFTLOCK         (1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT      (1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT      (1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK    (1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC    (1<<5)
-#define S3C2412_NFCONT_nFCE1            (1<<2)
-#define S3C2412_NFCONT_nFCE0            (1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE      (1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE      (1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS   (1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE       (1<<4)
-#define S3C2412_NFSTAT_nFCE1            (1<<3)
-#define S3C2412_NFSTAT_nFCE0            (1<<2)
-#define S3C2412_NFSTAT_Res1             (1<<1)
-#define S3C2412_NFSTAT_READY            (1<<0)
-
-#define S3C2412_NFECCERR_SERRDATA(x)    (((x) >> 21) & 0xf)
-#define S3C2412_NFECCERR_SERRBIT(x)     (((x) >> 18) & 0x7)
-#define S3C2412_NFECCERR_MERRDATA(x)    (((x) >> 7) & 0x3ff)
-#define S3C2412_NFECCERR_MERRBIT(x)     (((x) >> 4) & 0x7)
-#define S3C2412_NFECCERR_SPARE_ERR(x)   (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_MAIN_ERR(x)    (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_NONE           (0)
-#define S3C2412_NFECCERR_1BIT           (1)
-#define S3C2412_NFECCERR_MULTIBIT       (2)
-#define S3C2412_NFECCERR_ECCAREA        (3)
-
-
-
-#endif /* __ASM_ARM_REGS_NAND */
-
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 4afc32f90b6d..f48dc0a4736c 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void)
                         if (!(fifocon & S3C2410_UFCON_RESETBOTH))
                                 break;
                 }
+
+                uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
         }
 }
 #else
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index a8de3cfe2ee1..dd4c15d0d68f 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -19,6 +19,10 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
+#include <mach/gpio-samsung.h>
+#endif
+
 #include <plat/gpio-core.h>
 #include <plat/pm.h>
 
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index d0c23010b693..e5b0f2c2d884 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -28,8 +28,10 @@
 #ifdef CONFIG_SAMSUNG_ATAGS
 #include <mach/hardware.h>
 #include <mach/map.h>
+#ifndef CONFIG_ARCH_EXYNOS
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
+#endif
 #include <mach/irqs.h>
 #endif
 
@@ -182,7 +184,7 @@ void s3c_pm_do_save(struct sleep_save *ptr, int count)
  * restore the UARTs state yet
 */
 
-void s3c_pm_do_restore(struct sleep_save *ptr, int count)
+void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
 {
         for (; count > 0; count--, ptr++) {
                 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
@@ -203,7 +205,7 @@ void s3c_pm_do_restore(struct sleep_save *ptr, int count)
  * peripherals, as things may be changing!
 */
 
-void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
+void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
 {
         for (; count > 0; count--, ptr++)
                 __raw_writel(ptr->val, ptr->reg);
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
index faa651602780..ebee4dc11a94 100644
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ b/arch/arm/plat-samsung/s5p-irq-eint.c
@@ -16,6 +16,7 @@
 #include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/irqchip/arm-vic.h>
+#include <linux/of.h>
 
 #include <plat/regs-irqtype.h>
 
@@ -202,6 +203,9 @@ static int __init s5p_init_irq_eint(void)
 {
         int irq;
 
+        if (of_have_populated_dt())
+                return -ENODEV;
+
         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
                 irq_set_chip(irq, &s5p_irq_vic_eint);
 
diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
index 7c1e3b7072fc..591498035916 100644
--- a/arch/arm/plat-samsung/s5p-irq-pm.c
+++ b/arch/arm/plat-samsung/s5p-irq-pm.c
@@ -22,7 +22,10 @@
 #include <mach/map.h>
 
 #include <mach/regs-gpio.h>
+
+#ifndef CONFIG_ARCH_EXYNOS
 #include <mach/regs-irq.h>
+#endif
 
 /* state for IRQs over sleep */
 
diff --git a/arch/arm/plat-samsung/setup-camif.c b/arch/arm/plat-samsung/setup-camif.c
index e01bf760af2c..72d8edb8927a 100644
--- a/arch/arm/plat-samsung/setup-camif.c
+++ b/arch/arm/plat-samsung/setup-camif.c
@@ -10,6 +10,7 @@
 
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
+#include <mach/gpio-samsung.h>
 
 /* Number of camera port pins, without FIELD */
 #define S3C_CAMIF_NUM_GPIOS     13
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 39895d892c3b..53feb90c840c 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -27,8 +27,7 @@ static void write_pen_release(int val)
 {
         pen_release = val;
         smp_wmb();
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        sync_cache_w(&pen_release);
 }
 
 static DEFINE_SPINLOCK(boot_lock);
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
index 51b109e3b6c3..c966ae90f4a0 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -26,7 +26,7 @@
 
 static void __iomem *ctr;
 
-static u32 notrace versatile_read_sched_clock(void)
+static u64 notrace versatile_read_sched_clock(void)
 {
         if (ctr)
                 return readl(ctr);
@@ -37,5 +37,5 @@ static u32 notrace versatile_read_sched_clock(void)
 void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate)
 {
         ctr = reg;
-        setup_sched_clock(versatile_read_sched_clock, 32, rate);
+        sched_clock_register(versatile_read_sched_clock, 32, rate);
 }
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 85501238b425..b96723e258a0 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -23,6 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/cpuidle.h>
 #include <linux/cpufreq.h>
+#include <linux/cpu.h>
 
 #include <linux/mm.h>
 
@@ -154,7 +155,7 @@ int xen_unmap_domain_mfn_range(struct vm_area_struct *vma,
 }
 EXPORT_SYMBOL_GPL(xen_unmap_domain_mfn_range);
 
-static void __init xen_percpu_init(void *unused)
+static void xen_percpu_init(void)
 {
         struct vcpu_register_vcpu_info info;
         struct vcpu_info *vcpup;
@@ -193,6 +194,31 @@ static void xen_power_off(void)
                 BUG();
 }
 
+static int xen_cpu_notification(struct notifier_block *self,
+                                unsigned long action,
+                                void *hcpu)
+{
+        switch (action) {
+        case CPU_STARTING:
+                xen_percpu_init();
+                break;
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block xen_cpu_notifier = {
+        .notifier_call = xen_cpu_notification,
+};
+
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+        xen_hvm_evtchn_do_upcall();
+        return IRQ_HANDLED;
+}
+
 /*
  * see Documentation/devicetree/bindings/arm/xen.txt for the
  * documentation of the Xen Device Tree format.
@@ -208,6 +234,7 @@ static int __init xen_guest_init(void)
         const char *version = NULL;
         const char *xen_prefix = "xen,xen-";
         struct resource res;
+        phys_addr_t grant_frames;
 
         node = of_find_compatible_node(NULL, NULL, "xen,xen");
         if (!node) {
@@ -224,10 +251,14 @@ static int __init xen_guest_init(void)
         }
         if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
                 return 0;
-        xen_hvm_resume_frames = res.start;
+        grant_frames = res.start;
         xen_events_irq = irq_of_parse_and_map(node, 0);
-        pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
-                        version, xen_events_irq, (xen_hvm_resume_frames >> PAGE_SHIFT));
+        pr_info("Xen %s support found, events_irq=%d gnttab_frame=%pa\n",
+                        version, xen_events_irq, &grant_frames);
+
+        if (xen_events_irq < 0)
+                return -ENODEV;
+
         xen_domain_type = XEN_HVM_DOMAIN;
 
         xen_setup_features();
@@ -265,6 +296,10 @@ static int __init xen_guest_init(void)
         if (xen_vcpu_info == NULL)
                 return -ENOMEM;
 
+        if (gnttab_setup_auto_xlat_frames(grant_frames)) {
+                free_percpu(xen_vcpu_info);
+                return -ENOMEM;
+        }
         gnttab_init();
         if (!xen_initial_domain())
                 xenbus_probe(NULL);
@@ -276,9 +311,21 @@ static int __init xen_guest_init(void)
         disable_cpuidle();
         disable_cpufreq();
 
+        xen_init_IRQ();
+
+        if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+                               "events", &xen_vcpu)) {
+                pr_err("Error request IRQ %d\n", xen_events_irq);
+                return -EINVAL;
+        }
+
+        xen_percpu_init();
+
+        register_cpu_notifier(&xen_cpu_notifier);
+
         return 0;
 }
-core_initcall(xen_guest_init);
+early_initcall(xen_guest_init);
 
 static int __init xen_pm_init(void)
 {
@@ -292,31 +339,6 @@ static int __init xen_pm_init(void)
 }
 late_initcall(xen_pm_init);
 
-static irqreturn_t xen_arm_callback(int irq, void *arg)
-{
-        xen_hvm_evtchn_do_upcall();
-        return IRQ_HANDLED;
-}
-
-static int __init xen_init_events(void)
-{
-        if (!xen_domain() || xen_events_irq < 0)
-                return -ENODEV;
-
-        xen_init_IRQ();
-
-        if (request_percpu_irq(xen_events_irq, xen_arm_callback,
-                        "events", &xen_vcpu)) {
-                pr_err("Error requesting IRQ %d\n", xen_events_irq);
-                return -EINVAL;
-        }
-
-        on_each_cpu(xen_percpu_init, NULL, 0);
-
-        return 0;
-}
-postcore_initcall(xen_init_events);
-
 /* In the hypervisor.S file. */
 EXPORT_SYMBOL_GPL(HYPERVISOR_event_channel_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_grant_table_op);
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 6d4dd22ee4b7..dd4327f09ba4 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2,6 +2,7 @@ config ARM64
         def_bool y
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select ARCH_USE_CMPXCHG_LOCKREF
+        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
         select ARCH_WANT_FRAME_POINTERS
@@ -11,19 +12,27 @@ config ARM64
         select BUILDTIME_EXTABLE_SORT
         select CLONE_BACKWARDS
         select COMMON_CLK
+        select CPU_PM if (SUSPEND || CPU_IDLE)
+        select DCACHE_WORD_ACCESS
         select GENERIC_CLOCKEVENTS
+        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_IOMAP
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
         select GENERIC_SCHED_CLOCK
         select GENERIC_SMP_IDLE_THREAD
+        select GENERIC_STRNCPY_FROM_USER
+        select GENERIC_STRNLEN_USER
         select GENERIC_TIME_VSYSCALL
         select HARDIRQS_SW_RESEND
+        select HAVE_ARCH_JUMP_LABEL
         select HAVE_ARCH_TRACEHOOK
         select HAVE_DEBUG_BUGVERBOSE
         select HAVE_DEBUG_KMEMLEAK
         select HAVE_DMA_API_DEBUG
         select HAVE_DMA_ATTRS
+        select HAVE_DMA_CONTIGUOUS
+        select HAVE_EFFICIENT_UNALIGNED_ACCESS
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_HW_BREAKPOINT if PERF_EVENTS
         select HAVE_MEMBLOCK
@@ -275,6 +284,24 @@ config SYSVIPC_COMPAT
 
 endmenu
 
+menu "Power management options"
+
+source "kernel/power/Kconfig"
+
+config ARCH_SUSPEND_POSSIBLE
+        def_bool y
+
+config ARM64_CPU_SUSPEND
+        def_bool PM_SLEEP
+
+endmenu
+
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
 source "net/Kconfig"
 
 source "drivers/Kconfig"
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts
index 519c4b2c0687..4a060906809d 100644
--- a/arch/arm64/boot/dts/foundation-v8.dts
+++ b/arch/arm64/boot/dts/foundation-v8.dts
@@ -224,7 +224,7 @@
 
                         virtio_block@0130000 {
                                 compatible = "virtio,mmio";
-                                reg = <0x130000 0x1000>;
+                                reg = <0x130000 0x200>;
                                 interrupts = <42>;
                         };
                 };
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
index b45e5f39f577..2f2ecd217363 100644
--- a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
@@ -183,6 +183,12 @@
                                 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
                                 clock-names = "clcdclk", "apb_pclk";
                         };
+
+                        virtio_block@0130000 {
+                                compatible = "virtio,mmio";
+                                reg = <0x130000 0x200>;
+                                interrupts = <42>;
+                        };
                 };
 
                 v2m_fixed_3v3: fixedregulator@0 {
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 519f89f5b6a3..71c53ecfcc3a 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -26,7 +26,6 @@ generic-y += mman.h
 generic-y += msgbuf.h
 generic-y += mutex.h
 generic-y += pci.h
-generic-y += percpu.h
 generic-y += poll.h
 generic-y += posix_types.h
 generic-y += resource.h
@@ -51,3 +50,4 @@ generic-y += user.h
 generic-y += vga.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 3914c0dcd09c..56166d7f4a25 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -158,17 +158,23 @@ static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
         return ret;
 }
 
-#define cmpxchg(ptr,o,n)                                                \
-        ((__typeof__(*(ptr)))__cmpxchg_mb((ptr),                        \
-                                          (unsigned long)(o),           \
-                                          (unsigned long)(n),           \
-                                          sizeof(*(ptr))))
-
-#define cmpxchg_local(ptr,o,n)                                          \
-        ((__typeof__(*(ptr)))__cmpxchg((ptr),                           \
-                                       (unsigned long)(o),              \
-                                       (unsigned long)(n),              \
-                                       sizeof(*(ptr))))
+#define cmpxchg(ptr, o, n) \
+({ \
+        __typeof__(*(ptr)) __ret; \
+        __ret = (__typeof__(*(ptr))) \
+                __cmpxchg_mb((ptr), (unsigned long)(o), (unsigned long)(n), \
+                             sizeof(*(ptr))); \
+        __ret; \
+})
+
+#define cmpxchg_local(ptr, o, n) \
+({ \
+        __typeof__(*(ptr)) __ret; \
+        __ret = (__typeof__(*(ptr))) \
+                __cmpxchg((ptr), (unsigned long)(o), \
+                          (unsigned long)(n), sizeof(*(ptr))); \
+        __ret; \
+})
 
 #define cmpxchg64(ptr,o,n)              cmpxchg((ptr),(o),(n))
 #define cmpxchg64_local(ptr,o,n)        cmpxchg_local((ptr),(o),(n))
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index c4cdb5e5b73d..152413076503 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -39,6 +39,9 @@ struct device_node;
  *              from the cpu to be killed.
  * @cpu_die:    Makes a cpu leave the kernel. Must not fail. Called from the
  *              cpu being killed.
+ * @cpu_suspend: Suspends a cpu and saves the required context. May fail owing
+ *               to wrong parameters or error conditions. Called from the
+ *               CPU being suspended. Must be called with IRQs disabled.
  */
 struct cpu_operations {
         const char      *name;
@@ -50,6 +53,9 @@ struct cpu_operations {
         int             (*cpu_disable)(unsigned int cpu);
         void            (*cpu_die)(unsigned int cpu);
 #endif
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+        int             (*cpu_suspend)(unsigned long);
+#endif
 };
 
 extern const struct cpu_operations *cpu_ops[NR_CPUS];
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 5fe138e0b828..c404fb0df3a6 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -16,23 +16,23 @@
 #ifndef __ASM_CPUTYPE_H
 #define __ASM_CPUTYPE_H
 
-#define ID_MIDR_EL1             "midr_el1"
-#define ID_MPIDR_EL1            "mpidr_el1"
-#define ID_CTR_EL0              "ctr_el0"
-
-#define ID_AA64PFR0_EL1         "id_aa64pfr0_el1"
-#define ID_AA64DFR0_EL1         "id_aa64dfr0_el1"
-#define ID_AA64AFR0_EL1         "id_aa64afr0_el1"
-#define ID_AA64ISAR0_EL1        "id_aa64isar0_el1"
-#define ID_AA64MMFR0_EL1        "id_aa64mmfr0_el1"
-
 #define INVALID_HWID            ULONG_MAX
 
 #define MPIDR_HWID_BITMASK      0xff00ffffff
 
+#define MPIDR_LEVEL_BITS_SHIFT  3
+#define MPIDR_LEVEL_BITS        (1 << MPIDR_LEVEL_BITS_SHIFT)
+#define MPIDR_LEVEL_MASK        ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_LEVEL_SHIFT(level) \
+        (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
+
+#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+        ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+
 #define read_cpuid(reg) ({                                              \
         u64 __val;                                                      \
-        asm("mrs        %0, " reg : "=r" (__val));                      \
+        asm("mrs        %0, " #reg : "=r" (__val));                     \
         __val;                                                          \
 })
 
@@ -54,12 +54,12 @@
  */
 static inline u32 __attribute_const__ read_cpuid_id(void)
 {
-        return read_cpuid(ID_MIDR_EL1);
+        return read_cpuid(MIDR_EL1);
 }
 
 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
 {
-        return read_cpuid(ID_MPIDR_EL1);
+        return read_cpuid(MPIDR_EL1);
 }
 
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
@@ -74,7 +74,7 @@ static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 
 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
 {
-        return read_cpuid(ID_CTR_EL0);
+        return read_cpuid(CTR_EL0);
 }
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index a2232d07be9d..62314791570c 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -62,6 +62,27 @@ struct task_struct;
 
 #define DBG_ARCH_ID_RESERVED    0       /* In case of ptrace ABI updates. */
 
+#define DBG_HOOK_HANDLED        0
+#define DBG_HOOK_ERROR          1
+
+struct step_hook {
+        struct list_head node;
+        int (*fn)(struct pt_regs *regs, unsigned int esr);
+};
+
+void register_step_hook(struct step_hook *hook);
+void unregister_step_hook(struct step_hook *hook);
+
+struct break_hook {
+        struct list_head node;
+        u32 esr_val;
+        u32 esr_mask;
+        int (*fn)(struct pt_regs *regs, unsigned int esr);
+};
+
+void register_break_hook(struct break_hook *hook);
+void unregister_break_hook(struct break_hook *hook);
+
 u8 debug_monitors_arch(void);
 
 void enable_debug_monitors(enum debug_el el);
diff --git a/arch/arm64/include/asm/dma-contiguous.h b/arch/arm64/include/asm/dma-contiguous.h
new file mode 100644
index 000000000000..14c4c0ca7f2a
--- /dev/null
+++ b/arch/arm64/include/asm/dma-contiguous.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ASM_DMA_CONTIGUOUS_H
+#define _ASM_DMA_CONTIGUOUS_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_DMA_CMA
+
+#include <linux/types.h>
+
+static inline void
+dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { }
+
+#endif
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index c582fa316366..78cc3aba5d69 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -30,6 +30,7 @@
 "       cbnz    %w3, 1b\n"                                              \
 "3:\n"                                                                  \
 "       .pushsection .fixup,\"ax\"\n"                                   \
+"       .align  2\n"                                                    \
 "4:     mov     %w0, %w5\n"                                             \
 "       b       3b\n"                                                   \
 "       .popsection\n"                                                  \
diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index 990c051e7829..ae4801d77514 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -20,7 +20,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
-#define NR_IPI  4
+#define NR_IPI  5
 
 typedef struct {
         unsigned int __softirq_pending;
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
new file mode 100644
index 000000000000..c44ad39ed310
--- /dev/null
+++ b/arch/arm64/include/asm/insn.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2013 Huawei Ltd.
+ * Author: Jiang Liu <liuj97@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_INSN_H
+#define __ASM_INSN_H
+#include <linux/types.h>
+
+/* A64 instructions are always 32 bits. */
+#define AARCH64_INSN_SIZE               4
+
+/*
+ * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
+ * Section C3.1 "A64 instruction index by encoding":
+ * AArch64 main encoding table
+ *  Bit position
+ *   28 27 26 25        Encoding Group
+ *   0  0  -  -         Unallocated
+ *   1  0  0  -         Data processing, immediate
+ *   1  0  1  -         Branch, exception generation and system instructions
+ *   -  1  -  0         Loads and stores
+ *   -  1  0  1         Data processing - register
+ *   0  1  1  1         Data processing - SIMD and floating point
+ *   1  1  1  1         Data processing - SIMD and floating point
+ * "-" means "don't care"
+ */
+enum aarch64_insn_encoding_class {
+        AARCH64_INSN_CLS_UNKNOWN,       /* UNALLOCATED */
+        AARCH64_INSN_CLS_DP_IMM,        /* Data processing - immediate */
+        AARCH64_INSN_CLS_DP_REG,        /* Data processing - register */
+        AARCH64_INSN_CLS_DP_FPSIMD,     /* Data processing - SIMD and FP */
+        AARCH64_INSN_CLS_LDST,          /* Loads and stores */
+        AARCH64_INSN_CLS_BR_SYS,        /* Branch, exception generation and
+                                         * system instructions */
+};
+
+enum aarch64_insn_hint_op {
+        AARCH64_INSN_HINT_NOP   = 0x0 << 5,
+        AARCH64_INSN_HINT_YIELD = 0x1 << 5,
+        AARCH64_INSN_HINT_WFE   = 0x2 << 5,
+        AARCH64_INSN_HINT_WFI   = 0x3 << 5,
+        AARCH64_INSN_HINT_SEV   = 0x4 << 5,
+        AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
+};
+
+enum aarch64_insn_imm_type {
+        AARCH64_INSN_IMM_ADR,
+        AARCH64_INSN_IMM_26,
+        AARCH64_INSN_IMM_19,
+        AARCH64_INSN_IMM_16,
+        AARCH64_INSN_IMM_14,
+        AARCH64_INSN_IMM_12,
+        AARCH64_INSN_IMM_9,
+        AARCH64_INSN_IMM_MAX
+};
+
+enum aarch64_insn_branch_type {
+        AARCH64_INSN_BRANCH_NOLINK,
+        AARCH64_INSN_BRANCH_LINK,
+};
+
+#define __AARCH64_INSN_FUNCS(abbr, mask, val)   \
+static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
+{ return (code & (mask)) == (val); } \
+static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
+{ return (val); }
+
+__AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
+__AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
+__AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
+__AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
+__AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
+__AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
+__AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
+
+#undef  __AARCH64_INSN_FUNCS
+
+bool aarch64_insn_is_nop(u32 insn);
+
+int aarch64_insn_read(void *addr, u32 *insnp);
+int aarch64_insn_write(void *addr, u32 insn);
+enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
+u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
+                                  u32 insn, u64 imm);
+u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
+                                enum aarch64_insn_branch_type type);
+u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
+u32 aarch64_insn_gen_nop(void);
+
+bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
+
+int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
+int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
+int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
+
+#endif  /* __ASM_INSN_H */
diff --git a/arch/arm64/include/asm/jump_label.h b/arch/arm64/include/asm/jump_label.h
new file mode 100644
index 000000000000..076a1c714049
--- /dev/null
+++ b/arch/arm64/include/asm/jump_label.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 Huawei Ltd.
+ * Author: Jiang Liu <liuj97@gmail.com>
+ *
+ * Based on arch/arm/include/asm/jump_label.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_JUMP_LABEL_H
+#define __ASM_JUMP_LABEL_H
+#include <linux/types.h>
+#include <asm/insn.h>
+
+#ifdef __KERNEL__
+
+#define JUMP_LABEL_NOP_SIZE             AARCH64_INSN_SIZE
+
+static __always_inline bool arch_static_branch(struct static_key *key)
+{
+        asm goto("1: nop\n\t"
+                 ".pushsection __jump_table,  \"aw\"\n\t"
+                 ".align 3\n\t"
+                 ".quad 1b, %l[l_yes], %c0\n\t"
+                 ".popsection\n\t"
+                 :  :  "i"(key) :  : l_yes);
+
+        return false;
+l_yes:
+        return true;
+}
+
+#endif /* __KERNEL__ */
+
+typedef u64 jump_label_t;
+
+struct jump_entry {
+        jump_label_t code;
+        jump_label_t target;
+        jump_label_t key;
+};
+
+#endif  /* __ASM_JUMP_LABEL_H */
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 5d85a02d1231..0a1d69751562 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -26,7 +26,12 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 
-#define KVM_MAX_VCPUS 4
+#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
+#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#else
+#define KVM_MAX_VCPUS 0
+#endif
+
 #define KVM_USER_MEM_SLOTS 32
 #define KVM_PRIVATE_MEM_SLOTS 4
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 680f74e67497..7f1f9408ff66 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -136,6 +136,7 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
 }
 
 #define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
+#define kvm_virt_to_phys(x)             __virt_to_phys((unsigned long)(x))
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ARM64_KVM_MMU_H__ */
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 37762175896f..9dc5dc39fded 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -146,8 +146,7 @@ static inline void *phys_to_virt(phys_addr_t x)
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                 ((void *)(kaddr) < (void *)high_memory))
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
 
 #endif
 
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
new file mode 100644
index 000000000000..13fb0b3efc5f
--- /dev/null
+++ b/arch/arm64/include/asm/percpu.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PERCPU_H
+#define __ASM_PERCPU_H
+
+static inline void set_my_cpu_offset(unsigned long off)
+{
+        asm volatile("msr tpidr_el1, %0" :: "r" (off) : "memory");
+}
+
+static inline unsigned long __my_cpu_offset(void)
+{
+        unsigned long off;
+        register unsigned long *sp asm ("sp");
+
+        /*
+         * We want to allow caching the value, so avoid using volatile and
+         * instead use a fake stack read to hazard against barrier().
+         */
+        asm("mrs %0, tpidr_el1" : "=r" (off) : "Q" (*sp));
+
+        return off;
+}
+#define __my_cpu_offset __my_cpu_offset()
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ASM_PERCPU_H */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 7f2b60affbb4..b524dcd17243 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -28,7 +28,7 @@
 #define PTE_FILE                (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
 #define PTE_DIRTY               (_AT(pteval_t, 1) << 55)
 #define PTE_SPECIAL             (_AT(pteval_t, 1) << 56)
-                                /* bit 57 for PMD_SECT_SPLITTING */
+#define PTE_WRITE               (_AT(pteval_t, 1) << 57)
 #define PTE_PROT_NONE           (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
 
 /*
@@ -67,15 +67,15 @@ extern pgprot_t pgprot_default;
 
 #define _MOD_PROT(p, b)         __pgprot_modify(p, 0, b)
 
-#define PAGE_NONE               __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
-#define PAGE_SHARED             _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
-#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
-#define PAGE_COPY               _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
-#define PAGE_READONLY           _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
-#define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
-#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
+#define PAGE_NONE               __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_PXN | PTE_UXN)
+#define PAGE_SHARED             _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
+#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
+#define PAGE_COPY               _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
+#define PAGE_READONLY           _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
+#define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
+#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY | PTE_WRITE)
 
 #define PAGE_HYP                _MOD_PROT(pgprot_default, PTE_HYP)
 #define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
@@ -83,13 +83,13 @@ extern pgprot_t pgprot_default;
 #define PAGE_S2                 __pgprot_modify(pgprot_default, PTE_S2_MEMATTR_MASK, PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
 #define PAGE_S2_DEVICE          __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
 
-#define __PAGE_NONE             __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
-#define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
-#define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
-#define __PAGE_COPY             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-#define __PAGE_COPY_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
-#define __PAGE_READONLY         __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
-#define __PAGE_READONLY_EXEC    __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_RDONLY)
+#define __PAGE_NONE             __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
+#define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
+#define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
+#define __PAGE_COPY             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define __PAGE_COPY_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
+#define __PAGE_READONLY         __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
+#define __PAGE_READONLY_EXEC    __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
 
 #endif /* __ASSEMBLY__ */
 
@@ -140,22 +140,53 @@ extern struct page *empty_zero_page;
 #define pte_dirty(pte)          (pte_val(pte) & PTE_DIRTY)
 #define pte_young(pte)          (pte_val(pte) & PTE_AF)
 #define pte_special(pte)        (pte_val(pte) & PTE_SPECIAL)
-#define pte_write(pte)          (!(pte_val(pte) & PTE_RDONLY))
+#define pte_write(pte)          (pte_val(pte) & PTE_WRITE)
 #define pte_exec(pte)           (!(pte_val(pte) & PTE_UXN))
 
 #define pte_valid_user(pte) \
         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
 
-#define PTE_BIT_FUNC(fn,op) \
-static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) &= ~PTE_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) |= PTE_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte_val(pte) &= ~PTE_DIRTY;
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte_val(pte) |= PTE_DIRTY;
+        return pte;
+}
 
-PTE_BIT_FUNC(wrprotect, |= PTE_RDONLY);
-PTE_BIT_FUNC(mkwrite,   &= ~PTE_RDONLY);
-PTE_BIT_FUNC(mkclean,   &= ~PTE_DIRTY);
-PTE_BIT_FUNC(mkdirty,   |= PTE_DIRTY);
-PTE_BIT_FUNC(mkold,     &= ~PTE_AF);
-PTE_BIT_FUNC(mkyoung,   |= PTE_AF);
-PTE_BIT_FUNC(mkspecial, |= PTE_SPECIAL);
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte_val(pte) &= ~PTE_AF;
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte_val(pte) |= PTE_AF;
+        return pte;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        pte_val(pte) |= PTE_SPECIAL;
+        return pte;
+}
 
 static inline void set_pte(pte_t *ptep, pte_t pte)
 {
@@ -170,8 +201,10 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
         if (pte_valid_user(pte)) {
                 if (pte_exec(pte))
                         __sync_icache_dcache(pte, addr);
-                if (!pte_dirty(pte))
-                        pte = pte_wrprotect(pte);
+                if (pte_dirty(pte) && pte_write(pte))
+                        pte_val(pte) &= ~PTE_RDONLY;
+                else
+                        pte_val(pte) |= PTE_RDONLY;
         }
 
         set_pte(ptep, pte);
@@ -345,7 +378,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
         const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
-                              PTE_PROT_NONE | PTE_VALID;
+                              PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
         return pte;
 }
diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h
index 7cdf466fd0c5..0c657bb54597 100644
--- a/arch/arm64/include/asm/proc-fns.h
+++ b/arch/arm64/include/asm/proc-fns.h
@@ -26,11 +26,14 @@
 #include <asm/page.h>
 
 struct mm_struct;
+struct cpu_suspend_ctx;
 
 extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
+extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
 #include <asm/memory.h>
 
diff --git a/arch/arm64/include/asm/smp_plat.h b/arch/arm64/include/asm/smp_plat.h
index ed43a0d2b1b2..59e282311b58 100644
--- a/arch/arm64/include/asm/smp_plat.h
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -21,6 +21,19 @@
 
 #include <asm/types.h>
 
+struct mpidr_hash {
+        u64     mask;
+        u32     shift_aff[4];
+        u32     bits;
+};
+
+extern struct mpidr_hash mpidr_hash;
+
+static inline u32 mpidr_hash_size(void)
+{
+        return 1 << mpidr_hash.bits;
+}
+
 /*
  * Logical CPU mapping.
  */
diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/suspend.h
new file mode 100644
index 000000000000..e9c149c042e0
--- /dev/null
+++ b/arch/arm64/include/asm/suspend.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SUSPEND_H
+#define __ASM_SUSPEND_H
+
+#define NR_CTX_REGS 11
+
+/*
+ * struct cpu_suspend_ctx must be 16-byte aligned since it is allocated on
+ * the stack, which must be 16-byte aligned on v8
+ */
+struct cpu_suspend_ctx {
+        /*
+         * This struct must be kept in sync with
+         * cpu_do_{suspend/resume} in mm/proc.S
+         */
+        u64 ctx_regs[NR_CTX_REGS];
+        u64 sp;
+} __aligned(16);
+
+struct sleep_save_sp {
+        phys_addr_t *save_ptr_stash;
+        phys_addr_t save_ptr_stash_phys;
+};
+
+extern void cpu_resume(void);
+extern int cpu_suspend(unsigned long);
+
+#endif
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 7ecc2b23882e..6c0f684aca81 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -100,6 +100,7 @@ static inline void set_fs(mm_segment_t fs)
 })
 
 #define access_ok(type, addr, size)     __range_ok(addr, size)
+#define user_addr_max                   get_fs
 
 /*
  * The "__xxx" versions of the user access functions do not verify the address
@@ -240,9 +241,6 @@ extern unsigned long __must_check __copy_to_user(void __user *to, const void *fr
 extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n);
 extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
 
-extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count);
-extern unsigned long __must_check __strnlen_user(const char __user *s, long n);
-
 static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
 {
         if (access_ok(VERIFY_READ, from, n))
@@ -276,24 +274,9 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo
         return n;
 }
 
-static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res = -EFAULT;
-        if (access_ok(VERIFY_READ, src, 1))
-                res = __strncpy_from_user(dst, src, count);
-        return res;
-}
-
-#define strlen_user(s)  strnlen_user(s, ~0UL >> 1)
+extern long strncpy_from_user(char *dest, const char __user *src, long count);
 
-static inline long __must_check strnlen_user(const char __user *s, long n)
-{
-        unsigned long res = 0;
-
-        if (__addr_ok(s))
-                res = __strnlen_user(s, n);
-
-        return res;
-}
+extern __must_check long strlen_user(const char __user *str);
+extern __must_check long strnlen_user(const char __user *str, long n);
 
 #endif /* __ASM_UACCESS_H */
diff --git a/arch/arm64/include/asm/word-at-a-time.h b/arch/arm64/include/asm/word-at-a-time.h
new file mode 100644
index 000000000000..aab5bf09e9d9
--- /dev/null
+++ b/arch/arm64/include/asm/word-at-a-time.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_WORD_AT_A_TIME_H
+#define __ASM_WORD_AT_A_TIME_H
+
+#ifndef __AARCH64EB__
+
+#include <linux/kernel.h>
+
+struct word_at_a_time {
+        const unsigned long one_bits, high_bits;
+};
+
+#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
+
+static inline unsigned long has_zero(unsigned long a, unsigned long *bits,
+                                     const struct word_at_a_time *c)
+{
+        unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
+        *bits = mask;
+        return mask;
+}
+
+#define prep_zero_mask(a, bits, c) (bits)
+
+static inline unsigned long create_zero_mask(unsigned long bits)
+{
+        bits = (bits - 1) & ~bits;
+        return bits >> 7;
+}
+
+static inline unsigned long find_zero(unsigned long mask)
+{
+        return fls64(mask) >> 3;
+}
+
+#define zero_bytemask(mask) (mask)
+
+#else   /* __AARCH64EB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, offset;
+
+        /* Load word from unaligned pointer addr */
+        asm(
+        "1:     ldr     %0, %3\n"
+        "2:\n"
+        "       .pushsection .fixup,\"ax\"\n"
+        "       .align 2\n"
+        "3:     and     %1, %2, #0x7\n"
+        "       bic     %2, %2, #0x7\n"
+        "       ldr     %0, [%2]\n"
+        "       lsl     %1, %1, #0x3\n"
+#ifndef __AARCH64EB__
+        "       lsr     %0, %0, %1\n"
+#else
+        "       lsl     %0, %0, %1\n"
+#endif
+        "       b       2b\n"
+        "       .popsection\n"
+        "       .pushsection __ex_table,\"a\"\n"
+        "       .align  3\n"
+        "       .quad   1b, 3b\n"
+        "       .popsection"
+        : "=&r" (ret), "=&r" (offset)
+        : "r" (addr), "Q" (*(unsigned long *)addr));
+
+        return ret;
+}
+
+#endif /* __ASM_WORD_AT_A_TIME_H */
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 9b12476e9c85..73cf0f54d57c 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -22,6 +22,10 @@
 #define HWCAP_FP                (1 << 0)
 #define HWCAP_ASIMD             (1 << 1)
 #define HWCAP_EVTSTRM           (1 << 2)
-
+#define HWCAP_AES               (1 << 3)
+#define HWCAP_PMULL             (1 << 4)
+#define HWCAP_SHA1              (1 << 5)
+#define HWCAP_SHA2              (1 << 6)
+#define HWCAP_CRC32             (1 << 7)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 5031f4263937..495ab6f84a61 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -55,8 +55,9 @@ struct kvm_regs {
 #define KVM_ARM_TARGET_AEM_V8           0
 #define KVM_ARM_TARGET_FOUNDATION_V8    1
 #define KVM_ARM_TARGET_CORTEX_A57       2
+#define KVM_ARM_TARGET_XGENE_POTENZA    3
 
-#define KVM_ARM_NUM_TARGETS             3
+#define KVM_ARM_NUM_TARGETS             4
 
 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
 #define KVM_ARM_DEVICE_TYPE_SHIFT       0
@@ -129,6 +130,24 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT  0
 
+#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
+        (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
+        KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
+
+#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
+        (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
+        ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
+        ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
+        ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
+        ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
+        ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
+
+#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
+
+#define KVM_REG_ARM_TIMER_CTL           ARM64_SYS_REG(3, 3, 14, 3, 1)
+#define KVM_REG_ARM_TIMER_CNT           ARM64_SYS_REG(3, 3, 14, 3, 2)
+#define KVM_REG_ARM_TIMER_CVAL          ARM64_SYS_REG(3, 3, 14, 0, 2)
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
 #define KVM_ARM_IRQ_TYPE_MASK           0xff
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5ba2fd43a75b..2d4554b13410 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -9,7 +9,7 @@ AFLAGS_head.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 arm64-obj-y             := cputable.o debug-monitors.o entry.o irq.o fpsimd.o   \
                            entry-fpsimd.o process.o ptrace.o setup.o signal.o   \
                            sys.o stacktrace.o time.o traps.o io.o vdso.o        \
-                           hyp-stub.o psci.o cpu_ops.o
+                           hyp-stub.o psci.o cpu_ops.o insn.o
 
 arm64-obj-$(CONFIG_COMPAT)              += sys32.o kuser32.o signal32.o         \
                                            sys_compat.o
@@ -18,6 +18,8 @@ arm64-obj-$(CONFIG_SMP)			+= smp.o smp_spin_table.o
 arm64-obj-$(CONFIG_HW_PERF_EVENTS)      += perf_event.o
 arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
 arm64-obj-$(CONFIG_EARLY_PRINTK)        += early_printk.o
+arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND)   += sleep.o suspend.o
+arm64-obj-$(CONFIG_JUMP_LABEL)          += jump_label.o
 
 obj-y                                   += $(arm64-obj-y) vdso/
 obj-m                                   += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
index e7ee770c0697..338b568cd8ae 100644
--- a/arch/arm64/kernel/arm64ksyms.c
+++ b/arch/arm64/kernel/arm64ksyms.c
@@ -29,13 +29,10 @@
 
 #include <asm/checksum.h>
 
-        /* user mem (segment) */
-EXPORT_SYMBOL(__strnlen_user);
-EXPORT_SYMBOL(__strncpy_from_user);
-
 EXPORT_SYMBOL(copy_page);
 EXPORT_SYMBOL(clear_page);
 
+        /* user mem (segment) */
 EXPORT_SYMBOL(__copy_from_user);
 EXPORT_SYMBOL(__copy_to_user);
 EXPORT_SYMBOL(__clear_user);
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index 666e231d410b..646f888387cd 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -25,6 +25,8 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/cputable.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
 #include <asm/vdso_datapage.h>
 #include <linux/kbuild.h>
 
@@ -138,5 +140,14 @@ int main(void)
   DEFINE(KVM_VTTBR,             offsetof(struct kvm, arch.vttbr));
   DEFINE(KVM_VGIC_VCTRL,        offsetof(struct kvm, arch.vgic.vctrl_base));
 #endif
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+  DEFINE(CPU_SUSPEND_SZ,        sizeof(struct cpu_suspend_ctx));
+  DEFINE(CPU_CTX_SP,            offsetof(struct cpu_suspend_ctx, sp));
+  DEFINE(MPIDR_HASH_MASK,       offsetof(struct mpidr_hash, mask));
+  DEFINE(MPIDR_HASH_SHIFTS,     offsetof(struct mpidr_hash, shift_aff));
+  DEFINE(SLEEP_SAVE_SP_SZ,      sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,    offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,    offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   return 0;
 }
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 4ae68579031d..636ba8b6240b 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -187,6 +187,48 @@ static void clear_regs_spsr_ss(struct pt_regs *regs)
         regs->pstate = spsr;
 }
 
+/* EL1 Single Step Handler hooks */
+static LIST_HEAD(step_hook);
+DEFINE_RWLOCK(step_hook_lock);
+
+void register_step_hook(struct step_hook *hook)
+{
+        write_lock(&step_hook_lock);
+        list_add(&hook->node, &step_hook);
+        write_unlock(&step_hook_lock);
+}
+
+void unregister_step_hook(struct step_hook *hook)
+{
+        write_lock(&step_hook_lock);
+        list_del(&hook->node);
+        write_unlock(&step_hook_lock);
+}
+
+/*
+ * Call registered single step handers
+ * There is no Syndrome info to check for determining the handler.
+ * So we call all the registered handlers, until the right handler is
+ * found which returns zero.
+ */
+static int call_step_hook(struct pt_regs *regs, unsigned int esr)
+{
+        struct step_hook *hook;
+        int retval = DBG_HOOK_ERROR;
+
+        read_lock(&step_hook_lock);
+
+        list_for_each_entry(hook, &step_hook, node)     {
+                retval = hook->fn(regs, esr);
+                if (retval == DBG_HOOK_HANDLED)
+                        break;
+        }
+
+        read_unlock(&step_hook_lock);
+
+        return retval;
+}
+
 static int single_step_handler(unsigned long addr, unsigned int esr,
                                struct pt_regs *regs)
 {
@@ -214,7 +256,9 @@ static int single_step_handler(unsigned long addr, unsigned int esr,
                  */
                 user_rewind_single_step(current);
         } else {
-                /* TODO: route to KGDB */
+                if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
+                        return 0;
+
                 pr_warning("Unexpected kernel single-step exception at EL1\n");
                 /*
                  * Re-enable stepping since we know that we will be
@@ -226,11 +270,53 @@ static int single_step_handler(unsigned long addr, unsigned int esr,
         return 0;
 }
 
+/*
+ * Breakpoint handler is re-entrant as another breakpoint can
+ * hit within breakpoint handler, especically in kprobes.
+ * Use reader/writer locks instead of plain spinlock.
+ */
+static LIST_HEAD(break_hook);
+DEFINE_RWLOCK(break_hook_lock);
+
+void register_break_hook(struct break_hook *hook)
+{
+        write_lock(&break_hook_lock);
+        list_add(&hook->node, &break_hook);
+        write_unlock(&break_hook_lock);
+}
+
+void unregister_break_hook(struct break_hook *hook)
+{
+        write_lock(&break_hook_lock);
+        list_del(&hook->node);
+        write_unlock(&break_hook_lock);
+}
+
+static int call_break_hook(struct pt_regs *regs, unsigned int esr)
+{
+        struct break_hook *hook;
+        int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL;
+
+        read_lock(&break_hook_lock);
+        list_for_each_entry(hook, &break_hook, node)
+                if ((esr & hook->esr_mask) == hook->esr_val)
+                        fn = hook->fn;
+        read_unlock(&break_hook_lock);
+
+        return fn ? fn(regs, esr) : DBG_HOOK_ERROR;
+}
+
 static int brk_handler(unsigned long addr, unsigned int esr,
                        struct pt_regs *regs)
 {
         siginfo_t info;
 
+        if (call_break_hook(regs, esr) == DBG_HOOK_HANDLED)
+                return 0;
+
+        pr_warn("unexpected brk exception at %lx, esr=0x%x\n",
+                        (long)instruction_pointer(regs), esr);
+
         if (!user_mode(regs))
                 return -EFAULT;
 
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 4d2c6f3f0c41..39ac630d83de 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -288,6 +288,8 @@ el1_dbg:
         /*
          * Debug exception handling
          */
+        cmp     x24, #ESR_EL1_EC_BRK64          // if BRK64
+        cinc    x24, x24, eq                    // set bit '0'
         tbz     x24, #0, el1_inv                // EL1 only
         mrs     x0, far_el1
         mov     x2, sp                          // struct pt_regs
@@ -314,7 +316,7 @@ el1_irq:
 
 #ifdef CONFIG_PREEMPT
         get_thread_info tsk
-        ldr     w24, [tsk, #TI_PREEMPT]         // restore preempt count
+        ldr     w24, [tsk, #TI_PREEMPT]         // get preempt count
         cbnz    w24, 1f                         // preempt count != 0
         ldr     x0, [tsk, #TI_FLAGS]            // get flags
         tbz     x0, #TIF_NEED_RESCHED, 1f       // needs rescheduling?
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index bb785d23dbde..4aef42a04bdc 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -17,6 +17,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/cpu_pm.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/sched.h>
@@ -113,6 +114,39 @@ EXPORT_SYMBOL(kernel_neon_end);
 
 #endif /* CONFIG_KERNEL_MODE_NEON */
 
+#ifdef CONFIG_CPU_PM
+static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
+                                  unsigned long cmd, void *v)
+{
+        switch (cmd) {
+        case CPU_PM_ENTER:
+                if (current->mm)
+                        fpsimd_save_state(&current->thread.fpsimd_state);
+                break;
+        case CPU_PM_EXIT:
+                if (current->mm)
+                        fpsimd_load_state(&current->thread.fpsimd_state);
+                break;
+        case CPU_PM_ENTER_FAILED:
+        default:
+                return NOTIFY_DONE;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block fpsimd_cpu_pm_notifier_block = {
+        .notifier_call = fpsimd_cpu_pm_notifier,
+};
+
+static void fpsimd_pm_init(void)
+{
+        cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
+}
+
+#else
+static inline void fpsimd_pm_init(void) { }
+#endif /* CONFIG_CPU_PM */
+
 /*
  * FP/SIMD support code initialisation.
  */
@@ -131,6 +165,8 @@ static int __init fpsimd_init(void)
         else
                 elf_hwcap |= HWCAP_ASIMD;
 
+        fpsimd_pm_init();
+
         return 0;
 }
 late_initcall(fpsimd_init);
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index c68cca5c3523..0b281fffda51 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -482,8 +482,6 @@ ENDPROC(__create_page_tables)
         .type   __switch_data, %object
 __switch_data:
         .quad   __mmap_switched
-        .quad   __data_loc                      // x4
-        .quad   _data                           // x5
         .quad   __bss_start                     // x6
         .quad   _end                            // x7
         .quad   processor_id                    // x4
@@ -498,15 +496,7 @@ __switch_data:
 __mmap_switched:
         adr     x3, __switch_data + 8
 
-        ldp     x4, x5, [x3], #16
         ldp     x6, x7, [x3], #16
-        cmp     x4, x5                          // Copy data segment if needed
-1:      ccmp    x5, x6, #4, ne
-        b.eq    2f
-        ldr     x16, [x4], #8
-        str     x16, [x5], #8
-        b       1b
-2:
 1:      cmp     x6, x7
         b.hs    2f
         str     xzr, [x6], #8                   // Clear BSS
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index ff516f6691e4..f17f581116fc 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -20,6 +20,7 @@
 
 #define pr_fmt(fmt) "hw-breakpoint: " fmt
 
+#include <linux/cpu_pm.h>
 #include <linux/errno.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/perf_event.h>
@@ -169,15 +170,68 @@ static enum debug_el debug_exception_level(int privilege)
         }
 }
 
-/*
- * Install a perf counter breakpoint.
+enum hw_breakpoint_ops {
+        HW_BREAKPOINT_INSTALL,
+        HW_BREAKPOINT_UNINSTALL,
+        HW_BREAKPOINT_RESTORE
+};
+
+/**
+ * hw_breakpoint_slot_setup - Find and setup a perf slot according to
+ *                            operations
+ *
+ * @slots: pointer to array of slots
+ * @max_slots: max number of slots
+ * @bp: perf_event to setup
+ * @ops: operation to be carried out on the slot
+ *
+ * Return:
+ *      slot index on success
+ *      -ENOSPC if no slot is available/matches
+ *      -EINVAL on wrong operations parameter
  */
-int arch_install_hw_breakpoint(struct perf_event *bp)
+static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
+                                    struct perf_event *bp,
+                                    enum hw_breakpoint_ops ops)
+{
+        int i;
+        struct perf_event **slot;
+
+        for (i = 0; i < max_slots; ++i) {
+                slot = &slots[i];
+                switch (ops) {
+                case HW_BREAKPOINT_INSTALL:
+                        if (!*slot) {
+                                *slot = bp;
+                                return i;
+                        }
+                        break;
+                case HW_BREAKPOINT_UNINSTALL:
+                        if (*slot == bp) {
+                                *slot = NULL;
+                                return i;
+                        }
+                        break;
+                case HW_BREAKPOINT_RESTORE:
+                        if (*slot == bp)
+                                return i;
+                        break;
+                default:
+                        pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
+                        return -EINVAL;
+                }
+        }
+        return -ENOSPC;
+}
+
+static int hw_breakpoint_control(struct perf_event *bp,
+                                 enum hw_breakpoint_ops ops)
 {
         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
-        struct perf_event **slot, **slots;
+        struct perf_event **slots;
         struct debug_info *debug_info = &current->thread.debug;
         int i, max_slots, ctrl_reg, val_reg, reg_enable;
+        enum debug_el dbg_el = debug_exception_level(info->ctrl.privilege);
         u32 ctrl;
 
         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
@@ -196,67 +250,54 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 reg_enable = !debug_info->wps_disabled;
         }
 
-        for (i = 0; i < max_slots; ++i) {
-                slot = &slots[i];
-
-                if (!*slot) {
-                        *slot = bp;
-                        break;
-                }
-        }
-
-        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
-                return -ENOSPC;
+        i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
 
-        /* Ensure debug monitors are enabled at the correct exception level.  */
-        enable_debug_monitors(debug_exception_level(info->ctrl.privilege));
+        if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
+                return i;
 
-        /* Setup the address register. */
-        write_wb_reg(val_reg, i, info->address);
+        switch (ops) {
+        case HW_BREAKPOINT_INSTALL:
+                /*
+                 * Ensure debug monitors are enabled at the correct exception
+                 * level.
+                 */
+                enable_debug_monitors(dbg_el);
+                /* Fall through */
+        case HW_BREAKPOINT_RESTORE:
+                /* Setup the address register. */
+                write_wb_reg(val_reg, i, info->address);
+
+                /* Setup the control register. */
+                ctrl = encode_ctrl_reg(info->ctrl);
+                write_wb_reg(ctrl_reg, i,
+                             reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
+                break;
+        case HW_BREAKPOINT_UNINSTALL:
+                /* Reset the control register. */
+                write_wb_reg(ctrl_reg, i, 0);
 
-        /* Setup the control register. */
-        ctrl = encode_ctrl_reg(info->ctrl);
-        write_wb_reg(ctrl_reg, i, reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
+                /*
+                 * Release the debug monitors for the correct exception
+                 * level.
+                 */
+                disable_debug_monitors(dbg_el);
+                break;
+        }
 
         return 0;
 }
 
-void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+/*
+ * Install a perf counter breakpoint.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
 {
-        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
-        struct perf_event **slot, **slots;
-        int i, max_slots, base;
-
-        if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
-                /* Breakpoint */
-                base = AARCH64_DBG_REG_BCR;
-                slots = this_cpu_ptr(bp_on_reg);
-                max_slots = core_num_brps;
-        } else {
-                /* Watchpoint */
-                base = AARCH64_DBG_REG_WCR;
-                slots = this_cpu_ptr(wp_on_reg);
-                max_slots = core_num_wrps;
-        }
-
-        /* Remove the breakpoint. */
-        for (i = 0; i < max_slots; ++i) {
-                slot = &slots[i];
-
-                if (*slot == bp) {
-                        *slot = NULL;
-                        break;
-                }
-        }
-
-        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
-                return;
-
-        /* Reset the control register. */
-        write_wb_reg(base, i, 0);
+        return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
+}
 
-        /* Release the debug monitors for the correct exception level.  */
-        disable_debug_monitors(debug_exception_level(info->ctrl.privilege));
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+        hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
 }
 
 static int get_hbp_len(u8 hbp_len)
@@ -806,18 +847,36 @@ void hw_breakpoint_thread_switch(struct task_struct *next)
 /*
  * CPU initialisation.
  */
-static void reset_ctrl_regs(void *unused)
+static void hw_breakpoint_reset(void *unused)
 {
         int i;
-
-        for (i = 0; i < core_num_brps; ++i) {
-                write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
-                write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
+        struct perf_event **slots;
+        /*
+         * When a CPU goes through cold-boot, it does not have any installed
+         * slot, so it is safe to share the same function for restoring and
+         * resetting breakpoints; when a CPU is hotplugged in, it goes
+         * through the slots, which are all empty, hence it just resets control
+         * and value for debug registers.
+         * When this function is triggered on warm-boot through a CPU PM
+         * notifier some slots might be initialized; if so they are
+         * reprogrammed according to the debug slots content.
+         */
+        for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
+                if (slots[i]) {
+                        hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
+                } else {
+                        write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
+                        write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
+                }
         }
 
-        for (i = 0; i < core_num_wrps; ++i) {
-                write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
-                write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
+        for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
+                if (slots[i]) {
+                        hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
+                } else {
+                        write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
+                        write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
+                }
         }
 }
 
@@ -827,7 +886,7 @@ static int hw_breakpoint_reset_notify(struct notifier_block *self,
 {
         int cpu = (long)hcpu;
         if (action == CPU_ONLINE)
-                smp_call_function_single(cpu, reset_ctrl_regs, NULL, 1);
+                smp_call_function_single(cpu, hw_breakpoint_reset, NULL, 1);
         return NOTIFY_OK;
 }
 
@@ -835,6 +894,14 @@ static struct notifier_block hw_breakpoint_reset_nb = {
         .notifier_call = hw_breakpoint_reset_notify,
 };
 
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+extern void cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *));
+#else
+static inline void cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *))
+{
+}
+#endif
+
 /*
  * One-time initialisation.
  */
@@ -850,8 +917,8 @@ static int __init arch_hw_breakpoint_init(void)
          * Reset the breakpoint resources. We assume that a halting
          * debugger will leave the world in a nice state for us.
          */
-        smp_call_function(reset_ctrl_regs, NULL, 1);
-        reset_ctrl_regs(NULL);
+        smp_call_function(hw_breakpoint_reset, NULL, 1);
+        hw_breakpoint_reset(NULL);
 
         /* Register debug fault handlers. */
         hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
@@ -861,6 +928,8 @@ static int __init arch_hw_breakpoint_init(void)
 
         /* Register hotplug notifier. */
         register_cpu_notifier(&hw_breakpoint_reset_nb);
+        /* Register cpu_suspend hw breakpoint restore hook */
+        cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
 
         return 0;
 }
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
new file mode 100644
index 000000000000..92f36835486b
--- /dev/null
+++ b/arch/arm64/kernel/insn.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2013 Huawei Ltd.
+ * Author: Jiang Liu <liuj97@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/stop_machine.h>
+#include <linux/uaccess.h>
+#include <asm/cacheflush.h>
+#include <asm/insn.h>
+
+static int aarch64_insn_encoding_class[] = {
+        AARCH64_INSN_CLS_UNKNOWN,
+        AARCH64_INSN_CLS_UNKNOWN,
+        AARCH64_INSN_CLS_UNKNOWN,
+        AARCH64_INSN_CLS_UNKNOWN,
+        AARCH64_INSN_CLS_LDST,
+        AARCH64_INSN_CLS_DP_REG,
+        AARCH64_INSN_CLS_LDST,
+        AARCH64_INSN_CLS_DP_FPSIMD,
+        AARCH64_INSN_CLS_DP_IMM,
+        AARCH64_INSN_CLS_DP_IMM,
+        AARCH64_INSN_CLS_BR_SYS,
+        AARCH64_INSN_CLS_BR_SYS,
+        AARCH64_INSN_CLS_LDST,
+        AARCH64_INSN_CLS_DP_REG,
+        AARCH64_INSN_CLS_LDST,
+        AARCH64_INSN_CLS_DP_FPSIMD,
+};
+
+enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
+{
+        return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
+}
+
+/* NOP is an alias of HINT */
+bool __kprobes aarch64_insn_is_nop(u32 insn)
+{
+        if (!aarch64_insn_is_hint(insn))
+                return false;
+
+        switch (insn & 0xFE0) {
+        case AARCH64_INSN_HINT_YIELD:
+        case AARCH64_INSN_HINT_WFE:
+        case AARCH64_INSN_HINT_WFI:
+        case AARCH64_INSN_HINT_SEV:
+        case AARCH64_INSN_HINT_SEVL:
+                return false;
+        default:
+                return true;
+        }
+}
+
+/*
+ * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
+ * little-endian.
+ */
+int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
+{
+        int ret;
+        u32 val;
+
+        ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
+        if (!ret)
+                *insnp = le32_to_cpu(val);
+
+        return ret;
+}
+
+int __kprobes aarch64_insn_write(void *addr, u32 insn)
+{
+        insn = cpu_to_le32(insn);
+        return probe_kernel_write(addr, &insn, AARCH64_INSN_SIZE);
+}
+
+static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
+{
+        if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
+                return false;
+
+        return  aarch64_insn_is_b(insn) ||
+                aarch64_insn_is_bl(insn) ||
+                aarch64_insn_is_svc(insn) ||
+                aarch64_insn_is_hvc(insn) ||
+                aarch64_insn_is_smc(insn) ||
+                aarch64_insn_is_brk(insn) ||
+                aarch64_insn_is_nop(insn);
+}
+
+/*
+ * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
+ * Section B2.6.5 "Concurrent modification and execution of instructions":
+ * Concurrent modification and execution of instructions can lead to the
+ * resulting instruction performing any behavior that can be achieved by
+ * executing any sequence of instructions that can be executed from the
+ * same Exception level, except where the instruction before modification
+ * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
+ * or SMC instruction.
+ */
+bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
+{
+        return __aarch64_insn_hotpatch_safe(old_insn) &&
+               __aarch64_insn_hotpatch_safe(new_insn);
+}
+
+int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
+{
+        u32 *tp = addr;
+        int ret;
+
+        /* A64 instructions must be word aligned */
+        if ((uintptr_t)tp & 0x3)
+                return -EINVAL;
+
+        ret = aarch64_insn_write(tp, insn);
+        if (ret == 0)
+                flush_icache_range((uintptr_t)tp,
+                                   (uintptr_t)tp + AARCH64_INSN_SIZE);
+
+        return ret;
+}
+
+struct aarch64_insn_patch {
+        void            **text_addrs;
+        u32             *new_insns;
+        int             insn_cnt;
+        atomic_t        cpu_count;
+};
+
+static int __kprobes aarch64_insn_patch_text_cb(void *arg)
+{
+        int i, ret = 0;
+        struct aarch64_insn_patch *pp = arg;
+
+        /* The first CPU becomes master */
+        if (atomic_inc_return(&pp->cpu_count) == 1) {
+                for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
+                        ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
+                                                             pp->new_insns[i]);
+                /*
+                 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
+                 * which ends with "dsb; isb" pair guaranteeing global
+                 * visibility.
+                 */
+                atomic_set(&pp->cpu_count, -1);
+        } else {
+                while (atomic_read(&pp->cpu_count) != -1)
+                        cpu_relax();
+                isb();
+        }
+
+        return ret;
+}
+
+int __kprobes aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt)
+{
+        struct aarch64_insn_patch patch = {
+                .text_addrs = addrs,
+                .new_insns = insns,
+                .insn_cnt = cnt,
+                .cpu_count = ATOMIC_INIT(0),
+        };
+
+        if (cnt <= 0)
+                return -EINVAL;
+
+        return stop_machine(aarch64_insn_patch_text_cb, &patch,
+                            cpu_online_mask);
+}
+
+int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
+{
+        int ret;
+        u32 insn;
+
+        /* Unsafe to patch multiple instructions without synchronizaiton */
+        if (cnt == 1) {
+                ret = aarch64_insn_read(addrs[0], &insn);
+                if (ret)
+                        return ret;
+
+                if (aarch64_insn_hotpatch_safe(insn, insns[0])) {
+                        /*
+                         * ARMv8 architecture doesn't guarantee all CPUs see
+                         * the new instruction after returning from function
+                         * aarch64_insn_patch_text_nosync(). So send IPIs to
+                         * all other CPUs to achieve instruction
+                         * synchronization.
+                         */
+                        ret = aarch64_insn_patch_text_nosync(addrs[0], insns[0]);
+                        kick_all_cpus_sync();
+                        return ret;
+                }
+        }
+
+        return aarch64_insn_patch_text_sync(addrs, insns, cnt);
+}
+
+u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
+                                  u32 insn, u64 imm)
+{
+        u32 immlo, immhi, lomask, himask, mask;
+        int shift;
+
+        switch (type) {
+        case AARCH64_INSN_IMM_ADR:
+                lomask = 0x3;
+                himask = 0x7ffff;
+                immlo = imm & lomask;
+                imm >>= 2;
+                immhi = imm & himask;
+                imm = (immlo << 24) | (immhi);
+                mask = (lomask << 24) | (himask);
+                shift = 5;
+                break;
+        case AARCH64_INSN_IMM_26:
+                mask = BIT(26) - 1;
+                shift = 0;
+                break;
+        case AARCH64_INSN_IMM_19:
+                mask = BIT(19) - 1;
+                shift = 5;
+                break;
+        case AARCH64_INSN_IMM_16:
+                mask = BIT(16) - 1;
+                shift = 5;
+                break;
+        case AARCH64_INSN_IMM_14:
+                mask = BIT(14) - 1;
+                shift = 5;
+                break;
+        case AARCH64_INSN_IMM_12:
+                mask = BIT(12) - 1;
+                shift = 10;
+                break;
+        case AARCH64_INSN_IMM_9:
+                mask = BIT(9) - 1;
+                shift = 12;
+                break;
+        default:
+                pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
+                        type);
+                return 0;
+        }
+
+        /* Update the immediate field. */
+        insn &= ~(mask << shift);
+        insn |= (imm & mask) << shift;
+
+        return insn;
+}
+
+u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
+                                          enum aarch64_insn_branch_type type)
+{
+        u32 insn;
+        long offset;
+
+        /*
+         * PC: A 64-bit Program Counter holding the address of the current
+         * instruction. A64 instructions must be word-aligned.
+         */
+        BUG_ON((pc & 0x3) || (addr & 0x3));
+
+        /*
+         * B/BL support [-128M, 128M) offset
+         * ARM64 virtual address arrangement guarantees all kernel and module
+         * texts are within +/-128M.
+         */
+        offset = ((long)addr - (long)pc);
+        BUG_ON(offset < -SZ_128M || offset >= SZ_128M);
+
+        if (type == AARCH64_INSN_BRANCH_LINK)
+                insn = aarch64_insn_get_bl_value();
+        else
+                insn = aarch64_insn_get_b_value();
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
+                                             offset >> 2);
+}
+
+u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
+{
+        return aarch64_insn_get_hint_value() | op;
+}
+
+u32 __kprobes aarch64_insn_gen_nop(void)
+{
+        return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
+}
diff --git a/arch/arm64/kernel/jump_label.c b/arch/arm64/kernel/jump_label.c
new file mode 100644
index 000000000000..263a166291fb
--- /dev/null
+++ b/arch/arm64/kernel/jump_label.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2013 Huawei Ltd.
+ * Author: Jiang Liu <liuj97@gmail.com>
+ *
+ * Based on arch/arm/kernel/jump_label.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/jump_label.h>
+#include <asm/insn.h>
+
+#ifdef HAVE_JUMP_LABEL
+
+static void __arch_jump_label_transform(struct jump_entry *entry,
+                                        enum jump_label_type type,
+                                        bool is_static)
+{
+        void *addr = (void *)entry->code;
+        u32 insn;
+
+        if (type == JUMP_LABEL_ENABLE) {
+                insn = aarch64_insn_gen_branch_imm(entry->code,
+                                                   entry->target,
+                                                   AARCH64_INSN_BRANCH_NOLINK);
+        } else {
+                insn = aarch64_insn_gen_nop();
+        }
+
+        if (is_static)
+                aarch64_insn_patch_text_nosync(addr, insn);
+        else
+                aarch64_insn_patch_text(&addr, &insn, 1);
+}
+
+void arch_jump_label_transform(struct jump_entry *entry,
+                               enum jump_label_type type)
+{
+        __arch_jump_label_transform(entry, type, false);
+}
+
+void arch_jump_label_transform_static(struct jump_entry *entry,
+                                      enum jump_label_type type)
+{
+        __arch_jump_label_transform(entry, type, true);
+}
+
+#endif  /* HAVE_JUMP_LABEL */
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e2ad0d87721f..1eb1cc955139 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -25,6 +25,10 @@
 #include <linux/mm.h>
 #include <linux/moduleloader.h>
 #include <linux/vmalloc.h>
+#include <asm/insn.h>
+
+#define AARCH64_INSN_IMM_MOVNZ          AARCH64_INSN_IMM_MAX
+#define AARCH64_INSN_IMM_MOVK           AARCH64_INSN_IMM_16
 
 void *module_alloc(unsigned long size)
 {
@@ -94,28 +98,18 @@ static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
         return 0;
 }
 
-enum aarch64_imm_type {
-        INSN_IMM_MOVNZ,
-        INSN_IMM_MOVK,
-        INSN_IMM_ADR,
-        INSN_IMM_26,
-        INSN_IMM_19,
-        INSN_IMM_16,
-        INSN_IMM_14,
-        INSN_IMM_12,
-        INSN_IMM_9,
-};
-
-static u32 encode_insn_immediate(enum aarch64_imm_type type, u32 insn, u64 imm)
+static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
+                           int lsb, enum aarch64_insn_imm_type imm_type)
 {
-        u32 immlo, immhi, lomask, himask, mask;
-        int shift;
+        u64 imm, limit = 0;
+        s64 sval;
+        u32 insn = le32_to_cpu(*(u32 *)place);
 
-        /* The instruction stream is always little endian. */
-        insn = le32_to_cpu(insn);
+        sval = do_reloc(op, place, val);
+        sval >>= lsb;
+        imm = sval & 0xffff;
 
-        switch (type) {
-        case INSN_IMM_MOVNZ:
+        if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
                 /*
                  * For signed MOVW relocations, we have to manipulate the
                  * instruction encoding depending on whether or not the
@@ -134,70 +128,12 @@ static u32 encode_insn_immediate(enum aarch64_imm_type type, u32 insn, u64 imm)
                          */
                         imm = ~imm;
                 }
-        case INSN_IMM_MOVK:
-                mask = BIT(16) - 1;
-                shift = 5;
-                break;
-        case INSN_IMM_ADR:
-                lomask = 0x3;
-                himask = 0x7ffff;
-                immlo = imm & lomask;
-                imm >>= 2;
-                immhi = imm & himask;
-                imm = (immlo << 24) | (immhi);
-                mask = (lomask << 24) | (himask);
-                shift = 5;
-                break;
-        case INSN_IMM_26:
-                mask = BIT(26) - 1;
-                shift = 0;
-                break;
-        case INSN_IMM_19:
-                mask = BIT(19) - 1;
-                shift = 5;
-                break;
-        case INSN_IMM_16:
-                mask = BIT(16) - 1;
-                shift = 5;
-                break;
-        case INSN_IMM_14:
-                mask = BIT(14) - 1;
-                shift = 5;
-                break;
-        case INSN_IMM_12:
-                mask = BIT(12) - 1;
-                shift = 10;
-                break;
-        case INSN_IMM_9:
-                mask = BIT(9) - 1;
-                shift = 12;
-                break;
-        default:
-                pr_err("encode_insn_immediate: unknown immediate encoding %d\n",
-                        type);
-                return 0;
+                imm_type = AARCH64_INSN_IMM_MOVK;
         }
 
-        /* Update the immediate field. */
-        insn &= ~(mask << shift);
-        insn |= (imm & mask) << shift;
-
-        return cpu_to_le32(insn);
-}
-
-static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
-                           int lsb, enum aarch64_imm_type imm_type)
-{
-        u64 imm, limit = 0;
-        s64 sval;
-        u32 insn = *(u32 *)place;
-
-        sval = do_reloc(op, place, val);
-        sval >>= lsb;
-        imm = sval & 0xffff;
-
         /* Update the instruction with the new encoding. */
-        *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
+        insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
+        *(u32 *)place = cpu_to_le32(insn);
 
         /* Shift out the immediate field. */
         sval >>= 16;
@@ -206,9 +142,9 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
          * For unsigned immediates, the overflow check is straightforward.
          * For signed immediates, the sign bit is actually the bit past the
          * most significant bit of the field.
-         * The INSN_IMM_16 immediate type is unsigned.
+         * The AARCH64_INSN_IMM_16 immediate type is unsigned.
          */
-        if (imm_type != INSN_IMM_16) {
+        if (imm_type != AARCH64_INSN_IMM_16) {
                 sval++;
                 limit++;
         }
@@ -221,11 +157,11 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
 }
 
 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
-                          int lsb, int len, enum aarch64_imm_type imm_type)
+                          int lsb, int len, enum aarch64_insn_imm_type imm_type)
 {
         u64 imm, imm_mask;
         s64 sval;
-        u32 insn = *(u32 *)place;
+        u32 insn = le32_to_cpu(*(u32 *)place);
 
         /* Calculate the relocation value. */
         sval = do_reloc(op, place, val);
@@ -236,7 +172,8 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
         imm = sval & imm_mask;
 
         /* Update the instruction's immediate field. */
-        *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
+        insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
+        *(u32 *)place = cpu_to_le32(insn);
 
         /*
          * Extract the upper value bits (including the sign bit) and
@@ -318,125 +255,125 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
                         overflow_check = false;
                 case R_AARCH64_MOVW_UABS_G0:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
-                                              INSN_IMM_16);
+                                              AARCH64_INSN_IMM_16);
                         break;
                 case R_AARCH64_MOVW_UABS_G1_NC:
                         overflow_check = false;
                 case R_AARCH64_MOVW_UABS_G1:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
-                                              INSN_IMM_16);
+                                              AARCH64_INSN_IMM_16);
                         break;
                 case R_AARCH64_MOVW_UABS_G2_NC:
                         overflow_check = false;
                 case R_AARCH64_MOVW_UABS_G2:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
-                                              INSN_IMM_16);
+                                              AARCH64_INSN_IMM_16);
                         break;
                 case R_AARCH64_MOVW_UABS_G3:
                         /* We're using the top bits so we can't overflow. */
                         overflow_check = false;
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
-                                              INSN_IMM_16);
+                                              AARCH64_INSN_IMM_16);
                         break;
                 case R_AARCH64_MOVW_SABS_G0:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_SABS_G1:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_SABS_G2:
                         ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_PREL_G0_NC:
                         overflow_check = false;
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
-                                              INSN_IMM_MOVK);
+                                              AARCH64_INSN_IMM_MOVK);
                         break;
                 case R_AARCH64_MOVW_PREL_G0:
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_PREL_G1_NC:
                         overflow_check = false;
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
-                                              INSN_IMM_MOVK);
+                                              AARCH64_INSN_IMM_MOVK);
                         break;
                 case R_AARCH64_MOVW_PREL_G1:
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_PREL_G2_NC:
                         overflow_check = false;
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
-                                              INSN_IMM_MOVK);
+                                              AARCH64_INSN_IMM_MOVK);
                         break;
                 case R_AARCH64_MOVW_PREL_G2:
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
                 case R_AARCH64_MOVW_PREL_G3:
                         /* We're using the top bits so we can't overflow. */
                         overflow_check = false;
                         ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
-                                              INSN_IMM_MOVNZ);
+                                              AARCH64_INSN_IMM_MOVNZ);
                         break;
 
                 /* Immediate instruction relocations. */
                 case R_AARCH64_LD_PREL_LO19:
                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
-                                             INSN_IMM_19);
+                                             AARCH64_INSN_IMM_19);
                         break;
                 case R_AARCH64_ADR_PREL_LO21:
                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
-                                             INSN_IMM_ADR);
+                                             AARCH64_INSN_IMM_ADR);
                         break;
                 case R_AARCH64_ADR_PREL_PG_HI21_NC:
                         overflow_check = false;
                 case R_AARCH64_ADR_PREL_PG_HI21:
                         ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
-                                             INSN_IMM_ADR);
+                                             AARCH64_INSN_IMM_ADR);
                         break;
                 case R_AARCH64_ADD_ABS_LO12_NC:
                 case R_AARCH64_LDST8_ABS_LO12_NC:
                         overflow_check = false;
                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
-                                             INSN_IMM_12);
+                                             AARCH64_INSN_IMM_12);
                         break;
                 case R_AARCH64_LDST16_ABS_LO12_NC:
                         overflow_check = false;
                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
-                                             INSN_IMM_12);
+                                             AARCH64_INSN_IMM_12);
                         break;
                 case R_AARCH64_LDST32_ABS_LO12_NC:
                         overflow_check = false;
                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
-                                             INSN_IMM_12);
+                                             AARCH64_INSN_IMM_12);
                         break;
                 case R_AARCH64_LDST64_ABS_LO12_NC:
                         overflow_check = false;
                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
-                                             INSN_IMM_12);
+                                             AARCH64_INSN_IMM_12);
                         break;
                 case R_AARCH64_LDST128_ABS_LO12_NC:
                         overflow_check = false;
                         ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
-                                             INSN_IMM_12);
+                                             AARCH64_INSN_IMM_12);
                         break;
                 case R_AARCH64_TSTBR14:
                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
-                                             INSN_IMM_14);
+                                             AARCH64_INSN_IMM_14);
                         break;
                 case R_AARCH64_CONDBR19:
                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
-                                             INSN_IMM_19);
+                                             AARCH64_INSN_IMM_19);
                         break;
                 case R_AARCH64_JUMP26:
                 case R_AARCH64_CALL26:
                         ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
-                                             INSN_IMM_26);
+                                             AARCH64_INSN_IMM_26);
                         break;
 
                 default:
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 0e63c98d224c..5b1cd792274a 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -22,6 +22,7 @@
 
 #include <linux/bitmap.h>
 #include <linux/interrupt.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/export.h>
 #include <linux/perf_event.h>
@@ -363,26 +364,53 @@ validate_group(struct perf_event *event)
 }
 
 static void
+armpmu_disable_percpu_irq(void *data)
+{
+        unsigned int irq = *(unsigned int *)data;
+        disable_percpu_irq(irq);
+}
+
+static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-        int i, irq, irqs;
+        int irq;
+        unsigned int i, irqs;
         struct platform_device *pmu_device = armpmu->plat_device;
 
         irqs = min(pmu_device->num_resources, num_possible_cpus());
+        if (!irqs)
+                return;
 
-        for (i = 0; i < irqs; ++i) {
-                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
-                        continue;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0)
-                        free_irq(irq, armpmu);
+        irq = platform_get_irq(pmu_device, 0);
+        if (irq <= 0)
+                return;
+
+        if (irq_is_percpu(irq)) {
+                on_each_cpu(armpmu_disable_percpu_irq, &irq, 1);
+                free_percpu_irq(irq, &cpu_hw_events);
+        } else {
+                for (i = 0; i < irqs; ++i) {
+                        if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
+                                continue;
+                        irq = platform_get_irq(pmu_device, i);
+                        if (irq > 0)
+                                free_irq(irq, armpmu);
+                }
         }
 }
 
+static void
+armpmu_enable_percpu_irq(void *data)
+{
+        unsigned int irq = *(unsigned int *)data;
+        enable_percpu_irq(irq, IRQ_TYPE_NONE);
+}
+
 static int
 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
-        int i, err, irq, irqs;
+        int err, irq;
+        unsigned int i, irqs;
         struct platform_device *pmu_device = armpmu->plat_device;
 
         if (!pmu_device) {
@@ -391,39 +419,59 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
         }
 
         irqs = min(pmu_device->num_resources, num_possible_cpus());
-        if (irqs < 1) {
+        if (!irqs) {
                 pr_err("no irqs for PMUs defined\n");
                 return -ENODEV;
         }
 
-        for (i = 0; i < irqs; ++i) {
-                err = 0;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq < 0)
-                        continue;
+        irq = platform_get_irq(pmu_device, 0);
+        if (irq <= 0) {
+                pr_err("failed to get valid irq for PMU device\n");
+                return -ENODEV;
+        }
 
-                /*
-                 * If we have a single PMU interrupt that we can't shift,
-                 * assume that we're running on a uniprocessor machine and
-                 * continue. Otherwise, continue without this interrupt.
-                 */
-                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                    irq, i);
-                        continue;
-                }
+        if (irq_is_percpu(irq)) {
+                err = request_percpu_irq(irq, armpmu->handle_irq,
+                                "arm-pmu", &cpu_hw_events);
 
-                err = request_irq(irq, armpmu->handle_irq,
-                                  IRQF_NOBALANCING,
-                                  "arm-pmu", armpmu);
                 if (err) {
-                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
-                                irq);
+                        pr_err("unable to request percpu IRQ%d for ARM PMU counters\n",
+                                        irq);
                         armpmu_release_hardware(armpmu);
                         return err;
                 }
 
-                cpumask_set_cpu(i, &armpmu->active_irqs);
+                on_each_cpu(armpmu_enable_percpu_irq, &irq, 1);
+        } else {
+                for (i = 0; i < irqs; ++i) {
+                        err = 0;
+                        irq = platform_get_irq(pmu_device, i);
+                        if (irq <= 0)
+                                continue;
+
+                        /*
+                         * If we have a single PMU interrupt that we can't shift,
+                         * assume that we're running on a uniprocessor machine and
+                         * continue. Otherwise, continue without this interrupt.
+                         */
+                        if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                                irq, i);
+                                continue;
+                        }
+
+                        err = request_irq(irq, armpmu->handle_irq,
+                                        IRQF_NOBALANCING,
+                                        "arm-pmu", armpmu);
+                        if (err) {
+                                pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                                                irq);
+                                armpmu_release_hardware(armpmu);
+                                return err;
+                        }
+
+                        cpumask_set_cpu(i, &armpmu->active_irqs);
+                }
         }
 
         return 0;
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index de17c89985db..1c0a9be2ffa8 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -33,6 +33,7 @@
 #include <linux/kallsyms.h>
 #include <linux/init.h>
 #include <linux/cpu.h>
+#include <linux/cpuidle.h>
 #include <linux/elfcore.h>
 #include <linux/pm.h>
 #include <linux/tick.h>
@@ -84,11 +85,6 @@ EXPORT_SYMBOL_GPL(pm_power_off);
 void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
-void arch_cpu_idle_prepare(void)
-{
-        local_fiq_enable();
-}
-
 /*
  * This is our default idle handler.
  */
@@ -98,8 +94,10 @@ void arch_cpu_idle(void)
          * This should do all the clock switching and wait for interrupt
          * tricks
          */
-        cpu_do_idle();
-        local_irq_enable();
+        if (cpuidle_idle_call()) {
+                cpu_do_idle();
+                local_irq_enable();
+        }
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -135,7 +133,6 @@ void machine_restart(char *cmd)
 
         /* Disable interrupts first */
         local_irq_disable();
-        local_fiq_disable();
 
         /* Now call the architecture specific reboot code. */
         if (arm_pm_restart)
@@ -308,6 +305,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
 unsigned long get_wchan(struct task_struct *p)
 {
         struct stackframe frame;
+        unsigned long stack_page;
         int count = 0;
         if (!p || p == current || p->state == TASK_RUNNING)
                 return 0;
@@ -315,9 +313,11 @@ unsigned long get_wchan(struct task_struct *p)
         frame.fp = thread_saved_fp(p);
         frame.sp = thread_saved_sp(p);
         frame.pc = thread_saved_pc(p);
+        stack_page = (unsigned long)task_stack_page(p);
         do {
-                int ret = unwind_frame(&frame);
-                if (ret < 0)
+                if (frame.sp < stack_page ||
+                    frame.sp >= stack_page + THREAD_SIZE ||
+                    unwind_frame(&frame))
                         return 0;
                 if (!in_sched_functions(frame.pc))
                         return frame.pc;
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index bd9bbd0e44ed..c8e9effe52e1 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -108,20 +108,95 @@ void __init early_print(const char *str, ...)
         printk("%s", buf);
 }
 
+void __init smp_setup_processor_id(void)
+{
+        /*
+         * clear __my_cpu_offset on boot CPU to avoid hang caused by
+         * using percpu variable early, for example, lockdep will
+         * access percpu variable inside lock_release
+         */
+        set_my_cpu_offset(0);
+}
+
 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 {
         return phys_id == cpu_logical_map(cpu);
 }
 
+struct mpidr_hash mpidr_hash;
+#ifdef CONFIG_SMP
+/**
+ * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
+ *                        level in order to build a linear index from an
+ *                        MPIDR value. Resulting algorithm is a collision
+ *                        free hash carried out through shifting and ORing
+ */
+static void __init smp_build_mpidr_hash(void)
+{
+        u32 i, affinity, fs[4], bits[4], ls;
+        u64 mask = 0;
+        /*
+         * Pre-scan the list of MPIDRS and filter out bits that do
+         * not contribute to affinity levels, ie they never toggle.
+         */
+        for_each_possible_cpu(i)
+                mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
+        pr_debug("mask of set bits %#llx\n", mask);
+        /*
+         * Find and stash the last and first bit set at all affinity levels to
+         * check how many bits are required to represent them.
+         */
+        for (i = 0; i < 4; i++) {
+                affinity = MPIDR_AFFINITY_LEVEL(mask, i);
+                /*
+                 * Find the MSB bit and LSB bits position
+                 * to determine how many bits are required
+                 * to express the affinity level.
+                 */
+                ls = fls(affinity);
+                fs[i] = affinity ? ffs(affinity) - 1 : 0;
+                bits[i] = ls - fs[i];
+        }
+        /*
+         * An index can be created from the MPIDR_EL1 by isolating the
+         * significant bits at each affinity level and by shifting
+         * them in order to compress the 32 bits values space to a
+         * compressed set of values. This is equivalent to hashing
+         * the MPIDR_EL1 through shifting and ORing. It is a collision free
+         * hash though not minimal since some levels might contain a number
+         * of CPUs that is not an exact power of 2 and their bit
+         * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
+         */
+        mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
+        mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
+        mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
+                                                (bits[1] + bits[0]);
+        mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
+                                  fs[3] - (bits[2] + bits[1] + bits[0]);
+        mpidr_hash.mask = mask;
+        mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
+        pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
+                mpidr_hash.shift_aff[0],
+                mpidr_hash.shift_aff[1],
+                mpidr_hash.shift_aff[2],
+                mpidr_hash.shift_aff[3],
+                mpidr_hash.mask,
+                mpidr_hash.bits);
+        /*
+         * 4x is an arbitrary value used to warn on a hash table much bigger
+         * than expected on most systems.
+         */
+        if (mpidr_hash_size() > 4 * num_possible_cpus())
+                pr_warn("Large number of MPIDR hash buckets detected\n");
+        __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
+}
+#endif
+
 static void __init setup_processor(void)
 {
         struct cpu_info *cpu_info;
+        u64 features, block;
 
-        /*
-         * locate processor in the list of supported processor
-         * types.  The linker builds this table for us from the
-         * entries in arch/arm/mm/proc.S
-         */
         cpu_info = lookup_processor_type(read_cpuid_id());
         if (!cpu_info) {
                 printk("CPU configuration botched (ID %08x), unable to continue.\n",
@@ -136,6 +211,37 @@ static void __init setup_processor(void)
 
         sprintf(init_utsname()->machine, ELF_PLATFORM);
         elf_hwcap = 0;
+
+        /*
+         * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
+         * The blocks we test below represent incremental functionality
+         * for non-negative values. Negative values are reserved.
+         */
+        features = read_cpuid(ID_AA64ISAR0_EL1);
+        block = (features >> 4) & 0xf;
+        if (!(block & 0x8)) {
+                switch (block) {
+                default:
+                case 2:
+                        elf_hwcap |= HWCAP_PMULL;
+                case 1:
+                        elf_hwcap |= HWCAP_AES;
+                case 0:
+                        break;
+                }
+        }
+
+        block = (features >> 8) & 0xf;
+        if (block && !(block & 0x8))
+                elf_hwcap |= HWCAP_SHA1;
+
+        block = (features >> 12) & 0xf;
+        if (block && !(block & 0x8))
+                elf_hwcap |= HWCAP_SHA2;
+
+        block = (features >> 16) & 0xf;
+        if (block && !(block & 0x8))
+                elf_hwcap |= HWCAP_CRC32;
 }
 
 static void __init setup_machine_fdt(phys_addr_t dt_phys)
@@ -236,6 +342,7 @@ void __init setup_arch(char **cmdline_p)
         cpu_read_bootcpu_ops();
 #ifdef CONFIG_SMP
         smp_init_cpus();
+        smp_build_mpidr_hash();
 #endif
 
 #ifdef CONFIG_VT
@@ -275,6 +382,11 @@ static const char *hwcap_str[] = {
         "fp",
         "asimd",
         "evtstrm",
+        "aes",
+        "pmull",
+        "sha1",
+        "sha2",
+        "crc32",
         NULL
 };
 
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
new file mode 100644
index 000000000000..b1925729c692
--- /dev/null
+++ b/arch/arm64/kernel/sleep.S
@@ -0,0 +1,184 @@
+#include <linux/errno.h>
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/assembler.h>
+
+        .text
+/*
+ * Implementation of MPIDR_EL1 hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @rs3: register containing affinity level 3 bit shift
+ * @mpidr: register containing MPIDR_EL1 value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
+ *      u32 aff0, aff1, aff2, aff3;
+ *      u64 mpidr_masked = mpidr & mask;
+ *      aff0 = mpidr_masked & 0xff;
+ *      aff1 = mpidr_masked & 0xff00;
+ *      aff2 = mpidr_masked & 0xff0000;
+ *      aff2 = mpidr_masked & 0xff00000000;
+ *      dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
+ *}
+ * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
+ */
+        .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
+        and     \mpidr, \mpidr, \mask           // mask out MPIDR bits
+        and     \dst, \mpidr, #0xff             // mask=aff0
+        lsr     \dst ,\dst, \rs0                // dst=aff0>>rs0
+        and     \mask, \mpidr, #0xff00          // mask = aff1
+        lsr     \mask ,\mask, \rs1
+        orr     \dst, \dst, \mask               // dst|=(aff1>>rs1)
+        and     \mask, \mpidr, #0xff0000        // mask = aff2
+        lsr     \mask ,\mask, \rs2
+        orr     \dst, \dst, \mask               // dst|=(aff2>>rs2)
+        and     \mask, \mpidr, #0xff00000000    // mask = aff3
+        lsr     \mask ,\mask, \rs3
+        orr     \dst, \dst, \mask               // dst|=(aff3>>rs3)
+        .endm
+/*
+ * Save CPU state for a suspend.  This saves callee registers, and allocates
+ * space on the kernel stack to save the CPU specific registers + some
+ * other data for resume.
+ *
+ *  x0 = suspend finisher argument
+ */
+ENTRY(__cpu_suspend)
+        stp     x29, lr, [sp, #-96]!
+        stp     x19, x20, [sp,#16]
+        stp     x21, x22, [sp,#32]
+        stp     x23, x24, [sp,#48]
+        stp     x25, x26, [sp,#64]
+        stp     x27, x28, [sp,#80]
+        mov     x2, sp
+        sub     sp, sp, #CPU_SUSPEND_SZ // allocate cpu_suspend_ctx
+        mov     x1, sp
+        /*
+         * x1 now points to struct cpu_suspend_ctx allocated on the stack
+         */
+        str     x2, [x1, #CPU_CTX_SP]
+        ldr     x2, =sleep_save_sp
+        ldr     x2, [x2, #SLEEP_SAVE_SP_VIRT]
+#ifdef CONFIG_SMP
+        mrs     x7, mpidr_el1
+        ldr     x9, =mpidr_hash
+        ldr     x10, [x9, #MPIDR_HASH_MASK]
+        /*
+         * Following code relies on the struct mpidr_hash
+         * members size.
+         */
+        ldp     w3, w4, [x9, #MPIDR_HASH_SHIFTS]
+        ldp     w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
+        compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
+        add     x2, x2, x8, lsl #3
+#endif
+        bl      __cpu_suspend_finisher
+        /*
+         * Never gets here, unless suspend fails.
+         * Successful cpu_suspend should return from cpu_resume, returning
+         * through this code path is considered an error
+         * If the return value is set to 0 force x0 = -EOPNOTSUPP
+         * to make sure a proper error condition is propagated
+         */
+        cmp     x0, #0
+        mov     x3, #-EOPNOTSUPP
+        csel    x0, x3, x0, eq
+        add     sp, sp, #CPU_SUSPEND_SZ // rewind stack pointer
+        ldp     x19, x20, [sp, #16]
+        ldp     x21, x22, [sp, #32]
+        ldp     x23, x24, [sp, #48]
+        ldp     x25, x26, [sp, #64]
+        ldp     x27, x28, [sp, #80]
+        ldp     x29, lr, [sp], #96
+        ret
+ENDPROC(__cpu_suspend)
+        .ltorg
+
+/*
+ * x0 must contain the sctlr value retrieved from restored context
+ */
+ENTRY(cpu_resume_mmu)
+        ldr     x3, =cpu_resume_after_mmu
+        msr     sctlr_el1, x0           // restore sctlr_el1
+        isb
+        br      x3                      // global jump to virtual address
+ENDPROC(cpu_resume_mmu)
+cpu_resume_after_mmu:
+        mov     x0, #0                  // return zero on success
+        ldp     x19, x20, [sp, #16]
+        ldp     x21, x22, [sp, #32]
+        ldp     x23, x24, [sp, #48]
+        ldp     x25, x26, [sp, #64]
+        ldp     x27, x28, [sp, #80]
+        ldp     x29, lr, [sp], #96
+        ret
+ENDPROC(cpu_resume_after_mmu)
+
+        .data
+ENTRY(cpu_resume)
+        bl      el2_setup               // if in EL2 drop to EL1 cleanly
+#ifdef CONFIG_SMP
+        mrs     x1, mpidr_el1
+        adr     x4, mpidr_hash_ptr
+        ldr     x5, [x4]
+        add     x8, x4, x5              // x8 = struct mpidr_hash phys address
+        /* retrieve mpidr_hash members to compute the hash */
+        ldr     x2, [x8, #MPIDR_HASH_MASK]
+        ldp     w3, w4, [x8, #MPIDR_HASH_SHIFTS]
+        ldp     w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)]
+        compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
+        /* x7 contains hash index, let's use it to grab context pointer */
+#else
+        mov     x7, xzr
+#endif
+        adr     x0, sleep_save_sp
+        ldr     x0, [x0, #SLEEP_SAVE_SP_PHYS]
+        ldr     x0, [x0, x7, lsl #3]
+        /* load sp from context */
+        ldr     x2, [x0, #CPU_CTX_SP]
+        adr     x1, sleep_idmap_phys
+        /* load physical address of identity map page table in x1 */
+        ldr     x1, [x1]
+        mov     sp, x2
+        /*
+         * cpu_do_resume expects x0 to contain context physical address
+         * pointer and x1 to contain physical address of 1:1 page tables
+         */
+        bl      cpu_do_resume           // PC relative jump, MMU off
+        b       cpu_resume_mmu          // Resume MMU, never returns
+ENDPROC(cpu_resume)
+
+        .align 3
+mpidr_hash_ptr:
+        /*
+         * offset of mpidr_hash symbol from current location
+         * used to obtain run-time mpidr_hash address with MMU off
+         */
+        .quad   mpidr_hash - .
+/*
+ * physical address of identity mapped page tables
+ */
+        .type   sleep_idmap_phys, #object
+ENTRY(sleep_idmap_phys)
+        .quad   0
+/*
+ * struct sleep_save_sp {
+ *      phys_addr_t *save_ptr_stash;
+ *      phys_addr_t save_ptr_stash_phys;
+ * };
+ */
+        .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+        .space  SLEEP_SAVE_SP_SZ        // struct sleep_save_sp
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index a0c2ca602cf8..7cfb92a4ab66 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -61,6 +61,7 @@ enum ipi_msg_type {
         IPI_CALL_FUNC,
         IPI_CALL_FUNC_SINGLE,
         IPI_CPU_STOP,
+        IPI_TIMER,
 };
 
 /*
@@ -122,8 +123,6 @@ asmlinkage void secondary_start_kernel(void)
         struct mm_struct *mm = &init_mm;
         unsigned int cpu = smp_processor_id();
 
-        printk("CPU%u: Booted secondary processor\n", cpu);
-
         /*
          * All kernel threads share the same mm context; grab a
          * reference and switch to it.
@@ -132,6 +131,9 @@ asmlinkage void secondary_start_kernel(void)
         current->active_mm = mm;
         cpumask_set_cpu(cpu, mm_cpumask(mm));
 
+        set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
+        printk("CPU%u: Booted secondary processor\n", cpu);
+
         /*
          * TTBR0 is only used for the identity mapping at this stage. Make it
          * point to zero page to avoid speculatively fetching new entries.
@@ -159,7 +161,6 @@ asmlinkage void secondary_start_kernel(void)
         complete(&cpu_running);
 
         local_irq_enable();
-        local_fiq_enable();
         local_async_enable();
 
         /*
@@ -271,6 +272,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
 
 void __init smp_prepare_boot_cpu(void)
 {
+        set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
 }
 
 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
@@ -447,6 +449,7 @@ static const char *ipi_types[NR_IPI] = {
         S(IPI_CALL_FUNC, "Function call interrupts"),
         S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
         S(IPI_CPU_STOP, "CPU stop interrupts"),
+        S(IPI_TIMER, "Timer broadcast interrupts"),
 };
 
 void show_ipi_list(struct seq_file *p, int prec)
@@ -491,7 +494,6 @@ static void ipi_cpu_stop(unsigned int cpu)
 
         set_cpu_online(cpu, false);
 
-        local_fiq_disable();
         local_irq_disable();
 
         while (1)
@@ -532,6 +534,14 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
                 irq_exit();
                 break;
 
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+        case IPI_TIMER:
+                irq_enter();
+                tick_receive_broadcast();
+                irq_exit();
+                break;
+#endif
+
         default:
                 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
                 break;
@@ -544,6 +554,13 @@ void smp_send_reschedule(int cpu)
         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+void tick_broadcast(const struct cpumask *mask)
+{
+        smp_cross_call(mask, IPI_TIMER);
+}
+#endif
+
 void smp_send_stop(void)
 {
         unsigned long timeout;
diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
index d25459ff57fc..c3b6c63ea5fb 100644
--- a/arch/arm64/kernel/stacktrace.c
+++ b/arch/arm64/kernel/stacktrace.c
@@ -43,7 +43,7 @@ int unwind_frame(struct stackframe *frame)
         low  = frame->sp;
         high = ALIGN(low, THREAD_SIZE);
 
-        if (fp < low || fp > high || fp & 0xf)
+        if (fp < low || fp > high - 0x18 || fp & 0xf)
                 return -EINVAL;
 
         frame->sp = fp + 0x10;
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
new file mode 100644
index 000000000000..1fa9ce4afd8f
--- /dev/null
+++ b/arch/arm64/kernel/suspend.c
@@ -0,0 +1,140 @@
+#include <linux/percpu.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/cpu_ops.h>
+#include <asm/debug-monitors.h>
+#include <asm/pgtable.h>
+#include <asm/memory.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+#include <asm/tlbflush.h>
+
+extern int __cpu_suspend(unsigned long);
+/*
+ * This is called by __cpu_suspend() to save the state, and do whatever
+ * flushing is required to ensure that when the CPU goes to sleep we have
+ * the necessary data available when the caches are not searched.
+ *
+ * @arg: Argument to pass to suspend operations
+ * @ptr: CPU context virtual address
+ * @save_ptr: address of the location where the context physical address
+ *            must be saved
+ */
+int __cpu_suspend_finisher(unsigned long arg, struct cpu_suspend_ctx *ptr,
+                           phys_addr_t *save_ptr)
+{
+        int cpu = smp_processor_id();
+
+        *save_ptr = virt_to_phys(ptr);
+
+        cpu_do_suspend(ptr);
+        /*
+         * Only flush the context that must be retrieved with the MMU
+         * off. VA primitives ensure the flush is applied to all
+         * cache levels so context is pushed to DRAM.
+         */
+        __flush_dcache_area(ptr, sizeof(*ptr));
+        __flush_dcache_area(save_ptr, sizeof(*save_ptr));
+
+        return cpu_ops[cpu]->cpu_suspend(arg);
+}
+
+/*
+ * This hook is provided so that cpu_suspend code can restore HW
+ * breakpoints as early as possible in the resume path, before reenabling
+ * debug exceptions. Code cannot be run from a CPU PM notifier since by the
+ * time the notifier runs debug exceptions might have been enabled already,
+ * with HW breakpoints registers content still in an unknown state.
+ */
+void (*hw_breakpoint_restore)(void *);
+void __init cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *))
+{
+        /* Prevent multiple restore hook initializations */
+        if (WARN_ON(hw_breakpoint_restore))
+                return;
+        hw_breakpoint_restore = hw_bp_restore;
+}
+
+/**
+ * cpu_suspend
+ *
+ * @arg: argument to pass to the finisher function
+ */
+int cpu_suspend(unsigned long arg)
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret, cpu = smp_processor_id();
+        unsigned long flags;
+
+        /*
+         * If cpu_ops have not been registered or suspend
+         * has not been initialized, cpu_suspend call fails early.
+         */
+        if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_suspend)
+                return -EOPNOTSUPP;
+
+        /*
+         * From this point debug exceptions are disabled to prevent
+         * updates to mdscr register (saved and restored along with
+         * general purpose registers) from kernel debuggers.
+         */
+        local_dbg_save(flags);
+
+        /*
+         * mm context saved on the stack, it will be restored when
+         * the cpu comes out of reset through the identity mapped
+         * page tables, so that the thread address space is properly
+         * set-up on function return.
+         */
+        ret = __cpu_suspend(arg);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                flush_tlb_all();
+
+                /*
+                 * Restore per-cpu offset before any kernel
+                 * subsystem relying on it has a chance to run.
+                 */
+                set_my_cpu_offset(per_cpu_offset(cpu));
+
+                /*
+                 * Restore HW breakpoint registers to sane values
+                 * before debug exceptions are possibly reenabled
+                 * through local_dbg_restore.
+                 */
+                if (hw_breakpoint_restore)
+                        hw_breakpoint_restore(NULL);
+        }
+
+        /*
+         * Restore pstate flags. OS lock and mdscr have been already
+         * restored, so from this point onwards, debugging is fully
+         * renabled if it was enabled when core started shutdown.
+         */
+        local_dbg_restore(flags);
+
+        return ret;
+}
+
+extern struct sleep_save_sp sleep_save_sp;
+extern phys_addr_t sleep_idmap_phys;
+
+static int cpu_suspend_init(void)
+{
+        void *ctx_ptr;
+
+        /* ctx_ptr is an array of physical addresses */
+        ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(phys_addr_t), GFP_KERNEL);
+
+        if (WARN_ON(!ctx_ptr))
+                return -ENOMEM;
+
+        sleep_save_sp.save_ptr_stash = ctx_ptr;
+        sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+        sleep_idmap_phys = virt_to_phys(idmap_pg_dir);
+        __flush_dcache_area(&sleep_save_sp, sizeof(struct sleep_save_sp));
+        __flush_dcache_area(&sleep_idmap_phys, sizeof(sleep_idmap_phys));
+
+        return 0;
+}
+early_initcall(cpu_suspend_init);
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 5161ad992091..4ba7a55b49c7 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -99,17 +99,14 @@ SECTIONS
 
         . = ALIGN(PAGE_SIZE);
         _data = .;
-        __data_loc = _data - LOAD_OFFSET;
         _sdata = .;
         RW_DATA_SECTION(64, PAGE_SIZE, THREAD_SIZE)
         _edata = .;
-        _edata_loc = __data_loc + SIZEOF(.data);
 
         BSS_SECTION(0, 0, 0)
         _end = .;
 
         STABS_DEBUG
-        .comment 0 : { *(.comment) }
 }
 
 /*
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index 4480ab339a00..8ba85e9ea388 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -36,6 +36,17 @@ config KVM_ARM_HOST
         ---help---
           Provides host support for ARM processors.
 
+config KVM_ARM_MAX_VCPUS
+        int "Number maximum supported virtual CPUs per VM"
+        depends on KVM_ARM_HOST
+        default 4
+        help
+          Static number of max supported virtual CPUs per VM.
+
+          If you choose a high number, the vcpu structures will be quite
+          large, so only choose a reasonable number that you expect to
+          actually use.
+
 config KVM_ARM_VGIC
         bool
         depends on KVM_ARM_HOST && OF
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index 3f0731e53274..08745578d54d 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -207,20 +207,26 @@ int __attribute_const__ kvm_target_cpu(void)
         unsigned long implementor = read_cpuid_implementor();
         unsigned long part_number = read_cpuid_part_number();
 
-        if (implementor != ARM_CPU_IMP_ARM)
-                return -EINVAL;
+        switch (implementor) {
+        case ARM_CPU_IMP_ARM:
+                switch (part_number) {
+                case ARM_CPU_PART_AEM_V8:
+                        return KVM_ARM_TARGET_AEM_V8;
+                case ARM_CPU_PART_FOUNDATION:
+                        return KVM_ARM_TARGET_FOUNDATION_V8;
+                case ARM_CPU_PART_CORTEX_A57:
+                        return KVM_ARM_TARGET_CORTEX_A57;
+                };
+                break;
+        case ARM_CPU_IMP_APM:
+                switch (part_number) {
+                case APM_CPU_PART_POTENZA:
+                        return KVM_ARM_TARGET_XGENE_POTENZA;
+                };
+                break;
+        };
 
-        switch (part_number) {
-        case ARM_CPU_PART_AEM_V8:
-                return KVM_ARM_TARGET_AEM_V8;
-        case ARM_CPU_PART_FOUNDATION:
-                return KVM_ARM_TARGET_FOUNDATION_V8;
-        case ARM_CPU_PART_CORTEX_A57:
-                /* Currently handled by the generic backend */
-                return KVM_ARM_TARGET_CORTEX_A57;
-        default:
-                return -EINVAL;
-        }
+        return -EINVAL;
 }
 
 int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 8da56067c304..7bc41eab4c64 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -39,9 +39,6 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        if (kvm_psci_call(vcpu))
-                return 1;
-
         kvm_inject_undefined(vcpu);
         return 1;
 }
@@ -90,7 +87,7 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
 
         if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
             !arm_exit_handlers[hsr_ec]) {
-                kvm_err("Unkown exception class: hsr: %#08x\n",
+                kvm_err("Unknown exception class: hsr: %#08x\n",
                         (unsigned int)kvm_vcpu_get_hsr(vcpu));
                 BUG();
         }
diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c
index 4268ab9356b1..8fe6f76b0edc 100644
--- a/arch/arm64/kvm/sys_regs_generic_v8.c
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -90,6 +90,9 @@ static int __init sys_reg_genericv8_init(void)
                                           &genericv8_target_table);
         kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A57,
                                           &genericv8_target_table);
+        kvm_register_target_sys_reg_table(KVM_ARM_TARGET_XGENE_POTENZA,
+                                          &genericv8_target_table);
+
         return 0;
 }
 late_initcall(sys_reg_genericv8_init);
diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile
index 59acc0ef0462..328ce1a99daa 100644
--- a/arch/arm64/lib/Makefile
+++ b/arch/arm64/lib/Makefile
@@ -1,6 +1,4 @@
-lib-y           := bitops.o delay.o                                     \
-                   strncpy_from_user.o strnlen_user.o clear_user.o      \
-                   copy_from_user.o copy_to_user.o copy_in_user.o       \
-                   copy_page.o clear_page.o                             \
-                   memchr.o memcpy.o memmove.o memset.o                 \
+lib-y           := bitops.o clear_user.o delay.o copy_from_user.o       \
+                   copy_to_user.o copy_in_user.o copy_page.o            \
+                   clear_page.o memchr.o memcpy.o memmove.o memset.o    \
                    strchr.o strrchr.o
diff --git a/arch/arm64/lib/strncpy_from_user.S b/arch/arm64/lib/strncpy_from_user.S
deleted file mode 100644
index 56e448a831a0..000000000000
--- a/arch/arm64/lib/strncpy_from_user.S
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Based on arch/arm/lib/strncpy_from_user.S
- *
- * Copyright (C) 1995-2000 Russell King
- * Copyright (C) 2012 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/*
- * Copy a string from user space to kernel space.
- *  x0 = dst, x1 = src, x2 = byte length
- * returns the number of characters copied (strlen of copied string),
- *  -EFAULT on exception, or "len" if we fill the whole buffer
- */
-ENTRY(__strncpy_from_user)
-        mov     x4, x1
-1:      subs    x2, x2, #1
-        bmi     2f
-USER(9f, ldrb   w3, [x1], #1    )
-        strb    w3, [x0], #1
-        cbnz    w3, 1b
-        sub     x1, x1, #1      // take NUL character out of count
-2:      sub     x0, x1, x4
-        ret
-ENDPROC(__strncpy_from_user)
-
-        .section .fixup,"ax"
-        .align  0
-9:      strb    wzr, [x0]       // null terminate
-        mov     x0, #-EFAULT
-        ret
-        .previous
diff --git a/arch/arm64/lib/strnlen_user.S b/arch/arm64/lib/strnlen_user.S
deleted file mode 100644
index 7f7b176a5646..000000000000
--- a/arch/arm64/lib/strnlen_user.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Based on arch/arm/lib/strnlen_user.S
- *
- * Copyright (C) 1995-2000 Russell King
- * Copyright (C) 2012 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/* Prototype: unsigned long __strnlen_user(const char *str, long n)
- * Purpose  : get length of a string in user memory
- * Params   : str - address of string in user memory
- * Returns  : length of string *including terminator*
- *            or zero on exception, or n if too long
- */
-ENTRY(__strnlen_user)
-        mov     x2, x0
-1:      subs    x1, x1, #1
-        b.mi    2f
-USER(9f, ldrb   w3, [x0], #1    )
-        cbnz    w3, 1b
-2:      sub     x0, x0, x2
-        ret
-ENDPROC(__strnlen_user)
-
-        .section .fixup,"ax"
-        .align  0
-9:      mov     x0, #0
-        ret
-        .previous
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 48a386094fa3..1ea9f26d1b70 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -146,7 +146,7 @@ ENDPROC(flush_icache_range)
 ENDPROC(__flush_cache_user_range)
 
 /*
- *      __flush_kern_dcache_page(kaddr)
+ *      __flush_dcache_area(kaddr, size)
  *
  *      Ensure that the data held in the page kaddr is written back to the
  *      page in question.
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 4bd7579ec9e6..45b5ab54c9ee 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -21,6 +21,7 @@
 #include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
+#include <linux/dma-contiguous.h>
 #include <linux/vmalloc.h>
 #include <linux/swiotlb.h>
 
@@ -33,17 +34,47 @@ static void *arm64_swiotlb_alloc_coherent(struct device *dev, size_t size,
                                           dma_addr_t *dma_handle, gfp_t flags,
                                           struct dma_attrs *attrs)
 {
+        if (dev == NULL) {
+                WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
+                return NULL;
+        }
+
         if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
             dev->coherent_dma_mask <= DMA_BIT_MASK(32))
                 flags |= GFP_DMA32;
-        return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
+        if (IS_ENABLED(CONFIG_DMA_CMA)) {
+                struct page *page;
+
+                page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
+                                                        get_order(size));
+                if (!page)
+                        return NULL;
+
+                *dma_handle = phys_to_dma(dev, page_to_phys(page));
+                return page_address(page);
+        } else {
+                return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
+        }
 }
 
 static void arm64_swiotlb_free_coherent(struct device *dev, size_t size,
                                         void *vaddr, dma_addr_t dma_handle,
                                         struct dma_attrs *attrs)
 {
-        swiotlb_free_coherent(dev, size, vaddr, dma_handle);
+        if (dev == NULL) {
+                WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
+                return;
+        }
+
+        if (IS_ENABLED(CONFIG_DMA_CMA)) {
+                phys_addr_t paddr = dma_to_phys(dev, dma_handle);
+
+                dma_release_from_contiguous(dev,
+                                        phys_to_page(paddr),
+                                        size >> PAGE_SHIFT);
+        } else {
+                swiotlb_free_coherent(dev, size, vaddr, dma_handle);
+        }
 }
 
 static struct dma_map_ops arm64_swiotlb_dma_ops = {
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 0cb8742de4f2..d0b4c2efda90 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -30,6 +30,7 @@
 #include <linux/memblock.h>
 #include <linux/sort.h>
 #include <linux/of_fdt.h>
+#include <linux/dma-contiguous.h>
 
 #include <asm/sections.h>
 #include <asm/setup.h>
@@ -159,6 +160,8 @@ void __init arm64_memblock_init(void)
                 memblock_reserve(base, size);
         }
 
+        dma_contiguous_reserve(0);
+
         memblock_allow_resize();
         memblock_dump_all();
 }
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
index 8957b822010b..005d29e2977d 100644
--- a/arch/arm64/mm/proc-macros.S
+++ b/arch/arm64/mm/proc-macros.S
@@ -38,8 +38,7 @@
  */
         .macro  dcache_line_size, reg, tmp
         mrs     \tmp, ctr_el0                   // read CTR
-        lsr     \tmp, \tmp, #16
-        and     \tmp, \tmp, #0xf                // cache line size encoding
+        ubfm    \tmp, \tmp, #16, #19            // cache line size encoding
         mov     \reg, #4                        // bytes per word
         lsl     \reg, \reg, \tmp                // actual cache line size
         .endm
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 0f7fec52c7f8..1333e6f9a8e5 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -80,8 +80,77 @@ ENTRY(cpu_do_idle)
         ret
 ENDPROC(cpu_do_idle)
 
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+/**
+ * cpu_do_suspend - save CPU registers context
+ *
+ * x0: virtual address of context pointer
+ */
+ENTRY(cpu_do_suspend)
+        mrs     x2, tpidr_el0
+        mrs     x3, tpidrro_el0
+        mrs     x4, contextidr_el1
+        mrs     x5, mair_el1
+        mrs     x6, cpacr_el1
+        mrs     x7, ttbr1_el1
+        mrs     x8, tcr_el1
+        mrs     x9, vbar_el1
+        mrs     x10, mdscr_el1
+        mrs     x11, oslsr_el1
+        mrs     x12, sctlr_el1
+        stp     x2, x3, [x0]
+        stp     x4, x5, [x0, #16]
+        stp     x6, x7, [x0, #32]
+        stp     x8, x9, [x0, #48]
+        stp     x10, x11, [x0, #64]
+        str     x12, [x0, #80]
+        ret
+ENDPROC(cpu_do_suspend)
+
+/**
+ * cpu_do_resume - restore CPU register context
+ *
+ * x0: Physical address of context pointer
+ * x1: ttbr0_el1 to be restored
+ *
+ * Returns:
+ *      sctlr_el1 value in x0
+ */
+ENTRY(cpu_do_resume)
+        /*
+         * Invalidate local tlb entries before turning on MMU
+         */
+        tlbi    vmalle1
+        ldp     x2, x3, [x0]
+        ldp     x4, x5, [x0, #16]
+        ldp     x6, x7, [x0, #32]
+        ldp     x8, x9, [x0, #48]
+        ldp     x10, x11, [x0, #64]
+        ldr     x12, [x0, #80]
+        msr     tpidr_el0, x2
+        msr     tpidrro_el0, x3
+        msr     contextidr_el1, x4
+        msr     mair_el1, x5
+        msr     cpacr_el1, x6
+        msr     ttbr0_el1, x1
+        msr     ttbr1_el1, x7
+        msr     tcr_el1, x8
+        msr     vbar_el1, x9
+        msr     mdscr_el1, x10
+        /*
+         * Restore oslsr_el1 by writing oslar_el1
+         */
+        ubfx    x11, x11, #1, #1
+        msr     oslar_el1, x11
+        mov     x0, x12
+        dsb     nsh             // Make sure local tlb invalidation completed
+        isb
+        ret
+ENDPROC(cpu_do_resume)
+#endif
+
 /*
- *      cpu_switch_mm(pgd_phys, tsk)
+ *      cpu_do_switch_mm(pgd_phys, tsk)
  *
  *      Set the translation table base pointer to be pgd_phys.
  *
diff --git a/arch/avr32/include/asm/Kbuild b/arch/avr32/include/asm/Kbuild
index 658001b52400..cfb9fe1b8df9 100644
--- a/arch/avr32/include/asm/Kbuild
+++ b/arch/avr32/include/asm/Kbuild
@@ -18,3 +18,4 @@ generic-y       += sections.h
 generic-y       += topology.h
 generic-y       += trace_clock.h
 generic-y       += xor.h
+generic-y       += hash.h
diff --git a/arch/avr32/include/uapi/asm/socket.h b/arch/avr32/include/uapi/asm/socket.h
index cbf902e4cd9e..6e6cd159924b 100644
--- a/arch/avr32/include/uapi/asm/socket.h
+++ b/arch/avr32/include/uapi/asm/socket.h
@@ -78,4 +78,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _UAPI__ASM_AVR32_SOCKET_H */
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 90b175323644..af2738c7441b 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -146,6 +146,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OTG_BLACKLIST_HUB=y
 CONFIG_USB_MON=y
 CONFIG_USB_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
 CONFIG_USB_MUSB_BLACKFIN=y
 CONFIG_MUSB_PIO_ONLY=y
 CONFIG_USB_STORAGE=y
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index 972aa6263ad0..be03be6ba543 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -59,7 +59,6 @@ CONFIG_BFIN_SIR=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
index 91988370b75e..802f9c421621 100644
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -49,7 +49,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 7b982d0502ad..3853c473b443 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -44,7 +44,6 @@ CONFIG_IP_PNP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index c940a1e3ab36..5e0db82b679e 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -36,7 +36,6 @@ CONFIG_UNIX=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index e961483f1879..b9af4fa69984 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -53,7 +53,6 @@ CONFIG_INET_XFRM_MODE_BEET=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index 24936b91a6ee..d6dd98e67146 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -51,7 +51,6 @@ CONFIG_INET=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
index 89162d0fff9e..2b58cb221283 100644
--- a/arch/blackfin/configs/DNP5370_defconfig
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -36,7 +36,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_DEBUG=y
 CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_NFTL=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index a26436bf50ff..f754e490bbfd 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -36,7 +36,6 @@ CONFIG_IRTTY_SIR=m
 # CONFIG_WIRELESS is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index 647991514ac9..629516578760 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -43,7 +43,6 @@ CONFIG_IP_NF_TARGET_REJECT=y
 CONFIG_IP_NF_MANGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index 8fd9b446d658..a6a7298962ed 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -46,7 +46,6 @@ CONFIG_IP_PNP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index 0520c160230d..bc216646fe18 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -38,7 +38,6 @@ CONFIG_IRTTY_SIR=m
 # CONFIG_WIRELESS is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_JEDECPROBE=m
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
index e4ed865b885e..ea88158ab432 100644
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ b/arch/blackfin/configs/TCM-BF518_defconfig
@@ -54,7 +54,6 @@ CONFIG_IP_PNP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index f2b43474b0e2..359d36fdc247 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -45,3 +45,4 @@ generic-y += unaligned.h
 generic-y += user.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
index 9053beda8c50..7ac2436856a5 100644
--- a/arch/blackfin/include/asm/clkdev.h
+++ b/arch/blackfin/include/asm/clkdev.h
@@ -8,7 +8,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
         return kzalloc(size, GFP_KERNEL);
 }
 
+#ifndef CONFIG_COMMON_CLK
 #define __clk_put(clk)
 #define __clk_get(clk) ({ 1; })
+#endif
 
 #endif
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index ca67145c6a45..c5c8d8a3a5fa 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -544,6 +544,7 @@ do { \
 #define DCBS_P                  0x04    /* L1 Data Cache Bank Select */
 #define PORT_PREF0_P            0x12    /* DAG0 Port Preference */
 #define PORT_PREF1_P            0x13    /* DAG1 Port Preference */
+#define RDCHK                   0x9     /* Enable L1 Parity Check */
 
 /* Masks */
 #define ENDM               0x00000001   /* (doesn't really exist) Enable
diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h
index 9558416d578b..3b125da5dcb2 100644
--- a/arch/blackfin/include/uapi/asm/byteorder.h
+++ b/arch/blackfin/include/uapi/asm/byteorder.h
@@ -1 +1,6 @@
+#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
+#define _UAPI__BFIN_ASM_BYTEORDER_H
+
 #include <linux/byteorder/little_endian.h>
+
+#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */
diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h
index 03255df6c1ea..4fdab75dee15 100644
--- a/arch/blackfin/include/uapi/asm/cachectl.h
+++ b/arch/blackfin/include/uapi/asm/cachectl.h
@@ -7,8 +7,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _ASM_CACHECTL
-#define _ASM_CACHECTL
+#ifndef _UAPI_ASM_CACHECTL
+#define _UAPI_ASM_CACHECTL
 
 /*
  * Options for cacheflush system call
@@ -17,4 +17,4 @@
 #define DCACHE  (1<<1)          /* writeback and flush data cache */
 #define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
 
-#endif  /* _ASM_CACHECTL */
+#endif /* _UAPI_ASM_CACHECTL */
diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h
index 251c911d59c1..f51ad9a4f617 100644
--- a/arch/blackfin/include/uapi/asm/fcntl.h
+++ b/arch/blackfin/include/uapi/asm/fcntl.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _BFIN_FCNTL_H
-#define _BFIN_FCNTL_H
+#ifndef _UAPI_BFIN_FCNTL_H
+#define _UAPI_BFIN_FCNTL_H
 
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
@@ -14,4 +14,4 @@
 
 #include <asm-generic/fcntl.h>
 
-#endif
+#endif /* _UAPI_BFIN_FCNTL_H */
diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h
index eca8d75b0a8a..9a41c20fc83d 100644
--- a/arch/blackfin/include/uapi/asm/ioctls.h
+++ b/arch/blackfin/include/uapi/asm/ioctls.h
@@ -1,7 +1,7 @@
-#ifndef __ARCH_BFIN_IOCTLS_H__
-#define __ARCH_BFIN_IOCTLS_H__
+#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
+#define _UAPI__ARCH_BFIN_IOCTLS_H__
 
 #define FIOQSIZE        0x545E
 #include <asm-generic/ioctls.h>
 
-#endif
+#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h
index 072d8966c5c3..99c7d6816da0 100644
--- a/arch/blackfin/include/uapi/asm/poll.h
+++ b/arch/blackfin/include/uapi/asm/poll.h
@@ -5,12 +5,12 @@
  *
  */
 
-#ifndef __BFIN_POLL_H
-#define __BFIN_POLL_H
+#ifndef _UAPI__BFIN_POLL_H
+#define _UAPI__BFIN_POLL_H
 
 #define POLLWRNORM      4 /* POLLOUT */
 #define POLLWRBAND      256
 
 #include <asm-generic/poll.h>
 
-#endif
+#endif /* _UAPI__BFIN_POLL_H */
diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h
index 1bd3436db6a7..9608ef64dc47 100644
--- a/arch/blackfin/include/uapi/asm/posix_types.h
+++ b/arch/blackfin/include/uapi/asm/posix_types.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef __ARCH_BFIN_POSIX_TYPES_H
-#define __ARCH_BFIN_POSIX_TYPES_H
+#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
+#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
 
 typedef unsigned short __kernel_mode_t;
 #define __kernel_mode_t __kernel_mode_t
@@ -27,4 +27,4 @@ typedef unsigned short __kernel_old_dev_t;
 
 #include <asm-generic/posix_types.h>
 
-#endif
+#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */
diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h
index 906bdc1f5fda..b58f12dc27bd 100644
--- a/arch/blackfin/include/uapi/asm/sigcontext.h
+++ b/arch/blackfin/include/uapi/asm/sigcontext.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
-#define _ASM_BLACKFIN_SIGCONTEXT_H
+#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
+#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
 
 /* Add new entries at the end of the structure only.  */
 struct sigcontext {
@@ -58,4 +58,4 @@ struct sigcontext {
         unsigned long sc_seqstat;
 };
 
-#endif
+#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */
diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h
index 3e81306394e2..c72f4e6e386f 100644
--- a/arch/blackfin/include/uapi/asm/siginfo.h
+++ b/arch/blackfin/include/uapi/asm/siginfo.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _BFIN_SIGINFO_H
-#define _BFIN_SIGINFO_H
+#ifndef _UAPI_BFIN_SIGINFO_H
+#define _UAPI_BFIN_SIGINFO_H
 
 #include <linux/types.h>
 #include <asm-generic/siginfo.h>
@@ -38,4 +38,4 @@
  */
 #define SEGV_STACKFLOW  (__SI_FAULT|3)  /* stack overflow */
 
-#endif
+#endif /* _UAPI_BFIN_SIGINFO_H */
diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h
index 77a3bf37b69d..f0a0d8b6663a 100644
--- a/arch/blackfin/include/uapi/asm/signal.h
+++ b/arch/blackfin/include/uapi/asm/signal.h
@@ -1,7 +1,7 @@
-#ifndef _BLACKFIN_SIGNAL_H
-#define _BLACKFIN_SIGNAL_H
+#ifndef _UAPI_BLACKFIN_SIGNAL_H
+#define _UAPI_BLACKFIN_SIGNAL_H
 
 #define SA_RESTORER 0x04000000
 #include <asm-generic/signal.h>
 
-#endif
+#endif /* _UAPI_BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h
index 2e27665c4e91..d3068a750b94 100644
--- a/arch/blackfin/include/uapi/asm/stat.h
+++ b/arch/blackfin/include/uapi/asm/stat.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2.
  */
 
-#ifndef _BFIN_STAT_H
-#define _BFIN_STAT_H
+#ifndef _UAPI_BFIN_STAT_H
+#define _UAPI_BFIN_STAT_H
 
 struct stat {
         unsigned short st_dev;
@@ -66,4 +66,4 @@ struct stat64 {
         unsigned long long st_ino;
 };
 
-#endif                          /* _BFIN_STAT_H */
+#endif /* _UAPI_BFIN_STAT_H */
diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h
index 89de6507ca2b..f5626b77684a 100644
--- a/arch/blackfin/include/uapi/asm/swab.h
+++ b/arch/blackfin/include/uapi/asm/swab.h
@@ -4,8 +4,8 @@
  * Licensed under the GPL-2 or later.
  */
 
-#ifndef _BLACKFIN_SWAB_H
-#define _BLACKFIN_SWAB_H
+#ifndef _UAPI_BLACKFIN_SWAB_H
+#define _UAPI_BLACKFIN_SWAB_H
 
 #include <linux/types.h>
 #include <asm-generic/swab.h>
@@ -47,4 +47,4 @@ static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
 
 #endif /* __GNUC__ */
 
-#endif                          /* _BLACKFIN_SWAB_H */
+#endif /* _UAPI_BLACKFIN_SWAB_H */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 396193042127..4f424ae3b36d 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -17,7 +17,7 @@
 #ifdef CONFIG_MTD_UCLINUX
 #include <linux/mtd/map.h>
 #include <linux/ext2_fs.h>
-#include <linux/cramfs_fs.h>
+#include <uapi/linux/cramfs_fs.h>
 #include <linux/romfs_fs.h>
 #endif
 
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 4a8c2e3fd7e5..4da70c47cc05 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -370,7 +370,8 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
 
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || \
+        defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
         {
@@ -441,6 +442,50 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
 
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+static struct resource bfin_sport0_resources[] = {
+        {
+                .start = SPORT0_TCR1,
+                .end = SPORT0_MRCS3+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_SPORT0_TX,
+                .end = IRQ_SPORT0_TX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_RX,
+                .end = IRQ_SPORT0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_ERROR,
+                .end = IRQ_SPORT0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_SPORT0_TX,
+                .end = CH_SPORT0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_SPORT0_RX,
+                .end = CH_SPORT0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sport0_device = {
+        .name = "bfin_sport_raw",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sport0_resources),
+        .resource = bfin_sport0_resources,
+        .dev = {
+                .platform_data = &bfin_sport0_peripherals,
+        },
+};
+#endif
+
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index b0fca44110b0..6584190faeb8 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -17,6 +17,12 @@ config SEC_IRQ_PRIORITY_LEVELS
           Divide the total number of interrupt priority levels into sub-levels.
           There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
 
+config L1_PARITY_CHECK
+        bool "Enable L1 parity check"
+        default n
+        help
+          Enable the L1 parity check in L1 sram. A fault event is raised
+          when L1 parity error is found.
 
 comment "System Cross Bar Priority Assignment"
 
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index 82beedd953f6..8de8bc690b36 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -117,7 +117,7 @@ static struct stmmac_dma_cfg eth_dma_cfg = {
         .pbl    = 2,
 };
 
-int stmmac_ptp_clk_init(struct platform_device *pdev)
+int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
 {
         bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
         return 0;
@@ -1025,7 +1025,9 @@ static struct adv7842_platform_data adv7842_data = {
         .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
         .prim_mode = ADV7842_PRIM_MODE_SDP,
         .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
-        .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
+        .hdmi_free_run_enable = 1,
+        .sdp_free_run_auto = 1,
+        .llc_dll_phase = 0x10,
         .i2c_sdp_io = 0x40,
         .i2c_sdp = 0x41,
         .i2c_cp = 0x42,
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index dab8849af884..13644ed25489 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -120,6 +120,7 @@ void clk_disable(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_disable);
 
+
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long ret = 0;
@@ -131,7 +132,7 @@ EXPORT_SYMBOL(clk_get_rate);
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        long ret = -EIO;
+        long ret = 0;
         if (clk->ops && clk->ops->round_rate)
                 ret = clk->ops->round_rate(clk, rate);
         return ret;
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index 7a07374308ac..696786e9a531 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -23,11 +23,11 @@
 /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
 #define ANOMALY_16000003 (1)
 /* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (1)
+#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
 /* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (1)
+#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
 /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (1)
+#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
 /* DDR2 Memory Reads May Fail Intermittently */
 #define ANOMALY_16000007 (1)
 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
@@ -49,19 +49,53 @@
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_16000017 (1)
 /* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (1)
+#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
 /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (1)
+#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
 /* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (1)
+#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
 /* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (1)
+#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
 /* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (1)
+#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
+/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
+#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
+/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
+#define ANOMALY_16000024 (1)
+/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
+#define ANOMALY_16000025 (1)
 /* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (1)
+#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
+/* Default SPI Master Boot Mode Setting is Incorrect */
+#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
+/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
+#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
 /* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (1)
+#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
+/* Incorrect Default USB_PLL_OSC.PLLM Value */
+#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
+/* Core Reads of System MMRs May Cause the Core to Hang */
+#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
+/* PPI Data Underflow on First Word Not Reported in Certain Modes */
+#define ANOMALY_16000033 (1)
+/* CNV1 Red Pixel Substitution feature not functional in the PVP */
+#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
+/* IPF0 Output Port Color Separation feature not functional */
+#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
+/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
+#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
+/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
+#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
+/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
+#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
+/* CGU_STAT.PLOCKERR Bit May be Unreliable */
+#define ANOMALY_16000039 (1)
+/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
+#define ANOMALY_16000040 (1)
+/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
+#define ANOMALY_16000041 (1)
+/* Instruction Cache Failure When Parity Is Enabled */
+#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
index 0e1e451fd7d8..f4adedc92895 100644
--- a/arch/blackfin/mach-common/cache-c.c
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -6,7 +6,6 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/init.h>
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
 
@@ -42,6 +41,16 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
                 unsigned long mem_mask)
 {
         int i;
+#ifdef CONFIG_L1_PARITY_CHECK
+        u32 ctrl;
+
+        if (cplb_addr == DCPLB_ADDR0) {
+                ctrl = bfin_read32(mem_control) | (1 << RDCHK);
+                CSYNC();
+                bfin_write32(mem_control, ctrl);
+                SSYNC();
+        }
+#endif
 
         for (i = 0; i < MAX_CPLBS; i++) {
                 bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 2308ce52f849..d436bd907fc8 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -7,7 +7,6 @@
  */
 
 #include <linux/linkage.h>
-#include <linux/init.h>
 #include <asm/blackfin.h>
 
 #include <asm/dma.h>
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index ca75613231c8..867b7cef204c 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -471,13 +471,8 @@ void handle_sec_ssi_fault(uint32_t gstat)
 
 }
 
-void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
+void handle_sec_fault(uint32_t sec_gstat)
 {
-        uint32_t sec_gstat;
-
-        raw_spin_lock(&desc->lock);
-
-        sec_gstat = bfin_read32(SEC_GSTAT);
         if (sec_gstat & SEC_GSTAT_ERR) {
 
                 switch (sec_gstat & SEC_GSTAT_ERRC) {
@@ -494,18 +489,16 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
 
 
         }
-
-        raw_spin_unlock(&desc->lock);
-
-        handle_fasteoi_irq(irq, desc);
 }
 
-void handle_core_fault(unsigned int irq, struct irq_desc *desc)
+static struct irqaction bfin_fault_irq = {
+        .name = "Blackfin fault",
+};
+
+static irqreturn_t bfin_fault_routine(int irq, void *data)
 {
         struct pt_regs *fp = get_irq_regs();
 
-        raw_spin_lock(&desc->lock);
-
         switch (irq) {
         case IRQ_C0_DBL_FAULT:
                 double_fault_c(fp);
@@ -522,11 +515,15 @@ void handle_core_fault(unsigned int irq, struct irq_desc *desc)
         case IRQ_C0_NMI_L1_PARITY_ERR:
                 panic("Core 0 NMI L1 parity error");
                 break;
+        case IRQ_SEC_ERR:
+                pr_err("SEC error\n");
+                handle_sec_fault(bfin_read32(SEC_GSTAT));
+                break;
         default:
-                panic("Core 1 fault %d occurs unexpectedly", irq);
+                panic("Unknown fault %d", irq);
         }
 
-        raw_spin_unlock(&desc->lock);
+        return IRQ_HANDLED;
 }
 #endif /* SEC_GCTL */
 
@@ -1195,12 +1192,7 @@ int __init init_arch_irq(void)
                                 handle_percpu_irq);
                 } else {
                         irq_set_chip(irq, &bfin_sec_irqchip);
-                        if (irq == IRQ_SEC_ERR)
-                                irq_set_handler(irq, handle_sec_fault);
-                        else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS)
-                                irq_set_handler(irq, handle_core_fault);
-                        else
-                                irq_set_handler(irq, handle_fasteoi_irq);
+                        irq_set_handler(irq, handle_fasteoi_irq);
                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
                 }
         }
@@ -1239,6 +1231,13 @@ int __init init_arch_irq(void)
         register_syscore_ops(&sec_pm_syscore_ops);
 #endif
 
+        bfin_fault_irq.handler = bfin_fault_routine;
+#ifdef CONFIG_L1_PARITY_CHECK
+        setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
+#endif
+        setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
+        setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c
index 2cbfb0b5679e..8923398db66f 100644
--- a/arch/blackfin/mach-common/scb-init.c
+++ b/arch/blackfin/mach-common/scb-init.c
@@ -6,7 +6,6 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <asm/scb.h>
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 2bbae0783819..ba6c30d8534d 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -53,7 +53,6 @@ enum ipi_message_type {
         BFIN_IPI_TIMER,
         BFIN_IPI_RESCHEDULE,
         BFIN_IPI_CALL_FUNC,
-        BFIN_IPI_CALL_FUNC_SINGLE,
         BFIN_IPI_CPU_STOP,
 };
 
@@ -162,9 +161,6 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
                         case BFIN_IPI_CALL_FUNC:
                                 generic_smp_call_function_interrupt();
                                 break;
-                        case BFIN_IPI_CALL_FUNC_SINGLE:
-                                generic_smp_call_function_single_interrupt();
-                                break;
                         case BFIN_IPI_CPU_STOP:
                                 ipi_cpu_stop(cpu);
                                 break;
@@ -210,7 +206,7 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC_SINGLE);
+        send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
 }
 
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
index fc0b3c356027..d73bb85ccdd3 100644
--- a/arch/c6x/include/asm/Kbuild
+++ b/arch/c6x/include/asm/Kbuild
@@ -57,3 +57,4 @@ generic-y += user.h
 generic-y += vga.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 9c957c81c688..ed0fcdf7e990 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -122,12 +122,6 @@ config ETRAX100LX_V2
         help
           Support version 2 of the ETRAX 100LX.
 
-config SVINTO_SIM
-        bool "ETRAX-100LX-for-xsim-simulator"
-        select ARCH_USES_GETTIMEOFFSET
-        help
-          Support the xsim ETRAX Simulator.
-
 config ETRAXFS
         bool "ETRAX-FS-V32"
         help
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
index 609d5510410e..f4374bae4fb4 100644
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ b/arch/cris/arch-v10/drivers/gpio.c
@@ -838,13 +838,13 @@ static int __init gpio_init(void)
          * in some tests.
          */
         res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
-                IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
+                IRQF_SHARED, "gpio poll", gpio_name);
         if (res) {
                 printk(KERN_CRIT "err: timer0 irq for gpio\n");
                 return res;
         }
         res = request_irq(PA_IRQ_NBR, gpio_interrupt,
-                IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
+                IRQF_SHARED, "gpio PA", gpio_name);
         if (res)
                 printk(KERN_CRIT "err: PA irq for gpio\n");
 
diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c
index a1c498d18d31..29eb02ab3f25 100644
--- a/arch/cris/arch-v10/drivers/sync_serial.c
+++ b/arch/cris/arch-v10/drivers/sync_serial.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 #include <linux/timer.h>
+#include <linux/wait.h>
 #include <asm/irq.h>
 #include <asm/dma.h>
 #include <asm/io.h>
@@ -580,7 +581,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                         if (port == &ports[0]) {
                                 if (request_irq(8,
                                                 manual_interrupt,
-                                                IRQF_SHARED | IRQF_DISABLED,
+                                                IRQF_SHARED,
                                                 "synchronous serial manual irq",
                                                 &ports[0])) {
                                         printk(KERN_CRIT "Can't alloc "
@@ -590,7 +591,7 @@ static int sync_serial_open(struct inode *inode, struct file *file)
                         } else if (port == &ports[1]) {
                                 if (request_irq(8,
                                                 manual_interrupt,
-                                                IRQF_SHARED | IRQF_DISABLED,
+                                                IRQF_SHARED,
                                                 "synchronous serial manual irq",
                                                 &ports[1])) {
                                         printk(KERN_CRIT "Can't alloc "
@@ -1136,7 +1137,8 @@ static ssize_t sync_serial_read(struct file *file, char *buf,
                 if (file->f_flags & O_NONBLOCK)
                         return -EAGAIN;
 
-                interruptible_sleep_on(&port->in_wait_q);
+                wait_event_interruptible(port->in_wait_q,
+                                         !(start == end && !port->full));
                 if (signal_pending(current))
                         return -EINTR;
 
diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile
index dcfec41d3533..4841e822cdd1 100644
--- a/arch/cris/arch-v10/kernel/Makefile
+++ b/arch/cris/arch-v10/kernel/Makefile
@@ -1,4 +1,3 @@
-# $Id: Makefile,v 1.6 2004/12/13 12:21:51 starvik Exp $
 #
 # Makefile for the linux kernel.
 #
diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c
index f932c85fbde4..7d307cce8bd8 100644
--- a/arch/cris/arch-v10/kernel/debugport.c
+++ b/arch/cris/arch-v10/kernel/debugport.c
@@ -19,7 +19,6 @@
 #include <linux/delay.h>
 #include <linux/tty.h>
 #include <arch/svinto.h>
-#include <asm/io.h>             /* Get SIMCOUT. */
 
 extern void reset_watchdog(void);
 
@@ -318,12 +317,6 @@ console_write(struct console *co, const char *buf, unsigned int len)
         if (!port)
                 return;
 
-#ifdef CONFIG_SVINTO_SIM
-        /* no use to simulate the serial debug output */
-        SIMCOUT(buf, len);
-        return;
-#endif
-
         console_write_direct(co, buf, len);
 }
 
diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S
index 897bba67bf7a..81570fcd0412 100644
--- a/arch/cris/arch-v10/kernel/entry.S
+++ b/arch/cris/arch-v10/kernel/entry.S
@@ -13,8 +13,8 @@
  * after a timer-interrupt and after each system call.
  *
  * Stack layout in 'ret_from_system_call':
- *      ptrace needs to have all regs on the stack.
- *      if the order here is changed, it needs to be 
+ *      ptrace needs to have all regs on the stack.
+ *      if the order here is changed, it needs to be
  *      updated in fork.c:copy_process, signal.c:do_signal,
  *      ptrace.c and ptrace.h
  *
@@ -31,7 +31,7 @@
 #include <asm/pgtable.h>
 
         ;; functions exported from this file
-        
+
         .globl system_call
         .globl ret_from_intr
         .globl ret_from_fork
@@ -46,10 +46,10 @@
         .globl do_sigtrap
         .globl gdb_handle_breakpoint
         .globl sys_call_table
-        
+
         ;; below are various parts of system_call which are not in the fast-path
-        
-#ifdef CONFIG_PREEMPT   
+
+#ifdef CONFIG_PREEMPT
         ; Check if preemptive kernel scheduling should be done
 _resume_kernel:
         di
@@ -74,7 +74,7 @@ _need_resched:
         nop
 #else
 #define _resume_kernel _Rexit
-#endif  
+#endif
 
         ; Called at exit from fork. schedule_tail must be called to drop
         ; spinlock if CONFIG_PREEMPT
@@ -91,16 +91,16 @@ ret_from_kernel_thread:
         ba  ret_from_sys_call
 
 ret_from_intr:
-        ;; check for resched if preemptive kernel or if we're going back to user-mode 
+        ;; check for resched if preemptive kernel or if we're going back to user-mode
         ;; this test matches the user_regs(regs) macro
         ;; we cannot simply test $dccr, because that does not necessarily
         ;; reflect what mode we'll return into.
-        
+
         move.d  [$sp + PT_dccr], $r0; regs->dccr
         btstq   8, $r0          ; U-flag
         bpl     _resume_kernel
-        ; Note that di below is in delay slot 
-        
+        ; Note that di below is in delay slot
+
 _resume_userspace:
         di                      ; so need_resched and sigpending don't change
 
@@ -113,7 +113,7 @@ _resume_userspace:
         nop
         ba      _Rexit
         nop
-        
+
         ;; The system_call is called by a BREAK instruction, which works like
         ;; an interrupt call but it stores the return PC in BRP instead of IRP.
         ;; Since we dont really want to have two epilogues (one for system calls
@@ -123,7 +123,7 @@ _resume_userspace:
         ;;
         ;; Since we can't have system calls inside interrupts, it should not matter
         ;; that we don't stack IRP.
-        ;; 
+        ;;
         ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,r13,mof,srp
         ;;
         ;; This function looks on the _surface_ like spaghetti programming, but it's
@@ -140,7 +140,7 @@ system_call:
         movem   $r13, [$sp]     ; push r0-r13
         push    $r10            ; push orig_r10
         clear.d [$sp=$sp-4]     ; frametype == 0, normal stackframe
-        
+
         movs.w  -ENOSYS, $r0
         move.d  $r0, [$sp+PT_r10]       ; put the default return value in r10 in the frame
 
@@ -148,17 +148,17 @@ system_call:
 
         movs.w  -8192, $r0      ; THREAD_SIZE == 8192
         and.d   $sp, $r0
-        
+
         move.d  [$r0+TI_flags], $r0
         btstq   TIF_SYSCALL_TRACE, $r0
         bmi     _syscall_trace_entry
-        nop     
+        nop
 
-_syscall_traced:        
+_syscall_traced:
 
         ;; check for sanity in the requested syscall number
-        
-        cmpu.w  NR_syscalls, $r9        
+
+        cmpu.w  NR_syscalls, $r9
         bcc     ret_from_sys_call
         lslq    2, $r9          ;  multiply by 4, in the delay slot
 
@@ -166,28 +166,28 @@ _syscall_traced:
         ;; of the register structure itself. some syscalls need this.
 
         push    $sp
-        
+
         ;; the parameter carrying registers r10, r11, r12 and 13 are intact.
-        ;; the fifth and sixth parameters (if any) was in mof and srp 
+        ;; the fifth and sixth parameters (if any) was in mof and srp
         ;; respectively, and we need to put them on the stack.
 
         push    $srp
         push    $mof
-        
+
         jsr     [$r9+sys_call_table]    ; actually do the system call
         addq    3*4, $sp                ; pop the mof, srp and regs parameters
         move.d  $r10, [$sp+PT_r10]      ; save the return value
 
         moveq   1, $r9          ; "parameter" to ret_from_sys_call to show it was a sys call
-        
+
         ;; fall through into ret_from_sys_call to return
-        
+
 ret_from_sys_call:
         ;; r9 is a parameter - if >=1 we came from a syscall, if 0, from an irq
-                
+
         ;; get the current task-struct pointer (see top for defs)
 
-        movs.w  -8192, $r0      ; THREAD_SIZE == 8192 
+        movs.w  -8192, $r0      ; THREAD_SIZE == 8192
         and.d   $sp, $r0
 
         di                      ; make sure need_resched and sigpending don't change
@@ -202,7 +202,7 @@ _Rexit:
         bne     _RBFexit        ; was not CRIS_FRAME_NORMAL, handle otherwise
         addq    4, $sp          ; skip orig_r10, in delayslot
         movem   [$sp+], $r13    ; registers r0-r13
-        pop     $mof            ; multiply overflow register 
+        pop     $mof            ; multiply overflow register
         pop     $dccr           ; condition codes
         pop     $srp            ; subroutine return pointer
         ;; now we have a 4-word SBFS frame which we do not want to restore
@@ -216,14 +216,14 @@ _Rexit:
 
 _RBFexit:
         movem   [$sp+], $r13    ; registers r0-r13, in delay slot
-        pop     $mof            ; multiply overflow register 
+        pop     $mof            ; multiply overflow register
         pop     $dccr           ; condition codes
         pop     $srp            ; subroutine return pointer
         rbf     [$sp+]          ; return by popping the CPU status
 
         ;; We get here after doing a syscall if extra work might need to be done
         ;; perform syscall exit tracing if needed
-        
+
 _syscall_exit_work:
         ;; $r0 contains current at this point and irq's are disabled
 
@@ -231,22 +231,22 @@ _syscall_exit_work:
         btstq   TIF_SYSCALL_TRACE, $r1
         bpl     _work_pending
         nop
-        
+
         ei
 
         move.d  $r9, $r1        ; preserve r9
         jsr     do_syscall_trace
         move.d  $r1, $r9
-        
+
         ba      _resume_userspace
         nop
-        
+
 _work_pending:
         move.d  [$r0+TI_flags], $r1
         btstq   TIF_NEED_RESCHED, $r1
         bpl     _work_notifysig ; was neither trace nor sched, must be signal/notify
         nop
-        
+
 _work_resched:
         move.d  $r9, $r1        ; preserve r9
         jsr     schedule
@@ -268,17 +268,17 @@ _work_notifysig:
         move.d  $sp, $r11       ; the regs param
         move.d  $r1, $r12       ; the thread_info_flags parameter
         jsr     do_notify_resume
-        
+
         ba _Rexit
         nop
 
         ;; We get here as a sidetrack when we've entered a syscall with the
         ;; trace-bit set. We need to call do_syscall_trace and then continue
         ;; with the call.
-        
+
 _syscall_trace_entry:
         ;; PT_r10 in the frame contains -ENOSYS as required, at this point
-        
+
         jsr     do_syscall_trace
 
         ;; now re-enter the syscall code to do the syscall itself
@@ -292,10 +292,10 @@ _syscall_trace_entry:
         move.d  [$sp+PT_r13],      $r13
         move    [$sp+PT_mof],      $mof
         move    [$sp+PT_srp],      $srp
-        
+
         ba      _syscall_traced
         nop
-        
+
         ;; resume performs the actual task-switching, by switching stack pointers
         ;; input arguments: r10 = prev, r11 = next, r12 = thread offset in task struct
         ;; returns old current in r10
@@ -303,29 +303,29 @@ _syscall_trace_entry:
         ;; TODO:  see the i386 version. The switch_to which calls resume in our version
         ;;        could really be an inline asm of this.
 
-resume: 
-        push    $srp                     ; we keep the old/new PC on the stack 
+resume:
+        push    $srp                     ; we keep the old/new PC on the stack
         add.d   $r12, $r10               ; r10 = current tasks tss
         move    $dccr, [$r10+THREAD_dccr]; save irq enable state
         di
 
         move    $usp, [$r10+ THREAD_usp] ; save user-mode stackpointer
-        
+
         ;; See copy_thread for the reason why register R9 is saved.
         subq    10*4, $sp
         movem   $r9, [$sp]               ; save non-scratch registers and R9.
-        
+
         move.d  $sp, [$r10+THREAD_ksp]   ; save the kernel stack pointer for the old task
         move.d  $sp, $r10                ; return last running task in r10
         and.d   -8192, $r10              ; get thread_info from stackpointer
-        move.d  [$r10+TI_task], $r10     ; get task  
+        move.d  [$r10+TI_task], $r10     ; get task
         add.d   $r12, $r11               ; find the new tasks tss
         move.d  [$r11+THREAD_ksp], $sp   ; switch into the new stackframe by restoring kernel sp
 
         movem   [$sp+], $r9              ; restore non-scratch registers and R9.
 
         move    [$r11+THREAD_usp], $usp ; restore user-mode stackpointer
-        
+
         move    [$r11+THREAD_dccr], $dccr ; restore irq enable status
         jump    [$sp+]                   ; restore PC
 
@@ -401,7 +401,7 @@ mmu_bus_fault:
         push    $r10            ; frametype == 1, BUSFAULT frame type
 
         move.d  $sp, $r10       ; pt_regs argument to handle_mmu_bus_fault
-                
+
         jsr     handle_mmu_bus_fault  ; in arch/cris/arch-v10/mm/fault.c
 
         ;; now we need to return through the normal path, we cannot just
@@ -410,10 +410,10 @@ mmu_bus_fault:
         ;; whatever.
 
         moveq   0, $r9          ; busfault is equivalent to an irq
-                
+
         ba      ret_from_intr
         nop
-                
+
         ;; special handlers for breakpoint and NMI
 hwbreakpoint:
         push    $dccr
@@ -429,7 +429,7 @@ hwbreakpoint:
         pop     $dccr
         retb
         nop
-        
+
 IRQ1_interrupt:
         ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
         move    $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
@@ -457,7 +457,7 @@ IRQ1_interrupt:
         ba      _Rexit          ; Return the standard way
         nop
 wdog:
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_WATCHDOG)
 ;; Check if we're waiting for reset to happen, as signalled by
 ;; hard_reset_now setting cause_of_death to a magic value.  If so, just
 ;; get stuck until reset happens.
@@ -500,7 +500,7 @@ Watchdog_bite:
         move.d  $r10, [$r11]
 
 #endif
-        
+
 ;; Note that we don't do "setf m" here (or after two necessary NOPs),
 ;; since *not* doing that saves us from re-entrancy checks.  We don't want
 ;; to get here again due to possible subsequent NMIs; we want the watchdog
@@ -523,16 +523,16 @@ _watchdogmsg:
         .ascii  "Oops: bitten by watchdog\n\0"
         .previous
 
-#endif /* CONFIG_ETRAX_WATCHDOG and not CONFIG_SVINTO_SIM */
+#endif /* CONFIG_ETRAX_WATCHDOG */
 
-spurious_interrupt:     
+spurious_interrupt:
         di
         jump hard_reset_now
 
         ;; this handles the case when multiple interrupts arrive at the same time
         ;; we jump to the first set interrupt bit in a priority fashion
         ;; the hardware will call the unserved interrupts after the handler finishes
-        
+
 multiple_interrupt:
         ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
         move    $irp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
@@ -551,7 +551,7 @@ multiple_interrupt:
         jump    ret_from_intr
 
 do_sigtrap:
-        ;; 
+        ;;
         ;; SIGTRAP the process that executed the break instruction.
         ;; Make a frame that Rexit in entry.S expects.
         ;;
@@ -568,30 +568,30 @@ do_sigtrap:
         movs.w  -8192,$r9               ; THREAD_SIZE == 8192
         and.d   $sp, $r9
         move.d  [$r9+TI_task], $r10
-        move.d  [$r10+TASK_pid], $r10   ; current->pid as arg1. 
+        move.d  [$r10+TASK_pid], $r10   ; current->pid as arg1.
         moveq   5, $r11                 ; SIGTRAP as arg2.
-        jsr     sys_kill       
+        jsr     sys_kill
         jump    ret_from_intr           ; Use the return routine for interrupts.
 
-gdb_handle_breakpoint:  
+gdb_handle_breakpoint:
         push    $dccr
         push    $r0
 #ifdef CONFIG_ETRAX_KGDB
-        move    $dccr, $r0              ; U-flag not affected by previous insns. 
+        move    $dccr, $r0              ; U-flag not affected by previous insns.
         btstq   8, $r0                  ; Test the U-flag.
-        bmi     _ugdb_handle_breakpoint ; Go to user mode debugging. 
-        nop                             ; Empty delay slot (cannot pop r0 here). 
+        bmi     _ugdb_handle_breakpoint ; Go to user mode debugging.
+        nop                             ; Empty delay slot (cannot pop r0 here).
         pop     $r0                     ; Restore r0.
-        ba      kgdb_handle_breakpoint  ; Go to kernel debugging. 
+        ba      kgdb_handle_breakpoint  ; Go to kernel debugging.
         pop     $dccr                   ; Restore dccr in delay slot.
 #endif
-        
-_ugdb_handle_breakpoint:        
+
+_ugdb_handle_breakpoint:
         move    $brp, $r0               ; Use r0 temporarily for calculation.
         subq    2, $r0                  ; Set to address of previous instruction.
         move    $r0, $brp
-        pop     $r0                     ; Restore r0. 
-        ba      do_sigtrap              ; SIGTRAP the offending process. 
+        pop     $r0                     ; Restore r0.
+        ba      do_sigtrap              ; SIGTRAP the offending process.
         pop     $dccr                   ; Restore dccr in delay slot.
 
         .data
@@ -602,7 +602,7 @@ hw_bp_trig_ptr:
         .dword hw_bp_trigs
 
         .section .rodata,"a"
-sys_call_table: 
+sys_call_table:
         .long sys_restart_syscall       /* 0 - old "setup()" system call, used for restarting */
         .long sys_exit
         .long sys_fork
@@ -713,7 +713,7 @@ sys_call_table:
         .long sys_newlstat
         .long sys_newfstat
         .long sys_ni_syscall    /* old sys_uname holder */
-        .long sys_ni_syscall    /* sys_iopl in i386 */
+        .long sys_ni_syscall    /* 110 */ /* sys_iopl in i386 */
         .long sys_vhangup
         .long sys_ni_syscall    /* old "idle" system call */
         .long sys_ni_syscall    /* vm86old in i386 */
@@ -730,7 +730,7 @@ sys_call_table:
         .long sys_adjtimex
         .long sys_mprotect      /* 125 */
         .long sys_sigprocmask
-        .long sys_ni_syscall    /* old "create_module" */ 
+        .long sys_ni_syscall    /* old "create_module" */
         .long sys_init_module
         .long sys_delete_module
         .long sys_ni_syscall    /* 130: old "get_kernel_syms" */
@@ -795,7 +795,7 @@ sys_call_table:
         .long sys_ni_syscall    /* streams2 */
         .long sys_vfork         /* 190 */
         .long sys_getrlimit
-        .long sys_mmap2
+        .long sys_mmap2         /* mmap_pgoff */
         .long sys_truncate64
         .long sys_ftruncate64
         .long sys_stat64        /* 195 */
@@ -861,21 +861,21 @@ sys_call_table:
         .long sys_epoll_ctl     /* 255 */
         .long sys_epoll_wait
         .long sys_remap_file_pages
-        .long sys_set_tid_address
-        .long sys_timer_create
-        .long sys_timer_settime         /* 260 */
-        .long sys_timer_gettime
-        .long sys_timer_getoverrun
-        .long sys_timer_delete
-        .long sys_clock_settime
-        .long sys_clock_gettime         /* 265 */
-        .long sys_clock_getres
-        .long sys_clock_nanosleep
+        .long sys_set_tid_address
+        .long sys_timer_create
+        .long sys_timer_settime         /* 260 */
+        .long sys_timer_gettime
+        .long sys_timer_getoverrun
+        .long sys_timer_delete
+        .long sys_clock_settime
+        .long sys_clock_gettime         /* 265 */
+        .long sys_clock_getres
+        .long sys_clock_nanosleep
         .long sys_statfs64
-        .long sys_fstatfs64     
-        .long sys_tgkill        /* 270 */
+        .long sys_fstatfs64
+        .long sys_tgkill                /* 270 */
         .long sys_utimes
-        .long sys_fadvise64_64
+        .long sys_fadvise64_64
         .long sys_ni_syscall    /* sys_vserver */
         .long sys_ni_syscall    /* sys_mbind */
         .long sys_ni_syscall    /* 275 sys_get_mempolicy */
@@ -886,7 +886,7 @@ sys_call_table:
         .long sys_mq_timedreceive       /* 280 */
         .long sys_mq_notify
         .long sys_mq_getsetattr
-        .long sys_ni_syscall            /* reserved for kexec */
+        .long sys_ni_syscall
         .long sys_waitid
         .long sys_ni_syscall            /* 285 */ /* available */
         .long sys_add_key
@@ -939,6 +939,22 @@ sys_call_table:
         .long sys_preadv
         .long sys_pwritev
         .long sys_setns                 /* 335 */
+        .long sys_name_to_handle_at
+        .long sys_open_by_handle_at
+        .long sys_rt_tgsigqueueinfo
+        .long sys_perf_event_open
+        .long sys_recvmmsg              /* 340 */
+        .long sys_accept4
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
+        .long sys_clock_adjtime         /* 345 */
+        .long sys_syncfs
+        .long sys_sendmmsg
+        .long sys_process_vm_readv
+        .long sys_process_vm_writev
+        .long sys_kcmp                  /* 350 */
+        .long sys_finit_module
 
         /*
          * NOTE!! This doesn't have to be exact - we just have
@@ -950,4 +966,4 @@ sys_call_table:
         .rept NR_syscalls-(.-sys_call_table)/4
                 .long sys_ni_syscall
         .endr
-        
+
diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S
index a1f2014b4e3b..4a146e1749c9 100644
--- a/arch/cris/arch-v10/kernel/head.S
+++ b/arch/cris/arch-v10/kernel/head.S
@@ -1,12 +1,10 @@
 /*
  * Head of the kernel - alter with care
  *
- * Copyright (C) 2000, 2001 Axis Communications AB
+ * Copyright (C) 2000, 2001, 2010 Axis Communications AB
  *
- * Authors:     Bjorn Wesen (bjornw@axis.com)
- * 
  */
-        
+
 #define ASSEMBLER_MACROS_ONLY
 /* The IO_* macros use the ## token concatenation operator, so
    -traditional must not be used when assembling this file.  */
@@ -18,15 +16,15 @@
 
 #define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
                              IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
-                                
+
         ;; exported symbols
-                
+
         .globl  etrax_irv
         .globl  romfs_start
         .globl  romfs_length
         .globl  romfs_in_flash
         .globl  swapper_pg_dir
-                                        
+
         .text
 
         ;; This is the entry point of the kernel. We are in supervisor mode.
@@ -35,10 +33,10 @@
         ;; put a nop (2 bytes) here first so we dont accidentally skip the di
         ;;
         ;; NOTICE! The registers r8 and r9 are used as parameters carrying
-        ;; information from the decompressor (if the kernel was compressed). 
+        ;; information from the decompressor (if the kernel was compressed).
         ;; They should not be used in the code below until read.
-        
-        nop     
+
+        nop
         di
 
         ;; First setup the kseg_c mapping from where the kernel is linked
@@ -58,19 +56,19 @@
 
 #ifdef CONFIG_CRIS_LOW_MAP
         ; kseg mappings, temporary map of 0xc0->0x40
-        move.d    IO_FIELD (R_MMU_KBASE_HI, base_c, 4)          \
+        move.d    IO_FIELD (R_MMU_KBASE_HI, base_c, 4)          \
                 | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb)        \
                 | IO_FIELD (R_MMU_KBASE_HI, base_9, 9)          \
                 | IO_FIELD (R_MMU_KBASE_HI, base_8, 8), $r0
         move.d  $r0, [R_MMU_KBASE_HI]
 
-        ; temporary map of 0x40->0x40 and 0x60->0x40 
-        move.d    IO_FIELD (R_MMU_KBASE_LO, base_6, 4)          \
+        ; temporary map of 0x40->0x40 and 0x60->0x40
+        move.d    IO_FIELD (R_MMU_KBASE_LO, base_6, 4)          \
                 | IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
         move.d  $r0, [R_MMU_KBASE_LO]
 
         ; mmu enable, segs e,c,b,a,6,5,4,0 segment mapped
-        move.d    IO_STATE (R_MMU_CONFIG, mmu_enable, enable)   \
+        move.d    IO_STATE (R_MMU_CONFIG, mmu_enable, enable)   \
                 | IO_STATE (R_MMU_CONFIG, inv_excp, enable)     \
                 | IO_STATE (R_MMU_CONFIG, acc_excp, enable)     \
                 | IO_STATE (R_MMU_CONFIG, we_excp, enable)      \
@@ -93,17 +91,17 @@
         move.d  $r0, [R_MMU_CONFIG]
 #else
         ; kseg mappings
-        move.d    IO_FIELD (R_MMU_KBASE_HI, base_e, 8)          \
+        move.d    IO_FIELD (R_MMU_KBASE_HI, base_e, 8)          \
                 | IO_FIELD (R_MMU_KBASE_HI, base_c, 4)          \
                 | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb), $r0
         move.d  $r0, [R_MMU_KBASE_HI]
 
-        ; temporary map of 0x40->0x40 and 0x00->0x00 
+        ; temporary map of 0x40->0x40 and 0x00->0x00
         move.d    IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
         move.d  $r0, [R_MMU_KBASE_LO]
 
         ; mmu enable, segs f,e,c,b,4,0 segment mapped
-        move.d    IO_STATE (R_MMU_CONFIG, mmu_enable, enable)   \
+        move.d    IO_STATE (R_MMU_CONFIG, mmu_enable, enable)   \
                 | IO_STATE (R_MMU_CONFIG, inv_excp, enable)     \
                 | IO_STATE (R_MMU_CONFIG, acc_excp, enable)     \
                 | IO_STATE (R_MMU_CONFIG, we_excp, enable)      \
@@ -141,12 +139,12 @@
         ;;
         ;; In both cases, we start in un-cached mode, and need to jump into a
         ;; cached PC after we're done fiddling around with the segments.
-        ;; 
+        ;;
         ;; arch/etrax100/etrax100.ld sets some symbols that define the start
         ;; and end of each segment.
 
         ;; Check if we start from DRAM or FLASH by testing PC
-        
+
         move.d  $pc,$r0
         and.d   0x7fffffff,$r0  ; get rid of the non-cache bit
         cmp.d   0x10000,$r0     ; arbitrary... just something above this code
@@ -163,30 +161,28 @@ _inflash0:
         ;; after init.
         .section ".init.text", "ax"
 _inflash:
-#ifdef CONFIG_ETRAX_ETHERNET    
+#ifdef CONFIG_ETRAX_ETHERNET
         ;; Start MII clock to make sure it is running when tranceiver is reset
         move.d START_ETHERNET_CLOCK, $r0
         move.d $r0, [R_NETWORK_GEN_CONFIG]
 #endif
 
         ;; Set up waitstates etc according to kernel configuration.
-#ifndef CONFIG_SVINTO_SIM
         move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
         move.d   $r0, [R_WAITSTATES]
 
         move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
         move.d   $r0, [R_BUS_CONFIG]
-#endif
 
         ;; We need to initialze DRAM registers before we start using the DRAM
 
         cmp.d   RAM_INIT_MAGIC, $r8     ; Already initialized?
         beq     _dram_init_finished
         nop
-        
+
 #include "../lib/dram_init.S"
 
-_dram_init_finished:            
+_dram_init_finished:
         ;; Copy text+data to DRAM
         ;; This is fragile - the calculation of r4 as the image size depends
         ;; on that the labels below actually are the first and last positions
@@ -198,7 +194,7 @@ _dram_init_finished:
         ;; between the physical start of the flash and the flash-image start,
         ;; and when run with compression, the kernel is actually unpacked to
         ;; DRAM and we never get here in the first place :))
-        
+
         moveq   0, $r0                  ; source
         move.d  text_start, $r1         ; destination
         move.d  __vmlinux_end, $r2      ; end destination
@@ -229,10 +225,10 @@ _dram_init_finished:
         add.d   0xf0000000, $r4 ; add flash start in virtual memory (cached)
 #endif
         move.d  $r4, [romfs_start]
-1:      
+1:
         moveq   1, $r0
         move.d  $r0, [romfs_in_flash]
-                
+
         jump    _start_it       ; enter code, cached this time
 
 _inram:
@@ -241,7 +237,7 @@ _inram:
 
         moveq   0, $r0
         move.d  $r0, [romfs_length] ; default if there is no cramfs
-        
+
         ;; The kernel could have been unpacked to DRAM by the loader, but
         ;; the cramfs image could still be in the Flash directly after the
         ;; compressed kernel image. The loader passes the address of the
@@ -251,7 +247,7 @@ _inram:
         ;; (Notice that if this is not booted from the loader, r9 will be
         ;;  garbage but we do sanity checks on it, the chance that it points
         ;;  to a cramfs magic is small.. )
-        
+
         cmp.d   0x0ffffff8, $r9
         bhs     _no_romfs_in_flash      ; r9 points outside the flash area
         nop
@@ -274,7 +270,7 @@ _inram:
         jump    _start_it       ; enter code, cached this time
 
 _no_romfs_in_flash:
-        
+
         ;; Check if there is a cramfs (magic value).
         ;; Notice that we check for cramfs magic value - which is
         ;; the "rom fs" we'll possibly use in 2.4 if not JFFS (which does
@@ -286,8 +282,8 @@ _no_romfs_in_flash:
         bne     2f
         nop
 
-        ;; Ok. What is its size ? 
-        
+        ;; Ok. What is its size ?
+
         move.d  [$r0 + 4], $r2  ; cramfs_super.size (again, no need to swapwb)
 
         ;; We want to copy it to the end of the BSS
@@ -303,7 +299,7 @@ _no_romfs_in_flash:
 
         add.d   $r2, $r0
         add.d   $r2, $r1
-                
+
         ;; Go ahead. Make my loop.
 
         lsrq    1, $r2          ; size is in bytes, we copy words
@@ -314,14 +310,14 @@ _no_romfs_in_flash:
         bne     1b
         nop
 
-2:              
+2:
         ;; Dont worry that the BSS is tainted. It will be cleared later.
 
         moveq   0, $r0
         move.d  $r0, [romfs_in_flash]
 
         jump    _start_it       ; better skip the additional cramfs check below
-        
+
 _start_it:
 
         ;; Check if kernel command line is supplied
@@ -348,7 +344,7 @@ no_command_line:
         move.d  ibr_start,$r0   ; this symbol is set by the linker script 
         move    $r0,$ibr
         move.d  $r0,[etrax_irv] ; set the interrupt base register and pointer
-        
+
         ;; Clear BSS region, from _bss_start to _end
 
         move.d  __bss_start, $r0
@@ -357,7 +353,7 @@ no_command_line:
         cmp.d   $r1, $r0
         blo     1b
         nop
-        
+
 #ifdef CONFIG_BLK_DEV_ETRAXIDE
         ;; disable ATA before enabling it in genconfig below
         moveq   0,$r0
@@ -380,7 +376,7 @@ no_command_line:
 
 #ifdef CONFIG_JULIETTE
         ;; configure external DMA channel 0 before enabling it in genconfig
-        
+
         moveq   0,$r0
         move.d  $r0,[R_EXT_DMA_0_ADDR]
         ; cnt enable, word size, output, stop, size 0
@@ -395,7 +391,7 @@ no_command_line:
         move.d  $r0,[R_EXT_DMA_0_CMD]
 
         ;; reset dma4 and wait for completion
-        
+
         moveq   IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
         move.b  $r0,[R_DMA_CH4_CMD]
 1:      move.b  [R_DMA_CH4_CMD],$r0
@@ -405,7 +401,7 @@ no_command_line:
         nop
 
         ;; reset dma5 and wait for completion
-        
+
         moveq   IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
         move.b  $r0,[R_DMA_CH5_CMD]
 1:      move.b  [R_DMA_CH5_CMD],$r0
@@ -413,8 +409,8 @@ no_command_line:
         cmp.b   IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
         beq     1b
         nop
-#endif  
-                        
+#endif
+
         ;; Etrax product HW genconfig setup
 
         moveq   0,$r0
@@ -468,7 +464,6 @@ no_command_line:
 
         move.d  $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
 
-#ifndef CONFIG_SVINTO_SIM
         move.d  $r0,[R_GEN_CONFIG]
 
 #if 0
@@ -486,7 +481,7 @@ no_command_line:
         beq     1b
         nop
 #endif
-        
+
         moveq   IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
         move.b  $r0,[R_DMA_CH8_CMD]     ; reset (ser1 dma out)
         move.b  $r0,[R_DMA_CH9_CMD]     ; reset (ser1 dma in)
@@ -503,7 +498,7 @@ no_command_line:
 
         ;; setup port PA and PB default initial directions and data
         ;; including their shadow registers
-                
+
         move.b  CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
 #if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
         or.b    IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
@@ -520,7 +515,7 @@ no_command_line:
 #endif
         move.b  $r0,[port_pa_data_shadow]
         move.b  $r0,[R_PORT_PA_DATA]
-        
+
         move.b  CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0
         move.b  $r0,[port_pb_config_shadow]
         move.b  $r0,[R_PORT_PB_CONFIG]
@@ -562,13 +557,13 @@ no_command_line:
 #endif
         move.d  $r0,[port_g_data_shadow]
         move.d  $r0,[R_PORT_G_DATA]
-        
+
         ;; setup the serial port 0 at 115200 baud for debug purposes
-        
+
         moveq     IO_STATE (R_SERIAL0_XOFF, tx_stop, enable)            \
                 | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable)         \
                 | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0
-        move.d  $r0,[R_SERIAL0_XOFF] 
+        move.d  $r0,[R_SERIAL0_XOFF]
 
         ; 115.2kbaud for both transmit and receive
         move.b    IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz)          \
@@ -584,8 +579,8 @@ no_command_line:
                 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even)          \
                 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable)    \
                 | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
-        move.b  $r0,[R_SERIAL0_REC_CTRL] 
-        
+        move.b  $r0,[R_SERIAL0_REC_CTRL]
+
         ; Set up and enable the serial0 transmitter.
         move.b    IO_FIELD (R_SERIAL0_TR_CTRL, txd, 0)                  \
                 | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable)       \
@@ -598,11 +593,11 @@ no_command_line:
         move.b  $r0,[R_SERIAL0_TR_CTRL]
 
         ;; setup the serial port 1 at 115200 baud for debug purposes
-        
+
         moveq     IO_STATE (R_SERIAL1_XOFF, tx_stop, enable)            \
                 | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable)         \
                 | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0
-        move.d  $r0,[R_SERIAL1_XOFF] 
+        move.d  $r0,[R_SERIAL1_XOFF]
 
         ; 115.2kbaud for both transmit and receive
         move.b    IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz)          \
@@ -618,8 +613,8 @@ no_command_line:
                 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even)          \
                 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable)    \
                 | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
-        move.b  $r0,[R_SERIAL1_REC_CTRL] 
-        
+        move.b  $r0,[R_SERIAL1_REC_CTRL]
+
         ; Set up and enable the serial1 transmitter.
         move.b    IO_FIELD (R_SERIAL1_TR_CTRL, txd, 0)                  \
                 | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable)       \
@@ -666,14 +661,14 @@ no_command_line:
                 | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
         move.b  $r0,[R_SERIAL2_TR_CTRL]
 #endif
-        
-#ifdef CONFIG_ETRAX_SERIAL_PORT3        
+
+#ifdef CONFIG_ETRAX_SERIAL_PORT3
         ;; setup the serial port 3 at 115200 baud for debug purposes
-        
+
         moveq     IO_STATE (R_SERIAL3_XOFF, tx_stop, enable)            \
                 | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable)         \
                 | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0
-        move.d  $r0,[R_SERIAL3_XOFF] 
+        move.d  $r0,[R_SERIAL3_XOFF]
 
         ; 115.2kbaud for both transmit and receive
         move.b    IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz)          \
@@ -689,8 +684,8 @@ no_command_line:
                 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even)          \
                 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable)    \
                 | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
-        move.b  $r0,[R_SERIAL3_REC_CTRL] 
-        
+        move.b  $r0,[R_SERIAL3_REC_CTRL]
+
         ; Set up and enable the serial3 transmitter.
         move.b    IO_FIELD (R_SERIAL3_TR_CTRL, txd, 0)                  \
                 | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable)       \
@@ -702,13 +697,11 @@ no_command_line:
                 | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0
         move.b  $r0,[R_SERIAL3_TR_CTRL]
 #endif
-        
-#endif /* CONFIG_SVINTO_SIM */
 
         jump    start_kernel    ; jump into the C-function start_kernel in init/main.c
-                
+
         .data
-etrax_irv:      
+etrax_irv:
         .dword  0
 romfs_start:
         .dword  0
@@ -716,13 +709,13 @@ romfs_length:
         .dword  0
 romfs_in_flash:
         .dword  0
-        
+
         ;; put some special pages at the beginning of the kernel aligned
         ;; to page boundaries - the kernel cannot start until after this
 
 #ifdef CONFIG_CRIS_LOW_MAP
 swapper_pg_dir = 0x60002000
-#else   
+#else
 swapper_pg_dir = 0xc0002000
 #endif
 
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
index ba0e5965d6e3..09cae80a834a 100644
--- a/arch/cris/arch-v10/kernel/irq.c
+++ b/arch/cris/arch-v10/kernel/irq.c
@@ -5,7 +5,7 @@
  *
  *      Authors: Bjorn Wesen (bjornw@axis.com)
  *
- *      This file contains the interrupt vectors and some 
+ *      This file contains the interrupt vectors and some
  *      helper functions
  *
  */
@@ -182,19 +182,14 @@ void do_multiple_IRQ(struct pt_regs* regs)
    setting the irq vector table.
 */
 
-void __init
-init_IRQ(void)
+void __init init_IRQ(void)
 {
         int i;
 
         /* clear all interrupt masks */
-
-#ifndef CONFIG_SVINTO_SIM
         *R_IRQ_MASK0_CLR = 0xffffffff;
         *R_IRQ_MASK1_CLR = 0xffffffff;
         *R_IRQ_MASK2_CLR = 0xffffffff;
-#endif
-
         *R_VECT_MASK_CLR = 0xffffffff;
 
         for (i = 0; i < 256; i++)
@@ -211,25 +206,20 @@ init_IRQ(void)
            executed by the associated break handler, rather than just a jump
            address. therefore we need to setup a default breakpoint handler
            for all breakpoints */
-
         for (i = 0; i < 16; i++)
                 set_break_vector(i, do_sigtrap);
-        
-        /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
 
+        /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
         set_int_vector(15, multiple_interrupt);
-        
-        /* 0 and 1 which are special breakpoint/NMI traps */
 
+        /* 0 and 1 which are special breakpoint/NMI traps */
         set_int_vector(0, hwbreakpoint);
         set_int_vector(1, IRQ1_interrupt);
 
         /* and irq 14 which is the mmu bus fault handler */
-
         set_int_vector(14, mmu_bus_fault);
 
         /* setup the system-call trap, which is reached by BREAK 13 */
-
         set_break_vector(13, system_call);
 
         /* setup a breakpoint handler for debugging used for both user and
diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c
index 753e9a03cf87..02b783457be0 100644
--- a/arch/cris/arch-v10/kernel/process.c
+++ b/arch/cris/arch-v10/kernel/process.c
@@ -56,14 +56,14 @@ void hard_reset_now (void)
          * code to know about it than the watchdog handler in entry.S and
          * this code, implementing hard reset through the watchdog.
          */
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_WATCHDOG)
         extern int cause_of_death;
 #endif
 
         printk("*** HARD RESET ***\n");
         local_irq_disable();
 
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_WATCHDOG)
         cause_of_death = 0xbedead;
 #else
         /* Since we dont plan to keep on resetting the watchdog,
diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c
index fce7c541d70d..b5eb5cd2f60b 100644
--- a/arch/cris/arch-v10/kernel/time.c
+++ b/arch/cris/arch-v10/kernel/time.c
@@ -14,7 +14,6 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/mm.h>
-#include <arch/svinto.h>
 #include <asm/types.h>
 #include <asm/signal.h>
 #include <asm/io.h>
@@ -34,7 +33,7 @@ unsigned long get_ns_in_jiffie(void)
 
         local_irq_save(flags);
         timer_count = *R_TIMER0_DATA;
-        presc_count = *R_TIM_PRESC_STATUS;  
+        presc_count = *R_TIM_PRESC_STATUS;
         /* presc_count might be wrapped */
         t1 = *R_TIMER0_DATA;
 
@@ -50,7 +49,7 @@ unsigned long get_ns_in_jiffie(void)
                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
         }
 
-        ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 
+        ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
              ( (presc_count) * (1000000000/PRESCALE_FREQ));
         return ns;
 }
@@ -80,7 +79,7 @@ static u32 cris_v10_gettimeoffset(void)
  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
  * described in the table below:
- * 
+ *
  *   Watchdog    Value written:
  *   state:      To enable:  To key:      Operation:
  *   --------    ----------  -------      ----------
@@ -89,15 +88,15 @@ static u32 cris_v10_gettimeoffset(void)
  *   started         0       ~key         Stop watchdog
  *   started         1       ~key         Restart watchdog with key = ~key.
  *   started         X       new_key_val  Change key to new_key_val.
- * 
+ *
  * Note: '~' is the bitwise NOT operator.
- * 
+ *
  */
 
 /* right now, starting the watchdog is the same as resetting it */
 #define start_watchdog reset_watchdog
 
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#ifdef CONFIG_ETRAX_WATCHDOG
 static int watchdog_key = 0;  /* arbitrary number */
 #endif
 
@@ -107,10 +106,9 @@ static int watchdog_key = 0;  /* arbitrary number */
 
 #define WATCHDOG_MIN_FREE_PAGES 8
 
-void
-reset_watchdog(void)
+void reset_watchdog(void)
 {
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_WATCHDOG)
         /* only keep watchdog happy as long as we have memory left! */
         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
                 /* reset the watchdog with the inverse of the old key */
@@ -123,28 +121,23 @@ reset_watchdog(void)
 
 /* stop the watchdog - we still need the correct key */
 
-void 
-stop_watchdog(void)
+void stop_watchdog(void)
 {
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#ifdef CONFIG_ETRAX_WATCHDOG
         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
                 IO_STATE(R_WATCHDOG, enable, stop);
-#endif  
+#endif
 }
 
 
+extern void cris_do_profile(struct pt_regs *regs);
+
 /*
  * timer_interrupt() needs to keep up the real-time clock,
  * as well as call the "xtime_update()" routine every clocktick
  */
-
-//static unsigned short myjiff; /* used by our debug routine print_timestamp */
-
-extern void cris_do_profile(struct pt_regs *regs);
-
-static inline irqreturn_t
-timer_interrupt(int irq, void *dev_id)
+static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
         struct pt_regs *regs = get_irq_regs();
         /* acknowledge the timer irq */
@@ -160,44 +153,39 @@ timer_interrupt(int irq, void *dev_id)
                 IO_STATE( R_TIMER_CTRL, tm0, run) |
                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 #else
-        *R_TIMER_CTRL = r_timer_ctrl_shadow | 
-                IO_STATE(R_TIMER_CTRL, i0, clr);
+        *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
 #endif
 
         /* reset watchdog otherwise it resets us! */
         reset_watchdog();
-        
+
         /* Update statistics. */
         update_process_times(user_mode(regs));
 
         /* call the real timer interrupt handler */
-
         xtime_update(1);
-        
+
         cris_do_profile(regs); /* Save profiling information */
         return IRQ_HANDLED;
 }
 
-/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
- * it needs to be IRQF_DISABLED to make the jiffies update work properly
- */
+/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
 
 static struct irqaction irq2  = {
         .handler = timer_interrupt,
-        .flags = IRQF_SHARED | IRQF_DISABLED,
+        .flags = IRQF_SHARED,
         .name = "timer",
 };
 
-void __init
-time_init(void)
-{       
+void __init time_init(void)
+{
         arch_gettimeoffset = cris_v10_gettimeoffset;
 
-        /* probe for the RTC and read it if it exists 
-         * Before the RTC can be probed the loops_per_usec variable needs 
-         * to be initialized to make usleep work. A better value for 
-         * loops_per_usec is calculated by the kernel later once the 
-         * clock has started.  
+        /* probe for the RTC and read it if it exists
+         * Before the RTC can be probed the loops_per_usec variable needs
+         * to be initialized to make usleep work. A better value for
+         * loops_per_usec is calculated by the kernel later once the
+         * clock has started.
          */
         loops_per_usec = 50;
 
@@ -208,7 +196,7 @@ time_init(void)
          * Remember that linux/timex.h contains #defines that rely on the
          * timer settings below (hz and divide factor) !!!
          */
-        
+
 #ifdef USE_CASCADE_TIMERS
         *R_TIMER_CTRL =
                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
@@ -219,8 +207,8 @@ time_init(void)
                 IO_STATE( R_TIMER_CTRL, i0, nop) |
                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-        
-        *R_TIMER_CTRL = r_timer_ctrl_shadow = 
+
+        *R_TIMER_CTRL = r_timer_ctrl_shadow =
                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
                 IO_STATE( R_TIMER_CTRL, i1, nop) |
@@ -230,18 +218,18 @@ time_init(void)
                 IO_STATE( R_TIMER_CTRL, tm0, run) |
                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 #else
-        *R_TIMER_CTRL = 
-                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
+        *R_TIMER_CTRL =
+                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
-                IO_STATE(R_TIMER_CTRL, i1,        nop)      | 
+                IO_STATE(R_TIMER_CTRL, i1,        nop)      |
                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
-        
+
         *R_TIMER_CTRL = r_timer_ctrl_shadow =
-                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
+                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
@@ -253,16 +241,14 @@ time_init(void)
         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 #endif
 
-        *R_IRQ_MASK0_SET =
-                IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
-        
-        /* now actually register the timer irq handler that calls timer_interrupt() */
-        
+        /* unmask the timer irq */
+        *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
+
+        /* now actually register the irq handler that calls timer_interrupt() */
         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 
         /* enable watchdog if we should use one */
-
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_WATCHDOG)
         printk("Enabling watchdog...\n");
         start_watchdog();
 
@@ -275,9 +261,7 @@ time_init(void)
            driver or infrastructure support yet.  */
         asm ("setf m");
 
-        *R_IRQ_MASK0_SET =
-                IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
-        *R_VECT_MASK_SET =
-                IO_STATE(R_VECT_MASK_SET, nmi, set);
+        *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
+        *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
 #endif
 }
diff --git a/arch/cris/arch-v10/lib/dram_init.S b/arch/cris/arch-v10/lib/dram_init.S
index b9190ff7d0a4..e541d3d8f922 100644
--- a/arch/cris/arch-v10/lib/dram_init.S
+++ b/arch/cris/arch-v10/lib/dram_init.S
@@ -5,9 +5,7 @@
  * Note: This file may not modify r9 because r9 is used to carry
  *       information from the decompresser to the kernel
  *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors:  Mikael Starvik (starvik@axis.com)
+ * Copyright (C) 2000-2012 Axis Communications AB
  *
  */
 
@@ -18,16 +16,15 @@
 
 
         ;; WARNING! The registers r8 and r9 are used as parameters carrying
-        ;; information from the decompressor (if the kernel was compressed). 
+        ;; information from the decompressor (if the kernel was compressed).
         ;; They should not be used in the code below.
 
-#ifndef CONFIG_SVINTO_SIM       
         move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
         move.d   $r0, [R_WAITSTATES]
 
         move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
         move.d   $r0, [R_BUS_CONFIG]
-        
+
 #ifndef CONFIG_ETRAX_SDRAM
         move.d   CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
         move.d   $r0, [R_DRAM_CONFIG]
@@ -38,14 +35,14 @@
         ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
         moveq    2, $r6 
 _sdram_init:
-        
+
         ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
-        
+
         ; Bank configuration
         move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
         move.d   $r0, [R_SDRAM_CONFIG]
 
-        ; Calculate value of mrs_data 
+        ; Calculate value of mrs_data
         ; CAS latency = 2 && bus_width = 32 => 0x40
         ; CAS latency = 3 && bus_width = 32 => 0x60
         ; CAS latency = 2 && bus_width = 16 => 0x20
@@ -56,22 +53,22 @@ _sdram_init:
         and.d    0x00ff0000, $r2
         bne      _set_timing
         lsrq     16, $r2
-        
+
         move.d   0x40, $r2       ; Assume 32 bits and CAS latency = 2
         move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
         move.d   $r1, $r3
-        and.d    0x03, $r1       ; Get CAS latency
+        and.d    0x03, $r1       ; Get CAS latency
         and.d    0x1000, $r3     ; 50 or 100 MHz?
         beq      _speed_50
         nop
-_speed_100:             
+_speed_100:
         cmp.d    0x00, $r1      ; CAS latency = 2?
         beq      _bw_check
         nop
-        or.d     0x20, $r2      ; CAS latency = 3 
+        or.d     0x20, $r2      ; CAS latency = 3
         ba       _bw_check
         nop
-_speed_50:                      
+_speed_50:
         cmp.d    0x01, $r1      ; CAS latency = 2?
         beq      _bw_check
         nop
@@ -86,19 +83,19 @@ _bw_check:
         ; Set timing parameters. Starts master clock
 _set_timing:
         move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
-        and.d    0x8000f9ff, $r1 ; Make sure mrs data and command is 0 
+        and.d    0x8000f9ff, $r1 ; Make sure mrs data and command is 0
         or.d     0x80000000, $r1        ; Make sure sdram enable bit is set
         move.d   $r1, $r5
         or.d     0x0000c000, $r1 ; ref = disable
         lslq     16, $r2                ; mrs data starts at bit 16
-        or.d     $r2, $r1 
-        move.d   $r1, [R_SDRAM_TIMING]  
-                
+        or.d     $r2, $r1
+        move.d   $r1, [R_SDRAM_TIMING]
+
         ; Wait 200us
         move.d   10000, $r2
 1:      bne      1b
         subq     1, $r2
-        
+
         ; Issue initialization command sequence
         move.d   _sdram_commands_start, $r2
         and.d    0x000fffff, $r2 ; Make sure commands are read from flash
@@ -144,7 +141,6 @@ _sdram_commands_start:
         .byte   2       ; refresh
         .byte   0       ; nop
         .byte   1       ; mrs
-        .byte   0       ; nop 
-_sdram_commands_end:            
-#endif
+        .byte   0       ; nop
+_sdram_commands_end:
 #endif
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
index 1b6ad6247204..28dd77144e8f 100644
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ b/arch/cris/arch-v32/drivers/axisflashmap.c
@@ -24,8 +24,6 @@
 #include <linux/mtd/mtdram.h>
 #include <linux/mtd/partitions.h>
 
-#include <linux/cramfs_fs.h>
-
 #include <asm/axisflashmap.h>
 #include <asm/mmu.h>
 
diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
index 0b86deedacb9..74f9fe80940c 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c
+++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
@@ -978,7 +978,7 @@ static int __init gpio_init(void)
         CRIS_LED_DISK_WRITE(0);
 
         int res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
-                IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist);
+                IRQF_SHARED, "gpio", &alarmlist);
         if (res2) {
                 printk(KERN_ERR "err: irq for gpio\n");
                 return res2;
diff --git a/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/arch/cris/arch-v32/drivers/mach-fs/gpio.c
index a2ac0917f1a6..9e54273af0ca 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/gpio.c
+++ b/arch/cris/arch-v32/drivers/mach-fs/gpio.c
@@ -964,11 +964,11 @@ gpio_init(void)
          * in some tests.
          */
         if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
-                        IRQF_SHARED | IRQF_DISABLED, "gpio poll", &alarmlist))
+                        IRQF_SHARED, "gpio poll", &alarmlist))
                 printk(KERN_ERR "timer0 irq for gpio\n");
 
         if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
-                        IRQF_SHARED | IRQF_DISABLED, "gpio PA", &alarmlist))
+                        IRQF_SHARED, "gpio PA", &alarmlist))
                 printk(KERN_ERR "PA irq for gpio\n");
 
 #ifdef CONFIG_ETRAX_VIRTUAL_GPIO
diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c
index 219f704e3221..bbb806b68838 100644
--- a/arch/cris/arch-v32/drivers/sync_serial.c
+++ b/arch/cris/arch-v32/drivers/sync_serial.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/timer.h>
 #include <linux/spinlock.h>
+#include <linux/wait.h>
 
 #include <asm/io.h>
 #include <dma.h>
@@ -1144,7 +1145,8 @@ static ssize_t sync_serial_read(struct file * file, char * buf,
                 if (file->f_flags & O_NONBLOCK)
                         return -EAGAIN;
 
-                interruptible_sleep_on(&port->in_wait_q);
+                wait_event_interruptible(port->in_wait_q,
+                                         !(start == end && !port->full));
                 if (signal_pending(current))
                         return -EINTR;
 
diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S
index faa644111feb..2f19ac6217aa 100644
--- a/arch/cris/arch-v32/kernel/entry.S
+++ b/arch/cris/arch-v32/kernel/entry.S
@@ -424,7 +424,7 @@ nmi_interrupt:
         bpl     1f
         nop
         jsr     handle_watchdog_bite    ; In time.c.
-        move.d  $sp, $r10               ; Pointer to registers
+        move.d  $sp, $r10               ; Pointer to registers
 1:      btstq   REG_BIT(intr_vect, r_nmi, ext), $r0
         bpl     1f
         nop
@@ -452,7 +452,7 @@ spurious_interrupt:
         nop
 
         ;; This handles the case when multiple interrupts arrive at the same
-        ;; time. Jump to the first set interrupt bit in a priotiry fashion. The
+        ;; time. Jump to the first set interrupt bit in a priority fashion. The
         ;; hardware will call the unserved interrupts after the handler
         ;; finishes.
         .type   multiple_interrupt, @function
@@ -885,13 +885,29 @@ sys_call_table:
         .long sys_preadv
         .long sys_pwritev
         .long sys_setns                 /* 335 */
-
-        /*
-         * NOTE!! This doesn't have to be exact - we just have
-         * to make sure we have _enough_ of the "sys_ni_syscall"
-         * entries. Don't panic if you notice that this hasn't
-         * been shrunk every time we add a new system call.
-         */
+        .long sys_name_to_handle_at
+        .long sys_open_by_handle_at
+        .long sys_rt_tgsigqueueinfo
+        .long sys_perf_event_open
+        .long sys_recvmmsg              /* 340 */
+        .long sys_accept4
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
+        .long sys_clock_adjtime         /* 345 */
+        .long sys_syncfs
+        .long sys_sendmmsg
+        .long sys_process_vm_readv
+        .long sys_process_vm_writev
+        .long sys_kcmp                  /* 350 */
+        .long sys_finit_module
+
+        /*
+         * NOTE!! This doesn't have to be exact - we just have
+         * to make sure we have _enough_ of the "sys_ni_syscall"
+         * entries. Don't panic if you notice that this hasn't
+         * been shrunk every time we add a new system call.
+         */
 
         .rept NR_syscalls - (.-sys_call_table) / 4
                 .long sys_ni_syscall
diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c
index f6644535b17e..b130c2c5fdd8 100644
--- a/arch/cris/arch-v32/kernel/fasttimer.c
+++ b/arch/cris/arch-v32/kernel/fasttimer.c
@@ -786,7 +786,7 @@ int fast_timer_init(void)
     proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
 #endif /* PROC_FS */
                 if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt,
-                                IRQF_SHARED | IRQF_DISABLED,
+                                IRQF_SHARED,
                                 "fast timer int", &fast_timer_list))
                         printk(KERN_ERR "err: fasttimer irq\n");
     fast_timer_is_init = 1;
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 5ebe6e841820..25437ae28128 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -331,11 +331,11 @@ extern void do_IRQ(int irq, struct pt_regs * regs);
 void
 crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
 {
-        /* Interrupts that may not be moved to another CPU and
-         * are IRQF_DISABLED may skip blocking. This is currently
-         * only valid for the timer IRQ and the IPI and is used
-         * for the timer interrupt to avoid watchdog starvation.
-         */
+        /* Interrupts that may not be moved to another CPU may
+         * skip blocking. This is currently only valid for the
+         * timer IRQ and the IPI and is used for the timer
+         * interrupt to avoid watchdog starvation.
+         */
         if (!block) {
                 do_IRQ(irq, regs);
                 return;
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index fe8e6039db2a..0698582467ca 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -64,7 +64,7 @@ static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
 static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
 static struct irqaction irq_ipi  = {
         .handler = crisv32_ipi_interrupt,
-        .flags = IRQF_DISABLED,
+        .flags = 0,
         .name = "ipi",
 };
 
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index 8c4b45efd7b6..ee66866538f8 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -216,12 +216,10 @@ static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
- * It needs to be IRQF_DISABLED to make the jiffies update work properly.
- */
+/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
 static struct irqaction irq_timer = {
         .handler = timer_interrupt,
-        .flags = IRQF_SHARED | IRQF_DISABLED,
+        .flags = IRQF_SHARED,
         .name = "timer"
 };
 
diff --git a/arch/cris/arch-v32/mach-a3/arbiter.c b/arch/cris/arch-v32/mach-a3/arbiter.c
index 15f5c9de2639..ab5c421a4de8 100644
--- a/arch/cris/arch-v32/mach-a3/arbiter.c
+++ b/arch/cris/arch-v32/mach-a3/arbiter.c
@@ -256,11 +256,11 @@ static void crisv32_arbiter_init(void)
         crisv32_arbiter_config(1, EXT_REGION, 0);
 
         if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
-                        IRQF_DISABLED, "arbiter", NULL))
+                        0, "arbiter", NULL))
                 printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
 
         if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
-                        IRQF_DISABLED, "arbiter", NULL))
+                        0, "arbiter", NULL))
                 printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
 
 #ifndef CONFIG_ETRAX_KGDB
diff --git a/arch/cris/arch-v32/mach-fs/arbiter.c b/arch/cris/arch-v32/mach-fs/arbiter.c
index 3f8ebb5c1477..c97f4d8120f9 100644
--- a/arch/cris/arch-v32/mach-fs/arbiter.c
+++ b/arch/cris/arch-v32/mach-fs/arbiter.c
@@ -184,7 +184,7 @@ static void crisv32_arbiter_init(void)
         crisv32_arbiter_config(EXT_REGION, 0);
         crisv32_arbiter_config(INT_REGION, 0);
 
-        if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED,
+        if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, 0,
                         "arbiter", NULL))
                 printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
 
diff --git a/arch/cris/boot/rescue/kimagerescue.S b/arch/cris/boot/rescue/kimagerescue.S
index 6f7b3e61260b..655b511fecf3 100644
--- a/arch/cris/boot/rescue/kimagerescue.S
+++ b/arch/cris/boot/rescue/kimagerescue.S
@@ -50,7 +50,6 @@
 
         nop
         di
-#ifndef CONFIG_SVINTO_SIM
         ;; setup port PA and PB default initial directions and data
         ;; (so we can flash LEDs, and so that DTR and others are set)
 
@@ -67,7 +66,6 @@
         ;; We need to setup the bus registers before we start using the DRAM
 #include "../../lib/dram_init.S"
 
-#endif
         ;; Setup the stack to a suitably high address.
         ;; We assume 8 MB is the minimum DRAM in an eLinux
         ;; product and put the sp at the top for now.
diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h
index f627ad0b8a3d..4a724172877f 100644
--- a/arch/cris/include/arch-v10/arch/io.h
+++ b/arch/cris/include/arch-v10/arch/io.h
@@ -1,8 +1,6 @@
 #ifndef _ASM_ARCH_CRIS_IO_H
 #define _ASM_ARCH_CRIS_IO_H
 
-#include <arch/svinto.h>
-
 /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
 
 extern unsigned long gen_config_ii_shadow;
@@ -34,7 +32,7 @@ extern volatile unsigned long *port_csp4_addr;
 
 /* The LED's on various Etrax-based products are set differently. */
 
-#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM)
+#if defined(CONFIG_ETRAX_NO_LEDS)
 #undef CONFIG_ETRAX_PA_LEDS
 #undef CONFIG_ETRAX_PB_LEDS
 #undef CONFIG_ETRAX_CSP0_LEDS
@@ -171,29 +169,4 @@ extern volatile unsigned long *port_csp4_addr;
 #define SOFT_SHUTDOWN()
 #endif
 
-/* Console I/O for simulated etrax100.  Use #ifdef so erroneous
-   use will be evident. */
-#ifdef CONFIG_SVINTO_SIM
-  /* Let's use the ucsim interface since it lets us do write(2, ...) */
-#define SIMCOUT(s,len)                                                  \
-  asm ("moveq 4,$r9     \n\t"                                           \
-       "moveq 2,$r10    \n\t"                                           \
-       "move.d %0,$r11  \n\t"                                           \
-       "move.d %1,$r12  \n\t"                                           \
-       "push $irp       \n\t"                                           \
-       "move 0f,$irp    \n\t"                                           \
-       "jump -6809      \n"                                             \
-       "0:              \n\t"                                           \
-       "pop $irp"                                                       \
-       : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory")
-#define TRACE_ON() __extension__ \
- ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \
-                               (255)); _Foofoo; })
-
-#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0)
-#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0)
-#define CRIS_CYCLES() __extension__ \
- ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;})
-#endif /* ! defined CONFIG_SVINTO_SIM */
-
 #endif
diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h
index ca2675ae08ed..6aecb835037d 100644
--- a/arch/cris/include/arch-v10/arch/irq.h
+++ b/arch/cris/include/arch-v10/arch/irq.h
@@ -141,9 +141,9 @@ __asm__ ( \
  * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
  * it here, we would not get the multiple_irq at all.
  *
- * The non-blocking here is based on the knowledge that the timer interrupt is 
- * registered as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
- * be an sti() before the timer irq handler is run to acknowledge the interrupt.
+ * The non-blocking here is based on the knowledge that the timer interrupt runs
+ * with interrupts disabled, and therefore there will not be an sti() before the
+ * timer irq handler is run to acknowledge the interrupt.
  */
 
 #define BUILD_TIMER_IRQ(nr,mask) \
diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h
index fe3cdd22bed4..0c1b4d3a34e7 100644
--- a/arch/cris/include/arch-v32/arch/irq.h
+++ b/arch/cris/include/arch-v32/arch/irq.h
@@ -102,9 +102,9 @@ __asm__ (				\
  * multiple_irq handler is run and it prioritizes the timer interrupt. However
  * if we had BLOCK'edit here, we would not get the multiple_irq at all.
  *
- * The non-blocking here is based on the knowledge that the timer interrupt is
- * registered as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
- * be an sti() before the timer irq handler is run to acknowledge the interrupt.
+ * The non-blocking here is based on the knowledge that the timer interrupt runs
+ * with interrupts disabled, and therefore there will not be an sti() before the
+ * timer irq handler is run to acknowledge the interrupt.
  */
 #define BUILD_TIMER_IRQ(nr, mask)       \
 void IRQ_NAME(nr);                      \
diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
index 199b1a9dab89..f3fd8768f095 100644
--- a/arch/cris/include/asm/Kbuild
+++ b/arch/cris/include/asm/Kbuild
@@ -6,6 +6,7 @@ header-y += arch-v32/
 generic-y += barrier.h
 generic-y += clkdev.h
 generic-y += exec.h
+generic-y += hash.h
 generic-y += kvm_para.h
 generic-y += linkage.h
 generic-y += module.h
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
index 4353cf239a13..e59dba12ce94 100644
--- a/arch/cris/include/asm/io.h
+++ b/arch/cris/include/asm/io.h
@@ -169,7 +169,11 @@ static inline void outsl(unsigned int port, const void *addr,
 }
 
 #define inb_p(port)             inb(port)
+#define inw_p(port)             inw(port)
+#define inl_p(port)             inl(port)
 #define outb_p(val, port)       outb((val), (port))
+#define outw_p(val, port)       outw((val), (port))
+#define outl_p(val, port)       outl((val), (port))
 
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
index 0ff3f6889842..5cc7d1991e48 100644
--- a/arch/cris/include/asm/unistd.h
+++ b/arch/cris/include/asm/unistd.h
@@ -4,7 +4,7 @@
 #include <uapi/asm/unistd.h>
 
 
-#define NR_syscalls 336
+#define NR_syscalls 360
 
 #include <arch/unistd.h>
 
diff --git a/arch/cris/include/uapi/asm/socket.h b/arch/cris/include/uapi/asm/socket.h
index 13829aaaeec5..ed94e5ed0a23 100644
--- a/arch/cris/include/uapi/asm/socket.h
+++ b/arch/cris/include/uapi/asm/socket.h
@@ -80,6 +80,8 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_SOCKET_H */
 
 
diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h
index 48842896f6c2..f3287face443 100644
--- a/arch/cris/include/uapi/asm/unistd.h
+++ b/arch/cris/include/uapi/asm/unistd.h
@@ -340,5 +340,21 @@
 #define __NR_preadv             333
 #define __NR_pwritev            334
 #define __NR_setns              335
+#define __NR_name_to_handle_at  336
+#define __NR_open_by_handle_at  337
+#define __NR_rt_tgsigqueueinfo 338
+#define __NR_perf_event_open    339
+#define __NR_recvmmsg           340
+#define __NR_accept4            341
+#define __NR_fanotify_init      342
+#define __NR_fanotify_mark      343
+#define __NR_prlimit64          344
+#define __NR_clock_adjtime      345
+#define __NR_syncfs             346
+#define __NR_sendmmsg           347
+#define __NR_process_vm_readv   348
+#define __NR_process_vm_writev  349
+#define __NR_kcmp               350
+#define __NR_finit_module       351
 
 #endif /* _UAPI_ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
index d36836dbbc07..dd0be5de55d5 100644
--- a/arch/cris/kernel/irq.c
+++ b/arch/cris/kernel/irq.c
@@ -40,9 +40,6 @@
 
 /* called by the assembler IRQ entry functions defined in irq.h
  * to dispatch the interrupts to registered handlers
- * interrupts are disabled upon entry - depending on if the
- * interrupt was registered with IRQF_DISABLED or not, interrupts
- * are re-enabled or not.
  */
 
 asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
diff --git a/arch/frv/Makefile b/arch/frv/Makefile
index 4d1b1e9baef1..2a8fb730d1ca 100644
--- a/arch/frv/Makefile
+++ b/arch/frv/Makefile
@@ -74,13 +74,6 @@ KBUILD_CFLAGS	+= -mno-fdpic -mgpr-32 -msoft-float -mno-media
 KBUILD_CFLAGS   += -ffixed-fcc3 -ffixed-cc3 -ffixed-gr15 -ffixed-icc2
 KBUILD_AFLAGS   += -mno-fdpic
 
-# make sure the .S files get compiled with debug info
-# and disable optimisations that are unhelpful whilst debugging
-ifdef CONFIG_DEBUG_INFO
-#KBUILD_CFLAGS  += -O1
-KBUILD_AFLAGS   += -Wa,--gdwarf2
-endif
-
 head-y          := arch/frv/kernel/head.o
 
 core-y          += arch/frv/kernel/ arch/frv/mm/
diff --git a/arch/frv/include/asm/Kbuild b/arch/frv/include/asm/Kbuild
index 74742dc6a3da..bc42f14c9c2e 100644
--- a/arch/frv/include/asm/Kbuild
+++ b/arch/frv/include/asm/Kbuild
@@ -3,3 +3,4 @@ generic-y += clkdev.h
 generic-y += exec.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/frv/include/uapi/asm/socket.h b/arch/frv/include/uapi/asm/socket.h
index 5d4299762426..ca2c6e6f31c6 100644
--- a/arch/frv/include/uapi/asm/socket.h
+++ b/arch/frv/include/uapi/asm/socket.h
@@ -78,5 +78,7 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_SOCKET_H */
 
diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
index ada843c701ef..38ca45d3df1e 100644
--- a/arch/hexagon/include/asm/Kbuild
+++ b/arch/hexagon/include/asm/Kbuild
@@ -16,6 +16,7 @@ generic-y += fb.h
 generic-y += fcntl.h
 generic-y += ftrace.h
 generic-y += hardirq.h
+generic-y += hash.h
 generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ioctls.h
diff --git a/arch/hexagon/include/asm/fixmap.h b/arch/hexagon/include/asm/fixmap.h
index b75b6bf4269c..1387f84b42b6 100644
--- a/arch/hexagon/include/asm/fixmap.h
+++ b/arch/hexagon/include/asm/fixmap.h
@@ -26,45 +26,7 @@
  */
 #include <asm/mem-layout.h>
 
-/*
- * Full fixmap support involves set_fixmap() functions, but
- * these may not be needed if all we're after is an area for
- * highmem kernel mappings.
- */
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/**
- * fix_to_virt -- "index to address" translation.
- *
- * If anyone tries to use the idx directly without translation,
- * we catch the bug with a NULL-deference kernel oops. Illegal
- * ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * This branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #define kmap_get_fixmap_pte(vaddr) \
         pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), \
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index a8c3a11dc5ab..0c8e553e0b9f 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -7,6 +7,7 @@ menu "Processor type and features"
 config IA64
         bool
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select PCI if (!IA64_HP_SIM)
         select ACPI if (!IA64_HP_SIM)
         select PM if (!IA64_HP_SIM)
@@ -104,6 +105,7 @@ config HAVE_SETUP_PER_CPU_AREA
 config DMI
         bool
         default y
+        select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
 
 config EFI
         bool
diff --git a/arch/ia64/hp/common/aml_nfw.c b/arch/ia64/hp/common/aml_nfw.c
index 916ffe770bcf..84715fcbba08 100644
--- a/arch/ia64/hp/common/aml_nfw.c
+++ b/arch/ia64/hp/common/aml_nfw.c
@@ -23,8 +23,7 @@
  */
 
 #include <linux/module.h>
-#include <acpi/acpi_bus.h>
-#include <acpi/acpi_drivers.h>
+#include <linux/acpi.h>
 #include <asm/sal.h>
 
 MODULE_AUTHOR("Bjorn Helgaas <bjorn.helgaas@hp.com>");
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index 4c530a82fc46..8e858b593e4f 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -255,7 +255,7 @@ static u64 prefetch_spill_page;
 #endif
 
 #ifdef CONFIG_PCI
-# define GET_IOC(dev)   (((dev)->bus == &pci_bus_type)                                          \
+# define GET_IOC(dev)   ((dev_is_pci(dev))                                              \
                          ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
 #else
 # define GET_IOC(dev)   NULL
diff --git a/arch/ia64/include/asm/Kbuild b/arch/ia64/include/asm/Kbuild
index f93ee087e8fe..283a83154b5e 100644
--- a/arch/ia64/include/asm/Kbuild
+++ b/arch/ia64/include/asm/Kbuild
@@ -4,4 +4,5 @@ generic-y += exec.h
 generic-y += kvm_para.h
 generic-y += trace_clock.h
 generic-y += preempt.h
-generic-y += vtime.h
\ No newline at end of file
+generic-y += vtime.h
+generic-y += hash.h
diff --git a/arch/ia64/include/asm/dmi.h b/arch/ia64/include/asm/dmi.h
index 185d3d18d0ec..f365a61f5c71 100644
--- a/arch/ia64/include/asm/dmi.h
+++ b/arch/ia64/include/asm/dmi.h
@@ -5,8 +5,10 @@
 #include <asm/io.h>
 
 /* Use normal IO mappings for DMI */
-#define dmi_ioremap ioremap
-#define dmi_iounmap(x,l) iounmap(x)
-#define dmi_alloc(l) kzalloc(l, GFP_ATOMIC)
+#define dmi_early_remap         ioremap
+#define dmi_early_unmap(x, l)   iounmap(x)
+#define dmi_remap               ioremap
+#define dmi_unmap               iounmap
+#define dmi_alloc(l)            kzalloc(l, GFP_ATOMIC)
 
 #endif
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index 5a84b3a50741..efd1b927ccb7 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -71,6 +71,7 @@
 #include <linux/compiler.h>
 #include <linux/threads.h>
 #include <linux/types.h>
+#include <linux/bitops.h>
 
 #include <asm/fpu.h>
 #include <asm/page.h>
diff --git a/arch/ia64/include/uapi/asm/socket.h b/arch/ia64/include/uapi/asm/socket.h
index c25302fb48d9..a1b49bac7951 100644
--- a/arch/ia64/include/uapi/asm/socket.h
+++ b/arch/ia64/include/uapi/asm/socket.h
@@ -87,4 +87,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_IA64_SOCKET_H */
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index bfa19311e09c..07d209c9507f 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -60,7 +60,6 @@
 
 #define PREFIX                  "ACPI: "
 
-u32 acpi_rsdt_forced;
 unsigned int acpi_cpei_override;
 unsigned int acpi_cpei_phys_cpuid;
 
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 985bf80c622e..53f44bee9ebb 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -702,7 +702,7 @@ again:
 out:
         srcu_read_unlock(&vcpu->kvm->srcu, idx);
         if (r > 0) {
-                kvm_resched(vcpu);
+                cond_resched();
                 idx = srcu_read_lock(&vcpu->kvm->srcu);
                 goto again;
         }
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index da5237d636d6..52715a71aede 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -31,74 +31,6 @@
 static unsigned long max_gap;
 #endif
 
-/**
- * show_mem - give short summary of memory stats
- *
- * Shows a simple page count of reserved and used pages in the system.
- * For discontig machines, it does this on a per-pgdat basis.
- */
-void show_mem(unsigned int filter)
-{
-        int i, total_reserved = 0;
-        int total_shared = 0, total_cached = 0;
-        unsigned long total_present = 0;
-        pg_data_t *pgdat;
-
-        printk(KERN_INFO "Mem-info:\n");
-        show_free_areas(filter);
-        printk(KERN_INFO "Node memory in pages:\n");
-        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
-                return;
-        for_each_online_pgdat(pgdat) {
-                unsigned long present;
-                unsigned long flags;
-                int shared = 0, cached = 0, reserved = 0;
-                int nid = pgdat->node_id;
-
-                if (skip_free_areas_node(filter, nid))
-                        continue;
-                pgdat_resize_lock(pgdat, &flags);
-                present = pgdat->node_present_pages;
-                for(i = 0; i < pgdat->node_spanned_pages; i++) {
-                        struct page *page;
-                        if (unlikely(i % MAX_ORDER_NR_PAGES == 0))
-                                touch_nmi_watchdog();
-                        if (pfn_valid(pgdat->node_start_pfn + i))
-                                page = pfn_to_page(pgdat->node_start_pfn + i);
-                        else {
-#ifdef CONFIG_VIRTUAL_MEM_MAP
-                                if (max_gap < LARGE_GAP)
-                                        continue;
-#endif
-                                i = vmemmap_find_next_valid_pfn(nid, i) - 1;
-                                continue;
-                        }
-                        if (PageReserved(page))
-                                reserved++;
-                        else if (PageSwapCache(page))
-                                cached++;
-                        else if (page_count(page))
-                                shared += page_count(page)-1;
-                }
-                pgdat_resize_unlock(pgdat, &flags);
-                total_present += present;
-                total_reserved += reserved;
-                total_cached += cached;
-                total_shared += shared;
-                printk(KERN_INFO "Node %4d:  RAM: %11ld, rsvd: %8d, "
-                       "shrd: %10d, swpd: %10d\n", nid,
-                       present, reserved, shared, cached);
-        }
-        printk(KERN_INFO "%ld pages of RAM\n", total_present);
-        printk(KERN_INFO "%d reserved pages\n", total_reserved);
-        printk(KERN_INFO "%d pages shared\n", total_shared);
-        printk(KERN_INFO "%d pages swap cached\n", total_cached);
-        printk(KERN_INFO "Total of %ld pages in page table cache\n",
-               quicklist_total_size());
-        printk(KERN_INFO "%ld free buffer pages\n", nr_free_buffer_pages());
-}
-
-
 /* physical address where the bootmem map is located */
 unsigned long bootmap_start;
 
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index 2de08f4d9930..878626805369 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -608,69 +608,6 @@ void *per_cpu_init(void)
 #endif /* CONFIG_SMP */
 
 /**
- * show_mem - give short summary of memory stats
- *
- * Shows a simple page count of reserved and used pages in the system.
- * For discontig machines, it does this on a per-pgdat basis.
- */
-void show_mem(unsigned int filter)
-{
-        int i, total_reserved = 0;
-        int total_shared = 0, total_cached = 0;
-        unsigned long total_present = 0;
-        pg_data_t *pgdat;
-
-        printk(KERN_INFO "Mem-info:\n");
-        show_free_areas(filter);
-        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
-                return;
-        printk(KERN_INFO "Node memory in pages:\n");
-        for_each_online_pgdat(pgdat) {
-                unsigned long present;
-                unsigned long flags;
-                int shared = 0, cached = 0, reserved = 0;
-                int nid = pgdat->node_id;
-
-                if (skip_free_areas_node(filter, nid))
-                        continue;
-                pgdat_resize_lock(pgdat, &flags);
-                present = pgdat->node_present_pages;
-                for(i = 0; i < pgdat->node_spanned_pages; i++) {
-                        struct page *page;
-                        if (unlikely(i % MAX_ORDER_NR_PAGES == 0))
-                                touch_nmi_watchdog();
-                        if (pfn_valid(pgdat->node_start_pfn + i))
-                                page = pfn_to_page(pgdat->node_start_pfn + i);
-                        else {
-                                i = vmemmap_find_next_valid_pfn(nid, i) - 1;
-                                continue;
-                        }
-                        if (PageReserved(page))
-                                reserved++;
-                        else if (PageSwapCache(page))
-                                cached++;
-                        else if (page_count(page))
-                                shared += page_count(page)-1;
-                }
-                pgdat_resize_unlock(pgdat, &flags);
-                total_present += present;
-                total_reserved += reserved;
-                total_cached += cached;
-                total_shared += shared;
-                printk(KERN_INFO "Node %4d:  RAM: %11ld, rsvd: %8d, "
-                       "shrd: %10d, swpd: %10d\n", nid,
-                       present, reserved, shared, cached);
-        }
-        printk(KERN_INFO "%ld pages of RAM\n", total_present);
-        printk(KERN_INFO "%d reserved pages\n", total_reserved);
-        printk(KERN_INFO "%d pages shared\n", total_shared);
-        printk(KERN_INFO "%d pages swap cached\n", total_cached);
-        printk(KERN_INFO "Total of %ld pages in page table cache\n",
-               quicklist_total_size());
-        printk(KERN_INFO "%ld free buffer pages\n", nr_free_buffer_pages());
-}
-
-/**
  * call_pernode_memory - use SRAT to call callback functions with node info
  * @start: physical start of range
  * @len: length of range
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index 88504abf5704..25c350264a41 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -684,3 +684,51 @@ per_linux32_init(void)
 }
 
 __initcall(per_linux32_init);
+
+/**
+ * show_mem - give short summary of memory stats
+ *
+ * Shows a simple page count of reserved and used pages in the system.
+ * For discontig machines, it does this on a per-pgdat basis.
+ */
+void show_mem(unsigned int filter)
+{
+        int total_reserved = 0;
+        unsigned long total_present = 0;
+        pg_data_t *pgdat;
+
+        printk(KERN_INFO "Mem-info:\n");
+        show_free_areas(filter);
+        printk(KERN_INFO "Node memory in pages:\n");
+        for_each_online_pgdat(pgdat) {
+                unsigned long present;
+                unsigned long flags;
+                int reserved = 0;
+                int nid = pgdat->node_id;
+                int zoneid;
+
+                if (skip_free_areas_node(filter, nid))
+                        continue;
+                pgdat_resize_lock(pgdat, &flags);
+
+                for (zoneid = 0; zoneid < MAX_NR_ZONES; zoneid++) {
+                        struct zone *zone = &pgdat->node_zones[zoneid];
+                        if (!populated_zone(zone))
+                                continue;
+
+                        reserved += zone->present_pages - zone->managed_pages;
+                }
+                present = pgdat->node_present_pages;
+
+                pgdat_resize_unlock(pgdat, &flags);
+                total_present += present;
+                total_reserved += reserved;
+                printk(KERN_INFO "Node %4d:  RAM: %11ld, rsvd: %8d, ",
+                       nid, present, reserved);
+        }
+        printk(KERN_INFO "%ld pages of RAM\n", total_present);
+        printk(KERN_INFO "%d reserved pages\n", total_reserved);
+        printk(KERN_INFO "Total of %ld pages in page table cache\n",
+               quicklist_total_size());
+        printk(KERN_INFO "%ld free buffer pages\n", nr_free_buffer_pages());
+}
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
index 3290d6e00c31..d0853e8e8623 100644
--- a/arch/ia64/sn/pci/pci_dma.c
+++ b/arch/ia64/sn/pci/pci_dma.c
@@ -34,7 +34,7 @@
  */
 static int sn_dma_supported(struct device *dev, u64 mask)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         if (mask < 0x7fffffff)
                 return 0;
@@ -50,7 +50,7 @@ static int sn_dma_supported(struct device *dev, u64 mask)
  */
 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         if (!sn_dma_supported(dev, dma_mask))
                 return 0;
@@ -85,7 +85,7 @@ static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
         struct pci_dev *pdev = to_pci_dev(dev);
         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         /*
          * Allocate the memory.
@@ -143,7 +143,7 @@ static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr
         struct pci_dev *pdev = to_pci_dev(dev);
         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         provider->dma_unmap(pdev, dma_handle, 0);
         free_pages((unsigned long)cpu_addr, get_order(size));
@@ -187,7 +187,7 @@ static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
 
         dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         phys_addr = __pa(cpu_addr);
         if (dmabarr)
@@ -223,7 +223,7 @@ static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
         struct pci_dev *pdev = to_pci_dev(dev);
         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         provider->dma_unmap(pdev, dma_addr, dir);
 }
@@ -247,7 +247,7 @@ static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
         struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
         struct scatterlist *sg;
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         for_each_sg(sgl, sg, nhwentries, i) {
                 provider->dma_unmap(pdev, sg->dma_address, dir);
@@ -284,7 +284,7 @@ static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
 
         dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs);
 
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 
         /*
          * Setup a DMA address for each entry in the scatterlist.
@@ -323,26 +323,26 @@ static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
 static void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
                                        size_t size, enum dma_data_direction dir)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 }
 
 static void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
                                           size_t size,
                                           enum dma_data_direction dir)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 }
 
 static void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
                                    int nelems, enum dma_data_direction dir)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 }
 
 static void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                                       int nelems, enum dma_data_direction dir)
 {
-        BUG_ON(dev->bus != &pci_bus_type);
+        BUG_ON(!dev_is_pci(dev));
 }
 
 static int sn_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 09ef94a8a7c3..ca4504424dae 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -277,13 +277,13 @@ config SMP
         bool "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           People using multiprocessor machines who say Y here should also say
diff --git a/arch/m32r/include/asm/Kbuild b/arch/m32r/include/asm/Kbuild
index 2b58c5f0bc38..932435ac4e5c 100644
--- a/arch/m32r/include/asm/Kbuild
+++ b/arch/m32r/include/asm/Kbuild
@@ -4,3 +4,4 @@ generic-y += exec.h
 generic-y += module.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/m32r/include/uapi/asm/socket.h b/arch/m32r/include/uapi/asm/socket.h
index 52966650114f..6c9a24b3aefa 100644
--- a/arch/m32r/include/uapi/asm/socket.h
+++ b/arch/m32r/include/uapi/asm/socket.h
@@ -78,4 +78,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_M32R_SOCKET_H */
diff --git a/arch/m68k/emu/nfblock.c b/arch/m68k/emu/nfblock.c
index 0721858fbd1e..2d75ae246167 100644
--- a/arch/m68k/emu/nfblock.c
+++ b/arch/m68k/emu/nfblock.c
@@ -62,17 +62,18 @@ struct nfhd_device {
 static void nfhd_make_request(struct request_queue *queue, struct bio *bio)
 {
         struct nfhd_device *dev = queue->queuedata;
-        struct bio_vec *bvec;
-        int i, dir, len, shift;
-        sector_t sec = bio->bi_sector;
+        struct bio_vec bvec;
+        struct bvec_iter iter;
+        int dir, len, shift;
+        sector_t sec = bio->bi_iter.bi_sector;
 
         dir = bio_data_dir(bio);
         shift = dev->bshift;
-        bio_for_each_segment(bvec, bio, i) {
-                len = bvec->bv_len;
+        bio_for_each_segment(bvec, bio, iter) {
+                len = bvec.bv_len;
                 len >>= 9;
                 nfhd_read_write(dev->id, 0, dir, sec >> shift, len >> shift,
-                                bvec_to_phys(bvec));
+                                bvec_to_phys(&bvec));
                 sec += len;
         }
         bio_endio(bio, 0);
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index a5d27f272a59..7cc8c364924d 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -32,3 +32,4 @@ generic-y += types.h
 generic-y += word-at-a-time.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/metag/include/asm/Kbuild b/arch/metag/include/asm/Kbuild
index 84d0c1d6b9b3..b716d807c2ec 100644
--- a/arch/metag/include/asm/Kbuild
+++ b/arch/metag/include/asm/Kbuild
@@ -53,3 +53,4 @@ generic-y += user.h
 generic-y += vga.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/metag/include/asm/fixmap.h b/arch/metag/include/asm/fixmap.h
index 33312751c92b..af621b041739 100644
--- a/arch/metag/include/asm/fixmap.h
+++ b/arch/metag/include/asm/fixmap.h
@@ -51,37 +51,7 @@ enum fixed_addresses {
 #define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START   ((FIXADDR_TOP - FIXADDR_SIZE) & PMD_MASK)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #define kmap_get_fixmap_pte(vaddr) \
         pte_offset_kernel( \
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index 3cd6288f65c2..11fa51c89617 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -204,7 +204,8 @@ static void __init do_init_bootmem(void)
                 start_pfn = memblock_region_memory_base_pfn(reg);
                 end_pfn = memblock_region_memory_end_pfn(reg);
                 memblock_set_node(PFN_PHYS(start_pfn),
-                                  PFN_PHYS(end_pfn - start_pfn), 0);
+                                  PFN_PHYS(end_pfn - start_pfn),
+                                  &memblock.memory, 0);
         }
 
         /* All of system RAM sits in node 0 for the non-NUMA case */
diff --git a/arch/metag/mm/numa.c b/arch/metag/mm/numa.c
index b172aa45fcf8..67b46c295072 100644
--- a/arch/metag/mm/numa.c
+++ b/arch/metag/mm/numa.c
@@ -42,7 +42,8 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
         memblock_add(start, end - start);
 
         memblock_set_node(PFN_PHYS(start_pfn),
-                          PFN_PHYS(end_pfn - start_pfn), nid);
+                          PFN_PHYS(end_pfn - start_pfn),
+                          &memblock.memory, nid);
 
         /* Node-local pgdat */
         pgdat_paddr = memblock_alloc_base(sizeof(struct pglist_data),
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index e23cccde9c27..79b9bcdfe498 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -26,10 +26,13 @@ config MICROBLAZE
         select GENERIC_CPU_DEVICES
         select GENERIC_ATOMIC64
         select GENERIC_CLOCKEVENTS
+        select COMMON_CLK
+        select GENERIC_SCHED_CLOCK
         select GENERIC_IDLE_POLL_SETUP
         select MODULES_USE_ELF_RELA
         select CLONE_BACKWARDS3
         select CLKSRC_OF
+        select BUILDTIME_EXTABLE_SORT
 
 config SWAP
         def_bool n
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 40350a3c24e9..a69eaf2ab130 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -1,3 +1,5 @@
+KBUILD_DEFCONFIG := mmu_defconfig
+
 ifeq ($(CONFIG_MMU),y)
 UTS_SYSNAME = -DUTS_SYSNAME=\"Linux\"
 else
diff --git a/arch/microblaze/include/asm/Kbuild b/arch/microblaze/include/asm/Kbuild
index a82426589fff..2b98bc73642a 100644
--- a/arch/microblaze/include/asm/Kbuild
+++ b/arch/microblaze/include/asm/Kbuild
@@ -2,6 +2,7 @@
 generic-y += barrier.h
 generic-y += clkdev.h
 generic-y += exec.h
+generic-y += hash.h
 generic-y += trace_clock.h
 generic-y += syscalls.h
 generic-y += preempt.h
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index 7d6831ac8a46..3337417fcdca 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -91,15 +91,18 @@ extern struct cpuinfo cpuinfo;
 
 /* fwd declarations of the various CPUinfo populators */
 void setup_cpuinfo(void);
+void setup_cpuinfo_clk(void);
 
 void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
 
 static inline unsigned int fcpu(struct device_node *cpu, char *n)
 {
-        const __be32 *val;
-        return (val = of_get_property(cpu, n, NULL)) ?
-                                                        be32_to_cpup(val) : 0;
+        u32 val = 0;
+
+        of_property_read_u32(cpu, n, &val);
+
+        return val;
 }
 
 #endif /* _ASM_MICROBLAZE_CPUINFO_H */
diff --git a/arch/microblaze/include/asm/fixmap.h b/arch/microblaze/include/asm/fixmap.h
index f2b312e10b10..06c0e2b1883f 100644
--- a/arch/microblaze/include/asm/fixmap.h
+++ b/arch/microblaze/include/asm/fixmap.h
@@ -58,52 +58,12 @@ enum fixed_addresses {
 extern void __set_fixmap(enum fixed_addresses idx,
                                         phys_addr_t phys, pgprot_t flags);
 
-#define set_fixmap(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL_CI)
-
-#define clear_fixmap(idx) \
-                __set_fixmap(idx, 0, __pgprot(0))
-
 #define __FIXADDR_SIZE  (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START           (FIXADDR_TOP - __FIXADDR_SIZE)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
+#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_CI
 
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #endif /* !__ASSEMBLY__ */
 #endif
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 2565cb94f32f..a2cea7206077 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -342,4 +342,12 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
 #define iowrite32_rep(p, src, count) \
         outsl((unsigned long) (p), (src), (count))
 
+#define readb_relaxed   readb
+#define readw_relaxed   readw
+#define readl_relaxed   readl
+
+#define writeb_relaxed  writeb
+#define writew_relaxed  writew
+#define writel_relaxed  writel
+
 #endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/microblaze/include/asm/sections.h b/arch/microblaze/include/asm/sections.h
index c07ed5d2a820..1b281d3ea734 100644
--- a/arch/microblaze/include/asm/sections.h
+++ b/arch/microblaze/include/asm/sections.h
@@ -16,7 +16,6 @@
 # ifndef __ASSEMBLY__
 extern char _ssbss[], _esbss[];
 extern unsigned long __ivt_start[], __ivt_end[];
-extern char _etext[], _stext[];
 
 extern u32 _fdt_start[], _fdt_end[];
 
diff --git a/arch/microblaze/include/uapi/asm/Kbuild b/arch/microblaze/include/uapi/asm/Kbuild
index 6d7d7f4aaae8..1aac99f87df1 100644
--- a/arch/microblaze/include/uapi/asm/Kbuild
+++ b/arch/microblaze/include/uapi/asm/Kbuild
@@ -1,6 +1,8 @@
 # UAPI Header export list
 include include/uapi/asm-generic/Kbuild.asm
 
+generic-y += types.h
+
 header-y += auxvec.h
 header-y += bitsperlong.h
 header-y += byteorder.h
@@ -31,5 +33,4 @@ header-y += statfs.h
 header-y += swab.h
 header-y += termbits.h
 header-y += termios.h
-header-y += types.h
 header-y += unistd.h
diff --git a/arch/microblaze/include/uapi/asm/types.h b/arch/microblaze/include/uapi/asm/types.h
deleted file mode 100644
index b9e79bc580dd..000000000000
--- a/arch/microblaze/include/uapi/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/types.h>
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
index ee4689415410..93c26cf50de5 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -112,7 +112,4 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
         CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
 
         CI(fpga_family_code, TARGET_FAMILY);
-
-        /* take timebase-frequency from DTS */
-        ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
 }
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index 592bb2e838c4..4854285b26e7 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -113,8 +113,6 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
         ci->num_rd_brk = fcpu(cpu, "xlnx,number-of-rd-addr-brk");
         ci->num_wr_brk = fcpu(cpu, "xlnx,number-of-wr-addr-brk");
 
-        ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
-
         ci->pvr_user1 = fcpu(cpu, "xlnx,pvr-user1");
         ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
 
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index c9203b1007aa..234acad79b9e 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -8,6 +8,7 @@
  * for more details.
  */
 
+#include <linux/clk.h>
 #include <linux/init.h>
 #include <asm/cpuinfo.h>
 #include <asm/pvr.h>
@@ -39,6 +40,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
         {"8.30.a", 0x17},
         {"8.40.a", 0x18},
         {"8.40.b", 0x19},
+        {"8.50.a", 0x1a},
         {"9.0", 0x1b},
         {"9.1", 0x1d},
         {NULL, 0},
@@ -68,11 +70,10 @@ const struct family_string_key family_string_lookup[] = {
 };
 
 struct cpuinfo cpuinfo;
+static struct device_node *cpu;
 
 void __init setup_cpuinfo(void)
 {
-        struct device_node *cpu = NULL;
-
         cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");
         if (!cpu)
                 pr_err("You don't have cpu!!!\n");
@@ -102,3 +103,22 @@ void __init setup_cpuinfo(void)
                 pr_warn("%s: Stream instructions enabled"
                         " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);
 }
+
+void __init setup_cpuinfo_clk(void)
+{
+        struct clk *clk;
+
+        clk = of_clk_get(cpu, 0);
+        if (IS_ERR(clk)) {
+                pr_err("ERROR: CPU CCF input clock not found\n");
+                /* take timebase-frequency from DTS */
+                cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency");
+        } else {
+                cpuinfo.cpu_clock_freq = clk_get_rate(clk);
+        }
+
+        if (!cpuinfo.cpu_clock_freq) {
+                pr_err("ERROR: CPU clock frequency not setup\n");
+                BUG();
+        }
+}
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 817b7eec95b6..b7fb0438458c 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -64,6 +64,10 @@ real_start:
 #endif
 
         mts     rmsr, r0
+/* Disable stack protection from bootloader */
+        mts     rslr, r0
+        addi    r8, r0, 0xFFFFFFF
+        mts     rshr, r8
 /*
  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
  * if the msrclr instruction is not enabled. We use this to detect
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index fc6b89f4dd31..0b11a4469deb 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -147,15 +147,14 @@
                 or      r3, r0, NUM_TO_REG (regnum);
 
         /* Shift right instruction depending on available configuration */
-        #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
-        #define BSRLI(rD, rA, imm)      \
-                bsrli rD, rA, imm
-        #else
-        #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
+        #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0
         /* Only the used shift constants defined here - add more if needed */
         #define BSRLI2(rD, rA)                          \
                 srl rD, rA;             /* << 1 */      \
                 srl rD, rD;             /* << 2 */
+        #define BSRLI4(rD, rA)          \
+                BSRLI2(rD, rA);         \
+                BSRLI2(rD, rD)
         #define BSRLI10(rD, rA)                         \
                 srl rD, rA;             /* << 1 */      \
                 srl rD, rD;             /* << 2 */      \
@@ -170,7 +169,33 @@
         #define BSRLI20(rD, rA)         \
                 BSRLI10(rD, rA);        \
                 BSRLI10(rD, rD)
+
+        .macro  bsrli, rD, rA, IMM
+        .if (\IMM) == 2
+                BSRLI2(\rD, \rA)
+        .elseif (\IMM) == 10
+                BSRLI10(\rD, \rA)
+        .elseif (\IMM) == 12
+                BSRLI2(\rD, \rA)
+                BSRLI10(\rD, \rD)
+        .elseif (\IMM) == 14
+                BSRLI4(\rD, \rA)
+                BSRLI10(\rD, \rD)
+        .elseif (\IMM) == 20
+                BSRLI20(\rD, \rA)
+        .elseif (\IMM) == 24
+                BSRLI4(\rD, \rA)
+                BSRLI20(\rD, \rD)
+        .elseif (\IMM) == 28
+                BSRLI4(\rD, \rA)
+                BSRLI4(\rD, \rD)
+                BSRLI20(\rD, \rD)
+        .else
+        .error "BSRLI shift macros \IMM"
+        .endif
+        .endm
         #endif
+
 #endif /* CONFIG_MMU */
 
 .extern other_exception_handler /* Defined in exception.c */
@@ -604,7 +629,7 @@ ex_handler_done:
         ex4:
                 tophys(r4,r4)
                 /* Create L1 (pgdir/pmd) address */
-                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                bsrli   r5, r3, PGDIR_SHIFT - 2
                 andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
@@ -613,7 +638,7 @@ ex_handler_done:
                 beqi    r5, ex2                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
                 andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
@@ -705,7 +730,7 @@ ex_handler_done:
         ex6:
                 tophys(r4,r4)
                 /* Create L1 (pgdir/pmd) address */
-                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                bsrli   r5, r3, PGDIR_SHIFT - 2
                 andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
@@ -714,7 +739,7 @@ ex_handler_done:
                 beqi    r5, ex7                 /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
                 andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
@@ -776,7 +801,7 @@ ex_handler_done:
         ex9:
                 tophys(r4,r4)
                 /* Create L1 (pgdir/pmd) address */
-                BSRLI(r5,r3, PGDIR_SHIFT - 2)
+                bsrli   r5, r3, PGDIR_SHIFT - 2
                 andi    r5, r5, PAGE_SIZE - 4
 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
                 or      r4, r4, r5
@@ -785,7 +810,7 @@ ex_handler_done:
                 beqi    r5, ex10                /* Bail if no table */
 
                 tophys(r5,r5)
-                BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
+                bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
                 andi    r6, r6, PAGE_SIZE - 4
                 or      r5, r5, r6
                 lwi     r4, r5, 0               /* Get Linux PTE */
@@ -922,7 +947,7 @@ ex_handler_done:
 .ent _unaligned_data_exception
 _unaligned_data_exception:
         andi    r8, r3, 0x3E0;  /* Mask and extract the register operand */
-        BSRLI(r8,r8,2);         /* r8 >> 2 = register operand * 8 */
+        bsrli   r8, r8, 2;              /* r8 >> 2 = register operand * 8 */
         andi    r6, r3, 0x400;  /* Extract ESR[S] */
         bneid   r6, ex_sw_vm;
         andi    r6, r3, 0x800;  /* Extract ESR[W] - delay slot */
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 8de8ebc309f1..67cc4b282cc1 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/string.h>
 #include <linux/seq_file.h>
@@ -136,7 +137,7 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         lockdep_init();
 
 /* initialize device tree for usage in early_printk */
-        early_init_devtree((void *)_fdt_start);
+        early_init_devtree(_fdt_start);
 
 #ifdef CONFIG_EARLY_PRINTK
         setup_early_printk(NULL);
@@ -152,8 +153,7 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         if (fdt)
                 pr_info("FDT at 0x%08x\n", fdt);
         else
-                pr_info("Compiled-in FDT at 0x%08x\n",
-                                        (unsigned int)_fdt_start);
+                pr_info("Compiled-in FDT at %p\n", _fdt_start);
 
 #ifdef CONFIG_MTD_UCLINUX
         pr_info("Found romfs @ 0x%08x (0x%08x)\n",
@@ -175,7 +175,7 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
 #else
         if (!msr) {
                 pr_info("!!!Your kernel not setup MSR instruction but ");
-                pr_cont"CPU have it %x\n", msr);
+                pr_cont("CPU have it %x\n", msr);
         }
 #endif
 
@@ -196,6 +196,8 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
 
 void __init time_init(void)
 {
+        of_clk_init(NULL);
+        setup_cpuinfo_clk();
         clocksource_of_init();
 }
 
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 3e39b1082fdf..fb0c61443f19 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -12,12 +12,12 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/sched.h>
+#include <linux/sched_clock.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <asm/cpuinfo.h>
-#include <linux/cnt32_to_63.h>
 
 static void __iomem *timer_baseaddr;
 
@@ -167,10 +167,15 @@ static __init void xilinx_clockevent_init(void)
         clockevents_register_device(&clockevent_xilinx_timer);
 }
 
+static u64 xilinx_clock_read(void)
+{
+        return in_be32(timer_baseaddr + TCR1);
+}
+
 static cycle_t xilinx_read(struct clocksource *cs)
 {
         /* reading actual value of timer 1 */
-        return (cycle_t) (in_be32(timer_baseaddr + TCR1));
+        return (cycle_t)xilinx_clock_read();
 }
 
 static struct timecounter xilinx_tc = {
@@ -222,17 +227,17 @@ static int __init xilinx_clocksource_init(void)
         return 0;
 }
 
-/*
- * We have to protect accesses before timer initialization
- * and return 0 for sched_clock function below.
- */
-static int timer_initialized;
-
 static void __init xilinx_timer_init(struct device_node *timer)
 {
+        struct clk *clk;
+        static int initialized;
         u32 irq;
         u32 timer_num = 1;
-        int ret;
+
+        if (initialized)
+                return;
+
+        initialized = 1;
 
         timer_baseaddr = of_iomap(timer, 0);
         if (!timer_baseaddr) {
@@ -250,10 +255,20 @@ static void __init xilinx_timer_init(struct device_node *timer)
 
         pr_info("%s: irq=%d\n", timer->full_name, irq);
 
-        /* If there is clock-frequency property than use it */
-        ret = of_property_read_u32(timer, "clock-frequency", &timer_clock_freq);
-        if (ret < 0)
+        clk = of_clk_get(timer, 0);
+        if (IS_ERR(clk)) {
+                pr_err("ERROR: timer CCF input clock not found\n");
+                /* If there is clock-frequency property than use it */
+                of_property_read_u32(timer, "clock-frequency",
+                                    &timer_clock_freq);
+        } else {
+                timer_clock_freq = clk_get_rate(clk);
+        }
+
+        if (!timer_clock_freq) {
+                pr_err("ERROR: Using CPU clock frequency\n");
                 timer_clock_freq = cpuinfo.cpu_clock_freq;
+        }
 
         freq_div_hz = timer_clock_freq / HZ;
 
@@ -263,18 +278,8 @@ static void __init xilinx_timer_init(struct device_node *timer)
 #endif
         xilinx_clocksource_init();
         xilinx_clockevent_init();
-        timer_initialized = 1;
-}
 
-unsigned long long notrace sched_clock(void)
-{
-        if (timer_initialized) {
-                struct clocksource *cs = &clocksource_microblaze;
-
-                cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX;
-                return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
-        }
-        return 0;
+        sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
 }
 
 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 936d01a689d7..be9488d69734 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -51,6 +51,7 @@ SECTIONS {
         . = ALIGN(16);
         RODATA
         EXCEPTION_TABLE(16)
+        NOTES
 
         /*
          * sdata2 section can go anywhere, but must be word aligned
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 74c7bcc1e82d..89077d346714 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -192,7 +192,8 @@ void __init setup_memory(void)
                 start_pfn = memblock_region_memory_base_pfn(reg);
                 end_pfn = memblock_region_memory_end_pfn(reg);
                 memblock_set_node(start_pfn << PAGE_SHIFT,
-                                        (end_pfn - start_pfn) << PAGE_SHIFT, 0);
+                                  (end_pfn - start_pfn) << PAGE_SHIFT,
+                                  &memblock.memory, 0);
         }
 
         /* free bootmem is whole main memory */
diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts
index 3f85df2b73b3..b620da23febb 100644
--- a/arch/microblaze/platform/generic/system.dts
+++ b/arch/microblaze/platform/generic/system.dts
@@ -222,7 +222,6 @@
                         ranges ;
                         ethernet@81c00000 {
                                 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
-                                device_type = "network";
                                 interrupt-parent = <&xps_intc_0>;
                                 interrupts = < 5 2 >;
                                 llink-connected = <&PIM3>;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c93d92beb3d6..dcae3a7035db 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2,6 +2,7 @@ config MIPS
         bool
         default y
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select HAVE_CONTEXT_TRACKING
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_IDE
@@ -115,7 +116,6 @@ config BCM47XX
         select CEVT_R4K
         select CSRC_R4K
         select DMA_NONCOHERENT
-        select FW_CFE
         select HW_HAS_PCI
         select IRQ_CPU
         select SYS_HAS_CPU_MIPS32_R1
@@ -123,6 +123,7 @@ config BCM47XX
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
+        select EARLY_PRINTK_8250 if EARLY_PRINTK
         help
          Support for BCM47XX based boards
 
@@ -133,14 +134,13 @@ config BCM63XX
         select CSRC_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
-        select SYS_HAS_CPU_MIPS32_R1
-        select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_HAS_EARLY_PRINTK
         select SWAP_IO_SPACE
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
+        select MIPS_L1_CACHE_SHIFT_4
         help
          Support for BCM63XX based boards
 
@@ -185,6 +185,7 @@ config MACH_DECSTATION
         select SYS_SUPPORTS_128HZ
         select SYS_SUPPORTS_256HZ
         select SYS_SUPPORTS_1024HZ
+        select MIPS_L1_CACHE_SHIFT_4
         help
           This enables support for DEC's MIPS based workstations.  For details
           see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -304,7 +305,7 @@ config MIPS_MALTA
         select CEVT_R4K
         select CSRC_R4K
         select CSRC_GIC
-        select DMA_NONCOHERENT
+        select DMA_MAYBE_COHERENT
         select GENERIC_ISA_DMA
         select HAVE_PCSPKR_PLATFORM
         select IRQ_CPU
@@ -323,7 +324,6 @@ config MIPS_MALTA
         select SYS_HAS_CPU_MIPS64_R2
         select SYS_HAS_CPU_NEVADA
         select SYS_HAS_CPU_RM7000
-        select SYS_HAS_EARLY_PRINTK
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
@@ -348,6 +348,7 @@ config MIPS_SEAD3
         select DMA_NONCOHERENT
         select IRQ_CPU
         select IRQ_GIC
+        select LIBFDT
         select MIPS_MSC
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_HAS_CPU_MIPS32_R2
@@ -470,6 +471,7 @@ config SGI_IP22
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
+        select MIPS_L1_CACHE_SHIFT_7
         help
           This are the SGI Indy, Challenge S and Indigo2, as well as certain
           OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -490,6 +492,7 @@ config SGI_IP27
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_NUMA
         select SYS_SUPPORTS_SMP
+        select MIPS_L1_CACHE_SHIFT_7
         help
           This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
           workstations.  To compile a Linux kernel that runs on these, say Y
@@ -696,6 +699,7 @@ config MIKROTIK_RB532
         select SWAP_IO_SPACE
         select BOOT_RAW
         select ARCH_REQUIRE_GPIOLIB
+        select MIPS_L1_CACHE_SHIFT_4
         help
           Support the Mikrotik(tm) RouterBoard 532 series,
           based on the IDT RC32434 SoC.
@@ -778,6 +782,7 @@ config NLM_XLP_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
+        select ARCH_SUPPORTS_MSI
         select ZONE_DMA32 if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
@@ -896,6 +901,10 @@ config FW_CFE
 config ARCH_DMA_ADDR_T_64BIT
         def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT
 
+config DMA_MAYBE_COHERENT
+        select DMA_NONCOHERENT
+        bool
+
 config DMA_COHERENT
         bool
 
@@ -1090,11 +1099,24 @@ config FW_SNIPROM
 config BOOT_ELF32
         bool
 
+config MIPS_L1_CACHE_SHIFT_4
+        bool
+
+config MIPS_L1_CACHE_SHIFT_5
+        bool
+
+config MIPS_L1_CACHE_SHIFT_6
+        bool
+
+config MIPS_L1_CACHE_SHIFT_7
+        bool
+
 config MIPS_L1_CACHE_SHIFT
         int
-        default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
-        default "6" if MIPS_CPU_SCACHE
-        default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+        default "4" if MIPS_L1_CACHE_SHIFT_4
+        default "5" if MIPS_L1_CACHE_SHIFT_5
+        default "6" if MIPS_L1_CACHE_SHIFT_6
+        default "7" if MIPS_L1_CACHE_SHIFT_7
         default "5"
 
 config HAVE_STD_PC_SERIAL_PORT
@@ -1374,47 +1396,31 @@ config CPU_CAVIUM_OCTEON
         select LIBFDT
         select USE_OF
         select USB_EHCI_BIG_ENDIAN_MMIO
+        select SYS_HAS_DMA_OPS
+        select MIPS_L1_CACHE_SHIFT_7
         help
           The Cavium Octeon processor is a highly integrated chip containing
           many ethernet hardware widgets for networking tasks. The processor
           can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
           Full details can be found at http://www.caviumnetworks.com.
 
-config CPU_BMIPS3300
-        bool "BMIPS3300"
-        depends on SYS_HAS_CPU_BMIPS3300
-        select CPU_BMIPS
-        help
-          Broadcom BMIPS3300 processors.
-
-config CPU_BMIPS4350
-        bool "BMIPS4350"
-        depends on SYS_HAS_CPU_BMIPS4350
-        select CPU_BMIPS
-        select SYS_SUPPORTS_SMP
-        select SYS_SUPPORTS_HOTPLUG_CPU
-        help
-          Broadcom BMIPS4350 ("VIPER") processors.
-
-config CPU_BMIPS4380
-        bool "BMIPS4380"
-        depends on SYS_HAS_CPU_BMIPS4380
-        select CPU_BMIPS
-        select SYS_SUPPORTS_SMP
-        select SYS_SUPPORTS_HOTPLUG_CPU
-        help
-          Broadcom BMIPS4380 processors.
-
-config CPU_BMIPS5000
-        bool "BMIPS5000"
-        depends on SYS_HAS_CPU_BMIPS5000
-        select CPU_BMIPS
+config CPU_BMIPS
+        bool "Broadcom BMIPS"
+        depends on SYS_HAS_CPU_BMIPS
+        select CPU_MIPS32
+        select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
+        select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
+        select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
+        select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select WEAK_ORDERING
         select CPU_SUPPORTS_HIGHMEM
-        select MIPS_CPU_SCACHE
-        select SYS_SUPPORTS_SMP
-        select SYS_SUPPORTS_HOTPLUG_CPU
+        select CPU_HAS_PREFETCH
         help
-          Broadcom BMIPS5000 processors.
+          Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
 
 config CPU_XLR
         bool "Netlogic XLR SoC"
@@ -1497,14 +1503,25 @@ config CPU_LOONGSON1
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
 
-config CPU_BMIPS
+config CPU_BMIPS32_3300
+        select SMP_UP if SMP
         bool
-        select CPU_MIPS32
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
-        select WEAK_ORDERING
+
+config CPU_BMIPS4350
+        bool
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+
+config CPU_BMIPS4380
+        bool
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+
+config CPU_BMIPS5000
+        bool
+        select MIPS_CPU_SCACHE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
 
 config SYS_HAS_CPU_LOONGSON2E
         bool
@@ -1578,17 +1595,24 @@ config SYS_HAS_CPU_SB1
 config SYS_HAS_CPU_CAVIUM_OCTEON
         bool
 
-config SYS_HAS_CPU_BMIPS3300
+config SYS_HAS_CPU_BMIPS
+        bool
+
+config SYS_HAS_CPU_BMIPS32_3300
         bool
+        select SYS_HAS_CPU_BMIPS
 
 config SYS_HAS_CPU_BMIPS4350
         bool
+        select SYS_HAS_CPU_BMIPS
 
 config SYS_HAS_CPU_BMIPS4380
         bool
+        select SYS_HAS_CPU_BMIPS
 
 config SYS_HAS_CPU_BMIPS5000
         bool
+        select SYS_HAS_CPU_BMIPS
 
 config SYS_HAS_CPU_XLR
         bool
@@ -1796,6 +1820,7 @@ config IP22_CPU_SCACHE
 config MIPS_CPU_SCACHE
         bool
         select BOARD_SCACHE
+        select MIPS_L1_CACHE_SHIFT_6
 
 config R5000_CPU_SCACHE
         bool
@@ -1832,59 +1857,48 @@ choice
         prompt "MIPS MT options"
 
 config MIPS_MT_DISABLED
-        bool "Disable multithreading support."
+        bool "Disable multithreading support"
         help
-          Use this option if your workload can't take advantage of
-          MIPS hardware multithreading support.  On systems that don't have
-          the option of an MT-enabled processor this option will be the only
-          option in this menu.
+          Use this option if your platform does not support the MT ASE
+          which is hardware multithreading support. On systems without
+          an MT-enabled processor, this will be the only option that is
+          available in this menu.
 
 config MIPS_MT_SMP
         bool "Use 1 TC on each available VPE for SMP"
         depends on SYS_SUPPORTS_MULTITHREADING
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
+        select SYNC_R4K
         select MIPS_MT
         select SMP
-        select SYS_SUPPORTS_SCHED_SMT if SMP
-        select SYS_SUPPORTS_SMP
         select SMP_UP
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_SCHED_SMT
         select MIPS_PERF_SHARED_TC_COUNTERS
         help
-          This is a kernel model which is known a VSMP but lately has been
-          marketesed into SMVP.
-          Virtual SMP uses the processor's VPEs  to implement virtual
-          processors. In currently available configuration of the 34K processor
-          this allows for a dual processor. Both processors will share the same
-          primary caches; each will obtain the half of the TLB for it's own
-          exclusive use. For a layman this model can be described as similar to
-          what Intel calls Hyperthreading.
-
-          For further information see http://www.linux-mips.org/wiki/34K#VSMP
+          This is a kernel model which is known as SMVP. This is supported
+          on cores with the MT ASE and uses the available VPEs to implement
+          virtual processors which supports SMP. This is equivalent to the
+          Intel Hyperthreading feature. For further information go to
+          <http://www.imgtec.com/mips/mips-multithreading.asp>.
 
 config MIPS_MT_SMTC
-        bool "SMTC: Use all TCs on all VPEs for SMP"
+        bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
         depends on CPU_MIPS32_R2
-        #depends on CPU_MIPS64_R2               # once there is hardware ...
         depends on SYS_SUPPORTS_MULTITHREADING
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
         select MIPS_MT
-        select NR_CPUS_DEFAULT_8
         select SMP
-        select SYS_SUPPORTS_SMP
         select SMP_UP
+        select SYS_SUPPORTS_SMP
+        select NR_CPUS_DEFAULT_8
         help
-          This is a kernel model which is known a SMTC or lately has been
-          marketesed into SMVP.
-          is presenting the available TC's of the core as processors to Linux.
-          On currently available 34K processors this means a Linux system will
-          see up to 5 processors. The implementation of the SMTC kernel differs
-          significantly from VSMP and cannot efficiently coexist in the same
-          kernel binary so the choice between VSMP and SMTC is a compile time
-          decision.
-
-          For further information see http://www.linux-mips.org/wiki/34K#SMTC
+          This is a kernel model which is known as SMTC. This is
+          supported on cores with the MT ASE and presents all TCs
+          available on all VPEs to support SMP. For further
+          information see <http://www.linux-mips.org/wiki/34K#SMTC>.
 
 endchoice
 
@@ -1921,6 +1935,16 @@ config MIPS_VPE_LOADER
           Includes a loader for loading an elf relocatable object
           onto another VPE and running it.
 
+config MIPS_VPE_LOADER_CMP
+        bool
+        default "y"
+        depends on MIPS_VPE_LOADER && MIPS_CMP
+
+config MIPS_VPE_LOADER_MT
+        bool
+        default "y"
+        depends on MIPS_VPE_LOADER && !MIPS_CMP
+
 config MIPS_MT_SMTC_IM_BACKSTOP
         bool "Use per-TC register bits as backstop for inhibited IM bits"
         depends on MIPS_MT_SMTC
@@ -1954,24 +1978,29 @@ config MIPS_VPE_LOADER_TOM
           you to ensure the amount you put in the option and the space your
           program requires is less or equal to the amount physically present.
 
-# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
 config MIPS_VPE_APSP_API
         bool "Enable support for AP/SP API (RTLX)"
         depends on MIPS_VPE_LOADER
         help
 
+config MIPS_VPE_APSP_API_CMP
+        bool
+        default "y"
+        depends on MIPS_VPE_APSP_API && MIPS_CMP
+
+config MIPS_VPE_APSP_API_MT
+        bool
+        default "y"
+        depends on MIPS_VPE_APSP_API && !MIPS_CMP
+
 config MIPS_CMP
-        bool "MIPS CMP framework support"
-        depends on SYS_SUPPORTS_MIPS_CMP
-        select SMP
+        bool "MIPS CMP support"
+        depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
         select SYNC_R4K
-        select SYS_SUPPORTS_SMP
-        select SYS_SUPPORTS_SCHED_SMT if SMP
         select WEAK_ORDERING
         default n
         help
-          This is a placeholder option for the GCMP work. It will need to
-          be handled differently...
+          Enable Coherency Manager processor (CMP) support.
 
 config SB1_PASS_1_WORKAROUNDS
         bool
@@ -2129,13 +2158,13 @@ config SMP
         depends on SYS_SUPPORTS_SMP
         help
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           People using multiprocessor machines who say Y here should also say
@@ -2323,6 +2352,23 @@ config SECCOMP
 
           If unsure, say Y. Only embedded should say N here.
 
+config MIPS_O32_FP64_SUPPORT
+        bool "Support for O32 binaries using 64-bit FP"
+        depends on 32BIT || MIPS32_O32
+        default y
+        help
+          When this is enabled, the kernel will support use of 64-bit floating
+          point registers with binaries using the O32 ABI along with the
+          EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
+          32-bit MIPS systems this support is at the cost of increasing the
+          size and complexity of the compiled FPU emulator. Thus if you are
+          running a MIPS32 system and know that none of your userland binaries
+          will require 64-bit floating point, you may wish to reduce the size
+          of your kernel & potentially improve FP emulation performance by
+          saying N here.
+
+          If unsure, say Y.
+
 config USE_OF
         bool
         select OF
@@ -2430,7 +2476,7 @@ source "drivers/pcmcia/Kconfig"
 source "drivers/pci/hotplug/Kconfig"
 
 config RAPIDIO
-        bool "RapidIO support"
+        tristate "RapidIO support"
         depends on PCI
         default n
         help
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efe50787cd89..9b8556de9993 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -114,7 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= $(shell $(CC) -dumpmachine |grep -q 'mips.*e
 cflags-$(CONFIG_CPU_LITTLE_ENDIAN)      += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
 
 cflags-$(CONFIG_CPU_HAS_SMARTMIPS)      += $(call cc-option,-msmartmips)
-cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals)
+cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
 
 cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
                                    -fno-omit-frame-pointer
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 0c7fce2a3c12..bdb28dee8fdd 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -29,7 +29,6 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/sysctl.h>
 #include <linux/jiffies.h>
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index 22c93213b233..1dc6c3b37f91 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -18,7 +18,6 @@
  * Setting up the clock on the MIPS boards.
  */
 
-#include <linux/init.h>
 #include <linux/time.h>
 #include <linux/err.h>
 #include <linux/clk.h>
diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
index 648d2dafbc56..a3120714f0b7 100644
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -15,7 +15,6 @@
 #define __ATH79_COMMON_H
 
 #include <linux/types.h>
-#include <linux/init.h>
 
 #define ATH79_MEM_SIZE_MIN      (2 * 1024 * 1024)
 #define ATH79_MEM_SIZE_MAX      (128 * 1024 * 1024)
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
index 2b8b118398c4..09cb6f7aa3db 100644
--- a/arch/mips/bcm47xx/Kconfig
+++ b/arch/mips/bcm47xx/Kconfig
@@ -2,6 +2,7 @@ if BCM47XX
 
 config BCM47XX_SSB
         bool "SSB Support for Broadcom BCM47XX"
+        select SYS_HAS_CPU_BMIPS32_3300
         select SSB
         select SSB_DRIVER_MIPS
         select SSB_DRIVER_EXTIF
@@ -11,6 +12,7 @@ config BCM47XX_SSB
         select SSB_PCICORE_HOSTMODE if PCI
         select SSB_DRIVER_GPIO
         select GPIOLIB
+        select LEDS_GPIO_REGISTER
         default y
         help
          Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@@ -20,6 +22,7 @@ config BCM47XX_SSB
 config BCM47XX_BCMA
         bool "BCMA Support for Broadcom BCM47XX"
         select SYS_HAS_CPU_MIPS32_R2
+        select CPU_MIPSR2_IRQ_VI
         select BCMA
         select BCMA_HOST_SOC
         select BCMA_DRIVER_MIPS
@@ -27,6 +30,7 @@ config BCM47XX_BCMA
         select BCMA_DRIVER_PCI_HOSTMODE if PCI
         select BCMA_DRIVER_GPIO
         select GPIOLIB
+        select LEDS_GPIO_REGISTER
         default y
         help
          Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
index c52daf9b05c6..4688b6a6211b 100644
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -4,5 +4,4 @@
 #
 
 obj-y                           += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
-obj-y                           += board.o
-obj-$(CONFIG_BCM47XX_SSB)       += wgt634u.o
+obj-y                           += board.o buttons.o leds.o
diff --git a/arch/mips/bcm47xx/bcm47xx_private.h b/arch/mips/bcm47xx/bcm47xx_private.h
new file mode 100644
index 000000000000..5c94acebf76a
--- /dev/null
+++ b/arch/mips/bcm47xx/bcm47xx_private.h
@@ -0,0 +1,12 @@
+#ifndef LINUX_BCM47XX_PRIVATE_H_
+#define LINUX_BCM47XX_PRIVATE_H_
+
+#include <linux/kernel.h>
+
+/* buttons.c */
+int __init bcm47xx_buttons_register(void);
+
+/* leds.c */
+void __init bcm47xx_leds_register(void);
+
+#endif
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index f3f6bfe68a2a..6d612e2b949b 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -36,26 +36,32 @@ static const
 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
         {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"},
         {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* model_no */
 static const
 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
         {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* machine_name */
 static const
 struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
         {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* hardware_version */
 static const
 struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
+        {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"},
+        {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
+        {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"},
+        {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"},
+        {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RTN12D1"},
+        {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RTN12HP"},
         {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
         {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"},
         {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"},
@@ -66,7 +72,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons
         {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
         {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
         {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* productid */
@@ -75,19 +81,13 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
         {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
         {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
         {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
-        {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"},
-        {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
-        {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"},
-        {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"},
-        {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"},
-        {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"},
         {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
         {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
         {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
         {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
         {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"},
         {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* ModelId */
@@ -97,7 +97,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
         {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
         {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
         {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* melco_id or buf1falo_id */
@@ -112,7 +112,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = {
         {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"},
         {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"},
         {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* boot_hw_model, boot_hw_ver */
@@ -143,7 +143,7 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
         {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
         {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
         {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* board_id */
@@ -165,7 +165,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
         {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
         {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
         {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"},
-        { {0}, 0},
+        { {0}, NULL},
 };
 
 /* boardtype, boardnum, boardrev */
@@ -174,7 +174,9 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
         {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
         {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
         {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
-        { {0}, 0},
+        {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
+        {{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"},
+        { {0}, NULL},
 };
 
 static const
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
new file mode 100644
index 000000000000..872c62e93e0e
--- /dev/null
+++ b/arch/mips/bcm47xx/buttons.c
@@ -0,0 +1,531 @@
+#include "bcm47xx_private.h"
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/interrupt.h>
+#include <bcm47xx_board.h>
+#include <bcm47xx.h>
+
+/**************************************************
+ * Database
+ **************************************************/
+
+#define BCM47XX_GPIO_KEY(_gpio, _code)                                  \
+        {                                                               \
+                .code           = _code,                                \
+                .gpio           = _gpio,                                \
+                .active_low     = 1,                                    \
+        }
+
+/* Asus */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_rtn12[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(1, KEY_RESTART),
+        BCM47XX_GPIO_KEY(4, BTN_0), /* Router mode */
+        BCM47XX_GPIO_KEY(5, BTN_1), /* Repeater mode */
+        BCM47XX_GPIO_KEY(6, BTN_2), /* AP mode */
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_rtn16[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(8, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_rtn66u[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(9, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl300g[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl320ge[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl330ge[] __initconst = {
+        BCM47XX_GPIO_KEY(2, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl500gd[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl500gpv1[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_RESTART),
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl500gpv2[] __initconst = {
+        BCM47XX_GPIO_KEY(2, KEY_RESTART),
+        BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl500w[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+        BCM47XX_GPIO_KEY(7, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl520gc[] __initconst = {
+        BCM47XX_GPIO_KEY(2, KEY_RESTART),
+        BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl520gu[] __initconst = {
+        BCM47XX_GPIO_KEY(2, KEY_RESTART),
+        BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wl700ge[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_POWER), /* Hard disk power switch */
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), /* EZSetup */
+        BCM47XX_GPIO_KEY(6, KEY_COPY), /* Copy data from USB to internal disk */
+        BCM47XX_GPIO_KEY(7, KEY_RESTART), /* Hard reset */
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_asus_wlhdd[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+/* Huawei */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_huawei_e970[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+/* Belkin */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_belkin_f7d4301[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+        BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
+};
+
+/* Buffalo */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_whr2_a54g54[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_whr_g125[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+        BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+        BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+        BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_wzr_g300n[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_wzr_rs_g54[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_buffalo_wzr_rs_g54hp[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+};
+
+/* Dell */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_dell_tm2300[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_RESTART),
+};
+
+/* D-Link */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_dlink_dir130[] __initconst = {
+        BCM47XX_GPIO_KEY(3, KEY_RESTART),
+        BCM47XX_GPIO_KEY(7, KEY_UNKNOWN),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_dlink_dir330[] __initconst = {
+        BCM47XX_GPIO_KEY(3, KEY_RESTART),
+        BCM47XX_GPIO_KEY(7, KEY_UNKNOWN),
+};
+
+/* Linksys */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e1000v1[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e1000v21[] __initconst = {
+        BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(10, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e2000v1[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(8, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e3000v1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e3200v1[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_RESTART),
+        BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_e4200v1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt150nv1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt150nv11[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt160nv1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt160nv3[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt300nv11[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_UNKNOWN),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt310nv1[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+        BCM47XX_GPIO_KEY(8, KEY_UNKNOWN),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt610nv1[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+        BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt610nv2[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+/* Motorola */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_motorola_we800g[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_motorola_wr850gp[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_motorola_wr850gv2v3[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_RESTART),
+};
+
+/* Netgear */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_RESTART),
+        BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(8, KEY_RFKILL),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_wndr3700v3[] __initconst = {
+        BCM47XX_GPIO_KEY(2, KEY_RFKILL),
+        BCM47XX_GPIO_KEY(3, KEY_RESTART),
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_wndr4500v1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(5, KEY_RFKILL),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+static const struct gpio_keys_button
+bcm47xx_buttons_netgear_wnr834bv2[] __initconst = {
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+
+/* SimpleTech */
+
+static const struct gpio_keys_button
+bcm47xx_buttons_simpletech_simpleshare[] __initconst = {
+        BCM47XX_GPIO_KEY(0, KEY_RESTART),
+};
+
+/**************************************************
+ * Init
+ **************************************************/
+
+static struct gpio_keys_platform_data bcm47xx_button_pdata;
+
+static struct platform_device bcm47xx_buttons_gpio_keys = {
+        .name = "gpio-keys",
+        .dev = {
+                .platform_data = &bcm47xx_button_pdata,
+        }
+};
+
+/* Copy data from __initconst */
+static int __init bcm47xx_buttons_copy(const struct gpio_keys_button *buttons,
+                                       size_t nbuttons)
+{
+        size_t size = nbuttons * sizeof(*buttons);
+
+        bcm47xx_button_pdata.buttons = kmalloc(size, GFP_KERNEL);
+        if (!bcm47xx_button_pdata.buttons)
+                return -ENOMEM;
+        memcpy(bcm47xx_button_pdata.buttons, buttons, size);
+        bcm47xx_button_pdata.nbuttons = nbuttons;
+
+        return 0;
+}
+
+#define bcm47xx_copy_bdata(dev_buttons)                                 \
+        bcm47xx_buttons_copy(dev_buttons, ARRAY_SIZE(dev_buttons));
+
+int __init bcm47xx_buttons_register(void)
+{
+        enum bcm47xx_board board = bcm47xx_board_get();
+        int err;
+
+        switch (board) {
+        case BCM47XX_BOARD_ASUS_RTN12:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
+                break;
+        case BCM47XX_BOARD_ASUS_RTN16:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn16);
+                break;
+        case BCM47XX_BOARD_ASUS_RTN66U:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn66u);
+                break;
+        case BCM47XX_BOARD_ASUS_WL300G:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl300g);
+                break;
+        case BCM47XX_BOARD_ASUS_WL320GE:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl320ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WL330GE:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl330ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GD:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gd);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GPV1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv1);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GPV2:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv2);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500W:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500w);
+                break;
+        case BCM47XX_BOARD_ASUS_WL520GC:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gc);
+                break;
+        case BCM47XX_BOARD_ASUS_WL520GU:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gu);
+                break;
+        case BCM47XX_BOARD_ASUS_WL700GE:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl700ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WLHDD:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd);
+                break;
+
+        case BCM47XX_BOARD_BELKIN_F7D4301:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301);
+                break;
+
+        case BCM47XX_BOARD_BUFFALO_WHR2_A54G54:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr2_a54g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_G125:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g125);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_G54S:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g54s);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_HP_G54:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_hp_g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_G300N:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_g300n);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_RS_G54:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54hp);
+                break;
+
+        case BCM47XX_BOARD_DELL_TM2300:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_dell_tm2300);
+                break;
+
+        case BCM47XX_BOARD_DLINK_DIR130:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir130);
+                break;
+        case BCM47XX_BOARD_DLINK_DIR330:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir330);
+                break;
+
+        case BCM47XX_BOARD_HUAWEI_E970:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_huawei_e970);
+                break;
+
+        case BCM47XX_BOARD_LINKSYS_E1000V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E1000V21:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v21);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E2000V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E3000V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E3200V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3200v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E4200V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e4200v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT150NV1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT150NV11:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv11);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT160NV1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT160NV3:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT300NV11:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT310NV1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT610NV1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT610NV2:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2);
+                break;
+
+        case BCM47XX_BOARD_MOTOROLA_WE800G:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);
+                break;
+        case BCM47XX_BOARD_MOTOROLA_WR850GP:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gp);
+                break;
+        case BCM47XX_BOARD_MOTOROLA_WR850GV2V3:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gv2v3);
+                break;
+
+        case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
+                break;
+        case BCM47XX_BOARD_NETGEAR_WNDR3700V3:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3);
+                break;
+        case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr4500v1);
+                break;
+        case BCM47XX_BOARD_NETGEAR_WNR834BV2:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2);
+                break;
+
+        case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_simpletech_simpleshare);
+                break;
+
+        default:
+                pr_debug("No buttons configuration found for this device\n");
+                return -ENOTSUPP;
+        }
+
+        if (err)
+                return -ENOMEM;
+
+        err = platform_device_register(&bcm47xx_buttons_gpio_keys);
+        if (err) {
+                pr_err("Failed to register platform device: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}
diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c
index 8cf3833b2d29..e0585b76ec19 100644
--- a/arch/mips/bcm47xx/irq.c
+++ b/arch/mips/bcm47xx/irq.c
@@ -25,10 +25,11 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <asm/setup.h>
 #include <asm/irq_cpu.h>
 #include <bcm47xx.h>
 
-void plat_irq_dispatch(void)
+asmlinkage void plat_irq_dispatch(void)
 {
         u32 cause;
 
@@ -50,6 +51,18 @@ void plat_irq_dispatch(void)
                 do_IRQ(6);
 }
 
+#define DEFINE_HWx_IRQDISPATCH(x)                                       \
+        static void bcm47xx_hw ## x ## _irqdispatch(void)               \
+        {                                                               \
+                do_IRQ(x);                                              \
+        }
+DEFINE_HWx_IRQDISPATCH(2)
+DEFINE_HWx_IRQDISPATCH(3)
+DEFINE_HWx_IRQDISPATCH(4)
+DEFINE_HWx_IRQDISPATCH(5)
+DEFINE_HWx_IRQDISPATCH(6)
+DEFINE_HWx_IRQDISPATCH(7)
+
 void __init arch_init_irq(void)
 {
 #ifdef CONFIG_BCM47XX_BCMA
@@ -64,4 +77,14 @@ void __init arch_init_irq(void)
         }
 #endif
         mips_cpu_irq_init();
+
+        if (cpu_has_vint) {
+                pr_info("Setting up vectored interrupts\n");
+                set_vi_handler(2, bcm47xx_hw2_irqdispatch);
+                set_vi_handler(3, bcm47xx_hw3_irqdispatch);
+                set_vi_handler(4, bcm47xx_hw4_irqdispatch);
+                set_vi_handler(5, bcm47xx_hw5_irqdispatch);
+                set_vi_handler(6, bcm47xx_hw6_irqdispatch);
+                set_vi_handler(7, bcm47xx_hw7_irqdispatch);
+        }
 }
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
new file mode 100644
index 000000000000..647d15527066
--- /dev/null
+++ b/arch/mips/bcm47xx/leds.c
@@ -0,0 +1,542 @@
+#include "bcm47xx_private.h"
+
+#include <linux/leds.h>
+#include <bcm47xx_board.h>
+
+/**************************************************
+ * Database
+ **************************************************/
+
+#define BCM47XX_GPIO_LED(_gpio, _color, _function, _active_low,         \
+                         _default_state)                                \
+        {                                                               \
+                .name           = "bcm47xx:" _color ":" _function,      \
+                .gpio           = _gpio,                                \
+                .active_low     = _active_low,                          \
+                .default_state  = _default_state,                       \
+        }
+
+#define BCM47XX_GPIO_LED_TRIGGER(_gpio, _color, _function, _active_low, \
+                                 _default_trigger)                      \
+        {                                                               \
+                .name           = "bcm47xx:" _color ":" _function,      \
+                .gpio           = _gpio,                                \
+                .active_low     = _active_low,                          \
+                .default_state  = LEDS_GPIO_DEFSTATE_OFF,               \
+                .default_trigger        = _default_trigger,             \
+        }
+
+/* Asus */
+
+static const struct gpio_led
+bcm47xx_leds_asus_rtn12[] __initconst = {
+        BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_rtn16[] __initconst = {
+        BCM47XX_GPIO_LED(1, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_rtn66u[] __initconst = {
+        BCM47XX_GPIO_LED(12, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(15, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl300g[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl320ge[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(11, "unk", "link", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl330ge[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl500gd[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl500gpv1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl500gpv2[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl500w[] __initconst = {
+        BCM47XX_GPIO_LED(5, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl520gc[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl520gu[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wl700ge[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), /* Labeled "READY" (there is no "power" LED). Originally ON, flashing on USB activity. */
+};
+
+static const struct gpio_led
+bcm47xx_leds_asus_wlhdd[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(2, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Belkin */
+
+static const struct gpio_led
+bcm47xx_leds_belkin_f7d4301[] __initconst = {
+        BCM47XX_GPIO_LED(10, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(11, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(12, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(13, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(14, "unk", "usb0", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(15, "unk", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Buffalo */
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_whr2_a54g54[] __initconst = {
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_whr_g125[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_whr_g54s[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_whr_hp_g54[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_wzr_g300n[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_wzr_rs_g54[] __initconst = {
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_buffalo_wzr_rs_g54hp[] __initconst = {
+        BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Dell */
+
+static const struct gpio_led
+bcm47xx_leds_dell_tm2300[] __initconst = {
+        BCM47XX_GPIO_LED(6, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+/* D-Link */
+
+static const struct gpio_led
+bcm47xx_leds_dlink_dir130[] __initconst = {
+        BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */
+        BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_dlink_dir330[] __initconst = {
+        BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */
+        BCM47XX_GPIO_LED(4, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Huawei */
+
+static const struct gpio_led
+bcm47xx_leds_huawei_e970[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Linksys */
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e1000v1[] __initconst = {
+        BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e1000v21[] __initconst = {
+        BCM47XX_GPIO_LED(5, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(6, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "amber", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(8, "blue", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e2000v1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e3000v1[] __initconst = {
+        BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e3200v1[] __initconst = {
+        BCM47XX_GPIO_LED(3, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_e4200v1[] __initconst = {
+        BCM47XX_GPIO_LED(5, "white", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt150nv1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt150nv11[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt160nv1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt160nv3[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt300nv11[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt310nv1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "usb",  1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "power",  0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "amber", "wps",  1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(9, "blue", "wps",  1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt610nv2[] __initconst = {
+        BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Motorola */
+
+static const struct gpio_led
+bcm47xx_leds_motorola_we800g[] __initconst = {
+        BCM47XX_GPIO_LED(1, "amber", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "unk", "unk", 1, LEDS_GPIO_DEFSTATE_OFF), /* There are only 3 LEDs: Power, Wireless and Device (ethernet) */
+        BCM47XX_GPIO_LED(4, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+};
+
+static const struct gpio_led
+bcm47xx_leds_motorola_wr850gp[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(6, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_motorola_wr850gv2v3[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* Netgear */
+
+static const struct gpio_led
+bcm47xx_leds_netgear_wndr3400v1[] __initconst = {
+        BCM47XX_GPIO_LED(2, "green", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_netgear_wndr4500v1[] __initconst = {
+        BCM47XX_GPIO_LED(1, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(2, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(8, "green", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(9, "green", "2ghz", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(11, "blue", "5ghz", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(14, "green", "usb2", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+static const struct gpio_led
+bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
+        BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+
+/* SimpleTech */
+
+static const struct gpio_led
+bcm47xx_leds_simpletech_simpleshare[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "status", 1, LEDS_GPIO_DEFSTATE_OFF), /* "Ready" LED */
+};
+
+/**************************************************
+ * Init
+ **************************************************/
+
+static struct gpio_led_platform_data bcm47xx_leds_pdata;
+
+#define bcm47xx_set_pdata(dev_leds) do {                                \
+        bcm47xx_leds_pdata.leds = dev_leds;                             \
+        bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds);             \
+} while (0)
+
+void __init bcm47xx_leds_register(void)
+{
+        enum bcm47xx_board board = bcm47xx_board_get();
+
+        switch (board) {
+        case BCM47XX_BOARD_ASUS_RTN12:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
+                break;
+        case BCM47XX_BOARD_ASUS_RTN16:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_rtn16);
+                break;
+        case BCM47XX_BOARD_ASUS_RTN66U:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_rtn66u);
+                break;
+        case BCM47XX_BOARD_ASUS_WL300G:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl300g);
+                break;
+        case BCM47XX_BOARD_ASUS_WL320GE:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl320ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WL330GE:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl330ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GD:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gd);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GPV1:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv1);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500GPV2:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv2);
+                break;
+        case BCM47XX_BOARD_ASUS_WL500W:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl500w);
+                break;
+        case BCM47XX_BOARD_ASUS_WL520GC:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gc);
+                break;
+        case BCM47XX_BOARD_ASUS_WL520GU:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gu);
+                break;
+        case BCM47XX_BOARD_ASUS_WL700GE:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wl700ge);
+                break;
+        case BCM47XX_BOARD_ASUS_WLHDD:
+                bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd);
+                break;
+
+        case BCM47XX_BOARD_BELKIN_F7D4301:
+                bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301);
+                break;
+
+        case BCM47XX_BOARD_BUFFALO_WHR2_A54G54:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr2_a54g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_G125:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g125);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_G54S:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g54s);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WHR_HP_G54:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_hp_g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_G300N:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_g300n);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_RS_G54:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54);
+                break;
+        case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP:
+                bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54hp);
+                break;
+
+        case BCM47XX_BOARD_DELL_TM2300:
+                bcm47xx_set_pdata(bcm47xx_leds_dell_tm2300);
+                break;
+
+        case BCM47XX_BOARD_DLINK_DIR130:
+                bcm47xx_set_pdata(bcm47xx_leds_dlink_dir130);
+                break;
+        case BCM47XX_BOARD_DLINK_DIR330:
+                bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
+                break;
+
+        case BCM47XX_BOARD_HUAWEI_E970:
+                bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
+                break;
+
+        case BCM47XX_BOARD_LINKSYS_E1000V1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E1000V21:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v21);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E2000V1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e2000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E3000V1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e3000v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E3200V1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e3200v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_E4200V1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_e4200v1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT150NV1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT150NV11:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv11);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT160NV1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT160NV3:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT300NV11:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT310NV1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT610NV1:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT610NV2:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2);
+                break;
+
+        case BCM47XX_BOARD_MOTOROLA_WE800G:
+                bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
+                break;
+        case BCM47XX_BOARD_MOTOROLA_WR850GP:
+                bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gp);
+                break;
+        case BCM47XX_BOARD_MOTOROLA_WR850GV2V3:
+                bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gv2v3);
+                break;
+
+        case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
+                bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr3400v1);
+                break;
+        case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
+                bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr4500v1);
+                break;
+        case BCM47XX_BOARD_NETGEAR_WNR834BV2:
+                bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
+                break;
+
+        case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
+                bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare);
+                break;
+
+        default:
+                pr_debug("No LEDs configuration found for this device\n");
+                return;
+        }
+
+        gpio_led_register_device(-1, &bcm47xx_leds_pdata);
+}
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index b4c585b1c62e..6decb27cf48b 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -11,7 +11,6 @@
  * option) any later version.
  */
 
-#include <linux/init.h>
 #include <linux/types.h>
 #include <linux/module.h>
 #include <linux/ssb/ssb.h>
@@ -22,11 +21,11 @@
 #include <asm/mach-bcm47xx/bcm47xx.h>
 
 static char nvram_buf[NVRAM_SPACE];
+static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
 
 static u32 find_nvram_size(u32 end)
 {
         struct nvram_header *header;
-        u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
         int i;
 
         for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 5cba318bc1cd..0af808dfd1ca 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -28,126 +28,27 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
+#include <linux/ssb/ssb_driver_chipcommon.h>
+#include <linux/ssb/ssb_regs.h>
 #include <linux/smp.h>
 #include <asm/bootinfo.h>
-#include <asm/fw/cfe/cfe_api.h>
-#include <asm/fw/cfe/cfe_error.h>
 #include <bcm47xx.h>
 #include <bcm47xx_board.h>
 
-static int cfe_cons_handle;
 
-static u16 get_chip_id(void)
-{
-        switch (bcm47xx_bus_type) {
-#ifdef CONFIG_BCM47XX_SSB
-        case BCM47XX_BUS_TYPE_SSB:
-                return bcm47xx_bus.ssb.chip_id;
-#endif
-#ifdef CONFIG_BCM47XX_BCMA
-        case BCM47XX_BUS_TYPE_BCMA:
-                return bcm47xx_bus.bcma.bus.chipinfo.id;
-#endif
-        }
-        return 0;
-}
+static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
 
 const char *get_system_type(void)
 {
-        static char buf[50];
-        u16 chip_id = get_chip_id();
-
-        snprintf(buf, sizeof(buf),
-                 (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
-                                      "Broadcom BCM%04X (%s)",
-                 chip_id, bcm47xx_board_get_name());
-
-        return buf;
-}
-
-void prom_putchar(char c)
-{
-        while (cfe_write(cfe_cons_handle, &c, 1) == 0)
-                ;
+        return bcm47xx_system_type;
 }
 
-static __init void prom_init_cfe(void)
+__init void bcm47xx_set_system_type(u16 chip_id)
 {
-        uint32_t cfe_ept;
-        uint32_t cfe_handle;
-        uint32_t cfe_eptseal;
-        int argc = fw_arg0;
-        char **envp = (char **) fw_arg2;
-        int *prom_vec = (int *) fw_arg3;
-
-        /*
-         * Check if a loader was used; if NOT, the 4 arguments are
-         * what CFE gives us (handle, 0, EPT and EPTSEAL)
-         */
-        if (argc < 0) {
-                cfe_handle = (uint32_t)argc;
-                cfe_ept = (uint32_t)envp;
-                cfe_eptseal = (uint32_t)prom_vec;
-        } else {
-                if ((int)prom_vec < 0) {
-                        /*
-                         * Old loader; all it gives us is the handle,
-                         * so use the "known" entrypoint and assume
-                         * the seal.
-                         */
-                        cfe_handle = (uint32_t)prom_vec;
-                        cfe_ept = 0xBFC00500;
-                        cfe_eptseal = CFE_EPTSEAL;
-                } else {
-                        /*
-                         * Newer loaders bundle the handle/ept/eptseal
-                         * Note: prom_vec is in the loader's useg
-                         * which is still alive in the TLB.
-                         */
-                        cfe_handle = prom_vec[0];
-                        cfe_ept = prom_vec[2];
-                        cfe_eptseal = prom_vec[3];
-                }
-        }
-
-        if (cfe_eptseal != CFE_EPTSEAL) {
-                /* too early for panic to do any good */
-                printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
-                while (1) ;
-        }
-
-        cfe_init(cfe_handle, cfe_ept);
-}
-
-static __init void prom_init_console(void)
-{
-        /* Initialize CFE console */
-        cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
-}
-
-static __init void prom_init_cmdline(void)
-{
-        static char buf[COMMAND_LINE_SIZE] __initdata;
-
-        /* Get the kernel command line from CFE */
-        if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
-                buf[COMMAND_LINE_SIZE - 1] = 0;
-                strcpy(arcs_cmdline, buf);
-        }
-
-        /* Force a console handover by adding a console= argument if needed,
-         * as CFE is not available anymore later in the boot process. */
-        if ((strstr(arcs_cmdline, "console=")) == NULL) {
-                /* Try to read the default serial port used by CFE */
-                if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
-                    || (strncmp("uart", buf, 4)))
-                        /* Default to uart0 */
-                        strcpy(buf, "uart0");
-
-                /* Compute the new command line */
-                snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
-                         arcs_cmdline, buf[4]);
-        }
+        snprintf(bcm47xx_system_type, sizeof(bcm47xx_system_type),
+                 (chip_id > 0x9999) ? "Broadcom BCM%d" :
+                                      "Broadcom BCM%04X",
+                 chip_id);
 }
 
 static __init void prom_init_mem(void)
@@ -195,12 +96,16 @@ static __init void prom_init_mem(void)
         add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 
+/*
+ * This is the first serial on the chip common core, it is at this position
+ * for sb (ssb) and ai (bcma) bus.
+ */
+#define BCM47XX_SERIAL_ADDR (SSB_ENUM_BASE + SSB_CHIPCO_UART0_DATA)
+
 void __init prom_init(void)
 {
-        prom_init_cfe();
-        prom_init_console();
-        prom_init_cmdline();
         prom_init_mem();
+        setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
index b8ef965705cf..2f5bbd68e9a0 100644
--- a/arch/mips/bcm47xx/serial.c
+++ b/arch/mips/bcm47xx/serial.c
@@ -31,7 +31,8 @@ static int __init uart8250_init_ssb(void)
 
         memset(&uart8250_data, 0,  sizeof(uart8250_data));
 
-        for (i = 0; i < mcore->nr_serial_ports; i++) {
+        for (i = 0; i < mcore->nr_serial_ports &&
+                    i < ARRAY_SIZE(uart8250_data) - 1; i++) {
                 struct plat_serial8250_port *p = &(uart8250_data[i]);
                 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
 
@@ -55,7 +56,8 @@ static int __init uart8250_init_bcma(void)
 
         memset(&uart8250_data, 0,  sizeof(uart8250_data));
 
-        for (i = 0; i < cc->nr_serial_ports; i++) {
+        for (i = 0; i < cc->nr_serial_ports &&
+                    i < ARRAY_SIZE(uart8250_data) - 1; i++) {
                 struct plat_serial8250_port *p = &(uart8250_data[i]);
                 struct bcma_serial_port *bcma_port;
                 bcma_port = &(cc->serial_ports[i]);
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 1f30571968e7..025be218ea15 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -26,12 +26,19 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include "bcm47xx_private.h"
+
 #include <linux/export.h>
 #include <linux/types.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
 #include <linux/ssb/ssb.h>
 #include <linux/ssb/ssb_embedded.h>
 #include <linux/bcma/bcma_soc.h>
 #include <asm/bootinfo.h>
+#include <asm/idle.h>
+#include <asm/prom.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
 #include <bcm47xx.h>
@@ -210,12 +217,14 @@ void __init plat_mem_setup(void)
 #ifdef CONFIG_BCM47XX_BCMA
                 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
                 bcm47xx_register_bcma();
+                bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
 #endif
         } else {
                 printk(KERN_INFO "bcm47xx: using ssb bus\n");
 #ifdef CONFIG_BCM47XX_SSB
                 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
                 bcm47xx_register_ssb();
+                bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
 #endif
         }
 
@@ -223,7 +232,39 @@ void __init plat_mem_setup(void)
         _machine_halt = bcm47xx_machine_halt;
         pm_power_off = bcm47xx_machine_halt;
         bcm47xx_board_detect();
+        mips_set_machine_name(bcm47xx_board_get_name());
+}
+
+static int __init bcm47xx_cpu_fixes(void)
+{
+        switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+        case BCM47XX_BUS_TYPE_SSB:
+                /* Nothing to do */
+                break;
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+        case BCM47XX_BUS_TYPE_BCMA:
+                /* The BCM4706 has a problem with the CPU wait instruction.
+                 * When r4k_wait or r4k_wait_irqoff is used will just hang and
+                 * not return from a msleep(). Removing the cpu_wait
+                 * functionality is a workaround for this problem. The BCM4716
+                 * does not have this problem.
+                 */
+                if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
+                        cpu_wait = NULL;
+                break;
+#endif
+        }
+        return 0;
 }
+arch_initcall(bcm47xx_cpu_fixes);
+
+static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
+        .link   = 1,
+        .speed  = SPEED_100,
+        .duplex = DUPLEX_FULL,
+};
 
 static int __init bcm47xx_register_bus_complete(void)
 {
@@ -239,6 +280,10 @@ static int __init bcm47xx_register_bus_complete(void)
                 break;
 #endif
         }
+        bcm47xx_buttons_register();
+        bcm47xx_leds_register();
+
+        fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
         return 0;
 }
 device_initcall(bcm47xx_register_bus_complete);
diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
index ad03c931b905..a8b5408dd349 100644
--- a/arch/mips/bcm47xx/sprom.c
+++ b/arch/mips/bcm47xx/sprom.c
@@ -135,7 +135,7 @@ static void nvram_read_leddc(const char *prefix, const char *name,
 }
 
 static void nvram_read_macaddr(const char *prefix, const char *name,
-                               u8 (*val)[6], bool fallback)
+                               u8 val[6], bool fallback)
 {
         char buf[100];
         int err;
@@ -144,11 +144,11 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
         if (err < 0)
                 return;
 
-        bcm47xx_nvram_parse_macaddr(buf, *val);
+        bcm47xx_nvram_parse_macaddr(buf, val);
 }
 
 static void nvram_read_alpha2(const char *prefix, const char *name,
-                             char (*val)[2], bool fallback)
+                             char val[2], bool fallback)
 {
         char buf[10];
         int err;
@@ -162,7 +162,7 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
                 pr_warn("alpha2 is too long %s\n", buf);
                 return;
         }
-        memcpy(val, buf, sizeof(val));
+        memcpy(val, buf, 2);
 }
 
 static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
@@ -180,7 +180,7 @@ static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
                       fallback);
         nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
                       fallback);
-        nvram_read_alpha2(prefix, "ccode", &sprom->alpha2, fallback);
+        nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
 }
 
 static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
@@ -633,20 +633,20 @@ static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom,
 static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
                                         const char *prefix, bool fallback)
 {
-        nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac, fallback);
+        nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback);
         nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0,
                       fallback);
         nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0,
                       fallback);
 
-        nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac, fallback);
+        nvram_read_macaddr(prefix, "et1macaddr", sprom->et1mac, fallback);
         nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0,
                       fallback);
         nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0,
                       fallback);
 
-        nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac, fallback);
-        nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac, fallback);
+        nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback);
+        nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
 }
 
 static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
deleted file mode 100644
index c63a4c287b5c..000000000000
--- a/arch/mips/bcm47xx/wgt634u.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/leds.h>
-#include <linux/mtd/physmap.h>
-#include <linux/ssb/ssb.h>
-#include <linux/ssb/ssb_embedded.h>
-#include <linux/interrupt.h>
-#include <linux/reboot.h>
-#include <linux/gpio.h>
-#include <asm/mach-bcm47xx/bcm47xx.h>
-
-/* GPIO definitions for the WGT634U */
-#define WGT634U_GPIO_LED        3
-#define WGT634U_GPIO_RESET      2
-#define WGT634U_GPIO_TP1        7
-#define WGT634U_GPIO_TP2        6
-#define WGT634U_GPIO_TP3        5
-#define WGT634U_GPIO_TP4        4
-#define WGT634U_GPIO_TP5        1
-
-static struct gpio_led wgt634u_leds[] = {
-        {
-                .name = "power",
-                .gpio = WGT634U_GPIO_LED,
-                .active_low = 1,
-                .default_trigger = "heartbeat",
-        },
-};
-
-static struct gpio_led_platform_data wgt634u_led_data = {
-        .num_leds =     ARRAY_SIZE(wgt634u_leds),
-        .leds =         wgt634u_leds,
-};
-
-static struct platform_device wgt634u_gpio_leds = {
-        .name =         "leds-gpio",
-        .id =           -1,
-        .dev = {
-                .platform_data = &wgt634u_led_data,
-        }
-};
-
-
-/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
-   firmware. */
-static struct mtd_partition wgt634u_partitions[] = {
-        {
-                .name       = "cfe",
-                .offset     = 0,
-                .size       = 0x60000,          /* 384k */
-                .mask_flags = MTD_WRITEABLE     /* force read-only */
-        },
-        {
-                .name   = "config",
-                .offset = 0x60000,
-                .size   = 0x20000               /* 128k */
-        },
-        {
-                .name   = "linux",
-                .offset = 0x80000,
-                .size   = 0x140000              /* 1280k */
-        },
-        {
-                .name   = "jffs",
-                .offset = 0x1c0000,
-                .size   = 0x620000              /* 6272k */
-        },
-        {
-                .name   = "nvram",
-                .offset = 0x7e0000,
-                .size   = 0x20000               /* 128k */
-        },
-};
-
-static struct physmap_flash_data wgt634u_flash_data = {
-        .parts    = wgt634u_partitions,
-        .nr_parts = ARRAY_SIZE(wgt634u_partitions)
-};
-
-static struct resource wgt634u_flash_resource = {
-        .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device wgt634u_flash = {
-        .name          = "physmap-flash",
-        .id            = 0,
-        .dev           = { .platform_data = &wgt634u_flash_data, },
-        .resource      = &wgt634u_flash_resource,
-        .num_resources = 1,
-};
-
-/* Platform devices */
-static struct platform_device *wgt634u_devices[] __initdata = {
-        &wgt634u_flash,
-        &wgt634u_gpio_leds,
-};
-
-static irqreturn_t gpio_interrupt(int irq, void *ignored)
-{
-        int state;
-
-        /* Interrupts are shared, check if the current one is
-           a GPIO interrupt. */
-        if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco,
-                                   SSB_CHIPCO_IRQ_GPIO))
-                return IRQ_NONE;
-
-        state = gpio_get_value(WGT634U_GPIO_RESET);
-
-        /* Interrupt are level triggered, revert the interrupt polarity
-           to clear the interrupt. */
-        ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET,
-                          state ? 1 << WGT634U_GPIO_RESET : 0);
-
-        if (!state) {
-                printk(KERN_INFO "Reset button pressed");
-                ctrl_alt_del();
-        }
-
-        return IRQ_HANDLED;
-}
-
-static int __init wgt634u_init(void)
-{
-        /* There is no easy way to detect that we are running on a WGT634U
-         * machine. Use the MAC address as an heuristic. Netgear Inc. has
-         * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
-         */
-        u8 *et0mac;
-
-        if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
-                return -ENODEV;
-
-        et0mac = bcm47xx_bus.ssb.sprom.et0mac;
-
-        if (et0mac[0] == 0x00 &&
-            ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
-             (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
-                struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
-
-                printk(KERN_INFO "WGT634U machine detected.\n");
-
-                if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
-                                 gpio_interrupt, IRQF_SHARED,
-                                 "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
-                        gpio_direction_input(WGT634U_GPIO_RESET);
-                        ssb_gpio_intmask(&bcm47xx_bus.ssb,
-                                         1 << WGT634U_GPIO_RESET,
-                                         1 << WGT634U_GPIO_RESET);
-                        ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
-                                            SSB_CHIPCO_IRQ_GPIO,
-                                            SSB_CHIPCO_IRQ_GPIO);
-                }
-
-                wgt634u_flash_data.width = mcore->pflash.buswidth;
-                wgt634u_flash_resource.start = mcore->pflash.window;
-                wgt634u_flash_resource.end = mcore->pflash.window
-                                           + mcore->pflash.window_size
-                                           - 1;
-                return platform_add_devices(wgt634u_devices,
-                                            ARRAY_SIZE(wgt634u_devices));
-        } else
-                return -ENODEV;
-}
-
-module_init(wgt634u_init);
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index b78306ce56c7..a057fdf111c6 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -3,33 +3,41 @@ menu "CPU support"
 
 config BCM63XX_CPU_3368
         bool "support 3368 CPU"
+        select SYS_HAS_CPU_BMIPS4350
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6328
         bool "support 6328 CPU"
+        select SYS_HAS_CPU_BMIPS4350
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6338
         bool "support 6338 CPU"
+        select SYS_HAS_CPU_BMIPS32_3300
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6345
         bool "support 6345 CPU"
+        select SYS_HAS_CPU_BMIPS32_3300
 
 config BCM63XX_CPU_6348
         bool "support 6348 CPU"
+        select SYS_HAS_CPU_BMIPS32_3300
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6358
         bool "support 6358 CPU"
+        select SYS_HAS_CPU_BMIPS4350
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6362
         bool "support 6362 CPU"
+        select SYS_HAS_CPU_BMIPS4350
         select HW_HAS_PCI
 
 config BCM63XX_CPU_6368
         bool "support 6368 CPU"
+        select SYS_HAS_CPU_BMIPS4350
         select HW_HAS_PCI
 endmenu
 
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index ac2807397c1c..9019f54aee69 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,7 +1,7 @@
 obj-y           += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
                    setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
-                   dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \
-                   dev-usb-usbd.o
+                   dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
+                   dev-wdt.o dev-usb-usbd.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-y           += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 5b974eb125fc..33727e7f0c79 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -23,6 +23,7 @@
 #include <bcm63xx_dev_enet.h>
 #include <bcm63xx_dev_dsp.h>
 #include <bcm63xx_dev_flash.h>
+#include <bcm63xx_dev_hsspi.h>
 #include <bcm63xx_dev_pcmcia.h>
 #include <bcm63xx_dev_spi.h>
 #include <bcm63xx_dev_usb_usbd.h>
@@ -915,6 +916,8 @@ int __init board_register_devices(void)
 
         bcm63xx_spi_register();
 
+        bcm63xx_hsspi_register();
+
         bcm63xx_flash_register();
 
         bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 43da4ae04cc2..637565284732 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -226,6 +226,28 @@ static struct clk clk_spi = {
 };
 
 /*
+ * HSSPI clock
+ */
+static void hsspi_set(struct clk *clk, int enable)
+{
+        u32 mask;
+
+        if (BCMCPU_IS_6328())
+                mask = CKCTL_6328_HSSPI_EN;
+        else if (BCMCPU_IS_6362())
+                mask = CKCTL_6362_HSSPI_EN;
+        else
+                return;
+
+        bcm_hwclock_set(mask, enable);
+}
+
+static struct clk clk_hsspi = {
+        .set    = hsspi_set,
+};
+
+
+/*
  * XTM clock
  */
 static void xtm_set(struct clk *clk, int enable)
@@ -346,6 +368,8 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_usbd;
         if (!strcmp(id, "spi"))
                 return &clk_spi;
+        if (!strcmp(id, "hsspi"))
+                return &clk_hsspi;
         if (!strcmp(id, "xtm"))
                 return &clk_xtm;
         if (!strcmp(id, "periph"))
@@ -366,3 +390,21 @@ void clk_put(struct clk *clk)
 }
 
 EXPORT_SYMBOL(clk_put);
+
+#define HSSPI_PLL_HZ_6328       133333333
+#define HSSPI_PLL_HZ_6362       400000000
+
+static int __init bcm63xx_clk_init(void)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                clk_hsspi.rate = HSSPI_PLL_HZ_6328;
+                break;
+        case BCM6362_CPU_ID:
+                clk_hsspi.rate = HSSPI_PLL_HZ_6362;
+                break;
+        }
+
+        return 0;
+}
+arch_initcall(bcm63xx_clk_init);
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index b713cd64b087..1b1b8a89959b 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -123,7 +123,9 @@ unsigned int bcm63xx_get_memory_size(void)
 
 static unsigned int detect_cpu_clock(void)
 {
-        switch (bcm63xx_get_cpu_id()) {
+        u16 cpu_id = bcm63xx_get_cpu_id();
+
+        switch (cpu_id) {
         case BCM3368_CPU_ID:
                 return 300000000;
 
@@ -249,7 +251,7 @@ static unsigned int detect_cpu_clock(void)
         }
 
         default:
-                BUG();
+                panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
         }
 }
 
diff --git a/arch/mips/bcm63xx/dev-hsspi.c b/arch/mips/bcm63xx/dev-hsspi.c
new file mode 100644
index 000000000000..696abc48e3c8
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-hsspi.c
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_hsspi.h>
+#include <bcm63xx_regs.h>
+
+static struct resource spi_resources[] = {
+        {
+                .start          = -1, /* filled at runtime */
+                .end            = -1, /* filled at runtime */
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = -1, /* filled at runtime */
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bcm63xx_hsspi_device = {
+        .name           = "bcm63xx-hsspi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(spi_resources),
+        .resource       = spi_resources,
+};
+
+int __init bcm63xx_hsspi_register(void)
+{
+        if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
+                return -ENODEV;
+
+        spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
+        spi_resources[0].end = spi_resources[0].start;
+        spi_resources[0].end += RSET_HSSPI_SIZE - 1;
+        spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI);
+
+        return platform_device_register(&bcm63xx_hsspi_device);
+}
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
index aa8f7f9cc7a4..6092226a6d76 100644
--- a/arch/mips/bcm63xx/early_printk.c
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -6,9 +6,8 @@
  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  */
 
-#include <linux/init.h>
 #include <bcm63xx_io.h>
-#include <bcm63xx_regs.h>
+#include <linux/serial_bcm63xx.h>
 
 static void wait_xfered(void)
 {
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 8ac4e095e68e..e1f27d653f60 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -59,14 +59,12 @@ void __init prom_init(void)
         /* do low level board init */
         board_prom_init();
 
-        if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
-                /* set up SMP */
-                register_smp_ops(&bmips_smp_ops);
-
+        /* set up SMP */
+        if (!register_bmips_smp_ops()) {
                 /*
-                 * BCM6328 might not have its second CPU enabled, while BCM6358
-                 * needs special handling for its shared TLB, so disable SMP
-                 * for now.
+                 * BCM6328 might not have its second CPU enabled, while BCM3368
+                 * and BCM6358 need special handling for their shared TLB, so
+                 * disable SMP for now.
                  */
                 if (BCMCPU_IS_6328()) {
                         reg = bcm_readl(BCM_6328_OTP_BASE +
@@ -74,7 +72,7 @@ void __init prom_init(void)
 
                         if (reg & OTP_6328_REG3_TP1_DISABLED)
                                 bmips_smp_enabled = 0;
-                } else if (BCMCPU_IS_6358()) {
+                } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
                         bmips_smp_enabled = 0;
                 }
 
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index ca0c343c9ea5..61af6b6ab13d 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -27,10 +27,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
         -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
         -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
 
-targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
+targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
 
 # decompressor objects (linked with vmlinuz)
-vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o
 
 ifdef CONFIG_DEBUG_ZBOOT
 vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
index 134a6162e394..06c6a5bd175d 100644
--- a/arch/mips/boot/compressed/dbg.c
+++ b/arch/mips/boot/compressed/dbg.c
@@ -6,7 +6,6 @@
  * need to implement your own putc().
  */
 #include <linux/compiler.h>
-#include <linux/init.h>
 #include <linux/types.h>
 
 void __weak putc(char c)
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index a8c6fd6a4406..c00c4ddf4514 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -43,33 +43,11 @@ void error(char *x)
 /* activate the code for pre-boot environment */
 #define STATIC static
 
-#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \
-        defined(CONFIG_KERNEL_LZ4)
-void *memcpy(void *dest, const void *src, size_t n)
-{
-        int i;
-        const char *s = src;
-        char *d = dest;
-
-        for (i = 0; i < n; i++)
-                d[i] = s[i];
-        return dest;
-}
-#endif
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
 #endif
 
 #ifdef CONFIG_KERNEL_BZIP2
-void *memset(void *s, int c, size_t n)
-{
-        int i;
-        char *ss = s;
-
-        for (i = 0; i < n; i++)
-                ss[i] = c;
-        return s;
-}
 #include "../../../../lib/decompress_bunzip2.c"
 #endif
 
diff --git a/arch/mips/boot/compressed/string.c b/arch/mips/boot/compressed/string.c
new file mode 100644
index 000000000000..9de9885acd0d
--- /dev/null
+++ b/arch/mips/boot/compressed/string.c
@@ -0,0 +1,28 @@
+/*
+ * arch/mips/boot/compressed/string.c
+ *
+ * Very small subset of simple string routines
+ */
+
+#include <linux/types.h>
+
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        int i;
+        const char *s = src;
+        char *d = dest;
+
+        for (i = 0; i < n; i++)
+                d[i] = s[i];
+        return dest;
+}
+
+void *memset(void *s, int c, size_t n)
+{
+        int i;
+        char *ss = s;
+
+        for (i = 0; i < n; i++)
+                ss[i] = c;
+        return s;
+}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
index c01d343ce6ad..237494b7a21a 100644
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -4,7 +4,6 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <linux/init.h>
 
 #include <asm/addrspace.h>
 
@@ -19,8 +18,8 @@
 #endif
 
 #ifdef CONFIG_MACH_JZ4740
-#define UART0_BASE  0xB0030000
-#define PORT(offset) (UART0_BASE + (4 * offset))
+#include <asm/mach-jz4740/base.h>
+#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))
 #endif
 
 #ifdef CONFIG_CPU_XLR
diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index 132bccc66a93..8241fc6aa17d 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -47,6 +47,7 @@
  * state. It points to a bootmem named block.
  */
 __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
+EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr);
 
 /**
  * Initialize the Global queue state pointer.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 0a1283ce47f5..b764df64be40 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -722,3 +722,30 @@ int __cvmx_helper_board_hardware_enable(int interface)
         }
         return 0;
 }
+
+/**
+ * Get the clock type used for the USB block based on board type.
+ * Used by the USB code for auto configuration of clock type.
+ *
+ * Return USB clock type enumeration
+ */
+enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
+{
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_BBGW_REF:
+        case CVMX_BOARD_TYPE_LANAI2_A:
+        case CVMX_BOARD_TYPE_LANAI2_U:
+        case CVMX_BOARD_TYPE_LANAI2_G:
+        case CVMX_BOARD_TYPE_NIC10E_66:
+        case CVMX_BOARD_TYPE_UBNT_E100:
+                return USB_CLOCK_TYPE_CRYSTAL_12;
+        case CVMX_BOARD_TYPE_NIC10E:
+                return USB_CLOCK_TYPE_REF_12;
+        default:
+                break;
+        }
+        /* Most boards except NIC10e use a 12MHz crystal */
+        if (OCTEON_IS_MODEL(OCTEON_FAM_2))
+                return USB_CLOCK_TYPE_CRYSTAL_12;
+        return USB_CLOCK_TYPE_REF_48;
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index 65d2bc9a0bde..453d7f66459a 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -251,6 +251,7 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
 
         return 0;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_setup_red);
 
 /**
  * Setup the common GMX settings that determine the number of
@@ -384,6 +385,7 @@ int cvmx_helper_get_ipd_port(int interface, int port)
         }
         return -1;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port);
 
 /**
  * Returns the interface number for an IPD/PKO port number.
@@ -408,6 +410,7 @@ int cvmx_helper_get_interface_num(int ipd_port)
 
         return -1;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num);
 
 /**
  * Returns the interface index number for an IPD/PKO port
@@ -431,3 +434,4 @@ int cvmx_helper_get_interface_index_num(int ipd_port)
 
         return -1;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index d63d20dfbfb0..8553ad5c72b6 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -67,7 +67,7 @@ void (*cvmx_override_pko_queue_priority) (int pko_port,
 void (*cvmx_override_ipd_port_setup) (int ipd_port);
 
 /* Port count per interface */
-static int interface_port_count[4] = { 0, 0, 0, 0 };
+static int interface_port_count[5];
 
 /* Port last configured link info index by IPD/PKO port */
 static cvmx_helper_link_info_t
@@ -88,6 +88,7 @@ int cvmx_helper_get_number_of_interfaces(void)
         else
                 return 3;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_get_number_of_interfaces);
 
 /**
  * Return the number of ports on an interface. Depending on the
@@ -102,6 +103,7 @@ int cvmx_helper_ports_on_interface(int interface)
 {
         return interface_port_count[interface];
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface);
 
 /**
  * Get the operating mode of an interface. Depending on the Octeon
@@ -179,6 +181,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
                         return CVMX_HELPER_INTERFACE_MODE_RGMII;
         }
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_interface_get_mode);
 
 /**
  * Configure the IPD/PIP tagging and QoS options for a specific
@@ -825,6 +828,7 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
                 __cvmx_helper_errata_fix_ipd_ptr_alignment();
         return 0;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable);
 
 /**
  * Initialize the PIP, IPD, and PKO hardware to support
@@ -903,6 +907,7 @@ int cvmx_helper_initialize_packet_io_global(void)
 #endif
         return result;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global);
 
 /**
  * Does core local initialization for packet io
@@ -947,6 +952,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
          */
         return port_link_info[ipd_port];
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf);
 
 /**
  * Return the link state of an IPD/PKO port as returned by
@@ -1005,6 +1011,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
         }
         return result;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_link_get);
 
 /**
  * Configure an IPD/PKO port for the specified link state. This
@@ -1060,6 +1067,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
                 port_link_info[ipd_port].u64 = link_info.u64;
         return result;
 }
+EXPORT_SYMBOL_GPL(cvmx_helper_link_set);
 
 /**
  * Configure a port for internal and/or external loopback. Internal loopback
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index f2c877541597..008b881cdf64 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -140,7 +140,7 @@ void cvmx_pko_disable(void)
         pko_reg_flags.s.ena_pko = 0;
         cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
 }
-
+EXPORT_SYMBOL_GPL(cvmx_pko_disable);
 
 /**
  * Reset the packet output.
@@ -182,6 +182,7 @@ void cvmx_pko_shutdown(void)
         }
         __cvmx_pko_reset();
 }
+EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
 
 /**
  * Configure a output port and the associated queues for use.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index ef5198d13a0e..459e3b1eb61f 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -177,6 +177,7 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
 
         return res;
 }
+EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface);
 
 /**
  * Callback to perform SPI4 reset
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 1830874ff1e2..6df0f4d8f197 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -171,6 +171,7 @@ device_initcall(octeon_ohci_device_init);
 static struct of_device_id __initdata octeon_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "cavium,octeon-6335-uctl", },
+        { .compatible = "cavium,octeon-5750-usbn", },
         { .compatible = "cavium,octeon-3860-bootbus", },
         { .compatible = "cavium,mdio-mux", },
         { .compatible = "gpio-leds", },
@@ -336,14 +337,14 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
         int p;
         int count = 0;
 
-        if (cvmx_helper_interface_enumerate(idx) == 0)
-                count = cvmx_helper_ports_on_interface(idx);
-
         snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
         iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
         if (iface < 0)
                 return;
 
+        if (cvmx_helper_interface_enumerate(idx) == 0)
+                count = cvmx_helper_ports_on_interface(idx);
+
         for (p = 0; p < 16; p++)
                 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
 }
@@ -682,6 +683,37 @@ end_led:
                 }
         }
 
+        /* DWC2 USB */
+        alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                 "usbn", NULL);
+        if (alias_prop) {
+                int usbn = fdt_path_offset(initial_boot_params, alias_prop);
+
+                if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
+                                  !octeon_has_feature(OCTEON_FEATURE_USB))) {
+                        pr_debug("Deleting usbn\n");
+                        fdt_nop_node(initial_boot_params, usbn);
+                        fdt_nop_property(initial_boot_params, aliases, "usbn");
+                } else  {
+                        __be32 new_f[1];
+                        enum cvmx_helper_board_usb_clock_types c;
+                        c = __cvmx_helper_board_usb_get_clock_type();
+                        switch (c) {
+                        case USB_CLOCK_TYPE_REF_48:
+                                new_f[0] = cpu_to_be32(48000000);
+                                fdt_setprop_inplace(initial_boot_params, usbn,
+                                                    "refclk-frequency",  new_f, sizeof(new_f));
+                                /* Fall through ...*/
+                        case USB_CLOCK_TYPE_REF_12:
+                                /* Missing "refclk-type" defaults to external. */
+                                fdt_nop_property(initial_boot_params, usbn, "refclk-type");
+                                break;
+                        default:
+                                break;
+                        }
+                }
+        }
+
         return 0;
 }
 
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
index 88cb42d4cc49..fa33115bde33 100644
--- a/arch/mips/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -550,6 +550,24 @@
                                 big-endian-regs;
                         };
                 };
+
+                usbn: usbn@1180068000000 {
+                        compatible = "cavium,octeon-5750-usbn";
+                        reg = <0x11800 0x68000000 0x0 0x1000>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+
+                        usbc@16f0010000000 {
+                                compatible = "cavium,octeon-5750-usbc";
+                                reg = <0x16f00 0x10000000 0x0 0x80000>;
+                                interrupts = <0 56>;
+                        };
+                };
         };
 
         aliases {
@@ -566,6 +584,7 @@
                 flash0 = &flash0;
                 cf0 = &cf0;
                 uctl = &uctl;
+                usbn = &usbn;
                 led0 = &led0;
         };
  };
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 24a2167db778..67a078ffc464 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/cpu.h>
-#include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 80e012fa409c..320772caf054 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -86,7 +86,6 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 4ca8e5c99225..0db4eb319e0a 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -1,623 +1,86 @@
 CONFIG_BCM47XX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_KEXEC=y
-# CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_AUDIT=y
-CONFIG_TINY_RCU=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RELAY=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PCI=y
-CONFIG_BINFMT_MISC=m
+# CONFIG_SUSPEND is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_IP_MULTIPLE_TABLES=y
 CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
 CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
 CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=m
 CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=y
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
 CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
 CONFIG_IPV6_MULTIPLE_TABLES=y
 CONFIG_IPV6_SUBTREES=y
-CONFIG_NETWORK_SECMARK=y
+CONFIG_IPV6_MROUTE=y
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_ULOG=m
-CONFIG_IP_DCCP=m
-CONFIG_TIPC=m
-CONFIG_TIPC_ADVANCED=y
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q=y
 CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_CLS_IND=y
-CONFIG_NET_PKTGEN=m
-CONFIG_BT=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_CFG80211=m
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_PID=y
-CONFIG_MAC80211_RC_DEFAULT_PID=y
-CONFIG_MAC80211_MESH=y
-CONFIG_RFKILL=m
-CONFIG_RFKILL_INPUT=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_CONNECTOR=m
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_HAMRADIO=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
+CONFIG_MTD_BCM47XX_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_ABSENT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_ATA_OVER_ETH=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_ISCSI_TCP=m
+CONFIG_MTD_BCM47XXSFLASH=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BCM47XXNFLASH=y
 CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_VETH=m
-CONFIG_PHYLIB=m
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
 CONFIG_B44=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_ATH_COMMON=m
-CONFIG_ATH5K=m
-CONFIG_B43=m
-CONFIG_B43LEGACY=m
-CONFIG_ZD1211RW=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_SIERRA_NET=m
-CONFIG_ATM_DUMMY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
+CONFIG_TIGON3=y
+CONFIG_BGMAC=y
+CONFIG_ATH_CARDS=y
+CONFIG_ATH5K=y
+CONFIG_B43=y
+CONFIG_B43LEGACY=y
+CONFIG_BRCMSMAC=y
+CONFIG_ISDN=y
 CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_NR_UARTS=2
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_W1=m
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-CONFIG_W1_SLAVE_DS2433=m
-CONFIG_W1_SLAVE_DS2760=m
-# CONFIG_HWMON is not set
-CONFIG_THERMAL=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_HW_RANDOM=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_BCM47XX_WDT=y
+CONFIG_SSB_DEBUG=y
 CONFIG_SSB_DRIVER_GIGE=y
-CONFIG_DISPLAY_SUPPORT=m
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_HID=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_USB_STORAGE_ALAUDA=y
-CONFIG_USB_STORAGE_ONETOUCH=y
-CONFIG_USB_STORAGE_KARMA=y
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_FUNSOFT=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_HP4X=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_DEBUG=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_NET2280=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
+CONFIG_USB_HCD_BCMA=y
+CONFIG_USB_HCD_SSB=y
 CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_GFS2_FS=m
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_CRAMFS=m
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_CIFS=m
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_DLM=m
-CONFIG_DLM_DEBUG=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
-CONFIG_CRC7=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_CRC32_SARWATE=y
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index 919005139f5a..3fec26410f34 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -44,7 +44,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 5419adb219a8..23b66934e18d 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -19,7 +19,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_JEDECPROBE=y
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
index fb64589015fc..8f219dac9598 100644
--- a/arch/mips/configs/gpr_defconfig
+++ b/arch/mips/configs/gpr_defconfig
@@ -165,7 +165,6 @@ CONFIG_YAM=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index db5705e18b36..9bc08f275120 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -22,7 +22,6 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index d9f3db29ab95..0179c7fa014f 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -31,7 +31,6 @@ CONFIG_INET=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index 8a666021b870..d75931850392 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -4,7 +4,7 @@ CONFIG_CPU_MIPS32_R2=y
 CONFIG_MIPS_MT_SMP=y
 CONFIG_SCHED_SMT=y
 CONFIG_MIPS_CMP=y
-CONFIG_NR_CPUS=8
+CONFIG_NR_CPUS=2
 CONFIG_HZ_100=y
 CONFIG_LOCALVERSION="cmp"
 CONFIG_SYSVIPC=y
@@ -58,7 +58,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
 CONFIG_NET_SCH_HTB=m
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index 636f82b89fd3..4c2c0c4b9bb1 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -124,7 +124,6 @@ CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
 CONFIG_FW_LOADER=m
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9fa8f16068d8..593946afc483 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -246,7 +246,6 @@ CONFIG_BT_HCIBTUART=m
 CONFIG_BT_HCIVHCI=m
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/pnx8335_stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig
index f2925769dfa3..c887066ecc2a 100644
--- a/arch/mips/configs/pnx8335_stb225_defconfig
+++ b/arch/mips/configs/pnx8335_stb225_defconfig
@@ -31,7 +31,6 @@ CONFIG_INET_AH=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig
new file mode 100644
index 000000000000..2b965470c35b
--- /dev/null
+++ b/arch/mips/configs/qi_lb60_defconfig
@@ -0,0 +1,188 @@
+CONFIG_MACH_JZ4740=y
+# CONFIG_COMPACTION is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_HZ_100=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+CONFIG_TCP_CONG_WESTWOOD=y
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4740=y
+CONFIG_MTD_UBI=y
+CONFIG_NETDEVICES=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_MATRIX=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=2
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_BATTERY_JZ4740=y
+CONFIG_CHARGER_GPIO=y
+# CONFIG_HWMON is not set
+CONFIG_MFD_JZ4740_ADC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_JZ4740=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_JZ4740_SOC=y
+CONFIG_SND_JZ4740_SOC_QI_LB60=y
+CONFIG_USB=y
+CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_JZ4740=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_ETH=y
+# CONFIG_USB_ETH_RNDIS is not set
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_JZ4740=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_JZ4740=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_JZ4740=y
+CONFIG_PWM=y
+CONFIG_PWM_JZ4740=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+# CONFIG_JFFS2_ZLIB is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_READABLE_ASM=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_FTRACE is not set
+CONFIG_KGDB=y
+CONFIG_RUNTIME_DEBUG=y
+CONFIG_CRYPTO_ZLIB=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_FONTS=y
+CONFIG_FONT_SUN8x16=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index b85b121397c8..5d9d708e12e5 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -114,7 +114,6 @@ CONFIG_NET_CLS_IND=y
 CONFIG_HAMRADIO=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_BLOCK2MTD=y
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 9cba856277ff..f8bf9b4c1343 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -35,7 +35,6 @@ CONFIG_IP_PNP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=m
diff --git a/arch/mips/fw/arc/file.c b/arch/mips/fw/arc/file.c
index a8b08032348f..49fd3ff13fe5 100644
--- a/arch/mips/fw/arc/file.c
+++ b/arch/mips/fw/arc/file.c
@@ -8,7 +8,6 @@
  * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle
  * Copyright (C) 1999 Silicon Graphics, Inc.
  */
-#include <linux/init.h>
 
 #include <asm/fw/arc/types.h>
 #include <asm/sgialib.h>
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 1acbb8b77a71..2d7f65052c1f 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -14,3 +14,4 @@ generic-y += trace_clock.h
 generic-y += preempt.h
 generic-y += ucontext.h
 generic-y += xor.h
+generic-y += hash.h
diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h
index c3dc1a68dd8d..3cc03c64a9c7 100644
--- a/arch/mips/include/asm/amon.h
+++ b/arch/mips/include/asm/amon.h
@@ -1,7 +1,12 @@
 /*
- * Amon support
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * Arbitrary Monitor Support (AMON)
  */
-
-int amon_cpu_avail(int);
-void amon_cpu_start(int, unsigned long, unsigned long,
-                    unsigned long, unsigned long);
+int amon_cpu_avail(int cpu);
+int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
+                   unsigned long gp, unsigned long a0);
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 2413afe21b33..70e1f176f123 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -12,27 +12,6 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 
-        .macro  fpu_save_double thread status tmp1=t0
-        cfc1    \tmp1,  fcr31
-        sdc1    $f0,  THREAD_FPR0(\thread)
-        sdc1    $f2,  THREAD_FPR2(\thread)
-        sdc1    $f4,  THREAD_FPR4(\thread)
-        sdc1    $f6,  THREAD_FPR6(\thread)
-        sdc1    $f8,  THREAD_FPR8(\thread)
-        sdc1    $f10, THREAD_FPR10(\thread)
-        sdc1    $f12, THREAD_FPR12(\thread)
-        sdc1    $f14, THREAD_FPR14(\thread)
-        sdc1    $f16, THREAD_FPR16(\thread)
-        sdc1    $f18, THREAD_FPR18(\thread)
-        sdc1    $f20, THREAD_FPR20(\thread)
-        sdc1    $f22, THREAD_FPR22(\thread)
-        sdc1    $f24, THREAD_FPR24(\thread)
-        sdc1    $f26, THREAD_FPR26(\thread)
-        sdc1    $f28, THREAD_FPR28(\thread)
-        sdc1    $f30, THREAD_FPR30(\thread)
-        sw      \tmp1, THREAD_FCR31(\thread)
-        .endm
-
         .macro  fpu_save_single thread tmp=t0
         cfc1    \tmp,  fcr31
         swc1    $f0,  THREAD_FPR0(\thread)
@@ -70,27 +49,6 @@
         sw      \tmp, THREAD_FCR31(\thread)
         .endm
 
-        .macro  fpu_restore_double thread status tmp=t0
-        lw      \tmp, THREAD_FCR31(\thread)
-        ldc1    $f0,  THREAD_FPR0(\thread)
-        ldc1    $f2,  THREAD_FPR2(\thread)
-        ldc1    $f4,  THREAD_FPR4(\thread)
-        ldc1    $f6,  THREAD_FPR6(\thread)
-        ldc1    $f8,  THREAD_FPR8(\thread)
-        ldc1    $f10, THREAD_FPR10(\thread)
-        ldc1    $f12, THREAD_FPR12(\thread)
-        ldc1    $f14, THREAD_FPR14(\thread)
-        ldc1    $f16, THREAD_FPR16(\thread)
-        ldc1    $f18, THREAD_FPR18(\thread)
-        ldc1    $f20, THREAD_FPR20(\thread)
-        ldc1    $f22, THREAD_FPR22(\thread)
-        ldc1    $f24, THREAD_FPR24(\thread)
-        ldc1    $f26, THREAD_FPR26(\thread)
-        ldc1    $f28, THREAD_FPR28(\thread)
-        ldc1    $f30, THREAD_FPR30(\thread)
-        ctc1    \tmp, fcr31
-        .endm
-
         .macro  fpu_restore_single thread tmp=t0
         lw      \tmp, THREAD_FCR31(\thread)
         lwc1    $f0,  THREAD_FPR0(\thread)
diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
index 08a527dfe4a3..38ea609465b1 100644
--- a/arch/mips/include/asm/asmmacro-64.h
+++ b/arch/mips/include/asm/asmmacro-64.h
@@ -13,102 +13,6 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 
-        .macro  fpu_save_16even thread tmp=t0
-        cfc1    \tmp, fcr31
-        sdc1    $f0,  THREAD_FPR0(\thread)
-        sdc1    $f2,  THREAD_FPR2(\thread)
-        sdc1    $f4,  THREAD_FPR4(\thread)
-        sdc1    $f6,  THREAD_FPR6(\thread)
-        sdc1    $f8,  THREAD_FPR8(\thread)
-        sdc1    $f10, THREAD_FPR10(\thread)
-        sdc1    $f12, THREAD_FPR12(\thread)
-        sdc1    $f14, THREAD_FPR14(\thread)
-        sdc1    $f16, THREAD_FPR16(\thread)
-        sdc1    $f18, THREAD_FPR18(\thread)
-        sdc1    $f20, THREAD_FPR20(\thread)
-        sdc1    $f22, THREAD_FPR22(\thread)
-        sdc1    $f24, THREAD_FPR24(\thread)
-        sdc1    $f26, THREAD_FPR26(\thread)
-        sdc1    $f28, THREAD_FPR28(\thread)
-        sdc1    $f30, THREAD_FPR30(\thread)
-        sw      \tmp, THREAD_FCR31(\thread)
-        .endm
-
-        .macro  fpu_save_16odd thread
-        sdc1    $f1,  THREAD_FPR1(\thread)
-        sdc1    $f3,  THREAD_FPR3(\thread)
-        sdc1    $f5,  THREAD_FPR5(\thread)
-        sdc1    $f7,  THREAD_FPR7(\thread)
-        sdc1    $f9,  THREAD_FPR9(\thread)
-        sdc1    $f11, THREAD_FPR11(\thread)
-        sdc1    $f13, THREAD_FPR13(\thread)
-        sdc1    $f15, THREAD_FPR15(\thread)
-        sdc1    $f17, THREAD_FPR17(\thread)
-        sdc1    $f19, THREAD_FPR19(\thread)
-        sdc1    $f21, THREAD_FPR21(\thread)
-        sdc1    $f23, THREAD_FPR23(\thread)
-        sdc1    $f25, THREAD_FPR25(\thread)
-        sdc1    $f27, THREAD_FPR27(\thread)
-        sdc1    $f29, THREAD_FPR29(\thread)
-        sdc1    $f31, THREAD_FPR31(\thread)
-        .endm
-
-        .macro  fpu_save_double thread status tmp
-        sll     \tmp, \status, 5
-        bgez    \tmp, 2f
-        fpu_save_16odd \thread
-2:
-        fpu_save_16even \thread \tmp
-        .endm
-
-        .macro  fpu_restore_16even thread tmp=t0
-        lw      \tmp, THREAD_FCR31(\thread)
-        ldc1    $f0,  THREAD_FPR0(\thread)
-        ldc1    $f2,  THREAD_FPR2(\thread)
-        ldc1    $f4,  THREAD_FPR4(\thread)
-        ldc1    $f6,  THREAD_FPR6(\thread)
-        ldc1    $f8,  THREAD_FPR8(\thread)
-        ldc1    $f10, THREAD_FPR10(\thread)
-        ldc1    $f12, THREAD_FPR12(\thread)
-        ldc1    $f14, THREAD_FPR14(\thread)
-        ldc1    $f16, THREAD_FPR16(\thread)
-        ldc1    $f18, THREAD_FPR18(\thread)
-        ldc1    $f20, THREAD_FPR20(\thread)
-        ldc1    $f22, THREAD_FPR22(\thread)
-        ldc1    $f24, THREAD_FPR24(\thread)
-        ldc1    $f26, THREAD_FPR26(\thread)
-        ldc1    $f28, THREAD_FPR28(\thread)
-        ldc1    $f30, THREAD_FPR30(\thread)
-        ctc1    \tmp, fcr31
-        .endm
-
-        .macro  fpu_restore_16odd thread
-        ldc1    $f1,  THREAD_FPR1(\thread)
-        ldc1    $f3,  THREAD_FPR3(\thread)
-        ldc1    $f5,  THREAD_FPR5(\thread)
-        ldc1    $f7,  THREAD_FPR7(\thread)
-        ldc1    $f9,  THREAD_FPR9(\thread)
-        ldc1    $f11, THREAD_FPR11(\thread)
-        ldc1    $f13, THREAD_FPR13(\thread)
-        ldc1    $f15, THREAD_FPR15(\thread)
-        ldc1    $f17, THREAD_FPR17(\thread)
-        ldc1    $f19, THREAD_FPR19(\thread)
-        ldc1    $f21, THREAD_FPR21(\thread)
-        ldc1    $f23, THREAD_FPR23(\thread)
-        ldc1    $f25, THREAD_FPR25(\thread)
-        ldc1    $f27, THREAD_FPR27(\thread)
-        ldc1    $f29, THREAD_FPR29(\thread)
-        ldc1    $f31, THREAD_FPR31(\thread)
-        .endm
-
-        .macro  fpu_restore_double thread status tmp
-        sll     \tmp, \status, 5
-        bgez    \tmp, 1f                                # 16 register mode?
-
-        fpu_restore_16odd \thread
-1:      fpu_restore_16even \thread \tmp
-        .endm
-
         .macro  cpu_save_nonscratch thread
         LONG_S  s0, THREAD_REG16(\thread)
         LONG_S  s1, THREAD_REG17(\thread)
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 6c8342ae74db..3220c93ea981 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -62,6 +62,113 @@
         .endm
 #endif /* CONFIG_MIPS_MT_SMTC */
 
+        .macro  fpu_save_16even thread tmp=t0
+        cfc1    \tmp, fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_save_16odd thread
+        .set    push
+        .set    mips64r2
+        sdc1    $f1,  THREAD_FPR1(\thread)
+        sdc1    $f3,  THREAD_FPR3(\thread)
+        sdc1    $f5,  THREAD_FPR5(\thread)
+        sdc1    $f7,  THREAD_FPR7(\thread)
+        sdc1    $f9,  THREAD_FPR9(\thread)
+        sdc1    $f11, THREAD_FPR11(\thread)
+        sdc1    $f13, THREAD_FPR13(\thread)
+        sdc1    $f15, THREAD_FPR15(\thread)
+        sdc1    $f17, THREAD_FPR17(\thread)
+        sdc1    $f19, THREAD_FPR19(\thread)
+        sdc1    $f21, THREAD_FPR21(\thread)
+        sdc1    $f23, THREAD_FPR23(\thread)
+        sdc1    $f25, THREAD_FPR25(\thread)
+        sdc1    $f27, THREAD_FPR27(\thread)
+        sdc1    $f29, THREAD_FPR29(\thread)
+        sdc1    $f31, THREAD_FPR31(\thread)
+        .set    pop
+        .endm
+
+        .macro  fpu_save_double thread status tmp
+#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
+        sll     \tmp, \status, 5
+        bgez    \tmp, 10f
+        fpu_save_16odd \thread
+10:
+#endif
+        fpu_save_16even \thread \tmp
+        .endm
+
+        .macro  fpu_restore_16even thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  fpu_restore_16odd thread
+        .set    push
+        .set    mips64r2
+        ldc1    $f1,  THREAD_FPR1(\thread)
+        ldc1    $f3,  THREAD_FPR3(\thread)
+        ldc1    $f5,  THREAD_FPR5(\thread)
+        ldc1    $f7,  THREAD_FPR7(\thread)
+        ldc1    $f9,  THREAD_FPR9(\thread)
+        ldc1    $f11, THREAD_FPR11(\thread)
+        ldc1    $f13, THREAD_FPR13(\thread)
+        ldc1    $f15, THREAD_FPR15(\thread)
+        ldc1    $f17, THREAD_FPR17(\thread)
+        ldc1    $f19, THREAD_FPR19(\thread)
+        ldc1    $f21, THREAD_FPR21(\thread)
+        ldc1    $f23, THREAD_FPR23(\thread)
+        ldc1    $f25, THREAD_FPR25(\thread)
+        ldc1    $f27, THREAD_FPR27(\thread)
+        ldc1    $f29, THREAD_FPR29(\thread)
+        ldc1    $f31, THREAD_FPR31(\thread)
+        .set    pop
+        .endm
+
+        .macro  fpu_restore_double thread status tmp
+#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
+        sll     \tmp, \status, 5
+        bgez    \tmp, 10f                               # 16 register mode?
+
+        fpu_restore_16odd \thread
+10:
+#endif
+        fpu_restore_16even \thread \tmp
+        .endm
+
 /*
  * Temporary until all gas have MT ASE support
  */
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 27bd060d716e..cbaccebf5065 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -46,8 +46,35 @@
 
 #include <linux/cpumask.h>
 #include <asm/r4kcache.h>
+#include <asm/smp-ops.h>
+
+extern struct plat_smp_ops bmips43xx_smp_ops;
+extern struct plat_smp_ops bmips5000_smp_ops;
+
+static inline int register_bmips_smp_ops(void)
+{
+#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
+        switch (current_cpu_type()) {
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+                return register_up_smp_ops();
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                register_smp_ops(&bmips43xx_smp_ops);
+                break;
+        case CPU_BMIPS5000:
+                register_smp_ops(&bmips5000_smp_ops);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+#else
+        return -ENODEV;
+#endif
+}
 
-extern struct plat_smp_ops bmips_smp_ops;
 extern char bmips_reset_nmi_vec;
 extern char bmips_reset_nmi_vec_end;
 extern char bmips_smp_movevec;
diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
index 262475414e5f..1b3ad7b09dc1 100644
--- a/arch/mips/include/asm/clkdev.h
+++ b/arch/mips/include/asm/clkdev.h
@@ -14,8 +14,10 @@
 
 #include <linux/slab.h>
 
+#ifndef CONFIG_COMMON_CLK
 #define __clk_get(clk)  ({ 1; })
 #define __clk_put(clk)  do { } while (0)
+#endif
 
 static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
 {
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index d445d060e346..6e70b03b6aab 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -20,6 +20,13 @@
 #ifndef cpu_has_tlb
 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
 #endif
+#ifndef cpu_has_tlbinv
+#define cpu_has_tlbinv          (cpu_data[0].options & MIPS_CPU_TLBINV)
+#endif
+#ifndef cpu_has_segments
+#define cpu_has_segments        (cpu_data[0].options & MIPS_CPU_SEGMENTS)
+#endif
+
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 21c8e29c8f91..8f7adf0ac1e3 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -52,6 +52,9 @@ struct cpuinfo_mips {
         unsigned int            cputype;
         int                     isa_level;
         int                     tlbsize;
+        int                     tlbsizevtlb;
+        int                     tlbsizeftlbsets;
+        int                     tlbsizeftlbways;
         struct cache_desc       icache; /* Primary I-cache */
         struct cache_desc       dcache; /* Primary D or combined I/D cache */
         struct cache_desc       scache; /* Secondary cache */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 4a402cc60c03..02f591bd95ca 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -27,10 +27,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
         case CPU_4KC:
         case CPU_ALCHEMY:
-        case CPU_BMIPS3300:
-        case CPU_BMIPS4350:
         case CPU_PR4450:
-        case CPU_BMIPS32:
         case CPU_JZRISC:
 #endif
 
@@ -47,6 +44,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
         case CPU_74K:
         case CPU_M14KC:
         case CPU_M14KEC:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
 #endif
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
@@ -163,6 +162,16 @@ static inline int __pure __get_cpu_type(const int cpu_type)
         case CPU_CAVIUM_OCTEON2:
 #endif
 
+#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
+        defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+#endif
+
+#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
+        case CPU_BMIPS4350:
+#endif
+
 #ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
         case CPU_BMIPS4380:
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e16502a..76411df3d971 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,6 +111,10 @@
 #define PRID_IMP_1074K          0x9a00
 #define PRID_IMP_M14KC          0x9c00
 #define PRID_IMP_M14KEC         0x9e00
+#define PRID_IMP_INTERAPTIV_UP  0xa000
+#define PRID_IMP_INTERAPTIV_MP  0xa100
+#define PRID_IMP_PROAPTIV_UP    0xa200
+#define PRID_IMP_PROAPTIV_MP    0xa300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -194,6 +198,7 @@
 #define PRID_IMP_NETLOGIC_XLP8XX        0x1000
 #define PRID_IMP_NETLOGIC_XLP3XX        0x1100
 #define PRID_IMP_NETLOGIC_XLP2XX        0x1200
+#define PRID_IMP_NETLOGIC_XLP9XX        0x1500
 
 /*
  * Particular Revision values for bits 7:0 of the PRId register.
@@ -249,6 +254,8 @@
 
 #define FPIR_IMP_NONE           0x0000
 
+#if !defined(__ASSEMBLY__)
+
 enum cpu_type_enum {
         CPU_UNKNOWN,
 
@@ -289,7 +296,7 @@ enum cpu_type_enum {
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
         CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-        CPU_M14KEC,
+        CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
 
         /*
          * MIPS64 class processors
@@ -301,6 +308,7 @@ enum cpu_type_enum {
         CPU_LAST
 };
 
+#endif /* !__ASSEMBLY */
 
 /*
  * ISA Level encodings
@@ -348,6 +356,8 @@ enum cpu_type_enum {
 #define MIPS_CPU_PCI            0x00400000 /* CPU has Perf Ctr Int indicator */
 #define MIPS_CPU_RIXI           0x00800000 /* CPU has TLB Read/eXec Inhibit */
 #define MIPS_CPU_MICROMIPS      0x01000000 /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV         0x02000000 /* CPU supports TLBINV/F */
+#define MIPS_CPU_SEGMENTS       0x04000000 /* CPU supports Segmentation Control registers */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 242cbb3ca582..bc5e85d579e6 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,7 +9,16 @@
 #ifndef __ASM_DMA_COHERENCE_H
 #define __ASM_DMA_COHERENCE_H
 
+#ifdef CONFIG_DMA_MAYBE_COHERENT
 extern int coherentio;
 extern int hw_coherentio;
+#else
+#ifdef CONFIG_DMA_COHERENT
+#define coherentio      1
+#else
+#define coherentio      0
+#endif
+#define hw_coherentio   0
+#endif /* CONFIG_DMA_MAYBE_COHERENT */
 
 #endif
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index a66359ef4ece..d4144056e928 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -36,6 +36,7 @@
 #define EF_MIPS_ABI2            0x00000020
 #define EF_MIPS_OPTIONS_FIRST   0x00000080
 #define EF_MIPS_32BITMODE       0x00000100
+#define EF_MIPS_FP64            0x00000200
 #define EF_MIPS_ABI             0x0000f000
 #define EF_MIPS_ARCH            0xf0000000
 
@@ -176,6 +177,18 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #ifdef CONFIG_32BIT
 
 /*
+ * In order to be sure that we don't attempt to execute an O32 binary which
+ * requires 64 bit FP (FR=1) on a system which does not support it we refuse
+ * to execute any binary which has bits specified by the following macro set
+ * in its ELF header flags.
+ */
+#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
+# define __MIPS_O32_FP64_MUST_BE_ZERO   0
+#else
+# define __MIPS_O32_FP64_MUST_BE_ZERO   EF_MIPS_FP64
+#endif
+
+/*
  * This is used to ensure we don't load something for the wrong architecture.
  */
 #define elf_check_arch(hdr)                                             \
@@ -192,6 +205,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
         if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
             ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
                 __res = 0;                                              \
+        if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO)                \
+                __res = 0;                                              \
                                                                         \
         __res;                                                          \
 })
@@ -249,6 +264,11 @@ extern struct mips_abi mips_abi_n32;
 
 #define SET_PERSONALITY(ex)                                             \
 do {                                                                    \
+        if ((ex).e_flags & EF_MIPS_FP64)                                \
+                clear_thread_flag(TIF_32BIT_FPREGS);                    \
+        else                                                            \
+                set_thread_flag(TIF_32BIT_FPREGS);                      \
+                                                                        \
         if (personality(current->personality) != PER_LINUX)             \
                 set_personality(PER_LINUX);                             \
                                                                         \
@@ -271,14 +291,18 @@ do {									\
 #endif
 
 #ifdef CONFIG_MIPS32_O32
-#define __SET_PERSONALITY32_O32()                                       \
+#define __SET_PERSONALITY32_O32(ex)                                     \
         do {                                                            \
                 set_thread_flag(TIF_32BIT_REGS);                        \
                 set_thread_flag(TIF_32BIT_ADDR);                        \
+                                                                        \
+                if (!((ex).e_flags & EF_MIPS_FP64))                     \
+                        set_thread_flag(TIF_32BIT_FPREGS);              \
+                                                                        \
                 current->thread.abi = &mips_abi_32;                     \
         } while (0)
 #else
-#define __SET_PERSONALITY32_O32()                                       \
+#define __SET_PERSONALITY32_O32(ex)                                     \
         do { } while (0)
 #endif
 
@@ -289,7 +313,7 @@ do {									\
              ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
                 __SET_PERSONALITY32_N32();                              \
         else                                                            \
-                __SET_PERSONALITY32_O32();                              \
+                __SET_PERSONALITY32_O32(ex);                            \
 } while (0)
 #else
 #define __SET_PERSONALITY32(ex) do { } while (0)
@@ -300,6 +324,7 @@ do {									\
         unsigned int p;                                                 \
                                                                         \
         clear_thread_flag(TIF_32BIT_REGS);                              \
+        clear_thread_flag(TIF_32BIT_FPREGS);                            \
         clear_thread_flag(TIF_32BIT_ADDR);                              \
                                                                         \
         if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index dfaaf493e9d4..8c012af2f451 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -71,38 +71,7 @@ enum fixed_addresses {
 #define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #define kmap_get_fixmap_pte(vaddr)                                      \
         pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index d088e5db4903..cfe092fc720d 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -33,11 +33,48 @@ extern void _init_fpu(void);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
 
-#define __enable_fpu()                                                  \
-do {                                                                    \
-        set_c0_status(ST0_CU1);                                         \
-        enable_fpu_hazard();                                            \
-} while (0)
+/*
+ * This enum specifies a mode in which we want the FPU to operate, for cores
+ * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT
+ * purposefully have the values 0 & 1 respectively, so that an integer value
+ * of Status.FR can be trivially casted to the corresponding enum fpu_mode.
+ */
+enum fpu_mode {
+        FPU_32BIT = 0,          /* FR = 0 */
+        FPU_64BIT,              /* FR = 1 */
+        FPU_AS_IS,
+};
+
+static inline int __enable_fpu(enum fpu_mode mode)
+{
+        int fr;
+
+        switch (mode) {
+        case FPU_AS_IS:
+                /* just enable the FPU in its current mode */
+                set_c0_status(ST0_CU1);
+                enable_fpu_hazard();
+                return 0;
+
+        case FPU_64BIT:
+#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))
+                /* we only have a 32-bit FPU */
+                return SIGFPE;
+#endif
+                /* fall through */
+        case FPU_32BIT:
+                /* set CU1 & change FR appropriately */
+                fr = (int)mode;
+                change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
+                enable_fpu_hazard();
+
+                /* check FR has the desired value */
+                return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
+
+        default:
+                BUG();
+        }
+}
 
 #define __disable_fpu()                                                 \
 do {                                                                    \
@@ -45,19 +82,6 @@ do {									\
         disable_fpu_hazard();                                           \
 } while (0)
 
-#define enable_fpu()                                                    \
-do {                                                                    \
-        if (cpu_has_fpu)                                                \
-                __enable_fpu();                                         \
-} while (0)
-
-#define disable_fpu()                                                   \
-do {                                                                    \
-        if (cpu_has_fpu)                                                \
-                __disable_fpu();                                        \
-} while (0)
-
-
 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
 
 static inline int __is_fpu_owner(void)
@@ -70,27 +94,46 @@ static inline int is_fpu_owner(void)
         return cpu_has_fpu && __is_fpu_owner();
 }
 
-static inline void __own_fpu(void)
+static inline int __own_fpu(void)
 {
-        __enable_fpu();
+        enum fpu_mode mode;
+        int ret;
+
+        mode = !test_thread_flag(TIF_32BIT_FPREGS);
+        ret = __enable_fpu(mode);
+        if (ret)
+                return ret;
+
         KSTK_STATUS(current) |= ST0_CU1;
+        if (mode == FPU_64BIT)
+                KSTK_STATUS(current) |= ST0_FR;
+        else /* mode == FPU_32BIT */
+                KSTK_STATUS(current) &= ~ST0_FR;
+
         set_thread_flag(TIF_USEDFPU);
+        return 0;
 }
 
-static inline void own_fpu_inatomic(int restore)
+static inline int own_fpu_inatomic(int restore)
 {
+        int ret = 0;
+
         if (cpu_has_fpu && !__is_fpu_owner()) {
-                __own_fpu();
-                if (restore)
+                ret = __own_fpu();
+                if (restore && !ret)
                         _restore_fp(current);
         }
+        return ret;
 }
 
-static inline void own_fpu(int restore)
+static inline int own_fpu(int restore)
 {
+        int ret;
+
         preempt_disable();
-        own_fpu_inatomic(restore);
+        ret = own_fpu_inatomic(restore);
         preempt_enable();
+        return ret;
 }
 
 static inline void lose_fpu(int save)
@@ -106,16 +149,21 @@ static inline void lose_fpu(int save)
         preempt_enable();
 }
 
-static inline void init_fpu(void)
+static inline int init_fpu(void)
 {
+        int ret = 0;
+
         preempt_disable();
         if (cpu_has_fpu) {
-                __own_fpu();
-                _init_fpu();
+                ret = __own_fpu();
+                if (!ret)
+                        _init_fpu();
         } else {
                 fpu_emulator_init_fpu();
         }
+
         preempt_enable();
+        return ret;
 }
 
 static inline void save_fp(struct task_struct *tsk)
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index b0dd0c84df70..572e63ec2a38 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -19,7 +19,6 @@
 
 #ifdef __KERNEL__
 
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/uaccess.h>
 #include <asm/kmap_types.h>
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 32966969f2f9..a995fce87791 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -391,9 +391,6 @@ struct kvm_vcpu_arch {
         uint32_t guest_kernel_asid[NR_CPUS];
         struct mm_struct guest_kernel_mm, guest_user_mm;
 
-        struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
-
-
         struct hrtimer comparecount_timer;
 
         int last_sched_cpu;
@@ -529,7 +526,6 @@ extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 
 extern void kvm_mips_dump_host_tlbs(void);
 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
-extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
@@ -541,10 +537,7 @@ extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu
                                                    unsigned long gva);
 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
                                     struct kvm_vcpu *vcpu);
-extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
-extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
 extern void kvm_local_flush_tlb_all(void);
-extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index b86a1253a5bf..cd41e93bc1d8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -16,7 +16,6 @@
 #define __ASM_MACH_AR71XX_REGS_H
 
 #include <linux/types.h>
-#include <linux/init.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
 
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index cc7563ba1cbf..7527c1d33d02 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
                                  const char *prefix);
 #endif
 
+void bcm47xx_set_system_type(u16 chip_id);
+
 #endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 00867dd05a69..40005fb39618 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -66,6 +66,7 @@ enum bcm47xx_board {
         BCM47XX_BOARD_LINKSYS_WRT310NV1,
         BCM47XX_BOARD_LINKSYS_WRT310NV2,
         BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
+        BCM47XX_BOARD_LINKSYS_WRT54GSV1,
         BCM47XX_BOARD_LINKSYS_WRT610NV1,
         BCM47XX_BOARD_LINKSYS_WRT610NV2,
         BCM47XX_BOARD_LINKSYS_WRTSL54GS,
diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..b7992cd4aaf9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,82 @@
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_watch                   1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_watch                   0
+#endif
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+
+/* cpu_has_mips16 */
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_rixi                    0
+#define cpu_has_mmips                   0
+#define cpu_has_smartmips               0
+#define cpu_has_vtag_icache             0
+/* cpu_has_dc_aliases */
+#define cpu_has_ic_fills_f_dc           0
+#define cpu_has_pindexed_dcache         0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_mips_2                  1
+#define cpu_has_mips_3                  0
+#define cpu_has_mips32r1                1
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_mips32r2                1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_mips32r2                0
+#endif
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_dsp                     1
+#define cpu_has_dsp2                    1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_dsp                     0
+#define cpu_has_dsp2                    0
+#endif
+#define cpu_has_mipsmt                  0
+/* cpu_has_userlocal */
+
+#define cpu_has_nofpuex                 0
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_has_vint                    1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_has_vint                    0
+#endif
+#define cpu_has_veic                    0
+#define cpu_has_inclusive_pcaches       0
+
+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
+#define cpu_dcache_line_size()          32
+#define cpu_icache_line_size()          32
+#define cpu_has_perf_cntr_intr_bit      1
+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+#define cpu_has_perf_cntr_intr_bit      0
+#endif
+#define cpu_scache_line_size()          0
+#define cpu_has_vz                      0
+
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 19f9134bfe2f..3112f08f0c72 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
         RSET_UART1,
         RSET_GPIO,
         RSET_SPI,
+        RSET_HSSPI,
         RSET_UDC0,
         RSET_OHCI0,
         RSET_OHCI_PRIV,
@@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
 #define RSET_ENETDMAS_SIZE(chans)       (16 * (chans))
 #define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
+#define RSET_HSSPI_SIZE                 1536
 #define RSET_UDC_SIZE                   256
 #define RSET_OHCI_SIZE                  256
 #define RSET_EHCI_SIZE                  256
@@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
 #define BCM_6328_UART1_BASE             (0xb0000120)
 #define BCM_6328_GPIO_BASE              (0xb0000080)
 #define BCM_6328_SPI_BASE               (0xdeadbeef)
+#define BCM_6328_HSSPI_BASE             (0xb0001000)
 #define BCM_6328_UDC0_BASE              (0xdeadbeef)
 #define BCM_6328_USBDMA_BASE            (0xb000c000)
 #define BCM_6328_OHCI0_BASE             (0xb0002600)
@@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE             (0xdeadbeef)
 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 #define BCM_6338_SPI_BASE               (0xfffe0c00)
+#define BCM_6338_HSSPI_BASE             (0xdeadbeef)
 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
@@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE             (0xdeadbeef)
 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 #define BCM_6345_SPI_BASE               (0xdeadbeef)
+#define BCM_6345_HSSPI_BASE             (0xdeadbeef)
 #define BCM_6345_UDC0_BASE              (0xdeadbeef)
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
@@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE             (0xdeadbeef)
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
+#define BCM_6348_HSSPI_BASE             (0xdeadbeef)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 #define BCM_6348_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
@@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART1_BASE             (0xfffe0120)
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 #define BCM_6358_SPI_BASE               (0xfffe0800)
+#define BCM_6358_HSSPI_BASE             (0xdeadbeef)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
 #define BCM_6358_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
@@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
 #define BCM_6368_UART1_BASE             (0xb0000120)
 #define BCM_6368_GPIO_BASE              (0xb0000080)
 #define BCM_6368_SPI_BASE               (0xb0000800)
+#define BCM_6368_HSSPI_BASE             (0xdeadbeef)
 #define BCM_6368_UDC0_BASE              (0xdeadbeef)
 #define BCM_6368_USBDMA_BASE            (0xb0004800)
 #define BCM_6368_OHCI0_BASE             (0xb0001600)
@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base;
         __GEN_RSET_BASE(__cpu, UART1)                                   \
         __GEN_RSET_BASE(__cpu, GPIO)                                    \
         __GEN_RSET_BASE(__cpu, SPI)                                     \
+        __GEN_RSET_BASE(__cpu, HSSPI)                                   \
         __GEN_RSET_BASE(__cpu, UDC0)                                    \
         __GEN_RSET_BASE(__cpu, OHCI0)                                   \
         __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base;
         [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
         [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
         [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
+        [RSET_HSSPI]            = BCM_## __cpu ##_HSSPI_BASE,           \
         [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
         [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
         [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
@@ -727,6 +737,7 @@ enum bcm63xx_irq {
         IRQ_ENET0,
         IRQ_ENET1,
         IRQ_ENET_PHY,
+        IRQ_HSSPI,
         IRQ_OHCI0,
         IRQ_EHCI0,
         IRQ_USBD,
@@ -815,6 +826,7 @@ enum bcm63xx_irq {
 #define BCM_6328_ENET0_IRQ              0
 #define BCM_6328_ENET1_IRQ              0
 #define BCM_6328_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6328_HSSPI_IRQ              (IRQ_INTERNAL_BASE + 29)
 #define BCM_6328_OHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 9)
 #define BCM_6328_EHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 10)
 #define BCM_6328_USBD_IRQ               (IRQ_INTERNAL_BASE + 4)
@@ -860,6 +872,7 @@ enum bcm63xx_irq {
 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6338_ENET1_IRQ              0
 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6338_HSSPI_IRQ              0
 #define BCM_6338_OHCI0_IRQ              0
 #define BCM_6338_EHCI0_IRQ              0
 #define BCM_6338_USBD_IRQ               0
@@ -898,6 +911,7 @@ enum bcm63xx_irq {
 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6345_ENET1_IRQ              0
 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6345_HSSPI_IRQ              0
 #define BCM_6345_OHCI0_IRQ              0
 #define BCM_6345_EHCI0_IRQ              0
 #define BCM_6345_USBD_IRQ               0
@@ -936,6 +950,7 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6348_HSSPI_IRQ              0
 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 #define BCM_6348_EHCI0_IRQ              0
 #define BCM_6348_USBD_IRQ               0
@@ -974,6 +989,7 @@ enum bcm63xx_irq {
 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6358_HSSPI_IRQ              0
 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 #define BCM_6358_USBD_IRQ               0
@@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
 #define BCM_6368_ENET0_IRQ              0
 #define BCM_6368_ENET1_IRQ              0
 #define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_HSSPI_IRQ              0
 #define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6368_USBD_IRQ               (IRQ_INTERNAL_BASE + 8)
@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
         [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
         [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
         [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
+        [IRQ_HSSPI]             = BCM_## __cpu ##_HSSPI_IRQ,            \
         [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
         [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
         [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
new file mode 100644
index 000000000000..1b1acafb3d79
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
@@ -0,0 +1,8 @@
+#ifndef BCM63XX_DEV_HSSPI_H
+#define BCM63XX_DEV_HSSPI_H
+
+#include <linux/types.h>
+
+int bcm63xx_hsspi_register(void);
+
+#endif /* BCM63XX_DEV_HSSPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 9875db31d883..ab427f8814e6 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -463,126 +463,6 @@
 #define WDT_SOFTRESET_REG               0xc
 
 /*************************************************************************
- * _REG relative to RSET_UARTx
- *************************************************************************/
-
-/* UART Control Register */
-#define UART_CTL_REG                    0x0
-#define UART_CTL_RXTMOUTCNT_SHIFT       0
-#define UART_CTL_RXTMOUTCNT_MASK        (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
-#define UART_CTL_RSTTXDN_SHIFT          5
-#define UART_CTL_RSTTXDN_MASK           (1 << UART_CTL_RSTTXDN_SHIFT)
-#define UART_CTL_RSTRXFIFO_SHIFT                6
-#define UART_CTL_RSTRXFIFO_MASK         (1 << UART_CTL_RSTRXFIFO_SHIFT)
-#define UART_CTL_RSTTXFIFO_SHIFT                7
-#define UART_CTL_RSTTXFIFO_MASK         (1 << UART_CTL_RSTTXFIFO_SHIFT)
-#define UART_CTL_STOPBITS_SHIFT         8
-#define UART_CTL_STOPBITS_MASK          (0xf << UART_CTL_STOPBITS_SHIFT)
-#define UART_CTL_STOPBITS_1             (0x7 << UART_CTL_STOPBITS_SHIFT)
-#define UART_CTL_STOPBITS_2             (0xf << UART_CTL_STOPBITS_SHIFT)
-#define UART_CTL_BITSPERSYM_SHIFT       12
-#define UART_CTL_BITSPERSYM_MASK        (0x3 << UART_CTL_BITSPERSYM_SHIFT)
-#define UART_CTL_XMITBRK_SHIFT          14
-#define UART_CTL_XMITBRK_MASK           (1 << UART_CTL_XMITBRK_SHIFT)
-#define UART_CTL_RSVD_SHIFT             15
-#define UART_CTL_RSVD_MASK              (1 << UART_CTL_RSVD_SHIFT)
-#define UART_CTL_RXPAREVEN_SHIFT                16
-#define UART_CTL_RXPAREVEN_MASK         (1 << UART_CTL_RXPAREVEN_SHIFT)
-#define UART_CTL_RXPAREN_SHIFT          17
-#define UART_CTL_RXPAREN_MASK           (1 << UART_CTL_RXPAREN_SHIFT)
-#define UART_CTL_TXPAREVEN_SHIFT                18
-#define UART_CTL_TXPAREVEN_MASK         (1 << UART_CTL_TXPAREVEN_SHIFT)
-#define UART_CTL_TXPAREN_SHIFT          18
-#define UART_CTL_TXPAREN_MASK           (1 << UART_CTL_TXPAREN_SHIFT)
-#define UART_CTL_LOOPBACK_SHIFT         20
-#define UART_CTL_LOOPBACK_MASK          (1 << UART_CTL_LOOPBACK_SHIFT)
-#define UART_CTL_RXEN_SHIFT             21
-#define UART_CTL_RXEN_MASK              (1 << UART_CTL_RXEN_SHIFT)
-#define UART_CTL_TXEN_SHIFT             22
-#define UART_CTL_TXEN_MASK              (1 << UART_CTL_TXEN_SHIFT)
-#define UART_CTL_BRGEN_SHIFT            23
-#define UART_CTL_BRGEN_MASK             (1 << UART_CTL_BRGEN_SHIFT)
-
-/* UART Baudword register */
-#define UART_BAUD_REG                   0x4
-
-/* UART Misc Control register */
-#define UART_MCTL_REG                   0x8
-#define UART_MCTL_DTR_SHIFT             0
-#define UART_MCTL_DTR_MASK              (1 << UART_MCTL_DTR_SHIFT)
-#define UART_MCTL_RTS_SHIFT             1
-#define UART_MCTL_RTS_MASK              (1 << UART_MCTL_RTS_SHIFT)
-#define UART_MCTL_RXFIFOTHRESH_SHIFT    8
-#define UART_MCTL_RXFIFOTHRESH_MASK     (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
-#define UART_MCTL_TXFIFOTHRESH_SHIFT    12
-#define UART_MCTL_TXFIFOTHRESH_MASK     (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
-#define UART_MCTL_RXFIFOFILL_SHIFT      16
-#define UART_MCTL_RXFIFOFILL_MASK       (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
-#define UART_MCTL_TXFIFOFILL_SHIFT      24
-#define UART_MCTL_TXFIFOFILL_MASK       (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
-
-/* UART External Input Configuration register */
-#define UART_EXTINP_REG                 0xc
-#define UART_EXTINP_RI_SHIFT            0
-#define UART_EXTINP_RI_MASK             (1 << UART_EXTINP_RI_SHIFT)
-#define UART_EXTINP_CTS_SHIFT           1
-#define UART_EXTINP_CTS_MASK            (1 << UART_EXTINP_CTS_SHIFT)
-#define UART_EXTINP_DCD_SHIFT           2
-#define UART_EXTINP_DCD_MASK            (1 << UART_EXTINP_DCD_SHIFT)
-#define UART_EXTINP_DSR_SHIFT           3
-#define UART_EXTINP_DSR_MASK            (1 << UART_EXTINP_DSR_SHIFT)
-#define UART_EXTINP_IRSTAT(x)           (1 << (x + 4))
-#define UART_EXTINP_IRMASK(x)           (1 << (x + 8))
-#define UART_EXTINP_IR_RI               0
-#define UART_EXTINP_IR_CTS              1
-#define UART_EXTINP_IR_DCD              2
-#define UART_EXTINP_IR_DSR              3
-#define UART_EXTINP_RI_NOSENSE_SHIFT    16
-#define UART_EXTINP_RI_NOSENSE_MASK     (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
-#define UART_EXTINP_CTS_NOSENSE_SHIFT   17
-#define UART_EXTINP_CTS_NOSENSE_MASK    (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
-#define UART_EXTINP_DCD_NOSENSE_SHIFT   18
-#define UART_EXTINP_DCD_NOSENSE_MASK    (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
-#define UART_EXTINP_DSR_NOSENSE_SHIFT   19
-#define UART_EXTINP_DSR_NOSENSE_MASK    (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
-
-/* UART Interrupt register */
-#define UART_IR_REG                     0x10
-#define UART_IR_MASK(x)                 (1 << (x + 16))
-#define UART_IR_STAT(x)                 (1 << (x))
-#define UART_IR_EXTIP                   0
-#define UART_IR_TXUNDER                 1
-#define UART_IR_TXOVER                  2
-#define UART_IR_TXTRESH                 3
-#define UART_IR_TXRDLATCH               4
-#define UART_IR_TXEMPTY                 5
-#define UART_IR_RXUNDER                 6
-#define UART_IR_RXOVER                  7
-#define UART_IR_RXTIMEOUT               8
-#define UART_IR_RXFULL                  9
-#define UART_IR_RXTHRESH                10
-#define UART_IR_RXNOTEMPTY              11
-#define UART_IR_RXFRAMEERR              12
-#define UART_IR_RXPARERR                13
-#define UART_IR_RXBRK                   14
-#define UART_IR_TXDONE                  15
-
-/* UART Fifo register */
-#define UART_FIFO_REG                   0x14
-#define UART_FIFO_VALID_SHIFT           0
-#define UART_FIFO_VALID_MASK            0xff
-#define UART_FIFO_FRAMEERR_SHIFT        8
-#define UART_FIFO_FRAMEERR_MASK         (1 << UART_FIFO_FRAMEERR_SHIFT)
-#define UART_FIFO_PARERR_SHIFT          9
-#define UART_FIFO_PARERR_MASK           (1 << UART_FIFO_PARERR_SHIFT)
-#define UART_FIFO_BRKDET_SHIFT          10
-#define UART_FIFO_BRKDET_MASK           (1 << UART_FIFO_BRKDET_SHIFT)
-#define UART_FIFO_ANYERR_MASK           (UART_FIFO_FRAMEERR_MASK |      \
-                                        UART_FIFO_PARERR_MASK |         \
-                                        UART_FIFO_BRKDET_MASK)
-
-
-/*************************************************************************
  * _REG relative to RSET_GPIO
  *************************************************************************/
 
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index a9e8f6b62b0b..7629c35986f7 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -49,11 +49,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 
 static inline int plat_device_is_coherent(struct device *dev)
 {
-#ifdef CONFIG_DMA_COHERENT
-        return 1;
-#else
         return coherentio;
-#endif
 }
 
 #ifdef CONFIG_SWIOTLB
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 5b5cd689a2f7..e2561d99a3fe 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -9,7 +9,6 @@
 #define __ASM_MACH_GENERIC_FLOPPY_H
 
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/sched.h>
 #include <linux/linkage.h>
diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
index affa66f5c2da..4ae5fbcb15a5 100644
--- a/arch/mips/include/asm/mach-generic/ide.h
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -23,7 +23,7 @@
 static inline void __ide_flush_prologue(void)
 {
 #ifdef CONFIG_SMP
-        if (cpu_has_dc_aliases)
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
                 preempt_disable();
 #endif
 }
@@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void)
 static inline void __ide_flush_epilogue(void)
 {
 #ifdef CONFIG_SMP
-        if (cpu_has_dc_aliases)
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
                 preempt_enable();
 #endif
 }
 
 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
 {
-        if (cpu_has_dc_aliases) {
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
                 unsigned long end = addr + size;
 
                 while (addr < end) {
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 62aa1e287fba..4b86c88a03b7 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -9,7 +9,6 @@
 #define __ASM_MACH_JAZZ_FLOPPY_H
 
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
 #include <linux/mm.h>
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 05988c2d6565..069b43a9da6f 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -21,6 +21,7 @@
 
 extern struct platform_device jz4740_usb_ohci_device;
 extern struct platform_device jz4740_udc_device;
+extern struct platform_device jz4740_udc_xceiv_device;
 extern struct platform_device jz4740_mmc_device;
 extern struct platform_device jz4740_rtc_device;
 extern struct platform_device jz4740_i2c_device;
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index 868ed8a2ed5c..c0dbd530cca6 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -9,7 +9,8 @@
 #define __ASM_NETLOGIC_IRQ_H
 
 #include <asm/mach-netlogic/multi-node.h>
-#define NR_IRQS                 (64 * NLM_NR_NODES)
+#define NLM_IRQS_PER_NODE       1024
+#define NR_IRQS                 (NLM_IRQS_PER_NODE * NLM_NR_NODES)
 
 #define MIPS_CPU_IRQ_BASE       0
 
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index d62fc773f4d7..9ed8dacdc37c 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -47,8 +47,37 @@
 #endif
 #endif
 
-#define NLM_CORES_PER_NODE      8
 #define NLM_THREADS_PER_CORE    4
-#define NLM_CPUS_PER_NODE       (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
+#ifdef CONFIG_CPU_XLR
+#define nlm_cores_per_node()    8
+#else
+extern unsigned int xlp_cores_per_node;
+#define nlm_cores_per_node()    xlp_cores_per_node
+#endif
+
+#define nlm_threads_per_node()  (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
+#define nlm_cpuid_to_node(c)    ((c) / nlm_threads_per_node())
+
+struct nlm_soc_info {
+        unsigned long   coremask;       /* cores enabled on the soc */
+        unsigned long   ebase;          /* not used now */
+        uint64_t        irqmask;        /* EIMR for the node */
+        uint64_t        sysbase;        /* only for XLP - sys block base */
+        uint64_t        picbase;        /* PIC block base */
+        spinlock_t      piclock;        /* lock for PIC access */
+        cpumask_t       cpumask;        /* logical cpu mask for node */
+        unsigned int    socbus;
+};
+
+extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
+#define nlm_get_node(i)         (&nlm_nodes[i])
+#define nlm_node_present(n)     ((n) >= 0 && (n) < NLM_NR_NODES && \
+                                        nlm_get_node(n)->coremask != 0)
+#ifdef CONFIG_CPU_XLR
+#define nlm_current_node()      (&nlm_nodes[0])
+#else
+#define nlm_current_node()      (&nlm_nodes[nlm_nodeid()])
+#endif
+void nlm_node_init(int node);
 
 #endif
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
new file mode 100644
index 000000000000..0da99fa11c38
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/topology.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ */
+#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
+#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
+
+#include <asm/mach-netlogic/multi-node.h>
+
+#define topology_physical_package_id(cpu)       cpu_to_node(cpu)
+#define topology_core_id(cpu)   (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
+#define topology_thread_cpumask(cpu)            (&cpu_sibling_map[cpu])
+#define topology_core_cpumask(cpu)      cpumask_of_node(cpu_to_node(cpu))
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index e33227998713..836e2ede24de 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -26,6 +26,10 @@
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE        (1 << 7)
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK           0xf
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX            16
+/* SERIRQ Control */
+#define PIIX4_FUNC0_SERIRQC                     0x64
+#define   PIIX4_FUNC0_SERIRQC_EN                        (1 << 7)
+#define   PIIX4_FUNC0_SERIRQC_CONT                      (1 << 6)
 /* Top Of Memory */
 #define PIIX4_FUNC0_TOM                         0x69
 #define   PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK            0xf0
@@ -34,6 +38,9 @@
 #define   PIIX4_FUNC0_DLC_USBPR_EN                      (1 << 2)
 #define   PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN            (1 << 1)
 #define   PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN        (1 << 0)
+/* General Configuration */
+#define PIIX4_FUNC0_GENCFG                      0xb0
+#define   PIIX4_FUNC0_GENCFG_SERIRQ                     (1 << 16)
 
 /* IDE Timing */
 #define PIIX4_FUNC1_IDETIM_PRIMARY_LO           0x40
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index e0331414c7d6..bbc3dd4294bc 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -14,6 +14,7 @@
 #define _ASM_MIPSREGS_H
 
 #include <linux/linkage.h>
+#include <linux/types.h>
 #include <asm/hazards.h>
 #include <asm/war.h>
 
@@ -573,7 +574,9 @@
 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
+#define MIPS_CONF1_TLBS_SHIFT   (25)
+#define MIPS_CONF1_TLBS_SIZE    (6)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 
 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
@@ -587,21 +590,53 @@
 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
+#define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
-
+#define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT       (0)
+#define MIPS_CONF4_FTLBSETS_SHIFT       (0)
+#define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
+#define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
+#define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 
 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
@@ -611,11 +646,15 @@
 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 
 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
+/* proAptiv FTLB on/off bit */
+#define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 
+/*  EntryHI bit definition */
+#define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -628,6 +667,26 @@
 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT    9
+#define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT    4
+#define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT    3
+#define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT     0
+#define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK        _ULCAST_(7)
+#define MIPS_SEGCFG_USK         _ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
+#define MIPS_SEGCFG_MUSK        _ULCAST_(3)
+#define MIPS_SEGCFG_MSK         _ULCAST_(2)
+#define MIPS_SEGCFG_MK          _ULCAST_(1)
+#define MIPS_SEGCFG_UK          _ULCAST_(0)
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -649,6 +708,19 @@ static inline int mm_insn_16bit(u16 insn)
 }
 
 /*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noreorder\n\t"
+                ".word 0x42000004\n\t" /* tlbinvf */
+                ".set pop");
+}
+
+
+/*
  * Functions to access the R10000 performance counters.  These are basically
  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
  * performance counter number encoded into bits 1 ... 5 of the instruction.
@@ -1102,6 +1174,15 @@ do {									\
 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
 
+/* MIPSR3 */
+#define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
 
 /* Cavium OCTEON (cnMIPS) */
 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index bb68c3398c80..c281f03eb312 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -84,7 +84,6 @@ nlm_set_nmi_handler(void *handler)
  */
 void nlm_init_boot_cpu(void);
 unsigned int nlm_get_cpu_frequency(void);
-void nlm_node_init(int node);
 extern struct plat_smp_ops nlm_smp_ops;
 extern char nlm_reset_entry[], nlm_reset_entry_end[];
 
@@ -94,26 +93,16 @@ extern struct dma_map_ops nlm_swiotlb_dma_ops;
 extern unsigned int nlm_threads_per_core;
 extern cpumask_t nlm_cpumask;
 
-struct nlm_soc_info {
-        unsigned long coremask; /* cores enabled on the soc */
-        unsigned long ebase;
-        uint64_t irqmask;
-        uint64_t sysbase;       /* only for XLP */
-        uint64_t picbase;
-        spinlock_t piclock;
-};
-
-#define nlm_get_node(i)         (&nlm_nodes[i])
-#ifdef CONFIG_CPU_XLR
-#define nlm_current_node()      (&nlm_nodes[0])
-#else
-#define nlm_current_node()      (&nlm_nodes[nlm_nodeid()])
-#endif
-
 struct irq_data;
 uint64_t nlm_pci_irqmask(int node);
+void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
 void nlm_set_pic_extra_ack(int node, int irq,  void (*xack)(struct irq_data *));
 
+#ifdef CONFIG_PCI_MSI
+void nlm_dispatch_msi(int node, int lirq);
+void nlm_dispatch_msix(int node, int msixirq);
+#endif
+
 /*
  * The NR_IRQs is divided between nodes, each of them has a separate irq space
  */
@@ -122,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq)
         return node * NR_IRQS / NLM_NR_NODES + irq;
 }
 
-extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 extern int nlm_cpu_ready[];
 #endif
 #endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index f299d31d7c1a..de9aada6f4c1 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -146,7 +146,12 @@ static inline int hard_smp_processor_id(void)
 
 static inline int nlm_nodeid(void)
 {
-        return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
+        uint32_t prid = read_c0_prid();
+
+        if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
+                return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
+        else
+                return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
 }
 
 static inline unsigned int nlm_core_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 4e8eacb9588a..3067f983495d 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -69,44 +69,9 @@
 #define BRIDGE_FLASH_LIMIT3             0x13
 
 #define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
-#define BRIDGE_DRAM_BAR0                0x14
-#define BRIDGE_DRAM_BAR1                0x15
-#define BRIDGE_DRAM_BAR2                0x16
-#define BRIDGE_DRAM_BAR3                0x17
-#define BRIDGE_DRAM_BAR4                0x18
-#define BRIDGE_DRAM_BAR5                0x19
-#define BRIDGE_DRAM_BAR6                0x1a
-#define BRIDGE_DRAM_BAR7                0x1b
-
 #define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
-#define BRIDGE_DRAM_LIMIT0              0x1c
-#define BRIDGE_DRAM_LIMIT1              0x1d
-#define BRIDGE_DRAM_LIMIT2              0x1e
-#define BRIDGE_DRAM_LIMIT3              0x1f
-#define BRIDGE_DRAM_LIMIT4              0x20
-#define BRIDGE_DRAM_LIMIT5              0x21
-#define BRIDGE_DRAM_LIMIT6              0x22
-#define BRIDGE_DRAM_LIMIT7              0x23
-
 #define BRIDGE_DRAM_NODE_TRANSLN(i)     (0x24 + (i))
-#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
-#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
-#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
-#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
-#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
-#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
-#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
-#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
-
 #define BRIDGE_DRAM_CHNL_TRANSLN(i)     (0x2c + (i))
-#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
-#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
-#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
-#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
-#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
-#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
-#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
-#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
 
 #define BRIDGE_PCIEMEM_BASE0            0x34
 #define BRIDGE_PCIEMEM_BASE1            0x35
@@ -178,12 +143,42 @@
 #define BRIDGE_GIO_WEIGHT               0x2cb
 #define BRIDGE_FLASH_WEIGHT             0x2cc
 
+/* FIXME verify */
+#define BRIDGE_9XX_FLASH_BAR(i)         (0x11 + (i))
+#define BRIDGE_9XX_FLASH_BAR_LIMIT(i)   (0x15 + (i))
+
+#define BRIDGE_9XX_DRAM_BAR(i)          (0x19 + (i))
+#define BRIDGE_9XX_DRAM_LIMIT(i)        (0x29 + (i))
+#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
+#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
+
+#define BRIDGE_9XX_ADDRESS_ERROR0       0x9d
+#define BRIDGE_9XX_ADDRESS_ERROR1       0x9e
+#define BRIDGE_9XX_ADDRESS_ERROR2       0x9f
+
+#define BRIDGE_9XX_PCIEMEM_BASE0        0x59
+#define BRIDGE_9XX_PCIEMEM_BASE1        0x5a
+#define BRIDGE_9XX_PCIEMEM_BASE2        0x5b
+#define BRIDGE_9XX_PCIEMEM_BASE3        0x5c
+#define BRIDGE_9XX_PCIEMEM_LIMIT0       0x5d
+#define BRIDGE_9XX_PCIEMEM_LIMIT1       0x5e
+#define BRIDGE_9XX_PCIEMEM_LIMIT2       0x5f
+#define BRIDGE_9XX_PCIEMEM_LIMIT3       0x60
+#define BRIDGE_9XX_PCIEIO_BASE0         0x61
+#define BRIDGE_9XX_PCIEIO_BASE1         0x62
+#define BRIDGE_9XX_PCIEIO_BASE2         0x63
+#define BRIDGE_9XX_PCIEIO_BASE3         0x64
+#define BRIDGE_9XX_PCIEIO_LIMIT0        0x65
+#define BRIDGE_9XX_PCIEIO_LIMIT1        0x66
+#define BRIDGE_9XX_PCIEIO_LIMIT2        0x67
+#define BRIDGE_9XX_PCIEIO_LIMIT3        0x68
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
 #define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
-#define nlm_get_bridge_pcibase(node)    \
-                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_pcibase(node)    nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
 #define nlm_get_bridge_regbase(node)    \
                         (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 55eee77adaca..1f23dfaa7167 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -48,8 +48,10 @@
 #define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
 #define XLP_IO_PCI_HDRSZ                0x100
 #define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
-#define XLP_HDR_OFFSET(node, bus, dev, fn)      (((bus) << 20) | \
-                                ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
+#define XLP_IO_PCI_OFFSET(b, d, f)      (((b) << 20) | ((d) << 15) | ((f) << 12))
+
+#define XLP_HDR_OFFSET(node, bus, dev, fn) \
+                XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
 
 #define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
 /* coherent inter chip */
@@ -109,6 +111,36 @@
 #define XLP_IO_MMC_OFFSET(node, slot)   \
                 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
 
+/* Things have changed drastically in XLP 9XX */
+#define XLP9XX_HDR_OFFSET(n, d, f)      \
+                        XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
+
+#define XLP9XX_IO_BRIDGE_OFFSET(node)   XLP_IO_PCI_OFFSET(0, 0, node)
+#define XLP9XX_IO_PIC_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 2, 0)
+#define XLP9XX_IO_UART_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 2, 2)
+#define XLP9XX_IO_SYS_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 6, 0)
+#define XLP9XX_IO_FUSE_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 1)
+#define XLP9XX_IO_JTAG_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 4)
+
+#define XLP9XX_IO_PCIE_OFFSET(node, i)  XLP9XX_HDR_OFFSET(node, 1, i)
+#define XLP9XX_IO_PCIE0_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 0)
+#define XLP9XX_IO_PCIE2_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 2)
+#define XLP9XX_IO_PCIE3_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 3)
+
+/* XLP9xx USB block */
+#define XLP9XX_IO_USB_OFFSET(node, i)           XLP9XX_HDR_OFFSET(node, 4, i)
+#define XLP9XX_IO_USB_XHCI0_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 1)
+#define XLP9XX_IO_USB_XHCI1_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 2)
+
+/* XLP9XX on-chip SATA controller */
+#define XLP9XX_IO_SATA_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 3, 2)
+
+#define XLP9XX_IO_NOR_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 0)
+#define XLP9XX_IO_NAND_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 7, 1)
+#define XLP9XX_IO_SPI_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 2)
+/* SD flash */
+#define XLP9XX_IO_MMCSD_OFFSET(node)            XLP9XX_HDR_OFFSET(node, 7, 3)
+
 /* PCI config header register id's */
 #define XLP_PCI_CFGREG0                 0x00
 #define XLP_PCI_CFGREG1                 0x01
@@ -156,11 +188,23 @@
 #define PCI_DEVICE_ID_NLM_MMC           0x1018
 #define PCI_DEVICE_ID_NLM_XHCI          0x101d
 
+#define PCI_DEVICE_ID_XLP9XX_SATA       0x901A
+#define PCI_DEVICE_ID_XLP9XX_XHCI       0x901D
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
 #define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
 
+static inline int xlp9xx_get_socbus(int node)
+{
+        uint64_t socbridge;
+
+        if (node == 0)
+                return 1;
+        socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
+        return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
+}
 #endif /* !__ASSEMBLY */
 
 #endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index b559cb9f56ea..d4deb87ad069 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -52,25 +52,48 @@
 #define PCIE_BYTE_SWAP_MEM_LIM          0x248
 #define PCIE_BYTE_SWAP_IO_BASE          0x249
 #define PCIE_BYTE_SWAP_IO_LIM           0x24A
+
+#define PCIE_BRIDGE_MSIX_ADDR_BASE      0x24F
+#define PCIE_BRIDGE_MSIX_ADDR_LIMIT     0x250
 #define PCIE_MSI_STATUS                 0x25A
 #define PCIE_MSI_EN                     0x25B
+#define PCIE_MSIX_STATUS                0x25D
+#define PCIE_INT_STATUS0                0x25F
+#define PCIE_INT_STATUS1                0x260
 #define PCIE_INT_EN0                    0x261
+#define PCIE_INT_EN1                    0x262
 
-/* PCIE_MSI_EN */
-#define PCIE_MSI_VECTOR_INT_EN          0xFFFFFFFF
+/* XLP9XX has basic changes */
+#define PCIE_9XX_BYTE_SWAP_MEM_BASE     0x25c
+#define PCIE_9XX_BYTE_SWAP_MEM_LIM      0x25d
+#define PCIE_9XX_BYTE_SWAP_IO_BASE      0x25e
+#define PCIE_9XX_BYTE_SWAP_IO_LIM       0x25f
 
-/* PCIE_INT_EN0 */
-#define PCIE_MSI_INT_EN                 (1 << 9)
+/* other */
+#define PCIE_NLINKS                     4
 
+/* MSI addresses */
+#define MSI_ADDR_BASE                   0xfffee00000ULL
+#define MSI_ADDR_SZ                     0x10000
+#define MSI_LINK_ADDR(n, l)             (MSI_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
+#define MSIX_ADDR_BASE                  0xfffef00000ULL
+#define MSIX_LINK_ADDR(n, l)            (MSIX_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
 #ifndef __ASSEMBLY__
 
 #define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
 #define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
-#define nlm_get_pcie_base(node, inst)   \
-                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
-#define nlm_get_pcie_regbase(node, inst)        \
-                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
+#define nlm_get_pcie_base(node, inst)   nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+        XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
+
+#ifdef CONFIG_PCI_MSI
+void xlp_init_node_msi_irqs(int node, int link);
+#else
+static inline void xlp_init_node_msi_irqs(int node, int link) {}
+#endif
+
+struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
 
-int xlp_pcie_link_irt(int link);
 #endif
 #endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 105389b79f09..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
 #define PIC_IRT0                0x74
 #define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
 
-#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
+#define PIC_9XX_PENDING_0       0x6
+#define PIC_9XX_PENDING_1       0x8
+#define PIC_9XX_PENDING_2       0xa
+#define PIC_9XX_PENDING_3       0xc
+
+#define PIC_9XX_IRT0            0x1c0
+#define PIC_9XX_IRT(i)          (PIC_9XX_IRT0 + ((i) * 2))
 
 /*
  *    IRT Map
  */
 #define PIC_NUM_IRTS            160
+#define PIC_9XX_NUM_IRTS        256
 
 #define PIC_IRT_WD_0_INDEX      0
 #define PIC_IRT_WD_1_INDEX      1
@@ -193,14 +200,9 @@
 #define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
 
 #define PIC_CLOCK_TIMER                 7
-#define PIC_IRQ_BASE                    8
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 
-#define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
-#define PIC_IRT_LAST_IRQ                63
-#define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
-
 /*
  *   Misc
  */
@@ -210,30 +212,26 @@
 
 #define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
-#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 /* We use PIC on node 0 as a timer */
 #define pic_timer_freq()                nlm_get_pic_frequency(0)
 
 /* IRT and h/w interrupt routines */
-static inline int
-nlm_pic_read_irt(uint64_t base, int irt_index)
-{
-        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
-}
-
 static inline void
-nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int cpu)
 {
         uint64_t val;
 
-        val = nlm_read_pic_reg(base, PIC_IRT(irt));
-        /* clear cpuset and mask */
-        val &= ~((0x7ull << 16) | 0xffff);
-        /* set DB, cpuset and cpumask */
-        val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
-        nlm_write_pic_reg(base, PIC_IRT(irt), val);
+        val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
+                        ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
+                        ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
+                        (cpu & 0x3ff);
+
+        nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
 }
 
 static inline void
@@ -254,9 +252,13 @@ static inline void
 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
         int sch, int vec, int cpu)
 {
-        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
-                (cpu >> 4),             /* thread group */
-                1 << (cpu & 0xf));      /* thread mask */
+        if (cpu_is_xlp9xx())
+                nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
+                                                        1, 0, cpu);
+        else
+                nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                        (cpu >> 4),             /* thread group */
+                        1 << (cpu & 0xf));      /* thread mask */
 }
 
 static inline uint64_t
@@ -298,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        }
 }
 
 static inline void
@@ -307,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                reg &= ~((uint64_t)1 << 22);
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                reg &= ~((uint64_t)1 << 31);
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg);
+        }
 }
 
 static inline void
@@ -316,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
 {
         uint64_t ipi;
 
-        ipi = ((uint64_t)nmi << 31) | (irq << 20);
-        ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
+        if (cpu_is_xlp9xx())
+                ipi = (nmi << 23) | (irq << 24) |
+                        (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
+        else
+                ipi = ((uint64_t)nmi << 31) | (irq << 20) |
+                        ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
+
         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
 }
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index fcf2833c16ca..d9b107ffca93 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -147,13 +147,29 @@
 #define SYS_SYS_PLL_MEM_REQ                     0x2a3
 #define SYS_PLL_MEM_STAT                        0x2a4
 
+/* Registers changed on 9XX */
+#define SYS_9XX_POWER_ON_RESET_CFG              0x00
+#define SYS_9XX_CHIP_RESET                      0x01
+#define SYS_9XX_CPU_RESET                       0x02
+#define SYS_9XX_CPU_NONCOHERENT_MODE            0x03
+
+/* XLP 9XX fuse block registers */
+#define FUSE_9XX_DEVCFG6                        0xc6
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
 #define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
-#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
+/* XLP9XX fuse block */
+#define nlm_get_fuse_pcibase(node)      \
+                        nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
+#define nlm_get_fuse_regbase(node)      \
+                        (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
 unsigned int nlm_get_pic_frequency(int node);
 #endif
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 86d16e1e6072..a6c54424dd95 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -94,7 +94,8 @@
 #define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
 #define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
 #define nlm_get_uart_pcibase(node, inst)        \
-                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
+        nlm_pcicfg_base(cpu_is_xlp9xx() ?  XLP9XX_IO_UART_OFFSET(node) : \
+                                                XLP_IO_UART_OFFSET(node, inst))
 #define nlm_get_uart_regbase(node, inst)        \
                         (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 470f2095b346..2b0c9599ebe5 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -37,10 +37,9 @@
 
 #define PIC_UART_0_IRQ                  17
 #define PIC_UART_1_IRQ                  18
-#define PIC_PCIE_LINK_0_IRQ             19
-#define PIC_PCIE_LINK_1_IRQ             20
-#define PIC_PCIE_LINK_2_IRQ             21
-#define PIC_PCIE_LINK_3_IRQ             22
+
+#define PIC_PCIE_LINK_LEGACY_IRQ_BASE   19
+#define PIC_PCIE_LINK_LEGACY_IRQ(i)     (19 + (i))
 
 #define PIC_EHCI_0_IRQ                  23
 #define PIC_EHCI_1_IRQ                  24
@@ -51,6 +50,8 @@
 #define PIC_2XX_XHCI_0_IRQ              23
 #define PIC_2XX_XHCI_1_IRQ              24
 #define PIC_2XX_XHCI_2_IRQ              25
+#define PIC_9XX_XHCI_0_IRQ              23
+#define PIC_9XX_XHCI_1_IRQ              24
 
 #define PIC_MMC_IRQ                     29
 #define PIC_I2C_0_IRQ                   30
@@ -58,6 +59,23 @@
 #define PIC_I2C_2_IRQ                   32
 #define PIC_I2C_3_IRQ                   33
 
+#define PIC_PCIE_LINK_MSI_IRQ_BASE      44      /* 44 - 47 MSI IRQ */
+#define PIC_PCIE_LINK_MSI_IRQ(i)        (44 + (i))
+
+/* MSI-X with second link-level dispatch */
+#define PIC_PCIE_MSIX_IRQ_BASE          48      /* 48 - 51 MSI-X IRQ */
+#define PIC_PCIE_MSIX_IRQ(i)            (48 + (i))
+
+#define NLM_MSIX_VEC_BASE               96      /* 96 - 127 - MSIX mapped */
+#define NLM_MSI_VEC_BASE                128     /* 128 -255 - MSI mapped */
+
+#define NLM_PIC_INDIRECT_VEC_BASE       512
+#define NLM_GPIO_VEC_BASE               768
+
+#define PIC_IRQ_BASE                    8
+#define PIC_IRT_FIRST_IRQ               PIC_IRQ_BASE
+#define PIC_IRT_LAST_IRQ                63
+
 #ifndef __ASSEMBLY__
 
 /* SMP support functions */
@@ -68,6 +86,9 @@ void xlp_mmu_init(void);
 void nlm_hal_init(void);
 int xlp_get_dram_map(int n, uint64_t *dram_map);
 
+struct pci_dev;
+int xlp_socdev_to_node(const struct pci_dev *dev);
+
 /* Device tree related */
 void xlp_early_init_devtree(void);
 void *xlp_dt_init(void *fdtp);
@@ -76,8 +97,15 @@ static inline int cpu_is_xlpii(void)
 {
         int chip = read_c0_prid() & 0xff00;
 
-        return chip == PRID_IMP_NETLOGIC_XLP2XX;
+        return chip == PRID_IMP_NETLOGIC_XLP2XX ||
+                chip == PRID_IMP_NETLOGIC_XLP9XX;
 }
 
+static inline int cpu_is_xlp9xx(void)
+{
+        int chip = read_c0_prid() & 0xff00;
+
+        return chip == PRID_IMP_NETLOGIC_XLP9XX;
+}
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index c1667e0c272a..ceb991ca8436 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -35,11 +35,6 @@
 #ifndef _ASM_NLM_XLR_H
 #define _ASM_NLM_XLR_H
 
-/* Platform UART functions */
-struct uart_port;
-unsigned int nlm_xlr_uart_in(struct uart_port *, int);
-void nlm_xlr_uart_out(struct uart_port *, int, int);
-
 /* SMP helpers */
 void xlr_wakeup_secondary_cpus(void);
 
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index 41785dd0ddd0..893320375aef 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -36,6 +36,13 @@
 
 #include <asm/octeon/cvmx-helper.h>
 
+enum cvmx_helper_board_usb_clock_types {
+        USB_CLOCK_TYPE_REF_12,
+        USB_CLOCK_TYPE_REF_24,
+        USB_CLOCK_TYPE_REF_48,
+        USB_CLOCK_TYPE_CRYSTAL_12,
+};
+
 typedef enum {
         set_phy_link_flags_autoneg = 0x1,
         set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
@@ -154,4 +161,6 @@ extern int __cvmx_helper_board_interface_probe(int interface,
  */
 extern int __cvmx_helper_board_hardware_enable(int interface);
 
+enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void);
+
 #endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f6be4741f7e8..5e08bcc74897 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -11,6 +11,8 @@
 
 #include <spaces.h>
 #include <linux/const.h>
+#include <linux/kernel.h>
+#include <asm/mipsregs.h>
 
 /*
  * PAGE_SHIFT determines the page size
@@ -33,6 +35,29 @@
 #define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
 #define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
+/*
+ * This is used for calculating the real page sizes
+ * for FTLB or VTLB + FTLB confugrations.
+ */
+static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
+{
+        switch (mmuextdef) {
+        case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
+                if (PAGE_SIZE == (1 << 30))
+                        return 5;
+                if (PAGE_SIZE == (1llu << 32))
+                        return 6;
+                if (PAGE_SIZE > (256 << 10))
+                        return 7; /* reserved */
+                        /* fall through */
+        case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
+                return (PAGE_SHIFT - 10) / 2;
+        default:
+                panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
+                      mmuextdef >> 14);
+        }
+}
+
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
 #define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
index 90985b61dbd9..c1020654876e 100644
--- a/arch/mips/include/asm/rtlx.h
+++ b/arch/mips/include/asm/rtlx.h
@@ -1,13 +1,18 @@
 /*
- * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  */
-
 #ifndef __ASM_RTLX_H_
 #define __ASM_RTLX_H_
 
 #include <irq.h>
 
+#define RTLX_MODULE_NAME "rtlx"
+
 #define LX_NODE_BASE 10
 
 #define MIPS_CPU_RTLX_IRQ 0
@@ -15,18 +20,31 @@
 #define RTLX_VERSION 2
 #define RTLX_xID 0x12345600
 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
+#define RTLX_BUFFER_SIZE 2048
 #define RTLX_CHANNELS 8
 
 #define RTLX_CHANNEL_STDIO      0
 #define RTLX_CHANNEL_DBG        1
 #define RTLX_CHANNEL_SYSIO      2
 
-extern int rtlx_open(int index, int can_sleep);
-extern int rtlx_release(int index);
-extern ssize_t rtlx_read(int index, void __user *buff, size_t count);
-extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
-extern unsigned int rtlx_read_poll(int index, int can_sleep);
-extern unsigned int rtlx_write_poll(int index);
+void rtlx_starting(int vpe);
+void rtlx_stopping(int vpe);
+
+int rtlx_open(int index, int can_sleep);
+int rtlx_release(int index);
+ssize_t rtlx_read(int index, void __user *buff, size_t count);
+ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
+unsigned int rtlx_read_poll(int index, int can_sleep);
+unsigned int rtlx_write_poll(int index);
+
+int __init rtlx_module_init(void);
+void __exit rtlx_module_exit(void);
+
+void _interrupt_sp(void);
+
+extern struct vpe_notifications rtlx_notify;
+extern const struct file_operations rtlx_fops;
+extern void (*aprp_hook)(void);
 
 enum rtlx_state {
         RTLX_STATE_UNUSED = 0,
@@ -35,10 +53,15 @@ enum rtlx_state {
         RTLX_STATE_OPENED
 };
 
-#define RTLX_BUFFER_SIZE 2048
+extern struct chan_waitqueues {
+        wait_queue_head_t rt_queue;
+        wait_queue_head_t lx_queue;
+        atomic_t in_open;
+        struct mutex mutex;
+} channel_wqs[RTLX_CHANNELS];
 
 /* each channel supports read and write.
-   linux (vpe0) reads lx_buffer  and writes rt_buffer
+   linux (vpe0) reads lx_buffer and writes rt_buffer
    SP (vpe1) reads rt_buffer and writes lx_buffer
 */
 struct rtlx_channel {
@@ -55,11 +78,11 @@ struct rtlx_channel {
         char *lx_buffer;
 };
 
-struct rtlx_info {
+extern struct rtlx_info {
         unsigned long id;
         enum rtlx_state state;
+        int ap_int_pending;     /* Status of 0 or 1 for CONFIG_MIPS_CMP only */
 
         struct rtlx_channel channel[RTLX_CHANNELS];
-};
-
+} *rtlx;
 #endif /* __ASM_RTLX_H_ */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index eb0af15ac656..278d45a09728 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -19,11 +19,19 @@
 
 struct task_struct;
 
-/*
- * switch_to(n) should switch tasks to task nr n, first
- * checking that n isn't the current task, in which case it does nothing.
+/**
+ * resume - resume execution of a task
+ * @prev:       The task previously executed.
+ * @next:       The task to begin executing.
+ * @next_ti:    task_thread_info(next).
+ * @usedfpu:    Non-zero if prev's FP context should be saved.
+ *
+ * This function is used whilst scheduling to save the context of prev & load
+ * the context of next. Returns prev.
  */
-extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu);
+extern asmlinkage struct task_struct *resume(struct task_struct *prev,
+                struct task_struct *next, struct thread_info *next_ti,
+                u32 usedfpu);
 
 extern unsigned int ll_bit;
 extern struct task_struct *ll_task;
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 81c89132c59d..33e8dbfc1b63 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -29,7 +29,7 @@ static inline long syscall_get_nr(struct task_struct *task,
 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
         struct task_struct *task, struct pt_regs *regs, unsigned int n)
 {
-        unsigned long usp = regs->regs[29];
+        unsigned long usp __maybe_unused = regs->regs[29];
 
         switch (n) {
         case 0: case 1: case 2: case 3:
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 4f58ef6d0eed..24846f9053fe 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -110,11 +110,12 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NOHZ                19      /* in adaptive nohz mode */
 #define TIF_FIXADE              20      /* Fix address errors in software */
 #define TIF_LOGADE              21      /* Log address errors to syslog */
-#define TIF_32BIT_REGS          22      /* also implies 16/32 fprs */
+#define TIF_32BIT_REGS          22      /* 32-bit general purpose registers */
 #define TIF_32BIT_ADDR          23      /* 32-bit address space (o32/n32) */
 #define TIF_FPUBOUND            24      /* thread bound to FPU-full CPU set */
 #define TIF_LOAD_WATCH          25      /* If set, load watch registers */
 #define TIF_SYSCALL_TRACEPOINT  26      /* syscall tracepoint instrumentation */
+#define TIF_32BIT_FPREGS        27      /* 32-bit floating point registers */
 #define TIF_SYSCALL_TRACE       31      /* syscall trace active */
 
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -131,6 +132,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_32BIT_ADDR         (1<<TIF_32BIT_ADDR)
 #define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
+#define _TIF_32BIT_FPREGS       (1<<TIF_32BIT_FPREGS)
 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 
 #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index c67842bc8ef3..4a2349302b55 100644
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -18,6 +18,10 @@
  */
 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
 
+#define UNIQUE_ENTRYHI(idx)                                             \
+                ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) |               \
+                 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
+
 #include <asm-generic/tlb.h>
 
 #endif /* __ASM_TLB_H */
diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h
index c6e1b961537d..7849f3978fea 100644
--- a/arch/mips/include/asm/vpe.h
+++ b/arch/mips/include/asm/vpe.h
@@ -1,24 +1,95 @@
 /*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  */
-
 #ifndef _ASM_VPE_H
 #define _ASM_VPE_H
 
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+
+#define VPE_MODULE_NAME "vpe"
+#define VPE_MODULE_MINOR 1
+
+/* grab the likely amount of memory we will need. */
+#ifdef CONFIG_MIPS_VPE_LOADER_TOM
+#define P_SIZE (2 * 1024 * 1024)
+#else
+/* add an overhead to the max kmalloc size for non-striped symbols/etc */
+#define P_SIZE (256 * 1024)
+#endif
+
+#define MAX_VPES 16
+#define VPE_PATH_MAX 256
+
+static inline int aprp_cpu_index(void)
+{
+#ifdef CONFIG_MIPS_CMP
+        return setup_max_cpus;
+#else
+        extern int tclimit;
+        return tclimit;
+#endif
+}
+
+enum vpe_state {
+        VPE_STATE_UNUSED = 0,
+        VPE_STATE_INUSE,
+        VPE_STATE_RUNNING
+};
+
+enum tc_state {
+        TC_STATE_UNUSED = 0,
+        TC_STATE_INUSE,
+        TC_STATE_RUNNING,
+        TC_STATE_DYNAMIC
+};
+
+struct vpe {
+        enum vpe_state state;
+
+        /* (device) minor associated with this vpe */
+        int minor;
+
+        /* elfloader stuff */
+        void *load_addr;
+        unsigned long len;
+        char *pbuffer;
+        unsigned long plen;
+        char cwd[VPE_PATH_MAX];
+
+        unsigned long __start;
+
+        /* tc's associated with this vpe */
+        struct list_head tc;
+
+        /* The list of vpe's */
+        struct list_head list;
+
+        /* shared symbol address */
+        void *shared_ptr;
+
+        /* the list of who wants to know when something major happens */
+        struct list_head notify;
+
+        unsigned int ntcs;
+};
+
+struct tc {
+        enum tc_state state;
+        int index;
+
+        struct vpe *pvpe;       /* parent VPE */
+        struct list_head tc;    /* The list of TC's with this VPE */
+        struct list_head list;  /* The global list of tc's */
+};
+
 struct vpe_notifications {
         void (*start)(int vpe);
         void (*stop)(int vpe);
@@ -26,12 +97,34 @@ struct vpe_notifications {
         struct list_head list;
 };
 
+struct vpe_control {
+        spinlock_t vpe_list_lock;
+        struct list_head vpe_list;      /* Virtual processing elements */
+        spinlock_t tc_list_lock;
+        struct list_head tc_list;       /* Thread contexts */
+};
+
+extern unsigned long physical_memsize;
+extern struct vpe_control vpecontrol;
+extern const struct file_operations vpe_fops;
+
+int vpe_notify(int index, struct vpe_notifications *notify);
+
+void *vpe_get_shared(int index);
+char *vpe_getcwd(int index);
+
+struct vpe *get_vpe(int minor);
+struct tc *get_tc(int index);
+struct vpe *alloc_vpe(int minor);
+struct tc *alloc_tc(int index);
+void release_vpe(struct vpe *v);
 
-extern int vpe_notify(int index, struct vpe_notifications *notify);
+void *alloc_progmem(unsigned long len);
+void release_progmem(void *ptr);
 
-extern void *vpe_get_shared(int index);
-extern int vpe_getuid(int index);
-extern int vpe_getgid(int index);
-extern char *vpe_getcwd(int index);
+int __weak vpe_run(struct vpe *v);
+void cleanup_tc(struct tc *tc);
 
+int __init vpe_module_init(void);
+void __exit vpe_module_exit(void);
 #endif /* _ASM_VPE_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index e5a676e3d3c0..b39ba25b41cc 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -98,8 +98,9 @@ enum rt_op {
  */
 enum cop_op {
         mfc_op        = 0x00, dmfc_op       = 0x01,
-        cfc_op        = 0x02, mtc_op        = 0x04,
-        dmtc_op       = 0x05, ctc_op        = 0x06,
+        cfc_op        = 0x02, mfhc_op       = 0x03,
+        mtc_op        = 0x04, dmtc_op       = 0x05,
+        ctc_op        = 0x06, mthc_op       = 0x07,
         bc_op         = 0x08, cop_op        = 0x10,
         copm_op       = 0x18
 };
@@ -397,8 +398,10 @@ enum mm_32f_73_minor_op {
         mm_movt1_op = 0xa5,
         mm_ftruncw_op = 0xac,
         mm_fneg1_op = 0xad,
+        mm_mfhc1_op = 0xc0,
         mm_froundl_op = 0xcc,
         mm_fcvtd1_op = 0xcd,
+        mm_mthc1_op = 0xe0,
         mm_froundw_op = 0xec,
         mm_fcvts1_op = 0xed,
 };
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index 0df9787cd84d..a14baa218c76 100644
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -96,4 +96,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _UAPI_ASM_SOCKET_H */
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 8a5ec0eedeb0..c01900e5d078 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -427,6 +427,7 @@ static struct platform_device qi_lb60_audio_device = {
 
 static struct platform_device *jz_platform_devices[] __initdata = {
         &jz4740_udc_device,
+        &jz4740_udc_xceiv_device,
         &jz4740_mmc_device,
         &jz4740_nand_device,
         &qi_lb60_keypad,
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index df65677f3d0b..a447101cf9f1 100644
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -14,13 +14,14 @@
  */
 
 #include <linux/device.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/resource.h>
 
 #include <linux/dma-mapping.h>
 
+#include <linux/usb/musb.h>
+
 #include <asm/mach-jz4740/platform.h>
 #include <asm/mach-jz4740/base.h>
 #include <asm/mach-jz4740/irq.h>
@@ -56,29 +57,35 @@ struct platform_device jz4740_usb_ohci_device = {
         .resource       = jz4740_usb_ohci_resources,
 };
 
-/* UDC (USB gadget controller) */
-static struct resource jz4740_usb_gdt_resources[] = {
-        {
-                .start  = JZ4740_UDC_BASE_ADDR,
-                .end    = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
-                .flags  = IORESOURCE_MEM,
+/* USB Device Controller */
+struct platform_device jz4740_udc_xceiv_device = {
+        .name = "usb_phy_gen_xceiv",
+        .id   = 0,
+};
+
+static struct resource jz4740_udc_resources[] = {
+        [0] = {
+                .start = JZ4740_UDC_BASE_ADDR,
+                .end   = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
+                .flags = IORESOURCE_MEM,
         },
-        {
-                .start  = JZ4740_IRQ_UDC,
-                .end    = JZ4740_IRQ_UDC,
-                .flags  = IORESOURCE_IRQ,
+        [1] = {
+                .start = JZ4740_IRQ_UDC,
+                .end   = JZ4740_IRQ_UDC,
+                .flags = IORESOURCE_IRQ,
+                .name  = "mc",
         },
 };
 
 struct platform_device jz4740_udc_device = {
-        .name           = "jz-udc",
-        .id             = -1,
-        .dev = {
-                .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
+        .name = "musb-jz4740",
+        .id   = -1,
+        .dev  = {
+                .dma_mask          = &jz4740_udc_device.dev.coherent_dma_mask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
-        .num_resources  = ARRAY_SIZE(jz4740_usb_gdt_resources),
-        .resource       = jz4740_usb_gdt_resources,
+        .num_resources = ARRAY_SIZE(jz4740_udc_resources),
+        .resource      = jz4740_udc_resources,
 };
 
 /* MMC/SD controller */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1c1b71752c84..26c6175e1379 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CSRC_R4K)		+= csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)       += csrc-sb1250.o
 obj-$(CONFIG_SYNC_R4K)          += sync-r4k.o
 
+obj-$(CONFIG_DEBUG_FS)          += segment.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_MODULES)           += mips_ksyms.o module.o
 obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
@@ -55,7 +56,11 @@ obj-$(CONFIG_MIPS_CMP)		+= smp-cmp.o
 obj-$(CONFIG_CPU_MIPSR2)        += spram.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)   += vpe.o
+obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o
+obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o
 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
+obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
+obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
 
 obj-$(CONFIG_I8259)             += i8259.o
 obj-$(CONFIG_IRQ_CPU)           += irq_cpu.o
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 202e581e6096..7faf5f2bee25 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -28,6 +28,18 @@ typedef double elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 /*
+ * In order to be sure that we don't attempt to execute an O32 binary which
+ * requires 64 bit FP (FR=1) on a system which does not support it we refuse
+ * to execute any binary which has bits specified by the following macro set
+ * in its ELF header flags.
+ */
+#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
+# define __MIPS_O32_FP64_MUST_BE_ZERO   0
+#else
+# define __MIPS_O32_FP64_MUST_BE_ZERO   EF_MIPS_FP64
+#endif
+
+/*
  * This is used to ensure we don't load something for the wrong architecture.
  */
 #define elf_check_arch(hdr)                                             \
@@ -44,6 +56,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
         if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
             ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
                 __res = 0;                                              \
+        if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO)                \
+                __res = 0;                                              \
                                                                         \
         __res;                                                          \
 })
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index bd79c4f9bff4..a5bf73d22fcc 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -8,11 +8,11 @@
  * Reset/NMI/re-entry vectors for BMIPS processors
  */
 
-#include <linux/init.h>
 
 #include <asm/asm.h>
 #include <asm/asmmacro.h>
 #include <asm/cacheops.h>
+#include <asm/cpu.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
@@ -91,12 +91,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
         beqz    k0, bmips_smp_entry
 
 #if defined(CONFIG_CPU_BMIPS5000)
+        mfc0    k0, CP0_PRID
+        li      k1, PRID_IMP_BMIPS5000
+        andi    k0, 0xff00
+        bne     k0, k1, 1f
+
         /* if we're not on core 0, this must be the SMP boot signal */
         li      k1, (3 << 25)
         mfc0    k0, $22
         and     k0, k1
         bnez    k0, bmips_smp_entry
-#endif
+1:
+#endif /* CONFIG_CPU_BMIPS5000 */
 #endif /* CONFIG_SMP */
 
         /* nope, it's just a regular NMI */
@@ -139,7 +145,12 @@ bmips_smp_entry:
         xori    k0, 0x04
         mtc0    k0, CP0_CONFIG
 
+        mfc0    k0, CP0_PRID
+        andi    k0, 0xff00
 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        li      k1, PRID_IMP_BMIPS43XX
+        bne     k0, k1, 2f
+
         /* initialize CPU1's local I-cache */
         li      k0, 0x80000000
         li      k1, 0x80010000
@@ -150,14 +161,21 @@ bmips_smp_entry:
 1:      cache   Index_Store_Tag_I, 0(k0)
         addiu   k0, 16
         bne     k0, k1, 1b
-#elif defined(CONFIG_CPU_BMIPS5000)
+
+        b       3f
+2:
+#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
+#if defined(CONFIG_CPU_BMIPS5000)
         /* set exception vector base */
+        li      k1, PRID_IMP_BMIPS5000
+        bne     k0, k1, 3f
+
         la      k0, ebase
         lw      k0, 0(k0)
         mtc0    k0, $15, 1
         BARRIER
-#endif
-
+#endif /* CONFIG_CPU_BMIPS5000 */
+3:
         /* jump back to kseg0 in case we need to remap the kseg1 area */
         la      k0, 1f
         jr      k0
@@ -221,8 +239,18 @@ END(bmips_smp_int_vec)
 LEAF(bmips_enable_xks01)
 
 #if defined(CONFIG_XKS01)
-
+        mfc0    t0, CP0_PRID
+        andi    t2, t0, 0xff00
 #if defined(CONFIG_CPU_BMIPS4380)
+        li      t1, PRID_IMP_BMIPS43XX
+        bne     t2, t1, 1f
+
+        andi    t0, 0xff
+        addiu   t1, t0, -PRID_REV_BMIPS4380_HI
+        bgtz    t1, 2f
+        addiu   t0, -PRID_REV_BMIPS4380_LO
+        bltz    t0, 2f
+
         mfc0    t0, $22, 3
         li      t1, 0x1ff0
         li      t2, (1 << 12) | (1 << 9)
@@ -231,7 +259,13 @@ LEAF(bmips_enable_xks01)
         or      t0, t2
         mtc0    t0, $22, 3
         BARRIER
-#elif defined(CONFIG_CPU_BMIPS5000)
+        b       2f
+1:
+#endif /* CONFIG_CPU_BMIPS4380 */
+#if defined(CONFIG_CPU_BMIPS5000)
+        li      t1, PRID_IMP_BMIPS5000
+        bne     t2, t1, 2f
+
         mfc0    t0, $22, 5
         li      t1, 0x01ff
         li      t2, (1 << 8) | (1 << 5)
@@ -240,12 +274,8 @@ LEAF(bmips_enable_xks01)
         or      t0, t2
         mtc0    t0, $22, 5
         BARRIER
-#else
-
-#error Missing XKS01 setup
-
-#endif
-
+#endif /* CONFIG_CPU_BMIPS5000 */
+2:
 #endif /* defined(CONFIG_XKS01) */
 
         jr      ra
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c814287bdf5d..530f832de02c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -112,7 +112,7 @@ static inline unsigned long cpu_get_fpu_id(void)
         unsigned long tmp, fpu_id;
 
         tmp = read_c0_status();
-        __enable_fpu();
+        __enable_fpu(FPU_AS_IS);
         fpu_id = read_32bit_cp1_register(CP1_REVISION);
         write_c0_status(tmp);
         return fpu_id;
@@ -163,6 +163,25 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 static char unknown_isa[] = KERN_ERR \
         "Unsupported ISA type, c0.config0: %d.";
 
+static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
+{
+        unsigned int config6;
+        /*
+         * Config6 is implementation dependent and it's currently only
+         * used by proAptiv
+         */
+        if (c->cputype == CPU_PROAPTIV) {
+                config6 = read_c0_config6();
+                if (enable)
+                        /* Enable FTLB */
+                        write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
+                else
+                        /* Disable FTLB */
+                        write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
+                back_to_back_c0_hazard();
+        }
+}
+
 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 {
         unsigned int config0;
@@ -170,8 +189,13 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 
         config0 = read_c0_config();
 
-        if (((config0 & MIPS_CONF_MT) >> 7) == 1)
+        /*
+         * Look for Standard TLB or Dual VTLB and FTLB
+         */
+        if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
+            (((config0 & MIPS_CONF_MT) >> 7) == 4))
                 c->options |= MIPS_CPU_TLB;
+
         isa = (config0 & MIPS_CONF_AT) >> 13;
         switch (isa) {
         case 0:
@@ -226,8 +250,11 @@ static inline unsigned int decode_config1(struct cpuinfo_mips *c)
                 c->options |= MIPS_CPU_FPU;
                 c->options |= MIPS_CPU_32FPR;
         }
-        if (cpu_has_tlb)
+        if (cpu_has_tlb) {
                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
+                c->tlbsizevtlb = c->tlbsize;
+                c->tlbsizeftlbsets = 0;
+        }
 
         return config1 & MIPS_CONF_M;
 }
@@ -272,6 +299,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                 c->options |= MIPS_CPU_MICROMIPS;
         if (config3 & MIPS_CONF3_VZ)
                 c->ases |= MIPS_ASE_VZ;
+        if (config3 & MIPS_CONF3_SC)
+                c->options |= MIPS_CPU_SEGMENTS;
 
         return config3 & MIPS_CONF_M;
 }
@@ -279,12 +308,51 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 {
         unsigned int config4;
+        unsigned int newcf4;
+        unsigned int mmuextdef;
+        unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 
         config4 = read_c0_config4();
 
-        if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
-            && cpu_has_tlb)
-                c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+        if (cpu_has_tlb) {
+                if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
+                        c->options |= MIPS_CPU_TLBINV;
+                mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
+                switch (mmuextdef) {
+                case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
+                        c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+                        c->tlbsizevtlb = c->tlbsize;
+                        break;
+                case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
+                        c->tlbsizevtlb +=
+                                ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
+                                  MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
+                        c->tlbsize = c->tlbsizevtlb;
+                        ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
+                        /* fall through */
+                case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
+                        newcf4 = (config4 & ~ftlb_page) |
+                                (page_size_ftlb(mmuextdef) <<
+                                 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
+                        write_c0_config4(newcf4);
+                        back_to_back_c0_hazard();
+                        config4 = read_c0_config4();
+                        if (config4 != newcf4) {
+                                pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
+                                       PAGE_SIZE, config4);
+                                /* Switch FTLB off */
+                                set_ftlb_enable(c, 0);
+                                break;
+                        }
+                        c->tlbsizeftlbsets = 1 <<
+                                ((config4 & MIPS_CONF4_FTLBSETS) >>
+                                 MIPS_CONF4_FTLBSETS_SHIFT);
+                        c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
+                                              MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
+                        c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
+                        break;
+                }
+        }
 
         c->kscratch_mask = (config4 >> 16) & 0xff;
 
@@ -312,6 +380,9 @@ static void decode_configs(struct cpuinfo_mips *c)
 
         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
+        /* Enable FTLB if present */
+        set_ftlb_enable(c, 1);
+
         ok = decode_config0(c);                 /* Read Config registers.  */
         BUG_ON(!ok);                            /* Arch spec violation!  */
         if (ok)
@@ -675,7 +746,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
-        decode_configs(c);
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_4KC:
                 c->cputype = CPU_4KC;
@@ -739,8 +809,26 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_74K;
                 __cpu_name[cpu] = "MIPS 1074Kc";
                 break;
+        case PRID_IMP_INTERAPTIV_UP:
+                c->cputype = CPU_INTERAPTIV;
+                __cpu_name[cpu] = "MIPS interAptiv";
+                break;
+        case PRID_IMP_INTERAPTIV_MP:
+                c->cputype = CPU_INTERAPTIV;
+                __cpu_name[cpu] = "MIPS interAptiv (multi)";
+                break;
+        case PRID_IMP_PROAPTIV_UP:
+                c->cputype = CPU_PROAPTIV;
+                __cpu_name[cpu] = "MIPS proAptiv";
+                break;
+        case PRID_IMP_PROAPTIV_MP:
+                c->cputype = CPU_PROAPTIV;
+                __cpu_name[cpu] = "MIPS proAptiv (multi)";
+                break;
         }
 
+        decode_configs(c);
+
         spram_config();
 }
 
@@ -943,6 +1031,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_NETLOGIC_XLP2XX:
+        case PRID_IMP_NETLOGIC_XLP9XX:
                 c->cputype = CPU_XLP;
                 __cpu_name[cpu] = "Broadcom XLPII";
                 break;
diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
index 93aa302948d7..d21264681e97 100644
--- a/arch/mips/kernel/crash.c
+++ b/arch/mips/kernel/crash.c
@@ -5,7 +5,6 @@
 #include <linux/bootmem.h>
 #include <linux/crash_dump.h>
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/types.h>
 #include <linux/sched.h>
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 47d7583cd67f..d84f6a509502 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -476,6 +476,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
         BUILD_HANDLER ov ov sti silent                  /* #12 */
         BUILD_HANDLER tr tr sti silent                  /* #13 */
         BUILD_HANDLER fpe fpe fpe silent                /* #15 */
+        BUILD_HANDLER ftlb ftlb none silent             /* #16 */
         BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
 #ifdef  CONFIG_HARDWARE_WATCHPOINTS
         /*
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index f7991d95bff9..3553243bf9d6 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -184,6 +184,8 @@ void __init check_wait(void)
         case CPU_24K:
         case CPU_34K:
         case CPU_1004K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
                 cpu_wait = r4k_wait;
                 if (read_c0_config7() & MIPS_CONF7_WII)
                         cpu_wait = r4k_wait_irqoff;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 8c58d8a84bf3..00d20974b3e7 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -65,26 +65,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                                 cpu_data[n].watch_reg_masks[i]);
                 seq_printf(m, "]\n");
         }
-        if (cpu_has_mips_r) {
-                seq_printf(m, "isa\t\t\t: mips1");
-                if (cpu_has_mips_2)
-                        seq_printf(m, "%s", " mips2");
-                if (cpu_has_mips_3)
-                        seq_printf(m, "%s", " mips3");
-                if (cpu_has_mips_4)
-                        seq_printf(m, "%s", " mips4");
-                if (cpu_has_mips_5)
-                        seq_printf(m, "%s", " mips5");
-                if (cpu_has_mips32r1)
-                        seq_printf(m, "%s", " mips32r1");
-                if (cpu_has_mips32r2)
-                        seq_printf(m, "%s", " mips32r2");
-                if (cpu_has_mips64r1)
-                        seq_printf(m, "%s", " mips64r1");
-                if (cpu_has_mips64r2)
-                        seq_printf(m, "%s", " mips64r2");
-                seq_printf(m, "\n");
-        }
+
+        seq_printf(m, "isa\t\t\t: mips1");
+        if (cpu_has_mips_2)
+                seq_printf(m, "%s", " mips2");
+        if (cpu_has_mips_3)
+                seq_printf(m, "%s", " mips3");
+        if (cpu_has_mips_4)
+                seq_printf(m, "%s", " mips4");
+        if (cpu_has_mips_5)
+                seq_printf(m, "%s", " mips5");
+        if (cpu_has_mips32r1)
+                seq_printf(m, "%s", " mips32r1");
+        if (cpu_has_mips32r2)
+                seq_printf(m, "%s", " mips32r2");
+        if (cpu_has_mips64r1)
+                seq_printf(m, "%s", " mips64r1");
+        if (cpu_has_mips64r2)
+                seq_printf(m, "%s", " mips64r2");
+        seq_printf(m, "\n");
 
         seq_printf(m, "ASEs implemented\t:");
         if (cpu_has_mips16)     seq_printf(m, "%s", " mips16");
@@ -107,7 +106,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         seq_printf(m, "kscratch registers\t: %d\n",
                       hweight8(cpu_data[n].kscratch_mask));
         seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
-
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+        if (cpu_has_mipsmt) {
+                seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
+#if defined(CONFIG_MIPS_MT_SMTC)
+                seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
+#endif
+        }
+#endif
         sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
                       cpu_has_vce ? "%u" : "not available");
         seq_printf(m, fmt, 'D', vced_count);
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index ddc76103e78c..6ae540e133b2 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -60,15 +60,11 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
 
         /* New thread loses kernel privileges. */
         status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
-#ifdef CONFIG_64BIT
-        status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
-#endif
         status |= KU_USER;
         regs->cp0_status = status;
         clear_used_math();
         clear_fpu_owner();
-        if (cpu_has_dsp)
-                __init_dsp();
+        init_dsp();
         regs->cp0_epc = pc;
         regs->regs[29] = sp;
 }
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index b52e1d2b33e0..7da9b76db4d9 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -137,13 +137,13 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
                 if (cpu_has_mipsmt) {
                         unsigned int vpflags = dvpe();
                         flags = read_c0_status();
-                        __enable_fpu();
+                        __enable_fpu(FPU_AS_IS);
                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
                         write_c0_status(flags);
                         evpe(vpflags);
                 } else {
                         flags = read_c0_status();
-                        __enable_fpu();
+                        __enable_fpu(FPU_AS_IS);
                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
                         write_c0_status(flags);
                 }
@@ -408,6 +408,7 @@ long arch_ptrace(struct task_struct *child, long request,
         /* Read the word at location addr in the USER area. */
         case PTRACE_PEEKUSR: {
                 struct pt_regs *regs;
+                fpureg_t *fregs;
                 unsigned long tmp = 0;
 
                 regs = task_pt_regs(child);
@@ -418,26 +419,28 @@ long arch_ptrace(struct task_struct *child, long request,
                         tmp = regs->regs[addr];
                         break;
                 case FPR_BASE ... FPR_BASE + 31:
-                        if (tsk_used_math(child)) {
-                                fpureg_t *fregs = get_fpu_regs(child);
+                        if (!tsk_used_math(child)) {
+                                /* FP not yet used */
+                                tmp = -1;
+                                break;
+                        }
+                        fregs = get_fpu_regs(child);
 
 #ifdef CONFIG_32BIT
+                        if (test_thread_flag(TIF_32BIT_FPREGS)) {
                                 /*
                                  * The odd registers are actually the high
                                  * order bits of the values stored in the even
                                  * registers - unless we're using r2k_switch.S.
                                  */
                                 if (addr & 1)
-                                        tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
+                                        tmp = fregs[(addr & ~1) - 32] >> 32;
                                 else
-                                        tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
-#endif
-#ifdef CONFIG_64BIT
-                                tmp = fregs[addr - FPR_BASE];
-#endif
-                        } else {
-                                tmp = -1;       /* FP not yet used  */
+                                        tmp = fregs[addr - 32];
+                                break;
                         }
+#endif
+                        tmp = fregs[addr - FPR_BASE];
                         break;
                 case PC:
                         tmp = regs->cp0_epc;
@@ -483,13 +486,13 @@ long arch_ptrace(struct task_struct *child, long request,
                         if (cpu_has_mipsmt) {
                                 unsigned int vpflags = dvpe();
                                 flags = read_c0_status();
-                                __enable_fpu();
+                                __enable_fpu(FPU_AS_IS);
                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
                                 write_c0_status(flags);
                                 evpe(vpflags);
                         } else {
                                 flags = read_c0_status();
-                                __enable_fpu();
+                                __enable_fpu(FPU_AS_IS);
                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
                                 write_c0_status(flags);
                         }
@@ -554,22 +557,25 @@ long arch_ptrace(struct task_struct *child, long request,
                                 child->thread.fpu.fcr31 = 0;
                         }
 #ifdef CONFIG_32BIT
-                        /*
-                         * The odd registers are actually the high order bits
-                         * of the values stored in the even registers - unless
-                         * we're using r2k_switch.S.
-                         */
-                        if (addr & 1) {
-                                fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
-                                fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
-                        } else {
-                                fregs[addr - FPR_BASE] &= ~0xffffffffLL;
-                                fregs[addr - FPR_BASE] |= data;
+                        if (test_thread_flag(TIF_32BIT_FPREGS)) {
+                                /*
+                                 * The odd registers are actually the high
+                                 * order bits of the values stored in the even
+                                 * registers - unless we're using r2k_switch.S.
+                                 */
+                                if (addr & 1) {
+                                        fregs[(addr & ~1) - FPR_BASE] &=
+                                                0xffffffff;
+                                        fregs[(addr & ~1) - FPR_BASE] |=
+                                                ((u64)data) << 32;
+                                } else {
+                                        fregs[addr - FPR_BASE] &= ~0xffffffffLL;
+                                        fregs[addr - FPR_BASE] |= data;
+                                }
+                                break;
                         }
 #endif
-#ifdef CONFIG_64BIT
                         fregs[addr - FPR_BASE] = data;
-#endif
                         break;
                 }
                 case PC:
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 9486055ba660..b8aa2dd5b00b 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -80,6 +80,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
         /* Read the word at location addr in the USER area. */
         case PTRACE_PEEKUSR: {
                 struct pt_regs *regs;
+                fpureg_t *fregs;
                 unsigned int tmp;
 
                 regs = task_pt_regs(child);
@@ -90,21 +91,25 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         tmp = regs->regs[addr];
                         break;
                 case FPR_BASE ... FPR_BASE + 31:
-                        if (tsk_used_math(child)) {
-                                fpureg_t *fregs = get_fpu_regs(child);
-
+                        if (!tsk_used_math(child)) {
+                                /* FP not yet used */
+                                tmp = -1;
+                                break;
+                        }
+                        fregs = get_fpu_regs(child);
+                        if (test_thread_flag(TIF_32BIT_FPREGS)) {
                                 /*
                                  * The odd registers are actually the high
                                  * order bits of the values stored in the even
                                  * registers - unless we're using r2k_switch.S.
                                  */
                                 if (addr & 1)
-                                        tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
+                                        tmp = fregs[(addr & ~1) - 32] >> 32;
                                 else
-                                        tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
-                        } else {
-                                tmp = -1;       /* FP not yet used  */
+                                        tmp = fregs[addr - 32];
+                                break;
                         }
+                        tmp = fregs[addr - FPR_BASE];
                         break;
                 case PC:
                         tmp = regs->cp0_epc;
@@ -147,13 +152,13 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         if (cpu_has_mipsmt) {
                                 unsigned int vpflags = dvpe();
                                 flags = read_c0_status();
-                                __enable_fpu();
+                                __enable_fpu(FPU_AS_IS);
                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
                                 write_c0_status(flags);
                                 evpe(vpflags);
                         } else {
                                 flags = read_c0_status();
-                                __enable_fpu();
+                                __enable_fpu(FPU_AS_IS);
                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
                                 write_c0_status(flags);
                         }
@@ -236,20 +241,24 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                                        sizeof(child->thread.fpu));
                                 child->thread.fpu.fcr31 = 0;
                         }
-                        /*
-                         * The odd registers are actually the high order bits
-                         * of the values stored in the even registers - unless
-                         * we're using r2k_switch.S.
-                         */
-                        if (addr & 1) {
-                                fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
-                                fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
-                        } else {
-                                fregs[addr - FPR_BASE] &= ~0xffffffffLL;
-                                /* Must cast, lest sign extension fill upper
-                                   bits!  */
-                                fregs[addr - FPR_BASE] |= (unsigned int)data;
+                        if (test_thread_flag(TIF_32BIT_FPREGS)) {
+                                /*
+                                 * The odd registers are actually the high
+                                 * order bits of the values stored in the even
+                                 * registers - unless we're using r2k_switch.S.
+                                 */
+                                if (addr & 1) {
+                                        fregs[(addr & ~1) - FPR_BASE] &=
+                                                0xffffffff;
+                                        fregs[(addr & ~1) - FPR_BASE] |=
+                                                ((u64)data) << 32;
+                                } else {
+                                        fregs[addr - FPR_BASE] &= ~0xffffffffLL;
+                                        fregs[addr - FPR_BASE] |= data;
+                                }
+                                break;
                         }
+                        fregs[addr - FPR_BASE] = data;
                         break;
                 }
                 case PC:
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 55ffe149dae9..253b2fb52026 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -35,7 +35,15 @@
 LEAF(_save_fp_context)
         cfc1    t1, fcr31
 
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
+        .set    push
+#ifdef CONFIG_MIPS32_R2
+        .set    mips64r2
+        mfc0    t0, CP0_STATUS
+        sll     t0, t0, 5
+        bgez    t0, 1f                  # skip storing odd if FR=0
+         nop
+#endif
         /* Store the 16 odd double precision registers */
         EX      sdc1 $f1, SC_FPREGS+8(a0)
         EX      sdc1 $f3, SC_FPREGS+24(a0)
@@ -53,6 +61,7 @@ LEAF(_save_fp_context)
         EX      sdc1 $f27, SC_FPREGS+216(a0)
         EX      sdc1 $f29, SC_FPREGS+232(a0)
         EX      sdc1 $f31, SC_FPREGS+248(a0)
+1:      .set    pop
 #endif
 
         /* Store the 16 even double precision registers */
@@ -82,7 +91,31 @@ LEAF(_save_fp_context)
 LEAF(_save_fp_context32)
         cfc1    t1, fcr31
 
-        EX      sdc1 $f0, SC32_FPREGS+0(a0)
+        mfc0    t0, CP0_STATUS
+        sll     t0, t0, 5
+        bgez    t0, 1f                  # skip storing odd if FR=0
+         nop
+
+        /* Store the 16 odd double precision registers */
+        EX      sdc1 $f1, SC32_FPREGS+8(a0)
+        EX      sdc1 $f3, SC32_FPREGS+24(a0)
+        EX      sdc1 $f5, SC32_FPREGS+40(a0)
+        EX      sdc1 $f7, SC32_FPREGS+56(a0)
+        EX      sdc1 $f9, SC32_FPREGS+72(a0)
+        EX      sdc1 $f11, SC32_FPREGS+88(a0)
+        EX      sdc1 $f13, SC32_FPREGS+104(a0)
+        EX      sdc1 $f15, SC32_FPREGS+120(a0)
+        EX      sdc1 $f17, SC32_FPREGS+136(a0)
+        EX      sdc1 $f19, SC32_FPREGS+152(a0)
+        EX      sdc1 $f21, SC32_FPREGS+168(a0)
+        EX      sdc1 $f23, SC32_FPREGS+184(a0)
+        EX      sdc1 $f25, SC32_FPREGS+200(a0)
+        EX      sdc1 $f27, SC32_FPREGS+216(a0)
+        EX      sdc1 $f29, SC32_FPREGS+232(a0)
+        EX      sdc1 $f31, SC32_FPREGS+248(a0)
+
+        /* Store the 16 even double precision registers */
+1:      EX      sdc1 $f0, SC32_FPREGS+0(a0)
         EX      sdc1 $f2, SC32_FPREGS+16(a0)
         EX      sdc1 $f4, SC32_FPREGS+32(a0)
         EX      sdc1 $f6, SC32_FPREGS+48(a0)
@@ -114,7 +147,16 @@ LEAF(_save_fp_context32)
  */
 LEAF(_restore_fp_context)
         EX      lw t0, SC_FPC_CSR(a0)
-#ifdef CONFIG_64BIT
+
+#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
+        .set    push
+#ifdef CONFIG_MIPS32_R2
+        .set    mips64r2
+        mfc0    t0, CP0_STATUS
+        sll     t0, t0, 5
+        bgez    t0, 1f                  # skip loading odd if FR=0
+         nop
+#endif
         EX      ldc1 $f1, SC_FPREGS+8(a0)
         EX      ldc1 $f3, SC_FPREGS+24(a0)
         EX      ldc1 $f5, SC_FPREGS+40(a0)
@@ -131,6 +173,7 @@ LEAF(_restore_fp_context)
         EX      ldc1 $f27, SC_FPREGS+216(a0)
         EX      ldc1 $f29, SC_FPREGS+232(a0)
         EX      ldc1 $f31, SC_FPREGS+248(a0)
+1:      .set pop
 #endif
         EX      ldc1 $f0, SC_FPREGS+0(a0)
         EX      ldc1 $f2, SC_FPREGS+16(a0)
@@ -157,7 +200,30 @@ LEAF(_restore_fp_context)
 LEAF(_restore_fp_context32)
         /* Restore an o32 sigcontext.  */
         EX      lw t0, SC32_FPC_CSR(a0)
-        EX      ldc1 $f0, SC32_FPREGS+0(a0)
+
+        mfc0    t0, CP0_STATUS
+        sll     t0, t0, 5
+        bgez    t0, 1f                  # skip loading odd if FR=0
+         nop
+
+        EX      ldc1 $f1, SC32_FPREGS+8(a0)
+        EX      ldc1 $f3, SC32_FPREGS+24(a0)
+        EX      ldc1 $f5, SC32_FPREGS+40(a0)
+        EX      ldc1 $f7, SC32_FPREGS+56(a0)
+        EX      ldc1 $f9, SC32_FPREGS+72(a0)
+        EX      ldc1 $f11, SC32_FPREGS+88(a0)
+        EX      ldc1 $f13, SC32_FPREGS+104(a0)
+        EX      ldc1 $f15, SC32_FPREGS+120(a0)
+        EX      ldc1 $f17, SC32_FPREGS+136(a0)
+        EX      ldc1 $f19, SC32_FPREGS+152(a0)
+        EX      ldc1 $f21, SC32_FPREGS+168(a0)
+        EX      ldc1 $f23, SC32_FPREGS+184(a0)
+        EX      ldc1 $f25, SC32_FPREGS+200(a0)
+        EX      ldc1 $f27, SC32_FPREGS+216(a0)
+        EX      ldc1 $f29, SC32_FPREGS+232(a0)
+        EX      ldc1 $f31, SC32_FPREGS+248(a0)
+
+1:      EX      ldc1 $f0, SC32_FPREGS+0(a0)
         EX      ldc1 $f2, SC32_FPREGS+16(a0)
         EX      ldc1 $f4, SC32_FPREGS+32(a0)
         EX      ldc1 $f6, SC32_FPREGS+48(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 078de5eaca8f..cc78dd9a17c7 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -123,7 +123,7 @@
  * Save a thread's fp context.
  */
 LEAF(_save_fp)
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         mfc0    t0, CP0_STATUS
 #endif
         fpu_save_double a0 t0 t1                # clobbers t1
@@ -134,7 +134,7 @@ LEAF(_save_fp)
  * Restore a thread's fp context.
  */
 LEAF(_restore_fp)
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         mfc0    t0, CP0_STATUS
 #endif
         fpu_restore_double a0 t0 t1             # clobbers t1
@@ -228,6 +228,47 @@ LEAF(_init_fpu)
         mtc1    t1, $f29
         mtc1    t1, $f30
         mtc1    t1, $f31
+
+#ifdef CONFIG_CPU_MIPS32_R2
+        .set    push
+        .set    mips64r2
+        sll     t0, t0, 5                       # is Status.FR set?
+        bgez    t0, 1f                          # no: skip setting upper 32b
+
+        mthc1   t1, $f0
+        mthc1   t1, $f1
+        mthc1   t1, $f2
+        mthc1   t1, $f3
+        mthc1   t1, $f4
+        mthc1   t1, $f5
+        mthc1   t1, $f6
+        mthc1   t1, $f7
+        mthc1   t1, $f8
+        mthc1   t1, $f9
+        mthc1   t1, $f10
+        mthc1   t1, $f11
+        mthc1   t1, $f12
+        mthc1   t1, $f13
+        mthc1   t1, $f14
+        mthc1   t1, $f15
+        mthc1   t1, $f16
+        mthc1   t1, $f17
+        mthc1   t1, $f18
+        mthc1   t1, $f19
+        mthc1   t1, $f20
+        mthc1   t1, $f21
+        mthc1   t1, $f22
+        mthc1   t1, $f23
+        mthc1   t1, $f24
+        mthc1   t1, $f25
+        mthc1   t1, $f26
+        mthc1   t1, $f27
+        mthc1   t1, $f28
+        mthc1   t1, $f29
+        mthc1   t1, $f30
+        mthc1   t1, $f31
+1:      .set    pop
+#endif /* CONFIG_CPU_MIPS32_R2 */
 #else
         .set    mips3
         dmtc1   t1, $f0
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c
new file mode 100644
index 000000000000..56dc69635153
--- /dev/null
+++ b/arch/mips/kernel/rtlx-cmp.c
@@ -0,0 +1,116 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+
+#include <asm/mips_mt.h>
+#include <asm/vpe.h>
+#include <asm/rtlx.h>
+
+static int major;
+
+static void rtlx_interrupt(void)
+{
+        int i;
+        struct rtlx_info *info;
+        struct rtlx_info **p = vpe_get_shared(aprp_cpu_index());
+
+        if (p == NULL || *p == NULL)
+                return;
+
+        info = *p;
+
+        if (info->ap_int_pending == 1 && smp_processor_id() == 0) {
+                for (i = 0; i < RTLX_CHANNELS; i++) {
+                        wake_up(&channel_wqs[i].lx_queue);
+                        wake_up(&channel_wqs[i].rt_queue);
+                }
+                info->ap_int_pending = 0;
+        }
+}
+
+void _interrupt_sp(void)
+{
+        smp_send_reschedule(aprp_cpu_index());
+}
+
+int __init rtlx_module_init(void)
+{
+        struct device *dev;
+        int i, err;
+
+        if (!cpu_has_mipsmt) {
+                pr_warn("VPE loader: not a MIPS MT capable processor\n");
+                return -ENODEV;
+        }
+
+        if (num_possible_cpus() - aprp_cpu_index() < 1) {
+                pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
+                        "Pass maxcpus=<n> argument as kernel argument\n");
+
+                return -ENODEV;
+        }
+
+        major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
+        if (major < 0) {
+                pr_err("rtlx_module_init: unable to register device\n");
+                return major;
+        }
+
+        /* initialise the wait queues */
+        for (i = 0; i < RTLX_CHANNELS; i++) {
+                init_waitqueue_head(&channel_wqs[i].rt_queue);
+                init_waitqueue_head(&channel_wqs[i].lx_queue);
+                atomic_set(&channel_wqs[i].in_open, 0);
+                mutex_init(&channel_wqs[i].mutex);
+
+                dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
+                                    "%s%d", RTLX_MODULE_NAME, i);
+                if (IS_ERR(dev)) {
+                        err = PTR_ERR(dev);
+                        goto out_chrdev;
+                }
+        }
+
+        /* set up notifiers */
+        rtlx_notify.start = rtlx_starting;
+        rtlx_notify.stop = rtlx_stopping;
+        vpe_notify(aprp_cpu_index(), &rtlx_notify);
+
+        if (cpu_has_vint) {
+                aprp_hook = rtlx_interrupt;
+        } else {
+                pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
+                err = -ENODEV;
+                goto out_class;
+        }
+
+        return 0;
+
+out_class:
+        for (i = 0; i < RTLX_CHANNELS; i++)
+                device_destroy(mt_class, MKDEV(major, i));
+out_chrdev:
+        unregister_chrdev(major, RTLX_MODULE_NAME);
+
+        return err;
+}
+
+void __exit rtlx_module_exit(void)
+{
+        int i;
+
+        for (i = 0; i < RTLX_CHANNELS; i++)
+                device_destroy(mt_class, MKDEV(major, i));
+        unregister_chrdev(major, RTLX_MODULE_NAME);
+}
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c
new file mode 100644
index 000000000000..91d61ba422b4
--- /dev/null
+++ b/arch/mips/kernel/rtlx-mt.c
@@ -0,0 +1,148 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/mips_mt.h>
+#include <asm/vpe.h>
+#include <asm/rtlx.h>
+
+static int major;
+
+static void rtlx_dispatch(void)
+{
+        if (read_c0_cause() & read_c0_status() & C_SW0)
+                do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
+}
+
+/*
+ * Interrupt handler may be called before rtlx_init has otherwise had
+ * a chance to run.
+ */
+static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
+{
+        unsigned int vpeflags;
+        unsigned long flags;
+        int i;
+
+        /* Ought not to be strictly necessary for SMTC builds */
+        local_irq_save(flags);
+        vpeflags = dvpe();
+        set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
+        irq_enable_hazard();
+        evpe(vpeflags);
+        local_irq_restore(flags);
+
+        for (i = 0; i < RTLX_CHANNELS; i++) {
+                wake_up(&channel_wqs[i].lx_queue);
+                wake_up(&channel_wqs[i].rt_queue);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction rtlx_irq = {
+        .handler        = rtlx_interrupt,
+        .name           = "RTLX",
+};
+
+static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
+
+void _interrupt_sp(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        dvpe();
+        settc(1);
+        write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0);
+        evpe(EVPE_ENABLE);
+        local_irq_restore(flags);
+}
+
+int __init rtlx_module_init(void)
+{
+        struct device *dev;
+        int i, err;
+
+        if (!cpu_has_mipsmt) {
+                pr_warn("VPE loader: not a MIPS MT capable processor\n");
+                return -ENODEV;
+        }
+
+        if (aprp_cpu_index() == 0) {
+                pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
+                        "Pass maxtcs=<n> argument as kernel argument\n");
+
+                return -ENODEV;
+        }
+
+        major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
+        if (major < 0) {
+                pr_err("rtlx_module_init: unable to register device\n");
+                return major;
+        }
+
+        /* initialise the wait queues */
+        for (i = 0; i < RTLX_CHANNELS; i++) {
+                init_waitqueue_head(&channel_wqs[i].rt_queue);
+                init_waitqueue_head(&channel_wqs[i].lx_queue);
+                atomic_set(&channel_wqs[i].in_open, 0);
+                mutex_init(&channel_wqs[i].mutex);
+
+                dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
+                                    "%s%d", RTLX_MODULE_NAME, i);
+                if (IS_ERR(dev)) {
+                        err = PTR_ERR(dev);
+                        goto out_chrdev;
+                }
+        }
+
+        /* set up notifiers */
+        rtlx_notify.start = rtlx_starting;
+        rtlx_notify.stop = rtlx_stopping;
+        vpe_notify(aprp_cpu_index(), &rtlx_notify);
+
+        if (cpu_has_vint) {
+                aprp_hook = rtlx_dispatch;
+        } else {
+                pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
+                err = -ENODEV;
+                goto out_class;
+        }
+
+        rtlx_irq.dev_id = rtlx;
+        err = setup_irq(rtlx_irq_num, &rtlx_irq);
+        if (err)
+                goto out_class;
+
+        return 0;
+
+out_class:
+        for (i = 0; i < RTLX_CHANNELS; i++)
+                device_destroy(mt_class, MKDEV(major, i));
+out_chrdev:
+        unregister_chrdev(major, RTLX_MODULE_NAME);
+
+        return err;
+}
+
+void __exit rtlx_module_exit(void)
+{
+        int i;
+
+        for (i = 0; i < RTLX_CHANNELS; i++)
+                device_destroy(mt_class, MKDEV(major, i));
+        unregister_chrdev(major, RTLX_MODULE_NAME);
+}
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 2c12ea1668d1..31b1b763cb29 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -1,114 +1,51 @@
 /*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
  * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
  * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  */
-
-#include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/fs.h>
-#include <linux/init.h>
-#include <asm/uaccess.h>
-#include <linux/list.h>
-#include <linux/vmalloc.h>
-#include <linux/elf.h>
-#include <linux/seq_file.h>
 #include <linux/syscalls.h>
 #include <linux/moduleloader.h>
-#include <linux/interrupt.h>
-#include <linux/poll.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
+#include <linux/atomic.h>
 #include <asm/mipsmtregs.h>
 #include <asm/mips_mt.h>
-#include <asm/cacheflush.h>
-#include <linux/atomic.h>
-#include <asm/cpu.h>
 #include <asm/processor.h>
-#include <asm/vpe.h>
 #include <asm/rtlx.h>
 #include <asm/setup.h>
+#include <asm/vpe.h>
 
-static struct rtlx_info *rtlx;
-static int major;
-static char module_name[] = "rtlx";
-
-static struct chan_waitqueues {
-        wait_queue_head_t rt_queue;
-        wait_queue_head_t lx_queue;
-        atomic_t in_open;
-        struct mutex mutex;
-} channel_wqs[RTLX_CHANNELS];
-
-static struct vpe_notifications notify;
 static int sp_stopping;
-
-extern void *vpe_get_shared(int index);
-
-static void rtlx_dispatch(void)
-{
-        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
-}
-
-
-/* Interrupt handler may be called before rtlx_init has otherwise had
-   a chance to run.
-*/
-static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
-{
-        unsigned int vpeflags;
-        unsigned long flags;
-        int i;
-
-        /* Ought not to be strictly necessary for SMTC builds */
-        local_irq_save(flags);
-        vpeflags = dvpe();
-        set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
-        irq_enable_hazard();
-        evpe(vpeflags);
-        local_irq_restore(flags);
-
-        for (i = 0; i < RTLX_CHANNELS; i++) {
-                        wake_up(&channel_wqs[i].lx_queue);
-                        wake_up(&channel_wqs[i].rt_queue);
-        }
-
-        return IRQ_HANDLED;
-}
+struct rtlx_info *rtlx;
+struct chan_waitqueues channel_wqs[RTLX_CHANNELS];
+struct vpe_notifications rtlx_notify;
+void (*aprp_hook)(void) = NULL;
+EXPORT_SYMBOL(aprp_hook);
 
 static void __used dump_rtlx(void)
 {
         int i;
 
-        printk("id 0x%lx state %d\n", rtlx->id, rtlx->state);
+        pr_info("id 0x%lx state %d\n", rtlx->id, rtlx->state);
 
         for (i = 0; i < RTLX_CHANNELS; i++) {
                 struct rtlx_channel *chan = &rtlx->channel[i];
 
-                printk(" rt_state %d lx_state %d buffer_size %d\n",
-                       chan->rt_state, chan->lx_state, chan->buffer_size);
+                pr_info(" rt_state %d lx_state %d buffer_size %d\n",
+                        chan->rt_state, chan->lx_state, chan->buffer_size);
 
-                printk(" rt_read %d rt_write %d\n",
-                       chan->rt_read, chan->rt_write);
+                pr_info(" rt_read %d rt_write %d\n",
+                        chan->rt_read, chan->rt_write);
 
-                printk(" lx_read %d lx_write %d\n",
-                       chan->lx_read, chan->lx_write);
+                pr_info(" lx_read %d lx_write %d\n",
+                        chan->lx_read, chan->lx_write);
 
-                printk(" rt_buffer <%s>\n", chan->rt_buffer);
-                printk(" lx_buffer <%s>\n", chan->lx_buffer);
+                pr_info(" rt_buffer <%s>\n", chan->rt_buffer);
+                pr_info(" lx_buffer <%s>\n", chan->lx_buffer);
         }
 }
 
@@ -116,8 +53,7 @@ static void __used dump_rtlx(void)
 static int rtlx_init(struct rtlx_info *rtlxi)
 {
         if (rtlxi->id != RTLX_ID) {
-                printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n",
-                        rtlxi, rtlxi->id);
+                pr_err("no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id);
                 return -ENOEXEC;
         }
 
@@ -127,20 +63,20 @@ static int rtlx_init(struct rtlx_info *rtlxi)
 }
 
 /* notifications */
-static void starting(int vpe)
+void rtlx_starting(int vpe)
 {
         int i;
         sp_stopping = 0;
 
         /* force a reload of rtlx */
-        rtlx=NULL;
+        rtlx = NULL;
 
         /* wake up any sleeping rtlx_open's */
         for (i = 0; i < RTLX_CHANNELS; i++)
                 wake_up_interruptible(&channel_wqs[i].lx_queue);
 }
 
-static void stopping(int vpe)
+void rtlx_stopping(int vpe)
 {
         int i;
 
@@ -158,31 +94,30 @@ int rtlx_open(int index, int can_sleep)
         int ret = 0;
 
         if (index >= RTLX_CHANNELS) {
-                printk(KERN_DEBUG "rtlx_open index out of range\n");
+                pr_debug(KERN_DEBUG "rtlx_open index out of range\n");
                 return -ENOSYS;
         }
 
         if (atomic_inc_return(&channel_wqs[index].in_open) > 1) {
-                printk(KERN_DEBUG "rtlx_open channel %d already opened\n",
-                       index);
+                pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index);
                 ret = -EBUSY;
                 goto out_fail;
         }
 
         if (rtlx == NULL) {
-                if( (p = vpe_get_shared(tclimit)) == NULL) {
-                    if (can_sleep) {
-                        ret = __wait_event_interruptible(
+                p = vpe_get_shared(aprp_cpu_index());
+                if (p == NULL) {
+                        if (can_sleep) {
+                                ret = __wait_event_interruptible(
                                         channel_wqs[index].lx_queue,
-                                        (p = vpe_get_shared(tclimit)));
-                        if (ret)
+                                        (p = vpe_get_shared(aprp_cpu_index())));
+                                if (ret)
+                                        goto out_fail;
+                        } else {
+                                pr_debug("No SP program loaded, and device opened with O_NONBLOCK\n");
+                                ret = -ENOSYS;
                                 goto out_fail;
-                    } else {
-                        printk(KERN_DEBUG "No SP program loaded, and device "
-                                        "opened with O_NONBLOCK\n");
-                        ret = -ENOSYS;
-                        goto out_fail;
-                    }
+                        }
                 }
 
                 smp_rmb();
@@ -204,24 +139,24 @@ int rtlx_open(int index, int can_sleep)
                                         ret = -ERESTARTSYS;
                                         goto out_fail;
                                 }
-                                finish_wait(&channel_wqs[index].lx_queue, &wait);
+                                finish_wait(&channel_wqs[index].lx_queue,
+                                            &wait);
                         } else {
-                                pr_err(" *vpe_get_shared is NULL. "
-                                       "Has an SP program been loaded?\n");
+                                pr_err(" *vpe_get_shared is NULL. Has an SP program been loaded?\n");
                                 ret = -ENOSYS;
                                 goto out_fail;
                         }
                 }
 
                 if ((unsigned int)*p < KSEG0) {
-                        printk(KERN_WARNING "vpe_get_shared returned an "
-                               "invalid pointer maybe an error code %d\n",
-                               (int)*p);
+                        pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n",
+                                (int)*p);
                         ret = -ENOSYS;
                         goto out_fail;
                 }
 
-                if ((ret = rtlx_init(*p)) < 0)
+                ret = rtlx_init(*p);
+                if (ret < 0)
                         goto out_ret;
         }
 
@@ -352,7 +287,7 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
         size_t fl;
 
         if (rtlx == NULL)
-                return(-ENOSYS);
+                return -ENOSYS;
 
         rt = &rtlx->channel[index];
 
@@ -361,8 +296,8 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
         rt_read = rt->rt_read;
 
         /* total number of bytes to copy */
-        count = min(count, (size_t)write_spacefree(rt_read, rt->rt_write,
-                                                        rt->buffer_size));
+        count = min_t(size_t, count, write_spacefree(rt_read, rt->rt_write,
+                                                     rt->buffer_size));
 
         /* first bit from write pointer to the end of the buffer, or count */
         fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
@@ -372,9 +307,8 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
                 goto out;
 
         /* if there's any left copy to the beginning of the buffer */
-        if (count - fl) {
+        if (count - fl)
                 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
-        }
 
 out:
         count -= failed;
@@ -384,6 +318,8 @@ out:
         smp_wmb();
         mutex_unlock(&channel_wqs[index].mutex);
 
+        _interrupt_sp();
+
         return count;
 }
 
@@ -398,7 +334,7 @@ static int file_release(struct inode *inode, struct file *filp)
         return rtlx_release(iminor(inode));
 }
 
-static unsigned int file_poll(struct file *file, poll_table * wait)
+static unsigned int file_poll(struct file *file, poll_table *wait)
 {
         int minor = iminor(file_inode(file));
         unsigned int mask = 0;
@@ -420,21 +356,20 @@ static unsigned int file_poll(struct file *file, poll_table * wait)
         return mask;
 }
 
-static ssize_t file_read(struct file *file, char __user * buffer, size_t count,
-                         loff_t * ppos)
+static ssize_t file_read(struct file *file, char __user *buffer, size_t count,
+                         loff_t *ppos)
 {
         int minor = iminor(file_inode(file));
 
         /* data available? */
-        if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) {
-                return 0;       // -EAGAIN makes cat whinge
-        }
+        if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1))
+                return 0;       /* -EAGAIN makes 'cat' whine */
 
         return rtlx_read(minor, buffer, count);
 }
 
-static ssize_t file_write(struct file *file, const char __user * buffer,
-                          size_t count, loff_t * ppos)
+static ssize_t file_write(struct file *file, const char __user *buffer,
+                          size_t count, loff_t *ppos)
 {
         int minor = iminor(file_inode(file));
 
@@ -454,100 +389,16 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
         return rtlx_write(minor, buffer, count);
 }
 
-static const struct file_operations rtlx_fops = {
+const struct file_operations rtlx_fops = {
         .owner =   THIS_MODULE,
-        .open =    file_open,
+        .open =    file_open,
         .release = file_release,
         .write =   file_write,
-        .read =    file_read,
-        .poll =    file_poll,
+        .read =    file_read,
+        .poll =    file_poll,
         .llseek =  noop_llseek,
 };
 
-static struct irqaction rtlx_irq = {
-        .handler        = rtlx_interrupt,
-        .name           = "RTLX",
-};
-
-static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
-
-static char register_chrdev_failed[] __initdata =
-        KERN_ERR "rtlx_module_init: unable to register device\n";
-
-static int __init rtlx_module_init(void)
-{
-        struct device *dev;
-        int i, err;
-
-        if (!cpu_has_mipsmt) {
-                printk("VPE loader: not a MIPS MT capable processor\n");
-                return -ENODEV;
-        }
-
-        if (tclimit == 0) {
-                printk(KERN_WARNING "No TCs reserved for AP/SP, not "
-                       "initializing RTLX.\nPass maxtcs=<n> argument as kernel "
-                       "argument\n");
-
-                return -ENODEV;
-        }
-
-        major = register_chrdev(0, module_name, &rtlx_fops);
-        if (major < 0) {
-                printk(register_chrdev_failed);
-                return major;
-        }
-
-        /* initialise the wait queues */
-        for (i = 0; i < RTLX_CHANNELS; i++) {
-                init_waitqueue_head(&channel_wqs[i].rt_queue);
-                init_waitqueue_head(&channel_wqs[i].lx_queue);
-                atomic_set(&channel_wqs[i].in_open, 0);
-                mutex_init(&channel_wqs[i].mutex);
-
-                dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
-                                    "%s%d", module_name, i);
-                if (IS_ERR(dev)) {
-                        err = PTR_ERR(dev);
-                        goto out_chrdev;
-                }
-        }
-
-        /* set up notifiers */
-        notify.start = starting;
-        notify.stop = stopping;
-        vpe_notify(tclimit, &notify);
-
-        if (cpu_has_vint)
-                set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
-        else {
-                pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
-                err = -ENODEV;
-                goto out_chrdev;
-        }
-
-        rtlx_irq.dev_id = rtlx;
-        setup_irq(rtlx_irq_num, &rtlx_irq);
-
-        return 0;
-
-out_chrdev:
-        for (i = 0; i < RTLX_CHANNELS; i++)
-                device_destroy(mt_class, MKDEV(major, i));
-
-        return err;
-}
-
-static void __exit rtlx_module_exit(void)
-{
-        int i;
-
-        for (i = 0; i < RTLX_CHANNELS; i++)
-                device_destroy(mt_class, MKDEV(major, i));
-
-        unregister_chrdev(major, module_name);
-}
-
 module_init(rtlx_module_init);
 module_exit(rtlx_module_exit);
 
diff --git a/arch/mips/kernel/segment.c b/arch/mips/kernel/segment.c
new file mode 100644
index 000000000000..076ead2a9859
--- /dev/null
+++ b/arch/mips/kernel/segment.c
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <asm/cpu.h>
+#include <asm/mipsregs.h>
+
+static void build_segment_config(char *str, unsigned int cfg)
+{
+        unsigned int am;
+        static const char * const am_str[] = {
+                "UK", "MK", "MSK", "MUSK", "MUSUK", "USK",
+                "RSRVD", "UUSK"};
+
+        /* Segment access mode. */
+        am = (cfg & MIPS_SEGCFG_AM) >> MIPS_SEGCFG_AM_SHIFT;
+        str += sprintf(str, "%-5s", am_str[am]);
+
+        /*
+         * Access modes MK, MSK and MUSK are mapped segments. Therefore
+         * there is no direct physical address mapping.
+         */
+        if ((am == 0) || (am > 3)) {
+                str += sprintf(str, "         %03lx",
+                        ((cfg & MIPS_SEGCFG_PA) >> MIPS_SEGCFG_PA_SHIFT));
+                str += sprintf(str, "         %01ld",
+                        ((cfg & MIPS_SEGCFG_C) >> MIPS_SEGCFG_C_SHIFT));
+        } else {
+                str += sprintf(str, "         UND");
+                str += sprintf(str, "         U");
+        }
+
+        /* Exception configuration. */
+        str += sprintf(str, "       %01ld\n",
+                ((cfg & MIPS_SEGCFG_EU) >> MIPS_SEGCFG_EU_SHIFT));
+}
+
+static int show_segments(struct seq_file *m, void *v)
+{
+        unsigned int segcfg;
+        char str[42];
+
+        seq_puts(m, "Segment   Virtual    Size   Access Mode   Physical   Caching   EU\n");
+        seq_puts(m, "-------   -------    ----   -----------   --------   -------   --\n");
+
+        segcfg = read_c0_segctl0();
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   0      e0000000   512M      %s", str);
+
+        segcfg >>= 16;
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   1      c0000000   512M      %s", str);
+
+        segcfg = read_c0_segctl1();
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   2      a0000000   512M      %s", str);
+
+        segcfg >>= 16;
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   3      80000000   512M      %s", str);
+
+        segcfg = read_c0_segctl2();
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   4      40000000    1G       %s", str);
+
+        segcfg >>= 16;
+        build_segment_config(str, segcfg);
+        seq_printf(m, "   5      00000000    1G       %s\n", str);
+
+        return 0;
+}
+
+static int segments_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, show_segments, NULL);
+}
+
+static const struct file_operations segments_fops = {
+        .open           = segments_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init segments_info(void)
+{
+        extern struct dentry *mips_debugfs_dir;
+        struct dentry *segments;
+
+        if (cpu_has_segments) {
+                if (!mips_debugfs_dir)
+                        return -ENODEV;
+
+                segments = debugfs_create_file("segments", S_IRUGO,
+                                               mips_debugfs_dir, NULL,
+                                               &segments_fops);
+                if (!segments)
+                        return -ENOMEM;
+        }
+        return 0;
+}
+
+device_initcall(segments_info);
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 2f285abc76d5..5199563c4403 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -71,8 +71,9 @@ static int protected_save_fp_context(struct sigcontext __user *sc)
         int err;
         while (1) {
                 lock_fpu_owner();
-                own_fpu_inatomic(1);
-                err = save_fp_context(sc); /* this might fail */
+                err = own_fpu_inatomic(1);
+                if (!err)
+                        err = save_fp_context(sc); /* this might fail */
                 unlock_fpu_owner();
                 if (likely(!err))
                         break;
@@ -91,8 +92,9 @@ static int protected_restore_fp_context(struct sigcontext __user *sc)
         int err, tmp __maybe_unused;
         while (1) {
                 lock_fpu_owner();
-                own_fpu_inatomic(0);
-                err = restore_fp_context(sc); /* this might fail */
+                err = own_fpu_inatomic(0);
+                if (!err)
+                        err = restore_fp_context(sc); /* this might fail */
                 unlock_fpu_owner();
                 if (likely(!err))
                         break;
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 1905a419aa46..3d60f7750fa8 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -85,8 +85,9 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc)
         int err;
         while (1) {
                 lock_fpu_owner();
-                own_fpu_inatomic(1);
-                err = save_fp_context32(sc); /* this might fail */
+                err = own_fpu_inatomic(1);
+                if (!err)
+                        err = save_fp_context32(sc); /* this might fail */
                 unlock_fpu_owner();
                 if (likely(!err))
                         break;
@@ -105,8 +106,9 @@ static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
         int err, tmp __maybe_unused;
         while (1) {
                 lock_fpu_owner();
-                own_fpu_inatomic(0);
-                err = restore_fp_context32(sc); /* this might fail */
+                err = own_fpu_inatomic(0);
+                if (!err)
+                        err = restore_fp_context32(sc); /* this might fail */
                 unlock_fpu_owner();
                 if (likely(!err))
                         break;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 2362665ba496..ea4c2dc31692 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -49,8 +49,10 @@ cpumask_t bmips_booted_mask;
 unsigned long bmips_smp_boot_sp;
 unsigned long bmips_smp_boot_gp;
 
-static void bmips_send_ipi_single(int cpu, unsigned int action);
-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
+static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
+static void bmips5000_send_ipi_single(int cpu, unsigned int action);
+static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
+static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
 
 /* SW interrupts 0,1 are used for interprocessor signaling */
 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
@@ -64,49 +66,58 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
 static void __init bmips_smp_setup(void)
 {
         int i, cpu = 1, boot_cpu = 0;
-
-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
         int cpu_hw_intr;
 
-        /* arbitration priority */
-        clear_c0_brcm_cmt_ctrl(0x30);
-
-        /* NBK and weak order flags */
-        set_c0_brcm_config_0(0x30000);
-
-        /* Find out if we are running on TP0 or TP1 */
-        boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
-
-        /*
-         * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
-         * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
-         * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
-         */
-        if (boot_cpu == 0)
-                cpu_hw_intr = 0x02;
-        else
-                cpu_hw_intr = 0x1d;
-
-        change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
-
-        /* single core, 2 threads (2 pipelines) */
-        max_cpus = 2;
-#elif defined(CONFIG_CPU_BMIPS5000)
-        /* enable raceless SW interrupts */
-        set_c0_brcm_config(0x03 << 22);
-
-        /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
-        change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
-
-        /* N cores, 2 threads per core */
-        max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
+        switch (current_cpu_type()) {
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                /* arbitration priority */
+                clear_c0_brcm_cmt_ctrl(0x30);
+
+                /* NBK and weak order flags */
+                set_c0_brcm_config_0(0x30000);
+
+                /* Find out if we are running on TP0 or TP1 */
+                boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
+
+                /*
+                 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
+                 * thread
+                 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+                 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+                 */
+                if (boot_cpu == 0)
+                        cpu_hw_intr = 0x02;
+                else
+                        cpu_hw_intr = 0x1d;
+
+                change_c0_brcm_cmt_intr(0xf8018000,
+                                        (cpu_hw_intr << 27) | (0x03 << 15));
+
+                /* single core, 2 threads (2 pipelines) */
+                max_cpus = 2;
+
+                break;
+        case CPU_BMIPS5000:
+                /* enable raceless SW interrupts */
+                set_c0_brcm_config(0x03 << 22);
+
+                /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
+                change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
+
+                /* N cores, 2 threads per core */
+                max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
+
+                /* clear any pending SW interrupts */
+                for (i = 0; i < max_cpus; i++) {
+                        write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
+                        write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
+                }
 
-        /* clear any pending SW interrupts */
-        for (i = 0; i < max_cpus; i++) {
-                write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
-                write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
+                break;
+        default:
+                max_cpus = 1;
         }
-#endif
 
         if (!bmips_smp_enabled)
                 max_cpus = 1;
@@ -134,6 +145,20 @@ static void __init bmips_smp_setup(void)
  */
 static void bmips_prepare_cpus(unsigned int max_cpus)
 {
+        irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
+
+        switch (current_cpu_type()) {
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
+                break;
+        case CPU_BMIPS5000:
+                bmips_ipi_interrupt = bmips5000_ipi_interrupt;
+                break;
+        default:
+                return;
+        }
+
         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
                         "smp_ipi0", NULL))
                 panic("Can't request IPI0 interrupt");
@@ -168,26 +193,39 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 
         pr_info("SMP: Booting CPU%d...\n", cpu);
 
-        if (cpumask_test_cpu(cpu, &bmips_booted_mask))
-                bmips_send_ipi_single(cpu, 0);
+        if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
+                switch (current_cpu_type()) {
+                case CPU_BMIPS4350:
+                case CPU_BMIPS4380:
+                        bmips43xx_send_ipi_single(cpu, 0);
+                        break;
+                case CPU_BMIPS5000:
+                        bmips5000_send_ipi_single(cpu, 0);
+                        break;
+                }
+        }
         else {
-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
-                /* Reset slave TP1 if booting from TP0 */
-                if (cpu_logical_map(cpu) == 1)
-                        set_c0_brcm_cmt_ctrl(0x01);
-#elif defined(CONFIG_CPU_BMIPS5000)
-                if (cpu & 0x01)
-                        write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
-                else {
-                        /*
-                         * core N thread 0 was already booted; just
-                         * pulse the NMI line
-                         */
-                        bmips_write_zscm_reg(0x210, 0xc0000000);
-                        udelay(10);
-                        bmips_write_zscm_reg(0x210, 0x00);
+                switch (current_cpu_type()) {
+                case CPU_BMIPS4350:
+                case CPU_BMIPS4380:
+                        /* Reset slave TP1 if booting from TP0 */
+                        if (cpu_logical_map(cpu) == 1)
+                                set_c0_brcm_cmt_ctrl(0x01);
+                        break;
+                case CPU_BMIPS5000:
+                        if (cpu & 0x01)
+                                write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
+                        else {
+                                /*
+                                 * core N thread 0 was already booted; just
+                                 * pulse the NMI line
+                                 */
+                                bmips_write_zscm_reg(0x210, 0xc0000000);
+                                udelay(10);
+                                bmips_write_zscm_reg(0x210, 0x00);
+                        }
+                        break;
                 }
-#endif
                 cpumask_set_cpu(cpu, &bmips_booted_mask);
         }
 }
@@ -199,26 +237,32 @@ static void bmips_init_secondary(void)
 {
         /* move NMI vector to kseg0, in case XKS01 is enabled */
 
-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
-        void __iomem *cbr = BMIPS_GET_CBR();
+        void __iomem *cbr;
         unsigned long old_vec;
         unsigned long relo_vector;
         int boot_cpu;
 
-        boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
-        relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
-                          BMIPS_RELO_VECTOR_CONTROL_1;
+        switch (current_cpu_type()) {
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+                cbr = BMIPS_GET_CBR();
 
-        old_vec = __raw_readl(cbr + relo_vector);
-        __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
+                boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
+                relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
+                                  BMIPS_RELO_VECTOR_CONTROL_1;
 
-        clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
-#elif defined(CONFIG_CPU_BMIPS5000)
-        write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
-                (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
+                old_vec = __raw_readl(cbr + relo_vector);
+                __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
 
-        write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
-#endif
+                clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
+                break;
+        case CPU_BMIPS5000:
+                write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
+                        (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
+
+                write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
+                break;
+        }
 }
 
 /*
@@ -243,8 +287,6 @@ static void bmips_cpus_done(void)
 {
 }
 
-#if defined(CONFIG_CPU_BMIPS5000)
-
 /*
  * BMIPS5000 raceless IPIs
  *
@@ -253,12 +295,12 @@ static void bmips_cpus_done(void)
  * IPI1 is used for SMP_CALL_FUNCTION
  */
 
-static void bmips_send_ipi_single(int cpu, unsigned int action)
+static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 {
         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 }
 
-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 {
         int action = irq - IPI0_IRQ;
 
@@ -272,7 +314,14 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-#else
+static void bmips5000_send_ipi_mask(const struct cpumask *mask,
+        unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu(i, mask)
+                bmips5000_send_ipi_single(i, action);
+}
 
 /*
  * BMIPS43xx racey IPIs
@@ -287,7 +336,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
 static DEFINE_SPINLOCK(ipi_lock);
 static DEFINE_PER_CPU(int, ipi_action_mask);
 
-static void bmips_send_ipi_single(int cpu, unsigned int action)
+static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 {
         unsigned long flags;
 
@@ -298,7 +347,7 @@ static void bmips_send_ipi_single(int cpu, unsigned int action)
         spin_unlock_irqrestore(&ipi_lock, flags);
 }
 
-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 {
         unsigned long flags;
         int action, cpu = irq - IPI0_IRQ;
@@ -317,15 +366,13 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-#endif /* BMIPS type */
-
-static void bmips_send_ipi_mask(const struct cpumask *mask,
+static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
         unsigned int action)
 {
         unsigned int i;
 
         for_each_cpu(i, mask)
-                bmips_send_ipi_single(i, action);
+                bmips43xx_send_ipi_single(i, action);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -381,15 +428,30 @@ void __ref play_dead(void)
 
 #endif /* CONFIG_HOTPLUG_CPU */
 
-struct plat_smp_ops bmips_smp_ops = {
+struct plat_smp_ops bmips43xx_smp_ops = {
+        .smp_setup              = bmips_smp_setup,
+        .prepare_cpus           = bmips_prepare_cpus,
+        .boot_secondary         = bmips_boot_secondary,
+        .smp_finish             = bmips_smp_finish,
+        .init_secondary         = bmips_init_secondary,
+        .cpus_done              = bmips_cpus_done,
+        .send_ipi_single        = bmips43xx_send_ipi_single,
+        .send_ipi_mask          = bmips43xx_send_ipi_mask,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = bmips_cpu_disable,
+        .cpu_die                = bmips_cpu_die,
+#endif
+};
+
+struct plat_smp_ops bmips5000_smp_ops = {
         .smp_setup              = bmips_smp_setup,
         .prepare_cpus           = bmips_prepare_cpus,
         .boot_secondary         = bmips_boot_secondary,
         .smp_finish             = bmips_smp_finish,
         .init_secondary         = bmips_init_secondary,
         .cpus_done              = bmips_cpus_done,
-        .send_ipi_single        = bmips_send_ipi_single,
-        .send_ipi_mask          = bmips_send_ipi_mask,
+        .send_ipi_single        = bmips5000_send_ipi_single,
+        .send_ipi_mask          = bmips5000_send_ipi_mask,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_disable            = bmips_cpu_disable,
         .cpu_die                = bmips_cpu_die,
@@ -427,43 +489,47 @@ void bmips_ebase_setup(void)
 
         BUG_ON(ebase != CKSEG0);
 
-#if defined(CONFIG_CPU_BMIPS4350)
-        /*
-         * BMIPS4350 cannot relocate the normal vectors, but it
-         * can relocate the BEV=1 vectors.  So CPU1 starts up at
-         * the relocated BEV=1, IV=0 general exception vector @
-         * 0xa000_0380.
-         *
-         * set_uncached_handler() is used here because:
-         *  - CPU1 will run this from uncached space
-         *  - None of the cacheflush functions are set up yet
-         */
-        set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
-                &bmips_smp_int_vec, 0x80);
-        __sync();
-        return;
-#elif defined(CONFIG_CPU_BMIPS4380)
-        /*
-         * 0x8000_0000: reset/NMI (initially in kseg1)
-         * 0x8000_0400: normal vectors
-         */
-        new_ebase = 0x80000400;
-        cbr = BMIPS_GET_CBR();
-        __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
-        __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-#elif defined(CONFIG_CPU_BMIPS5000)
-        /*
-         * 0x8000_0000: reset/NMI (initially in kseg1)
-         * 0x8000_1000: normal vectors
-         */
-        new_ebase = 0x80001000;
-        write_c0_brcm_bootvec(0xa0088008);
-        write_c0_ebase(new_ebase);
-        if (max_cpus > 2)
-                bmips_write_zscm_reg(0xa0, 0xa008a008);
-#else
-        return;
-#endif
+        switch (current_cpu_type()) {
+        case CPU_BMIPS4350:
+                /*
+                 * BMIPS4350 cannot relocate the normal vectors, but it
+                 * can relocate the BEV=1 vectors.  So CPU1 starts up at
+                 * the relocated BEV=1, IV=0 general exception vector @
+                 * 0xa000_0380.
+                 *
+                 * set_uncached_handler() is used here because:
+                 *  - CPU1 will run this from uncached space
+                 *  - None of the cacheflush functions are set up yet
+                 */
+                set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
+                        &bmips_smp_int_vec, 0x80);
+                __sync();
+                return;
+        case CPU_BMIPS4380:
+                /*
+                 * 0x8000_0000: reset/NMI (initially in kseg1)
+                 * 0x8000_0400: normal vectors
+                 */
+                new_ebase = 0x80000400;
+                cbr = BMIPS_GET_CBR();
+                __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+                __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+                break;
+        case CPU_BMIPS5000:
+                /*
+                 * 0x8000_0000: reset/NMI (initially in kseg1)
+                 * 0x8000_1000: normal vectors
+                 */
+                new_ebase = 0x80001000;
+                write_c0_brcm_bootvec(0xa0088008);
+                write_c0_ebase(new_ebase);
+                if (max_cpus > 2)
+                        bmips_write_zscm_reg(0xa0, 0xa008a008);
+                break;
+        default:
+                return;
+        }
+
         board_nmi_handler_setup = &bmips_nmi_handler_setup;
         ebase = new_ebase;
 }
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 5969f1e9b62a..1b925d8a610c 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -199,11 +199,14 @@ void __init cmp_prepare_cpus(unsigned int max_cpus)
         pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
                  smp_processor_id(), __func__, max_cpus);
 
+#ifdef CONFIG_MIPS_MT
         /*
          * FIXME: some of these options are per-system, some per-core and
          * some per-cpu
          */
         mips_mt_set_cpuoptions();
+#endif
+
 }
 
 struct plat_smp_ops cmp_smp_ops = {
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 57a3f7a2b370..0fb8cefc9114 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
 
                 /* Record this as available CPU */
                 set_cpu_possible(tc, true);
+                set_cpu_present(tc, true);
                 __cpu_number_map[tc]    = ++ncpu;
                 __cpu_logical_map[ncpu] = tc;
         }
@@ -112,12 +113,39 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
         write_tc_c0_tchalt(TCHALT_H);
 }
 
+#ifdef CONFIG_IRQ_GIC
+static void mp_send_ipi_single(int cpu, unsigned int action)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        switch (action) {
+        case SMP_CALL_FUNCTION:
+                gic_send_ipi(plat_ipi_call_int_xlate(cpu));
+                break;
+
+        case SMP_RESCHEDULE_YOURSELF:
+                gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
+                break;
+        }
+
+        local_irq_restore(flags);
+}
+#endif
+
 static void vsmp_send_ipi_single(int cpu, unsigned int action)
 {
         int i;
         unsigned long flags;
         int vpflags;
 
+#ifdef CONFIG_IRQ_GIC
+        if (gic_present) {
+                mp_send_ipi_single(cpu, action);
+                return;
+        }
+#endif
         local_irq_save(flags);
 
         vpflags = dvpe();       /* can't access the other CPU's registers whilst MVPE enabled */
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 93f86817f20a..b242e2c10ea0 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -8,7 +8,6 @@
  *
  * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/ptrace.h>
 #include <linux/stddef.h>
@@ -206,6 +205,8 @@ void spram_config(void)
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
                 config0 = read_c0_config();
                 /* FIXME: addresses are Malta specific */
                 if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 84536bf4a154..c24ad5f4b324 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/irqflags.h>
 #include <linux/cpumask.h>
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f9c8746be8d6..e0b499694d18 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -78,6 +78,7 @@ extern asmlinkage void handle_cpu(void);
 extern asmlinkage void handle_ov(void);
 extern asmlinkage void handle_tr(void);
 extern asmlinkage void handle_fpe(void);
+extern asmlinkage void handle_ftlb(void);
 extern asmlinkage void handle_mdmx(void);
 extern asmlinkage void handle_watch(void);
 extern asmlinkage void handle_mt(void);
@@ -1080,7 +1081,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
         unsigned long old_epc, old31;
         unsigned int opcode;
         unsigned int cpid;
-        int status;
+        int status, err;
         unsigned long __maybe_unused flags;
 
         prev_state = exception_enter();
@@ -1153,19 +1154,19 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 
         case 1:
                 if (used_math())        /* Using the FPU again.  */
-                        own_fpu(1);
+                        err = own_fpu(1);
                 else {                  /* First time FPU user.  */
-                        init_fpu();
+                        err = init_fpu();
                         set_used_math();
                 }
 
-                if (!raw_cpu_has_fpu) {
+                if (!raw_cpu_has_fpu || err) {
                         int sig;
                         void __user *fault_addr = NULL;
                         sig = fpu_emulator_cop1Handler(regs,
                                                        &current->thread.fpu,
                                                        0, &fault_addr);
-                        if (!process_fpemu_return(sig, fault_addr))
+                        if (!process_fpemu_return(sig, fault_addr) && !err)
                                 mt_ase_fp_affinity();
                 }
 
@@ -1336,6 +1337,8 @@ static inline void parity_protection_init(void)
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
                 {
 #define ERRCTL_PE       0x80000000
 #define ERRCTL_L2P      0x00800000
@@ -1425,14 +1428,27 @@ asmlinkage void cache_parity_error(void)
         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
                reg_val & (1<<30) ? "secondary" : "primary",
                reg_val & (1<<31) ? "data" : "insn");
-        printk("Error bits: %s%s%s%s%s%s%s\n",
-               reg_val & (1<<29) ? "ED " : "",
-               reg_val & (1<<28) ? "ET " : "",
-               reg_val & (1<<26) ? "EE " : "",
-               reg_val & (1<<25) ? "EB " : "",
-               reg_val & (1<<24) ? "EI " : "",
-               reg_val & (1<<23) ? "E1 " : "",
-               reg_val & (1<<22) ? "E0 " : "");
+        if (cpu_has_mips_r2 &&
+            ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
+                pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
+                        reg_val & (1<<29) ? "ED " : "",
+                        reg_val & (1<<28) ? "ET " : "",
+                        reg_val & (1<<27) ? "ES " : "",
+                        reg_val & (1<<26) ? "EE " : "",
+                        reg_val & (1<<25) ? "EB " : "",
+                        reg_val & (1<<24) ? "EI " : "",
+                        reg_val & (1<<23) ? "E1 " : "",
+                        reg_val & (1<<22) ? "E0 " : "");
+        } else {
+                pr_err("Error bits: %s%s%s%s%s%s%s\n",
+                        reg_val & (1<<29) ? "ED " : "",
+                        reg_val & (1<<28) ? "ET " : "",
+                        reg_val & (1<<26) ? "EE " : "",
+                        reg_val & (1<<25) ? "EB " : "",
+                        reg_val & (1<<24) ? "EI " : "",
+                        reg_val & (1<<23) ? "E1 " : "",
+                        reg_val & (1<<22) ? "E0 " : "");
+        }
         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 
 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
@@ -1446,6 +1462,34 @@ asmlinkage void cache_parity_error(void)
         panic("Can't handle the cache error!");
 }
 
+asmlinkage void do_ftlb(void)
+{
+        const int field = 2 * sizeof(unsigned long);
+        unsigned int reg_val;
+
+        /* For the moment, report the problem and hang. */
+        if (cpu_has_mips_r2 &&
+            ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
+                pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
+                       read_c0_ecc());
+                pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
+                reg_val = read_c0_cacheerr();
+                pr_err("c0_cacheerr == %08x\n", reg_val);
+
+                if ((reg_val & 0xc0000000) == 0xc0000000) {
+                        pr_err("Decoded c0_cacheerr: FTLB parity error\n");
+                } else {
+                        pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
+                               reg_val & (1<<30) ? "secondary" : "primary",
+                               reg_val & (1<<31) ? "data" : "insn");
+                }
+        } else {
+                pr_err("FTLB error exception\n");
+        }
+        /* Just print the cacheerr bits for now */
+        cache_parity_error();
+}
+
 /*
  * SDBBP EJTAG debug exception handler.
  * We skip the instruction and return to the next instruction.
@@ -1995,6 +2039,7 @@ void __init trap_init(void)
         if (cpu_has_fpu && !cpu_has_nofpuex)
                 set_except_vector(15, handle_fpe);
 
+        set_except_vector(16, handle_ftlb);
         set_except_vector(22, handle_mdmx);
 
         if (cpu_has_mcheck)
diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c
new file mode 100644
index 000000000000..9268ebc0f61e
--- /dev/null
+++ b/arch/mips/kernel/vpe-cmp.c
@@ -0,0 +1,180 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+
+#include <asm/vpe.h>
+
+static int major;
+
+void cleanup_tc(struct tc *tc)
+{
+
+}
+
+static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+                          const char *buf, size_t len)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+        struct vpe_notifications *notifier;
+
+        list_for_each_entry(notifier, &vpe->notify, list)
+                notifier->stop(aprp_cpu_index());
+
+        release_progmem(vpe->load_addr);
+        vpe->state = VPE_STATE_UNUSED;
+
+        return len;
+}
+static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
+
+static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
+                         char *buf)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+
+        return sprintf(buf, "%d\n", vpe->ntcs);
+}
+
+static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
+                          const char *buf, size_t len)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+        unsigned long new;
+        int ret;
+
+        ret = kstrtoul(buf, 0, &new);
+        if (ret < 0)
+                return ret;
+
+        /* APRP can only reserve one TC in a VPE and no more. */
+        if (new != 1)
+                return -EINVAL;
+
+        vpe->ntcs = new;
+
+        return len;
+}
+static DEVICE_ATTR_RW(ntcs);
+
+static struct attribute *vpe_attrs[] = {
+        &dev_attr_kill.attr,
+        &dev_attr_ntcs.attr,
+        NULL,
+};
+ATTRIBUTE_GROUPS(vpe);
+
+static void vpe_device_release(struct device *cd)
+{
+        kfree(cd);
+}
+
+static struct class vpe_class = {
+        .name = "vpe",
+        .owner = THIS_MODULE,
+        .dev_release = vpe_device_release,
+        .dev_groups = vpe_groups,
+};
+
+static struct device vpe_device;
+
+int __init vpe_module_init(void)
+{
+        struct vpe *v = NULL;
+        struct tc *t;
+        int err;
+
+        if (!cpu_has_mipsmt) {
+                pr_warn("VPE loader: not a MIPS MT capable processor\n");
+                return -ENODEV;
+        }
+
+        if (num_possible_cpus() - aprp_cpu_index() < 1) {
+                pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
+                        "Pass maxcpus=<n> argument as kernel argument\n");
+                return -ENODEV;
+        }
+
+        major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
+        if (major < 0) {
+                pr_warn("VPE loader: unable to register character device\n");
+                return major;
+        }
+
+        err = class_register(&vpe_class);
+        if (err) {
+                pr_err("vpe_class registration failed\n");
+                goto out_chrdev;
+        }
+
+        device_initialize(&vpe_device);
+        vpe_device.class        = &vpe_class,
+        vpe_device.parent       = NULL,
+        dev_set_name(&vpe_device, "vpe_sp");
+        vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
+        err = device_add(&vpe_device);
+        if (err) {
+                pr_err("Adding vpe_device failed\n");
+                goto out_class;
+        }
+
+        t = alloc_tc(aprp_cpu_index());
+        if (!t) {
+                pr_warn("VPE: unable to allocate TC\n");
+                err = -ENOMEM;
+                goto out_dev;
+        }
+
+        /* VPE */
+        v = alloc_vpe(aprp_cpu_index());
+        if (v == NULL) {
+                pr_warn("VPE: unable to allocate VPE\n");
+                kfree(t);
+                err = -ENOMEM;
+                goto out_dev;
+        }
+
+        v->ntcs = 1;
+
+        /* add the tc to the list of this vpe's tc's. */
+        list_add(&t->tc, &v->tc);
+
+        /* TC */
+        t->pvpe = v;    /* set the parent vpe */
+
+        return 0;
+
+out_dev:
+        device_del(&vpe_device);
+
+out_class:
+        class_unregister(&vpe_class);
+
+out_chrdev:
+        unregister_chrdev(major, VPE_MODULE_NAME);
+
+        return err;
+}
+
+void __exit vpe_module_exit(void)
+{
+        struct vpe *v, *n;
+
+        device_del(&vpe_device);
+        class_unregister(&vpe_class);
+        unregister_chrdev(major, VPE_MODULE_NAME);
+
+        /* No locking needed here */
+        list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list)
+                if (v->state != VPE_STATE_UNUSED)
+                        release_vpe(v);
+}
diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c
new file mode 100644
index 000000000000..949ae0e17018
--- /dev/null
+++ b/arch/mips/kernel/vpe-mt.c
@@ -0,0 +1,523 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ */
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+
+#include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
+#include <asm/mips_mt.h>
+#include <asm/vpe.h>
+
+static int major;
+
+/* The number of TCs and VPEs physically available on the core */
+static int hw_tcs, hw_vpes;
+
+/* We are prepared so configure and start the VPE... */
+int vpe_run(struct vpe *v)
+{
+        unsigned long flags, val, dmt_flag;
+        struct vpe_notifications *notifier;
+        unsigned int vpeflags;
+        struct tc *t;
+
+        /* check we are the Master VPE */
+        local_irq_save(flags);
+        val = read_c0_vpeconf0();
+        if (!(val & VPECONF0_MVP)) {
+                pr_warn("VPE loader: only Master VPE's are able to config MT\n");
+                local_irq_restore(flags);
+
+                return -1;
+        }
+
+        dmt_flag = dmt();
+        vpeflags = dvpe();
+
+        if (list_empty(&v->tc)) {
+                evpe(vpeflags);
+                emt(dmt_flag);
+                local_irq_restore(flags);
+
+                pr_warn("VPE loader: No TC's associated with VPE %d\n",
+                        v->minor);
+
+                return -ENOEXEC;
+        }
+
+        t = list_first_entry(&v->tc, struct tc, tc);
+
+        /* Put MVPE's into 'configuration state' */
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        settc(t->index);
+
+        /* should check it is halted, and not activated */
+        if ((read_tc_c0_tcstatus() & TCSTATUS_A) ||
+           !(read_tc_c0_tchalt() & TCHALT_H)) {
+                evpe(vpeflags);
+                emt(dmt_flag);
+                local_irq_restore(flags);
+
+                pr_warn("VPE loader: TC %d is already active!\n",
+                        t->index);
+
+                return -ENOEXEC;
+        }
+
+        /*
+         * Write the address we want it to start running from in the TCPC
+         * register.
+         */
+        write_tc_c0_tcrestart((unsigned long)v->__start);
+        write_tc_c0_tccontext((unsigned long)0);
+
+        /*
+         * Mark the TC as activated, not interrupt exempt and not dynamically
+         * allocatable
+         */
+        val = read_tc_c0_tcstatus();
+        val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A;
+        write_tc_c0_tcstatus(val);
+
+        write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
+
+        /*
+         * The sde-kit passes 'memsize' to __start in $a3, so set something
+         * here...  Or set $a3 to zero and define DFLT_STACK_SIZE and
+         * DFLT_HEAP_SIZE when you compile your program
+         */
+        mttgpr(6, v->ntcs);
+        mttgpr(7, physical_memsize);
+
+        /* set up VPE1 */
+        /*
+         * bind the TC to VPE 1 as late as possible so we only have the final
+         * VPE registers to set up, and so an EJTAG probe can trigger on it
+         */
+        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
+
+        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
+
+        back_to_back_c0_hazard();
+
+        /* Set up the XTC bit in vpeconf0 to point at our tc */
+        write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
+                              | (t->index << VPECONF0_XTC_SHIFT));
+
+        back_to_back_c0_hazard();
+
+        /* enable this VPE */
+        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
+
+        /* clear out any left overs from a previous program */
+        write_vpe_c0_status(0);
+        write_vpe_c0_cause(0);
+
+        /* take system out of configuration state */
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        /*
+         * SMTC/SMVP kernels manage VPE enable independently,
+         * but uniprocessor kernels need to turn it on, even
+         * if that wasn't the pre-dvpe() state.
+         */
+#ifdef CONFIG_SMP
+        evpe(vpeflags);
+#else
+        evpe(EVPE_ENABLE);
+#endif
+        emt(dmt_flag);
+        local_irq_restore(flags);
+
+        list_for_each_entry(notifier, &v->notify, list)
+                notifier->start(VPE_MODULE_MINOR);
+
+        return 0;
+}
+
+void cleanup_tc(struct tc *tc)
+{
+        unsigned long flags;
+        unsigned int mtflags, vpflags;
+        int tmp;
+
+        local_irq_save(flags);
+        mtflags = dmt();
+        vpflags = dvpe();
+        /* Put MVPE's into 'configuration state' */
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        settc(tc->index);
+        tmp = read_tc_c0_tcstatus();
+
+        /* mark not allocated and not dynamically allocatable */
+        tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
+        tmp |= TCSTATUS_IXMT;   /* interrupt exempt */
+        write_tc_c0_tcstatus(tmp);
+
+        write_tc_c0_tchalt(TCHALT_H);
+        mips_ihb();
+
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+        evpe(vpflags);
+        emt(mtflags);
+        local_irq_restore(flags);
+}
+
+/* module wrapper entry points */
+/* give me a vpe */
+void *vpe_alloc(void)
+{
+        int i;
+        struct vpe *v;
+
+        /* find a vpe */
+        for (i = 1; i < MAX_VPES; i++) {
+                v = get_vpe(i);
+                if (v != NULL) {
+                        v->state = VPE_STATE_INUSE;
+                        return v;
+                }
+        }
+        return NULL;
+}
+EXPORT_SYMBOL(vpe_alloc);
+
+/* start running from here */
+int vpe_start(void *vpe, unsigned long start)
+{
+        struct vpe *v = vpe;
+
+        v->__start = start;
+        return vpe_run(v);
+}
+EXPORT_SYMBOL(vpe_start);
+
+/* halt it for now */
+int vpe_stop(void *vpe)
+{
+        struct vpe *v = vpe;
+        struct tc *t;
+        unsigned int evpe_flags;
+
+        evpe_flags = dvpe();
+
+        t = list_entry(v->tc.next, struct tc, tc);
+        if (t != NULL) {
+                settc(t->index);
+                write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
+        }
+
+        evpe(evpe_flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(vpe_stop);
+
+/* I've done with it thank you */
+int vpe_free(void *vpe)
+{
+        struct vpe *v = vpe;
+        struct tc *t;
+        unsigned int evpe_flags;
+
+        t = list_entry(v->tc.next, struct tc, tc);
+        if (t == NULL)
+                return -ENOEXEC;
+
+        evpe_flags = dvpe();
+
+        /* Put MVPE's into 'configuration state' */
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        settc(t->index);
+        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
+
+        /* halt the TC */
+        write_tc_c0_tchalt(TCHALT_H);
+        mips_ihb();
+
+        /* mark the TC unallocated */
+        write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
+
+        v->state = VPE_STATE_UNUSED;
+
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+        evpe(evpe_flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(vpe_free);
+
+static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+                          const char *buf, size_t len)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+        struct vpe_notifications *notifier;
+
+        list_for_each_entry(notifier, &vpe->notify, list)
+                notifier->stop(aprp_cpu_index());
+
+        release_progmem(vpe->load_addr);
+        cleanup_tc(get_tc(aprp_cpu_index()));
+        vpe_stop(vpe);
+        vpe_free(vpe);
+
+        return len;
+}
+static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
+
+static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
+                         char *buf)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+
+        return sprintf(buf, "%d\n", vpe->ntcs);
+}
+
+static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
+                          const char *buf, size_t len)
+{
+        struct vpe *vpe = get_vpe(aprp_cpu_index());
+        unsigned long new;
+        int ret;
+
+        ret = kstrtoul(buf, 0, &new);
+        if (ret < 0)
+                return ret;
+
+        if (new == 0 || new > (hw_tcs - aprp_cpu_index()))
+                return -EINVAL;
+
+        vpe->ntcs = new;
+
+        return len;
+}
+static DEVICE_ATTR_RW(ntcs);
+
+static struct attribute *vpe_attrs[] = {
+        &dev_attr_kill.attr,
+        &dev_attr_ntcs.attr,
+        NULL,
+};
+ATTRIBUTE_GROUPS(vpe);
+
+static void vpe_device_release(struct device *cd)
+{
+        kfree(cd);
+}
+
+static struct class vpe_class = {
+        .name = "vpe",
+        .owner = THIS_MODULE,
+        .dev_release = vpe_device_release,
+        .dev_groups = vpe_groups,
+};
+
+static struct device vpe_device;
+
+int __init vpe_module_init(void)
+{
+        unsigned int mtflags, vpflags;
+        unsigned long flags, val;
+        struct vpe *v = NULL;
+        struct tc *t;
+        int tc, err;
+
+        if (!cpu_has_mipsmt) {
+                pr_warn("VPE loader: not a MIPS MT capable processor\n");
+                return -ENODEV;
+        }
+
+        if (vpelimit == 0) {
+                pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
+                        "Pass maxvpes=<n> argument as kernel argument\n");
+
+                return -ENODEV;
+        }
+
+        if (aprp_cpu_index() == 0) {
+                pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n"
+                        "Pass maxtcs=<n> argument as kernel argument\n");
+
+                return -ENODEV;
+        }
+
+        major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
+        if (major < 0) {
+                pr_warn("VPE loader: unable to register character device\n");
+                return major;
+        }
+
+        err = class_register(&vpe_class);
+        if (err) {
+                pr_err("vpe_class registration failed\n");
+                goto out_chrdev;
+        }
+
+        device_initialize(&vpe_device);
+        vpe_device.class        = &vpe_class,
+        vpe_device.parent       = NULL,
+        dev_set_name(&vpe_device, "vpe1");
+        vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
+        err = device_add(&vpe_device);
+        if (err) {
+                pr_err("Adding vpe_device failed\n");
+                goto out_class;
+        }
+
+        local_irq_save(flags);
+        mtflags = dmt();
+        vpflags = dvpe();
+
+        /* Put MVPE's into 'configuration state' */
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        val = read_c0_mvpconf0();
+        hw_tcs = (val & MVPCONF0_PTC) + 1;
+        hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+
+        for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) {
+                /*
+                 * Must re-enable multithreading temporarily or in case we
+                 * reschedule send IPIs or similar we might hang.
+                 */
+                clear_c0_mvpcontrol(MVPCONTROL_VPC);
+                evpe(vpflags);
+                emt(mtflags);
+                local_irq_restore(flags);
+                t = alloc_tc(tc);
+                if (!t) {
+                        err = -ENOMEM;
+                        goto out_dev;
+                }
+
+                local_irq_save(flags);
+                mtflags = dmt();
+                vpflags = dvpe();
+                set_c0_mvpcontrol(MVPCONTROL_VPC);
+
+                /* VPE's */
+                if (tc < hw_tcs) {
+                        settc(tc);
+
+                        v = alloc_vpe(tc);
+                        if (v == NULL) {
+                                pr_warn("VPE: unable to allocate VPE\n");
+                                goto out_reenable;
+                        }
+
+                        v->ntcs = hw_tcs - aprp_cpu_index();
+
+                        /* add the tc to the list of this vpe's tc's. */
+                        list_add(&t->tc, &v->tc);
+
+                        /* deactivate all but vpe0 */
+                        if (tc >= aprp_cpu_index()) {
+                                unsigned long tmp = read_vpe_c0_vpeconf0();
+
+                                tmp &= ~VPECONF0_VPA;
+
+                                /* master VPE */
+                                tmp |= VPECONF0_MVP;
+                                write_vpe_c0_vpeconf0(tmp);
+                        }
+
+                        /* disable multi-threading with TC's */
+                        write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() &
+                                                ~VPECONTROL_TE);
+
+                        if (tc >= vpelimit) {
+                                /*
+                                 * Set config to be the same as vpe0,
+                                 * particularly kseg0 coherency alg
+                                 */
+                                write_vpe_c0_config(read_c0_config());
+                        }
+                }
+
+                /* TC's */
+                t->pvpe = v;    /* set the parent vpe */
+
+                if (tc >= aprp_cpu_index()) {
+                        unsigned long tmp;
+
+                        settc(tc);
+
+                        /* Any TC that is bound to VPE0 gets left as is - in
+                         * case we are running SMTC on VPE0. A TC that is bound
+                         * to any other VPE gets bound to VPE0, ideally I'd like
+                         * to make it homeless but it doesn't appear to let me
+                         * bind a TC to a non-existent VPE. Which is perfectly
+                         * reasonable.
+                         *
+                         * The (un)bound state is visible to an EJTAG probe so
+                         * may notify GDB...
+                         */
+                        tmp = read_tc_c0_tcbind();
+                        if (tmp & TCBIND_CURVPE) {
+                                /* tc is bound >vpe0 */
+                                write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE);
+
+                                t->pvpe = get_vpe(0);   /* set the parent vpe */
+                        }
+
+                        /* halt the TC */
+                        write_tc_c0_tchalt(TCHALT_H);
+                        mips_ihb();
+
+                        tmp = read_tc_c0_tcstatus();
+
+                        /* mark not activated and not dynamically allocatable */
+                        tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
+                        tmp |= TCSTATUS_IXMT;   /* interrupt exempt */
+                        write_tc_c0_tcstatus(tmp);
+                }
+        }
+
+out_reenable:
+        /* release config state */
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+
+        evpe(vpflags);
+        emt(mtflags);
+        local_irq_restore(flags);
+
+        return 0;
+
+out_dev:
+        device_del(&vpe_device);
+
+out_class:
+        class_unregister(&vpe_class);
+
+out_chrdev:
+        unregister_chrdev(major, VPE_MODULE_NAME);
+
+        return err;
+}
+
+void __exit vpe_module_exit(void)
+{
+        struct vpe *v, *n;
+
+        device_del(&vpe_device);
+        class_unregister(&vpe_class);
+        unregister_chrdev(major, VPE_MODULE_NAME);
+
+        /* No locking needed here */
+        list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
+                if (v->state != VPE_STATE_UNUSED)
+                        release_vpe(v);
+        }
+}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 59b2b3cd7885..11da314565cc 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1,37 +1,22 @@
 /*
- * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-/*
- * VPE support module
- *
- * Provides support for loading a MIPS SP program on VPE1.
- * The SP environment is rather simple, no tlb's.  It needs to be relocatable
- * (or partially linked). You should initialise your stack in the startup
- * code. This loader looks for the symbol __start and sets up
- * execution to resume from there. The MIPS SDE kit contains suitable examples.
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  *
- * To load and run, simply cat a SP 'program file' to /dev/vpe1.
- * i.e cat spapp >/dev/vpe1.
+ * VPE spport module for loading a MIPS SP program into VPE1. The SP
+ * environment is rather simple since there are no TLBs. It needs
+ * to be relocatable (or partiall linked). Initialize your stack in
+ * the startup-code. The loader looks for the symbol __start and sets
+ * up the execution to resume from there. To load and run, simply do
+ * a cat SP 'binary' to the /dev/vpe1 device.
  */
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/fs.h>
 #include <linux/init.h>
-#include <asm/uaccess.h>
 #include <linux/slab.h>
 #include <linux/list.h>
 #include <linux/vmalloc.h>
@@ -46,13 +31,10 @@
 #include <asm/mipsmtregs.h>
 #include <asm/cacheflush.h>
 #include <linux/atomic.h>
-#include <asm/cpu.h>
 #include <asm/mips_mt.h>
 #include <asm/processor.h>
 #include <asm/vpe.h>
 
-typedef void *vpe_handle;
-
 #ifndef ARCH_SHF_SMALL
 #define ARCH_SHF_SMALL 0
 #endif
@@ -60,96 +42,15 @@ typedef void *vpe_handle;
 /* If this is set, the section belongs in the init part of the module */
 #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1))
 
-/*
- * The number of TCs and VPEs physically available on the core
- */
-static int hw_tcs, hw_vpes;
-static char module_name[] = "vpe";
-static int major;
-static const int minor = 1;     /* fixed for now  */
-
-/* grab the likely amount of memory we will need. */
-#ifdef CONFIG_MIPS_VPE_LOADER_TOM
-#define P_SIZE (2 * 1024 * 1024)
-#else
-/* add an overhead to the max kmalloc size for non-striped symbols/etc */
-#define P_SIZE (256 * 1024)
-#endif
-
-extern unsigned long physical_memsize;
-
-#define MAX_VPES 16
-#define VPE_PATH_MAX 256
-
-enum vpe_state {
-        VPE_STATE_UNUSED = 0,
-        VPE_STATE_INUSE,
-        VPE_STATE_RUNNING
-};
-
-enum tc_state {
-        TC_STATE_UNUSED = 0,
-        TC_STATE_INUSE,
-        TC_STATE_RUNNING,
-        TC_STATE_DYNAMIC
-};
-
-struct vpe {
-        enum vpe_state state;
-
-        /* (device) minor associated with this vpe */
-        int minor;
-
-        /* elfloader stuff */
-        void *load_addr;
-        unsigned long len;
-        char *pbuffer;
-        unsigned long plen;
-        unsigned int uid, gid;
-        char cwd[VPE_PATH_MAX];
-
-        unsigned long __start;
-
-        /* tc's associated with this vpe */
-        struct list_head tc;
-
-        /* The list of vpe's */
-        struct list_head list;
-
-        /* shared symbol address */
-        void *shared_ptr;
-
-        /* the list of who wants to know when something major happens */
-        struct list_head notify;
-
-        unsigned int ntcs;
-};
-
-struct tc {
-        enum tc_state state;
-        int index;
-
-        struct vpe *pvpe;       /* parent VPE */
-        struct list_head tc;    /* The list of TC's with this VPE */
-        struct list_head list;  /* The global list of tc's */
-};
-
-struct {
-        spinlock_t vpe_list_lock;
-        struct list_head vpe_list;      /* Virtual processing elements */
-        spinlock_t tc_list_lock;
-        struct list_head tc_list;       /* Thread contexts */
-} vpecontrol = {
+struct vpe_control vpecontrol = {
         .vpe_list_lock  = __SPIN_LOCK_UNLOCKED(vpe_list_lock),
         .vpe_list       = LIST_HEAD_INIT(vpecontrol.vpe_list),
         .tc_list_lock   = __SPIN_LOCK_UNLOCKED(tc_list_lock),
         .tc_list        = LIST_HEAD_INIT(vpecontrol.tc_list)
 };
 
-static void release_progmem(void *ptr);
-
 /* get the vpe associated with this minor */
-static struct vpe *get_vpe(int minor)
+struct vpe *get_vpe(int minor)
 {
         struct vpe *res, *v;
 
@@ -159,7 +60,7 @@ static struct vpe *get_vpe(int minor)
         res = NULL;
         spin_lock(&vpecontrol.vpe_list_lock);
         list_for_each_entry(v, &vpecontrol.vpe_list, list) {
-                if (v->minor == minor) {
+                if (v->minor == VPE_MODULE_MINOR) {
                         res = v;
                         break;
                 }
@@ -170,7 +71,7 @@ static struct vpe *get_vpe(int minor)
 }
 
 /* get the vpe associated with this minor */
-static struct tc *get_tc(int index)
+struct tc *get_tc(int index)
 {
         struct tc *res, *t;
 
@@ -188,12 +89,13 @@ static struct tc *get_tc(int index)
 }
 
 /* allocate a vpe and associate it with this minor (or index) */
-static struct vpe *alloc_vpe(int minor)
+struct vpe *alloc_vpe(int minor)
 {
         struct vpe *v;
 
-        if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL)
-                return NULL;
+        v = kzalloc(sizeof(struct vpe), GFP_KERNEL);
+        if (v == NULL)
+                goto out;
 
         INIT_LIST_HEAD(&v->tc);
         spin_lock(&vpecontrol.vpe_list_lock);
@@ -201,17 +103,19 @@ static struct vpe *alloc_vpe(int minor)
         spin_unlock(&vpecontrol.vpe_list_lock);
 
         INIT_LIST_HEAD(&v->notify);
-        v->minor = minor;
+        v->minor = VPE_MODULE_MINOR;
 
+out:
         return v;
 }
 
 /* allocate a tc. At startup only tc0 is running, all other can be halted. */
-static struct tc *alloc_tc(int index)
+struct tc *alloc_tc(int index)
 {
         struct tc *tc;
 
-        if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL)
+        tc = kzalloc(sizeof(struct tc), GFP_KERNEL);
+        if (tc == NULL)
                 goto out;
 
         INIT_LIST_HEAD(&tc->tc);
@@ -226,7 +130,7 @@ out:
 }
 
 /* clean up and free everything */
-static void release_vpe(struct vpe *v)
+void release_vpe(struct vpe *v)
 {
         list_del(&v->list);
         if (v->load_addr)
@@ -234,28 +138,8 @@ static void release_vpe(struct vpe *v)
         kfree(v);
 }
 
-static void __maybe_unused dump_mtregs(void)
-{
-        unsigned long val;
-
-        val = read_c0_config3();
-        printk("config3 0x%lx MT %ld\n", val,
-               (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT);
-
-        val = read_c0_mvpcontrol();
-        printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val,
-               (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT,
-               (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT,
-               (val & MVPCONTROL_EVP));
-
-        val = read_c0_mvpconf0();
-        printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val,
-               (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT,
-               val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
-}
-
-/* Find some VPE program space  */
-static void *alloc_progmem(unsigned long len)
+/* Find some VPE program space */
+void *alloc_progmem(unsigned long len)
 {
         void *addr;
 
@@ -274,7 +158,7 @@ static void *alloc_progmem(unsigned long len)
         return addr;
 }
 
-static void release_progmem(void *ptr)
+void release_progmem(void *ptr)
 {
 #ifndef CONFIG_MIPS_VPE_LOADER_TOM
         kfree(ptr);
@@ -282,7 +166,7 @@ static void release_progmem(void *ptr)
 }
 
 /* Update size with this section: return offset. */
-static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
+static long get_offset(unsigned long *size, Elf_Shdr *sechdr)
 {
         long ret;
 
@@ -295,8 +179,8 @@ static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
    might -- code, read-only data, read-write data, small data.  Tally
    sizes, and place the offsets into sh_entsize fields: high bit means it
    belongs in init. */
-static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
-                            Elf_Shdr * sechdrs, const char *secstrings)
+static void layout_sections(struct module *mod, const Elf_Ehdr *hdr,
+                            Elf_Shdr *sechdrs, const char *secstrings)
 {
         static unsigned long const masks[][2] = {
                 /* NOTE: all executable code must be the first section
@@ -316,7 +200,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
                 for (i = 0; i < hdr->e_shnum; ++i) {
                         Elf_Shdr *s = &sechdrs[i];
 
-                        //  || strncmp(secstrings + s->sh_name, ".init", 5) == 0)
                         if ((s->sh_flags & masks[m][0]) != masks[m][0]
                             || (s->sh_flags & masks[m][1])
                             || s->sh_entsize != ~0UL)
@@ -331,7 +214,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
         }
 }
 
-
 /* from module-elf32.c, but subverted a little */
 
 struct mips_hi16 {
@@ -354,20 +236,18 @@ static int apply_r_mips_gprel16(struct module *me, uint32_t *location,
 {
         int rel;
 
-        if( !(*location & 0xffff) ) {
+        if (!(*location & 0xffff)) {
                 rel = (int)v - gp_addr;
-        }
-        else {
+        } else {
                 /* .sbss + gp(relative) + offset */
                 /* kludge! */
                 rel =  (int)(short)((int)v + gp_offs +
                                     (int)(short)(*location & 0xffff) - gp_addr);
         }
 
-        if( (rel > 32768) || (rel < -32768) ) {
-                printk(KERN_DEBUG "VPE loader: apply_r_mips_gprel16: "
-                       "relative address 0x%x out of range of gp register\n",
-                       rel);
+        if ((rel > 32768) || (rel < -32768)) {
+                pr_debug("VPE loader: apply_r_mips_gprel16: relative address 0x%x out of range of gp register\n",
+                         rel);
                 return -ENOEXEC;
         }
 
@@ -381,12 +261,12 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location,
 {
         int rel;
         rel = (((unsigned int)v - (unsigned int)location));
-        rel >>= 2;              // because the offset is in _instructions_ not bytes.
-        rel -= 1;               // and one instruction less due to the branch delay slot.
+        rel >>= 2; /* because the offset is in _instructions_ not bytes. */
+        rel -= 1;  /* and one instruction less due to the branch delay slot. */
 
-        if( (rel > 32768) || (rel < -32768) ) {
-                printk(KERN_DEBUG "VPE loader: "
-                       "apply_r_mips_pc16: relative address out of range 0x%x\n", rel);
+        if ((rel > 32768) || (rel < -32768)) {
+                pr_debug("VPE loader: apply_r_mips_pc16: relative address out of range 0x%x\n",
+                         rel);
                 return -ENOEXEC;
         }
 
@@ -407,8 +287,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location,
                            Elf32_Addr v)
 {
         if (v % 4) {
-                printk(KERN_DEBUG "VPE loader: apply_r_mips_26 "
-                       " unaligned relocation\n");
+                pr_debug("VPE loader: apply_r_mips_26: unaligned relocation\n");
                 return -ENOEXEC;
         }
 
@@ -439,7 +318,7 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location,
          * the carry we need to add.  Save the information, and let LO16 do the
          * actual relocation.
          */
-        n = kmalloc(sizeof *n, GFP_KERNEL);
+        n = kmalloc(sizeof(*n), GFP_KERNEL);
         if (!n)
                 return -ENOMEM;
 
@@ -471,9 +350,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
                          * The value for the HI16 had best be the same.
                          */
                         if (v != l->value) {
-                                printk(KERN_DEBUG "VPE loader: "
-                                       "apply_r_mips_lo16/hi16: \t"
-                                       "inconsistent value information\n");
+                                pr_debug("VPE loader: apply_r_mips_lo16/hi16: inconsistent value information\n");
                                 goto out_free;
                         }
 
@@ -569,20 +446,19 @@ static int apply_relocations(Elf32_Shdr *sechdrs,
                         + ELF32_R_SYM(r_info);
 
                 if (!sym->st_value) {
-                        printk(KERN_DEBUG "%s: undefined weak symbol %s\n",
-                               me->name, strtab + sym->st_name);
+                        pr_debug("%s: undefined weak symbol %s\n",
+                                 me->name, strtab + sym->st_name);
                         /* just print the warning, dont barf */
                 }
 
                 v = sym->st_value;
 
                 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
-                if( res ) {
+                if (res) {
                         char *r = rstrs[ELF32_R_TYPE(r_info)];
-                        printk(KERN_WARNING "VPE loader: .text+0x%x "
-                               "relocation type %s for symbol \"%s\" failed\n",
-                               rel[i].r_offset, r ? r : "UNKNOWN",
-                               strtab + sym->st_name);
+                        pr_warn("VPE loader: .text+0x%x relocation type %s for symbol \"%s\" failed\n",
+                                rel[i].r_offset, r ? r : "UNKNOWN",
+                                strtab + sym->st_name);
                         return res;
                 }
         }
@@ -597,10 +473,8 @@ static inline void save_gp_address(unsigned int secbase, unsigned int rel)
 }
 /* end module-elf32.c */
 
-
-
 /* Change all symbols so that sh_value encodes the pointer directly. */
-static void simplify_symbols(Elf_Shdr * sechdrs,
+static void simplify_symbols(Elf_Shdr *sechdrs,
                             unsigned int symindex,
                             const char *strtab,
                             const char *secstrings,
@@ -641,18 +515,16 @@ static void simplify_symbols(Elf_Shdr * sechdrs,
                         break;
 
                 case SHN_MIPS_SCOMMON:
-                        printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON "
-                               "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name,
-                               sym[i].st_shndx);
-                        // .sbss section
+                        pr_debug("simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n",
+                                 strtab + sym[i].st_name, sym[i].st_shndx);
+                        /* .sbss section */
                         break;
 
                 default:
                         secbase = sechdrs[sym[i].st_shndx].sh_addr;
 
-                        if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) {
+                        if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0)
                                 save_gp_address(secbase, sym[i].st_value);
-                        }
 
                         sym[i].st_value += secbase;
                         break;
@@ -661,142 +533,21 @@ static void simplify_symbols(Elf_Shdr * sechdrs,
 }
 
 #ifdef DEBUG_ELFLOADER
-static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex,
+static void dump_elfsymbols(Elf_Shdr *sechdrs, unsigned int symindex,
                             const char *strtab, struct module *mod)
 {
         Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr;
         unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
 
-        printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n);
+        pr_debug("dump_elfsymbols: n %d\n", n);
         for (i = 1; i < n; i++) {
-                printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i,
-                       strtab + sym[i].st_name, sym[i].st_value);
+                pr_debug(" i %d name <%s> 0x%x\n", i, strtab + sym[i].st_name,
+                         sym[i].st_value);
         }
 }
 #endif
 
-/* We are prepared so configure and start the VPE... */
-static int vpe_run(struct vpe * v)
-{
-        unsigned long flags, val, dmt_flag;
-        struct vpe_notifications *n;
-        unsigned int vpeflags;
-        struct tc *t;
-
-        /* check we are the Master VPE */
-        local_irq_save(flags);
-        val = read_c0_vpeconf0();
-        if (!(val & VPECONF0_MVP)) {
-                printk(KERN_WARNING
-                       "VPE loader: only Master VPE's are allowed to configure MT\n");
-                local_irq_restore(flags);
-
-                return -1;
-        }
-
-        dmt_flag = dmt();
-        vpeflags = dvpe();
-
-        if (list_empty(&v->tc)) {
-                evpe(vpeflags);
-                emt(dmt_flag);
-                local_irq_restore(flags);
-
-                printk(KERN_WARNING
-                       "VPE loader: No TC's associated with VPE %d\n",
-                       v->minor);
-
-                return -ENOEXEC;
-        }
-
-        t = list_first_entry(&v->tc, struct tc, tc);
-
-        /* Put MVPE's into 'configuration state' */
-        set_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        settc(t->index);
-
-        /* should check it is halted, and not activated */
-        if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) {
-                evpe(vpeflags);
-                emt(dmt_flag);
-                local_irq_restore(flags);
-
-                printk(KERN_WARNING "VPE loader: TC %d is already active!\n",
-                       t->index);
-
-                return -ENOEXEC;
-        }
-
-        /* Write the address we want it to start running from in the TCPC register. */
-        write_tc_c0_tcrestart((unsigned long)v->__start);
-        write_tc_c0_tccontext((unsigned long)0);
-
-        /*
-         * Mark the TC as activated, not interrupt exempt and not dynamically
-         * allocatable
-         */
-        val = read_tc_c0_tcstatus();
-        val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A;
-        write_tc_c0_tcstatus(val);
-
-        write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
-
-        /*
-         * The sde-kit passes 'memsize' to __start in $a3, so set something
-         * here...  Or set $a3 to zero and define DFLT_STACK_SIZE and
-         * DFLT_HEAP_SIZE when you compile your program
-         */
-        mttgpr(6, v->ntcs);
-        mttgpr(7, physical_memsize);
-
-        /* set up VPE1 */
-        /*
-         * bind the TC to VPE 1 as late as possible so we only have the final
-         * VPE registers to set up, and so an EJTAG probe can trigger on it
-         */
-        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
-
-        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
-
-        back_to_back_c0_hazard();
-
-        /* Set up the XTC bit in vpeconf0 to point at our tc */
-        write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
-                              | (t->index << VPECONF0_XTC_SHIFT));
-
-        back_to_back_c0_hazard();
-
-        /* enable this VPE */
-        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
-
-        /* clear out any left overs from a previous program */
-        write_vpe_c0_status(0);
-        write_vpe_c0_cause(0);
-
-        /* take system out of configuration state */
-        clear_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        /*
-         * SMTC/SMVP kernels manage VPE enable independently,
-         * but uniprocessor kernels need to turn it on, even
-         * if that wasn't the pre-dvpe() state.
-         */
-#ifdef CONFIG_SMP
-        evpe(vpeflags);
-#else
-        evpe(EVPE_ENABLE);
-#endif
-        emt(dmt_flag);
-        local_irq_restore(flags);
-
-        list_for_each_entry(n, &v->notify, list)
-                n->start(minor);
-
-        return 0;
-}
-
-static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
+static int find_vpe_symbols(struct vpe *v, Elf_Shdr *sechdrs,
                                       unsigned int symindex, const char *strtab,
                                       struct module *mod)
 {
@@ -804,16 +555,14 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
         unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
 
         for (i = 1; i < n; i++) {
-                if (strcmp(strtab + sym[i].st_name, "__start") == 0) {
+                if (strcmp(strtab + sym[i].st_name, "__start") == 0)
                         v->__start = sym[i].st_value;
-                }
 
-                if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) {
+                if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0)
                         v->shared_ptr = (void *)sym[i].st_value;
-                }
         }
 
-        if ( (v->__start == 0) || (v->shared_ptr == NULL))
+        if ((v->__start == 0) || (v->shared_ptr == NULL))
                 return -1;
 
         return 0;
@@ -824,14 +573,14 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
  * contents of the program (p)buffer performing relocatations/etc, free's it
  * when finished.
  */
-static int vpe_elfload(struct vpe * v)
+static int vpe_elfload(struct vpe *v)
 {
         Elf_Ehdr *hdr;
         Elf_Shdr *sechdrs;
         long err = 0;
         char *secstrings, *strtab = NULL;
         unsigned int len, i, symindex = 0, strindex = 0, relocate = 0;
-        struct module mod;      // so we can re-use the relocations code
+        struct module mod; /* so we can re-use the relocations code */
 
         memset(&mod, 0, sizeof(struct module));
         strcpy(mod.name, "VPE loader");
@@ -845,8 +594,7 @@ static int vpe_elfload(struct vpe * v)
             || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC)
             || !elf_check_arch(hdr)
             || hdr->e_shentsize != sizeof(*sechdrs)) {
-                printk(KERN_WARNING
-                       "VPE loader: program wrong arch or weird elf version\n");
+                pr_warn("VPE loader: program wrong arch or weird elf version\n");
 
                 return -ENOEXEC;
         }
@@ -855,8 +603,7 @@ static int vpe_elfload(struct vpe * v)
                 relocate = 1;
 
         if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) {
-                printk(KERN_ERR "VPE loader: program length %u truncated\n",
-                       len);
+                pr_err("VPE loader: program length %u truncated\n", len);
 
                 return -ENOEXEC;
         }
@@ -871,22 +618,24 @@ static int vpe_elfload(struct vpe * v)
 
         if (relocate) {
                 for (i = 1; i < hdr->e_shnum; i++) {
-                        if (sechdrs[i].sh_type != SHT_NOBITS
-                            && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) {
-                                printk(KERN_ERR "VPE program length %u truncated\n",
+                        if ((sechdrs[i].sh_type != SHT_NOBITS) &&
+                            (len < sechdrs[i].sh_offset + sechdrs[i].sh_size)) {
+                                pr_err("VPE program length %u truncated\n",
                                        len);
                                 return -ENOEXEC;
                         }
 
                         /* Mark all sections sh_addr with their address in the
                            temporary image. */
-                        sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
+                        sechdrs[i].sh_addr = (size_t) hdr +
+                                sechdrs[i].sh_offset;
 
                         /* Internal symbols and strings. */
                         if (sechdrs[i].sh_type == SHT_SYMTAB) {
                                 symindex = i;
                                 strindex = sechdrs[i].sh_link;
-                                strtab = (char *)hdr + sechdrs[strindex].sh_offset;
+                                strtab = (char *)hdr +
+                                        sechdrs[strindex].sh_offset;
                         }
                 }
                 layout_sections(&mod, hdr, sechdrs, secstrings);
@@ -913,8 +662,9 @@ static int vpe_elfload(struct vpe * v)
                         /* Update sh_addr to point to copy in image. */
                         sechdrs[i].sh_addr = (unsigned long)dest;
 
-                        printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n",
-                               secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr);
+                        pr_debug(" section sh_name %s sh_addr 0x%x\n",
+                                 secstrings + sechdrs[i].sh_name,
+                                 sechdrs[i].sh_addr);
                 }
 
                 /* Fix up syms, so that st_value is a pointer to location. */
@@ -935,17 +685,18 @@ static int vpe_elfload(struct vpe * v)
                                 continue;
 
                         if (sechdrs[i].sh_type == SHT_REL)
-                                err = apply_relocations(sechdrs, strtab, symindex, i,
-                                                        &mod);
+                                err = apply_relocations(sechdrs, strtab,
+                                                        symindex, i, &mod);
                         else if (sechdrs[i].sh_type == SHT_RELA)
-                                err = apply_relocate_add(sechdrs, strtab, symindex, i,
-                                                         &mod);
+                                err = apply_relocate_add(sechdrs, strtab,
+                                                         symindex, i, &mod);
                         if (err < 0)
                                 return err;
 
                 }
         } else {
-                struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
+                struct elf_phdr *phdr = (struct elf_phdr *)
+                                                ((char *)hdr + hdr->e_phoff);
 
                 for (i = 0; i < hdr->e_phnum; i++) {
                         if (phdr->p_type == PT_LOAD) {
@@ -963,11 +714,15 @@ static int vpe_elfload(struct vpe * v)
                         if (sechdrs[i].sh_type == SHT_SYMTAB) {
                                 symindex = i;
                                 strindex = sechdrs[i].sh_link;
-                                strtab = (char *)hdr + sechdrs[strindex].sh_offset;
+                                strtab = (char *)hdr +
+                                        sechdrs[strindex].sh_offset;
 
-                                /* mark the symtab's address for when we try to find the
-                                   magic symbols */
-                                sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
+                                /*
+                                 * mark symtab's address for when we try
+                                 * to find the magic symbols
+                                 */
+                                sechdrs[i].sh_addr = (size_t) hdr +
+                                        sechdrs[i].sh_offset;
                         }
                 }
         }
@@ -978,53 +733,19 @@ static int vpe_elfload(struct vpe * v)
 
         if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
                 if (v->__start == 0) {
-                        printk(KERN_WARNING "VPE loader: program does not contain "
-                               "a __start symbol\n");
+                        pr_warn("VPE loader: program does not contain a __start symbol\n");
                         return -ENOEXEC;
                 }
 
                 if (v->shared_ptr == NULL)
-                        printk(KERN_WARNING "VPE loader: "
-                               "program does not contain vpe_shared symbol.\n"
-                               " Unable to use AMVP (AP/SP) facilities.\n");
+                        pr_warn("VPE loader: program does not contain vpe_shared symbol.\n"
+                                " Unable to use AMVP (AP/SP) facilities.\n");
         }
 
-        printk(" elf loaded\n");
+        pr_info(" elf loaded\n");
         return 0;
 }
 
-static void cleanup_tc(struct tc *tc)
-{
-        unsigned long flags;
-        unsigned int mtflags, vpflags;
-        int tmp;
-
-        local_irq_save(flags);
-        mtflags = dmt();
-        vpflags = dvpe();
-        /* Put MVPE's into 'configuration state' */
-        set_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        settc(tc->index);
-        tmp = read_tc_c0_tcstatus();
-
-        /* mark not allocated and not dynamically allocatable */
-        tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
-        tmp |= TCSTATUS_IXMT;   /* interrupt exempt */
-        write_tc_c0_tcstatus(tmp);
-
-        write_tc_c0_tchalt(TCHALT_H);
-        mips_ihb();
-
-        /* bind it to anything other than VPE1 */
-//      write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
-
-        clear_c0_mvpcontrol(MVPCONTROL_VPC);
-        evpe(vpflags);
-        emt(mtflags);
-        local_irq_restore(flags);
-}
-
 static int getcwd(char *buff, int size)
 {
         mm_segment_t old_fs;
@@ -1044,52 +765,49 @@ static int getcwd(char *buff, int size)
 static int vpe_open(struct inode *inode, struct file *filp)
 {
         enum vpe_state state;
-        struct vpe_notifications *not;
+        struct vpe_notifications *notifier;
         struct vpe *v;
         int ret;
 
-        if (minor != iminor(inode)) {
+        if (VPE_MODULE_MINOR != iminor(inode)) {
                 /* assume only 1 device at the moment. */
-                pr_warning("VPE loader: only vpe1 is supported\n");
+                pr_warn("VPE loader: only vpe1 is supported\n");
 
                 return -ENODEV;
         }
 
-        if ((v = get_vpe(tclimit)) == NULL) {
-                pr_warning("VPE loader: unable to get vpe\n");
+        v = get_vpe(aprp_cpu_index());
+        if (v == NULL) {
+                pr_warn("VPE loader: unable to get vpe\n");
 
                 return -ENODEV;
         }
 
         state = xchg(&v->state, VPE_STATE_INUSE);
         if (state != VPE_STATE_UNUSED) {
-                printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n");
+                pr_debug("VPE loader: tc in use dumping regs\n");
 
-                list_for_each_entry(not, &v->notify, list) {
-                        not->stop(tclimit);
-                }
+                list_for_each_entry(notifier, &v->notify, list)
+                        notifier->stop(aprp_cpu_index());
 
                 release_progmem(v->load_addr);
-                cleanup_tc(get_tc(tclimit));
+                cleanup_tc(get_tc(aprp_cpu_index()));
         }
 
         /* this of-course trashes what was there before... */
         v->pbuffer = vmalloc(P_SIZE);
         if (!v->pbuffer) {
-                pr_warning("VPE loader: unable to allocate memory\n");
+                pr_warn("VPE loader: unable to allocate memory\n");
                 return -ENOMEM;
         }
         v->plen = P_SIZE;
         v->load_addr = NULL;
         v->len = 0;
 
-        v->uid = filp->f_cred->fsuid;
-        v->gid = filp->f_cred->fsgid;
-
         v->cwd[0] = 0;
         ret = getcwd(v->cwd, VPE_PATH_MAX);
         if (ret < 0)
-                printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret);
+                pr_warn("VPE loader: open, getcwd returned %d\n", ret);
 
         v->shared_ptr = NULL;
         v->__start = 0;
@@ -1103,20 +821,20 @@ static int vpe_release(struct inode *inode, struct file *filp)
         Elf_Ehdr *hdr;
         int ret = 0;
 
-        v = get_vpe(tclimit);
+        v = get_vpe(aprp_cpu_index());
         if (v == NULL)
                 return -ENODEV;
 
         hdr = (Elf_Ehdr *) v->pbuffer;
         if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) {
-                if (vpe_elfload(v) >= 0) {
+                if ((vpe_elfload(v) >= 0) && vpe_run) {
                         vpe_run(v);
                 } else {
-                        printk(KERN_WARNING "VPE loader: ELF load failed.\n");
+                        pr_warn("VPE loader: ELF load failed.\n");
                         ret = -ENOEXEC;
                 }
         } else {
-                printk(KERN_WARNING "VPE loader: only elf files are supported\n");
+                pr_warn("VPE loader: only elf files are supported\n");
                 ret = -ENOEXEC;
         }
 
@@ -1134,22 +852,22 @@ static int vpe_release(struct inode *inode, struct file *filp)
         return ret;
 }
 
-static ssize_t vpe_write(struct file *file, const char __user * buffer,
-                         size_t count, loff_t * ppos)
+static ssize_t vpe_write(struct file *file, const char __user *buffer,
+                         size_t count, loff_t *ppos)
 {
         size_t ret = count;
         struct vpe *v;
 
-        if (iminor(file_inode(file)) != minor)
+        if (iminor(file_inode(file)) != VPE_MODULE_MINOR)
                 return -ENODEV;
 
-        v = get_vpe(tclimit);
+        v = get_vpe(aprp_cpu_index());
+
         if (v == NULL)
                 return -ENODEV;
 
         if ((count + v->len) > v->plen) {
-                printk(KERN_WARNING
-                       "VPE loader: elf size too big. Perhaps strip uneeded symbols\n");
+                pr_warn("VPE loader: elf size too big. Perhaps strip uneeded symbols\n");
                 return -ENOMEM;
         }
 
@@ -1161,7 +879,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
         return ret;
 }
 
-static const struct file_operations vpe_fops = {
+const struct file_operations vpe_fops = {
         .owner = THIS_MODULE,
         .open = vpe_open,
         .release = vpe_release,
@@ -1169,420 +887,40 @@ static const struct file_operations vpe_fops = {
         .llseek = noop_llseek,
 };
 
-/* module wrapper entry points */
-/* give me a vpe */
-vpe_handle vpe_alloc(void)
-{
-        int i;
-        struct vpe *v;
-
-        /* find a vpe */
-        for (i = 1; i < MAX_VPES; i++) {
-                if ((v = get_vpe(i)) != NULL) {
-                        v->state = VPE_STATE_INUSE;
-                        return v;
-                }
-        }
-        return NULL;
-}
-
-EXPORT_SYMBOL(vpe_alloc);
-
-/* start running from here */
-int vpe_start(vpe_handle vpe, unsigned long start)
-{
-        struct vpe *v = vpe;
-
-        v->__start = start;
-        return vpe_run(v);
-}
-
-EXPORT_SYMBOL(vpe_start);
-
-/* halt it for now */
-int vpe_stop(vpe_handle vpe)
-{
-        struct vpe *v = vpe;
-        struct tc *t;
-        unsigned int evpe_flags;
-
-        evpe_flags = dvpe();
-
-        if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) {
-
-                settc(t->index);
-                write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
-        }
-
-        evpe(evpe_flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(vpe_stop);
-
-/* I've done with it thank you */
-int vpe_free(vpe_handle vpe)
-{
-        struct vpe *v = vpe;
-        struct tc *t;
-        unsigned int evpe_flags;
-
-        if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
-                return -ENOEXEC;
-        }
-
-        evpe_flags = dvpe();
-
-        /* Put MVPE's into 'configuration state' */
-        set_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        settc(t->index);
-        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
-
-        /* halt the TC */
-        write_tc_c0_tchalt(TCHALT_H);
-        mips_ihb();
-
-        /* mark the TC unallocated */
-        write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
-
-        v->state = VPE_STATE_UNUSED;
-
-        clear_c0_mvpcontrol(MVPCONTROL_VPC);
-        evpe(evpe_flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(vpe_free);
-
 void *vpe_get_shared(int index)
 {
-        struct vpe *v;
+        struct vpe *v = get_vpe(index);
 
-        if ((v = get_vpe(index)) == NULL)
+        if (v == NULL)
                 return NULL;
 
         return v->shared_ptr;
 }
-
 EXPORT_SYMBOL(vpe_get_shared);
 
-int vpe_getuid(int index)
-{
-        struct vpe *v;
-
-        if ((v = get_vpe(index)) == NULL)
-                return -1;
-
-        return v->uid;
-}
-
-EXPORT_SYMBOL(vpe_getuid);
-
-int vpe_getgid(int index)
-{
-        struct vpe *v;
-
-        if ((v = get_vpe(index)) == NULL)
-                return -1;
-
-        return v->gid;
-}
-
-EXPORT_SYMBOL(vpe_getgid);
-
 int vpe_notify(int index, struct vpe_notifications *notify)
 {
-        struct vpe *v;
+        struct vpe *v = get_vpe(index);
 
-        if ((v = get_vpe(index)) == NULL)
+        if (v == NULL)
                 return -1;
 
         list_add(&notify->list, &v->notify);
         return 0;
 }
-
 EXPORT_SYMBOL(vpe_notify);
 
 char *vpe_getcwd(int index)
 {
-        struct vpe *v;
+        struct vpe *v = get_vpe(index);
 
-        if ((v = get_vpe(index)) == NULL)
+        if (v == NULL)
                 return NULL;
 
         return v->cwd;
 }
-
 EXPORT_SYMBOL(vpe_getcwd);
 
-static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
-                          const char *buf, size_t len)
-{
-        struct vpe *vpe = get_vpe(tclimit);
-        struct vpe_notifications *not;
-
-        list_for_each_entry(not, &vpe->notify, list) {
-                not->stop(tclimit);
-        }
-
-        release_progmem(vpe->load_addr);
-        cleanup_tc(get_tc(tclimit));
-        vpe_stop(vpe);
-        vpe_free(vpe);
-
-        return len;
-}
-static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
-
-static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
-                         char *buf)
-{
-        struct vpe *vpe = get_vpe(tclimit);
-
-        return sprintf(buf, "%d\n", vpe->ntcs);
-}
-
-static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
-                          const char *buf, size_t len)
-{
-        struct vpe *vpe = get_vpe(tclimit);
-        unsigned long new;
-        char *endp;
-
-        new = simple_strtoul(buf, &endp, 0);
-        if (endp == buf)
-                goto out_einval;
-
-        if (new == 0 || new > (hw_tcs - tclimit))
-                goto out_einval;
-
-        vpe->ntcs = new;
-
-        return len;
-
-out_einval:
-        return -EINVAL;
-}
-static DEVICE_ATTR_RW(ntcs);
-
-static struct attribute *vpe_attrs[] = {
-        &dev_attr_kill.attr,
-        &dev_attr_ntcs.attr,
-        NULL,
-};
-ATTRIBUTE_GROUPS(vpe);
-
-static void vpe_device_release(struct device *cd)
-{
-        kfree(cd);
-}
-
-struct class vpe_class = {
-        .name = "vpe",
-        .owner = THIS_MODULE,
-        .dev_release = vpe_device_release,
-        .dev_groups = vpe_groups,
-};
-
-struct device vpe_device;
-
-static int __init vpe_module_init(void)
-{
-        unsigned int mtflags, vpflags;
-        unsigned long flags, val;
-        struct vpe *v = NULL;
-        struct tc *t;
-        int tc, err;
-
-        if (!cpu_has_mipsmt) {
-                printk("VPE loader: not a MIPS MT capable processor\n");
-                return -ENODEV;
-        }
-
-        if (vpelimit == 0) {
-                printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
-                       "initializing VPE loader.\nPass maxvpes=<n> argument as "
-                       "kernel argument\n");
-
-                return -ENODEV;
-        }
-
-        if (tclimit == 0) {
-                printk(KERN_WARNING "No TCs reserved for AP/SP, not "
-                       "initializing VPE loader.\nPass maxtcs=<n> argument as "
-                       "kernel argument\n");
-
-                return -ENODEV;
-        }
-
-        major = register_chrdev(0, module_name, &vpe_fops);
-        if (major < 0) {
-                printk("VPE loader: unable to register character device\n");
-                return major;
-        }
-
-        err = class_register(&vpe_class);
-        if (err) {
-                printk(KERN_ERR "vpe_class registration failed\n");
-                goto out_chrdev;
-        }
-
-        device_initialize(&vpe_device);
-        vpe_device.class        = &vpe_class,
-        vpe_device.parent       = NULL,
-        dev_set_name(&vpe_device, "vpe1");
-        vpe_device.devt = MKDEV(major, minor);
-        err = device_add(&vpe_device);
-        if (err) {
-                printk(KERN_ERR "Adding vpe_device failed\n");
-                goto out_class;
-        }
-
-        local_irq_save(flags);
-        mtflags = dmt();
-        vpflags = dvpe();
-
-        /* Put MVPE's into 'configuration state' */
-        set_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        /* dump_mtregs(); */
-
-        val = read_c0_mvpconf0();
-        hw_tcs = (val & MVPCONF0_PTC) + 1;
-        hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
-
-        for (tc = tclimit; tc < hw_tcs; tc++) {
-                /*
-                 * Must re-enable multithreading temporarily or in case we
-                 * reschedule send IPIs or similar we might hang.
-                 */
-                clear_c0_mvpcontrol(MVPCONTROL_VPC);
-                evpe(vpflags);
-                emt(mtflags);
-                local_irq_restore(flags);
-                t = alloc_tc(tc);
-                if (!t) {
-                        err = -ENOMEM;
-                        goto out;
-                }
-
-                local_irq_save(flags);
-                mtflags = dmt();
-                vpflags = dvpe();
-                set_c0_mvpcontrol(MVPCONTROL_VPC);
-
-                /* VPE's */
-                if (tc < hw_tcs) {
-                        settc(tc);
-
-                        if ((v = alloc_vpe(tc)) == NULL) {
-                                printk(KERN_WARNING "VPE: unable to allocate VPE\n");
-
-                                goto out_reenable;
-                        }
-
-                        v->ntcs = hw_tcs - tclimit;
-
-                        /* add the tc to the list of this vpe's tc's. */
-                        list_add(&t->tc, &v->tc);
-
-                        /* deactivate all but vpe0 */
-                        if (tc >= tclimit) {
-                                unsigned long tmp = read_vpe_c0_vpeconf0();
-
-                                tmp &= ~VPECONF0_VPA;
-
-                                /* master VPE */
-                                tmp |= VPECONF0_MVP;
-                                write_vpe_c0_vpeconf0(tmp);
-                        }
-
-                        /* disable multi-threading with TC's */
-                        write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
-
-                        if (tc >= vpelimit) {
-                                /*
-                                 * Set config to be the same as vpe0,
-                                 * particularly kseg0 coherency alg
-                                 */
-                                write_vpe_c0_config(read_c0_config());
-                        }
-                }
-
-                /* TC's */
-                t->pvpe = v;    /* set the parent vpe */
-
-                if (tc >= tclimit) {
-                        unsigned long tmp;
-
-                        settc(tc);
-
-                        /* Any TC that is bound to VPE0 gets left as is - in case
-                           we are running SMTC on VPE0. A TC that is bound to any
-                           other VPE gets bound to VPE0, ideally I'd like to make
-                           it homeless but it doesn't appear to let me bind a TC
-                           to a non-existent VPE. Which is perfectly reasonable.
-
-                           The (un)bound state is visible to an EJTAG probe so may
-                           notify GDB...
-                        */
-
-                        if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) {
-                                /* tc is bound >vpe0 */
-                                write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE);
-
-                                t->pvpe = get_vpe(0);   /* set the parent vpe */
-                        }
-
-                        /* halt the TC */
-                        write_tc_c0_tchalt(TCHALT_H);
-                        mips_ihb();
-
-                        tmp = read_tc_c0_tcstatus();
-
-                        /* mark not activated and not dynamically allocatable */
-                        tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
-                        tmp |= TCSTATUS_IXMT;   /* interrupt exempt */
-                        write_tc_c0_tcstatus(tmp);
-                }
-        }
-
-out_reenable:
-        /* release config state */
-        clear_c0_mvpcontrol(MVPCONTROL_VPC);
-
-        evpe(vpflags);
-        emt(mtflags);
-        local_irq_restore(flags);
-
-        return 0;
-
-out_class:
-        class_unregister(&vpe_class);
-out_chrdev:
-        unregister_chrdev(major, module_name);
-
-out:
-        return err;
-}
-
-static void __exit vpe_module_exit(void)
-{
-        struct vpe *v, *n;
-
-        device_del(&vpe_device);
-        unregister_chrdev(major, module_name);
-
-        /* No locking needed here */
-        list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
-                if (v->state != VPE_STATE_UNUSED)
-                        release_vpe(v);
-        }
-}
-
 module_init(vpe_module_init);
 module_exit(vpe_module_exit);
 MODULE_DESCRIPTION("MIPS VPE Loader");
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index 73b34827826c..da5186fbd77a 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -1001,7 +1001,6 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
                      HRTIMER_MODE_REL);
         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
-        kvm_mips_init_shadow_tlb(vcpu);
         return 0;
 }
 
diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c
index c777dd36d4a8..50ab9c4d4a5d 100644
--- a/arch/mips/kvm/kvm_tlb.c
+++ b/arch/mips/kvm/kvm_tlb.c
@@ -10,7 +10,6 @@
 * Authors: Sanjay Lal <sanjayl@kymasys.com>
 */
 
-#include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
@@ -25,6 +24,7 @@
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
+#include <asm/tlb.h>
 
 #undef CONFIG_MIPS_MT
 #include <asm/r4kcache.h>
@@ -35,9 +35,6 @@
 
 #define PRIx64 "llx"
 
-/* Use VZ EntryHi.EHINV to invalidate TLB entries */
-#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-
 atomic_t kvm_mips_instance;
 EXPORT_SYMBOL(kvm_mips_instance);
 
@@ -147,30 +144,6 @@ void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
         }
 }
 
-void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu)
-{
-        int i;
-        volatile struct kvm_mips_tlb tlb;
-
-        printk("Shadow TLBs:\n");
-        for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
-                tlb = vcpu->arch.shadow_tlb[smp_processor_id()][i];
-                printk("TLB%c%3d Hi 0x%08lx ",
-                       (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
-                       i, tlb.tlb_hi);
-                printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ",
-                       (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
-                       (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
-                       (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
-                       (tlb.tlb_lo0 >> 3) & 7);
-                printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n",
-                       (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
-                       (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
-                       (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
-                       (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
-        }
-}
-
 static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn)
 {
         int srcu_idx, err = 0;
@@ -657,70 +630,6 @@ kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
         cpu_context(cpu, mm) = asid_cache(cpu) = asid;
 }
 
-void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu)
-{
-        unsigned long flags;
-        unsigned long old_entryhi;
-        unsigned long old_pagemask;
-        int entry = 0;
-        int cpu = smp_processor_id();
-
-        local_irq_save(flags);
-
-        old_entryhi = read_c0_entryhi();
-        old_pagemask = read_c0_pagemask();
-
-        for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
-                write_c0_index(entry);
-                mtc0_tlbw_hazard();
-                tlb_read();
-                tlbw_use_hazard();
-
-                vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = read_c0_entryhi();
-                vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = read_c0_entrylo0();
-                vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = read_c0_entrylo1();
-                vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = read_c0_pagemask();
-        }
-
-        write_c0_entryhi(old_entryhi);
-        write_c0_pagemask(old_pagemask);
-        mtc0_tlbw_hazard();
-
-        local_irq_restore(flags);
-
-}
-
-void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu)
-{
-        unsigned long flags;
-        unsigned long old_ctx;
-        int entry;
-        int cpu = smp_processor_id();
-
-        local_irq_save(flags);
-
-        old_ctx = read_c0_entryhi();
-
-        for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
-                write_c0_entryhi(vcpu->arch.shadow_tlb[cpu][entry].tlb_hi);
-                mtc0_tlbw_hazard();
-                write_c0_entrylo0(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0);
-                write_c0_entrylo1(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1);
-
-                write_c0_index(entry);
-                mtc0_tlbw_hazard();
-
-                tlb_write_indexed();
-                tlbw_use_hazard();
-        }
-
-        tlbw_use_hazard();
-        write_c0_entryhi(old_ctx);
-        mtc0_tlbw_hazard();
-        local_irq_restore(flags);
-}
-
-
 void kvm_local_flush_tlb_all(void)
 {
         unsigned long flags;
@@ -749,30 +658,6 @@ void kvm_local_flush_tlb_all(void)
         local_irq_restore(flags);
 }
 
-void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu)
-{
-        int cpu, entry;
-
-        for_each_possible_cpu(cpu) {
-                for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
-                        vcpu->arch.shadow_tlb[cpu][entry].tlb_hi =
-                            UNIQUE_ENTRYHI(entry);
-                        vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = 0x0;
-                        vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = 0x0;
-                        vcpu->arch.shadow_tlb[cpu][entry].tlb_mask =
-                            read_c0_pagemask();
-#ifdef DEBUG
-                        kvm_debug
-                            ("shadow_tlb[%d][%d]: tlb_hi: %#lx, lo0: %#lx, lo1: %#lx\n",
-                             cpu, entry,
-                             vcpu->arch.shadow_tlb[cpu][entry].tlb_hi,
-                             vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0,
-                             vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1);
-#endif
-                }
-        }
-}
-
 /* Restore ASID once we are scheduled back after preemption */
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
@@ -810,14 +695,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
                          vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id);
         }
 
-        /* Only reload shadow host TLB if new ASIDs haven't been allocated */
-#if 0
-        if ((atomic_read(&kvm_mips_instance) > 1) && !newasid) {
-                kvm_mips_flush_host_tlb(0);
-                kvm_shadow_tlb_load(vcpu);
-        }
-#endif
-
         if (!newasid) {
                 /* If we preempted while the guest was executing, then reload the pre-empted ASID */
                 if (current->flags & PF_VCPU) {
@@ -863,12 +740,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
         vcpu->arch.preempt_entryhi = read_c0_entryhi();
         vcpu->arch.last_sched_cpu = cpu;
 
-#if 0
-        if ((atomic_read(&kvm_mips_instance) > 1)) {
-                kvm_shadow_tlb_put(vcpu);
-        }
-#endif
-
         if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) &
              ASID_VERSION_MASK)) {
                 kvm_debug("%s: Dropping MMU Context:  %#lx\n", __func__,
@@ -930,10 +801,8 @@ uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu)
 }
 
 EXPORT_SYMBOL(kvm_local_flush_tlb_all);
-EXPORT_SYMBOL(kvm_shadow_tlb_put);
 EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault);
 EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault);
-EXPORT_SYMBOL(kvm_mips_init_shadow_tlb);
 EXPORT_SYMBOL(kvm_mips_dump_host_tlbs);
 EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault);
 EXPORT_SYMBOL(kvm_mips_host_tlb_lookup);
@@ -941,8 +810,6 @@ EXPORT_SYMBOL(kvm_mips_flush_host_tlb);
 EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup);
 EXPORT_SYMBOL(kvm_mips_host_tlb_inv);
 EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa);
-EXPORT_SYMBOL(kvm_shadow_tlb_load);
-EXPORT_SYMBOL(kvm_mips_dump_shadow_tlbs);
 EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs);
 EXPORT_SYMBOL(kvm_get_inst);
 EXPORT_SYMBOL(kvm_arch_vcpu_load);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index 1ab576dc9bd1..8750dc0a1bf6 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -8,7 +8,6 @@
 
 #include <linux/io.h>
 #include <linux/export.h>
-#include <linux/init.h>
 #include <linux/clk.h>
 
 #include <asm/time.h>
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 08f7ebd9c774..78a91fa41944 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -220,10 +220,6 @@ ltq_dma_init(struct platform_device *pdev)
         int i;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                panic("Failed to get dma resource");
-
-        /* remap dma register range */
         ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(ltq_dma_membase))
                 panic("Failed to remap dma resource");
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
index 793e234719a6..942f32b91d12 100644
--- a/arch/mips/lasat/at93c.c
+++ b/arch/mips/lasat/at93c.c
@@ -8,7 +8,6 @@
 #include <linux/delay.h>
 #include <asm/lasat/lasat.h>
 #include <linux/module.h>
-#include <linux/init.h>
 
 #include "at93c.h"
 
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index 7eb334892693..d613b97cd513 100644
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -9,7 +9,6 @@
 #include <asm/bootinfo.h>
 #include <asm/lasat/lasat.h>
 #include <linux/module.h>
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index d8522f8e842a..09d5deea747f 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -8,7 +8,6 @@
  *      Author: Maciej W. Rozycki <macro@mips.com>
  */
 
-#include <linux/init.h>
 
 #include <asm/addrspace.h>
 #include <asm/bug.h>
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index 4dc2f5fa3f67..aed32b88576c 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -10,7 +10,6 @@
 #include <linux/cpufreq.h>
 #include <linux/errno.h>
 #include <linux/export.h>
-#include <linux/init.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index efe008846ed0..506925b2c3f3 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -417,14 +417,20 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
                         case mm_mtc1_op:
                         case mm_cfc1_op:
                         case mm_ctc1_op:
+                        case mm_mfhc1_op:
+                        case mm_mthc1_op:
                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
                                         op = mfc_op;
                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
                                         op = mtc_op;
                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
                                         op = cfc_op;
-                                else
+                                else if (insn.mm_fp1_format.op == mm_ctc1_op)
                                         op = ctc_op;
+                                else if (insn.mm_fp1_format.op == mm_mfhc1_op)
+                                        op = mfhc_op;
+                                else
+                                        op = mthc_op;
                                 mips32_insn.fp1_format.opcode = cop1_op;
                                 mips32_insn.fp1_format.op = op;
                                 mips32_insn.fp1_format.rt =
@@ -853,20 +859,20 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
- * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
+ * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
  * FPU emu is slow and bulky and optimizing this function offers fairly
  * sizeable benefits so we try to be clever and make this function return
  * a constant whenever possible, that is on 64-bit kernels without O32
- * compatibility enabled and on 32-bit kernels.
+ * compatibility enabled and on 32-bit without 64-bit FPU support.
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
         return 1;
-#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
-        return !test_thread_flag(TIF_32BIT_REGS);
-#else
+#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
         return 0;
+#else
+        return !test_thread_flag(TIF_32BIT_FPREGS);
 #endif
 }
 
@@ -878,6 +884,10 @@ static inline int cop1_64bit(struct pt_regs *xcp)
                         ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
                         ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
 
+#define SIFROMHREG(si, x)       ((si) = (int)(ctx->fpr[x] >> 32))
+#define SITOHREG(si, x)         (ctx->fpr[x] = \
+                                ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
+
 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
 #define DITOREG(di, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
 
@@ -1055,6 +1065,25 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         break;
 #endif
 
+                case mfhc_op:
+                        if (!cpu_has_mips_r2)
+                                goto sigill;
+
+                        /* copregister rd -> gpr[rt] */
+                        if (MIPSInst_RT(ir) != 0) {
+                                SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
+                                        MIPSInst_RD(ir));
+                        }
+                        break;
+
+                case mthc_op:
+                        if (!cpu_has_mips_r2)
+                                goto sigill;
+
+                        /* copregister rd <- gpr[rt] */
+                        SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
+                        break;
+
                 case mfc_op:
                         /* copregister rd -> gpr[rt] */
                         if (MIPSInst_RT(ir) != 0) {
@@ -1263,6 +1292,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 #endif
 
         default:
+sigill:
                 return SIGILL;
         }
 
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 1c586575fe17..3aeae07ed5b8 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -89,8 +89,9 @@ int fpu_emulator_save_context32(struct sigcontext32 __user *sc)
 {
         int i;
         int err = 0;
+        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
 
-        for (i = 0; i < 32; i+=2) {
+        for (i = 0; i < 32; i += inc) {
                 err |=
                     __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
         }
@@ -103,8 +104,9 @@ int fpu_emulator_restore_context32(struct sigcontext32 __user *sc)
 {
         int i;
         int err = 0;
+        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
 
-        for (i = 0; i < 32; i+=2) {
+        for (i = 0; i < 32; i += inc) {
                 err |=
                     __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
         }
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index c8efdb5b6ee0..f41a5c5b0865 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2005-2007 Cavium Networks
  */
 #include <linux/export.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 2fcde0c8ea02..135ec313c1f6 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -9,7 +9,6 @@
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
  * Copyright (C) 2001, 2004, 2007  Maciej W. Rozycki
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 49e572d879e1..c14259edd53f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1020,10 +1020,14 @@ static void probe_pcache(void)
                  */
                 config1 = read_c0_config1();
 
-                if ((lsize = ((config1 >> 19) & 7)))
-                        c->icache.linesz = 2 << lsize;
-                else
-                        c->icache.linesz = lsize;
+                lsize = (config1 >> 19) & 7;
+
+                /* IL == 7 is reserved */
+                if (lsize == 7)
+                        panic("Invalid icache line size");
+
+                c->icache.linesz = lsize ? 2 << lsize : 0;
+
                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 
@@ -1040,10 +1044,14 @@ static void probe_pcache(void)
                  */
                 c->dcache.flags = 0;
 
-                if ((lsize = ((config1 >> 10) & 7)))
-                        c->dcache.linesz = 2 << lsize;
-                else
-                        c->dcache.linesz= lsize;
+                lsize = (config1 >> 10) & 7;
+
+                /* DL == 7 is reserved */
+                if (lsize == 7)
+                        panic("Invalid dcache line size");
+
+                c->dcache.linesz = lsize ? 2 << lsize : 0;
+
                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
@@ -1105,6 +1113,8 @@ static void probe_pcache(void)
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
                 if (current_cpu_type() == CPU_74K)
                         alias_74k_erratum(c);
                 if ((read_c0_config7() & (1 << 16))) {
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 15f813c303b4..fde7e56d13fe 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -8,7 +8,6 @@
  */
 #include <linux/fs.h>
 #include <linux/fcntl.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/linkage.h>
 #include <linux/module.h>
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 191cf6e0c725..5d5f29681a21 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -15,7 +15,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
-#include <linux/init.h>
 
 #include <asm/asm.h>
 #include <asm/regdef.h>
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 2e9418562258..44b6dff5aba2 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -23,6 +23,7 @@
 
 #include <dma-coherence.h>
 
+#ifdef CONFIG_DMA_MAYBE_COHERENT
 int coherentio = 0;     /* User defined DMA coherency from command line. */
 EXPORT_SYMBOL_GPL(coherentio);
 int hw_coherentio = 0;  /* Actual hardware supported DMA coherency setting. */
@@ -42,6 +43,7 @@ static int __init setnocoherentio(char *str)
         return 0;
 }
 early_param("nocoherentio", setnocoherentio);
+#endif
 
 static inline struct page *dma_addr_to_page(struct device *dev,
         dma_addr_t dma_addr)
diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c
index 01fda4419ed0..77e0ae036e7c 100644
--- a/arch/mips/mm/hugetlbpage.c
+++ b/arch/mips/mm/hugetlbpage.c
@@ -11,7 +11,6 @@
  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
  */
 
-#include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 12156176c7ca..6b59617760c1 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -171,8 +171,6 @@ void *kmap_coherent(struct page *page, unsigned long addr)
         return (void*) vaddr;
 }
 
-#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-
 void kunmap_coherent(void)
 {
 #ifndef CONFIG_MIPS_MT_SMTC
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cbd81d17793a..58033c44690d 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -8,7 +8,6 @@
  * Copyright (C) 2008  Thiemo Seufer
  * Copyright (C) 2012  MIPS Technologies, Inc.
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 08d05aee8788..7a56aee5fce7 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -76,6 +76,8 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
         case CPU_BMIPS5000:
                 if (config2 & (1 << 12))
                         return 0;
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index aaffbba33706..9ac1efcfbcc7 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -6,7 +6,6 @@
 
 #undef DEBUG
 
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/bitops.h>
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 9aca10994cd2..d657493ef561 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2002  Ralf Baechle
  * Copyright (C) 2002  Maciej W. Rozycki
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index da3b0b9c9eae..ae4ca2450707 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -20,16 +20,11 @@
 #include <asm/bootinfo.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
+#include <asm/tlb.h>
 #include <asm/tlbmisc.h>
 
 extern void build_tlb_refill_handler(void);
 
-/*
- * Make sure all entries differ.  If they're not different
- * MIPS32 will take revenge ...
- */
-#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-
 /* Atomicity and interruptability */
 #ifdef CONFIG_MIPS_MT_SMTC
 
@@ -77,7 +72,7 @@ void local_flush_tlb_all(void)
 {
         unsigned long flags;
         unsigned long old_ctx;
-        int entry;
+        int entry, ftlbhighset;
 
         ENTER_CRITICAL(flags);
         /* Save old context and create impossible VPN2 value */
@@ -88,13 +83,30 @@ void local_flush_tlb_all(void)
         entry = read_c0_wired();
 
         /* Blast 'em all away. */
-        while (entry < current_cpu_data.tlbsize) {
-                /* Make sure all entries differ. */
-                write_c0_entryhi(UNIQUE_ENTRYHI(entry));
-                write_c0_index(entry);
-                mtc0_tlbw_hazard();
-                tlb_write_indexed();
-                entry++;
+        if (cpu_has_tlbinv) {
+                if (current_cpu_data.tlbsizevtlb) {
+                        write_c0_index(0);
+                        mtc0_tlbw_hazard();
+                        tlbinvf();  /* invalidate VTLB */
+                }
+                ftlbhighset = current_cpu_data.tlbsizevtlb +
+                        current_cpu_data.tlbsizeftlbsets;
+                for (entry = current_cpu_data.tlbsizevtlb;
+                     entry < ftlbhighset;
+                     entry++) {
+                        write_c0_index(entry);
+                        mtc0_tlbw_hazard();
+                        tlbinvf();  /* invalidate one FTLB set */
+                }
+        } else {
+                while (entry < current_cpu_data.tlbsize) {
+                        /* Make sure all entries differ. */
+                        write_c0_entryhi(UNIQUE_ENTRYHI(entry));
+                        write_c0_index(entry);
+                        mtc0_tlbw_hazard();
+                        tlb_write_indexed();
+                        entry++;
+                }
         }
         tlbw_use_hazard();
         write_c0_entryhi(old_ctx);
@@ -133,7 +145,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                 start = round_down(start, PAGE_SIZE << 1);
                 end = round_up(end, PAGE_SIZE << 1);
                 size = (end - start) >> (PAGE_SHIFT + 1);
-                if (size <= current_cpu_data.tlbsize/2) {
+                if (size <= (current_cpu_data.tlbsizeftlbsets ?
+                             current_cpu_data.tlbsize / 8 :
+                             current_cpu_data.tlbsize / 2)) {
                         int oldpid = read_c0_entryhi();
                         int newpid = cpu_asid(cpu, mm);
 
@@ -172,7 +186,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
         ENTER_CRITICAL(flags);
         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
         size = (size + 1) >> 1;
-        if (size <= current_cpu_data.tlbsize / 2) {
+        if (size <= (current_cpu_data.tlbsizeftlbsets ?
+                     current_cpu_data.tlbsize / 8 :
+                     current_cpu_data.tlbsize / 2)) {
                 int pid = read_c0_entryhi();
 
                 start &= (PAGE_MASK << 1);
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 6a99733a4440..138a2ec7cc6b 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -8,7 +8,6 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
  */
-#include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 183f2b583e4d..b234b1b5ccad 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <linux/smp.h>
 #include <linux/string.h>
-#include <linux/init.h>
 #include <linux/cache.h>
 
 #include <asm/cacheflush.h>
@@ -510,6 +509,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 switch (current_cpu_type()) {
                 case CPU_M14KC:
                 case CPU_74K:
+                case CPU_PROAPTIV:
                         break;
 
                 default:
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 060000fa653c..b8d580ca02e5 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -15,7 +15,6 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/init.h>
 
 #include <asm/inst.h>
 #include <asm/elf.h>
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 0c724589854e..3abd609518c9 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -15,7 +15,6 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/init.h>
 
 #include <asm/inst.h>
 #include <asm/elf.h>
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 72fdedbf76db..eae0ba3876d9 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -9,7 +9,5 @@ obj-y				:= malta-amon.o malta-display.o malta-init.o \
                                    malta-int.o malta-memory.o malta-platform.o \
                                    malta-reset.o malta-setup.o malta-time.o
 
-obj-$(CONFIG_EARLY_PRINTK)      += malta-console.o
-
 # FIXME FIXME FIXME
 obj-$(CONFIG_MIPS_MT_SMTC)      += malta-smtc.o
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 1e4784458016..592ac0427426 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -1,30 +1,20 @@
 /*
- * Copyright (C) 2007  MIPS Technologies, Inc.
- *      All rights reserved.
-
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * Copyright (C) 2007 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  *
- * Arbitrary Monitor interface
+ * Arbitrary Monitor Interface
  */
-
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 
 #include <asm/addrspace.h>
-#include <asm/mips-boards/launch.h>
 #include <asm/mipsmtregs.h>
+#include <asm/mips-boards/launch.h>
+#include <asm/vpe.h>
 
 int amon_cpu_avail(int cpu)
 {
@@ -48,7 +38,7 @@ int amon_cpu_avail(int cpu)
         return 1;
 }
 
-void amon_cpu_start(int cpu,
+int amon_cpu_start(int cpu,
                     unsigned long pc, unsigned long sp,
                     unsigned long gp, unsigned long a0)
 {
@@ -56,10 +46,10 @@ void amon_cpu_start(int cpu,
                 (struct cpulaunch  *)CKSEG0ADDR(CPULAUNCH);
 
         if (!amon_cpu_avail(cpu))
-                return;
+                return -1;
         if (cpu == smp_processor_id()) {
                 pr_debug("launch: I am cpu%d!\n", cpu);
-                return;
+                return -1;
         }
         launch += cpu;
 
@@ -78,4 +68,21 @@ void amon_cpu_start(int cpu,
                 ;
         smp_rmb();      /* Target will be updating flags soon */
         pr_debug("launch: cpu%d gone!\n", cpu);
+
+        return 0;
+}
+
+#ifdef CONFIG_MIPS_VPE_LOADER
+int vpe_run(struct vpe *v)
+{
+        struct vpe_notifications *n;
+
+        if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0)
+                return -1;
+
+        list_for_each_entry(n, &v->notify, list)
+                n->start(VPE_MODULE_MINOR);
+
+        return 0;
 }
+#endif
diff --git a/arch/mips/mti-malta/malta-console.c b/arch/mips/mti-malta/malta-console.c
deleted file mode 100644
index 43bcfb4f8167..000000000000
--- a/arch/mips/mti-malta/malta-console.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Putting things on the screen/serial line using YAMONs facilities.
- */
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/serial_reg.h>
-#include <asm/io.h>
-
-
-#define PORT(offset) (0x3f8 + (offset))
-
-
-static inline unsigned int serial_in(int offset)
-{
-        return inb(PORT(offset));
-}
-
-static inline void serial_out(int offset, int value)
-{
-        outb(value, PORT(offset));
-}
-
-int prom_putchar(char c)
-{
-        while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
-                ;
-
-        serial_out(UART_TX, c);
-
-        return 1;
-}
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index ff8caffd3266..fcebfced26d0 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
+#include <linux/serial_8250.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp-ops.h>
@@ -44,32 +45,39 @@ static void __init console_config(void)
         char parity = '\0', bits = '\0', flow = '\0';
         char *s;
 
-        if ((strstr(fw_getcmdline(), "console=")) == NULL) {
-                s = fw_getenv("modetty0");
-                if (s) {
-                        while (*s >= '0' && *s <= '9')
-                                baud = baud*10 + *s++ - '0';
-                        if (*s == ',')
-                                s++;
-                        if (*s)
-                                parity = *s++;
-                        if (*s == ',')
-                                s++;
-                        if (*s)
-                                bits = *s++;
-                        if (*s == ',')
-                                s++;
-                        if (*s == 'h')
-                                flow = 'r';
-                }
-                if (baud == 0)
-                        baud = 38400;
-                if (parity != 'n' && parity != 'o' && parity != 'e')
-                        parity = 'n';
-                if (bits != '7' && bits != '8')
-                        bits = '8';
-                if (flow == '\0')
+        s = fw_getenv("modetty0");
+        if (s) {
+                while (*s >= '0' && *s <= '9')
+                        baud = baud*10 + *s++ - '0';
+                if (*s == ',')
+                        s++;
+                if (*s)
+                        parity = *s++;
+                if (*s == ',')
+                        s++;
+                if (*s)
+                        bits = *s++;
+                if (*s == ',')
+                        s++;
+                if (*s == 'h')
                         flow = 'r';
+        }
+        if (baud == 0)
+                baud = 38400;
+        if (parity != 'n' && parity != 'o' && parity != 'e')
+                parity = 'n';
+        if (bits != '7' && bits != '8')
+                bits = '8';
+        if (flow == '\0')
+                flow = 'r';
+
+        if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) {
+                sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud,
+                        parity, bits);
+                setup_early_serial8250_console(console_string);
+        }
+
+        if ((strstr(fw_getcmdline(), "console=")) == NULL) {
                 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
                         parity, bits, flow);
                 strcat(fw_getcmdline(), console_string);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 0892575f829d..ca3e3a46a42f 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -1,25 +1,16 @@
 /*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  * Copyright (C) 2001 Ralf Baechle
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  *
  * Routines for generic manipulation of the interrupts found on the MIPS
- * Malta board.
- * The interrupt controller is located in the South Bridge a PIIX4 device
- * with two internal 82C95 interrupt controllers.
+ * Malta board. The interrupt controller is located in the South Bridge
+ * a PIIX4 device with two internal 82C95 interrupt controllers.
  */
 #include <linux/init.h>
 #include <linux/irq.h>
@@ -44,6 +35,7 @@
 #include <asm/gic.h>
 #include <asm/gcmpregs.h>
 #include <asm/setup.h>
+#include <asm/rtlx.h>
 
 int gcmp_present = -1;
 static unsigned long _msc01_biu_base;
@@ -90,7 +82,7 @@ static inline int mips_pcibios_iack(void)
                 BONITO_PCIMAP_CFG = 0;
                 break;
         default:
-                printk(KERN_WARNING "Unknown system controller.\n");
+                pr_emerg("Unknown system controller.\n");
                 return -1;
         }
         return irq;
@@ -126,6 +118,11 @@ static void malta_hw0_irqdispatch(void)
         }
 
         do_IRQ(MALTA_INT_BASE + irq);
+
+#ifdef MIPS_VPE_APSP_API
+        if (aprp_hook)
+                aprp_hook();
+#endif
 }
 
 static void malta_ipi_irqdispatch(void)
@@ -149,11 +146,11 @@ static void corehi_irqdispatch(void)
         unsigned int intrcause, datalo, datahi;
         struct pt_regs *regs = get_irq_regs();
 
-        printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
-        printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
-                        "Cause : %08lx\nbadVaddr : %08lx\n",
-                        regs->cp0_epc, regs->cp0_status,
-                        regs->cp0_cause, regs->cp0_badvaddr);
+        pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
+        pr_emerg("epc    : %08lx\nStatus: %08lx\n"
+                 "Cause : %08lx\nbadVaddr : %08lx\n",
+                 regs->cp0_epc, regs->cp0_status,
+                 regs->cp0_cause, regs->cp0_badvaddr);
 
         /* Read all the registers and then print them as there is a
            problem with interspersed printk's upsetting the Bonito controller.
@@ -171,8 +168,8 @@ static void corehi_irqdispatch(void)
                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
-                printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
-                printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
+                pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
+                pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
                                 datahi, datalo);
                 break;
         case MIPS_REVISION_SCON_BONITO:
@@ -184,14 +181,14 @@ static void corehi_irqdispatch(void)
                 intedge = BONITO_INTEDGE;
                 intsteer = BONITO_INTSTEER;
                 pcicmd = BONITO_PCICMD;
-                printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
-                printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
-                printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
-                printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
-                printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
-                printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
-                printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
-                printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
+                pr_emerg("BONITO_INTISR = %08x\n", intisr);
+                pr_emerg("BONITO_INTEN = %08x\n", inten);
+                pr_emerg("BONITO_INTPOL = %08x\n", intpol);
+                pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
+                pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
+                pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
+                pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
+                pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
                 break;
         }
 
@@ -313,6 +310,11 @@ static void ipi_call_dispatch(void)
 
 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 {
+#ifdef MIPS_VPE_APSP_API
+        if (aprp_hook)
+                aprp_hook();
+#endif
+
         scheduler_ipi();
 
         return IRQ_HANDLED;
@@ -365,13 +367,13 @@ static struct irqaction corehi_irqaction = {
         .flags = IRQF_NO_THREAD,
 };
 
-static msc_irqmap_t __initdata msc_irqmap[] = {
+static msc_irqmap_t msc_irqmap[] __initdata = {
         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 };
-static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
+static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
 
-static msc_irqmap_t __initdata msc_eicirqmap[] = {
+static msc_irqmap_t msc_eicirqmap[] __initdata = {
         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
@@ -384,7 +386,7 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 };
 
-static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
+static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
 
 /*
  * This GIC specific tabular array defines the association between External
@@ -431,9 +433,12 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
         if (gcmp_present >= 0)
                 return gcmp_present;
 
-        _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
-        _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
-        gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
+        _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR,
+                GCMP_ADDRSPACE_SZ);
+        _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE,
+                MSC01_BIU_ADDRSPACE_SZ);
+        gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) ==
+                GCMP_BASE_ADDR);
 
         if (gcmp_present)
                 pr_debug("GCMP present\n");
@@ -443,9 +448,8 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
 /* Return the number of IOCU's present */
 int __init gcmp_niocu(void)
 {
-  return gcmp_present ?
-    (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
-    0;
+        return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >>
+                GCMP_GCB_GC_NUMIOCU_SHF) : 0;
 }
 
 /* Set GCMP region attributes */
@@ -594,11 +598,14 @@ void __init arch_init_irq(void)
                         set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
                 }
                 /* Argh.. this really needs sorting out.. */
-                printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
+                pr_info("CPU%d: status register was %08x\n",
+                        smp_processor_id(), read_c0_status());
                 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
-                printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
+                pr_info("CPU%d: status register now %08x\n",
+                        smp_processor_id(), read_c0_status());
                 write_c0_status(0x1100dc00);
-                printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
+                pr_info("CPU%d: status register frc %08x\n",
+                        smp_processor_id(), read_c0_status());
                 for (i = 0; i < nr_cpu_ids; i++) {
                         arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
                                          GIC_RESCHED_INT(i), &irq_resched);
@@ -616,11 +623,15 @@ void __init arch_init_irq(void)
                         cpu_ipi_call_irq = MSC01E_INT_SW1;
                 } else {
                         if (cpu_has_vint) {
-                                set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
-                                set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
+                                set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ,
+                                        ipi_resched_dispatch);
+                                set_vi_handler (MIPS_CPU_IPI_CALL_IRQ,
+                                        ipi_call_dispatch);
                         }
-                        cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
-                        cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
+                        cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
+                                MIPS_CPU_IPI_RESCHED_IRQ;
+                        cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
+                                MIPS_CPU_IPI_CALL_IRQ;
                 }
                 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
                 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
@@ -630,9 +641,7 @@ void __init arch_init_irq(void)
 
 void malta_be_init(void)
 {
-        if (gcmp_present) {
-                /* Could change CM error mask register */
-        }
+        /* Could change CM error mask register. */
 }
 
 
@@ -712,14 +721,14 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
                         if (cause < 16) {
                                 unsigned long cca_bits = (cm_error >> 15) & 7;
                                 unsigned long tr_bits = (cm_error >> 12) & 7;
-                                unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
+                                unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
                                 unsigned long stag_bits = (cm_error >> 3) & 15;
                                 unsigned long sport_bits = (cm_error >> 0) & 7;
 
                                 snprintf(buf, sizeof(buf),
                                          "CCA=%lu TR=%s MCmd=%s STag=%lu "
                                          "SPort=%lu\n",
-                                         cca_bits, tr[tr_bits], mcmd[mcmd_bits],
+                                         cca_bits, tr[tr_bits], mcmd[cmd_bits],
                                          stag_bits, sport_bits);
                         } else {
                                 /* glob state & sresp together */
@@ -728,7 +737,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
                                 unsigned long c1_bits = (cm_error >> 12) & 7;
                                 unsigned long c0_bits = (cm_error >> 9) & 7;
                                 unsigned long sc_bit = (cm_error >> 8) & 1;
-                                unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
+                                unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
                                 unsigned long sport_bits = (cm_error >> 0) & 7;
                                 snprintf(buf, sizeof(buf),
                                          "C3=%s C2=%s C1=%s C0=%s SC=%s "
@@ -736,16 +745,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
                                          core[c3_bits], core[c2_bits],
                                          core[c1_bits], core[c0_bits],
                                          sc_bit ? "True" : "False",
-                                         mcmd[mcmd_bits], sport_bits);
+                                         mcmd[cmd_bits], sport_bits);
                         }
 
                         ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
                                  GCMP_GCB_GMEO_ERROR_2ND_SHF;
 
-                        printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
+                        pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
                                causes[cause], buf);
-                        printk("CM_ADDR =%08lx\n", cm_addr);
-                        printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
+                        pr_err("CM_ADDR =%08lx\n", cm_addr);
+                        pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
 
                         /* reprime cause register */
                         GCMPGCB(GCMEC) = 0;
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 132f8663825e..e1dd1c1d3fde 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -47,6 +47,7 @@
 static struct plat_serial8250_port uart8250_data[] = {
         SMC_PORT(0x3F8, 4),
         SMC_PORT(0x2F8, 3),
+#ifndef CONFIG_MIPS_CMP
         {
                 .mapbase        = 0x1f000900,   /* The CBUS UART */
                 .irq            = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
@@ -55,6 +56,7 @@ static struct plat_serial8250_port uart8250_data[] = {
                 .flags          = CBUS_UART_FLAGS,
                 .regshift       = 3,
         },
+#endif
         { },
 };
 
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index a18af5fce67e..319009912142 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -42,8 +42,6 @@
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/maltaint.h>
 
-unsigned long cpu_khz;
-
 static int mips_cpu_timer_irq;
 static int mips_cpu_perf_irq;
 extern int cp0_perfcount_irq;
@@ -168,11 +166,24 @@ unsigned int get_c0_compare_int(void)
         return mips_cpu_timer_irq;
 }
 
+static void __init init_rtc(void)
+{
+        /* stop the clock whilst setting it up */
+        CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
+
+        /* 32KHz time base */
+        CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
+
+        /* start the clock */
+        CMOS_WRITE(RTC_24H, RTC_CONTROL);
+}
+
 void __init plat_time_init(void)
 {
         unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
         unsigned int freq;
 
+        init_rtc();
         estimate_frequencies();
 
         freq = mips_hpt_frequency;
@@ -182,7 +193,6 @@ void __init plat_time_init(void)
         freq = freqround(freq, 5000);
         printk("CPU frequency %d.%02d MHz\n", freq/1000000,
                (freq%1000000)*100/1000000);
-        cpu_khz = freq / 1000;
 
         mips_scroll_message();
 
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index be114209217c..071786fa234b 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -21,5 +21,7 @@ obj-$(CONFIG_EARLY_PRINTK)	+= sead3-console.o
 obj-$(CONFIG_USB_EHCI_HCD)      += sead3-ehci.o
 obj-$(CONFIG_OF)                += sead3.dtb.o
 
+CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt
+
 $(obj)/%.dtb: $(obj)/%.dts
         $(call if_changed,dtc)
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
index eb2bf936d102..3b12aa5a7c88 100644
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ b/arch/mips/mti-sead3/sead3-pic32-bus.c
@@ -8,7 +8,6 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
-#include <linux/init.h>
 #include <linux/io.h>
 #include <linux/errno.h>
 
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
index 928ba84c8a78..bf7fe48bf2f9 100644
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ b/arch/mips/mti-sead3/sead3-setup.c
@@ -4,13 +4,15 @@
  * for more details.
  *
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Imagination Technologies Ltd.
  */
 #include <linux/init.h>
+#include <linux/libfdt.h>
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/bootmem.h>
 
 #include <asm/prom.h>
+#include <asm/fw/fw.h>
 
 #include <asm/mips-boards/generic.h>
 
@@ -19,8 +21,73 @@ const char *get_system_type(void)
         return "MIPS SEAD3";
 }
 
+static uint32_t get_memsize_from_cmdline(void)
+{
+        int memsize = 0;
+        char *p = arcs_cmdline;
+        char *s = "memsize=";
+
+        p = strstr(p, s);
+        if (p) {
+                p += strlen(s);
+                memsize = memparse(p, NULL);
+        }
+
+        return memsize;
+}
+
+static uint32_t get_memsize_from_env(void)
+{
+        int memsize = 0;
+        char *p;
+
+        p = fw_getenv("memsize");
+        if (p)
+                memsize = memparse(p, NULL);
+
+        return memsize;
+}
+
+static uint32_t get_memsize(void)
+{
+        uint32_t memsize;
+
+        memsize = get_memsize_from_cmdline();
+        if (memsize)
+                return memsize;
+
+        return get_memsize_from_env();
+}
+
+static void __init parse_memsize_param(void)
+{
+        int offset;
+        const uint64_t *prop_value;
+        int prop_len;
+        uint32_t memsize = get_memsize();
+
+        if (!memsize)
+                return;
+
+        offset = fdt_path_offset(&__dtb_start, "/memory");
+        if (offset > 0) {
+                uint64_t new_value;
+                /*
+                 * reg contains 2 32-bits BE values, offset and size. We just
+                 * want to replace the size value without affecting the offset
+                 */
+                prop_value = fdt_getprop(&__dtb_start, offset, "reg", &prop_len);
+                new_value = be64_to_cpu(*prop_value);
+                new_value =  (new_value & ~0xffffffffllu) | memsize;
+                fdt_setprop_inplace_u64(&__dtb_start, offset, "reg", new_value);
+        }
+}
+
 void __init plat_mem_setup(void)
 {
+        /* allow command line/bootloader env to override memory size in DT */
+        parse_memsize_param();
+
         /*
          * Load the builtin devicetree. This causes the chosen node to be
          * parsed resulting in our memory appearing
@@ -30,16 +97,15 @@ void __init plat_mem_setup(void)
 
 void __init device_tree_init(void)
 {
-        unsigned long base, size;
-
         if (!initial_boot_params)
                 return;
 
-        base = virt_to_phys((void *)initial_boot_params);
-        size = be32_to_cpu(initial_boot_params->totalsize);
-
-        /* Before we do anything, lets reserve the dt blob */
-        reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+        unflatten_and_copy_device_tree();
+}
 
-        unflatten_device_tree();
+static int __init customize_machine(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        return 0;
 }
+arch_initcall(customize_machine);
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index 552d26c34386..678d03d53c60 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -13,8 +13,6 @@
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 
-unsigned long cpu_khz;
-
 static int mips_cpu_timer_irq;
 static int mips_cpu_perf_irq;
 
@@ -109,8 +107,6 @@ void __init plat_time_init(void)
         pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
                 (est_freq % 1000000) * 100 / 1000000);
 
-        cpu_khz = est_freq / 1000;
-
         mips_scroll_message();
 
         plat_perf_setup();
diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts
index 658f43787056..e4b317d414f1 100644
--- a/arch/mips/mti-sead3/sead3.dts
+++ b/arch/mips/mti-sead3/sead3.dts
@@ -15,10 +15,6 @@
                 };
         };
 
-        chosen {
-                bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x0 0x08000000>;
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 852a4ee09954..4eb683aef7d7 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -28,6 +28,15 @@ config DT_XLP_FVP
           pointer to the kernel.  The corresponding DTS file is at
           arch/mips/netlogic/dts/xlp_fvp.dts
 
+config DT_XLP_GVP
+        bool "Built-in device tree for XLP GVP boards"
+        default y
+        help
+          Add an FDT blob for XLP GVP board into the kernel.
+          This DTB will be used if the firmware does not pass in a DTB
+          pointer to the kernel.  The corresponding DTS file is at
+          arch/mips/netlogic/dts/xlp_gvp.dts
+
 config NLM_MULTINODE
         bool "Support for multi-chip boards"
         depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index 1902fa22d277..769f93032c53 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -37,9 +37,11 @@
 
 #include <asm/mipsregs.h>
 #include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
 
 #if defined(CONFIG_CPU_XLP)
 #include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
 #include <asm/netlogic/xlp-hal/uart.h>
 #elif defined(CONFIG_CPU_XLR)
 #include <asm/netlogic/xlr/iomap.h>
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 1c7e3a1b81ab..5afc4b7fce0f 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -180,6 +180,7 @@ static void __init nlm_init_percpu_irqs(void)
 #endif
 }
 
+
 void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
 {
         struct nlm_pic_irq *pic_data;
@@ -207,32 +208,32 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
 
 static void nlm_init_node_irqs(int node)
 {
-        int i, irt;
-        uint64_t irqmask;
         struct nlm_soc_info *nodep;
+        int i, irt;
 
         pr_info("Init IRQ for node %d\n", node);
         nodep = nlm_get_node(node);
-        irqmask = PERCPU_IRQ_MASK;
+        nodep->irqmask = PERCPU_IRQ_MASK;
         for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
                 irt = nlm_irq_to_irt(i);
-                if (irt == -1)
+                if (irt == -1)          /* unused irq */
                         continue;
-                nlm_setup_pic_irq(node, i, i, irt);
-                /* set interrupts to first cpu in node */
+                nodep->irqmask |= 1ull << i;
+                if (irt == -2)          /* not a direct PIC irq */
+                        continue;
+
                 nlm_pic_init_irt(nodep->picbase, irt, i,
-                                        node * NLM_CPUS_PER_NODE, 0);
-                irqmask |= (1ull << i);
+                                node * nlm_threads_per_node(), 0);
+                nlm_setup_pic_irq(node, i, i, irt);
         }
-        nodep->irqmask = irqmask;
 }
 
 void nlm_smp_irq_init(int hwcpuid)
 {
         int node, cpu;
 
-        node = hwcpuid / NLM_CPUS_PER_NODE;
-        cpu  = hwcpuid % NLM_CPUS_PER_NODE;
+        node = nlm_cpuid_to_node(hwcpuid);
+        cpu  = hwcpuid % nlm_threads_per_node();
 
         if (cpu == 0 && node != 0)
                 nlm_init_node_irqs(node);
@@ -256,13 +257,23 @@ asmlinkage void plat_irq_dispatch(void)
                 return;
         }
 
+#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP)
+        /* PCI interrupts need a second level dispatch for MSI bits */
+        if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) {
+                nlm_dispatch_msi(node, i);
+                return;
+        }
+        if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) {
+                nlm_dispatch_msix(node, i);
+                return;
+        }
+
+#endif
         /* top level irq handling */
         do_IRQ(nlm_irq_to_xirq(node, i));
 }
 
 #ifdef CONFIG_OF
-static struct irq_domain *xlp_pic_domain;
-
 static const struct irq_domain_ops xlp_pic_irq_domain_ops = {
         .xlate = irq_domain_xlate_onetwocell,
 };
@@ -271,8 +282,9 @@ static int __init xlp_of_pic_init(struct device_node *node,
                                         struct device_node *parent)
 {
         const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1;
+        struct irq_domain *xlp_pic_domain;
         struct resource res;
-        int socid, ret;
+        int socid, ret, bus;
 
         /* we need a hack to get the PIC's SoC chip id */
         ret = of_address_to_resource(node, 0, &res);
@@ -280,7 +292,34 @@ static int __init xlp_of_pic_init(struct device_node *node,
                 pr_err("PIC %s: reg property not found!\n", node->name);
                 return -EINVAL;
         }
-        socid = (res.start >> 18) & 0x3;
+
+        if (cpu_is_xlp9xx()) {
+                bus = (res.start >> 20) & 0xf;
+                for (socid = 0; socid < NLM_NR_NODES; socid++) {
+                        if (!nlm_node_present(socid))
+                                continue;
+                        if (nlm_get_node(socid)->socbus == bus)
+                                break;
+                }
+                if (socid == NLM_NR_NODES) {
+                        pr_err("PIC %s: Node mapping for bus %d not found!\n",
+                                        node->name, bus);
+                        return -EINVAL;
+                }
+        } else {
+                socid = (res.start >> 18) & 0x3;
+                if (!nlm_node_present(socid)) {
+                        pr_err("PIC %s: node %d does not exist!\n",
+                                                        node->name, socid);
+                        return -EINVAL;
+                }
+        }
+
+        if (!nlm_node_present(socid)) {
+                pr_err("PIC %s: node %d does not exist!\n", node->name, socid);
+                return -EINVAL;
+        }
+
         xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs,
                 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE,
                 &xlp_pic_irq_domain_ops, NULL);
@@ -288,8 +327,7 @@ static int __init xlp_of_pic_init(struct device_node *node,
                 pr_err("PIC %s: Creating legacy domain failed!\n", node->name);
                 return -EINVAL;
         }
-        pr_info("Node %d: IRQ domain created for PIC@%pa\n", socid,
-                                                        &res.start);
+        pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res);
         return 0;
 }
 
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index adb18288a6c0..b231fe1e7a09 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -32,10 +32,10 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/init.h>
 
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/cacheops.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
@@ -50,8 +50,8 @@
 #include <asm/netlogic/xlp-hal/cpucontrol.h>
 
 #define CP0_EBASE       $15
-#define SYS_CPU_COHERENT_BASE(node)     CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
-                        XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
+#define SYS_CPU_COHERENT_BASE   CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
+                        XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
                         SYS_CPU_NONCOHERENT_MODE * 4
 
 /* Enable XLP features and workarounds in the LSU */
@@ -74,35 +74,55 @@
 .endm
 
 /*
- * Low level flush for L1D cache on XLP, the normal cache ops does
- * not do the complete and correct cache flush.
+ * L1D cache has to be flushed before enabling threads in XLP.
+ * On XLP8xx/XLP3xx, we do a low level flush using processor control
+ * registers. On XLPII CPUs, usual cache instructions work.
  */
 .macro  xlp_flush_l1_dcache
+        mfc0    t0, CP0_EBASE, 0
+        andi    t0, t0, 0xff00
+        slt     t1, t0, 0x1200
+        beqz    t1, 15f
+        nop
+
+        /* XLP8xx low level cache flush */
         li      t0, LSU_DEBUG_DATA0
         li      t1, LSU_DEBUG_ADDR
         li      t2, 0           /* index */
         li      t3, 0x1000      /* loop count */
-1:
+11:
         sll     v0, t2, 5
         mtcr    zero, t0
         ori     v1, v0, 0x3     /* way0 | write_enable | write_active */
         mtcr    v1, t1
-2:
+12:
         mfcr    v1, t1
         andi    v1, 0x1         /* wait for write_active == 0 */
-        bnez    v1, 2b
+        bnez    v1, 12b
         nop
         mtcr    zero, t0
         ori     v1, v0, 0x7     /* way1 | write_enable | write_active */
         mtcr    v1, t1
-3:
+13:
         mfcr    v1, t1
         andi    v1, 0x1         /* wait for write_active == 0 */
-        bnez    v1, 3b
+        bnez    v1, 13b
         nop
         addi    t2, 1
-        bne     t3, t2, 1b
+        bne     t3, t2, 11b
+        nop
+        b       17f
+        nop
+
+        /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
+15:
+        li      t0, 0x80000000
+        li      t1, 0x80010000
+16:     cache   Index_Writeback_Inv_D, 0(t0)
+        addiu   t0, t0, 32
+        bne     t0, t1, 16b
         nop
+17:
 .endm
 
 /*
@@ -138,6 +158,13 @@ FEXPORT(nlm_reset_entry)
         nop
 
 1:      /* Entry point on core wakeup */
+        mfc0    t0, CP0_EBASE, 0        /* processor ID */
+        andi    t0, 0xff00
+        li      t1, 0x1500              /* XLP 9xx */
+        beq     t0, t1, 2f              /* does not need to set coherent */
+        nop
+
+        /* set bit in SYS coherent register for the core */
         mfc0    t0, CP0_EBASE, 1
         mfc0    t1, CP0_EBASE, 1
         srl     t1, 5
@@ -149,7 +176,7 @@ FEXPORT(nlm_reset_entry)
         li      t1, 0x1
         sll     t0, t1, t0
         nor     t0, t0, zero            /* t0 <- ~(1 << core) */
-        li      t2, SYS_CPU_COHERENT_BASE(0)
+        li      t2, SYS_CPU_COHERENT_BASE
         add     t2, t2, t3              /* t2 <- SYS offset for node */
         lw      t1, 0(t2)
         and     t1, t1, t0
@@ -159,13 +186,13 @@ FEXPORT(nlm_reset_entry)
         lw      t1, 0(t2)
         sync
 
+2:
         /* Configure LSU on Non-0 Cores. */
         xlp_config_lsu
         /* FALL THROUGH */
 
 /*
- * Wake up sibling threads from the initial thread in
- * a core.
+ * Wake up sibling threads from the initial thread in a core.
  */
 EXPORT(nlm_boot_siblings)
         /* core L1D flush before enable threads */
@@ -181,8 +208,10 @@ EXPORT(nlm_boot_siblings)
         /*
          * The new hardware thread starts at the next instruction
          * For all the cases other than core 0 thread 0, we will
-        * jump to the secondary wait function.
-        */
+         * jump to the secondary wait function.
+
+         * NOTE: All GPR contents are lost after the mtcr above!
+         */
         mfc0    v0, CP0_EBASE, 1
         andi    v0, 0x3ff               /* v0 <- node/core */
 
@@ -196,7 +225,7 @@ EXPORT(nlm_boot_siblings)
 #endif
         mtc0    t1, CP0_STATUS
 
-        /* mark CPU ready, careful here, previous mtcr trashed registers */
+        /* mark CPU ready */
         li      t3, CKSEG1ADDR(RESET_DATA_PHYS)
         ADDIU   t1, t3, BOOT_CPU_READY
         sll     v1, v0, 2
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index c0eded01fde9..6baae15cc7b1 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -63,7 +63,7 @@ void nlm_send_ipi_single(int logical_cpu, unsigned int action)
         uint64_t picbase;
 
         cpu = cpu_logical_map(logical_cpu);
-        node = cpu / NLM_CPUS_PER_NODE;
+        node = nlm_cpuid_to_node(cpu);
         picbase = nlm_get_node(node)->picbase;
 
         if (action & SMP_CALL_FUNCTION)
@@ -152,7 +152,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
         int cpu, node;
 
         cpu = cpu_logical_map(logical_cpu);
-        node = cpu / NLM_CPUS_PER_NODE;
+        node = nlm_cpuid_to_node(logical_cpu);
         nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
         nlm_next_gp = (unsigned long)task_thread_info(idle);
 
@@ -164,7 +164,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 void __init nlm_smp_setup(void)
 {
         unsigned int boot_cpu;
-        int num_cpus, i, ncore;
+        int num_cpus, i, ncore, node;
         volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
         char buf[64];
 
@@ -187,6 +187,8 @@ void __init nlm_smp_setup(void)
                         __cpu_number_map[i] = num_cpus;
                         __cpu_logical_map[num_cpus] = i;
                         set_cpu_possible(num_cpus, true);
+                        node = nlm_cpuid_to_node(i);
+                        cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
                         ++num_cpus;
                 }
         }
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index aa6cff0a229b..8597657c27fc 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -32,7 +32,6 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/init.h>
 
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
@@ -98,7 +97,7 @@ END(nlm_boot_secondary_cpus)
  * In case of RMIboot bootloader which is used on XLR boards, the CPUs
  * be already woken up and waiting in bootloader code.
  * This will get them out of the bootloader code and into linux. Needed
- *  because the bootloader area will be taken and initialized by linux.
+ * because the bootloader area will be taken and initialized by linux.
  */
 NESTED(nlm_rmiboot_preboot, 16, sp)
         mfc0    t0, $15, 1      /* read ebase */
@@ -133,6 +132,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
         or      t1, t2, v1      /* put in new value */
         mtcr    t1, t0          /* update core control */
 
+        /* wait for NMI to hit */
 1:      wait
         b       1b
         nop
diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile
index 0b9be5fd2e46..25c8e873ee25 100644
--- a/arch/mips/netlogic/dts/Makefile
+++ b/arch/mips/netlogic/dts/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
 obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
 obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
+obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o
diff --git a/arch/mips/netlogic/dts/xlp_gvp.dts b/arch/mips/netlogic/dts/xlp_gvp.dts
new file mode 100644
index 000000000000..047d27f54487
--- /dev/null
+++ b/arch/mips/netlogic/dts/xlp_gvp.dts
@@ -0,0 +1,76 @@
+/*
+ * XLP9XX Device Tree Source for GVP boards
+ */
+
+/dts-v1/;
+/ {
+        model = "netlogic,XLP-GVP";
+        compatible = "netlogic,xlp";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+                          1 0  0 0x16000000  0x02000000>; // GBU chipselects
+
+                serial0: serial@30000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x112100 0xa00>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clock-frequency = <125000000>;
+                        interrupt-parent = <&pic>;
+                        interrupts = <17>;
+                };
+                pic: pic@4000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0 0x110000 0x200>;
+                };
+
+                nor_flash@1,0 {
+                        compatible = "cfi-flash";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        reg = <1 0 0x1000000>;
+
+                        partition@0 {
+                                label = "x-loader";
+                                reg = <0x0 0x100000>; /* 1M */
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "u-boot";
+                                reg = <0x100000 0x100000>; /* 1M */
+                        };
+
+                        partition@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x500000>; /* 5M */
+                        };
+
+                        partition@700000 {
+                                label = "rootfs";
+                                reg = <0x700000 0x800000>; /* 8M */
+                        };
+
+                        partition@f00000 {
+                                label = "env";
+                                reg = <0xf00000 0x100000>; /* 1M */
+                                read-only;
+                        };
+                };
+
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
+        };
+};
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 8316d5454b17..5754097b9cde 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -42,13 +42,18 @@
 #include <asm/prom.h>
 
 extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
-        __dtb_xlp_fvp_begin[], __dtb_start[];
+        __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[];
 static void *xlp_fdt_blob;
 
 void __init *xlp_dt_init(void *fdtp)
 {
         if (!fdtp) {
                 switch (current_cpu_data.processor_id & 0xff00) {
+#ifdef CONFIG_DT_XLP_GVP
+                case PRID_IMP_NETLOGIC_XLP9XX:
+                        fdtp = __dtb_xlp_gvp_begin;
+                        break;
+#endif
 #ifdef CONFIG_DT_XLP_FVP
                 case PRID_IMP_NETLOGIC_XLP2XX:
                         fdtp = __dtb_xlp_fvp_begin;
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 56c50ba43c9b..997cd9ee10de 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -57,6 +57,10 @@ void nlm_node_init(int node)
         nodep->sysbase = nlm_get_sys_regbase(node);
         nodep->picbase = nlm_get_pic_regbase(node);
         nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
+        if (cpu_is_xlp9xx())
+                nodep->socbus = xlp9xx_get_socbus(node);
+        else
+                nodep->socbus = 0;
         spin_lock_init(&nodep->piclock);
 }
 
@@ -65,6 +69,26 @@ int nlm_irq_to_irt(int irq)
         uint64_t pcibase;
         int devoff, irt;
 
+        /* bypass for 9xx */
+        if (cpu_is_xlp9xx()) {
+                switch (irq) {
+                case PIC_9XX_XHCI_0_IRQ:
+                        return 114;
+                case PIC_9XX_XHCI_1_IRQ:
+                        return 115;
+                case PIC_UART_0_IRQ:
+                        return 133;
+                case PIC_UART_1_IRQ:
+                        return 134;
+                case PIC_PCIE_LINK_LEGACY_IRQ(0):
+                case PIC_PCIE_LINK_LEGACY_IRQ(1):
+                case PIC_PCIE_LINK_LEGACY_IRQ(2):
+                case PIC_PCIE_LINK_LEGACY_IRQ(3):
+                        return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
+                }
+                return -1;
+        }
+
         devoff = 0;
         switch (irq) {
         case PIC_UART_0_IRQ:
@@ -135,9 +159,17 @@ int nlm_irq_to_irt(int irq)
                 case PIC_I2C_3_IRQ:
                         irt = irt + 3; break;
                 }
-        } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
+        } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
+                        irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
                 /* HW bug, PCI IRT entries are bad on early silicon, fix */
-                irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
+                irt = PIC_IRT_PCIE_LINK_INDEX(irq -
+                                        PIC_PCIE_LINK_LEGACY_IRQ_BASE);
+        } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
+                        irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
+                irt = -2;
+        } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
+                        irq <= PIC_PCIE_MSIX_IRQ(3)) {
+                irt = -2;
         } else {
                 irt = -1;
         }
@@ -151,7 +183,10 @@ unsigned int nlm_get_core_frequency(int node, int core)
         uint64_t num, sysbase;
 
         sysbase = nlm_get_node(node)->sysbase;
-        rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
+        if (cpu_is_xlp9xx())
+                rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
+        else
+                rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
         if (cpu_is_xlpii()) {
                 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
                 denom = 3;
@@ -265,6 +300,10 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
 
 unsigned int nlm_get_pic_frequency(int node)
 {
+        /* TODO Has to calculate freq as like 2xx */
+        if (cpu_is_xlp9xx())
+                return 250000000;
+
         if (cpu_is_xlpii())
                 return nlm_2xx_get_pic_frequency(node);
         else
@@ -284,21 +323,33 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
 {
         uint64_t bridgebase, base, lim;
         uint32_t val;
+        unsigned int barreg, limreg, xlatreg;
         int i, node, rv;
 
         /* Look only at mapping on Node 0, we don't handle crazy configs */
         bridgebase = nlm_get_bridge_regbase(0);
         rv = 0;
         for (i = 0; i < 8; i++) {
-                val = nlm_read_bridge_reg(bridgebase,
-                                        BRIDGE_DRAM_NODE_TRANSLN(i));
-                node = (val >> 1) & 0x3;
-                if (n >= 0 && n != node)
-                        continue;
-                val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
+                if (cpu_is_xlp9xx()) {
+                        barreg = BRIDGE_9XX_DRAM_BAR(i);
+                        limreg = BRIDGE_9XX_DRAM_LIMIT(i);
+                        xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
+                } else {
+                        barreg = BRIDGE_DRAM_BAR(i);
+                        limreg = BRIDGE_DRAM_LIMIT(i);
+                        xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
+                }
+                if (n >= 0) {
+                        /* node specified, get node mapping of BAR */
+                        val = nlm_read_bridge_reg(bridgebase, xlatreg);
+                        node = (val >> 1) & 0x3;
+                        if (n != node)
+                                continue;
+                }
+                val = nlm_read_bridge_reg(bridgebase, barreg);
                 val = (val >>  12) & 0xfffff;
                 base = (uint64_t) val << 20;
-                val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
+                val = nlm_read_bridge_reg(bridgebase, limreg);
                 val = (val >>  12) & 0xfffff;
                 if (val == 0)   /* BAR not used */
                         continue;
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 54e75c77184b..8c60a2dd9ef6 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,12 +51,16 @@ uint64_t nlm_io_base;
 struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 cpumask_t nlm_cpumask = CPU_MASK_CPU0;
 unsigned int nlm_threads_per_core;
+unsigned int xlp_cores_per_node;
 
 static void nlm_linux_exit(void)
 {
         uint64_t sysbase = nlm_get_node(0)->sysbase;
 
-        nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
+        if (cpu_is_xlp9xx())
+                nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1);
+        else
+                nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
         for ( ; ; )
                 cpu_wait();
 }
@@ -92,6 +96,14 @@ static void __init xlp_init_mem_from_bars(void)
 
 void __init plat_mem_setup(void)
 {
+#ifdef CONFIG_SMP
+        nlm_wakeup_secondary_cpus();
+
+        /* update TLB size after waking up threads */
+        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+
+        register_smp_ops(&nlm_smp_ops);
+#endif
         _machine_restart = (void (*)(char *))nlm_linux_exit;
         _machine_halt   = nlm_linux_exit;
         pm_power_off    = nlm_linux_exit;
@@ -110,6 +122,7 @@ void __init plat_mem_setup(void)
 const char *get_system_type(void)
 {
         switch (read_c0_prid() & 0xff00) {
+        case PRID_IMP_NETLOGIC_XLP9XX:
         case PRID_IMP_NETLOGIC_XLP2XX:
                 return "Broadcom XLPII Series";
         default:
@@ -149,6 +162,10 @@ void __init prom_init(void)
         void *reset_vec;
 
         nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
+        if (cpu_is_xlp9xx())
+                xlp_cores_per_node = 32;
+        else
+                xlp_cores_per_node = 8;
         nlm_init_boot_cpu();
         xlp_mmu_init();
         nlm_node_init(0);
@@ -162,11 +179,5 @@ void __init prom_init(void)
 
 #ifdef CONFIG_SMP
         cpumask_setall(&nlm_cpumask);
-        nlm_wakeup_secondary_cpus();
-
-        /* update TLB size after waking up threads */
-        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
-
-        register_smp_ops(&nlm_smp_ops);
 #endif
 }
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 36e9c22afc46..17ade1ce5dfd 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -37,6 +37,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/pci_ids.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 
@@ -83,12 +84,14 @@
 #define nlm_read_usb_reg(b, r)          nlm_read_reg(b, r)
 #define nlm_write_usb_reg(b, r, v)      nlm_write_reg(b, r, v)
 
-#define nlm_xlpii_get_usb_pcibase(node, inst)           \
-        nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst))
+#define nlm_xlpii_get_usb_pcibase(node, inst)                   \
+                        nlm_pcicfg_base(cpu_is_xlp9xx() ?       \
+                        XLP9XX_IO_USB_OFFSET(node, inst) :      \
+                        XLP2XX_IO_USB_OFFSET(node, inst))
 #define nlm_xlpii_get_usb_regbase(node, inst)           \
         (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
 
-static void xlpii_usb_ack(struct irq_data *data)
+static void xlp2xx_usb_ack(struct irq_data *data)
 {
         u64 port_addr;
 
@@ -109,6 +112,29 @@ static void xlpii_usb_ack(struct irq_data *data)
         nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
 }
 
+static void xlp9xx_usb_ack(struct irq_data *data)
+{
+        u64 port_addr;
+        int node, irq;
+
+        /* Find the node and irq on the node */
+        irq = data->irq % NLM_IRQS_PER_NODE;
+        node = data->irq / NLM_IRQS_PER_NODE;
+
+        switch (irq) {
+        case PIC_9XX_XHCI_0_IRQ:
+                port_addr = nlm_xlpii_get_usb_regbase(node, 1);
+                break;
+        case PIC_9XX_XHCI_1_IRQ:
+                port_addr = nlm_xlpii_get_usb_regbase(node, 2);
+                break;
+        default:
+                pr_err("No matching USB irq %d node  %d!\n", irq, node);
+                return;
+        }
+        nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
+}
+
 static void nlm_xlpii_usb_hw_reset(int node, int port)
 {
         u64 port_addr, xhci_base, pci_base;
@@ -178,17 +204,33 @@ static void nlm_xlpii_usb_hw_reset(int node, int port)
 
 static int __init nlm_platform_xlpii_usb_init(void)
 {
+        int node;
+
         if (!cpu_is_xlpii())
                 return 0;
 
-        pr_info("Initializing 2XX USB Interface\n");
-        nlm_xlpii_usb_hw_reset(0, 1);
-        nlm_xlpii_usb_hw_reset(0, 2);
-        nlm_xlpii_usb_hw_reset(0, 3);
-        nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack);
-        nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack);
-        nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack);
+        if (!cpu_is_xlp9xx()) {
+                /* XLP 2XX single node */
+                pr_info("Initializing 2XX USB Interface\n");
+                nlm_xlpii_usb_hw_reset(0, 1);
+                nlm_xlpii_usb_hw_reset(0, 2);
+                nlm_xlpii_usb_hw_reset(0, 3);
+                nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack);
+                nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack);
+                nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack);
+                return 0;
+        }
 
+        /* XLP 9XX, multi-node */
+        pr_info("Initializing 9XX USB Interface\n");
+        for (node = 0; node < NLM_NR_NODES; node++) {
+                if (!nlm_node_present(node))
+                        continue;
+                nlm_xlpii_usb_hw_reset(node, 1);
+                nlm_xlpii_usb_hw_reset(node, 2);
+                nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
+                nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
+        }
         return 0;
 }
 
@@ -196,8 +238,26 @@ arch_initcall(nlm_platform_xlpii_usb_init);
 
 static u64 xlp_usb_dmamask = ~(u32)0;
 
-/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */
-static void nlm_usb_fixup_final(struct pci_dev *dev)
+/* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */
+static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
+{
+        int node;
+
+        node = xlp_socdev_to_node(dev);
+        dev->dev.dma_mask               = &xlp_usb_dmamask;
+        dev->dev.coherent_dma_mask      = DMA_BIT_MASK(32);
+        switch (dev->devfn) {
+        case 0x21:
+                dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ);
+                break;
+        case 0x22:
+                dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
+                break;
+        }
+}
+
+/* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */
+static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev)
 {
         dev->dev.dma_mask               = &xlp_usb_dmamask;
         dev->dev.coherent_dma_mask      = DMA_BIT_MASK(32);
@@ -214,5 +274,7 @@ static void nlm_usb_fixup_final(struct pci_dev *dev)
         }
 }
 
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI,
+                nlm_xlp9xx_usb_fixup_final);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
-                nlm_usb_fixup_final);
+                nlm_xlp2xx_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 682d5638dc01..9a92617a2af5 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -32,7 +32,6 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/threads.h>
 
@@ -47,14 +46,14 @@
 #include <asm/netlogic/mips-extns.h>
 
 #include <asm/netlogic/xlp-hal/iomap.h>
-#include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/sys.h>
 
 static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
 {
         uint32_t coremask, value;
-        int count;
+        int count, resetreg;
 
         coremask = (1 << core);
 
@@ -65,12 +64,24 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
                 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
         }
 
+        /* On 9XX, mark coherent first */
+        if (cpu_is_xlp9xx()) {
+                value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
+                value &= ~coremask;
+                nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
+        }
+
         /* Remove CPU Reset */
-        value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
+        resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
+        value = nlm_read_sys_reg(sysbase, resetreg);
         value &= ~coremask;
-        nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
+        nlm_write_sys_reg(sysbase, resetreg, value);
+
+        /* We are done on 9XX */
+        if (cpu_is_xlp9xx())
+                return 1;
 
-        /* Poll for CPU to mark itself coherent */
+        /* Poll for CPU to mark itself coherent on other type of XLP */
         count = 100000;
         do {
                 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
@@ -84,7 +95,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
         volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
         int i, count, notready;
 
-        count = 0x20000000;
+        count = 0x800000;
         do {
                 notready = nlm_threads_per_core;
                 for (i = 0; i < nlm_threads_per_core; i++)
@@ -98,27 +109,62 @@ static int wait_for_cpus(int cpu, int bootcpu)
 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 {
         struct nlm_soc_info *nodep;
-        uint64_t syspcibase;
-        uint32_t syscoremask;
+        uint64_t syspcibase, fusebase;
+        uint32_t syscoremask, mask, fusemask;
         int core, n, cpu;
 
         for (n = 0; n < NLM_NR_NODES; n++) {
-                syspcibase = nlm_get_sys_pcibase(n);
-                if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
-                        break;
+                if (n != 0) {
+                        /* check if node exists and is online */
+                        if (cpu_is_xlp9xx()) {
+                                int b = xlp9xx_get_socbus(n);
+                                pr_info("Node %d SoC PCI bus %d.\n", n, b);
+                                if (b == 0)
+                                        break;
+                        } else {
+                                syspcibase = nlm_get_sys_pcibase(n);
+                                if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
+                                        break;
+                        }
+                        nlm_node_init(n);
+                }
 
                 /* read cores in reset from SYS */
-                if (n != 0)
-                        nlm_node_init(n);
                 nodep = nlm_get_node(n);
-                syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
+
+                if (cpu_is_xlp9xx()) {
+                        fusebase = nlm_get_fuse_regbase(n);
+                        fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
+                        mask = 0xfffff;
+                } else {
+                        fusemask = nlm_read_sys_reg(nodep->sysbase,
+                                                SYS_EFUSE_DEVICE_CFG_STATUS0);
+                        switch (read_c0_prid() & 0xff00) {
+                        case PRID_IMP_NETLOGIC_XLP3XX:
+                                mask = 0xf;
+                                break;
+                        case PRID_IMP_NETLOGIC_XLP2XX:
+                                mask = 0x3;
+                                break;
+                        case PRID_IMP_NETLOGIC_XLP8XX:
+                        default:
+                                mask = 0xff;
+                                break;
+                        }
+                }
+
+                /*
+                 * Fused out cores are set in the fusemask, and the remaining
+                 * cores are renumbered to range 0 .. nactive-1
+                 */
+                syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
+
                 /* The boot cpu */
-                if (n == 0) {
-                        syscoremask |= 1;
+                if (n == 0)
                         nodep->coremask = 1;
-                }
 
-                for (core = 0; core < NLM_CORES_PER_NODE; core++) {
+                pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
+                for (core = 0; core < nlm_cores_per_node(); core++) {
                         /* we will be on node 0 core 0 */
                         if (n == 0 && core == 0)
                                 continue;
@@ -128,7 +174,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
                                 continue;
 
                         /* see if at least the first hw thread is enabled */
-                        cpu = (n * NLM_CORES_PER_NODE + core)
+                        cpu = (n * nlm_cores_per_node() + core)
                                                 * NLM_THREADS_PER_CORE;
                         if (!cpumask_test_cpu(cpu, wakeup_mask))
                                 continue;
@@ -141,7 +187,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
                         nodep->coremask |= 1u << core;
 
                         /* spin until the hw threads sets their ready */
-                        wait_for_cpus(cpu, 0);
+                        if (!wait_for_cpus(cpu, 0))
+                                pr_err("Node %d : timeout core %d\n", n, core);
                 }
         }
 }
@@ -153,7 +200,8 @@ void xlp_wakeup_secondary_cpus()
          * first wakeup core 0 threads
          */
         xlp_boot_core0_siblings();
-        wait_for_cpus(0, 0);
+        if (!wait_for_cpus(0, 0))
+                pr_err("Node 0 : timeout core 0\n");
 
         /* now get other cores out of reset */
         xlp_enable_secondary_cores(&nlm_cpumask);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 7b96a91f4773..4785932af248 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -23,7 +23,7 @@
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
 
-unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
+static unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
 {
         uint64_t uartbase;
         unsigned int value;
@@ -41,7 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
         return value;
 }
 
-void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
+static void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
 {
         uint64_t uartbase;
 
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 921be5f77797..d118b9aa7647 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -60,25 +60,6 @@ unsigned int  nlm_threads_per_core = 1;
 struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 cpumask_t nlm_cpumask = CPU_MASK_CPU0;
 
-static void __init nlm_early_serial_setup(void)
-{
-        struct uart_port s;
-        unsigned long uart_base;
-
-        uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
-        memset(&s, 0, sizeof(s));
-        s.flags         = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
-        s.iotype        = UPIO_MEM32;
-        s.regshift      = 2;
-        s.irq           = PIC_UART_0_IRQ;
-        s.uartclk       = PIC_CLK_HZ;
-        s.serial_in     = nlm_xlr_uart_in;
-        s.serial_out    = nlm_xlr_uart_out;
-        s.mapbase       = uart_base;
-        s.membase       = (unsigned char __iomem *)uart_base;
-        early_serial_setup(&s);
-}
-
 static void nlm_linux_exit(void)
 {
         uint64_t gpiobase;
@@ -214,7 +195,6 @@ void __init prom_init(void)
         memcpy(reset_vec, (void *)nlm_reset_entry,
                         (nlm_reset_entry_end - nlm_reset_entry));
 
-        nlm_early_serial_setup();
         build_arcs_cmdline(argv);
         prom_add_memory();
 
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 9fb81fa6272a..d61cba1e9c65 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -32,7 +32,6 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/threads.h>
 
@@ -70,7 +69,7 @@ int xlr_wakeup_secondary_cpus(void)
 
         /* Fill up the coremask early */
         nodep->coremask = 1;
-        for (i = 1; i < NLM_CORES_PER_NODE; i++) {
+        for (i = 1; i < nlm_cores_per_node(); i++) {
                 for (j = 1000000; j > 0; j--) {
                         if (cpu_ready[i * NLM_THREADS_PER_CORE])
                                 break;
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 4d1736fc1955..2a86e38872a7 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -86,6 +86,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         case CPU_34K:
         case CPU_1004K:
         case CPU_74K:
+        case CPU_INTERAPTIV:
+        case CPU_PROAPTIV:
         case CPU_LOONGSON1:
         case CPU_SB1:
         case CPU_SB1A:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 3a2b6e9f25cf..4d94d75ec6f9 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -376,6 +376,14 @@ static int __init mipsxx_init(void)
                 op_model_mipsxx_ops.cpu_type = "mips/74K";
                 break;
 
+        case CPU_INTERAPTIV:
+                op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
+                break;
+
+        case CPU_PROAPTIV:
+                op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
+                break;
+
         case CPU_5KC:
                 op_model_mipsxx_ops.cpu_type = "mips/5K";
                 break;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 719e4557e22e..137f2a6feb25 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -60,4 +60,5 @@ obj-$(CONFIG_CPU_XLP)		+= pci-xlp.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
+obj-$(CONFIG_CPU_XLP)           += msi-xlp.o
 endif
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index df36e2327c54..7a0eda782e35 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -54,6 +54,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 static void malta_piix_func0_fixup(struct pci_dev *pdev)
 {
         unsigned char reg_val;
+        u32 reg_val32;
         /* PIIX PIRQC[A:D] irq mappings */
         static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
                 0,  0,  0,  3,
@@ -83,6 +84,16 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
                 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
                                 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
         }
+
+        /* Mux SERIRQ to its pin */
+        pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
+        pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
+                               reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
+
+        /* Enable SERIRQ */
+        pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
+        reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
+        pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index d0f6ecbf35f7..7fcafd5da7da 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -27,7 +27,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 
 #include <asm/mach-rc32434/rc32434.h>
 #include <asm/mach-rc32434/irq.h>
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index 1441becdcb6c..8feae9154baf 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -8,7 +8,6 @@
  *      2 of the License, or (at your option) any later version.
  */
 
-#include <linux/init.h>
 #include <linux/pci.h>
 
 /*
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
new file mode 100644
index 000000000000..afd8405e0188
--- /dev/null
+++ b/arch/mips/pci/msi-xlp.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/msi.h>
+#include <linux/mm.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
+#include <linux/console.h>
+
+#include <asm/io.h>
+
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/pcibus.h>
+#include <asm/netlogic/xlp-hal/bridge.h>
+
+#define XLP_MSIVEC_PER_LINK     32
+#define XLP_MSIXVEC_TOTAL       32
+#define XLP_MSIXVEC_PER_LINK    8
+
+/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
+static inline int nlm_link_msiirq(int link, int msivec)
+{
+        return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec;
+}
+
+static inline int nlm_irq_msivec(int irq)
+{
+        return irq % XLP_MSIVEC_PER_LINK;
+}
+
+static inline int nlm_irq_msilink(int irq)
+{
+        return (irq % (XLP_MSIVEC_PER_LINK * PCIE_NLINKS)) /
+                                                XLP_MSIVEC_PER_LINK;
+}
+
+/*
+ * Only 32 MSI-X vectors are possible because there are only 32 PIC
+ * interrupts for MSI. We split them statically and use 8 MSI-X vectors
+ * per link - this keeps the allocation and lookup simple.
+ */
+static inline int nlm_link_msixirq(int link, int bit)
+{
+        return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit;
+}
+
+static inline int nlm_irq_msixvec(int irq)
+{
+        return irq % XLP_MSIXVEC_TOTAL;  /* works when given xirq */
+}
+
+static inline int nlm_irq_msixlink(int irq)
+{
+        return nlm_irq_msixvec(irq) / XLP_MSIXVEC_PER_LINK;
+}
+
+/*
+ * Per link MSI and MSI-X information, set as IRQ handler data for
+ * MSI and MSI-X interrupts.
+ */
+struct xlp_msi_data {
+        struct nlm_soc_info *node;
+        uint64_t        lnkbase;
+        uint32_t        msi_enabled_mask;
+        uint32_t        msi_alloc_mask;
+        uint32_t        msix_alloc_mask;
+        spinlock_t      msi_lock;
+};
+
+/*
+ * MSI Chip definitions
+ *
+ * On XLP, there is a PIC interrupt associated with each PCIe link on the
+ * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa
+ * per link and 128 overall.
+ *
+ * When a device connected to the link raises a MSI interrupt, we get a
+ * link interrupt and we then have to look at PCIE_MSI_STATUS register at
+ * the bridge to map it to the IRQ
+ */
+static void xlp_msi_enable(struct irq_data *d)
+{
+        struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+        unsigned long flags;
+        int vec;
+
+        vec = nlm_irq_msivec(d->irq);
+        spin_lock_irqsave(&md->msi_lock, flags);
+        md->msi_enabled_mask |= 1u << vec;
+        nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
+        spin_unlock_irqrestore(&md->msi_lock, flags);
+}
+
+static void xlp_msi_disable(struct irq_data *d)
+{
+        struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+        unsigned long flags;
+        int vec;
+
+        vec = nlm_irq_msivec(d->irq);
+        spin_lock_irqsave(&md->msi_lock, flags);
+        md->msi_enabled_mask &= ~(1u << vec);
+        nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
+        spin_unlock_irqrestore(&md->msi_lock, flags);
+}
+
+static void xlp_msi_mask_ack(struct irq_data *d)
+{
+        struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+        int link, vec;
+
+        link = nlm_irq_msilink(d->irq);
+        vec = nlm_irq_msivec(d->irq);
+        xlp_msi_disable(d);
+
+        /* Ack MSI on bridge */
+        nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
+
+        /* Ack at eirr and PIC */
+        ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
+        nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
+}
+
+static struct irq_chip xlp_msi_chip = {
+        .name           = "XLP-MSI",
+        .irq_enable     = xlp_msi_enable,
+        .irq_disable    = xlp_msi_disable,
+        .irq_mask_ack   = xlp_msi_mask_ack,
+        .irq_unmask     = xlp_msi_enable,
+};
+
+/*
+ * The MSI-X interrupt handling is different from MSI, there are 32
+ * MSI-X interrupts generated by the PIC and each of these correspond
+ * to a MSI-X vector (0-31) that can be assigned.
+ *
+ * We divide the MSI-X vectors to 8 per link and do a per-link
+ * allocation
+ *
+ * Enable and disable done using standard MSI functions.
+ */
+static void xlp_msix_mask_ack(struct irq_data *d)
+{
+        struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
+        int link, msixvec;
+
+        msixvec = nlm_irq_msixvec(d->irq);
+        link = nlm_irq_msixlink(d->irq);
+        mask_msi_irq(d);
+
+        /* Ack MSI on bridge */
+        nlm_write_reg(md->lnkbase, PCIE_MSIX_STATUS, 1u << msixvec);
+
+        /* Ack at eirr and PIC */
+        ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
+        nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_MSIX_INDEX(msixvec));
+}
+
+static struct irq_chip xlp_msix_chip = {
+        .name           = "XLP-MSIX",
+        .irq_enable     = unmask_msi_irq,
+        .irq_disable    = mask_msi_irq,
+        .irq_mask_ack   = xlp_msix_mask_ack,
+        .irq_unmask     = unmask_msi_irq,
+};
+
+void destroy_irq(unsigned int irq)
+{
+            /* nothing to do yet */
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        destroy_irq(irq);
+}
+
+/*
+ * Setup a PCIe link for MSI.  By default, the links are in
+ * legacy interrupt mode.  We will switch them to MSI mode
+ * at the first MSI request.
+ */
+static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
+{
+        u32 val;
+
+        val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
+        if ((val & 0x200) == 0) {
+                val |= 0x200;           /* MSI Interrupt enable */
+                nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
+        }
+
+        val = nlm_read_reg(lnkbase, 0x1);       /* CMD */
+        if ((val & 0x0400) == 0) {
+                val |= 0x0400;
+                nlm_write_reg(lnkbase, 0x1, val);
+        }
+
+        /* Update IRQ in the PCI irq reg */
+        val = nlm_read_pci_reg(lnkbase, 0xf);
+        val &= ~0x1fu;
+        val |= (1 << 8) | lirq;
+        nlm_write_pci_reg(lnkbase, 0xf, val);
+
+        /* MSI addr */
+        nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
+        nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
+
+        /* MSI cap for bridge */
+        val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
+        if ((val & (1 << 16)) == 0) {
+                val |= 0xb << 16;               /* mmc32, msi enable */
+                nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
+        }
+}
+
+/*
+ * Allocate a MSI vector on a link
+ */
+static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
+        struct msi_desc *desc)
+{
+        struct xlp_msi_data *md;
+        struct msi_msg msg;
+        unsigned long flags;
+        int msivec, irt, lirq, xirq, ret;
+        uint64_t msiaddr;
+
+        /* Get MSI data for the link */
+        lirq = PIC_PCIE_LINK_MSI_IRQ(link);
+        xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
+        md = irq_get_handler_data(xirq);
+        msiaddr = MSI_LINK_ADDR(node, link);
+
+        spin_lock_irqsave(&md->msi_lock, flags);
+        if (md->msi_alloc_mask == 0) {
+                /* switch the link IRQ to MSI range */
+                xlp_config_link_msi(lnkbase, lirq, msiaddr);
+                irt = PIC_IRT_PCIE_LINK_INDEX(link);
+                nlm_setup_pic_irq(node, lirq, lirq, irt);
+                nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
+                                 node * nlm_threads_per_node(), 1 /*en */);
+        }
+
+        /* allocate a MSI vec, and tell the bridge about it */
+        msivec = fls(md->msi_alloc_mask);
+        if (msivec == XLP_MSIVEC_PER_LINK) {
+                spin_unlock_irqrestore(&md->msi_lock, flags);
+                return -ENOMEM;
+        }
+        md->msi_alloc_mask |= (1u << msivec);
+        spin_unlock_irqrestore(&md->msi_lock, flags);
+
+        msg.address_hi = msiaddr >> 32;
+        msg.address_lo = msiaddr & 0xffffffff;
+        msg.data = 0xc00 | msivec;
+
+        xirq = xirq + msivec;           /* msi mapped to global irq space */
+        ret = irq_set_msi_desc(xirq, desc);
+        if (ret < 0) {
+                destroy_irq(xirq);
+                return ret;
+        }
+
+        write_msi_msg(xirq, &msg);
+        return 0;
+}
+
+/*
+ * Switch a link to MSI-X mode
+ */
+static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
+{
+        u32 val;
+
+        val = nlm_read_reg(lnkbase, 0x2C);
+        if ((val & 0x80000000U) == 0) {
+                val |= 0x80000000U;
+                nlm_write_reg(lnkbase, 0x2C, val);
+        }
+        val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
+        if ((val & 0x200) == 0) {
+                val |= 0x200;           /* MSI Interrupt enable */
+                nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
+        }
+
+        val = nlm_read_reg(lnkbase, 0x1);       /* CMD */
+        if ((val & 0x0400) == 0) {
+                val |= 0x0400;
+                nlm_write_reg(lnkbase, 0x1, val);
+        }
+
+        /* Update IRQ in the PCI irq reg */
+        val = nlm_read_pci_reg(lnkbase, 0xf);
+        val &= ~0x1fu;
+        val |= (1 << 8) | lirq;
+        nlm_write_pci_reg(lnkbase, 0xf, val);
+
+        /* MSI-X addresses */
+        nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, msixaddr >> 8);
+        nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
+                                        (msixaddr + MSI_ADDR_SZ) >> 8);
+}
+
+/*
+ *  Allocate a MSI-X vector
+ */
+static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
+        struct msi_desc *desc)
+{
+        struct xlp_msi_data *md;
+        struct msi_msg msg;
+        unsigned long flags;
+        int t, msixvec, lirq, xirq, ret;
+        uint64_t msixaddr;
+
+        /* Get MSI data for the link */
+        lirq = PIC_PCIE_MSIX_IRQ(link);
+        xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
+        md = irq_get_handler_data(xirq);
+        msixaddr = MSIX_LINK_ADDR(node, link);
+
+        spin_lock_irqsave(&md->msi_lock, flags);
+        /* switch the PCIe link to MSI-X mode at the first alloc */
+        if (md->msix_alloc_mask == 0)
+                xlp_config_link_msix(lnkbase, lirq, msixaddr);
+
+        /* allocate a MSI-X vec, and tell the bridge about it */
+        t = fls(md->msix_alloc_mask);
+        if (t == XLP_MSIXVEC_PER_LINK) {
+                spin_unlock_irqrestore(&md->msi_lock, flags);
+                return -ENOMEM;
+        }
+        md->msix_alloc_mask |= (1u << t);
+        spin_unlock_irqrestore(&md->msi_lock, flags);
+
+        xirq += t;
+        msixvec = nlm_irq_msixvec(xirq);
+        msg.address_hi = msixaddr >> 32;
+        msg.address_lo = msixaddr & 0xffffffff;
+        msg.data = 0xc00 | msixvec;
+
+        ret = irq_set_msi_desc(xirq, desc);
+        if (ret < 0) {
+                destroy_irq(xirq);
+                return ret;
+        }
+
+        write_msi_msg(xirq, &msg);
+        return 0;
+}
+
+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
+        struct pci_dev *lnkdev;
+        uint64_t lnkbase;
+        int node, link, slot;
+
+        lnkdev = xlp_get_pcie_link(dev);
+        if (lnkdev == NULL) {
+                dev_err(&dev->dev, "Could not find bridge\n");
+                return 1;
+        }
+        slot = PCI_SLOT(lnkdev->devfn);
+        link = PCI_FUNC(lnkdev->devfn);
+        node = slot / 8;
+        lnkbase = nlm_get_pcie_base(node, link);
+
+        if (desc->msi_attrib.is_msix)
+                return xlp_setup_msix(lnkbase, node, link, desc);
+        else
+                return xlp_setup_msi(lnkbase, node, link, desc);
+}
+
+void __init xlp_init_node_msi_irqs(int node, int link)
+{
+        struct nlm_soc_info *nodep;
+        struct xlp_msi_data *md;
+        int irq, i, irt, msixvec;
+
+        pr_info("[%d %d] Init node PCI IRT\n", node, link);
+        nodep = nlm_get_node(node);
+
+        /* Alloc an MSI block for the link */
+        md = kzalloc(sizeof(*md), GFP_KERNEL);
+        spin_lock_init(&md->msi_lock);
+        md->msi_enabled_mask = 0;
+        md->msi_alloc_mask = 0;
+        md->msix_alloc_mask = 0;
+        md->node = nodep;
+        md->lnkbase = nlm_get_pcie_base(node, link);
+
+        /* extended space for MSI interrupts */
+        irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
+        for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
+                irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
+                irq_set_handler_data(i, md);
+        }
+
+        for (i = 0; i < XLP_MSIXVEC_PER_LINK; i++) {
+                /* Initialize MSI-X irts to generate one interrupt per link */
+                msixvec = link * XLP_MSIXVEC_PER_LINK + i;
+                irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec);
+                nlm_pic_init_irt(nodep->picbase, irt, PIC_PCIE_MSIX_IRQ(link),
+                        node * nlm_threads_per_node(), 1 /* enable */);
+
+                /* Initialize MSI-X extended irq space for the link  */
+                irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
+                irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
+                irq_set_handler_data(irq, md);
+        }
+
+}
+
+void nlm_dispatch_msi(int node, int lirq)
+{
+        struct xlp_msi_data *md;
+        int link, i, irqbase;
+        u32 status;
+
+        link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
+        irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
+        md = irq_get_handler_data(irqbase);
+        status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
+                                                md->msi_enabled_mask;
+        while (status) {
+                i = __ffs(status);
+                do_IRQ(irqbase + i);
+                status &= status - 1;
+        }
+}
+
+void nlm_dispatch_msix(int node, int lirq)
+{
+        struct xlp_msi_data *md;
+        int link, i, irqbase;
+        u32 status;
+
+        link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
+        irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
+        md = irq_get_handler_data(irqbase);
+        status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
+
+        /* narrow it down to the MSI-x vectors for our link */
+        status = (status >> (link * XLP_MSIXVEC_PER_LINK)) &
+                        ((1 << XLP_MSIXVEC_PER_LINK) - 1);
+
+        while (status) {
+                i = __ffs(status);
+                do_IRQ(irqbase + i);
+                status &= status - 1;
+        }
+}
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 6144bb337e44..13eea696bbe7 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -9,7 +9,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 830352e3aeda..c06205a87348 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -22,7 +22,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 
 #include <asm/mips-boards/bonito64.h>
 
diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
index 16e7c2526d77..e5738ee26f4f 100644
--- a/arch/mips/pci/ops-lantiq.c
+++ b/arch/mips/pci/ops-lantiq.c
@@ -9,7 +9,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
 #include <asm/addrspace.h>
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index 98254afa0287..24138bb0cbe1 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -14,7 +14,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/export.h>
 
 #include <loongson.h>
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index 1cfb5588699f..6b5821febc38 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -6,7 +6,6 @@
  * Copyright (C) 2000, 2001 Keith M Wesolowski
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/types.h>
 #include <asm/pci.h>
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 92a8543361bb..dbbf3657896c 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -24,7 +24,6 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 
 #include <asm/mips-boards/msc01_pci.h>
 
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index 499e35c3eb35..a1a7c9f4096e 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -1,5 +1,4 @@
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/pci.h>
 #include <asm/bootinfo.h>
 
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
index 7c7182e2350a..874ed6df9768 100644
--- a/arch/mips/pci/ops-rc32434.c
+++ b/arch/mips/pci/ops-rc32434.c
@@ -26,7 +26,6 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/io.h>
 #include <linux/pci.h>
 #include <linux/types.h>
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 162b4cb29dba..0f09eafa5e3a 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -7,7 +7,6 @@
  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/export.h>
 #include <linux/pci.h>
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c
index 37134ddfeaa5..f1a73890dd4f 100644
--- a/arch/mips/pci/pci-malta.c
+++ b/arch/mips/pci/pci-malta.c
@@ -241,9 +241,9 @@ void __init mips_pcibios_init(void)
                 return;
         }
 
-        /* Change start address to avoid conflicts with ACPI and SMB devices */
-        if (controller->io_resource->start < 0x00002000UL)
-                controller->io_resource->start = 0x00002000UL;
+        /* PIIX4 ACPI starts at 0x1000 */
+        if (controller->io_resource->start < 0x00001000UL)
+                controller->io_resource->start = 0x00001000UL;
 
         iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
         ioport_resource.end = controller->io_resource->end;
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index adeff2bfe4cd..72919aeef42b 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -436,9 +436,6 @@ static int rt3883_pci_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                return -EINVAL;
-
         rpc->base = devm_ioremap_resource(dev, res);
         if (IS_ERR(rpc->base))
                 return PTR_ERR(rpc->base);
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 653d2db9e0c5..7babf01600cb 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -47,10 +47,11 @@
 #include <asm/netlogic/interrupt.h>
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
 
 #include <asm/netlogic/xlp-hal/iomap.h>
-#include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/pcibus.h>
 #include <asm/netlogic/xlp-hal/bridge.h>
 
@@ -66,9 +67,22 @@ static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
         u32 *cfgaddr;
 
         where &= ~3;
-        if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954)
+        if (cpu_is_xlp9xx()) {
+                /* be very careful on SoC buses */
+                if (bus->number == 0) {
+                        /* Scan only existing nodes - uboot bug? */
+                        if (PCI_SLOT(devfn) != 0 ||
+                                           !nlm_node_present(PCI_FUNC(devfn)))
+                                return 0xffffffff;
+                } else if (bus->parent->number == 0) {  /* SoC bus */
+                        if (PCI_SLOT(devfn) == 0)       /* b.0.0 hangs */
+                                return 0xffffffff;
+                        if (devfn == 44)                /* b.5.4 hangs */
+                                return 0xffffffff;
+                }
+        } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
                 return 0xffffffff;
-
+        }
         cfgaddr = (u32 *)(pci_config_base +
                         pci_cfg_addr(bus->number, devfn, where));
         data = *cfgaddr;
@@ -162,27 +176,39 @@ struct pci_controller nlm_pci_controller = {
         .io_offset      = 0x00000000UL,
 };
 
-static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
+struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
 {
         struct pci_bus *bus, *p;
 
-        /* Find the bridge on bus 0 */
         bus = dev->bus;
-        for (p = bus->parent; p && p->number != 0; p = p->parent)
-                bus = p;
 
-        return p ? bus->self : NULL;
+        if (cpu_is_xlp9xx()) {
+                /* find bus with grand parent number == 0 */
+                for (p = bus->parent; p && p->parent && p->parent->number != 0;
+                                p = p->parent)
+                        bus = p;
+                return (p && p->parent) ? bus->self : NULL;
+        } else {
+                /* Find the bridge on bus 0 */
+                for (p = bus->parent; p && p->number != 0; p = p->parent)
+                        bus = p;
+
+                return p ? bus->self : NULL;
+        }
 }
 
-static inline int nlm_pci_link_to_irq(int link)
+int xlp_socdev_to_node(const struct pci_dev *lnkdev)
 {
-        return PIC_PCIE_LINK_0_IRQ + link;
+        if (cpu_is_xlp9xx())
+                return PCI_FUNC(lnkdev->bus->self->devfn);
+        else
+                return PCI_SLOT(lnkdev->devfn) / 8;
 }
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct pci_dev *lnkdev;
-        int lnkslot, lnkfunc;
+        int lnkfunc, node;
 
         /*
          * For XLP PCIe, there is an IRQ per Link, find out which
@@ -191,9 +217,11 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         lnkdev = xlp_get_pcie_link(dev);
         if (lnkdev == NULL)
                 return 0;
+
         lnkfunc = PCI_FUNC(lnkdev->devfn);
-        lnkslot = PCI_SLOT(lnkdev->devfn);
-        return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc));
+        node = xlp_socdev_to_node(lnkdev);
+
+        return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
 }
 
 /* Do platform specific device initialization at pci_enable_device() time */
@@ -220,17 +248,38 @@ static void xlp_config_pci_bswap(int node, int link)
          *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
          * from the link's address ranges.
          */
-        reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
-        nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
-
-        reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
-        nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
-
-        reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
-        nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
-
-        reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
-        nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_bridge_reg(nbubase,
+                                BRIDGE_9XX_PCIEMEM_BASE0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
+
+                reg = nlm_read_bridge_reg(nbubase,
+                                BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
+                nlm_write_pci_reg(lnkbase,
+                                PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);
+
+                reg = nlm_read_bridge_reg(nbubase,
+                                BRIDGE_9XX_PCIEIO_BASE0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
+
+                reg = nlm_read_bridge_reg(nbubase,
+                                BRIDGE_9XX_PCIEIO_LIMIT0 + link);
+                nlm_write_pci_reg(lnkbase,
+                                PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
+        } else {
+                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
+
+                reg = nlm_read_bridge_reg(nbubase,
+                                        BRIDGE_PCIEMEM_LIMIT0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
+
+                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
+
+                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
+                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
+        }
 }
 #else
 /* Swap configuration not needed in little-endian mode */
@@ -239,7 +288,6 @@ static inline void xlp_config_pci_bswap(int node, int link) {}
 
 static int __init pcibios_init(void)
 {
-        struct nlm_soc_info *nodep;
         uint64_t pciebase;
         int link, n;
         u32 reg;
@@ -253,20 +301,20 @@ static int __init pcibios_init(void)
         ioport_resource.end   = ~0;
 
         for (n = 0; n < NLM_NR_NODES; n++) {
-                nodep = nlm_get_node(n);
-                if (!nodep->coremask)
-                        continue;       /* node does not exist */
+                if (!nlm_node_present(n))
+                        continue;
 
-                for (link = 0; link < 4; link++) {
+                for (link = 0; link < PCIE_NLINKS; link++) {
                         pciebase = nlm_get_pcie_base(n, link);
                         if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
                                 continue;
                         xlp_config_pci_bswap(n, link);
+                        xlp_init_node_msi_irqs(n, link);
 
                         /* put in intpin and irq - u-boot does not */
                         reg = nlm_read_pci_reg(pciebase, 0xf);
-                        reg &= ~0x1fu;
-                        reg |= (1 << 8) | nlm_pci_link_to_irq(link);
+                        reg &= ~0x1ffu;
+                        reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
                         nlm_write_pci_reg(pciebase, 0xf, reg);
                         pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
                 }
diff --git a/arch/mips/pmcs-msp71xx/Kconfig b/arch/mips/pmcs-msp71xx/Kconfig
index 3482b8c8640c..6073ca456d11 100644
--- a/arch/mips/pmcs-msp71xx/Kconfig
+++ b/arch/mips/pmcs-msp71xx/Kconfig
@@ -6,6 +6,7 @@ config PMC_MSP4200_EVAL
         bool "PMC-Sierra MSP4200 Eval Board"
         select IRQ_MSP_SLP
         select HW_HAS_PCI
+        select MIPS_L1_CACHE_SHIFT_4
 
 config PMC_MSP4200_GW
         bool "PMC-Sierra MSP4200 VoIP Gateway"
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 424f03496d14..1bfd1c17b3c2 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -15,6 +15,7 @@ choice
 
         config SOC_RT288X
                 bool "RT288x"
+                select MIPS_L1_CACHE_SHIFT_4
 
         config SOC_RT305X
                 bool "RT305x"
diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c
index cc17566d1934..24bf057a3613 100644
--- a/arch/mips/ralink/cevt-rt3352.c
+++ b/arch/mips/ralink/cevt-rt3352.c
@@ -138,7 +138,7 @@ static void __init ralink_systick_init(struct device_node *np)
 
         clockevents_register_device(&systick.dev);
 
-        pr_info("%s: runing - mult: %d, shift: %d\n",
+        pr_info("%s: running - mult: %d, shift: %d\n",
                         np->name, systick.dev.mult, systick.dev.shift);
 }
 
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
index 202785709441..e38692a44e69 100644
--- a/arch/mips/ralink/timer.c
+++ b/arch/mips/ralink/timer.c
@@ -147,7 +147,7 @@ static int rt_timer_probe(struct platform_device *pdev)
         rt_timer_config(rt, 2);
         rt_timer_enable(rt);
 
-        dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
+        dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
 
         return 0;
 }
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index b952d5b1af86..45fdfbcbd4c6 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -5,7 +5,6 @@
  *
  * Copyright (C) 2001, 2002 Ralf Baechle
  */
-#include <linux/init.h>
 
 #include <asm/page.h>
 #include <asm/sn/addrs.h>
diff --git a/arch/mips/sgi-ip27/ip27-irq-pci.c b/arch/mips/sgi-ip27/ip27-irq-pci.c
index ec22ec5600f3..2a1c40784bd9 100644
--- a/arch/mips/sgi-ip27/ip27-irq-pci.c
+++ b/arch/mips/sgi-ip27/ip27-irq-pci.c
@@ -8,7 +8,6 @@
 
 #undef DEBUG
 
-#include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/errno.h>
 #include <linux/signal.h>
diff --git a/arch/mips/sgi-ip27/ip27-klconfig.c b/arch/mips/sgi-ip27/ip27-klconfig.c
index 7afe14688003..c873d62ff083 100644
--- a/arch/mips/sgi-ip27/ip27-klconfig.c
+++ b/arch/mips/sgi-ip27/ip27-klconfig.c
@@ -2,7 +2,6 @@
  * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index d59b820f528d..20f582a2137a 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -7,7 +7,6 @@
  * Generic XTALK initialization code
  */
 
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/smp.h>
 #include <asm/sn/types.h>
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 8bde9237d13b..a648de1b1096 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -184,13 +184,13 @@ config SMP
         depends on MN10300_PROC_MN2WS0038 || MN10300_PROC_MN2WS0050
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           See also <file:Documentation/x86/i386/IO-APIC.txt>,
diff --git a/arch/mn10300/Makefile b/arch/mn10300/Makefile
index a3d0fef3b126..3f1ea5ddc402 100644
--- a/arch/mn10300/Makefile
+++ b/arch/mn10300/Makefile
@@ -92,14 +92,6 @@ define archhelp
   echo  '* zImage        - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
 endef
 
-# If you make sure the .S files get compiled with debug info,
-# uncomment the following to disable optimisations
-# that are unhelpful whilst debugging.
-ifdef CONFIG_DEBUG_INFO
-#KBUILD_CFLAGS  += -O1
-KBUILD_AFLAGS   += -Wa,--gdwarf2
-endif
-
 #
 # include the appropriate processor- and unit-specific headers
 #
diff --git a/arch/mn10300/include/asm/Kbuild b/arch/mn10300/include/asm/Kbuild
index 032143ec2324..992e989ab785 100644
--- a/arch/mn10300/include/asm/Kbuild
+++ b/arch/mn10300/include/asm/Kbuild
@@ -2,5 +2,6 @@
 generic-y += barrier.h
 generic-y += clkdev.h
 generic-y += exec.h
+generic-y += hash.h
 generic-y += trace_clock.h
 generic-y += preempt.h
diff --git a/arch/mn10300/include/uapi/asm/socket.h b/arch/mn10300/include/uapi/asm/socket.h
index 71dedcae55a6..6aa3ce1854aa 100644
--- a/arch/mn10300/include/uapi/asm/socket.h
+++ b/arch/mn10300/include/uapi/asm/socket.h
@@ -78,4 +78,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index da1951a22907..2e40f1ca8667 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -69,3 +69,4 @@ generic-y += vga.h
 generic-y += word-at-a-time.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index d8a455ede5a7..fec8bf97d806 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -853,37 +853,44 @@ UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 
 /* ========================================================[ return ] === */
 
+_resume_userspace:
+        DISABLE_INTERRUPTS(r3,r4)
+        l.lwz   r4,TI_FLAGS(r10)
+        l.andi  r13,r4,_TIF_WORK_MASK
+        l.sfeqi r13,0
+        l.bf    _restore_all
+         l.nop
+
 _work_pending:
-        /*
-         * if (current_thread_info->flags & _TIF_NEED_RESCHED)
-         *     schedule();
-         */
-        l.lwz   r5,TI_FLAGS(r10)
-        l.andi  r3,r5,_TIF_NEED_RESCHED
-        l.sfnei r3,0
-        l.bnf   _work_notifysig
+        l.lwz   r5,PT_ORIG_GPR11(r1)
+        l.sfltsi r5,0
+        l.bnf   1f
          l.nop
-        l.jal   schedule
+        l.andi  r5,r5,0
+1:
+        l.jal   do_work_pending
+         l.ori  r3,r1,0                 /* pt_regs */
+
+        l.sfeqi r11,0
+        l.bf    _restore_all
          l.nop
-        l.j     _resume_userspace
+        l.sfltsi r11,0
+        l.bnf   1f
          l.nop
-
-/* Handle pending signals and notify-resume requests.
- * do_notify_resume must be passed the latest pushed pt_regs, not
- * necessarily the "userspace" ones.  Also, pt_regs->syscallno
- * must be set so that the syscall restart functionality works.
- */
-_work_notifysig:
-        l.jal   do_notify_resume
-         l.ori  r3,r1,0           /* pt_regs */
-
-_resume_userspace:
-        DISABLE_INTERRUPTS(r3,r4)
-        l.lwz   r3,TI_FLAGS(r10)
-        l.andi  r3,r3,_TIF_WORK_MASK
-        l.sfnei r3,0
-        l.bf    _work_pending
+        l.and   r11,r11,r0
+        l.ori   r11,r11,__NR_restart_syscall
+        l.j     _syscall_check_trace_enter
          l.nop
+1:
+        l.lwz   r11,PT_ORIG_GPR11(r1)
+        /* Restore arg registers */
+        l.lwz   r3,PT_GPR3(r1)
+        l.lwz   r4,PT_GPR4(r1)
+        l.lwz   r5,PT_GPR5(r1)
+        l.lwz   r6,PT_GPR6(r1)
+        l.lwz   r7,PT_GPR7(r1)
+        l.j     _syscall_check_trace_enter
+         l.lwz  r8,PT_GPR8(r1)
 
 _restore_all:
         RESTORE_ALL
diff --git a/arch/openrisc/kernel/signal.c b/arch/openrisc/kernel/signal.c
index ae167f7e081a..66775bc07a8e 100644
--- a/arch/openrisc/kernel/signal.c
+++ b/arch/openrisc/kernel/signal.c
@@ -28,24 +28,24 @@
 #include <linux/tracehook.h>
 
 #include <asm/processor.h>
+#include <asm/syscall.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
 
 #define DEBUG_SIG 0
 
 struct rt_sigframe {
-        struct siginfo *pinfo;
-        void *puc;
         struct siginfo info;
         struct ucontext uc;
         unsigned char retcode[16];      /* trampoline code */
 };
 
-static int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
+static int restore_sigcontext(struct pt_regs *regs,
+                              struct sigcontext __user *sc)
 {
-        unsigned int err = 0;
+        int err = 0;
 
-        /* Alwys make any pending restarted system call return -EINTR */
+        /* Always make any pending restarted system calls return -EINTR */
         current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
         /*
@@ -53,25 +53,21 @@ static int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
          * (sc is already checked for VERIFY_READ since the sigframe was
          *  checked in sys_sigreturn previously)
          */
-        if (__copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long)))
-                goto badframe;
-        if (__copy_from_user(&regs->pc, &sc->regs.pc, sizeof(unsigned long)))
-                goto badframe;
-        if (__copy_from_user(&regs->sr, &sc->regs.sr, sizeof(unsigned long)))
-                goto badframe;
+        err |= __copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long));
+        err |= __copy_from_user(&regs->pc, &sc->regs.pc, sizeof(unsigned long));
+        err |= __copy_from_user(&regs->sr, &sc->regs.sr, sizeof(unsigned long));
 
         /* make sure the SM-bit is cleared so user-mode cannot fool us */
         regs->sr &= ~SPR_SR_SM;
 
+        regs->orig_gpr11 = -1;  /* Avoid syscall restart checks */
+
         /* TODO: the other ports use regs->orig_XX to disable syscall checks
          * after this completes, but we don't use that mechanism. maybe we can
          * use it now ?
          */
 
         return err;
-
-badframe:
-        return 1;
 }
 
 asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs)
@@ -111,21 +107,18 @@ badframe:
  * Set up a signal frame.
  */
 
-static int setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
-                            unsigned long mask)
+static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
 {
         int err = 0;
 
         /* copy the regs */
-
+        /* There should be no need to save callee-saved registers here...
+         * ...but we save them anyway.  Revisit this
+         */
         err |= __copy_to_user(sc->regs.gpr, regs, 32 * sizeof(unsigned long));
         err |= __copy_to_user(&sc->regs.pc, &regs->pc, sizeof(unsigned long));
         err |= __copy_to_user(&sc->regs.sr, &regs->sr, sizeof(unsigned long));
 
-        /* then some other stuff */
-
-        err |= __put_user(mask, &sc->oldmask);
-
         return err;
 }
 
@@ -173,55 +166,53 @@ static inline void __user *get_sigframe(struct k_sigaction *ka,
  * trampoline which performs the syscall sigreturn, or a provided
  * user-mode trampoline.
  */
-static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                          sigset_t *set, struct pt_regs *regs)
+static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
+                          struct pt_regs *regs)
 {
         struct rt_sigframe *frame;
         unsigned long return_ip;
         int err = 0;
 
-        frame = get_sigframe(ka, regs, sizeof(*frame));
+        frame = get_sigframe(&ksig->ka, regs, sizeof(*frame));
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
-                goto give_sigsegv;
+                return -EFAULT;
 
-        err |= __put_user(&frame->info, &frame->pinfo);
-        err |= __put_user(&frame->uc, &frame->puc);
+        /* Create siginfo.  */
+        if (ksig->ka.sa.sa_flags & SA_SIGINFO)
+                err |= copy_siginfo_to_user(&frame->info, &ksig->info);
 
-        if (ka->sa.sa_flags & SA_SIGINFO)
-                err |= copy_siginfo_to_user(&frame->info, info);
-        if (err)
-                goto give_sigsegv;
-
-        /* Clear all the bits of the ucontext we don't use.  */
-        err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
+        /* Create the ucontext.  */
         err |= __put_user(0, &frame->uc.uc_flags);
         err |= __put_user(NULL, &frame->uc.uc_link);
         err |= __save_altstack(&frame->uc.uc_stack, regs->sp);
-        err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
+        err |= setup_sigcontext(regs, &frame->uc.uc_mcontext);
 
         err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
 
         if (err)
-                goto give_sigsegv;
+                return -EFAULT;
 
         /* trampoline - the desired return ip is the retcode itself */
         return_ip = (unsigned long)&frame->retcode;
-        /* This is l.ori r11,r0,__NR_sigreturn, l.sys 1 */
-        err |= __put_user(0xa960, (short *)(frame->retcode + 0));
-        err |= __put_user(__NR_rt_sigreturn, (short *)(frame->retcode + 2));
+        /* This is:
+                l.ori r11,r0,__NR_sigreturn
+                l.sys 1
+         */
+        err |= __put_user(0xa960,             (short *)(frame->retcode + 0));
+        err |= __put_user(__NR_rt_sigreturn,  (short *)(frame->retcode + 2));
         err |= __put_user(0x20000001, (unsigned long *)(frame->retcode + 4));
         err |= __put_user(0x15000000, (unsigned long *)(frame->retcode + 8));
 
         if (err)
-                goto give_sigsegv;
+                return -EFAULT;
 
         /* TODO what is the current->exec_domain stuff and invmap ? */
 
         /* Set up registers for signal handler */
-        regs->pc = (unsigned long)ka->sa.sa_handler; /* what we enter NOW */
+        regs->pc = (unsigned long)ksig->ka.sa.sa_handler; /* what we enter NOW */
         regs->gpr[9] = (unsigned long)return_ip;     /* what we enter LATER */
-        regs->gpr[3] = (unsigned long)sig;           /* arg 1: signo */
+        regs->gpr[3] = (unsigned long)ksig->sig;           /* arg 1: signo */
         regs->gpr[4] = (unsigned long)&frame->info;  /* arg 2: (siginfo_t*) */
         regs->gpr[5] = (unsigned long)&frame->uc;    /* arg 3: ucontext */
 
@@ -229,25 +220,16 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->sp = (unsigned long)frame;
 
         return 0;
-
-give_sigsegv:
-        force_sigsegv(sig, current);
-        return -EFAULT;
 }
 
 static inline void
-handle_signal(unsigned long sig,
-              siginfo_t *info, struct k_sigaction *ka,
-              struct pt_regs *regs)
+handle_signal(struct ksignal *ksig, struct pt_regs *regs)
 {
         int ret;
 
-        ret = setup_rt_frame(sig, ka, info, sigmask_to_save(), regs);
-        if (ret)
-                return;
+        ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
 
-        signal_delivered(sig, info, ka, regs,
-                                 test_thread_flag(TIF_SINGLESTEP));
+        signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
 }
 
 /*
@@ -262,82 +244,99 @@ handle_signal(unsigned long sig,
  * mode below.
  */
 
-void do_signal(struct pt_regs *regs)
+int do_signal(struct pt_regs *regs, int syscall)
 {
-        siginfo_t info;
-        int signr;
-        struct k_sigaction ka;
-
-        /*
-         * We want the common case to go fast, which
-         * is why we may in certain cases get here from
-         * kernel mode. Just return without doing anything
-         * if so.
-         */
-        if (!user_mode(regs))
-                return;
-
-        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
-
-        /* If we are coming out of a syscall then we need
-         * to check if the syscall was interrupted and wants to be
-         * restarted after handling the signal.  If so, the original
-         * syscall number is put back into r11 and the PC rewound to
-         * point at the l.sys instruction that resulted in the
-         * original syscall.  Syscall results other than the four
-         * below mean that the syscall executed to completion and no
-         * restart is necessary.
-         */
-        if (regs->orig_gpr11) {
-                int restart = 0;
-
-                switch (regs->gpr[11]) {
+        struct ksignal ksig;
+        unsigned long continue_addr = 0;
+        unsigned long restart_addr = 0;
+        unsigned long retval = 0;
+        int restart = 0;
+
+        if (syscall) {
+                continue_addr = regs->pc;
+                restart_addr = continue_addr - 4;
+                retval = regs->gpr[11];
+
+                /*
+                 * Setup syscall restart here so that a debugger will
+                 * see the already changed PC.
+                 */
+                switch (retval) {
                 case -ERESTART_RESTARTBLOCK:
+                        restart = -2;
+                        /* Fall through */
                 case -ERESTARTNOHAND:
-                        /* Restart if there is no signal handler */
-                        restart = (signr <= 0);
-                        break;
                 case -ERESTARTSYS:
-                        /* Restart if there no signal handler or
-                         * SA_RESTART flag is set */
-                        restart = (signr <= 0 || (ka.sa.sa_flags & SA_RESTART));
-                        break;
                 case -ERESTARTNOINTR:
-                        /* Always restart */
-                        restart = 1;
+                        restart++;
+                        regs->gpr[11] = regs->orig_gpr11;
+                        regs->pc = restart_addr;
                         break;
                 }
-
-                if (restart) {
-                        if (regs->gpr[11] == -ERESTART_RESTARTBLOCK)
-                                regs->gpr[11] = __NR_restart_syscall;
-                        else
-                                regs->gpr[11] = regs->orig_gpr11;
-                        regs->pc -= 4;
-                } else {
-                        regs->gpr[11] = -EINTR;
-                }
         }
 
-        if (signr <= 0) {
-                /* no signal to deliver so we just put the saved sigmask
-                 * back */
+        /*
+         * Get the signal to deliver.  During the call to get_signal the
+         * debugger may change all our registers so we may need to revert
+         * the decision to restart the syscall; specifically, if the PC is
+         * changed, don't restart the syscall.
+         */
+        if (get_signal(&ksig)) {
+                if (unlikely(restart) && regs->pc == restart_addr) {
+                        if (retval == -ERESTARTNOHAND ||
+                            retval == -ERESTART_RESTARTBLOCK
+                            || (retval == -ERESTARTSYS
+                                && !(ksig.ka.sa.sa_flags & SA_RESTART))) {
+                                /* No automatic restart */
+                                regs->gpr[11] = -EINTR;
+                                regs->pc = continue_addr;
+                        }
+                }
+                handle_signal(&ksig, regs);
+        } else {
+                /* no handler */
                 restore_saved_sigmask();
-        } else {                /* signr > 0 */
-                /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &info, &ka, regs);
+                /*
+                 * Restore pt_regs PC as syscall restart will be handled by
+                 * kernel without return to userspace
+                 */
+                if (unlikely(restart) && regs->pc == restart_addr) {
+                        regs->pc = continue_addr;
+                        return restart;
+                }
         }
 
-        return;
+        return 0;
 }
 
-asmlinkage void do_notify_resume(struct pt_regs *regs)
+asmlinkage int
+do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
-        if (current_thread_info()->flags & _TIF_SIGPENDING)
-                do_signal(regs);
-
-        if (current_thread_info()->flags & _TIF_NOTIFY_RESUME) {
-                clear_thread_flag(TIF_NOTIFY_RESUME);
-                tracehook_notify_resume(regs);
-        }
+        do {
+                if (likely(thread_flags & _TIF_NEED_RESCHED)) {
+                        schedule();
+                } else {
+                        if (unlikely(!user_mode(regs)))
+                                return 0;
+                        local_irq_enable();
+                        if (thread_flags & _TIF_SIGPENDING) {
+                                int restart = do_signal(regs, syscall);
+                                if (unlikely(restart)) {
+                                        /*
+                                         * Restart without handlers.
+                                         * Deal with it without leaving
+                                         * the kernel space.
+                                         */
+                                        return restart;
+                                }
+                                syscall = 0;
+                        } else {
+                                clear_thread_flag(TIF_NOTIFY_RESUME);
+                                tracehook_notify_resume(regs);
+                        }
+                }
+                local_irq_disable();
+                thread_flags = current_thread_info()->flags;
+        } while (thread_flags & _TIF_WORK_MASK);
+        return 0;
 }
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index b5f1858baf33..bb2a8ec440e7 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -229,13 +229,13 @@ config SMP
         bool "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           See also <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO
diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild
index 34b0be4ca52d..752c981bc3c7 100644
--- a/arch/parisc/include/asm/Kbuild
+++ b/arch/parisc/include/asm/Kbuild
@@ -6,3 +6,4 @@ generic-y += word-at-a-time.h auxvec.h user.h cputime.h emergency-restart.h \
           poll.h xor.h clkdev.h exec.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 2f9b751878ba..de65f66ea64e 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -132,7 +132,6 @@ void mark_rodata_ro(void);
 static inline void *kmap(struct page *page)
 {
         might_sleep();
-        flush_dcache_page(page);
         return page_address(page);
 }
 
@@ -144,7 +143,6 @@ static inline void kunmap(struct page *page)
 static inline void *kmap_atomic(struct page *page)
 {
         pagefault_disable();
-        flush_dcache_page(page);
         return page_address(page);
 }
 
diff --git a/arch/parisc/include/asm/elf.h b/arch/parisc/include/asm/elf.h
index ad2b50397894..3391d061eccc 100644
--- a/arch/parisc/include/asm/elf.h
+++ b/arch/parisc/include/asm/elf.h
@@ -348,4 +348,8 @@ struct pt_regs;	/* forward declaration... */
 
 #define ELF_HWCAP       0
 
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif
diff --git a/arch/parisc/include/asm/page.h b/arch/parisc/include/asm/page.h
index c53fc63149e8..637fe031aa84 100644
--- a/arch/parisc/include/asm/page.h
+++ b/arch/parisc/include/asm/page.h
@@ -29,7 +29,8 @@ struct page;
 void clear_page_asm(void *page);
 void copy_page_asm(void *to, void *from);
 #define clear_user_page(vto, vaddr, page) clear_page_asm(vto)
-#define copy_user_page(vto, vfrom, vaddr, page) copy_page_asm(vto, vfrom)
+void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+                        struct page *pg);
 
 /* #define CONFIG_PARISC_TMPALIAS */
 
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 34899b5d959a..22b89d1edba7 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -511,6 +511,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 /* We provide our own get_unmapped_area to provide cache coherency */
 
 #define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index cc2290a3cace..198a86feb574 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -30,6 +30,8 @@
 #endif
 #define current_text_addr() ({ void *pc; current_ia(pc); pc; })
 
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
 #define TASK_SIZE_OF(tsk)       ((tsk)->thread.task_size)
 #define TASK_SIZE               TASK_SIZE_OF(current)
 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index d5f97ea3a4e1..4b9b10ce1f9d 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -76,6 +76,16 @@ struct thread_info {
 #define _TIF_SYSCALL_TRACE_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
                                  _TIF_BLOCKSTEP | _TIF_SYSCALL_AUDIT)
 
+#ifdef CONFIG_64BIT
+# ifdef CONFIG_COMPAT
+#  define is_32bit_task()       (test_thread_flag(TIF_32BIT))
+# else
+#  define is_32bit_task()       (0)
+# endif
+#else
+# define is_32bit_task()        (1)
+#endif
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_PARISC_THREAD_INFO_H */
diff --git a/arch/parisc/include/uapi/asm/errno.h b/arch/parisc/include/uapi/asm/errno.h
index f3a8aa554841..c0ae62520d15 100644
--- a/arch/parisc/include/uapi/asm/errno.h
+++ b/arch/parisc/include/uapi/asm/errno.h
@@ -106,7 +106,7 @@
 
 #define EALREADY        244     /* Operation already in progress */
 #define EINPROGRESS     245     /* Operation now in progress */
-#define EWOULDBLOCK     246     /* Operation would block (Linux returns EAGAIN) */
+#define EWOULDBLOCK     EAGAIN  /* Operation would block (Not HPUX compliant) */
 #define ENOTEMPTY       247     /* Directory not empty */
 #define ENAMETOOLONG    248     /* File name too long */
 #define ELOOP           249     /* Too many symbolic links encountered */
diff --git a/arch/parisc/include/uapi/asm/socket.h b/arch/parisc/include/uapi/asm/socket.h
index 70b3674dac4e..fe35ceacf0e7 100644
--- a/arch/parisc/include/uapi/asm/socket.h
+++ b/arch/parisc/include/uapi/asm/socket.h
@@ -77,4 +77,6 @@
 
 #define SO_MAX_PACING_RATE      0x4028
 
+#define SO_BPF_EXTENSIONS       0x4029
+
 #endif /* _UAPI_ASM_SOCKET_H */
diff --git a/arch/parisc/include/uapi/asm/stat.h b/arch/parisc/include/uapi/asm/stat.h
index d76fbda5d62c..b606b366d0a7 100644
--- a/arch/parisc/include/uapi/asm/stat.h
+++ b/arch/parisc/include/uapi/asm/stat.h
@@ -5,67 +5,65 @@
 
 struct stat {
         unsigned int    st_dev;         /* dev_t is 32 bits on parisc */
-        ino_t           st_ino;         /* 32 bits */
-        mode_t          st_mode;        /* 16 bits */
+        unsigned int    st_ino;         /* 32 bits */
+        unsigned short  st_mode;        /* 16 bits */
         unsigned short  st_nlink;       /* 16 bits */
         unsigned short  st_reserved1;   /* old st_uid */
         unsigned short  st_reserved2;   /* old st_gid */
         unsigned int    st_rdev;
-        off_t           st_size;
-        time_t          st_atime;
+        signed int      st_size;
+        signed int      st_atime;
         unsigned int    st_atime_nsec;
-        time_t          st_mtime;
+        signed int      st_mtime;
         unsigned int    st_mtime_nsec;
-        time_t          st_ctime;
+        signed int      st_ctime;
         unsigned int    st_ctime_nsec;
         int             st_blksize;
         int             st_blocks;
         unsigned int    __unused1;      /* ACL stuff */
         unsigned int    __unused2;      /* network */
-        ino_t           __unused3;      /* network */
+        unsigned int    __unused3;      /* network */
         unsigned int    __unused4;      /* cnodes */
         unsigned short  __unused5;      /* netsite */
         short           st_fstype;
         unsigned int    st_realdev;
         unsigned short  st_basemode;
         unsigned short  st_spareshort;
-        uid_t           st_uid;
-        gid_t           st_gid;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
         unsigned int    st_spare4[3];
 };
 
 #define STAT_HAVE_NSEC
 
-typedef __kernel_off64_t        off64_t;
-
 struct hpux_stat64 {
         unsigned int    st_dev;         /* dev_t is 32 bits on parisc */
-        ino_t           st_ino;         /* 32 bits */
-        mode_t          st_mode;        /* 16 bits */
+        unsigned int    st_ino;         /* 32 bits */
+        unsigned short  st_mode;        /* 16 bits */
         unsigned short  st_nlink;       /* 16 bits */
         unsigned short  st_reserved1;   /* old st_uid */
         unsigned short  st_reserved2;   /* old st_gid */
         unsigned int    st_rdev;
-        off64_t         st_size;
-        time_t          st_atime;
+        signed long long st_size;
+        signed int      st_atime;
         unsigned int    st_spare1;
-        time_t          st_mtime;
+        signed int      st_mtime;
         unsigned int    st_spare2;
-        time_t          st_ctime;
+        signed int      st_ctime;
         unsigned int    st_spare3;
         int             st_blksize;
-        __u64           st_blocks;
+        unsigned long long st_blocks;
         unsigned int    __unused1;      /* ACL stuff */
         unsigned int    __unused2;      /* network */
-        ino_t           __unused3;      /* network */
+        unsigned int    __unused3;      /* network */
         unsigned int    __unused4;      /* cnodes */
         unsigned short  __unused5;      /* netsite */
         short           st_fstype;
         unsigned int    st_realdev;
         unsigned short  st_basemode;
         unsigned short  st_spareshort;
-        uid_t           st_uid;
-        gid_t           st_gid;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
         unsigned int    st_spare4[3];
 };
 
diff --git a/arch/parisc/include/uapi/asm/unistd.h b/arch/parisc/include/uapi/asm/unistd.h
index 2c8b9bde18eb..42706794a36f 100644
--- a/arch/parisc/include/uapi/asm/unistd.h
+++ b/arch/parisc/include/uapi/asm/unistd.h
@@ -826,8 +826,10 @@
 #define __NR_process_vm_writev  (__NR_Linux + 331)
 #define __NR_kcmp               (__NR_Linux + 332)
 #define __NR_finit_module       (__NR_Linux + 333)
+#define __NR_sched_setattr      (__NR_Linux + 334)
+#define __NR_sched_getattr      (__NR_Linux + 335)
 
-#define __NR_Linux_syscalls     (__NR_finit_module + 1)
+#define __NR_Linux_syscalls     (__NR_sched_getattr + 1)
 
 
 #define __IGNORE_select         /* newselect */
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index a72545554a31..ac87a40502e6 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -388,6 +388,20 @@ void flush_kernel_dcache_page_addr(void *addr)
 }
 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 
+void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+        struct page *pg)
+{
+       /* Copy using kernel mapping.  No coherency is needed (all in
+          kunmap) for the `to' page.  However, the `from' page needs to
+          be flushed through a mapping equivalent to the user mapping
+          before it can be accessed through the kernel mapping. */
+        preempt_disable();
+        flush_dcache_page_asm(__pa(vfrom), vaddr);
+        preempt_enable();
+        copy_page_asm(vto, vfrom);
+}
+EXPORT_SYMBOL(copy_user_page);
+
 void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
 {
         unsigned long flags;
diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c
index 14285caec71a..dba508fe1683 100644
--- a/arch/parisc/kernel/drivers.c
+++ b/arch/parisc/kernel/drivers.c
@@ -282,18 +282,6 @@ find_pa_parent_type(const struct parisc_device *padev, int type)
         return NULL;
 }
 
-#ifdef CONFIG_PCI
-static inline int is_pci_dev(struct device *dev)
-{
-        return dev->bus == &pci_bus_type;
-}
-#else
-static inline int is_pci_dev(struct device *dev)
-{
-        return 0;
-}
-#endif
-
 /*
  * get_node_path fills in @path with the firmware path to the device.
  * Note that if @node is a parisc device, we don't fill in the 'mod' field.
@@ -306,7 +294,7 @@ static void get_node_path(struct device *dev, struct hardware_path *path)
         int i = 5;
         memset(&path->bc, -1, 6);
 
-        if (is_pci_dev(dev)) {
+        if (dev_is_pci(dev)) {
                 unsigned int devfn = to_pci_dev(dev)->devfn;
                 path->mod = PCI_FUNC(devfn);
                 path->bc[i--] = PCI_SLOT(devfn);
@@ -314,7 +302,7 @@ static void get_node_path(struct device *dev, struct hardware_path *path)
         }
 
         while (dev != &root) {
-                if (is_pci_dev(dev)) {
+                if (dev_is_pci(dev)) {
                         unsigned int devfn = to_pci_dev(dev)->devfn;
                         path->bc[i--] = PCI_SLOT(devfn) | (PCI_FUNC(devfn)<< 5);
                 } else if (dev->bus == &parisc_bus_type) {
@@ -695,7 +683,7 @@ static int check_parent(struct device * dev, void * data)
                 if (dev->bus == &parisc_bus_type) {
                         if (match_parisc_device(dev, d->index, d->modpath))
                                 d->dev = dev;
-                } else if (is_pci_dev(dev)) {
+                } else if (dev_is_pci(dev)) {
                         if (match_pci_device(dev, d->index, d->modpath))
                                 d->dev = dev;
                 } else if (dev->bus == NULL) {
@@ -753,7 +741,7 @@ struct device *hwpath_to_device(struct hardware_path *modpath)
                 if (!parent)
                         return NULL;
         }
-        if (is_pci_dev(parent)) /* pci devices already parse MOD */
+        if (dev_is_pci(parent)) /* pci devices already parse MOD */
                 return parent;
         else
                 return parse_tree_node(parent, 6, modpath);
@@ -772,7 +760,7 @@ void device_to_hwpath(struct device *dev, struct hardware_path *path)
                 padev = to_parisc_device(dev);
                 get_node_path(dev->parent, path);
                 path->mod = padev->hw_path;
-        } else if (is_pci_dev(dev)) {
+        } else if (dev_is_pci(dev)) {
                 get_node_path(dev, path);
         }
 }
diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c
index 55f92b614182..0bbbf0d3f608 100644
--- a/arch/parisc/kernel/process.c
+++ b/arch/parisc/kernel/process.c
@@ -13,7 +13,7 @@
  *    Copyright (C) 2000 Grant Grundler <grundler with parisc-linux.org>
  *    Copyright (C) 2001 Alan Modra <amodra at parisc-linux.org>
  *    Copyright (C) 2001-2002 Ryan Bradetich <rbrad at parisc-linux.org>
- *    Copyright (C) 2001-2007 Helge Deller <deller at parisc-linux.org>
+ *    Copyright (C) 2001-2014 Helge Deller <deller@gmx.de>
  *    Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
  *
  *
@@ -49,6 +49,7 @@
 #include <linux/kallsyms.h>
 #include <linux/uaccess.h>
 #include <linux/rcupdate.h>
+#include <linux/random.h>
 
 #include <asm/io.h>
 #include <asm/asm-offsets.h>
@@ -286,3 +287,21 @@ void *dereference_function_descriptor(void *ptr)
         return ptr;
 }
 #endif
+
+static inline unsigned long brk_rnd(void)
+{
+        /* 8MB for 32bit, 1GB for 64bit */
+        if (is_32bit_task())
+                return (get_random_int() & 0x7ffUL) << PAGE_SHIFT;
+        else
+                return (get_random_int() & 0x3ffffUL) << PAGE_SHIFT;
+}
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+        unsigned long ret = PAGE_ALIGN(mm->brk + brk_rnd());
+
+        if (ret < mm->brk)
+                return mm->brk;
+        return ret;
+}
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index 0d3a9d4927b5..b7cadc4a06cd 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -5,6 +5,7 @@
  *    Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
  *    Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
  *    Copyright (C) 2001 Thomas Bogendoerfer <tsbogend at parisc-linux.org>
+ *    Copyright (C) 1999-2014 Helge Deller <deller@gmx.de>
  *
  *
  *    This program is free software; you can redistribute it and/or modify
@@ -23,6 +24,7 @@
  */
 
 #include <asm/uaccess.h>
+#include <asm/elf.h>
 #include <linux/file.h>
 #include <linux/fs.h>
 #include <linux/linkage.h>
@@ -32,78 +34,230 @@
 #include <linux/syscalls.h>
 #include <linux/utsname.h>
 #include <linux/personality.h>
+#include <linux/random.h>
 
-static unsigned long get_unshared_area(unsigned long addr, unsigned long len)
+/* we construct an artificial offset for the mapping based on the physical
+ * address of the kernel mapping variable */
+#define GET_LAST_MMAP(filp)             \
+        (filp ? ((unsigned long) filp->f_mapping) >> 8 : 0UL)
+#define SET_LAST_MMAP(filp, val)        \
+         { /* nothing */ }
+
+static int get_offset(unsigned int last_mmap)
 {
-        struct vm_unmapped_area_info info;
+        return (last_mmap & (SHMLBA-1)) >> PAGE_SHIFT;
+}
 
-        info.flags = 0;
-        info.length = len;
-        info.low_limit = PAGE_ALIGN(addr);
-        info.high_limit = TASK_SIZE;
-        info.align_mask = 0;
-        info.align_offset = 0;
-        return vm_unmapped_area(&info);
+static unsigned long shared_align_offset(unsigned int last_mmap,
+                                         unsigned long pgoff)
+{
+        return (get_offset(last_mmap) + pgoff) << PAGE_SHIFT;
 }
 
-/*
- * We need to know the offset to use.  Old scheme was to look for
- * existing mapping and use the same offset.  New scheme is to use the
- * address of the kernel data structure as the seed for the offset.
- * We'll see how that works...
- *
- * The mapping is cacheline aligned, so there's no information in the bottom
- * few bits of the address.  We're looking for 10 bits (4MB / 4k), so let's
- * drop the bottom 8 bits and use bits 8-17.  
- */
-static int get_offset(struct address_space *mapping)
+static inline unsigned long COLOR_ALIGN(unsigned long addr,
+                         unsigned int last_mmap, unsigned long pgoff)
 {
-        return (unsigned long) mapping >> 8;
+        unsigned long base = (addr+SHMLBA-1) & ~(SHMLBA-1);
+        unsigned long off  = (SHMLBA-1) &
+                (shared_align_offset(last_mmap, pgoff) << PAGE_SHIFT);
+
+        return base + off;
 }
 
-static unsigned long shared_align_offset(struct file *filp, unsigned long pgoff)
+/*
+ * Top of mmap area (just below the process stack).
+ */
+
+static unsigned long mmap_upper_limit(void)
 {
-        struct address_space *mapping = filp ? filp->f_mapping : NULL;
+        unsigned long stack_base;
 
-        return (get_offset(mapping) + pgoff) << PAGE_SHIFT;
+        /* Limit stack size to 1GB - see setup_arg_pages() in fs/exec.c */
+        stack_base = rlimit_max(RLIMIT_STACK);
+        if (stack_base > (1 << 30))
+                stack_base = 1 << 30;
+
+        return PAGE_ALIGN(STACK_TOP - stack_base);
 }
 
-static unsigned long get_shared_area(struct file *filp, unsigned long addr,
-                unsigned long len, unsigned long pgoff)
+
+unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
+                unsigned long len, unsigned long pgoff, unsigned long flags)
 {
+        struct mm_struct *mm = current->mm;
+        struct vm_area_struct *vma;
+        unsigned long task_size = TASK_SIZE;
+        int do_color_align, last_mmap;
         struct vm_unmapped_area_info info;
 
+        if (len > task_size)
+                return -ENOMEM;
+
+        do_color_align = 0;
+        if (filp || (flags & MAP_SHARED))
+                do_color_align = 1;
+        last_mmap = GET_LAST_MMAP(filp);
+
+        if (flags & MAP_FIXED) {
+                if ((flags & MAP_SHARED) && last_mmap &&
+                    (addr - shared_align_offset(last_mmap, pgoff))
+                                & (SHMLBA - 1))
+                        return -EINVAL;
+                goto found_addr;
+        }
+
+        if (addr) {
+                if (do_color_align && last_mmap)
+                        addr = COLOR_ALIGN(addr, last_mmap, pgoff);
+                else
+                        addr = PAGE_ALIGN(addr);
+
+                vma = find_vma(mm, addr);
+                if (task_size - len >= addr &&
+                    (!vma || addr + len <= vma->vm_start))
+                        goto found_addr;
+        }
+
         info.flags = 0;
         info.length = len;
-        info.low_limit = PAGE_ALIGN(addr);
-        info.high_limit = TASK_SIZE;
-        info.align_mask = PAGE_MASK & (SHMLBA - 1);
-        info.align_offset = shared_align_offset(filp, pgoff);
-        return vm_unmapped_area(&info);
+        info.low_limit = mm->mmap_legacy_base;
+        info.high_limit = mmap_upper_limit();
+        info.align_mask = last_mmap ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+        info.align_offset = shared_align_offset(last_mmap, pgoff);
+        addr = vm_unmapped_area(&info);
+
+found_addr:
+        if (do_color_align && !last_mmap && !(addr & ~PAGE_MASK))
+                SET_LAST_MMAP(filp, addr - (pgoff << PAGE_SHIFT));
+
+        return addr;
 }
 
-unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
-                unsigned long len, unsigned long pgoff, unsigned long flags)
+unsigned long
+arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
+                          const unsigned long len, const unsigned long pgoff,
+                          const unsigned long flags)
 {
+        struct vm_area_struct *vma;
+        struct mm_struct *mm = current->mm;
+        unsigned long addr = addr0;
+        int do_color_align, last_mmap;
+        struct vm_unmapped_area_info info;
+
+#ifdef CONFIG_64BIT
+        /* This should only ever run for 32-bit processes.  */
+        BUG_ON(!test_thread_flag(TIF_32BIT));
+#endif
+
+        /* requested length too big for entire address space */
         if (len > TASK_SIZE)
                 return -ENOMEM;
+
+        do_color_align = 0;
+        if (filp || (flags & MAP_SHARED))
+                do_color_align = 1;
+        last_mmap = GET_LAST_MMAP(filp);
+
         if (flags & MAP_FIXED) {
-                if ((flags & MAP_SHARED) &&
-                    (addr - shared_align_offset(filp, pgoff)) & (SHMLBA - 1))
+                if ((flags & MAP_SHARED) && last_mmap &&
+                    (addr - shared_align_offset(last_mmap, pgoff))
+                        & (SHMLBA - 1))
                         return -EINVAL;
-                return addr;
+                goto found_addr;
         }
-        if (!addr)
-                addr = TASK_UNMAPPED_BASE;
 
-        if (filp || (flags & MAP_SHARED))
-                addr = get_shared_area(filp, addr, len, pgoff);
-        else
-                addr = get_unshared_area(addr, len);
+        /* requesting a specific address */
+        if (addr) {
+                if (do_color_align && last_mmap)
+                        addr = COLOR_ALIGN(addr, last_mmap, pgoff);
+                else
+                        addr = PAGE_ALIGN(addr);
+                vma = find_vma(mm, addr);
+                if (TASK_SIZE - len >= addr &&
+                    (!vma || addr + len <= vma->vm_start))
+                        goto found_addr;
+        }
+
+        info.flags = VM_UNMAPPED_AREA_TOPDOWN;
+        info.length = len;
+        info.low_limit = PAGE_SIZE;
+        info.high_limit = mm->mmap_base;
+        info.align_mask = last_mmap ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+        info.align_offset = shared_align_offset(last_mmap, pgoff);
+        addr = vm_unmapped_area(&info);
+        if (!(addr & ~PAGE_MASK))
+                goto found_addr;
+        VM_BUG_ON(addr != -ENOMEM);
+
+        /*
+         * A failed mmap() very likely causes application failure,
+         * so fall back to the bottom-up function here. This scenario
+         * can happen with large stack limits and large mmap()
+         * allocations.
+         */
+        return arch_get_unmapped_area(filp, addr0, len, pgoff, flags);
+
+found_addr:
+        if (do_color_align && !last_mmap && !(addr & ~PAGE_MASK))
+                SET_LAST_MMAP(filp, addr - (pgoff << PAGE_SHIFT));
 
         return addr;
 }
 
+static int mmap_is_legacy(void)
+{
+        if (current->personality & ADDR_COMPAT_LAYOUT)
+                return 1;
+
+        /* parisc stack always grows up - so a unlimited stack should
+         * not be an indicator to use the legacy memory layout.
+         * if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
+         *      return 1;
+         */
+
+        return sysctl_legacy_va_layout;
+}
+
+static unsigned long mmap_rnd(void)
+{
+        unsigned long rnd = 0;
+
+        /*
+        *  8 bits of randomness in 32bit mmaps, 20 address space bits
+        * 28 bits of randomness in 64bit mmaps, 40 address space bits
+        */
+        if (current->flags & PF_RANDOMIZE) {
+                if (is_32bit_task())
+                        rnd = get_random_int() % (1<<8);
+                else
+                        rnd = get_random_int() % (1<<28);
+        }
+        return rnd << PAGE_SHIFT;
+}
+
+static unsigned long mmap_legacy_base(void)
+{
+        return TASK_UNMAPPED_BASE + mmap_rnd();
+}
+
+/*
+ * This function, called very early during the creation of a new
+ * process VM image, sets up which VM layout function to use:
+ */
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+        mm->mmap_legacy_base = mmap_legacy_base();
+        mm->mmap_base = mmap_upper_limit();
+
+        if (mmap_is_legacy()) {
+                mm->mmap_base = mm->mmap_legacy_base;
+                mm->get_unmapped_area = arch_get_unmapped_area;
+        } else {
+                mm->get_unmapped_area = arch_get_unmapped_area_topdown;
+        }
+}
+
+
 asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags, unsigned long fd,
         unsigned long pgoff)
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index 0c9107285e66..8fa3fbb3e4d3 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -429,6 +429,8 @@
         ENTRY_COMP(process_vm_writev)
         ENTRY_SAME(kcmp)
         ENTRY_SAME(finit_module)
+        ENTRY_SAME(sched_setattr)
+        ENTRY_SAME(sched_getattr)       /* 335 */
 
         /* Nothing yet */
 
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 96f8168cf4ec..ae085ad0fba0 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -645,55 +645,30 @@ EXPORT_SYMBOL(empty_zero_page);
 
 void show_mem(unsigned int filter)
 {
-        int i,free = 0,total = 0,reserved = 0;
-        int shared = 0, cached = 0;
+        int total = 0,reserved = 0;
+        pg_data_t *pgdat;
 
         printk(KERN_INFO "Mem-info:\n");
         show_free_areas(filter);
-        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
-                return;
-#ifndef CONFIG_DISCONTIGMEM
-        i = max_mapnr;
-        while (i-- > 0) {
-                total++;
-                if (PageReserved(mem_map+i))
-                        reserved++;
-                else if (PageSwapCache(mem_map+i))
-                        cached++;
-                else if (!page_count(&mem_map[i]))
-                        free++;
-                else
-                        shared += page_count(&mem_map[i]) - 1;
-        }
-#else
-        for (i = 0; i < npmem_ranges; i++) {
-                int j;
 
-                for (j = node_start_pfn(i); j < node_end_pfn(i); j++) {
-                        struct page *p;
-                        unsigned long flags;
-
-                        pgdat_resize_lock(NODE_DATA(i), &flags);
-                        p = nid_page_nr(i, j) - node_start_pfn(i);
-
-                        total++;
-                        if (PageReserved(p))
-                                reserved++;
-                        else if (PageSwapCache(p))
-                                cached++;
-                        else if (!page_count(p))
-                                free++;
-                        else
-                                shared += page_count(p) - 1;
-                        pgdat_resize_unlock(NODE_DATA(i), &flags);
-                }
+        for_each_online_pgdat(pgdat) {
+                unsigned long flags;
+                int zoneid;
+
+                pgdat_resize_lock(pgdat, &flags);
+                for (zoneid = 0; zoneid < MAX_NR_ZONES; zoneid++) {
+                        struct zone *zone = &pgdat->node_zones[zoneid];
+                        if (!populated_zone(zone))
+                                continue;
+
+                        total += zone->present_pages;
+                        reserved = zone->present_pages - zone->managed_pages;
+                }
+                pgdat_resize_unlock(pgdat, &flags);
         }
-#endif
+
         printk(KERN_INFO "%d pages of RAM\n", total);
         printk(KERN_INFO "%d reserved pages\n", reserved);
-        printk(KERN_INFO "%d pages shared\n", shared);
-        printk(KERN_INFO "%d pages swap cached\n", cached);
-
 
 #ifdef CONFIG_DISCONTIGMEM
         {
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b2be8e8cb5c7..957bf344c0f5 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -86,6 +86,7 @@ config PPC
         bool
         default y
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select BINFMT_ELF
         select OF
         select OF_EARLY_FLATTREE
@@ -139,6 +140,7 @@ config PPC
         select OLD_SIGACTION if PPC32
         select HAVE_DEBUG_STACKOVERFLOW
         select HAVE_IRQ_EXIT_ON_IRQ_STACK
+        select ARCH_USE_CMPXCHG_LOCKREF if PPC64
 
 config GENERIC_CSUM
         def_bool CPU_LITTLE_ENDIAN
@@ -213,9 +215,6 @@ config DEFAULT_UIMAGE
           Used to allow a board to specify it wants a uImage built by default
         default n
 
-config REDBOOT
-        bool
-
 config ARCH_HIBERNATION_POSSIBLE
         bool
         default y
@@ -343,6 +342,8 @@ config PPC_TRANSACTIONAL_MEM
        bool "Transactional Memory support for POWERPC"
        depends on PPC_BOOK3S_64
        depends on SMP
+       select ALTIVEC
+       select VSX
        default n
        ---help---
          Support user-mode Transactional Memory on POWERPC.
@@ -383,6 +384,12 @@ config ARCH_HAS_WALK_MEMORY
 config ARCH_ENABLE_MEMORY_HOTREMOVE
         def_bool y
 
+config PPC64_SUPPORTS_MEMORY_FAILURE
+        bool "Add support for memory hwpoison"
+        depends on PPC_BOOK3S_64
+        default "y" if PPC_POWERNV
+        select ARCH_SUPPORTS_MEMORY_FAILURE
+
 config KEXEC
         bool "kexec system call"
         depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP))
@@ -403,8 +410,7 @@ config KEXEC
 config CRASH_DUMP
         bool "Build a kdump crash kernel"
         depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP)
-        select RELOCATABLE if PPC64 || 44x
-        select DYNAMIC_MEMSTART if FSL_BOOKE
+        select RELOCATABLE if PPC64 || 44x || FSL_BOOKE
         help
           Build a kernel suitable for use as a kdump capture kernel.
           The same kernel binary can be used as production kernel and dump
@@ -528,6 +534,7 @@ config PPC_16K_PAGES
 
 config PPC_64K_PAGES
         bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
+        depends on !PPC_FSL_BOOK3E
         select PPC_HAS_HASH_64K if PPC_STD_MMU_64
 
 config PPC_256K_PAGES
@@ -794,7 +801,7 @@ config HAS_RAPIDIO
         default n
 
 config RAPIDIO
-        bool "RapidIO support"
+        tristate "RapidIO support"
         depends on HAS_RAPIDIO || PCI
         help
           If you say Y here, the kernel will include drivers and
@@ -802,7 +809,7 @@ config RAPIDIO
 
 config FSL_RIO
         bool "Freescale Embedded SRIO Controller support"
-        depends on RAPIDIO && HAS_RAPIDIO
+        depends on RAPIDIO = y && HAS_RAPIDIO
         default "n"
         ---help---
           Include support for RapidIO controller on Freescale embedded
@@ -885,7 +892,7 @@ config DYNAMIC_MEMSTART
 
 config RELOCATABLE
         bool "Build a relocatable kernel"
-        depends on ADVANCED_OPTIONS && FLATMEM && 44x
+        depends on ADVANCED_OPTIONS && FLATMEM && (44x || FSL_BOOKE)
         select NONSTATIC_KERNEL
         help
           This builds a kernel image that is capable of running at the
@@ -1041,11 +1048,6 @@ config KEYS_COMPAT
 
 source "crypto/Kconfig"
 
-config PPC_CLOCK
-        bool
-        default n
-        select HAVE_CLK
-
 config PPC_LIB_RHEAP
         bool
 
diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore
index 554734ff302e..d61c03525777 100644
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -16,6 +16,7 @@ mktree
 uImage
 cuImage.*
 dtbImage.*
+*.dtb
 treeImage.*
 zImage
 zImage.initrd
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index ca7f08cc4afd..90e9d9548660 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -71,9 +71,9 @@ src-wlib-y := string.S crt0.S crtsavres.S stdio.c main.c \
                 uartlite.c mpc52xx-psc.c
 src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
 src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
-src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c
+src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c fsl-soc.c
 src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
-src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c
+src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
 
 src-plat-y := of.c epapr.c
 src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
@@ -95,7 +95,7 @@ src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
 src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
                                         cuboot-c2k.c gamecube-head.S \
                                         gamecube.c wii-head.S wii.c holly.c \
-                                        prpmc2800.c
+                                        prpmc2800.c fixed-head.S mvme5100.c
 src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
 src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
 src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
@@ -286,6 +286,7 @@ image-$(CONFIG_MPC7448HPC2)		+= cuImage.mpc7448hpc2
 image-$(CONFIG_PPC_C2K)                 += cuImage.c2k
 image-$(CONFIG_GAMECUBE)                += dtbImage.gamecube
 image-$(CONFIG_WII)                     += dtbImage.wii
+image-$(CONFIG_MVME5100)                += dtbImage.mvme5100
 
 # Board port in arch/powerpc/platform/amigaone/Kconfig
 image-$(CONFIG_AMIGAONE)                += cuImage.amigaone
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
index a543c4088cba..a1b883730b31 100644
--- a/arch/powerpc/boot/dts/ac14xx.dts
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -139,7 +139,14 @@
                 };
         };
 
+        clocks {
+                osc {
+                        clock-frequency = <25000000>;
+                };
+        };
+
         soc@80000000 {
+                bus-frequency = <80000000>;     /* 80 MHz ips bus */
 
                 clock@f00 {
                         compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
diff --git a/arch/powerpc/boot/dts/adder875-redboot.dts b/arch/powerpc/boot/dts/adder875-redboot.dts
index 28e9cd3d7a21..083984720b2f 100644
--- a/arch/powerpc/boot/dts/adder875-redboot.dts
+++ b/arch/powerpc/boot/dts/adder875-redboot.dts
@@ -87,12 +87,10 @@
 
                         PHY0: ethernet-phy@0 {
                                 reg = <0>;
-                                device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
                                 reg = <1>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/adder875-uboot.dts b/arch/powerpc/boot/dts/adder875-uboot.dts
index 54fb60ec03e5..e4554caf8f8d 100644
--- a/arch/powerpc/boot/dts/adder875-uboot.dts
+++ b/arch/powerpc/boot/dts/adder875-uboot.dts
@@ -86,12 +86,10 @@
 
                         PHY0: ethernet-phy@0 {
                                 reg = <0>;
-                                device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
                                 reg = <1>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 227290db866d..9198745f45fb 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -207,14 +207,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
index f5d625fa3e52..1e32903cb0a8 100644
--- a/arch/powerpc/boot/dts/c2k.dts
+++ b/arch/powerpc/boot/dts/c2k.dts
@@ -73,19 +73,16 @@
                         compatible = "marvell,mv64360-mdio";
                         reg = <0x2000 4>;
                         PHY0: ethernet-phy@0 {
-                                device_type = "ethernet-phy";
                                 interrupts = <76>;      /* GPP 12 */
                                 interrupt-parent = <&PIC>;
                                 reg = <0>;
                         };
                         PHY1: ethernet-phy@1 {
-                                device_type = "ethernet-phy";
                                 interrupts = <76>;      /* GPP 12 */
                                 interrupt-parent = <&PIC>;
                                 reg = <1>;
                         };
                         PHY2: ethernet-phy@2 {
-                                device_type = "ethernet-phy";
                                 interrupts = <76>;      /* GPP 12 */
                                 interrupt-parent = <&PIC>;
                                 reg = <2>;
@@ -174,7 +171,6 @@
                 };
 
                 MPSC0: mpsc@8000 {
-                        device_type = "serial";
                         compatible = "marvell,mv64360-mpsc";
                         reg = <0x8000 0x38>;
                         virtual-reg = <0xd8008000>;
@@ -189,7 +185,6 @@
                 };
 
                 MPSC1: mpsc@9000 {
-                        device_type = "serial";
                         compatible = "marvell,mv64360-mpsc";
                         reg = <0x9000 0x38>;
                         virtual-reg = <0xd8009000>;
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts
index 756758fb5b7b..8b3a49f34f5a 100644
--- a/arch/powerpc/boot/dts/ep8248e.dts
+++ b/arch/powerpc/boot/dts/ep8248e.dts
@@ -67,7 +67,6 @@
                         ranges;
 
                         mdio {
-                                device_type = "mdio";
                                 compatible = "fsl,ep8248e-mdio-bitbang";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -76,13 +75,11 @@
                                 PHY0: ethernet-phy@0 {
                                         interrupt-parent = <&PIC>;
                                         reg = <0>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&PIC>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                         };
                 };
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
index ae57d6240120..2aa5bf559645 100644
--- a/arch/powerpc/boot/dts/ep88xc.dts
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -85,12 +85,10 @@
 
                         PHY0: ethernet-phy@0 {
                                 reg = <0x0>;
-                                device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000000000000..d3cc8d0f7c25
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma2: dma@102300 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,elo3-dma";
+        reg = <0x102300 0x4>,
+              <0x102600 0x4>;
+        ranges = <0x0 0x102100 0x500>;
+        dma-channel@0 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x0 0x80>;
+                interrupts = <464 2 0 0>;
+        };
+        dma-channel@80 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x80 0x80>;
+                interrupts = <465 2 0 0>;
+        };
+        dma-channel@100 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x100 0x80>;
+                interrupts = <466 2 0 0>;
+        };
+        dma-channel@180 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x180 0x80>;
+                interrupts = <467 2 0 0>;
+        };
+        dma-channel@300 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x300 0x80>;
+                interrupts = <468 2 0 0>;
+        };
+        dma-channel@380 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x380 0x80>;
+                interrupts = <469 2 0 0>;
+        };
+        dma-channel@400 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x400 0x80>;
+                interrupts = <470 2 0 0>;
+        };
+        dma-channel@480 {
+                compatible = "fsl,eloplus-dma-channel";
+                reg = <0x480 0x80>;
+                interrupts = <471 2 0 0>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 68cc5e7f6477..642dc3a83d0e 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -36,7 +36,8 @@
         #address-cells = <2>;
         #size-cells = <1>;
         compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
-        interrupts = <19 2 0 0>;
+        interrupts = <19 2 0 0>,
+                     <16 2 0 0>;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index adb82fd9057f..407cb5fd0f5b 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -36,7 +36,8 @@
         #address-cells = <2>;
         #size-cells = <1>;
         compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
-        interrupts = <19 2 0 0>;
+        interrupts = <19 2 0 0>,
+                     <16 2 0 0>;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index e179803a81ef..ebf202234549 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -40,7 +40,8 @@
          * pin muxing when the DIU is enabled.
          */
         compatible = "fsl,p1022-elbc", "fsl,elbc";
-        interrupts = <19 2 0 0>;
+        interrupts = <19 2 0 0>,
+                     <16 2 0 0>;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index f1105bffa915..81437fdf1db4 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -36,7 +36,8 @@
         #address-cells = <2>;
         #size-cells = <1>;
         compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
-        interrupts = <19 2 0 0>;
+        interrupts = <19 2 0 0>,
+                     <16 2 0 0>;
 };
 
 /* controller at 0xa000 */
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 38dcb96c8e26..83eb0fda2666 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -292,13 +292,11 @@
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x9 0x4>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x8 0x4>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 5ab8932d09b7..d426dd3de9ef 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -290,13 +290,11 @@
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x9 0x4>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x8 0x4>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index d5341f5741aa..5db3399b76b7 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -290,13 +290,11 @@
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x9 0x4>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&gef_pic>;
                                         interrupts = <0x8 0x4>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index c6e11ebecebb..43e6f0c8e449 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -58,7 +58,6 @@
                 };
 
                 MDIO: mdio@6000 {
-                        device_type = "mdio";
                         compatible = "tsi109-mdio", "tsi108-mdio";
                         reg = <0x00006000 0x00000050>;
                         #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 1613d6e4049e..5ba7f01e2a29 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -406,7 +406,7 @@
 
                 MSI: ppc4xx-msi@C10000000 {
                         compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
-                        reg = < 0x0 0xEF620000 0x100>;
+                        reg = <0xEF620000 0x100>;
                         sdr-base = <0x4B0>;
                         msi-data = <0x00000000>;
                         msi-mask = <0x44440000>;
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index 296c572ea605..5d68236e7c3c 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -161,13 +161,11 @@
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 PHY2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
@@ -284,7 +282,6 @@
                                 PHY0: ethernet-phy@0 {
                                         interrupt-parent = <&mpic>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
                         };
 
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 2d7cb04ac962..2c0e1552d20b 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -9,6 +9,8 @@
  * option) any later version.
  */
 
+#include <dt-bindings/clock/mpc512x-clock.h>
+
 /dts-v1/;
 
 / {
@@ -49,6 +51,10 @@
                 compatible = "fsl,mpc5121-mbx";
                 reg = <0x20000000 0x4000>;
                 interrupts = <66 0x8>;
+                clocks = <&clks MPC512x_CLK_MBX_BUS>,
+                         <&clks MPC512x_CLK_MBX_3D>,
+                         <&clks MPC512x_CLK_MBX>;
+                clock-names = "mbx-bus", "mbx-3d", "mbx";
         };
 
         sram@30000000 {
@@ -62,6 +68,8 @@
                 interrupts = <6 8>;
                 #address-cells = <1>;
                 #size-cells = <1>;
+                clocks = <&clks MPC512x_CLK_NFC>;
+                clock-names = "ipg";
         };
 
         localbus@80000020 {
@@ -73,6 +81,17 @@
                 ranges = <0x0 0x0 0xfc000000 0x04000000>;
         };
 
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: osc {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <33000000>;
+                };
+        };
+
         soc@80000000 {
                 compatible = "fsl,mpc5121-immr";
                 #address-cells = <1>;
@@ -117,9 +136,12 @@
                 };
 
                 /* Clock control */
-                clock@f00 {
+                clks: clock@f00 {
                         compatible = "fsl,mpc5121-clock";
                         reg = <0xf00 0x100>;
+                        #clock-cells = <1>;
+                        clocks = <&osc>;
+                        clock-names = "osc";
                 };
 
                 /* Power Management Controller */
@@ -139,12 +161,24 @@
                         compatible = "fsl,mpc5121-mscan";
                         reg = <0x1300 0x80>;
                         interrupts = <12 0x8>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN0_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 can@1380 {
                         compatible = "fsl,mpc5121-mscan";
                         reg = <0x1380 0x80>;
                         interrupts = <13 0x8>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN1_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 sdhc@1500 {
@@ -153,6 +187,9 @@
                         interrupts = <8 0x8>;
                         dmas = <&dma0 30>;
                         dma-names = "rx-tx";
+                        clocks = <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SDHC>;
+                        clock-names = "ipg", "per";
                 };
 
                 i2c@1700 {
@@ -161,6 +198,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1700 0x20>;
                         interrupts = <9 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2c@1720 {
@@ -169,6 +208,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1720 0x20>;
                         interrupts = <10 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2c@1740 {
@@ -177,6 +218,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1740 0x20>;
                         interrupts = <11 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2ccontrol@1760 {
@@ -188,30 +231,48 @@
                         compatible = "fsl,mpc5121-axe";
                         reg = <0x2000 0x100>;
                         interrupts = <42 0x8>;
+                        clocks = <&clks MPC512x_CLK_AXE>;
+                        clock-names = "ipg";
                 };
 
                 display@2100 {
                         compatible = "fsl,mpc5121-diu";
                         reg = <0x2100 0x100>;
                         interrupts = <64 0x8>;
+                        clocks = <&clks MPC512x_CLK_DIU>;
+                        clock-names = "ipg";
                 };
 
                 can@2300 {
                         compatible = "fsl,mpc5121-mscan";
                         reg = <0x2300 0x80>;
                         interrupts = <90 0x8>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN2_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 can@2380 {
                         compatible = "fsl,mpc5121-mscan";
                         reg = <0x2380 0x80>;
                         interrupts = <91 0x8>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN3_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 viu@2400 {
                         compatible = "fsl,mpc5121-viu";
                         reg = <0x2400 0x400>;
                         interrupts = <67 0x8>;
+                        clocks = <&clks MPC512x_CLK_VIU>;
+                        clock-names = "ipg";
                 };
 
                 mdio@2800 {
@@ -219,6 +280,8 @@
                         reg = <0x2800 0x800>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        clocks = <&clks MPC512x_CLK_FEC>;
+                        clock-names = "per";
                 };
 
                 eth0: ethernet@2800 {
@@ -227,6 +290,8 @@
                         reg = <0x2800 0x800>;
                         local-mac-address = [ 00 00 00 00 00 00 ];
                         interrupts = <4 0x8>;
+                        clocks = <&clks MPC512x_CLK_FEC>;
+                        clock-names = "per";
                 };
 
                 /* USB1 using external ULPI PHY */
@@ -238,6 +303,8 @@
                         interrupts = <43 0x8>;
                         dr_mode = "otg";
                         phy_type = "ulpi";
+                        clocks = <&clks MPC512x_CLK_USB1>;
+                        clock-names = "ipg";
                 };
 
                 /* USB0 using internal UTMI PHY */
@@ -249,6 +316,8 @@
                         interrupts = <44 0x8>;
                         dr_mode = "otg";
                         phy_type = "utmi_wide";
+                        clocks = <&clks MPC512x_CLK_USB2>;
+                        clock-names = "ipg";
                 };
 
                 /* IO control */
@@ -267,6 +336,8 @@
                         compatible = "fsl,mpc5121-pata";
                         reg = <0x10200 0x100>;
                         interrupts = <5 0x8>;
+                        clocks = <&clks MPC512x_CLK_PATA>;
+                        clock-names = "ipg";
                 };
 
                 /* 512x PSCs are not 52xx PSC compatible */
@@ -278,6 +349,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC0>,
+                                 <&clks MPC512x_CLK_PSC0_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC1 */
@@ -287,6 +361,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC1>,
+                                 <&clks MPC512x_CLK_PSC1_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC2 */
@@ -296,6 +373,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC2>,
+                                 <&clks MPC512x_CLK_PSC2_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC3 */
@@ -305,6 +385,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC3>,
+                                 <&clks MPC512x_CLK_PSC3_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC4 */
@@ -314,6 +397,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC4>,
+                                 <&clks MPC512x_CLK_PSC4_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC5 */
@@ -323,6 +409,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC5>,
+                                 <&clks MPC512x_CLK_PSC5_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC6 */
@@ -332,6 +421,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC6>,
+                                 <&clks MPC512x_CLK_PSC6_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC7 */
@@ -341,6 +433,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC7>,
+                                 <&clks MPC512x_CLK_PSC7_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC8 */
@@ -350,6 +445,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC8>,
+                                 <&clks MPC512x_CLK_PSC8_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC9 */
@@ -359,6 +457,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC9>,
+                                 <&clks MPC512x_CLK_PSC9_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC10 */
@@ -368,6 +469,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC10>,
+                                 <&clks MPC512x_CLK_PSC10_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 /* PSC11 */
@@ -377,12 +481,17 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC11>,
+                                 <&clks MPC512x_CLK_PSC11_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 pscfifo@11f00 {
                         compatible = "fsl,mpc5121-psc-fifo";
                         reg = <0x11f00 0x100>;
                         interrupts = <40 0x8>;
+                        clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+                        clock-names = "ipg";
                 };
 
                 dma0: dma@14000 {
@@ -400,6 +509,8 @@
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
+                clocks = <&clks MPC512x_CLK_PCI>;
+                clock-names = "ipg";
 
                 reg = <0x80008500 0x100 /* internal registers */
                        0x80008300 0x8>; /* config space access registers */
diff --git a/arch/powerpc/boot/dts/mpc5125twr.dts b/arch/powerpc/boot/dts/mpc5125twr.dts
index a618dfc13e4c..e4f297471748 100644
--- a/arch/powerpc/boot/dts/mpc5125twr.dts
+++ b/arch/powerpc/boot/dts/mpc5125twr.dts
@@ -12,6 +12,8 @@
  * option) any later version.
  */
 
+#include <dt-bindings/clock/mpc512x-clock.h>
+
 /dts-v1/;
 
 / {
@@ -54,6 +56,17 @@
                 reg = <0x30000000 0x08000>;             // 32K at 0x30000000
         };
 
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: osc {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <33000000>;
+                };
+        };
+
         soc@80000000 {
                 compatible = "fsl,mpc5121-immr";
                 #address-cells = <1>;
@@ -87,9 +100,12 @@
                         reg = <0xe00 0x100>;
                 };
 
-                clock@f00 {     // Clock control
+                clks: clock@f00 {       // Clock control
                         compatible = "fsl,mpc5121-clock";
                         reg = <0xf00 0x100>;
+                        #clock-cells = <1>;
+                        clocks = <&osc>;
+                        clock-names = "osc";
                 };
 
                 pmc@1000{  // Power Management Controller
@@ -114,18 +130,33 @@
                         compatible = "fsl,mpc5121-mscan";
                         interrupts = <12 0x8>;
                         reg = <0x1300 0x80>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN0_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 can@1380 {
                         compatible = "fsl,mpc5121-mscan";
                         interrupts = <13 0x8>;
                         reg = <0x1380 0x80>;
+                        clocks = <&clks MPC512x_CLK_BDLC>,
+                                 <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SYS>,
+                                 <&clks MPC512x_CLK_REF>,
+                                 <&clks MPC512x_CLK_MSCAN1_MCLK>;
+                        clock-names = "ipg", "ips", "sys", "ref", "mclk";
                 };
 
                 sdhc@1500 {
                         compatible = "fsl,mpc5121-sdhc";
                         interrupts = <8 0x8>;
                         reg = <0x1500 0x100>;
+                        clocks = <&clks MPC512x_CLK_IPS>,
+                                 <&clks MPC512x_CLK_SDHC>;
+                        clock-names = "ipg", "per";
                 };
 
                 i2c@1700 {
@@ -134,6 +165,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1700 0x20>;
                         interrupts = <0x9 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2c@1720 {
@@ -142,6 +175,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1720 0x20>;
                         interrupts = <0xa 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2c@1740 {
@@ -150,6 +185,8 @@
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
                         reg = <0x1740 0x20>;
                         interrupts = <0xb 0x8>;
+                        clocks = <&clks MPC512x_CLK_I2C>;
+                        clock-names = "ipg";
                 };
 
                 i2ccontrol@1760 {
@@ -161,6 +198,8 @@
                         compatible = "fsl,mpc5121-diu";
                         reg = <0x2100 0x100>;
                         interrupts = <64 0x8>;
+                        clocks = <&clks MPC512x_CLK_DIU>;
+                        clock-names = "ipg";
                 };
 
                 mdio@2800 {
@@ -180,6 +219,8 @@
                         interrupts = <4 0x8>;
                         phy-handle = < &phy0 >;
                         phy-connection-type = "rmii";
+                        clocks = <&clks MPC512x_CLK_FEC>;
+                        clock-names = "per";
                 };
 
                 // IO control
@@ -200,6 +241,8 @@
                         interrupts = <43 0x8>;
                         dr_mode = "host";
                         phy_type = "ulpi";
+                        clocks = <&clks MPC512x_CLK_USB1>;
+                        clock-names = "ipg";
                         status = "disabled";
                 };
 
@@ -211,6 +254,9 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC1>,
+                                 <&clks MPC512x_CLK_PSC1_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 // PSC9 uart1 aka ttyPSC1
@@ -220,12 +266,17 @@
                         interrupts = <40 0x8>;
                         fsl,rx-fifo-size = <16>;
                         fsl,tx-fifo-size = <16>;
+                        clocks = <&clks MPC512x_CLK_PSC9>,
+                                 <&clks MPC512x_CLK_PSC9_MCLK>;
+                        clock-names = "ipg", "mclk";
                 };
 
                 pscfifo@11f00 {
                         compatible = "fsl,mpc5121-psc-fifo";
                         reg = <0x11f00 0x100>;
                         interrupts = <40 0x8>;
+                        clocks = <&clks MPC512x_CLK_PSC_FIFO>;
+                        clock-names = "ipg";
                 };
 
                 dma@14000 {
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 2544f3ecd6e9..20a0d22df473 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -68,7 +68,6 @@
                 };
 
                 MDIO: mdio@6000 {
-                        device_type = "mdio";
                         compatible = "tsi108-mdio";
                         reg = <0x6000 0x50>;
                         #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index e802ebd88cb1..6d2cddf64cfd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -182,7 +182,6 @@
                         };
 
                         mdio@10d40 {
-                                device_type = "mdio";
                                 compatible = "fsl,mpc8272ads-mdio-bitbang",
                                              "fsl,mpc8272-mdio-bitbang",
                                              "fsl,cpm2-mdio-bitbang";
@@ -196,14 +195,12 @@
                                         interrupt-parent = <&PIC>;
                                         interrupts = <23 8>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&PIC>;
                                         interrupts = <23 8>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
                         };
 
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 22b0832b6c31..651e4f55acdb 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -189,13 +189,11 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <19 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index f66d10d95a8d..9ce45f2efd34 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -166,7 +166,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 1c836c6c5be6..4b635dc4ecde 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -217,7 +217,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <20 0x8>;
                                         reg = <0x4>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 811848e93aef..43546844ea5a 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -216,14 +216,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <20 0x8>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <19 0x8>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index da9c72ddc343..0793cdf0d46e 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -356,13 +356,11 @@
                                 interrupt-parent = <&ipic>;
                                 interrupts = <17 0x8>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                         phy4: ethernet-phy@04 {
                                 interrupt-parent = <&ipic>;
                                 interrupts = <18 0x8>;
                                 reg = <0x4>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index ff7b15b340a3..91df1eb16667 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -314,13 +314,11 @@
                                 interrupt-parent = <&ipic>;
                                 interrupts = <0>;
                                 reg = <0x0>;
-                                device_type = "ethernet-phy";
                         };
                         phy04:ethernet-phy@04 {
                                 interrupt-parent = <&ipic>;
                                 interrupts = <0>;
                                 reg = <0x4>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 2608679d0d4a..cf8542401a3c 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -240,7 +240,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x1c>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 6cd044d8fb89..f00066dcc8de 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -176,7 +176,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x1c>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 4552864082c2..4843c3ff7166 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -193,14 +193,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 81dd513d6308..ecb6ccd3a6aa 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -397,13 +397,11 @@
                                 interrupt-parent = <&ipic>;
                                 interrupts = <17 0x8>;
                                 reg = <0x0>;
-                                device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@01 {
                                 interrupt-parent = <&ipic>;
                                 interrupts = <18 0x8>;
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
                         tbi-phy@2 {
                                 device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index b6e9aec1d860..daeacbdcf8b4 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -332,25 +332,21 @@
                                 reg = <0x2120 0x18>;
 
                                 phy1: ethernet-phy@1 {
-                                        device_type = "ethernet-phy";
                                         compatible = "national,DP83848VV";
                                         reg = <1>;
                                 };
 
                                 phy2: ethernet-phy@2 {
-                                        device_type = "ethernet-phy";
                                         compatible = "broadcom,BCM5481UA2KMLG";
                                         reg = <2>;
                                 };
 
                                 phy3: ethernet-phy@3 {
-                                        device_type = "ethernet-phy";
                                         compatible = "national,DP83848VV";
                                         reg = <3>;
                                 };
 
                                 phy4: ethernet-phy@4 {
-                                        device_type = "ethernet-phy";
                                         compatible = "broadcom,BCM5481UA2KMLG";
                                         reg = <4>;
                                 };
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index cfccef57cd1d..c2c062e8175d 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -225,14 +225,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 353deff1b7f6..2b4b6532d69c 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -277,7 +277,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
index ef4a305a0d0c..c0c790168b96 100644
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -253,14 +253,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 538fcb927337..1b82b77f9415 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -264,14 +264,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 32333a908f3d..74b6a535a413 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -277,7 +277,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 5387092fdfb4..38e5048d65d2 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -262,14 +262,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <18 0x8>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 46224c2430ff..3b5cbac85368 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -275,7 +275,6 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <17 0x8>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index 7c3dde84d193..937ad7e46119 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -200,12 +200,10 @@
                 phy0: ethernet-phy@0 {
                         interrupts = <10 0x1 0 0>;
                         reg = <0>;
-                        device_type = "ethernet-phy";
                 };
                 phy1: ethernet-phy@1 {
                         interrupts = <10 0x1 0 0>;
                         reg = <1>;
-                        device_type = "ethernet-phy";
                 };
                 sgmii_phy0: sgmii-phy@0 {
                         interrupts = <6 1 0 0>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 2d31863accf5..7ce274c9a2d5 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -165,19 +165,16 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <7 1>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 1c03c2667373..4d35a3e0fb02 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -165,13 +165,11 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
index b219d035d794..47d986b041f6 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -82,12 +82,10 @@
                 phy0: ethernet-phy@0 {
                         interrupts = <10 1 0 0>;
                         reg = <0x0>;
-                        device_type = "ethernet-phy";
                 };
                 phy1: ethernet-phy@1 {
                         interrupts = <10 1 0 0>;
                         reg = <0x1>;
-                        device_type = "ethernet-phy";
                 };
 
                 sgmii_phy0: sgmii-phy@0 {
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dtsi b/arch/powerpc/boot/dts/mpc8548cds.dtsi
index c61f525e4740..3bc7d4711220 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi
@@ -109,22 +109,18 @@
                 phy0: ethernet-phy@0 {
                         interrupts = <5 1 0 0>;
                         reg = <0x0>;
-                        device_type = "ethernet-phy";
                 };
                 phy1: ethernet-phy@1 {
                         interrupts = <5 1 0 0>;
                         reg = <0x1>;
-                        device_type = "ethernet-phy";
                 };
                 phy2: ethernet-phy@2 {
                         interrupts = <5 1 0 0>;
                         reg = <0x2>;
-                        device_type = "ethernet-phy";
                 };
                 phy3: ethernet-phy@3 {
                         interrupts = <5 1 0 0>;
                         reg = <0x3>;
-                        device_type = "ethernet-phy";
                 };
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 36a7ea138c2f..f115f21cb0ae 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -165,13 +165,11 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 1a43f5a968f5..0d70921d6125 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -154,25 +154,21 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <7 1>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <7 1>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 09598bb5d443..bead2b655b9f 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -91,22 +91,18 @@
                         phy0: ethernet-phy@7 {
                                 interrupts = <1 1 0 0>;
                                 reg = <0x7>;
-                                device_type = "ethernet-phy";
                         };
                         phy1: ethernet-phy@1 {
                                 interrupts = <2 1 0 0>;
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
                         phy2: ethernet-phy@2 {
                                 interrupts = <1 1 0 0>;
                                 reg = <0x2>;
-                                device_type = "ethernet-phy";
                         };
                         phy3: ethernet-phy@3 {
                                 interrupts = <2 1 0 0>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                         tbi0: tbi-phy@11 {
                                 reg = <0x11>;
@@ -236,25 +232,21 @@
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1 0 0>;
                                 reg = <0x7>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy1: ethernet-phy@01 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1 0 0>;
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy2: ethernet-phy@02 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1 0 0>;
                                 reg = <0x2>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy3: ethernet-phy@03 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1 0 0>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                 };
         };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index fe0d60935e9b..d0dcdafa5eb2 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -276,33 +276,27 @@
                                 interrupt-parent = <&mpic>;
                                 interrupts = <1 1 0 0>;
                                 reg = <0x7>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy1: ethernet-phy@01 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <2 1 0 0>;
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy2: ethernet-phy@02 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <3 1 0 0>;
                                 reg = <0x2>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy3: ethernet-phy@03 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <4 1 0 0>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy5: ethernet-phy@04 {
                                 reg = <0x04>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy7: ethernet-phy@06 {
                                 reg = <0x6>;
-                                device_type = "ethernet-phy";
                         };
                         tbi1: tbi-phy@11 {
                                 reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 1e8666ccbed8..1c03060dd0b8 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -211,25 +211,21 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
index fd4cd4da60b5..bb575e28042a 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -211,25 +211,21 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index bd700651f360..34c1f48b1a09 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -74,7 +74,6 @@
                         #size-cells = <0>;
                         PHY: ethernet-phy@f {
                                 reg = <0xf>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index b123e9f7a5a8..4e93bd961e0f 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -86,17 +86,14 @@
 
                         PHY0: ethernet-phy@0 {
                                 reg = <0x0>;
-                                device_type = "ethernet-phy";
                         };
 
                         PHY1: ethernet-phy@1 {
                                 reg = <0x1>;
-                                device_type = "ethernet-phy";
                         };
 
                         PHY2: ethernet-phy@2 {
                                 reg = <0x2>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mvme5100.dts b/arch/powerpc/boot/dts/mvme5100.dts
new file mode 100644
index 000000000000..1ecb341a232a
--- /dev/null
+++ b/arch/powerpc/boot/dts/mvme5100.dts
@@ -0,0 +1,185 @@
+/*
+ * Device Tree Source for Motorola/Emerson MVME5100.
+ *
+ * Copyright 2013 CSC Australia Pty. Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "MVME5100";
+        compatible = "MVME5100";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                serial0 = &serial0;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,7410 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        /* Following required by dtc but not used */
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        timebase-frequency = <25000000>;
+                        clock-frequency = <500000000>;
+                        bus-frequency = <100000000>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+
+        hawk@fef80000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "hawk-bridge", "simple-bus";
+                ranges = <0x0 0xfef80000 0x10000>;
+                reg = <0xfef80000 0x10000>;
+
+                serial0: serial@8000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x8000 0x80>;
+                        reg-shift = <4>;
+                        clock-frequency = <1843200>;
+                        current-speed = <9600>;
+                        interrupts = <1 1>; // IRQ1 Level Active Low.
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@8200 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x8200 0x80>;
+                        reg-shift = <4>;
+                        clock-frequency = <1843200>;
+                        current-speed = <9600>;
+                        interrupts = <1 1>; // IRQ1 Level Active Low.
+                        interrupt-parent = <&mpic>;
+                };
+
+                mpic: interrupt-controller@f3f80000 {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        device_type = "open-pic";
+                        compatible = "chrp,open-pic";
+                        interrupt-controller;
+                        reg = <0xf3f80000 0x40000>;
+                };
+        };
+
+        pci0: pci@feff0000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "hawk-pci";
+                reg = <0xfec00000 0x400000>;
+                8259-interrupt-acknowledge = <0xfeff0030>;
+                ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0x800000
+                          0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>;
+                bus-range = <0 255>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /*
+                         * This definition (IDSEL 11) duplicates the
+                         * interrupts definition in the i8259
+                         * interrupt controller below.
+                         *
+                         * Do not change the interrupt sense/polarity from
+                         * 0x2 to anything else, doing so will cause endless
+                         * "spurious" i8259 interrupts to be fielded.
+                         */
+                        // IDSEL 11 - iPMC712 PCI/ISA Bridge
+                        0x5800 0x0 0x0 0x1 &mpic 0x0 0x2
+                        0x5800 0x0 0x0 0x2 &mpic 0x0 0x2
+                        0x5800 0x0 0x0 0x3 &mpic 0x0 0x2
+                        0x5800 0x0 0x0 0x4 &mpic 0x0 0x2
+
+                        /* IDSEL 12 - Not Used */
+
+                        /* IDSEL 13 - Universe VME Bridge */
+                        0x6800 0x0 0x0 0x1 &mpic 0x5 0x1
+                        0x6800 0x0 0x0 0x2 &mpic 0x6 0x1
+                        0x6800 0x0 0x0 0x3 &mpic 0x7 0x1
+                        0x6800 0x0 0x0 0x4 &mpic 0x8 0x1
+
+                        /* IDSEL 14 - ENET 1 */
+                        0x7000 0x0 0x0 0x1 &mpic 0x2 0x1
+
+                        /* IDSEL 15 - Not Used */
+
+                        /* IDSEL 16 - PMC Slot 1 */
+                        0x8000 0x0 0x0 0x1 &mpic 0x9 0x1
+                        0x8000 0x0 0x0 0x2 &mpic 0xa 0x1
+                        0x8000 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0x8000 0x0 0x0 0x4 &mpic 0xc 0x1
+
+                        /* IDSEL 17 - PMC Slot 2 */
+                        0x8800 0x0 0x0 0x1 &mpic 0xc 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x9 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0xa 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0xb 0x1
+
+                        /* IDSEL 18 - Not Used */
+
+                        /* IDSEL 19 - ENET 2 */
+                        0x9800 0x0 0x0 0x1 &mpic 0xd 0x1
+
+                        /* IDSEL 20 - PMCSPAN (PCI-X) */
+                        0xa000 0x0 0x0 0x1 &mpic 0x9 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0xa 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0xc 0x1
+
+                >;
+
+                isa {
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        #interrupt-cells = <2>;
+                        device_type = "isa";
+                        compatible = "isa";
+                        ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
+                        interrupt-parent = <&i8259>;
+
+                        i8259: interrupt-controller@20 {
+                                #interrupt-cells = <2>;
+                                #address-cells = <0>;
+                                interrupts = <0 2>;
+                                device_type = "interrupt-controller";
+                                compatible = "chrp,iic";
+                                interrupt-controller;
+                                reg = <1 0x00000020 0x00000002
+                                       1 0x000000a0 0x00000002
+                                       1 0x000004d0 0x00000002>;
+                                interrupt-parent = <&mpic>;
+                        };
+
+                };
+
+        };
+
+        chosen {
+                linux,stdout-path = &serial0;
+        };
+
+};
diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dts b/arch/powerpc/boot/dts/p1010rdb-pa.dts
new file mode 100644
index 000000000000..767d4c032857
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pa.dts
@@ -0,0 +1,23 @@
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+        model = "fsl,P1010RDB";
+        compatible = "fsl,P1010RDB";
+
+        /include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010rdb.dtsi"
+/include/ "p1010rdb-pa.dtsi"
+/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dtsi b/arch/powerpc/boot/dts/p1010rdb-pa.dtsi
new file mode 100644
index 000000000000..434fb2d58575
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pa.dtsi
@@ -0,0 +1,85 @@
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc_nand {
+        partition@0 {
+                /* This location must not be altered  */
+                /* 1MB for u-boot Bootloader Image */
+                reg = <0x0 0x00100000>;
+                label = "NAND U-Boot Image";
+                read-only;
+        };
+
+        partition@100000 {
+                /* 1MB for DTB Image */
+                reg = <0x00100000 0x00100000>;
+                label = "NAND DTB Image";
+        };
+
+        partition@200000 {
+                /* 4MB for Linux Kernel Image */
+                reg = <0x00200000 0x00400000>;
+                label = "NAND Linux Kernel Image";
+        };
+
+        partition@600000 {
+                /* 4MB for Compressed Root file System Image */
+                reg = <0x00600000 0x00400000>;
+                label = "NAND Compressed RFS Image";
+        };
+
+        partition@a00000 {
+                /* 15MB for JFFS2 based Root file System */
+                reg = <0x00a00000 0x00f00000>;
+                label = "NAND JFFS2 Root File System";
+        };
+
+        partition@1900000 {
+                /* 7MB for User Area */
+                reg = <0x01900000 0x00700000>;
+                label = "NAND User area";
+        };
+};
+
+&phy0 {
+        interrupts = <1 1 0 0>;
+};
+
+&phy1 {
+        interrupts = <2 1 0 0>;
+};
+
+&phy2 {
+        interrupts = <4 1 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/p1010rdb-pa_36b.dts
index 64776f4a4651..3033371bc007 100644
--- a/arch/powerpc/boot/dts/p1010rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1010rdb-pa_36b.dts
@@ -38,52 +38,9 @@
         model = "fsl,P1010RDB";
         compatible = "fsl,P1010RDB";
 
-        memory {
-                device_type = "memory";
-        };
-
-        board_ifc: ifc: ifc@fffe1e000 {
-                /* NOR, NAND Flashes and CPLD on board */
-                ranges = <0x0 0x0 0xf 0xee000000 0x02000000
-                          0x1 0x0 0xf 0xff800000 0x00010000
-                          0x3 0x0 0xf 0xffb00000 0x00000020>;
-                reg = <0xf 0xffe1e000 0 0x2000>;
-        };
-
-        board_soc: soc: soc@fffe00000 {
-                ranges = <0x0 0xf 0xffe00000 0x100000>;
-        };
-
-        pci0: pcie@fffe09000 {
-                reg = <0xf 0xffe09000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-
-        pci1: pcie@fffe0a000 {
-                reg = <0xf 0xffe0a000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
+        /include/ "p1010rdb_36b.dtsi"
 };
 
 /include/ "p1010rdb.dtsi"
+/include/ "p1010rdb-pa.dtsi"
 /include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pb.dts b/arch/powerpc/boot/dts/p1010rdb-pb.dts
new file mode 100644
index 000000000000..6eeb7d3185be
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pb.dts
@@ -0,0 +1,35 @@
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+        model = "fsl,P1010RDB-PB";
+        compatible = "fsl,P1010RDB-PB";
+
+        /include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010rdb.dtsi"
+
+&phy0 {
+        interrupts = <0 1 0 0>;
+};
+
+&phy1 {
+        interrupts = <2 1 0 0>;
+};
+
+&phy2 {
+        interrupts = <1 1 0 0>;
+};
+
+/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts b/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts
new file mode 100644
index 000000000000..7ab3c907b326
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb-pb_36b.dts
@@ -0,0 +1,58 @@
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+        model = "fsl,P1010RDB-PB";
+        compatible = "fsl,P1010RDB-PB";
+
+        /include/ "p1010rdb_36b.dtsi"
+};
+
+/include/ "p1010rdb.dtsi"
+
+&phy0 {
+        interrupts = <0 1 0 0>;
+};
+
+&phy1 {
+        interrupts = <2 1 0 0>;
+};
+
+&phy2 {
+        interrupts = <1 1 0 0>;
+};
+
+/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
deleted file mode 100644
index b868d22984e9..000000000000
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * P1010 RDB Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "fsl/p1010si-pre.dtsi"
-
-/ {
-        model = "fsl,P1010RDB";
-        compatible = "fsl,P1010RDB";
-
-        memory {
-                device_type = "memory";
-        };
-
-        board_ifc: ifc: ifc@ffe1e000 {
-                /* NOR, NAND Flashes and CPLD on board */
-                ranges = <0x0 0x0 0x0 0xee000000 0x02000000
-                          0x1 0x0 0x0 0xff800000 0x00010000
-                          0x3 0x0 0x0 0xffb00000 0x00000020>;
-                reg = <0x0 0xffe1e000 0 0x2000>;
-        };
-
-        board_soc: soc: soc@ffe00000 {
-                ranges = <0x0 0x0 0xffe00000 0x100000>;
-        };
-
-        pci0: pcie@ffe09000 {
-                reg = <0 0xffe09000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-
-        pci1: pcie@ffe0a000 {
-                reg = <0 0xffe0a000 0 0x1000>;
-                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-};
-
-/include/ "p1010rdb.dtsi"
-/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index ec7c27a64671..ea534efa790d 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -69,49 +69,11 @@
                 };
         };
 
-        nand@1,0 {
+        ifc_nand: nand@1,0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "fsl,ifc-nand";
                 reg = <0x1 0x0 0x10000>;
-
-                partition@0 {
-                        /* This location must not be altered  */
-                        /* 1MB for u-boot Bootloader Image */
-                        reg = <0x0 0x00100000>;
-                        label = "NAND U-Boot Image";
-                        read-only;
-                };
-
-                partition@100000 {
-                        /* 1MB for DTB Image */
-                        reg = <0x00100000 0x00100000>;
-                        label = "NAND DTB Image";
-                };
-
-                partition@200000 {
-                        /* 4MB for Linux Kernel Image */
-                        reg = <0x00200000 0x00400000>;
-                        label = "NAND Linux Kernel Image";
-                };
-
-                partition@600000 {
-                        /* 4MB for Compressed Root file System Image */
-                        reg = <0x00600000 0x00400000>;
-                        label = "NAND Compressed RFS Image";
-                };
-
-                partition@a00000 {
-                        /* 15MB for JFFS2 based Root file System */
-                        reg = <0x00a00000 0x00f00000>;
-                        label = "NAND JFFS2 Root File System";
-                };
-
-                partition@1900000 {
-                        /* 7MB for User Area */
-                        reg = <0x01900000 0x00700000>;
-                        label = "NAND User area";
-                };
         };
 
         cpld@3,0 {
@@ -193,17 +155,14 @@
 
         mdio@24000 {
                 phy0: ethernet-phy@0 {
-                        interrupts = <3 1 0 0>;
                         reg = <0x1>;
                 };
 
                 phy1: ethernet-phy@1 {
-                        interrupts = <2 1 0 0>;
                         reg = <0x0>;
                 };
 
                 phy2: ethernet-phy@2 {
-                        interrupts = <2 1 0 0>;
                         reg = <0x2>;
                 };
 
diff --git a/arch/powerpc/boot/dts/p1010rdb_32b.dtsi b/arch/powerpc/boot/dts/p1010rdb_32b.dtsi
new file mode 100644
index 000000000000..fdc19aab2f70
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_32b.dtsi
@@ -0,0 +1,79 @@
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+memory {
+        device_type = "memory";
+};
+
+board_ifc: ifc: ifc@ffe1e000 {
+        /* NOR, NAND Flashes and CPLD on board */
+        ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+                  0x1 0x0 0x0 0xff800000 0x00010000
+                  0x3 0x0 0x0 0xffb00000 0x00000020>;
+        reg = <0x0 0xffe1e000 0 0x2000>;
+};
+
+board_soc: soc: soc@ffe00000 {
+        ranges = <0x0 0x0 0xffe00000 0x100000>;
+};
+
+pci0: pcie@ffe09000 {
+        reg = <0 0xffe09000 0 0x1000>;
+        ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+        pcie@0 {
+                ranges = <0x2000000 0x0 0xa0000000
+                          0x2000000 0x0 0xa0000000
+                          0x0 0x20000000
+
+                          0x1000000 0x0 0x0
+                          0x1000000 0x0 0x0
+                          0x0 0x100000>;
+        };
+};
+
+pci1: pcie@ffe0a000 {
+        reg = <0 0xffe0a000 0 0x1000>;
+        ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+        pcie@0 {
+                ranges = <0x2000000 0x0 0x80000000
+                          0x2000000 0x0 0x80000000
+                          0x0 0x20000000
+
+                          0x1000000 0x0 0x0
+                          0x1000000 0x0 0x0
+                          0x0 0x100000>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dtsi b/arch/powerpc/boot/dts/p1010rdb_36b.dtsi
new file mode 100644
index 000000000000..de2fceed4f79
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_36b.dtsi
@@ -0,0 +1,79 @@
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+memory {
+        device_type = "memory";
+};
+
+board_ifc: ifc: ifc@fffe1e000 {
+        /* NOR, NAND Flashes and CPLD on board */
+        ranges = <0x0 0x0 0xf 0xee000000 0x02000000
+                  0x1 0x0 0xf 0xff800000 0x00010000
+                  0x3 0x0 0xf 0xffb00000 0x00000020>;
+        reg = <0xf 0xffe1e000 0 0x2000>;
+};
+
+board_soc: soc: soc@fffe00000 {
+        ranges = <0x0 0xf 0xffe00000 0x100000>;
+};
+
+pci0: pcie@fffe09000 {
+        reg = <0xf 0xffe09000 0 0x1000>;
+        ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+        pcie@0 {
+                ranges = <0x2000000 0x0 0xc0000000
+                          0x2000000 0x0 0xc0000000
+                          0x0 0x20000000
+
+                          0x1000000 0x0 0x0
+                          0x1000000 0x0 0x0
+                          0x0 0x100000>;
+        };
+};
+
+pci1: pcie@fffe0a000 {
+        reg = <0xf 0xffe0a000 0 0x1000>;
+        ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+        pcie@0 {
+                ranges = <0x2000000 0x0 0xc0000000
+                          0x2000000 0x0 0xc0000000
+                          0x0 0x20000000
+
+                          0x1000000 0x0 0x0
+                          0x1000000 0x0 0x0
+                          0x0 0x100000>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index 97116f198a37..76559044df41 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -295,13 +295,11 @@
                                 interrupt-parent = <&mpic>;
                                 interrupts = <4 1 0 0>;
                                 reg = <0x0>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy1: ethernet-phy@03 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1 0 0>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                         tbi-phy@11 {
                                 reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index 873da350d01b..957e0dc1dc0f 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -146,8 +146,9 @@
                          */
                 };
                 rtc@68 {
-                        compatible = "dallas,ds1339";
+                        compatible = "dallas,ds3232";
                         reg = <0x68>;
+                        interrupts = <0x1 0x1 0 0>;
                 };
                 adt7461@4c {
                         compatible = "adi,adt7461";
diff --git a/arch/powerpc/boot/dts/p1025rdb_32b.dts b/arch/powerpc/boot/dts/p1025rdb_32b.dts
index ac5729c14eda..a2ed6280ba7a 100644
--- a/arch/powerpc/boot/dts/p1025rdb_32b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_32b.dts
@@ -105,13 +105,11 @@
                                 interrupt-parent = <&mpic>;
                                 interrupts = <4 1 0 0>;
                                 reg = <0x6>;
-                                device_type = "ethernet-phy";
                         };
                         qe_phy1: ethernet-phy@03 {
                                 interrupt-parent = <&mpic>;
                                 interrupts = <5 1 0 0>;
                                 reg = <0x3>;
-                                device_type = "ethernet-phy";
                         };
                         tbi-phy@11 {
                                 reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/p1025twr.dts b/arch/powerpc/boot/dts/p1025twr.dts
new file mode 100644
index 000000000000..9036a4987905
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dts
@@ -0,0 +1,95 @@
+/*
+ * P1025 TWR Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+        model = "fsl,P1025";
+        compatible = "fsl,TWR-P1025";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
+
+                /* NOR Flash and SSD1289 */
+                ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+                          0x2 0x0 0x0 0xe0000000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        qe: qe@ffe80000 {
+                ranges = <0x0 0x0 0xffe80000 0x40000>;
+                reg = <0 0xffe80000 0 0x480>;
+                brg-frequency = <0>;
+                bus-frequency = <0>;
+        };
+};
+
+/include/ "p1025twr.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000000000000..8453501c256e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,280 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+       aliases {
+                ethernet3 = &enet3;
+                ethernet4 = &enet4;
+       };
+};
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x4000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 5.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00580000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 56.75MB for Root file System */
+                        reg = <0x00600000 0x038c0000>;
+                        label = "NOR Root File System";
+                };
+
+                partition@ec0000 {
+                        /* This location must not be altered  */
+                        /* 256KB for QE ucode firmware*/
+                        reg = <0x03ec0000 0x00040000>;
+                        label = "NOR QE microcode firmware";
+                        read-only;
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x03f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        /* CS2 for Display */
+        display@2,0 {
+                compatible = "solomon,ssd1289fb";
+                reg = <0x2 0x0000 0x0004>;
+        };
+
+};
+
+&soc {
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@2 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <1 1 0 0>;
+                        reg = <0x2>;
+                };
+
+                phy1: ethernet-phy@1 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                };
+
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+
+        };
+
+        enet1: ethernet@b1000 {
+                status = "disabled";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        par_io@e0100 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xe0100 0x60>;
+                ranges = <0x0 0xe0100 0x60>;
+                device_type = "par_io";
+                num-ports = <3>;
+                pio1: ucc_pin@01 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
+                                0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
+                                0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
+                                0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
+                                0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
+                                0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
+                                0x0  0xc  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
+                                0x0  0x6  0x2  0x0  0x2  0x0    /* ENET1_RXD0_SER1_RXD0 */
+                                0x0  0xa  0x2  0x0  0x2  0x0    /* ENET1_RXD1_SER1_RXD1 */
+                                0x0  0xe  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
+                                0x0  0xf  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
+                                0x0  0x5  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
+                                0x0  0xd  0x1  0x0  0x2  0x0    /* ENET1_TX_ER */
+                                0x0  0x4  0x2  0x0  0x2  0x0    /* ENET1_RX_DV_SER1_CTS_B */
+                                0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RX_ER_SER1_CD_B */
+                                0x0  0x11 0x2  0x0  0x2  0x0    /* ENET1_CRS */
+                                0x0  0x10 0x2  0x0  0x2  0x0>;    /* ENET1_COL */
+                };
+
+                pio2: ucc_pin@02 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
+                                0x1  0xb  0x2  0x0  0x1  0x0    /* CLK13 */
+                                0x1  0x7  0x1  0x0  0x2  0x0    /* ENET5_TXD0_SER5_TXD0 */
+                                0x1  0xa  0x1  0x0  0x2  0x0    /* ENET5_TXD1_SER5_TXD1 */
+                                0x1  0x6  0x2  0x0  0x2  0x0    /* ENET5_RXD0_SER5_RXD0 */
+                                0x1  0x9  0x2  0x0  0x2  0x0    /* ENET5_RXD1_SER5_RXD1 */
+                                0x1  0x5  0x1  0x0  0x2  0x0    /* ENET5_TX_EN_SER5_RTS_B */
+                                0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
+                                0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
+                };
+
+                pio3: ucc_pin@03 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x0  0x16 0x2  0x0  0x2  0x0    /* SER7_CD_B*/
+                                0x0  0x12 0x2  0x0  0x2  0x0    /* SER7_CTS_B*/
+                                0x0  0x13 0x1  0x0  0x2  0x0    /* SER7_RTS_B*/
+                                0x0  0x14 0x2  0x0  0x2  0x0    /* SER7_RXD0*/
+                                0x0  0x15 0x1  0x0  0x2  0x0>;    /* SER7_TXD0*/
+                };
+
+                pio4: ucc_pin@04 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x0  0x2  0x0  0x2  0x0    /* SER3_CD_B*/
+                                0x0  0x1c 0x2  0x0  0x2  0x0    /* SER3_CTS_B*/
+                                0x0  0x1d 0x1  0x0  0x2  0x0    /* SER3_RTS_B*/
+                                0x0  0x1e 0x2  0x0  0x2  0x0    /* SER3_RXD0*/
+                                0x0  0x1f 0x1  0x0  0x2  0x0>;    /* SER3_TXD0*/
+                };
+        };
+};
+
+&qe {
+        enet3: ucc@2000 {
+                device_type = "network";
+                compatible = "ucc_geth";
+                rx-clock-name = "clk12";
+                tx-clock-name = "clk9";
+                pio-handle = <&pio1>;
+                phy-handle = <&qe_phy0>;
+                phy-connection-type = "mii";
+        };
+
+        mdio@2120 {
+                qe_phy0: ethernet-phy@18 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <4 1 0 0>;
+                        reg = <0x18>;
+                        device_type = "ethernet-phy";
+                };
+                qe_phy1: ethernet-phy@19 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <5 1 0 0>;
+                        reg = <0x19>;
+                        device_type = "ethernet-phy";
+                };
+                tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet4: ucc@2400 {
+                device_type = "network";
+                compatible = "ucc_geth";
+                rx-clock-name = "none";
+                tx-clock-name = "clk13";
+                pio-handle = <&pio2>;
+                phy-handle = <&qe_phy1>;
+                phy-connection-type = "rmii";
+        };
+
+        serial2: ucc@2600 {
+                device_type = "serial";
+                compatible = "ucc_uart";
+                port-number = <0>;
+                rx-clock-name = "brg6";
+                tx-clock-name = "brg6";
+                pio-handle = <&pio3>;
+        };
+
+        serial3: ucc@2200 {
+                device_type = "serial";
+                compatible = "ucc_uart";
+                port-number = <1>;
+                rx-clock-name = "brg2";
+                tx-clock-name = "brg2";
+                pio-handle = <&pio4>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/ppa8548.dts b/arch/powerpc/boot/dts/ppa8548.dts
index f97eceed610a..27b0699ee923 100644
--- a/arch/powerpc/boot/dts/ppa8548.dts
+++ b/arch/powerpc/boot/dts/ppa8548.dts
@@ -110,12 +110,10 @@
                 phy0: ethernet-phy@0 {
                         interrupts = <7 1 0 0>;
                         reg = <0x0>;
-                        device_type = "ethernet-phy";
                 };
                 phy1: ethernet-phy@1 {
                         interrupts = <8 1 0 0>;
                         reg = <0x1>;
-                        device_type = "ethernet-phy";
                 };
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index 0bb669376743..0c525ff0c257 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -198,7 +198,6 @@
                         };
 
                         mdio@10d40 {
-                                device_type = "mdio";
                                 compatible = "fsl,pq2fads-mdio-bitbang",
                                              "fsl,mpc8280-mdio-bitbang",
                                              "fsl,cpm2-mdio-bitbang";
@@ -212,14 +211,12 @@
                                         interrupt-parent = <&PIC>;
                                         interrupts = <25 2>;
                                         reg = <0x0>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 PHY1: ethernet-phy@1 {
                                         interrupt-parent = <&PIC>;
                                         interrupts = <25 2>;
                                         reg = <0x3>;
-                                        device_type = "ethernet-phy";
                                 };
                         };
 
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 1ee6ff43dd57..00afaacf8c8c 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -73,17 +73,14 @@
                 mdio {
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        device_type = "mdio";
                         compatible = "marvell,mv64360-mdio";
                         PHY0: ethernet-phy@1 {
-                                device_type = "ethernet-phy";
                                 compatible = "broadcom,bcm5421";
                                 interrupts = <76>;      /* GPP 12 */
                                 interrupt-parent = <&PIC>;
                                 reg = <1>;
                         };
                         PHY1: ethernet-phy@3 {
-                                device_type = "ethernet-phy";
                                 compatible = "broadcom,bcm5421";
                                 interrupts = <76>;      /* GPP 12 */
                                 interrupt-parent = <&PIC>;
@@ -162,7 +159,6 @@
                 };
 
                 MPSC0: mpsc@8000 {
-                        device_type = "serial";
                         compatible = "marvell,mv64360-mpsc";
                         reg = <0x8000 0x38>;
                         virtual-reg = <0xf1008000>;
@@ -177,7 +173,6 @@
                 };
 
                 MPSC1: mpsc@9000 {
-                        device_type = "serial";
                         compatible = "marvell,mv64360-mpsc";
                         reg = <0x9000 0x38>;
                         virtual-reg = <0xf1009000>;
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index b1e45a8537a5..fc89e00b765c 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -173,14 +173,12 @@
                                         interrupt-parent = <&ipic>;
                                         interrupts = <20 0x8>;
                                         reg = <0x19>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 phy1: ethernet-phy@1a {
                                         interrupt-parent = <&ipic>;
                                         interrupts = <21 0x8>;
                                         reg = <0x1a>;
-                                        device_type = "ethernet-phy";
                                 };
 
                                 tbi0: tbi-phy@11 {
diff --git a/arch/powerpc/boot/dts/sbc8548-post.dtsi b/arch/powerpc/boot/dts/sbc8548-post.dtsi
index 33a47e27a11e..9b505c8e5350 100644
--- a/arch/powerpc/boot/dts/sbc8548-post.dtsi
+++ b/arch/powerpc/boot/dts/sbc8548-post.dtsi
@@ -137,13 +137,11 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <0x6 0x1>;
                                         reg = <0x19>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@1a {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <0x7 0x1>;
                                         reg = <0x1a>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index 56bebce87842..631ede72e226 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -230,25 +230,21 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <0x1f>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@0 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <0>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <10 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index b670d03fbcd9..78a72ee48205 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -161,13 +161,11 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 4>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy4: ethernet-phy@4 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 4>;
                                         reg = <4>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
index 4f166b01c1b6..859f854ba538 100644
--- a/arch/powerpc/boot/dts/stxssa8555.dts
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -164,13 +164,11 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy1: ethernet-phy@4 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <5 1>;
                                         reg = <0x4>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index ed264d9ae356..91cbd7acd276 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -172,19 +172,16 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index 925242115814..84dce2d5fc48 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -172,19 +172,16 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 6e1ac50852a4..7a333dd02d9c 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -185,31 +185,26 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy4: ethernet-phy@4 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <4>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy5: ethernet-phy@5 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <5>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 161e75eac7f7..c737caff10c7 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -185,31 +185,26 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@1 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy4: ethernet-phy@4 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <4>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy5: ethernet-phy@5 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <5>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index aa6ff0d3dd9a..d0416a5cdddf 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -172,19 +172,16 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 7665a16a8b9a..f9a11ebf736c 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -174,19 +174,16 @@
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <1>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy2: ethernet-phy@2 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <2>;
-                                        device_type = "ethernet-phy";
                                 };
                                 phy3: ethernet-phy@3 {
                                         interrupt-parent = <&mpic>;
                                         interrupts = <8 1>;
                                         reg = <3>;
-                                        device_type = "ethernet-phy";
                                 };
                                 tbi0: tbi-phy@11 {
                                         reg = <0x11>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
index c3dba2518d8c..3d1446b99c7e 100644
--- a/arch/powerpc/boot/dts/tqm8xx.dts
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -107,7 +107,6 @@
                         #size-cells = <0>;
                         PHY: ethernet-phy@f {
                                 reg = <0xf>;
-                                device_type = "ethernet-phy";
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
index fc7073bc547e..391a4e299783 100644
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -257,6 +257,8 @@
                         #size-cells = <1>;
                         compatible = "xlnx,compound";
                         ethernet@81c00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 compatible = "xlnx,xps-ll-temac-1.01.b";
                                 device_type = "network";
                                 interrupt-parent = <&xps_intc_0>;
diff --git a/arch/powerpc/boot/mvme5100.c b/arch/powerpc/boot/mvme5100.c
new file mode 100644
index 000000000000..cb865f83c60b
--- /dev/null
+++ b/arch/powerpc/boot/mvme5100.c
@@ -0,0 +1,27 @@
+/*
+ * Motorola/Emerson MVME5100 with PPCBug firmware.
+ *
+ * Author: Stephen Chivers <schivers@csc.com>
+ *
+ * Copyright 2013 CSC Australia Pty. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+#include "types.h"
+#include "ops.h"
+#include "io.h"
+
+BSS_STACK(4096);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
+{
+        u32                     heapsize;
+
+        heapsize = 0x8000000 - (u32)_end; /* 128M */
+        simple_alloc_init(_end, heapsize, 32, 64);
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 2e1af74a64be..d27a25518b01 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -265,6 +265,10 @@ epapr)
     link_address='0x20000000'
     pie=-pie
     ;;
+mvme5100)
+    platformo="$object/fixed-head.o $object/mvme5100.o"
+    binary=y
+    ;;
 esac
 
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
diff --git a/arch/powerpc/configs/85xx/p1023_defconfig b/arch/powerpc/configs/85xx/p1023_defconfig
deleted file mode 100644
index b06d37da44f4..000000000000
--- a/arch/powerpc/configs/85xx/p1023_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
-CONFIG_PPC_85xx=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_RCU_FANOUT=32
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_EMBEDDED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_PHYSICAL_START=0x00000000
-CONFIG_P1023_RDB=y
-CONFIG_P1023_RDS=y
-CONFIG_QUICC_ENGINE=y
-CONFIG_QE_GPIO=y
-CONFIG_CPM2=y
-CONFIG_HIGHMEM=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_MATH_EMULATION=y
-CONFIG_SWIOTLB=y
-CONFIG_PCI=y
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIEAER is not set
-# CONFIG_PCIEASPM is not set
-CONFIG_PCI_MSI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_ARPD=y
-CONFIG_INET_ESP=y
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_IP_SCTP=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_FSL_ELBC=y
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_LEGACY=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_ATA=y
-CONFIG_SATA_FSL=y
-CONFIG_SATA_SIL24=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_FS_ENET=y
-CONFIG_FSL_PQ_MDIO=y
-CONFIG_E1000E=y
-CONFIG_PHYLIB=y
-CONFIG_AT803X_PHY=y
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_FIXED_PHY=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_NVRAM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_CPM=m
-CONFIG_I2C_MPC=y
-CONFIG_GPIO_MPC8XXX=y
-# CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_EDAC=y
-CONFIG_EDAC_MM_EDAC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_DMA=y
-# CONFIG_NET_DMA is not set
-CONFIG_STAGING=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_CRC_T10DIF=y
-CONFIG_FRAME_WARN=8092
-CONFIG_DEBUG_FS=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_STRICT_DEVMEM=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/adder875_defconfig b/arch/powerpc/configs/adder875_defconfig
index 69128740c14d..15b1ff5d96e7 100644
--- a/arch/powerpc/configs/adder875_defconfig
+++ b/arch/powerpc/configs/adder875_defconfig
@@ -70,3 +70,4 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/ep88xc_defconfig b/arch/powerpc/configs/ep88xc_defconfig
index 219fd470ed22..b8a79d7ee89f 100644
--- a/arch/powerpc/configs/ep88xc_defconfig
+++ b/arch/powerpc/configs/ep88xc_defconfig
@@ -72,3 +72,4 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index d2e0fab5ee5b..83d3550fdb54 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -31,6 +31,7 @@ CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
+CONFIG_P1023_RDB=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
@@ -113,6 +114,7 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -211,6 +213,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
 # CONFIG_NET_DMA is not set
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4cb7b59e98bd..4b686294feb4 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -34,6 +34,7 @@ CONFIG_C293_PCIE=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
+CONFIG_P1023_RDB=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
@@ -116,6 +117,7 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -212,6 +214,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
 # CONFIG_NET_DMA is not set
diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig
index 5c258823e694..d954e80c286a 100644
--- a/arch/powerpc/configs/mpc866_ads_defconfig
+++ b/arch/powerpc/configs/mpc866_ads_defconfig
@@ -55,3 +55,4 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_CRC_CCITT=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig
index 9e146cdf63de..3f47d00a10c0 100644
--- a/arch/powerpc/configs/mpc885_ads_defconfig
+++ b/arch/powerpc/configs/mpc885_ads_defconfig
@@ -78,3 +78,4 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/configs/mvme5100_defconfig b/arch/powerpc/configs/mvme5100_defconfig
new file mode 100644
index 000000000000..93c7752e2dbb
--- /dev/null
+++ b/arch/powerpc/configs/mvme5100_defconfig
@@ -0,0 +1,144 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_PPC_CHRP is not set
+# CONFIG_PPC_PMAC is not set
+CONFIG_EMBEDDED6xx=y
+CONFIG_MVME5100=y
+CONFIG_KVM_GUEST=y
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_COMPACTION is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,9600 ip=dhcp root=/dev/nfs"
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_LAPB=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_EEPROM_LEGACY=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_E100=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=10
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MPC=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_VME_BUS=m
+CONFIG_VME_CA91CX42=m
+CONFIG_EXT2_FS=m
+CONFIG_EXT3_FS=m
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_XFS_FS=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_CIFS=m
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_UTF8=m
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 581a3bcae728..e015896b7e5c 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -186,6 +186,7 @@ CONFIG_SCSI_DH_RDAC=m
 CONFIG_SCSI_DH_ALUA=m
 CONFIG_ATA=y
 CONFIG_SATA_SIL24=y
+CONFIG_SATA_MV=y
 CONFIG_SATA_SVW=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=y
diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig
index 8616fde0896f..4b6f8bf104e0 100644
--- a/arch/powerpc/configs/tqm8xx_defconfig
+++ b/arch/powerpc/configs/tqm8xx_defconfig
@@ -84,3 +84,4 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_CRC32_SLICEBY4=y
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d8f9d2f18a23..6c0a955a1b06 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -3,4 +3,5 @@ generic-y += clkdev.h
 generic-y += rwsem.h
 generic-y += trace_clock.h
 generic-y += preempt.h
-generic-y += vtime.h
\ No newline at end of file
+generic-y += vtime.h
+generic-y += hash.h
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 910194e9a1e2..a5e9a7d494d8 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -46,6 +46,11 @@
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
 
+/* PPC bit number conversion */
+#define PPC_BITLSHIFT(be)       (BITS_PER_LONG - 1 - (be))
+#define PPC_BIT(bit)            (1UL << PPC_BITLSHIFT(bit))
+#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
+
 /*
  * clear_bit doesn't imply a memory barrier
  */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 9e495c9a6a88..ed0afc1e44a4 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -41,8 +41,20 @@ struct ppc64_caches {
 extern struct ppc64_caches ppc64_caches;
 #endif /* __powerpc64__ && ! __ASSEMBLY__ */
 
-#if !defined(__ASSEMBLY__)
+#if defined(__ASSEMBLY__)
+/*
+ * For a snooping icache, we still need a dummy icbi to purge all the
+ * prefetched instructions from the ifetch buffers. We also need a sync
+ * before the icbi to order the the actual stores to memory that might
+ * have modified instructions with the icbi.
+ */
+#define PURGE_PREFETCHED_INS    \
+        sync;                   \
+        icbi    0,r3;           \
+        sync;                   \
+        isync
 
+#else
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
 #ifdef CONFIG_6xx
diff --git a/arch/powerpc/include/asm/clk_interface.h b/arch/powerpc/include/asm/clk_interface.h
deleted file mode 100644
index ab1882c1e176..000000000000
--- a/arch/powerpc/include/asm/clk_interface.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_POWERPC_CLK_INTERFACE_H
-#define __ASM_POWERPC_CLK_INTERFACE_H
-
-#include <linux/clk.h>
-
-struct clk_interface {
-        struct clk*     (*clk_get)      (struct device *dev, const char *id);
-        int             (*clk_enable)   (struct clk *clk);
-        void            (*clk_disable)  (struct clk *clk);
-        unsigned long   (*clk_get_rate) (struct clk *clk);
-        void            (*clk_put)      (struct clk *clk);
-        long            (*clk_round_rate) (struct clk *clk, unsigned long rate);
-        int             (*clk_set_rate) (struct clk *clk, unsigned long rate);
-        int             (*clk_set_parent) (struct clk *clk, struct clk *parent);
-        struct clk*     (*clk_get_parent) (struct clk *clk);
-};
-
-extern struct clk_interface clk_functions;
-
-#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h
index e245aab7f191..d463c68fe7f0 100644
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -300,6 +300,7 @@ __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
         cmpxchg_local((ptr), (o), (n));                                 \
   })
+#define cmpxchg64_relaxed       cmpxchg64_local
 #else
 #include <asm-generic/cmpxchg-local.h>
 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index a6f8c7a5cbb7..97e02f985df8 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -34,6 +34,13 @@ int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
 unsigned long branch_target(const unsigned int *instr);
 unsigned int translate_branch(const unsigned int *dest,
                               const unsigned int *src);
+#ifdef CONFIG_PPC_BOOK3E_64
+void __patch_exception(int exc, unsigned long addr);
+#define patch_exception(exc, name) do { \
+        extern unsigned int name; \
+        __patch_exception((exc), (unsigned long)&name); \
+} while (0)
+#endif
 
 static inline unsigned long ppc_function_entry(void *func)
 {
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 0d4939ba48e7..617cc767c076 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -90,6 +90,18 @@ struct cpu_spec {
          * if the error is fatal, 1 if it was fully recovered and 0 to
          * pass up (not CPU originated) */
         int             (*machine_check)(struct pt_regs *regs);
+
+        /*
+         * Processor specific early machine check handler which is
+         * called in real mode to handle SLB and TLB errors.
+         */
+        long            (*machine_check_early)(struct pt_regs *regs);
+
+        /*
+         * Processor specific routine to flush tlbs.
+         */
+        void            (*flush_tlb)(unsigned long inval_selector);
+
 };
 
 extern struct cpu_spec          *cur_cpu_spec;
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index d3e5e9bc8f94..9e39ceb1d19f 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -90,7 +90,8 @@ struct eeh_pe {
 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 
-#define EEH_DEV_SYSFS           (1 << 8)        /* Sysfs created        */
+#define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
+#define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 
 struct eeh_dev {
         int mode;                       /* EEH mode                     */
@@ -117,6 +118,16 @@ static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
         return edev ? edev->pdev : NULL;
 }
 
+/* Return values from eeh_ops::next_error */
+enum {
+        EEH_NEXT_ERR_NONE = 0,
+        EEH_NEXT_ERR_INF,
+        EEH_NEXT_ERR_FROZEN_PE,
+        EEH_NEXT_ERR_FENCED_PHB,
+        EEH_NEXT_ERR_DEAD_PHB,
+        EEH_NEXT_ERR_DEAD_IOC
+};
+
 /*
  * The struct is used to trace the registered EEH operation
  * callback functions. Actually, those operation callback
@@ -157,6 +168,7 @@ struct eeh_ops {
         int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
         int (*write_config)(struct device_node *dn, int where, int size, u32 val);
         int (*next_error)(struct eeh_pe **pe);
+        int (*restore_config)(struct device_node *dn);
 };
 
 extern struct eeh_ops *eeh_ops;
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index 86b0ac79990c..334459ad145b 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -460,5 +460,116 @@ static inline unsigned int ev_idle(void)
 
         return r3;
 }
+
+#ifdef CONFIG_EPAPR_PARAVIRT
+static inline unsigned long epapr_hypercall(unsigned long *in,
+                            unsigned long *out,
+                            unsigned long nr)
+{
+        unsigned long register r0 asm("r0");
+        unsigned long register r3 asm("r3") = in[0];
+        unsigned long register r4 asm("r4") = in[1];
+        unsigned long register r5 asm("r5") = in[2];
+        unsigned long register r6 asm("r6") = in[3];
+        unsigned long register r7 asm("r7") = in[4];
+        unsigned long register r8 asm("r8") = in[5];
+        unsigned long register r9 asm("r9") = in[6];
+        unsigned long register r10 asm("r10") = in[7];
+        unsigned long register r11 asm("r11") = nr;
+        unsigned long register r12 asm("r12");
+
+        asm volatile("bl        epapr_hypercall_start"
+                     : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6),
+                       "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11),
+                       "=r"(r12)
+                     : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8),
+                       "r"(r9), "r"(r10), "r"(r11)
+                     : "memory", "cc", "xer", "ctr", "lr");
+
+        out[0] = r4;
+        out[1] = r5;
+        out[2] = r6;
+        out[3] = r7;
+        out[4] = r8;
+        out[5] = r9;
+        out[6] = r10;
+        out[7] = r11;
+
+        return r3;
+}
+#else
+static unsigned long epapr_hypercall(unsigned long *in,
+                                   unsigned long *out,
+                                   unsigned long nr)
+{
+        return EV_UNIMPLEMENTED;
+}
+#endif
+
+static inline long epapr_hypercall0_1(unsigned int nr, unsigned long *r2)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+        unsigned long r;
+
+        r = epapr_hypercall(in, out, nr);
+        *r2 = out[0];
+
+        return r;
+}
+
+static inline long epapr_hypercall0(unsigned int nr)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        return epapr_hypercall(in, out, nr);
+}
+
+static inline long epapr_hypercall1(unsigned int nr, unsigned long p1)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        return epapr_hypercall(in, out, nr);
+}
+
+static inline long epapr_hypercall2(unsigned int nr, unsigned long p1,
+                                    unsigned long p2)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        return epapr_hypercall(in, out, nr);
+}
+
+static inline long epapr_hypercall3(unsigned int nr, unsigned long p1,
+                                    unsigned long p2, unsigned long p3)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        in[2] = p3;
+        return epapr_hypercall(in, out, nr);
+}
+
+static inline long epapr_hypercall4(unsigned int nr, unsigned long p1,
+                                    unsigned long p2, unsigned long p3,
+                                    unsigned long p4)
+{
+        unsigned long in[8];
+        unsigned long out[8];
+
+        in[0] = p1;
+        in[1] = p2;
+        in[2] = p3;
+        in[3] = p4;
+        return epapr_hypercall(in, out, nr);
+}
 #endif /* !__ASSEMBLY__ */
 #endif /* _EPAPR_HCALLS_H */
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 243ce69ad685..66830618cc19 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -301,9 +301,12 @@ do_kvm_##n:								\
         beq     4f;                     /* if from kernel mode          */ \
         ACCOUNT_CPU_USER_ENTRY(r9, r10);                                   \
         SAVE_PPR(area, r9, r10);                                           \
-4:      std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
-        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
-        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
+4:      EXCEPTION_PROLOG_COMMON_2(area)                                    \
+        EXCEPTION_PROLOG_COMMON_3(n)                                       \
+        ACCOUNT_STOLEN_TIME
+
+/* Save original regs values from save area to stack frame. */
+#define EXCEPTION_PROLOG_COMMON_2(area)                                    \
         ld      r9,area+EX_R9(r13);     /* move r9, r10 to stackframe   */ \
         ld      r10,area+EX_R10(r13);                                      \
         std     r9,GPR9(r1);                                               \
@@ -318,11 +321,16 @@ do_kvm_##n:								\
         ld      r10,area+EX_CFAR(r13);                                     \
         std     r10,ORIG_GPR3(r1);                                         \
         END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);            \
+        GET_CTR(r10, area);                                                \
+        std     r10,_CTR(r1);
+
+#define EXCEPTION_PROLOG_COMMON_3(n)                                       \
+        std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
         mflr    r9;                     /* Get LR, later save to stack  */ \
         ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
         std     r9,_LINK(r1);                                              \
-        GET_CTR(r10, area);                                                \
-        std     r10,_CTR(r1);                                              \
         lbz     r10,PACASOFTIRQEN(r13);                            \
         mfspr   r11,SPRN_XER;           /* save XER in stackframe       */ \
         std     r10,SOFTE(r1);                                             \
@@ -332,8 +340,7 @@ do_kvm_##n:								\
         li      r10,0;                                                     \
         ld      r11,exception_marker@toc(r2);                              \
         std     r10,RESULT(r1);         /* clear regs->result           */ \
-        std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */ \
-        ACCOUNT_STOLEN_TIME
+        std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
 
 /*
  * Exception vectors.
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index 5c2c0233175e..90f604bbcd19 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -58,52 +58,12 @@ enum fixed_addresses {
 extern void __set_fixmap (enum fixed_addresses idx,
                                         phys_addr_t phys, pgprot_t flags);
 
-#define set_fixmap(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL_NCG)
-
-#define clear_fixmap(idx) \
-                __set_fixmap(idx, 0, __pgprot(0))
-
 #define __FIXADDR_SIZE  (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START           (FIXADDR_TOP - __FIXADDR_SIZE)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
+#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NCG
 
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #endif /* !__ASSEMBLY__ */
 #endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 420b45368fcf..067fb0dca549 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -285,7 +285,7 @@ struct fsl_lbc_ctrl {
         /* device info */
         struct device                   *dev;
         struct fsl_lbc_regs __iomem     *regs;
-        int                             irq;
+        int                             irq[2];
         wait_queue_head_t               irq_wait;
         spinlock_t                      lock;
         void                            *nand;
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 3bdcfce2c42a..418fb654370d 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -6,7 +6,8 @@
 
 typedef struct {
         unsigned int __softirq_pending;
-        unsigned int timer_irqs;
+        unsigned int timer_irqs_event;
+        unsigned int timer_irqs_others;
         unsigned int pmu_irqs;
         unsigned int mce_exceptions;
         unsigned int spurious_irqs;
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 575fbf81fad0..97d3869991ca 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -191,8 +191,24 @@ DEF_MMIO_OUT_D(out_le32, 32, stw);
 
 #endif /* __BIG_ENDIAN */
 
+/*
+ * Cache inhibitied accessors for use in real mode, you don't want to use these
+ * unless you know what you're doing.
+ *
+ * NB. These use the cpu byte ordering.
+ */
+DEF_MMIO_OUT_X(out_rm8,   8, stbcix);
+DEF_MMIO_OUT_X(out_rm16, 16, sthcix);
+DEF_MMIO_OUT_X(out_rm32, 32, stwcix);
+DEF_MMIO_IN_X(in_rm8,   8, lbzcix);
+DEF_MMIO_IN_X(in_rm16, 16, lhzcix);
+DEF_MMIO_IN_X(in_rm32, 32, lwzcix);
+
 #ifdef __powerpc64__
 
+DEF_MMIO_OUT_X(out_rm64, 64, stdcix);
+DEF_MMIO_IN_X(in_rm64, 64, ldcix);
+
 #ifdef __BIG_ENDIAN__
 DEF_MMIO_OUT_D(out_be64, 64, std);
 DEF_MMIO_IN_D(in_be64, 64, ld);
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index c34656a8925e..f7a8036579b5 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -30,22 +30,19 @@
 #include <asm/machdep.h>
 #include <asm/types.h>
 
-#define IOMMU_PAGE_SHIFT      12
-#define IOMMU_PAGE_SIZE       (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
-#define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
-#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
+#define IOMMU_PAGE_SHIFT_4K      12
+#define IOMMU_PAGE_SIZE_4K       (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
+#define IOMMU_PAGE_MASK_4K       (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
+#define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K)
+
+#define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
+#define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
+#define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr))
 
 /* Boot time flags */
 extern int iommu_is_off;
 extern int iommu_force_on;
 
-/* Pure 2^n version of get_order */
-static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
-{
-        return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
-}
-
-
 /*
  * IOMAP_MAX_ORDER defines the largest contiguous block
  * of dma space we can get.  IOMAP_MAX_ORDER = 13
@@ -76,11 +73,20 @@ struct iommu_table {
         struct iommu_pool large_pool;
         struct iommu_pool pools[IOMMU_NR_POOLS];
         unsigned long *it_map;       /* A simple allocation bitmap for now */
+        unsigned long  it_page_shift;/* table iommu page size */
 #ifdef CONFIG_IOMMU_API
         struct iommu_group *it_group;
 #endif
 };
 
+/* Pure 2^n version of get_order */
+static inline __attribute_const__
+int get_iommu_order(unsigned long size, struct iommu_table *tbl)
+{
+        return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
+}
+
+
 struct scatterlist;
 
 static inline void set_iommu_table_base(struct device *dev, void *base)
@@ -101,8 +107,34 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
  */
 extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
                                             int nid);
+#ifdef CONFIG_IOMMU_API
 extern void iommu_register_group(struct iommu_table *tbl,
                                  int pci_domain_number, unsigned long pe_num);
+extern int iommu_add_device(struct device *dev);
+extern void iommu_del_device(struct device *dev);
+#else
+static inline void iommu_register_group(struct iommu_table *tbl,
+                                        int pci_domain_number,
+                                        unsigned long pe_num)
+{
+}
+
+static inline int iommu_add_device(struct device *dev)
+{
+        return 0;
+}
+
+static inline void iommu_del_device(struct device *dev)
+{
+}
+#endif /* !CONFIG_IOMMU_API */
+
+static inline void set_iommu_table_base_and_group(struct device *dev,
+                                                  void *base)
+{
+        set_iommu_table_base(dev, base);
+        iommu_add_device(dev);
+}
 
 extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                         struct scatterlist *sglist, int nelems,
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 1bd92fd43cfb..19eb74a95b59 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -74,6 +74,7 @@
 #define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39
 #define BOOKE_INTERRUPT_HV_SYSCALL 40
 #define BOOKE_INTERRUPT_HV_PRIV 41
+#define BOOKE_INTERRUPT_LRAT_ERROR 42
 
 /* book3s */
 
@@ -91,14 +92,17 @@
 #define BOOK3S_INTERRUPT_FP_UNAVAIL     0x800
 #define BOOK3S_INTERRUPT_DECREMENTER    0x900
 #define BOOK3S_INTERRUPT_HV_DECREMENTER 0x980
+#define BOOK3S_INTERRUPT_DOORBELL       0xa00
 #define BOOK3S_INTERRUPT_SYSCALL        0xc00
 #define BOOK3S_INTERRUPT_TRACE          0xd00
 #define BOOK3S_INTERRUPT_H_DATA_STORAGE 0xe00
 #define BOOK3S_INTERRUPT_H_INST_STORAGE 0xe20
 #define BOOK3S_INTERRUPT_H_EMUL_ASSIST  0xe40
+#define BOOK3S_INTERRUPT_H_DOORBELL     0xe80
 #define BOOK3S_INTERRUPT_PERFMON        0xf00
 #define BOOK3S_INTERRUPT_ALTIVEC        0xf20
 #define BOOK3S_INTERRUPT_VSX            0xf40
+#define BOOK3S_INTERRUPT_H_FAC_UNAVAIL  0xf80
 
 #define BOOK3S_IRQPRIO_SYSTEM_RESET             0
 #define BOOK3S_IRQPRIO_DATA_SEGMENT             1
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index bc23b1ba7980..83851aabfdc8 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -186,9 +186,6 @@ extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,
 
 extern void kvmppc_entry_trampoline(void);
 extern void kvmppc_hv_entry_trampoline(void);
-extern void kvmppc_load_up_fpu(void);
-extern void kvmppc_load_up_altivec(void);
-extern void kvmppc_load_up_vsx(void);
 extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);
 extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst);
 extern int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd);
@@ -271,16 +268,25 @@ static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
         return vcpu->arch.pc;
 }
 
-static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
+static inline bool kvmppc_need_byteswap(struct kvm_vcpu *vcpu)
 {
-        ulong pc = kvmppc_get_pc(vcpu);
+        return (vcpu->arch.shared->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
+}
 
+static inline u32 kvmppc_get_last_inst_internal(struct kvm_vcpu *vcpu, ulong pc)
+{
         /* Load the instruction manually if it failed to do so in the
          * exit path */
         if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED)
                 kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false);
 
-        return vcpu->arch.last_inst;
+        return kvmppc_need_byteswap(vcpu) ? swab32(vcpu->arch.last_inst) :
+                vcpu->arch.last_inst;
+}
+
+static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
+{
+        return kvmppc_get_last_inst_internal(vcpu, kvmppc_get_pc(vcpu));
 }
 
 /*
@@ -290,14 +296,7 @@ static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
  */
 static inline u32 kvmppc_get_last_sc(struct kvm_vcpu *vcpu)
 {
-        ulong pc = kvmppc_get_pc(vcpu) - 4;
-
-        /* Load the instruction manually if it failed to do so in the
-         * exit path */
-        if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED)
-                kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false);
-
-        return vcpu->arch.last_inst;
+        return kvmppc_get_last_inst_internal(vcpu, kvmppc_get_pc(vcpu) - 4);
 }
 
 static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 192917d2239c..f3a91dc02c98 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -88,6 +88,7 @@ struct kvmppc_host_state {
         u8 hwthread_req;
         u8 hwthread_state;
         u8 host_ipi;
+        u8 ptid;
         struct kvm_vcpu *kvm_vcpu;
         struct kvmppc_vcore *kvm_vcore;
         unsigned long xics_phys;
diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h
index dd8f61510dfd..80d46b5a7efb 100644
--- a/arch/powerpc/include/asm/kvm_booke.h
+++ b/arch/powerpc/include/asm/kvm_booke.h
@@ -63,6 +63,12 @@ static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
         return vcpu->arch.xer;
 }
 
+static inline bool kvmppc_need_byteswap(struct kvm_vcpu *vcpu)
+{
+        /* XXX Would need to check TLB entry */
+        return false;
+}
+
 static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
 {
         return vcpu->arch.last_inst;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 237d1d25b448..1eaea2dea174 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -288,6 +288,7 @@ struct kvmppc_vcore {
         int n_woken;
         int nap_count;
         int napping_threads;
+        int first_vcpuid;
         u16 pcpu;
         u16 last_cpu;
         u8 vcore_state;
@@ -298,10 +299,12 @@ struct kvmppc_vcore {
         u64 stolen_tb;
         u64 preempt_tb;
         struct kvm_vcpu *runner;
+        struct kvm *kvm;
         u64 tb_offset;          /* guest timebase - host timebase */
         ulong lpcr;
         u32 arch_compat;
         ulong pcr;
+        ulong dpdes;            /* doorbell state (POWER8) */
 };
 
 #define VCORE_ENTRY_COUNT(vc)   ((vc)->entry_exit_count & 0xff)
@@ -410,8 +413,7 @@ struct kvm_vcpu_arch {
 
         ulong gpr[32];
 
-        u64 fpr[32];
-        u64 fpscr;
+        struct thread_fp_state fp;
 
 #ifdef CONFIG_SPE
         ulong evr[32];
@@ -420,12 +422,7 @@ struct kvm_vcpu_arch {
         u64 acc;
 #endif
 #ifdef CONFIG_ALTIVEC
-        vector128 vr[32];
-        vector128 vscr;
-#endif
-
-#ifdef CONFIG_VSX
-        u64 vsr[64];
+        struct thread_vr_state vr;
 #endif
 
 #ifdef CONFIG_KVM_BOOKE_HV
@@ -452,6 +449,7 @@ struct kvm_vcpu_arch {
         ulong pc;
         ulong ctr;
         ulong lr;
+        ulong tar;
 
         ulong xer;
         u32 cr;
@@ -461,13 +459,30 @@ struct kvm_vcpu_arch {
         ulong guest_owned_ext;
         ulong purr;
         ulong spurr;
+        ulong ic;
+        ulong vtb;
         ulong dscr;
         ulong amr;
         ulong uamor;
+        ulong iamr;
         u32 ctrl;
+        u32 dabrx;
         ulong dabr;
+        ulong dawr;
+        ulong dawrx;
+        ulong ciabr;
         ulong cfar;
         ulong ppr;
+        ulong pspb;
+        ulong fscr;
+        ulong ebbhr;
+        ulong ebbrr;
+        ulong bescr;
+        ulong csigr;
+        ulong tacr;
+        ulong tcscr;
+        ulong acop;
+        ulong wort;
         ulong shadow_srr1;
 #endif
         u32 vrsave; /* also USPRG0 */
@@ -502,10 +517,33 @@ struct kvm_vcpu_arch {
         u32 ccr1;
         u32 dbsr;
 
-        u64 mmcr[3];
+        u64 mmcr[5];
         u32 pmc[8];
+        u32 spmc[2];
         u64 siar;
         u64 sdar;
+        u64 sier;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        u64 tfhar;
+        u64 texasr;
+        u64 tfiar;
+
+        u32 cr_tm;
+        u64 lr_tm;
+        u64 ctr_tm;
+        u64 amr_tm;
+        u64 ppr_tm;
+        u64 dscr_tm;
+        u64 tar_tm;
+
+        ulong gpr_tm[32];
+
+        struct thread_fp_state fp_tm;
+
+        struct thread_vr_state vr_tm;
+        u32 vrsave_tm; /* also USPRG0 */
+
+#endif
 
 #ifdef CONFIG_KVM_EXIT_TIMING
         struct mutex exit_timing_lock;
@@ -546,6 +584,7 @@ struct kvm_vcpu_arch {
 #endif
         gpa_t paddr_accessed;
         gva_t vaddr_accessed;
+        pgd_t *pgdir;
 
         u8 io_gpr; /* GPR used as IO source/target */
         u8 mmio_is_bigendian;
@@ -603,7 +642,6 @@ struct kvm_vcpu_arch {
         struct list_head run_list;
         struct task_struct *run_task;
         struct kvm_run *kvm_run;
-        pgd_t *pgdir;
 
         spinlock_t vpa_update_lock;
         struct kvmppc_vpa vpa;
@@ -616,9 +654,12 @@ struct kvm_vcpu_arch {
         spinlock_t tbacct_lock;
         u64 busy_stolen;
         u64 busy_preempt;
+        unsigned long intr_msr;
 #endif
 };
 
+#define VCPU_FPR(vcpu, i)       (vcpu)->arch.fp.fpr[i][TS_FPROFFSET]
+
 /* Values for vcpu->arch.state */
 #define KVMPPC_VCPU_NOTREADY            0
 #define KVMPPC_VCPU_RUNNABLE            1
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
index 2b119654b4c1..336a91acb8b1 100644
--- a/arch/powerpc/include/asm/kvm_para.h
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -39,10 +39,6 @@ static inline int kvm_para_available(void)
         return 1;
 }
 
-extern unsigned long kvm_hypercall(unsigned long *in,
-                                   unsigned long *out,
-                                   unsigned long nr);
-
 #else
 
 static inline int kvm_para_available(void)
@@ -50,82 +46,8 @@ static inline int kvm_para_available(void)
         return 0;
 }
 
-static unsigned long kvm_hypercall(unsigned long *in,
-                                   unsigned long *out,
-                                   unsigned long nr)
-{
-        return EV_UNIMPLEMENTED;
-}
-
 #endif
 
-static inline long kvm_hypercall0_1(unsigned int nr, unsigned long *r2)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-        unsigned long r;
-
-        r = kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-        *r2 = out[0];
-
-        return r;
-}
-
-static inline long kvm_hypercall0(unsigned int nr)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-
-        return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-}
-
-static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-
-        in[0] = p1;
-        return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-}
-
-static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
-                                  unsigned long p2)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-
-        in[0] = p1;
-        in[1] = p2;
-        return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-}
-
-static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
-                                  unsigned long p2, unsigned long p3)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-
-        in[0] = p1;
-        in[1] = p2;
-        in[2] = p3;
-        return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-}
-
-static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
-                                  unsigned long p2, unsigned long p3,
-                                  unsigned long p4)
-{
-        unsigned long in[8];
-        unsigned long out[8];
-
-        in[0] = p1;
-        in[1] = p2;
-        in[2] = p3;
-        in[3] = p4;
-        return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
-}
-
-
 static inline unsigned int kvm_arch_para_features(void)
 {
         unsigned long r;
@@ -133,7 +55,7 @@ static inline unsigned int kvm_arch_para_features(void)
         if (!kvm_para_available())
                 return 0;
 
-        if(kvm_hypercall0_1(KVM_HC_FEATURES, &r))
+        if(epapr_hypercall0_1(KVM_HCALL_TOKEN(KVM_HC_FEATURES), &r))
                 return 0;
 
         return r;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index c8317fbf92c4..fcd53f0d34ba 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -54,12 +54,13 @@ extern void kvmppc_handler_highmem(void);
 extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
 extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                               unsigned int rt, unsigned int bytes,
-                              int is_bigendian);
+                              int is_default_endian);
 extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                unsigned int rt, unsigned int bytes,
-                               int is_bigendian);
+                               int is_default_endian);
 extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                               u64 val, unsigned int bytes, int is_bigendian);
+                               u64 val, unsigned int bytes,
+                               int is_default_endian);
 
 extern int kvmppc_emulate_instruction(struct kvm_run *run,
                                       struct kvm_vcpu *vcpu);
@@ -455,6 +456,12 @@ static inline void kvmppc_fix_ee_before_entry(void)
         trace_hardirqs_on();
 
 #ifdef CONFIG_PPC64
+        /*
+         * To avoid races, the caller must have gone directly from having
+         * interrupts fully-enabled to hard-disabled.
+         */
+        WARN_ON(local_paca->irq_happened != PACA_IRQ_HARD_DIS);
+
         /* Only need to enable IRQs by hard enabling them after this */
         local_paca->irq_happened = 0;
         local_paca->soft_enabled = 1;
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 844c28de7ec0..d0a2a2f99564 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -132,8 +132,6 @@ struct slb_shadow {
         } save_area[SLB_NUM_BOLTED];
 } ____cacheline_aligned;
 
-extern struct slb_shadow slb_shadow[];
-
 /*
  * Layout of entries in the hypervisor's dispatch trace log buffer.
  */
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
new file mode 100644
index 000000000000..8e99edf6d966
--- /dev/null
+++ b/arch/powerpc/include/asm/mce.h
@@ -0,0 +1,197 @@
+/*
+ * Machine check exception header file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2013 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#ifndef __ASM_PPC64_MCE_H__
+#define __ASM_PPC64_MCE_H__
+
+#include <linux/bitops.h>
+
+/*
+ * Machine Check bits on power7 and power8
+ */
+#define P7_SRR1_MC_LOADSTORE(srr1)      ((srr1) & PPC_BIT(42)) /* P8 too */
+
+/* SRR1 bits for machine check (On Power7 and Power8) */
+#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
+
+#define P7_SRR1_MC_IFETCH_UE            (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
+#define P7_SRR1_MC_IFETCH_SLB_PARITY    (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
+#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT  (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
+#define P7_SRR1_MC_IFETCH_SLB_BOTH      (0x4 << PPC_BITLSHIFT(45))
+#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT  (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
+#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
+#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL       (0x7 << PPC_BITLSHIFT(45))
+
+/* SRR1 bits for machine check (On Power8) */
+#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
+
+/* DSISR bits for machine check (On Power7 and Power8) */
+#define P7_DSISR_MC_UE                  (PPC_BIT(48))   /* P8 too */
+#define P7_DSISR_MC_UE_TABLEWALK        (PPC_BIT(49))   /* P8 too */
+#define P7_DSISR_MC_ERAT_MULTIHIT       (PPC_BIT(52))   /* P8 too */
+#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB  (PPC_BIT(53))   /* P8 too */
+#define P7_DSISR_MC_SLB_PARITY_MFSLB    (PPC_BIT(55))   /* P8 too */
+#define P7_DSISR_MC_SLB_MULTIHIT        (PPC_BIT(56))   /* P8 too */
+#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57))   /* P8 too */
+
+/*
+ * DSISR bits for machine check (Power8) in addition to above.
+ * Secondary DERAT Multihit
+ */
+#define P8_DSISR_MC_ERAT_MULTIHIT_SEC   (PPC_BIT(54))
+
+/* SLB error bits */
+#define P7_DSISR_MC_SLB_ERRORS          (P7_DSISR_MC_ERAT_MULTIHIT | \
+                                         P7_DSISR_MC_SLB_PARITY_MFSLB | \
+                                         P7_DSISR_MC_SLB_MULTIHIT | \
+                                         P7_DSISR_MC_SLB_MULTIHIT_PARITY)
+
+#define P8_DSISR_MC_SLB_ERRORS          (P7_DSISR_MC_SLB_ERRORS | \
+                                         P8_DSISR_MC_ERAT_MULTIHIT_SEC)
+enum MCE_Version {
+        MCE_V1 = 1,
+};
+
+enum MCE_Severity {
+        MCE_SEV_NO_ERROR = 0,
+        MCE_SEV_WARNING = 1,
+        MCE_SEV_ERROR_SYNC = 2,
+        MCE_SEV_FATAL = 3,
+};
+
+enum MCE_Disposition {
+        MCE_DISPOSITION_RECOVERED = 0,
+        MCE_DISPOSITION_NOT_RECOVERED = 1,
+};
+
+enum MCE_Initiator {
+        MCE_INITIATOR_UNKNOWN = 0,
+        MCE_INITIATOR_CPU = 1,
+};
+
+enum MCE_ErrorType {
+        MCE_ERROR_TYPE_UNKNOWN = 0,
+        MCE_ERROR_TYPE_UE = 1,
+        MCE_ERROR_TYPE_SLB = 2,
+        MCE_ERROR_TYPE_ERAT = 3,
+        MCE_ERROR_TYPE_TLB = 4,
+};
+
+enum MCE_UeErrorType {
+        MCE_UE_ERROR_INDETERMINATE = 0,
+        MCE_UE_ERROR_IFETCH = 1,
+        MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
+        MCE_UE_ERROR_LOAD_STORE = 3,
+        MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
+};
+
+enum MCE_SlbErrorType {
+        MCE_SLB_ERROR_INDETERMINATE = 0,
+        MCE_SLB_ERROR_PARITY = 1,
+        MCE_SLB_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_EratErrorType {
+        MCE_ERAT_ERROR_INDETERMINATE = 0,
+        MCE_ERAT_ERROR_PARITY = 1,
+        MCE_ERAT_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_TlbErrorType {
+        MCE_TLB_ERROR_INDETERMINATE = 0,
+        MCE_TLB_ERROR_PARITY = 1,
+        MCE_TLB_ERROR_MULTIHIT = 2,
+};
+
+struct machine_check_event {
+        enum MCE_Version        version:8;      /* 0x00 */
+        uint8_t                 in_use;         /* 0x01 */
+        enum MCE_Severity       severity:8;     /* 0x02 */
+        enum MCE_Initiator      initiator:8;    /* 0x03 */
+        enum MCE_ErrorType      error_type:8;   /* 0x04 */
+        enum MCE_Disposition    disposition:8;  /* 0x05 */
+        uint8_t                 reserved_1[2];  /* 0x06 */
+        uint64_t                gpr3;           /* 0x08 */
+        uint64_t                srr0;           /* 0x10 */
+        uint64_t                srr1;           /* 0x18 */
+        union {                                 /* 0x20 */
+                struct {
+                        enum MCE_UeErrorType ue_error_type:8;
+                        uint8_t         effective_address_provided;
+                        uint8_t         physical_address_provided;
+                        uint8_t         reserved_1[5];
+                        uint64_t        effective_address;
+                        uint64_t        physical_address;
+                        uint8_t         reserved_2[8];
+                } ue_error;
+
+                struct {
+                        enum MCE_SlbErrorType slb_error_type:8;
+                        uint8_t         effective_address_provided;
+                        uint8_t         reserved_1[6];
+                        uint64_t        effective_address;
+                        uint8_t         reserved_2[16];
+                } slb_error;
+
+                struct {
+                        enum MCE_EratErrorType erat_error_type:8;
+                        uint8_t         effective_address_provided;
+                        uint8_t         reserved_1[6];
+                        uint64_t        effective_address;
+                        uint8_t         reserved_2[16];
+                } erat_error;
+
+                struct {
+                        enum MCE_TlbErrorType tlb_error_type:8;
+                        uint8_t         effective_address_provided;
+                        uint8_t         reserved_1[6];
+                        uint64_t        effective_address;
+                        uint8_t         reserved_2[16];
+                } tlb_error;
+        } u;
+};
+
+struct mce_error_info {
+        enum MCE_ErrorType error_type:8;
+        union {
+                enum MCE_UeErrorType ue_error_type:8;
+                enum MCE_SlbErrorType slb_error_type:8;
+                enum MCE_EratErrorType erat_error_type:8;
+                enum MCE_TlbErrorType tlb_error_type:8;
+        } u;
+        uint8_t         reserved[2];
+};
+
+#define MAX_MC_EVT      100
+
+/* Release flags for get_mce_event() */
+#define MCE_EVENT_RELEASE       true
+#define MCE_EVENT_DONTRELEASE   false
+
+extern void save_mce_event(struct pt_regs *regs, long handled,
+                           struct mce_error_info *mce_err, uint64_t addr);
+extern int get_mce_event(struct machine_check_event *mce, bool release);
+extern void release_mce_event(void);
+extern void machine_check_queue_event(void);
+extern void machine_check_print_event_info(struct machine_check_event *evt);
+extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
+
+#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 936db360790a..89b785d16846 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -286,8 +286,21 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 extern int mmu_linear_psize;
 extern int mmu_vmemmap_psize;
 
+struct tlb_core_data {
+        /* For software way selection, as on Freescale TLB1 */
+        u8 esel_next, esel_max, esel_first;
+
+        /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
+        u8 lock;
+};
+
 #ifdef CONFIG_PPC64
 extern unsigned long linear_map_top;
+extern int book3e_htw_mode;
+
+#define PPC_HTW_NONE    0
+#define PPC_HTW_IBM     1
+#define PPC_HTW_E6500   2
 
 /*
  * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 691fd8aca939..f8d1d6dcf7db 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -180,16 +180,17 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 #define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
 #define MMU_PAGE_256K   4
 #define MMU_PAGE_1M     5
-#define MMU_PAGE_4M     6
-#define MMU_PAGE_8M     7
-#define MMU_PAGE_16M    8
-#define MMU_PAGE_64M    9
-#define MMU_PAGE_256M   10
-#define MMU_PAGE_1G     11
-#define MMU_PAGE_16G    12
-#define MMU_PAGE_64G    13
-
-#define MMU_PAGE_COUNT  14
+#define MMU_PAGE_2M     6
+#define MMU_PAGE_4M     7
+#define MMU_PAGE_8M     8
+#define MMU_PAGE_16M    9
+#define MMU_PAGE_64M    10
+#define MMU_PAGE_256M   11
+#define MMU_PAGE_1G     12
+#define MMU_PAGE_16G    13
+#define MMU_PAGE_64G    14
+
+#define MMU_PAGE_COUNT  15
 
 #if defined(CONFIG_PPC_STD_MMU_64)
 /* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 887d3d6133e3..4a69cd1d5041 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -37,7 +37,12 @@ struct mpc512x_ccm {
         u32     cccr;   /* CFM Clock Control Register */
         u32     dccr;   /* DIU Clock Control Register */
         u32     mscan_ccr[4];   /* MSCAN Clock Control Registers */
-        u8      res[0x98]; /* Reserved */
+        u32     out_ccr[4];     /* OUT CLK Configure Registers */
+        u32     rsv0[2];        /* Reserved */
+        u32     scfr3;          /* System Clock Frequency Register 3 */
+        u32     rsv1[3];        /* Reserved */
+        u32     spll_lock_cnt;  /* System PLL Lock Counter */
+        u8      res[0x6c];      /* Reserved */
 };
 
 /*
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 7bdcf340016c..40157e2ca691 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -33,6 +33,28 @@ struct opal_takeover_args {
         u64     rd_loc;                 /* r11 */
 };
 
+/*
+ * SG entry
+ *
+ * WARNING: The current implementation requires each entry
+ * to represent a block that is 4k aligned *and* each block
+ * size except the last one in the list to be as well.
+ */
+struct opal_sg_entry {
+        void    *data;
+        long    length;
+};
+
+/* sg list */
+struct opal_sg_list {
+        unsigned long num_entries;
+        struct opal_sg_list *next;
+        struct opal_sg_entry entry[];
+};
+
+/* We calculate number of sg entries based on PAGE_SIZE */
+#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
+
 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
 
 extern long opal_do_takeover(struct opal_takeover_args *args);
@@ -132,6 +154,9 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_FLASH_VALIDATE                     76
 #define OPAL_FLASH_MANAGE                       77
 #define OPAL_FLASH_UPDATE                       78
+#define OPAL_GET_MSG                            85
+#define OPAL_CHECK_ASYNC_COMPLETION             86
+#define OPAL_SYNC_HOST_REBOOT                   87
 
 #ifndef __ASSEMBLY__
 
@@ -211,7 +236,16 @@ enum OpalPendingState {
         OPAL_EVENT_ERROR_LOG            = 0x40,
         OPAL_EVENT_EPOW                 = 0x80,
         OPAL_EVENT_LED_STATUS           = 0x100,
-        OPAL_EVENT_PCI_ERROR            = 0x200
+        OPAL_EVENT_PCI_ERROR            = 0x200,
+        OPAL_EVENT_MSG_PENDING          = 0x800,
+};
+
+enum OpalMessageType {
+        OPAL_MSG_ASYNC_COMP             = 0,
+        OPAL_MSG_MEM_ERR,
+        OPAL_MSG_EPOW,
+        OPAL_MSG_SHUTDOWN,
+        OPAL_MSG_TYPE_MAX,
 };
 
 /* Machine check related definitions */
@@ -311,12 +345,16 @@ enum OpalMveEnableAction {
         OPAL_ENABLE_MVE = 1
 };
 
-enum OpalPciResetAndReinitScope {
+enum OpalPciResetScope {
         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
         OPAL_PCI_IODA_TABLE_RESET = 6,
 };
 
+enum OpalPciReinitScope {
+        OPAL_REINIT_PCI_DEV = 1000
+};
+
 enum OpalPciResetState {
         OPAL_DEASSERT_RESET = 0,
         OPAL_ASSERT_RESET = 1
@@ -356,6 +394,12 @@ enum OpalLPCAddressType {
         OPAL_LPC_FW     = 2,
 };
 
+struct opal_msg {
+        uint32_t msg_type;
+        uint32_t reserved;
+        uint64_t params[8];
+};
+
 struct opal_machine_check_event {
         enum OpalMCE_Version    version:8;      /* 0x00 */
         uint8_t                 in_use;         /* 0x01 */
@@ -404,6 +448,58 @@ struct opal_machine_check_event {
         } u;
 };
 
+/* FSP memory errors handling */
+enum OpalMemErr_Version {
+        OpalMemErr_V1 = 1,
+};
+
+enum OpalMemErrType {
+        OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
+        OPAL_MEM_ERR_TYPE_DYN_DALLOC,
+        OPAL_MEM_ERR_TYPE_SCRUB,
+};
+
+/* Memory Reilience error type */
+enum OpalMemErr_ResilErrType {
+        OPAL_MEM_RESILIENCE_CE          = 0,
+        OPAL_MEM_RESILIENCE_UE,
+        OPAL_MEM_RESILIENCE_UE_SCRUB,
+};
+
+/* Dynamic Memory Deallocation type */
+enum OpalMemErr_DynErrType {
+        OPAL_MEM_DYNAMIC_DEALLOC        = 0,
+};
+
+/* OpalMemoryErrorData->flags */
+#define OPAL_MEM_CORRECTED_ERROR        0x0001
+#define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
+#define OPAL_MEM_ACK_REQUIRED           0x8000
+
+struct OpalMemoryErrorData {
+        enum OpalMemErr_Version version:8;      /* 0x00 */
+        enum OpalMemErrType     type:8;         /* 0x01 */
+        uint16_t                flags;          /* 0x02 */
+        uint8_t                 reserved_1[4];  /* 0x04 */
+
+        union {
+                /* Memory Resilience corrected/uncorrected error info */
+                struct {
+                        enum OpalMemErr_ResilErrType resil_err_type:8;
+                        uint8_t         reserved_1[7];
+                        uint64_t        physical_address_start;
+                        uint64_t        physical_address_end;
+                } resilience;
+                /* Dynamic memory deallocation error info */
+                struct {
+                        enum OpalMemErr_DynErrType dyn_err_type:8;
+                        uint8_t         reserved_1[7];
+                        uint64_t        physical_address_start;
+                        uint64_t        physical_address_end;
+                } dyn_dealloc;
+        } u;
+};
+
 enum {
         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
@@ -710,7 +806,7 @@ int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
                                     uint64_t diag_buffer_len);
 int64_t opal_pci_fence_phb(uint64_t phb_id);
-int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
+int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 int64_t opal_get_epow_status(__be64 *status);
@@ -731,6 +827,10 @@ int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 int64_t opal_manage_flash(uint8_t op);
 int64_t opal_update_flash(uint64_t blk_list);
 
+int64_t opal_get_msg(uint64_t buffer, size_t size);
+int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
+int64_t opal_sync_host_reboot(void);
+
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 
@@ -744,6 +844,8 @@ extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
                                    int depth, void *data);
 
 extern int opal_notifier_register(struct notifier_block *nb);
+extern int opal_message_notifier_register(enum OpalMessageType msg_type,
+                                                struct notifier_block *nb);
 extern void opal_notifier_enable(void);
 extern void opal_notifier_disable(void);
 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index b6ea9e068c13..9c5dbc3833fb 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -16,7 +16,6 @@
 
 #ifdef CONFIG_PPC64
 
-#include <linux/init.h>
 #include <asm/types.h>
 #include <asm/lppaca.h>
 #include <asm/mmu.h>
@@ -113,6 +112,10 @@ struct paca_struct {
         /* Keep pgd in the same cacheline as the start of extlb */
         pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
         pgd_t *kernel_pgd;              /* Kernel PGD */
+
+        /* Shared by all threads of a core -- points to tcd of first thread */
+        struct tlb_core_data *tcd_ptr;
+
         /* We can have up to 3 levels of reentrancy in the TLB miss handler */
         u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
         u64 exmc[8];            /* used for machine checks */
@@ -123,6 +126,8 @@ struct paca_struct {
         void *mc_kstack;
         void *crit_kstack;
         void *dbg_kstack;
+
+        struct tlb_core_data tcd;
 #endif /* CONFIG_PPC_BOOK3E */
 
         mm_context_t context;
@@ -152,6 +157,15 @@ struct paca_struct {
          */
         struct opal_machine_check_event *opal_mc_evt;
 #endif
+#ifdef CONFIG_PPC_BOOK3S_64
+        /* Exclusive emergency stack pointer for machine check exception. */
+        void *mc_emergency_sp;
+        /*
+         * Flag to check whether we are in machine check early handler
+         * and already using emergency stack.
+         */
+        u16 in_mce;
+#endif
 
         /* Stuff for accurate time accounting */
         u64 user_time;                  /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 4a191c472867..bc141c950b1e 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -558,5 +558,19 @@ extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 #define __HAVE_ARCH_PMDP_INVALIDATE
 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
                             pmd_t *pmdp);
+
+#define pmd_move_must_withdraw pmd_move_must_withdraw
+struct spinlock;
+static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
+                                         struct spinlock *old_pmd_ptl)
+{
+        /*
+         * Archs like ppc64 use pgtable to store per pmd
+         * specific information. So when we switch the pmd,
+         * we should also withdraw and deposit the pgtable
+         */
+        return true;
+}
+
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 7d6eacf249cf..f83b6f3e1b39 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #ifndef __ASSEMBLY__
+#include <linux/mmdebug.h>
 #include <asm/processor.h>              /* For TASK_SIZE */
 #include <asm/mmu.h>
 #include <asm/page.h>
@@ -33,10 +34,73 @@ static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 static inline int pte_special(pte_t pte)        { return pte_val(pte) & _PAGE_SPECIAL; }
-static inline int pte_present(pte_t pte)        { return pte_val(pte) & _PAGE_PRESENT; }
 static inline int pte_none(pte_t pte)           { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
 static inline pgprot_t pte_pgprot(pte_t pte)    { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
 
+#ifdef CONFIG_NUMA_BALANCING
+
+static inline int pte_present(pte_t pte)
+{
+        return pte_val(pte) & (_PAGE_PRESENT | _PAGE_NUMA);
+}
+
+#define pte_numa pte_numa
+static inline int pte_numa(pte_t pte)
+{
+        return (pte_val(pte) &
+                (_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA;
+}
+
+#define pte_mknonnuma pte_mknonnuma
+static inline pte_t pte_mknonnuma(pte_t pte)
+{
+        pte_val(pte) &= ~_PAGE_NUMA;
+        pte_val(pte) |=  _PAGE_PRESENT | _PAGE_ACCESSED;
+        return pte;
+}
+
+#define pte_mknuma pte_mknuma
+static inline pte_t pte_mknuma(pte_t pte)
+{
+        /*
+         * We should not set _PAGE_NUMA on non present ptes. Also clear the
+         * present bit so that hash_page will return 1 and we collect this
+         * as numa fault.
+         */
+        if (pte_present(pte)) {
+                pte_val(pte) |= _PAGE_NUMA;
+                pte_val(pte) &= ~_PAGE_PRESENT;
+        } else
+                VM_BUG_ON(1);
+        return pte;
+}
+
+#define pmd_numa pmd_numa
+static inline int pmd_numa(pmd_t pmd)
+{
+        return pte_numa(pmd_pte(pmd));
+}
+
+#define pmd_mknonnuma pmd_mknonnuma
+static inline pmd_t pmd_mknonnuma(pmd_t pmd)
+{
+        return pte_pmd(pte_mknonnuma(pmd_pte(pmd)));
+}
+
+#define pmd_mknuma pmd_mknuma
+static inline pmd_t pmd_mknuma(pmd_t pmd)
+{
+        return pte_pmd(pte_mknuma(pmd_pte(pmd)));
+}
+
+# else
+
+static inline int pte_present(pte_t pte)
+{
+        return pte_val(pte) & _PAGE_PRESENT;
+}
+#endif /* CONFIG_NUMA_BALANCING */
+
 /* Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
  *
@@ -223,6 +287,27 @@ extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
 #endif
 pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
                                  unsigned *shift);
+
+static inline pte_t *lookup_linux_ptep(pgd_t *pgdir, unsigned long hva,
+                                     unsigned long *pte_sizep)
+{
+        pte_t *ptep;
+        unsigned long ps = *pte_sizep;
+        unsigned int shift;
+
+        ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
+        if (!ptep)
+                return NULL;
+        if (shift)
+                *pte_sizep = 1ul << shift;
+        else
+                *pte_sizep = PAGE_SIZE;
+
+        if (ps > *pte_sizep)
+                return NULL;
+
+        return ptep;
+}
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index f595b98079ee..6586a40a46ce 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -4,7 +4,6 @@
 #ifndef _ASM_POWERPC_PPC_ASM_H
 #define _ASM_POWERPC_PPC_ASM_H
 
-#include <linux/init.h>
 #include <linux/stringify.h>
 #include <asm/asm-compat.h>
 #include <asm/processor.h>
@@ -295,6 +294,11 @@ n:
  *   you want to access various offsets within it).  On ppc32 this is
  *   identical to LOAD_REG_IMMEDIATE.
  *
+ * LOAD_REG_ADDR_PIC(rn, name)
+ *   Loads the address of label 'name' into register 'run'. Use this when
+ *   the kernel doesn't run at the linked or relocated address. Please
+ *   note that this macro will clobber the lr register.
+ *
  * LOAD_REG_ADDRBASE(rn, name)
  * ADDROFF(name)
  *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
@@ -305,6 +309,14 @@ n:
  *      LOAD_REG_ADDRBASE(rX, name)
  *      ld      rY,ADDROFF(name)(rX)
  */
+
+/* Be careful, this will clobber the lr register. */
+#define LOAD_REG_ADDR_PIC(reg, name)            \
+        bl      0f;                             \
+0:      mflr    reg;                            \
+        addis   reg,reg,(name - 0b)@ha;         \
+        addi    reg,reg,(name - 0b)@l;
+
 #ifdef __powerpc64__
 #define LOAD_REG_IMMEDIATE(reg,expr)            \
         lis     reg,(expr)@highest;             \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fc14a38c7ccf..b62de43ae5f3 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -256,6 +256,8 @@ struct thread_struct {
         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
         u64             acc;            /* Accumulator */
         unsigned long   spefscr;        /* SPE & eFP status */
+        unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
+                                           call or trap return */
         int             used_spe;       /* set if process has used spe */
 #endif /* CONFIG_SPE */
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -317,7 +319,9 @@ struct thread_struct {
         (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 
 #ifdef CONFIG_SPE
-#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
+#define SPEFSCR_INIT \
+        .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
+        .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 #else
 #define SPEFSCR_INIT
 #endif
@@ -373,6 +377,8 @@ extern int set_endian(struct task_struct *tsk, unsigned int val);
 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 
+extern void fp_enable(void);
+extern void vec_enable(void);
 extern void load_fp_state(struct thread_fp_state *fp);
 extern void store_fp_state(struct thread_fp_state *fp);
 extern void load_vr_state(struct thread_vr_state *vr);
@@ -444,13 +450,6 @@ enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 extern void power7_nap(void);
-
-#ifdef CONFIG_PSERIES_IDLE
-extern void update_smt_snooze_delay(int cpu, int residency);
-#else
-static inline void update_smt_snooze_delay(int cpu, int residency) {}
-#endif
-
 extern void flush_instruction_cache(void);
 extern void hard_reset_now(void);
 extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
index 678a7c1d9cb8..a1bc7e758422 100644
--- a/arch/powerpc/include/asm/ps3.h
+++ b/arch/powerpc/include/asm/ps3.h
@@ -21,7 +21,6 @@
 #if !defined(_ASM_POWERPC_PS3_H)
 #define _ASM_POWERPC_PS3_H
 
-#include <linux/init.h>
 #include <linux/types.h>
 #include <linux/device.h>
 #include <asm/cell-pmu.h>
diff --git a/arch/powerpc/include/asm/pte-hash64.h b/arch/powerpc/include/asm/pte-hash64.h
index 0419eeb53274..2505d8eab15c 100644
--- a/arch/powerpc/include/asm/pte-hash64.h
+++ b/arch/powerpc/include/asm/pte-hash64.h
@@ -19,7 +19,7 @@
 #define _PAGE_FILE              0x0002 /* (!present only) software: pte holds file offset */
 #define _PAGE_EXEC              0x0004 /* No execute on POWER4 and newer (we invert) */
 #define _PAGE_GUARDED           0x0008
-#define _PAGE_COHERENT          0x0010 /* M: enforce memory coherence (SMP systems) */
+/* We can derive Memory coherence from _PAGE_NO_CACHE */
 #define _PAGE_NO_CACHE          0x0020 /* I: cache inhibit */
 #define _PAGE_WRITETHRU         0x0040 /* W: cache write-through */
 #define _PAGE_DIRTY             0x0080 /* C: page changed */
@@ -27,6 +27,12 @@
 #define _PAGE_RW                0x0200 /* software: user write access allowed */
 #define _PAGE_BUSY              0x0800 /* software: PTE & hash are busy */
 
+/*
+ * Used for tracking numa faults
+ */
+#define _PAGE_NUMA      0x00000010 /* Gather numa placement stats */
+
+
 /* No separate kernel read-only */
 #define _PAGE_KERNEL_RW         (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
 #define _PAGE_KERNEL_RO          _PAGE_KERNEL_RW
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fa8388ed94c5..90c06ec6eff5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -223,17 +223,26 @@
 #define   CTRL_TE       0x00c00000      /* thread enable */
 #define   CTRL_RUNLATCH 0x1
 #define SPRN_DAWR       0xB4
+#define SPRN_CIABR      0xBB
+#define   CIABR_PRIV            0x3
+#define   CIABR_PRIV_USER       1
+#define   CIABR_PRIV_SUPER      2
+#define   CIABR_PRIV_HYPER      3
 #define SPRN_DAWRX      0xBC
-#define   DAWRX_USER    (1UL << 0)
-#define   DAWRX_KERNEL  (1UL << 1)
-#define   DAWRX_HYP     (1UL << 2)
+#define   DAWRX_USER    __MASK(0)
+#define   DAWRX_KERNEL  __MASK(1)
+#define   DAWRX_HYP     __MASK(2)
+#define   DAWRX_WTI     __MASK(3)
+#define   DAWRX_WT      __MASK(4)
+#define   DAWRX_DR      __MASK(5)
+#define   DAWRX_DW      __MASK(6)
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 #define SPRN_DABR2      0x13D   /* e300 */
 #define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
-#define   DABRX_USER    (1UL << 0)
-#define   DABRX_KERNEL  (1UL << 1)
-#define   DABRX_HYP     (1UL << 2)
-#define   DABRX_BTI     (1UL << 3)
+#define   DABRX_USER    __MASK(0)
+#define   DABRX_KERNEL  __MASK(1)
+#define   DABRX_HYP     __MASK(2)
+#define   DABRX_BTI     __MASK(3)
 #define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
 #define SPRN_DAR        0x013   /* Data Address Register */
 #define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
@@ -260,6 +269,8 @@
 #define SPRN_HRMOR      0x139   /* Real mode offset register */
 #define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
+#define SPRN_IC         0x350   /* Virtual Instruction Count */
+#define SPRN_VTB        0x351   /* Virtual Time Base */
 /* HFSCR and FSCR bit numbers are the same */
 #define FSCR_TAR_LG     8       /* Enable Target Address Register */
 #define FSCR_EBB_LG     7       /* Enable Event Based Branching */
@@ -298,9 +309,13 @@
 #define   LPCR_RMLS    0x1C000000      /* impl dependent rmo limit sel */
 #define   LPCR_RMLS_SH  (63-37)
 #define   LPCR_ILE     0x02000000      /* !HV irqs set MSR:LE */
+#define   LPCR_AIL      0x01800000      /* Alternate interrupt location */
 #define   LPCR_AIL_0    0x00000000      /* MMU off exception offset 0x0 */
 #define   LPCR_AIL_3    0x01800000      /* MMU on exception offset 0xc00...4xxx */
-#define   LPCR_PECE     0x00007000      /* powersave exit cause enable */
+#define   LPCR_ONL      0x00040000      /* online - PURR/SPURR count */
+#define   LPCR_PECE     0x0001f000      /* powersave exit cause enable */
+#define     LPCR_PECEDP 0x00010000      /* directed priv dbells cause exit */
+#define     LPCR_PECEDH 0x00008000      /* directed hyp dbells cause exit */
 #define     LPCR_PECE0  0x00004000      /* ext. exceptions can cause exit */
 #define     LPCR_PECE1  0x00002000      /* decrementer can cause exit */
 #define     LPCR_PECE2  0x00001000      /* machine check etc can cause exit */
@@ -322,6 +337,8 @@
 #define SPRN_PCR        0x152   /* Processor compatibility register */
 #define   PCR_VEC_DIS   (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
 #define   PCR_VSX_DIS   (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
+#define   PCR_TM_DIS    (1ul << (63-2)) /* Trans. memory disable (POWER8) */
+#define   PCR_ARCH_206  0x4             /* Architecture 2.06 */
 #define   PCR_ARCH_205  0x2             /* Architecture 2.05 */
 #define SPRN_HEIR       0x153   /* Hypervisor Emulated Instruction Register */
 #define SPRN_TLBINDEXR  0x154   /* P7 TLB control register */
@@ -368,6 +385,8 @@
 #define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
 #define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
 #define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
+#define SPRN_DHDES      0x0B1           /* Directed Hyp. Doorbell Exc. State */
+#define SPRN_DPDES      0x0B0           /* Directed Priv. Doorbell Exc. State */
 #define SPRN_EAR        0x11A           /* External Address Register */
 #define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
 #define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
@@ -427,6 +446,7 @@
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 #define SPRN_IABR2      0x3FA           /* 83xx */
 #define SPRN_IBCR       0x135           /* 83xx Insn Breakpoint Control Reg */
+#define SPRN_IAMR       0x03D           /* Instr. Authority Mask Reg */
 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 #define  HID4_LPES0      (1ul << (63-0)) /* LPAR env. sel. bit 0 */
 #define  HID4_RMLS2_SH   (63 - 2)       /* Real mode limit bottom 2 bits */
@@ -541,6 +561,7 @@
 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 #endif
 #define SPRN_TIR        0x1BE   /* Thread Identification Register */
+#define SPRN_PSPB       0x09F   /* Problem State Priority Boost reg */
 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
 #define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
@@ -682,6 +703,7 @@
 #define SPRN_EBBHR      804     /* Event based branch handler register */
 #define SPRN_EBBRR      805     /* Event based branch return register */
 #define SPRN_BESCR      806     /* Branch event status and control register */
+#define SPRN_WORT       895     /* Workload optimization register - thread */
 
 #define SPRN_PMC1       787
 #define SPRN_PMC2       788
@@ -698,6 +720,11 @@
 #define   SIER_SIHV             0x1000000       /* Sampled MSR_HV */
 #define   SIER_SIAR_VALID       0x0400000       /* SIAR contents valid */
 #define   SIER_SDAR_VALID       0x0200000       /* SDAR contents valid */
+#define SPRN_TACR       888
+#define SPRN_TCSCR      889
+#define SPRN_CSIGR      890
+#define SPRN_SPMC1      892
+#define SPRN_SPMC2      893
 
 /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
 #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
@@ -1075,6 +1102,8 @@
 #define PVR_8560        0x80200000
 #define PVR_VER_E500V1  0x8020
 #define PVR_VER_E500V2  0x8021
+#define PVR_VER_E6500   0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2e31aacd8acc..163c3b05a76e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -101,6 +101,7 @@
 #define SPRN_IVOR39     0x1B1   /* Interrupt Vector Offset Register 39 */
 #define SPRN_IVOR40     0x1B2   /* Interrupt Vector Offset Register 40 */
 #define SPRN_IVOR41     0x1B3   /* Interrupt Vector Offset Register 41 */
+#define SPRN_IVOR42     0x1B4   /* Interrupt Vector Offset Register 42 */
 #define SPRN_GIVOR2     0x1B8   /* Guest IVOR2 */
 #define SPRN_GIVOR3     0x1B9   /* Guest IVOR3 */
 #define SPRN_GIVOR4     0x1BA   /* Guest IVOR4 */
@@ -170,6 +171,7 @@
 #define SPRN_L2CSR1     0x3FA   /* L2 Data Cache Control and Status Register 1 */
 #define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0  0x3FB   /* Power management control register 0 */
 #define SPRN_SVR        0x3FF   /* System Version Register */
 
 /*
@@ -216,6 +218,14 @@
 #define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define CCR1_TCS        0x00000080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT             (1 << 14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT        8
+#define PWRMGTCR0_PW20_ENT              0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN         (1 << 22) /* Altivec idle enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT     16
+#define PWRMGTCR0_AV_IDLE_CNT           0x3F0000
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS        0x80000000 /* Machine Check Summary */
 #define MCSR_IB         0x40000000 /* Instruction PLB Error */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index f6e78d63fb6a..35aa339410bd 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -30,8 +30,6 @@
 
 #define smp_mb__after_unlock_lock()     smp_mb()  /* Full ordering for lock. */
 
-#define arch_spin_is_locked(x)          ((x)->slock != 0)
-
 #ifdef CONFIG_PPC64
 /* use 0x800000yy when locked, where yy == CPU number */
 #ifdef __BIG_ENDIAN__
@@ -56,6 +54,16 @@
 #define SYNC_IO
 #endif
 
+static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
+{
+        return lock.slock == 0;
+}
+
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+        return !arch_spin_value_unlocked(*lock);
+}
+
 /*
  * This returns the old value in the lock, so we succeeded
  * in getting the lock if the return value is 0.
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index aace90547614..0e83e7d8c73f 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -25,10 +25,8 @@ static inline void save_tar(struct thread_struct *prev)
 static inline void save_tar(struct thread_struct *prev) {}
 #endif
 
-extern void load_up_fpu(void);
 extern void enable_kernel_fp(void);
 extern void enable_kernel_altivec(void);
-extern void load_up_altivec(struct task_struct *);
 extern int emulate_altivec(struct pt_regs *);
 extern void __giveup_vsx(struct task_struct *);
 extern void giveup_vsx(struct task_struct *);
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 43523fe0d8b4..3ddf70276706 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -359,3 +359,5 @@ COMPAT_SYS(process_vm_readv)
 COMPAT_SYS(process_vm_writev)
 SYSCALL(finit_module)
 SYSCALL(ni_syscall) /* sys_kcmp */
+SYSCALL_SPU(sched_setattr)
+SYSCALL_SPU(sched_getattr)
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 9854c564ac52..b034ecdb7c74 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -91,8 +91,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
                                            TIF_NEED_RESCHED */
 #define TIF_32BIT               4       /* 32 bit binary */
-#define TIF_PERFMON_WORK        5       /* work for pfm_handle_work() */
-#define TIF_PERFMON_CTXSW       6       /* perfmon needs ctxsw calls */
+#define TIF_RESTORE_TM          5       /* need to restore TM FP/VEC/VSX */
 #define TIF_SYSCALL_AUDIT       7       /* syscall auditing active */
 #define TIF_SINGLESTEP          8       /* singlestepping active */
 #define TIF_NOHZ                9       /* in adaptive nohz mode */
@@ -115,8 +114,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_32BIT              (1<<TIF_32BIT)
-#define _TIF_PERFMON_WORK       (1<<TIF_PERFMON_WORK)
-#define _TIF_PERFMON_CTXSW      (1<<TIF_PERFMON_CTXSW)
+#define _TIF_RESTORE_TM         (1<<TIF_RESTORE_TM)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
@@ -132,7 +130,8 @@ static inline struct thread_info *current_thread_info(void)
                                  _TIF_NOHZ)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
-                                 _TIF_NOTIFY_RESUME | _TIF_UPROBE)
+                                 _TIF_NOTIFY_RESUME | _TIF_UPROBE | \
+                                 _TIF_RESTORE_TM)
 #define _TIF_PERSYSCALL_MASK    (_TIF_RESTOREALL|_TIF_NOERROR)
 
 /* Bits in local_flags */
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
index 9dfbc34bdbf5..0c9f8b74dd97 100644
--- a/arch/powerpc/include/asm/tm.h
+++ b/arch/powerpc/include/asm/tm.h
@@ -15,6 +15,7 @@ extern void do_load_up_transact_altivec(struct thread_struct *thread);
 extern void tm_enable(void);
 extern void tm_reclaim(struct thread_struct *thread,
                        unsigned long orig_msr, uint8_t cause);
+extern void tm_reclaim_current(uint8_t cause);
 extern void tm_recheckpoint(struct thread_struct *thread,
                             unsigned long orig_msr);
 extern void tm_abort(uint8_t cause);
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 89e3ef2496ac..d0b5fca6b077 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -22,7 +22,15 @@ struct device_node;
 
 static inline int cpu_to_node(int cpu)
 {
-        return numa_cpu_lookup_table[cpu];
+        int nid;
+
+        nid = numa_cpu_lookup_table[cpu];
+
+        /*
+         * During early boot, the numa-cpu lookup table might not have been
+         * setup for all CPUs yet. In such cases, default to node 0.
+         */
+        return (nid < 0) ? 0 : nid;
 }
 
 #define parent_node(node)       (node)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3ca819f541bf..4494f029b632 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
 #include <uapi/asm/unistd.h>
 
 
-#define __NR_syscalls           355
+#define __NR_syscalls           357
 
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
index 68d0cc998b1b..4f9b7ca0710f 100644
--- a/arch/powerpc/include/asm/vio.h
+++ b/arch/powerpc/include/asm/vio.h
@@ -15,7 +15,6 @@
 #define _ASM_POWERPC_VIO_H
 #ifdef __KERNEL__
 
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index 6836ec79a830..a6665be4f3ab 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -545,6 +545,7 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_TCSCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
 #define KVM_REG_PPC_PID         (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
 #define KVM_REG_PPC_ACOP        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
+#define KVM_REG_PPC_WORT        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb4)
 
 #define KVM_REG_PPC_VRSAVE      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
 #define KVM_REG_PPC_LPCR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
@@ -553,6 +554,8 @@ struct kvm_get_htab_header {
 /* Architecture compatibility level */
 #define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
 
+#define KVM_REG_PPC_DABRX       (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
+
 /* Transactional Memory checkpointed state:
  * This is all GPRs, all VSX regs and a subset of SPRs
  */
diff --git a/arch/powerpc/include/uapi/asm/socket.h b/arch/powerpc/include/uapi/asm/socket.h
index fa698324a1fd..a9c3e2e18c05 100644
--- a/arch/powerpc/include/uapi/asm/socket.h
+++ b/arch/powerpc/include/uapi/asm/socket.h
@@ -85,4 +85,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif  /* _ASM_POWERPC_SOCKET_H */
diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h
index 85059a00f560..5d836b7c1176 100644
--- a/arch/powerpc/include/uapi/asm/tm.h
+++ b/arch/powerpc/include/uapi/asm/tm.h
@@ -6,6 +6,8 @@
  * the failure is persistent.  PAPR saves 0xff-0xe0 for the hypervisor.
  */
 #define TM_CAUSE_PERSISTENT     0x01
+#define TM_CAUSE_KVM_RESCHED    0xe0  /* From PAPR */
+#define TM_CAUSE_KVM_FAC_UNAV   0xe2  /* From PAPR */
 #define TM_CAUSE_RESCHED        0xde
 #define TM_CAUSE_TLBI           0xdc
 #define TM_CAUSE_FAC_UNAV       0xda
diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h
index 74cb4d72d673..881bf2e2560d 100644
--- a/arch/powerpc/include/uapi/asm/unistd.h
+++ b/arch/powerpc/include/uapi/asm/unistd.h
@@ -377,6 +377,7 @@
 #define __NR_process_vm_writev  352
 #define __NR_finit_module       353
 #define __NR_kcmp               354
-
+#define __NR_sched_setattr      355
+#define __NR_sched_getattr      356
 
 #endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 445cb6e39d5b..fcc9a89a4695 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PPC64)		+= setup_64.o sys_ppc32.o \
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_power.o
+obj-$(CONFIG_PPC_BOOK3S_64)     += mce.o mce_power.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
 obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o idle_book3e.o
 obj-$(CONFIG_PPC_A2)            += cpu_setup_a2.o
@@ -47,7 +48,6 @@ obj-$(CONFIG_ALTIVEC)		+= vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
 obj-$(CONFIG_PPC_P7_NAP)        += idle_power7.o
 obj-$(CONFIG_PPC_OF)            += of_platform.o prom_parse.o
-obj-$(CONFIG_PPC_CLOCK)         += clock.o
 procfs-y                        := proc_powerpc.o
 obj-$(CONFIG_PROC_FS)           += $(procfs-y)
 rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI)   := rtas_pci.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index d3de01066f7d..b5aacf72ae6f 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -203,6 +203,15 @@ int main(void)
         DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
         DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
         DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
+        DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
+
+        DEFINE(TCD_ESEL_NEXT,
+                offsetof(struct tlb_core_data, esel_next));
+        DEFINE(TCD_ESEL_MAX,
+                offsetof(struct tlb_core_data, esel_max));
+        DEFINE(TCD_ESEL_FIRST,
+                offsetof(struct tlb_core_data, esel_first));
+        DEFINE(TCD_LOCK, offsetof(struct tlb_core_data, lock));
 #endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef CONFIG_PPC_STD_MMU_64
@@ -232,6 +241,10 @@ int main(void)
         DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
 #endif /* CONFIG_PPC_STD_MMU_64 */
         DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
+#ifdef CONFIG_PPC_BOOK3S_64
+        DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp));
+        DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce));
+#endif
         DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
         DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
         DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
@@ -425,18 +438,14 @@ int main(void)
         DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
         DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
         DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
-        DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fpr));
-        DEFINE(VCPU_FPSCR, offsetof(struct kvm_vcpu, arch.fpscr));
+        DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr));
 #ifdef CONFIG_ALTIVEC
-        DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr));
-        DEFINE(VCPU_VSCR, offsetof(struct kvm_vcpu, arch.vscr));
-#endif
-#ifdef CONFIG_VSX
-        DEFINE(VCPU_VSRS, offsetof(struct kvm_vcpu, arch.vsr));
+        DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr));
 #endif
         DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
         DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
         DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
+        DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar));
         DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
         DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -484,16 +493,24 @@ int main(void)
         DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
         DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
         DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
+        DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr));
 #endif
 #ifdef CONFIG_PPC_BOOK3S
         DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
         DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
         DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
+        DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic));
+        DEFINE(VCPU_VTB, offsetof(struct kvm_vcpu, arch.vtb));
         DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
         DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
         DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
+        DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr));
         DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
         DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
+        DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx));
+        DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr));
+        DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx));
+        DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr));
         DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
         DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
         DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
@@ -502,8 +519,10 @@ int main(void)
         DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded));
         DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
         DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
+        DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc));
         DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar));
         DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar));
+        DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier));
         DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
         DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
         DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
@@ -511,20 +530,47 @@ int main(void)
         DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
         DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
         DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
-        DEFINE(VCPU_PTID, offsetof(struct kvm_vcpu, arch.ptid));
         DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
         DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
+        DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
+        DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
+        DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
+        DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
+        DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
+        DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr));
+        DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr));
+        DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr));
+        DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop));
+        DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort));
         DEFINE(VCPU_SHADOW_SRR1, offsetof(struct kvm_vcpu, arch.shadow_srr1));
         DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_count));
         DEFINE(VCORE_NAP_COUNT, offsetof(struct kvmppc_vcore, nap_count));
         DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
         DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads));
+        DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm));
         DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset));
         DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr));
         DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr));
+        DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes));
         DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
         DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
         DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
+        DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
+        DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
+        DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
+        DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
+        DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
+        DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
+        DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
+        DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
+        DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
+        DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
+        DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
+        DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
+        DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
+#endif
 
 #ifdef CONFIG_PPC_BOOK3S_64
 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
@@ -589,6 +635,7 @@ int main(void)
         HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
         HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
         HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
+        HSTATE_FIELD(HSTATE_PTID, ptid);
         HSTATE_FIELD(HSTATE_MMCR, host_mmcr);
         HSTATE_FIELD(HSTATE_PMC, host_pmc);
         HSTATE_FIELD(HSTATE_PURR, host_purr);
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 654932727873..2912b8787aa4 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -12,7 +12,6 @@
 
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/kobject.h>
 #include <linux/list.h>
@@ -794,6 +793,9 @@ static void remove_cache_dir(struct cache_dir *cache_dir)
 {
         remove_index_dirs(cache_dir);
 
+        /* Remove cache dir from sysfs */
+        kobject_del(cache_dir->kobj);
+
         kobject_put(cache_dir->kobj);
 
         kfree(cache_dir);
diff --git a/arch/powerpc/kernel/clock.c b/arch/powerpc/kernel/clock.c
deleted file mode 100644
index a764b47791e8..000000000000
--- a/arch/powerpc/kernel/clock.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Dummy clk implementations for powerpc.
- * These need to be overridden in platform code.
- */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <asm/clk_interface.h>
-
-struct clk_interface clk_functions;
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        if (clk_functions.clk_get)
-                return clk_functions.clk_get(dev, id);
-        return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-        if (clk_functions.clk_put)
-                clk_functions.clk_put(clk);
-}
-EXPORT_SYMBOL(clk_put);
-
-int clk_enable(struct clk *clk)
-{
-        if (clk_functions.clk_enable)
-                return clk_functions.clk_enable(clk);
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        if (clk_functions.clk_disable)
-                clk_functions.clk_disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (clk_functions.clk_get_rate)
-                return clk_functions.clk_get_rate(clk);
-        return 0;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk_functions.clk_round_rate)
-                return clk_functions.clk_round_rate(clk, rate);
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk_functions.clk_set_rate)
-                return clk_functions.clk_set_rate(clk, rate);
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        if (clk_functions.clk_get_parent)
-                return clk_functions.clk_get_parent(clk);
-        return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        if (clk_functions.clk_set_parent)
-                return clk_functions.clk_set_parent(clk, parent);
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7290b7..cc2d8962e090 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,57 @@ _GLOBAL(__e500_dcache_setup)
         isync
         blr
 
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT              50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+        mfspr   r3, SPRN_PWRMGTCR0
+
+        /* Set PW20_WAIT bit, enable pw20 state*/
+        ori     r3, r3, PWRMGTCR0_PW20_WAIT
+        li      r11, PW20_WAIT_IDLE_BIT
+
+        /* Set Automatic PW20 Core Idle Count */
+        rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+        mtspr   SPRN_PWRMGTCR0, r3
+
+        blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT                50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+        mfspr   r3, SPRN_PWRMGTCR0
+
+        /* Enable Altivec Idle */
+        oris    r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+        li      r11, AV_WAIT_IDLE_BIT
+
+        /* Set Automatic AltiVec Idle Count */
+        rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+        mtspr   SPRN_PWRMGTCR0, r3
+
+        blr
+
 _GLOBAL(__setup_cpu_e6500)
         mflr    r6
 #ifdef CONFIG_PPC64
         bl      .setup_altivec_ivors
+        /* Touch IVOR42 only if the CPU supports E.HV category */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
+        bl      .setup_lrat_ivor
+1:
 #endif
+        bl      setup_pw20_idle
+        bl      setup_altivec_idle
         bl      __setup_cpu_e5500
         mtlr    r6
         blr
@@ -119,6 +165,14 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
         mflr    r5
         bl      .setup_altivec_ivors
+        /* Touch IVOR42 only if the CPU supports E.HV category */
+        mfspr   r10,SPRN_MMUCFG
+        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
+        beq     1f
+        bl      .setup_lrat_ivor
+1:
+        bl      .setup_pw20_idle
+        bl      .setup_altivec_idle
         bl      __restore_cpu_e5500
         mtlr    r5
         blr
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 18b5b9cf8e37..37d1bb002aa9 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -29,7 +29,7 @@ _GLOBAL(__setup_cpu_power7)
         mtspr   SPRN_LPID,r0
         mfspr   r3,SPRN_LPCR
         bl      __init_LPCR
-        bl      __init_TLB
+        bl      __init_tlb_power7
         mtlr    r11
         blr
 
@@ -42,7 +42,7 @@ _GLOBAL(__restore_cpu_power7)
         mtspr   SPRN_LPID,r0
         mfspr   r3,SPRN_LPCR
         bl      __init_LPCR
-        bl      __init_TLB
+        bl      __init_tlb_power7
         mtlr    r11
         blr
 
@@ -59,7 +59,7 @@ _GLOBAL(__setup_cpu_power8)
         oris    r3, r3, LPCR_AIL_3@h
         bl      __init_LPCR
         bl      __init_HFSCR
-        bl      __init_TLB
+        bl      __init_tlb_power8
         bl      __init_PMU_HV
         mtlr    r11
         blr
@@ -78,7 +78,7 @@ _GLOBAL(__restore_cpu_power8)
         oris    r3, r3, LPCR_AIL_3@h
         bl      __init_LPCR
         bl      __init_HFSCR
-        bl      __init_TLB
+        bl      __init_tlb_power8
         bl      __init_PMU_HV
         mtlr    r11
         blr
@@ -134,15 +134,31 @@ __init_HFSCR:
         mtspr   SPRN_HFSCR,r3
         blr
 
-__init_TLB:
-        /*
-         * Clear the TLB using the "IS 3" form of tlbiel instruction
-         * (invalidate by congruence class). P7 has 128 CCs, P8 has 512
-         * so we just always do 512
-         */
+/*
+ * Clear the TLB using the specified IS form of tlbiel instruction
+ * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
+ *
+ * r3 = IS field
+ */
+__init_tlb_power7:
+        li      r3,0xc00        /* IS field = 0b11 */
+_GLOBAL(__flush_tlb_power7)
+        li      r6,128
+        mtctr   r6
+        mr      r7,r3           /* IS field */
+        ptesync
+2:      tlbiel  r7
+        addi    r7,r7,0x1000
+        bdnz    2b
+        ptesync
+1:      blr
+
+__init_tlb_power8:
+        li      r3,0xc00        /* IS field = 0b11 */
+_GLOBAL(__flush_tlb_power8)
         li      r6,512
         mtctr   r6
-        li      r7,0xc00        /* IS field = 0b11 */
+        mr      r7,r3           /* IS field */
         ptesync
 2:      tlbiel  r7
         addi    r7,r7,0x1000
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 597d954e5860..6c8dd5da4de5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -71,6 +71,10 @@ extern void __restore_cpu_power7(void);
 extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
 extern void __restore_cpu_power8(void);
 extern void __restore_cpu_a2(void);
+extern void __flush_tlb_power7(unsigned long inval_selector);
+extern void __flush_tlb_power8(unsigned long inval_selector);
+extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
 #endif /* CONFIG_PPC64 */
 #if defined(CONFIG_E500)
 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -440,6 +444,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
                 .cpu_setup              = __setup_cpu_power7,
                 .cpu_restore            = __restore_cpu_power7,
+                .flush_tlb              = __flush_tlb_power7,
+                .machine_check_early    = __machine_check_early_realmode_p7,
                 .platform               = "power7",
         },
         {       /* 2.07-compliant processor, i.e. Power8 "architected" mode */
@@ -456,6 +462,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
+                .flush_tlb              = __flush_tlb_power8,
+                .machine_check_early    = __machine_check_early_realmode_p8,
                 .platform               = "power8",
         },
         {       /* Power7 */
@@ -474,6 +482,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_type          = PPC_OPROFILE_POWER4,
                 .cpu_setup              = __setup_cpu_power7,
                 .cpu_restore            = __restore_cpu_power7,
+                .flush_tlb              = __flush_tlb_power7,
+                .machine_check_early    = __machine_check_early_realmode_p7,
                 .platform               = "power7",
         },
         {       /* Power7+ */
@@ -492,6 +502,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_type          = PPC_OPROFILE_POWER4,
                 .cpu_setup              = __setup_cpu_power7,
                 .cpu_restore            = __restore_cpu_power7,
+                .flush_tlb              = __flush_tlb_power7,
+                .machine_check_early    = __machine_check_early_realmode_p7,
                 .platform               = "power7+",
         },
         {       /* Power8E */
@@ -510,6 +522,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_type          = PPC_OPROFILE_INVALID,
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
+                .flush_tlb              = __flush_tlb_power8,
+                .machine_check_early    = __machine_check_early_realmode_p8,
                 .platform               = "power8",
         },
         {       /* Power8 */
@@ -528,6 +542,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .oprofile_type          = PPC_OPROFILE_INVALID,
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
+                .flush_tlb              = __flush_tlb_power8,
+                .machine_check_early    = __machine_check_early_realmode_p8,
                 .platform               = "power8",
         },
         {       /* Cell Broadband Engine */
diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c
index fdcd8f551aff..18d7c80ddeb9 100644
--- a/arch/powerpc/kernel/crash.c
+++ b/arch/powerpc/kernel/crash.c
@@ -17,7 +17,6 @@
 #include <linux/export.h>
 #include <linux/crash_dump.h>
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/types.h>
 
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index e4897523de41..54d0116256f7 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -83,10 +83,10 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask)
                 return 0;
         }
 
-        if (tbl->it_offset > (mask >> IOMMU_PAGE_SHIFT)) {
+        if (tbl->it_offset > (mask >> tbl->it_page_shift)) {
                 dev_info(dev, "Warning: IOMMU offset too big for device mask\n");
                 dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
-                                mask, tbl->it_offset << IOMMU_PAGE_SHIFT);
+                                mask, tbl->it_offset << tbl->it_page_shift);
                 return 0;
         } else
                 return 1;
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 4bd687d5e7aa..148db72a8c43 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -84,7 +84,7 @@
 #define EEH_MAX_FAILS   2100000
 
 /* Time to wait for a PCI slot to report status, in milliseconds */
-#define PCI_BUS_RESET_WAIT_MSEC (60*1000)
+#define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
 
 /* Platform dependent EEH operations */
 struct eeh_ops *eeh_ops = NULL;
@@ -921,6 +921,13 @@ void eeh_add_device_late(struct pci_dev *dev)
                 eeh_sysfs_remove_device(edev->pdev);
                 edev->mode &= ~EEH_DEV_SYSFS;
 
+                /*
+                 * We definitely should have the PCI device removed
+                 * though it wasn't correctly. So we needn't call
+                 * into error handler afterwards.
+                 */
+                edev->mode |= EEH_DEV_NO_HANDLER;
+
                 edev->pdev = NULL;
                 dev->dev.archdata.edev = NULL;
         }
@@ -1023,6 +1030,14 @@ void eeh_remove_device(struct pci_dev *dev)
         else
                 edev->mode |= EEH_DEV_DISCONNECTED;
 
+        /*
+         * We're removing from the PCI subsystem, that means
+         * the PCI device driver can't support EEH or not
+         * well. So we rely on hotplug completely to do recovery
+         * for the specific PCI device.
+         */
+        edev->mode |= EEH_DEV_NO_HANDLER;
+
         eeh_addr_cache_rmv_dev(dev);
         eeh_sysfs_remove_device(dev);
         edev->mode &= ~EEH_DEV_SYSFS;
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index 36bed5a12750..7bb30dca4e19 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -217,7 +217,8 @@ static void *eeh_report_mmio_enabled(void *data, void *userdata)
         if (!driver) return NULL;
 
         if (!driver->err_handler ||
-            !driver->err_handler->mmio_enabled) {
+            !driver->err_handler->mmio_enabled ||
+            (edev->mode & EEH_DEV_NO_HANDLER)) {
                 eeh_pcid_put(dev);
                 return NULL;
         }
@@ -258,7 +259,8 @@ static void *eeh_report_reset(void *data, void *userdata)
         eeh_enable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->slot_reset) {
+            !driver->err_handler->slot_reset ||
+            (edev->mode & EEH_DEV_NO_HANDLER)) {
                 eeh_pcid_put(dev);
                 return NULL;
         }
@@ -297,7 +299,9 @@ static void *eeh_report_resume(void *data, void *userdata)
         eeh_enable_irq(dev);
 
         if (!driver->err_handler ||
-            !driver->err_handler->resume) {
+            !driver->err_handler->resume ||
+            (edev->mode & EEH_DEV_NO_HANDLER)) {
+                edev->mode &= ~EEH_DEV_NO_HANDLER;
                 eeh_pcid_put(dev);
                 return NULL;
         }
@@ -369,7 +373,9 @@ static void *eeh_rmv_device(void *data, void *userdata)
         edev->mode |= EEH_DEV_DISCONNECTED;
         (*removed)++;
 
+        pci_lock_rescan_remove();
         pci_stop_and_remove_bus_device(dev);
+        pci_unlock_rescan_remove();
 
         return NULL;
 }
@@ -416,10 +422,13 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
          * into pcibios_add_pci_devices().
          */
         eeh_pe_state_mark(pe, EEH_PE_KEEP);
-        if (bus)
+        if (bus) {
+                pci_lock_rescan_remove();
                 pcibios_remove_pci_devices(bus);
-        else if (frozen_bus)
+                pci_unlock_rescan_remove();
+        } else if (frozen_bus) {
                 eeh_pe_dev_traverse(pe, eeh_rmv_device, &removed);
+        }
 
         /* Reset the pci controller. (Asserts RST#; resets config space).
          * Reconfigure bridges and devices. Don't try to bring the system
@@ -429,6 +438,8 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
         if (rc)
                 return rc;
 
+        pci_lock_rescan_remove();
+
         /* Restore PE */
         eeh_ops->configure_bridge(pe);
         eeh_pe_restore_bars(pe);
@@ -462,13 +473,14 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
         pe->tstamp = tstamp;
         pe->freeze_count = cnt;
 
+        pci_unlock_rescan_remove();
         return 0;
 }
 
 /* The longest amount of time to wait for a pci device
  * to come back on line, in seconds.
  */
-#define MAX_WAIT_FOR_RECOVERY 150
+#define MAX_WAIT_FOR_RECOVERY 300
 
 static void eeh_handle_normal_event(struct eeh_pe *pe)
 {
@@ -618,92 +630,103 @@ perm_error:
         eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
 
         /* Shut down the device drivers for good. */
-        if (frozen_bus)
+        if (frozen_bus) {
+                pci_lock_rescan_remove();
                 pcibios_remove_pci_devices(frozen_bus);
+                pci_unlock_rescan_remove();
+        }
 }
 
 static void eeh_handle_special_event(void)
 {
         struct eeh_pe *pe, *phb_pe;
         struct pci_bus *bus;
-        struct pci_controller *hose, *tmp;
+        struct pci_controller *hose;
         unsigned long flags;
-        int rc = 0;
+        int rc;
 
-        /*
-         * The return value from next_error() has been classified as follows.
-         * It might be good to enumerate them. However, next_error() is only
-         * supported by PowerNV platform for now. So it would be fine to use
-         * integer directly:
-         *
-         * 4 - Dead IOC           3 - Dead PHB
-         * 2 - Fenced PHB         1 - Frozen PE
-         * 0 - No error found
-         *
-         */
-        rc = eeh_ops->next_error(&pe);
-        if (rc <= 0)
-                return;
 
-        switch (rc) {
-        case 4:
-                /* Mark all PHBs in dead state */
-                eeh_serialize_lock(&flags);
-                list_for_each_entry_safe(hose, tmp,
-                                &hose_list, list_node) {
-                        phb_pe = eeh_phb_pe_get(hose);
-                        if (!phb_pe) continue;
-
-                        eeh_pe_state_mark(phb_pe,
-                                EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
+        do {
+                rc = eeh_ops->next_error(&pe);
+
+                switch (rc) {
+                case EEH_NEXT_ERR_DEAD_IOC:
+                        /* Mark all PHBs in dead state */
+                        eeh_serialize_lock(&flags);
+
+                        /* Purge all events */
+                        eeh_remove_event(NULL);
+
+                        list_for_each_entry(hose, &hose_list, list_node) {
+                                phb_pe = eeh_phb_pe_get(hose);
+                                if (!phb_pe) continue;
+
+                                eeh_pe_state_mark(phb_pe,
+                                        EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
+                        }
+
+                        eeh_serialize_unlock(flags);
+
+                        break;
+                case EEH_NEXT_ERR_FROZEN_PE:
+                case EEH_NEXT_ERR_FENCED_PHB:
+                case EEH_NEXT_ERR_DEAD_PHB:
+                        /* Mark the PE in fenced state */
+                        eeh_serialize_lock(&flags);
+
+                        /* Purge all events of the PHB */
+                        eeh_remove_event(pe);
+
+                        if (rc == EEH_NEXT_ERR_DEAD_PHB)
+                                eeh_pe_state_mark(pe,
+                                        EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
+                        else
+                                eeh_pe_state_mark(pe,
+                                        EEH_PE_ISOLATED | EEH_PE_RECOVERING);
+
+                        eeh_serialize_unlock(flags);
+
+                        break;
+                case EEH_NEXT_ERR_NONE:
+                        return;
+                default:
+                        pr_warn("%s: Invalid value %d from next_error()\n",
+                                __func__, rc);
+                        return;
                 }
-                eeh_serialize_unlock(flags);
-
-                /* Purge all events */
-                eeh_remove_event(NULL);
-                break;
-        case 3:
-        case 2:
-        case 1:
-                /* Mark the PE in fenced state */
-                eeh_serialize_lock(&flags);
-                if (rc == 3)
-                        eeh_pe_state_mark(pe,
-                                EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
-                else
-                        eeh_pe_state_mark(pe,
-                                EEH_PE_ISOLATED | EEH_PE_RECOVERING);
-                eeh_serialize_unlock(flags);
-
-                /* Purge all events of the PHB */
-                eeh_remove_event(pe);
-                break;
-        default:
-                pr_err("%s: Invalid value %d from next_error()\n",
-                       __func__, rc);
-                return;
-        }
 
-        /*
-         * For fenced PHB and frozen PE, it's handled as normal
-         * event. We have to remove the affected PHBs for dead
-         * PHB and IOC
-         */
-        if (rc == 2 || rc == 1)
-                eeh_handle_normal_event(pe);
-        else {
-                list_for_each_entry_safe(hose, tmp,
-                        &hose_list, list_node) {
-                        phb_pe = eeh_phb_pe_get(hose);
-                        if (!phb_pe || !(phb_pe->state & EEH_PE_PHB_DEAD))
-                                continue;
-
-                        bus = eeh_pe_bus_get(phb_pe);
-                        /* Notify all devices that they're about to go down. */
-                        eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
-                        pcibios_remove_pci_devices(bus);
+                /*
+                 * For fenced PHB and frozen PE, it's handled as normal
+                 * event. We have to remove the affected PHBs for dead
+                 * PHB and IOC
+                 */
+                if (rc == EEH_NEXT_ERR_FROZEN_PE ||
+                    rc == EEH_NEXT_ERR_FENCED_PHB) {
+                        eeh_handle_normal_event(pe);
+                } else {
+                        pci_lock_rescan_remove();
+                        list_for_each_entry(hose, &hose_list, list_node) {
+                                phb_pe = eeh_phb_pe_get(hose);
+                                if (!phb_pe ||
+                                    !(phb_pe->state & EEH_PE_PHB_DEAD))
+                                        continue;
+
+                                /* Notify all devices to be down */
+                                bus = eeh_pe_bus_get(phb_pe);
+                                eeh_pe_dev_traverse(pe,
+                                        eeh_report_failure, NULL);
+                                pcibios_remove_pci_devices(bus);
+                        }
+                        pci_unlock_rescan_remove();
                 }
-        }
+
+                /*
+                 * If we have detected dead IOC, we needn't proceed
+                 * any more since all PHBs would have been removed
+                 */
+                if (rc == EEH_NEXT_ERR_DEAD_IOC)
+                        break;
+        } while (rc != EEH_NEXT_ERR_NONE);
 }
 
 /**
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index f9450537e335..f0c353fa655a 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -25,7 +25,6 @@
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/gfp.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/string.h>
@@ -737,6 +736,9 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
         else
                 eeh_restore_device_bars(edev, dn);
 
+        if (eeh_ops->restore_config)
+                eeh_ops->restore_config(dn);
+
         return NULL;
 }
 
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index bbfb0294b354..662c6dd98072 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -664,8 +664,16 @@ _GLOBAL(ret_from_except_lite)
         bl      .restore_interrupts
         SCHEDULE_USER
         b       .ret_from_except_lite
-
-2:      bl      .save_nvgprs
+2:
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        andi.   r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
+        bne     3f              /* only restore TM if nothing else to do */
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .restore_tm_state
+        b       restore
+3:
+#endif
+        bl      .save_nvgprs
         bl      .restore_interrupts
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_notify_resume
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index e7751561fd1d..063b65dd4f27 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -308,6 +308,7 @@ interrupt_base_book3e:					/* fake trap */
         EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
         EXCEPTION_STUB(0x300, hypercall)
         EXCEPTION_STUB(0x320, ehpriv)
+        EXCEPTION_STUB(0x340, lrat_error)
 
         .globl interrupt_end_book3e
 interrupt_end_book3e:
@@ -677,6 +678,17 @@ kernel_dbg_exc:
         bl      .unknown_exception
         b       .ret_from_except
 
+/* LRAT Error interrupt */
+        START_EXCEPTION(lrat_error);
+        NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
+                                PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x340, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
+
 /*
  * An interrupt came in while soft-disabled; We mark paca->irq_happened
  * accordingly and if the interrupt is level sensitive, we hard disable
@@ -859,6 +871,7 @@ BAD_STACK_TRAMPOLINE(0x2e0)
 BAD_STACK_TRAMPOLINE(0x300)
 BAD_STACK_TRAMPOLINE(0x310)
 BAD_STACK_TRAMPOLINE(0x320)
+BAD_STACK_TRAMPOLINE(0x340)
 BAD_STACK_TRAMPOLINE(0x400)
 BAD_STACK_TRAMPOLINE(0x500)
 BAD_STACK_TRAMPOLINE(0x600)
@@ -1055,12 +1068,9 @@ skpinv:	addi	r6,r6,1				/* Increment */
         mtspr   SPRN_MAS0,r3
         tlbre
         mfspr   r6,SPRN_MAS1
-        rlwinm  r6,r6,0,2,0     /* clear IPROT */
+        rlwinm  r6,r6,0,2,31    /* clear IPROT and VALID */
         mtspr   SPRN_MAS1,r6
         tlbwe
-
-        /* Invalidate TLB1 */
-        PPC_TLBILX_ALL(0,R0)
         sync
         isync
 
@@ -1114,12 +1124,9 @@ skpinv:	addi	r6,r6,1				/* Increment */
         mtspr   SPRN_MAS0,r4
         tlbre
         mfspr   r5,SPRN_MAS1
-        rlwinm  r5,r5,0,2,0     /* clear IPROT */
+        rlwinm  r5,r5,0,2,31    /* clear IPROT and VALID */
         mtspr   SPRN_MAS1,r5
         tlbwe
-
-        /* Invalidate TLB1 */
-        PPC_TLBILX_ALL(0,R0)
         sync
         isync
 
@@ -1414,3 +1421,7 @@ _GLOBAL(setup_ehv_ivors)
         SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
         SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
         blr
+
+_GLOBAL(setup_lrat_ivor)
+        SET_IVOR(42, 0x340) /* LRAT Error */
+        blr
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 9f905e40922e..38d507306a11 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -155,8 +155,30 @@ machine_check_pSeries_1:
          */
         HMT_MEDIUM_PPR_DISCARD
         SET_SCRATCH0(r13)               /* save r13 */
+#ifdef CONFIG_PPC_P7_NAP
+BEGIN_FTR_SECTION
+        /* Running native on arch 2.06 or later, check if we are
+         * waking up from nap. We only handle no state loss and
+         * supervisor state loss. We do -not- handle hypervisor
+         * state loss at this time.
+         */
+        mfspr   r13,SPRN_SRR1
+        rlwinm. r13,r13,47-31,30,31
+        beq     9f
+
+        /* waking up from powersave (nap) state */
+        cmpwi   cr1,r13,2
+        /* Total loss of HV state is fatal. let's just stay stuck here */
+        bgt     cr1,.
+9:
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
+#endif /* CONFIG_PPC_P7_NAP */
         EXCEPTION_PROLOG_0(PACA_EXMC)
+BEGIN_FTR_SECTION
+        b       machine_check_pSeries_early
+FTR_SECTION_ELSE
         b       machine_check_pSeries_0
+ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 
         . = 0x300
         .globl data_access_pSeries
@@ -405,6 +427,64 @@ denorm_exception_hv:
 
         .align  7
         /* moved from 0x200 */
+machine_check_pSeries_early:
+BEGIN_FTR_SECTION
+        EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
+        /*
+         * Register contents:
+         * R13          = PACA
+         * R9           = CR
+         * Original R9 to R13 is saved on PACA_EXMC
+         *
+         * Switch to mc_emergency stack and handle re-entrancy (though we
+         * currently don't test for overflow). Save MCE registers srr1,
+         * srr0, dar and dsisr and then set ME=1
+         *
+         * We use paca->in_mce to check whether this is the first entry or
+         * nested machine check. We increment paca->in_mce to track nested
+         * machine checks.
+         *
+         * If this is the first entry then set stack pointer to
+         * paca->mc_emergency_sp, otherwise r1 is already pointing to
+         * stack frame on mc_emergency stack.
+         *
+         * NOTE: We are here with MSR_ME=0 (off), which means we risk a
+         * checkstop if we get another machine check exception before we do
+         * rfid with MSR_ME=1.
+         */
+        mr      r11,r1                  /* Save r1 */
+        lhz     r10,PACA_IN_MCE(r13)
+        cmpwi   r10,0                   /* Are we in nested machine check */
+        bne     0f                      /* Yes, we are. */
+        /* First machine check entry */
+        ld      r1,PACAMCEMERGSP(r13)   /* Use MC emergency stack */
+0:      subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame */
+        addi    r10,r10,1               /* increment paca->in_mce */
+        sth     r10,PACA_IN_MCE(r13)
+        std     r11,GPR1(r1)            /* Save r1 on the stack. */
+        std     r11,0(r1)               /* make stack chain pointer */
+        mfspr   r11,SPRN_SRR0           /* Save SRR0 */
+        std     r11,_NIP(r1)
+        mfspr   r11,SPRN_SRR1           /* Save SRR1 */
+        std     r11,_MSR(r1)
+        mfspr   r11,SPRN_DAR            /* Save DAR */
+        std     r11,_DAR(r1)
+        mfspr   r11,SPRN_DSISR          /* Save DSISR */
+        std     r11,_DSISR(r1)
+        std     r9,_CCR(r1)             /* Save CR in stackframe */
+        /* Save r9 through r13 from EXMC save area to stack frame. */
+        EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
+        mfmsr   r11                     /* get MSR value */
+        ori     r11,r11,MSR_ME          /* turn on ME bit */
+        ori     r11,r11,MSR_RI          /* turn on RI bit */
+        ld      r12,PACAKBASE(r13)      /* get high part of &label */
+        LOAD_HANDLER(r12, machine_check_handle_early)
+        mtspr   SPRN_SRR0,r12
+        mtspr   SPRN_SRR1,r11
+        rfid
+        b       .       /* prevent speculative execution */
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+
 machine_check_pSeries:
         .globl machine_check_fwnmi
 machine_check_fwnmi:
@@ -688,30 +768,6 @@ kvmppc_skip_Hinterrupt:
 
         STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
 
-        /*
-         * Machine check is different because we use a different
-         * save area: PACA_EXMC instead of PACA_EXGEN.
-         */
-        .align  7
-        .globl machine_check_common
-machine_check_common:
-
-        mfspr   r10,SPRN_DAR
-        std     r10,PACA_EXGEN+EX_DAR(r13)
-        mfspr   r10,SPRN_DSISR
-        stw     r10,PACA_EXGEN+EX_DSISR(r13)
-        EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
-        FINISH_NAP
-        DISABLE_INTS
-        ld      r3,PACA_EXGEN+EX_DAR(r13)
-        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
-        std     r3,_DAR(r1)
-        std     r4,_DSISR(r1)
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .machine_check_exception
-        b       .ret_from_except
-
         STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ)
         STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt)
         STD_EXCEPTION_COMMON(0x980, hdecrementer, .hdec_interrupt)
@@ -1080,6 +1136,30 @@ unrecov_user_slb:
 #endif /* __DISABLED__ */
 
 
+        /*
+         * Machine check is different because we use a different
+         * save area: PACA_EXMC instead of PACA_EXGEN.
+         */
+        .align  7
+        .globl machine_check_common
+machine_check_common:
+
+        mfspr   r10,SPRN_DAR
+        std     r10,PACA_EXGEN+EX_DAR(r13)
+        mfspr   r10,SPRN_DSISR
+        stw     r10,PACA_EXGEN+EX_DSISR(r13)
+        EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
+        FINISH_NAP
+        DISABLE_INTS
+        ld      r3,PACA_EXGEN+EX_DAR(r13)
+        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
+        std     r3,_DAR(r1)
+        std     r4,_DSISR(r1)
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .machine_check_exception
+        b       .ret_from_except
+
         .align  7
         .globl alignment_common
 alignment_common:
@@ -1263,6 +1343,120 @@ _GLOBAL(opal_mc_secondary_handler)
 #endif /* CONFIG_PPC_POWERNV */
 
 
+#define MACHINE_CHECK_HANDLER_WINDUP                    \
+        /* Clear MSR_RI before setting SRR0 and SRR1. */\
+        li      r0,MSR_RI;                              \
+        mfmsr   r9;             /* get MSR value */     \
+        andc    r9,r9,r0;                               \
+        mtmsrd  r9,1;           /* Clear MSR_RI */      \
+        /* Move original SRR0 and SRR1 into the respective regs */      \
+        ld      r9,_MSR(r1);                            \
+        mtspr   SPRN_SRR1,r9;                           \
+        ld      r3,_NIP(r1);                            \
+        mtspr   SPRN_SRR0,r3;                           \
+        ld      r9,_CTR(r1);                            \
+        mtctr   r9;                                     \
+        ld      r9,_XER(r1);                            \
+        mtxer   r9;                                     \
+        ld      r9,_LINK(r1);                           \
+        mtlr    r9;                                     \
+        REST_GPR(0, r1);                                \
+        REST_8GPRS(2, r1);                              \
+        REST_GPR(10, r1);                               \
+        ld      r11,_CCR(r1);                           \
+        mtcr    r11;                                    \
+        /* Decrement paca->in_mce. */                   \
+        lhz     r12,PACA_IN_MCE(r13);                   \
+        subi    r12,r12,1;                              \
+        sth     r12,PACA_IN_MCE(r13);                   \
+        REST_GPR(11, r1);                               \
+        REST_2GPRS(12, r1);                             \
+        /* restore original r1. */                      \
+        ld      r1,GPR1(r1)
+
+        /*
+         * Handle machine check early in real mode. We come here with
+         * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
+         */
+        .align  7
+        .globl machine_check_handle_early
+machine_check_handle_early:
+        std     r0,GPR0(r1)     /* Save r0 */
+        EXCEPTION_PROLOG_COMMON_3(0x200)
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .machine_check_early
+        ld      r12,_MSR(r1)
+#ifdef  CONFIG_PPC_P7_NAP
+        /*
+         * Check if thread was in power saving mode. We come here when any
+         * of the following is true:
+         * a. thread wasn't in power saving mode
+         * b. thread was in power saving mode with no state loss or
+         *    supervisor state loss
+         *
+         * Go back to nap again if (b) is true.
+         */
+        rlwinm. r11,r12,47-31,30,31     /* Was it in power saving mode? */
+        beq     4f                      /* No, it wasn;t */
+        /* Thread was in power saving mode. Go back to nap again. */
+        cmpwi   r11,2
+        bne     3f
+        /* Supervisor state loss */
+        li      r0,1
+        stb     r0,PACA_NAPSTATELOST(r13)
+3:      bl      .machine_check_queue_event
+        MACHINE_CHECK_HANDLER_WINDUP
+        GET_PACA(r13)
+        ld      r1,PACAR1(r13)
+        b       .power7_enter_nap_mode
+4:
+#endif
+        /*
+         * Check if we are coming from hypervisor userspace. If yes then we
+         * continue in host kernel in V mode to deliver the MC event.
+         */
+        rldicl. r11,r12,4,63            /* See if MC hit while in HV mode. */
+        beq     5f
+        andi.   r11,r12,MSR_PR          /* See if coming from user. */
+        bne     9f                      /* continue in V mode if we are. */
+
+5:
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+        /*
+         * We are coming from kernel context. Check if we are coming from
+         * guest. if yes, then we can continue. We will fall through
+         * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
+         */
+        lbz     r11,HSTATE_IN_GUEST(r13)
+        cmpwi   r11,0                   /* Check if coming from guest */
+        bne     9f                      /* continue if we are. */
+#endif
+        /*
+         * At this point we are not sure about what context we come from.
+         * Queue up the MCE event and return from the interrupt.
+         * But before that, check if this is an un-recoverable exception.
+         * If yes, then stay on emergency stack and panic.
+         */
+        andi.   r11,r12,MSR_RI
+        bne     2f
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .unrecoverable_exception
+        b       1b
+2:
+        /*
+         * Return from MC interrupt.
+         * Queue up the MCE event so that we can log it later, while
+         * returning from kernel or opal call.
+         */
+        bl      .machine_check_queue_event
+        MACHINE_CHECK_HANDLER_WINDUP
+        rfid
+9:
+        /* Deliver the machine check to host kernel in V mode. */
+        MACHINE_CHECK_HANDLER_WINDUP
+        b       machine_check_pSeries
+
 /*
  * r13 points to the PACA, r9 contains the saved CR,
  * r12 contain the saved SRR1, SRR0 is still ready for return
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index f7f5b8bed68f..9ad236e5d2c9 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -81,6 +81,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 /*
+ * Enable use of the FPU, and VSX if possible, for the caller.
+ */
+_GLOBAL(fp_enable)
+        mfmsr   r3
+        ori     r3,r3,MSR_FP
+#ifdef CONFIG_VSX
+BEGIN_FTR_SECTION
+        oris    r3,r3,MSR_VSX@h
+END_FTR_SECTION_IFSET(CPU_FTR_VSX)
+#endif
+        SYNC
+        MTMSRD(r3)
+        isync                   /* (not necessary for arch 2.02 and later) */
+        blr
+
+/*
  * Load state from memory into FP registers including FPSCR.
  * Assumes the caller has enabled FP in the MSR.
  */
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index a92c79be2728..f22e7e44fbf3 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -176,6 +176,8 @@ skpinv:	addi	r6,r6,1				/* Increment */
 /* 7. Jump to KERNELBASE mapping */
         lis     r6,(KERNELBASE & ~0xfff)@h
         ori     r6,r6,(KERNELBASE & ~0xfff)@l
+        rlwinm  r7,r25,0,0x03ffffff
+        add     r6,r7,r6
 
 #elif defined(ENTRY_MAPPING_KEXEC_SETUP)
 /*
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 4f0946de2d5c..b7363bd42452 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -23,6 +23,7 @@
  */
 
 #include <linux/threads.h>
+#include <linux/init.h>
 #include <asm/reg.h>
 #include <asm/page.h>
 #include <asm/mmu.h>
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index f45726a1d963..b497188a94a1 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -65,29 +65,78 @@ _ENTRY(_start);
         nop
 
         /* Translate device tree address to physical, save in r30/r31 */
-        mfmsr   r16
-        mfspr   r17,SPRN_PID
-        rlwinm  r17,r17,16,0x3fff0000   /* turn PID into MAS6[SPID] */
-        rlwimi  r17,r16,28,0x00000001   /* turn MSR[DS] into MAS6[SAS] */
-        mtspr   SPRN_MAS6,r17
-
-        tlbsx   0,r3                    /* must succeed */
-
-        mfspr   r16,SPRN_MAS1
-        mfspr   r20,SPRN_MAS3
-        rlwinm  r17,r16,25,0x1f         /* r17 = log2(page size) */
-        li      r18,1024
-        slw     r18,r18,r17             /* r18 = page size */
-        addi    r18,r18,-1
-        and     r19,r3,r18              /* r19 = page offset */
-        andc    r31,r20,r18             /* r31 = page base */
-        or      r31,r31,r19             /* r31 = devtree phys addr */
-        mfspr   r30,SPRN_MAS7
+        bl      get_phys_addr
+        mr      r30,r3
+        mr      r31,r4
 
         li      r25,0                   /* phys kernel start (low) */
         li      r24,0                   /* CPU number */
         li      r23,0                   /* phys kernel start (high) */
 
+#ifdef CONFIG_RELOCATABLE
+        LOAD_REG_ADDR_PIC(r3, _stext)   /* Get our current runtime base */
+
+        /* Translate _stext address to physical, save in r23/r25 */
+        bl      get_phys_addr
+        mr      r23,r3
+        mr      r25,r4
+
+        bl      0f
+0:      mflr    r8
+        addis   r3,r8,(is_second_reloc - 0b)@ha
+        lwz     r19,(is_second_reloc - 0b)@l(r3)
+
+        /* Check if this is the second relocation. */
+        cmpwi   r19,1
+        bne     1f
+
+        /*
+         * For the second relocation, we already get the real memstart_addr
+         * from device tree. So we will map PAGE_OFFSET to memstart_addr,
+         * then the virtual address of start kernel should be:
+         *          PAGE_OFFSET + (kernstart_addr - memstart_addr)
+         * Since the offset between kernstart_addr and memstart_addr should
+         * never be beyond 1G, so we can just use the lower 32bit of them
+         * for the calculation.
+         */
+        lis     r3,PAGE_OFFSET@h
+
+        addis   r4,r8,(kernstart_addr - 0b)@ha
+        addi    r4,r4,(kernstart_addr - 0b)@l
+        lwz     r5,4(r4)
+
+        addis   r6,r8,(memstart_addr - 0b)@ha
+        addi    r6,r6,(memstart_addr - 0b)@l
+        lwz     r7,4(r6)
+
+        subf    r5,r7,r5
+        add     r3,r3,r5
+        b       2f
+
+1:
+        /*
+         * We have the runtime (virutal) address of our base.
+         * We calculate our shift of offset from a 64M page.
+         * We could map the 64M page we belong to at PAGE_OFFSET and
+         * get going from there.
+         */
+        lis     r4,KERNELBASE@h
+        ori     r4,r4,KERNELBASE@l
+        rlwinm  r6,r25,0,0x3ffffff              /* r6 = PHYS_START % 64M */
+        rlwinm  r5,r4,0,0x3ffffff               /* r5 = KERNELBASE % 64M */
+        subf    r3,r5,r6                        /* r3 = r6 - r5 */
+        add     r3,r4,r3                        /* Required Virtual Address */
+
+2:      bl      relocate
+
+        /*
+         * For the second relocation, we already set the right tlb entries
+         * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
+        */
+        cmpwi   r19,1
+        beq     set_ivor
+#endif
+
 /* We try to not make any assumptions about how the boot loader
  * setup or used the TLBs.  We invalidate all mappings from the
  * boot loader and load a single entry in TLB1[0] to map the
@@ -113,6 +162,7 @@ _ENTRY(__early_start)
 #include "fsl_booke_entry_mapping.S"
 #undef ENTRY_MAPPING_BOOT_SETUP
 
+set_ivor:
         /* Establish the interrupt vector offsets */
         SET_IVOR(0,  CriticalInput);
         SET_IVOR(1,  MachineCheck);
@@ -166,8 +216,7 @@ _ENTRY(__early_start)
         /* Check to see if we're the second processor, and jump
          * to the secondary_start code if so
          */
-        lis     r24, boot_cpuid@h
-        ori     r24, r24, boot_cpuid@l
+        LOAD_REG_ADDR_PIC(r24, boot_cpuid)
         lwz     r24, 0(r24)
         cmpwi   r24, -1
         mfspr   r24,SPRN_PIR
@@ -197,6 +246,18 @@ _ENTRY(__early_start)
 
         bl      early_init
 
+#ifdef CONFIG_RELOCATABLE
+        mr      r3,r30
+        mr      r4,r31
+#ifdef CONFIG_PHYS_64BIT
+        mr      r5,r23
+        mr      r6,r25
+#else
+        mr      r5,r25
+#endif
+        bl      relocate_init
+#endif
+
 #ifdef CONFIG_DYNAMIC_MEMSTART
         lis     r3,kernstart_addr@ha
         la      r3,kernstart_addr@l(r3)
@@ -856,6 +917,33 @@ KernelSPE:
 #endif /* CONFIG_SPE */
 
 /*
+ * Translate the effec addr in r3 to phys addr. The phys addr will be put
+ * into r3(higher 32bit) and r4(lower 32bit)
+ */
+get_phys_addr:
+        mfmsr   r8
+        mfspr   r9,SPRN_PID
+        rlwinm  r9,r9,16,0x3fff0000     /* turn PID into MAS6[SPID] */
+        rlwimi  r9,r8,28,0x00000001     /* turn MSR[DS] into MAS6[SAS] */
+        mtspr   SPRN_MAS6,r9
+
+        tlbsx   0,r3                    /* must succeed */
+
+        mfspr   r8,SPRN_MAS1
+        mfspr   r12,SPRN_MAS3
+        rlwinm  r9,r8,25,0x1f           /* r9 = log2(page size) */
+        li      r10,1024
+        slw     r10,r10,r9              /* r10 = page size */
+        addi    r10,r10,-1
+        and     r11,r3,r10              /* r11 = page offset */
+        andc    r4,r12,r10              /* r4 = page base */
+        or      r4,r4,r11               /* r4 = devtree phys addr */
+#ifdef CONFIG_PHYS_64BIT
+        mfspr   r3,SPRN_MAS7
+#endif
+        blr
+
+/*
  * Global functions
  */
 
@@ -1057,24 +1145,36 @@ _GLOBAL(__flush_disable_L1)
 /* When we get here, r24 needs to hold the CPU # */
         .globl __secondary_start
 __secondary_start:
-        lis     r3,__secondary_hold_acknowledge@h
-        ori     r3,r3,__secondary_hold_acknowledge@l
-        stw     r24,0(r3)
-
-        li      r3,0
-        mr      r4,r24          /* Why? */
-        bl      call_setup_cpu
-
-        lis     r3,tlbcam_index@ha
-        lwz     r3,tlbcam_index@l(r3)
+        LOAD_REG_ADDR_PIC(r3, tlbcam_index)
+        lwz     r3,0(r3)
         mtctr   r3
         li      r26,0           /* r26 safe? */
 
+        bl      switch_to_as1
+        mr      r27,r3          /* tlb entry */
         /* Load each CAM entry */
 1:      mr      r3,r26
         bl      loadcam_entry
         addi    r26,r26,1
         bdnz    1b
+        mr      r3,r27          /* tlb entry */
+        LOAD_REG_ADDR_PIC(r4, memstart_addr)
+        lwz     r4,0(r4)
+        mr      r5,r25          /* phys kernel start */
+        rlwinm  r5,r5,0,~0x3ffffff      /* aligned 64M */
+        subf    r4,r5,r4        /* memstart_addr - phys kernel start */
+        li      r5,0            /* no device tree */
+        li      r6,0            /* not boot cpu */
+        bl      restore_to_as0
+
+
+        lis     r3,__secondary_hold_acknowledge@h
+        ori     r3,r3,__secondary_hold_acknowledge@l
+        stw     r24,0(r3)
+
+        li      r3,0
+        mr      r4,r24          /* Why? */
+        bl      call_setup_cpu
 
         /* get current_thread_info and current */
         lis     r1,secondary_ti@ha
@@ -1111,6 +1211,112 @@ __secondary_hold_acknowledge:
 #endif
 
 /*
+ * Create a tlb entry with the same effective and physical address as
+ * the tlb entry used by the current running code. But set the TS to 1.
+ * Then switch to the address space 1. It will return with the r3 set to
+ * the ESEL of the new created tlb.
+ */
+_GLOBAL(switch_to_as1)
+        mflr    r5
+
+        /* Find a entry not used */
+        mfspr   r3,SPRN_TLB1CFG
+        andi.   r3,r3,0xfff
+        mfspr   r4,SPRN_PID
+        rlwinm  r4,r4,16,0x3fff0000     /* turn PID into MAS6[SPID] */
+        mtspr   SPRN_MAS6,r4
+1:      lis     r4,0x1000               /* Set MAS0(TLBSEL) = 1 */
+        addi    r3,r3,-1
+        rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
+        mtspr   SPRN_MAS0,r4
+        tlbre
+        mfspr   r4,SPRN_MAS1
+        andis.  r4,r4,MAS1_VALID@h
+        bne     1b
+
+        /* Get the tlb entry used by the current running code */
+        bl      0f
+0:      mflr    r4
+        tlbsx   0,r4
+
+        mfspr   r4,SPRN_MAS1
+        ori     r4,r4,MAS1_TS           /* Set the TS = 1 */
+        mtspr   SPRN_MAS1,r4
+
+        mfspr   r4,SPRN_MAS0
+        rlwinm  r4,r4,0,~MAS0_ESEL_MASK
+        rlwimi  r4,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
+        mtspr   SPRN_MAS0,r4
+        tlbwe
+        isync
+        sync
+
+        mfmsr   r4
+        ori     r4,r4,MSR_IS | MSR_DS
+        mtspr   SPRN_SRR0,r5
+        mtspr   SPRN_SRR1,r4
+        sync
+        rfi
+
+/*
+ * Restore to the address space 0 and also invalidate the tlb entry created
+ * by switch_to_as1.
+ * r3 - the tlb entry which should be invalidated
+ * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
+ * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
+ * r6 - boot cpu
+*/
+_GLOBAL(restore_to_as0)
+        mflr    r0
+
+        bl      0f
+0:      mflr    r9
+        addi    r9,r9,1f - 0b
+
+        /*
+         * We may map the PAGE_OFFSET in AS0 to a different physical address,
+         * so we need calculate the right jump and device tree address based
+         * on the offset passed by r4.
+         */
+        add     r9,r9,r4
+        add     r5,r5,r4
+        add     r0,r0,r4
+
+2:      mfmsr   r7
+        li      r8,(MSR_IS | MSR_DS)
+        andc    r7,r7,r8
+
+        mtspr   SPRN_SRR0,r9
+        mtspr   SPRN_SRR1,r7
+        sync
+        rfi
+
+        /* Invalidate the temporary tlb entry for AS1 */
+1:      lis     r9,0x1000               /* Set MAS0(TLBSEL) = 1 */
+        rlwimi  r9,r3,16,4,15           /* Setup MAS0 = TLBSEL | ESEL(r3) */
+        mtspr   SPRN_MAS0,r9
+        tlbre
+        mfspr   r9,SPRN_MAS1
+        rlwinm  r9,r9,0,2,31            /* Clear MAS1 Valid and IPPROT */
+        mtspr   SPRN_MAS1,r9
+        tlbwe
+        isync
+
+        cmpwi   r4,0
+        cmpwi   cr1,r6,0
+        cror    eq,4*cr1+eq,eq
+        bne     3f                      /* offset != 0 && is_boot_cpu */
+        mtlr    r0
+        blr
+
+        /*
+         * The PAGE_OFFSET will map to a different physical address,
+         * jump to _start to do another relocation again.
+        */
+3:      mr      r3,r5
+        bl      _start
+
+/*
  * We put a few things here that have to be page-aligned. This stuff
  * goes at the beginning of the data segment, which is page-aligned.
  */
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index f0b47d1a6b0e..b0a1792279bb 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -28,7 +28,6 @@
 #include <linux/percpu.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 
 #include <asm/hw_breakpoint.h>
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 847e40e62fce..3fdef0f0c67f 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -84,6 +84,7 @@ _GLOBAL(power7_nap)
         std     r9,_MSR(r1)
         std     r1,PACAR1(r13)
 
+_GLOBAL(power7_enter_nap_mode)
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
         /* Tell KVM we're napping */
         li      r4,KVM_HWTHREAD_IN_NAP
diff --git a/arch/powerpc/kernel/iomap.c b/arch/powerpc/kernel/iomap.c
index 97a3715ac8bd..b82227e7e21b 100644
--- a/arch/powerpc/kernel/iomap.c
+++ b/arch/powerpc/kernel/iomap.c
@@ -3,7 +3,6 @@
  *
  * (C) Copyright 2004 Linus Torvalds
  */
-#include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/mm.h>
 #include <linux/export.h>
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 572bb5b95f35..d773dd440a45 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -251,14 +251,13 @@ again:
 
         if (dev)
                 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
-                                      1 << IOMMU_PAGE_SHIFT);
+                                      1 << tbl->it_page_shift);
         else
-                boundary_size = ALIGN(1UL << 32, 1 << IOMMU_PAGE_SHIFT);
+                boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
         /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
 
-        n = iommu_area_alloc(tbl->it_map, limit, start, npages,
-                             tbl->it_offset, boundary_size >> IOMMU_PAGE_SHIFT,
-                             align_mask);
+        n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
+                             boundary_size >> tbl->it_page_shift, align_mask);
         if (n == -1) {
                 if (likely(pass == 0)) {
                         /* First try the pool from the start */
@@ -320,12 +319,12 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
                 return DMA_ERROR_CODE;
 
         entry += tbl->it_offset;        /* Offset into real TCE table */
-        ret = entry << IOMMU_PAGE_SHIFT;        /* Set the return dma address */
+        ret = entry << tbl->it_page_shift;      /* Set the return dma address */
 
         /* Put the TCEs in the HW table */
         build_fail = ppc_md.tce_build(tbl, entry, npages,
-                                      (unsigned long)page & IOMMU_PAGE_MASK,
-                                      direction, attrs);
+                                      (unsigned long)page &
+                                      IOMMU_PAGE_MASK(tbl), direction, attrs);
 
         /* ppc_md.tce_build() only returns non-zero for transient errors.
          * Clean up the table bitmap in this case and return
@@ -352,7 +351,7 @@ static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
 {
         unsigned long entry, free_entry;
 
-        entry = dma_addr >> IOMMU_PAGE_SHIFT;
+        entry = dma_addr >> tbl->it_page_shift;
         free_entry = entry - tbl->it_offset;
 
         if (((free_entry + npages) > tbl->it_size) ||
@@ -401,7 +400,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
         unsigned long flags;
         struct iommu_pool *pool;
 
-        entry = dma_addr >> IOMMU_PAGE_SHIFT;
+        entry = dma_addr >> tbl->it_page_shift;
         free_entry = entry - tbl->it_offset;
 
         pool = get_pool(tbl, free_entry);
@@ -468,13 +467,13 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                 }
                 /* Allocate iommu entries for that segment */
                 vaddr = (unsigned long) sg_virt(s);
-                npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE);
+                npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
                 align = 0;
-                if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && slen >= PAGE_SIZE &&
+                if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
                     (vaddr & ~PAGE_MASK) == 0)
-                        align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
+                        align = PAGE_SHIFT - tbl->it_page_shift;
                 entry = iommu_range_alloc(dev, tbl, npages, &handle,
-                                          mask >> IOMMU_PAGE_SHIFT, align);
+                                          mask >> tbl->it_page_shift, align);
 
                 DBG("  - vaddr: %lx, size: %lx\n", vaddr, slen);
 
@@ -489,16 +488,16 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
 
                 /* Convert entry to a dma_addr_t */
                 entry += tbl->it_offset;
-                dma_addr = entry << IOMMU_PAGE_SHIFT;
-                dma_addr |= (s->offset & ~IOMMU_PAGE_MASK);
+                dma_addr = entry << tbl->it_page_shift;
+                dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
 
                 DBG("  - %lu pages, entry: %lx, dma_addr: %lx\n",
                             npages, entry, dma_addr);
 
                 /* Insert into HW table */
                 build_fail = ppc_md.tce_build(tbl, entry, npages,
-                                              vaddr & IOMMU_PAGE_MASK,
-                                              direction, attrs);
+                                              vaddr & IOMMU_PAGE_MASK(tbl),
+                                              direction, attrs);
                 if(unlikely(build_fail))
                         goto failure;
 
@@ -559,9 +558,9 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                 if (s->dma_length != 0) {
                         unsigned long vaddr, npages;
 
-                        vaddr = s->dma_address & IOMMU_PAGE_MASK;
+                        vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
                         npages = iommu_num_pages(s->dma_address, s->dma_length,
-                                                 IOMMU_PAGE_SIZE);
+                                                 IOMMU_PAGE_SIZE(tbl));
                         __iommu_free(tbl, vaddr, npages);
                         s->dma_address = DMA_ERROR_CODE;
                         s->dma_length = 0;
@@ -592,7 +591,7 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
                 if (sg->dma_length == 0)
                         break;
                 npages = iommu_num_pages(dma_handle, sg->dma_length,
-                                         IOMMU_PAGE_SIZE);
+                                         IOMMU_PAGE_SIZE(tbl));
                 __iommu_free(tbl, dma_handle, npages);
                 sg = sg_next(sg);
         }
@@ -676,7 +675,7 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
                 set_bit(0, tbl->it_map);
 
         /* We only split the IOMMU table if we have 1GB or more of space */
-        if ((tbl->it_size << IOMMU_PAGE_SHIFT) >= (1UL * 1024 * 1024 * 1024))
+        if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
                 tbl->nr_pools = IOMMU_NR_POOLS;
         else
                 tbl->nr_pools = 1;
@@ -768,16 +767,16 @@ dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
 
         vaddr = page_address(page) + offset;
         uaddr = (unsigned long)vaddr;
-        npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE);
+        npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
 
         if (tbl) {
                 align = 0;
-                if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && size >= PAGE_SIZE &&
+                if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
                     ((unsigned long)vaddr & ~PAGE_MASK) == 0)
-                        align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
+                        align = PAGE_SHIFT - tbl->it_page_shift;
 
                 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
-                                         mask >> IOMMU_PAGE_SHIFT, align,
+                                         mask >> tbl->it_page_shift, align,
                                          attrs);
                 if (dma_handle == DMA_ERROR_CODE) {
                         if (printk_ratelimit())  {
@@ -786,7 +785,7 @@ dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
                                          npages);
                         }
                 } else
-                        dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
+                        dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
         }
 
         return dma_handle;
@@ -801,7 +800,8 @@ void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
         BUG_ON(direction == DMA_NONE);
 
         if (tbl) {
-                npages = iommu_num_pages(dma_handle, size, IOMMU_PAGE_SIZE);
+                npages = iommu_num_pages(dma_handle, size,
+                                         IOMMU_PAGE_SIZE(tbl));
                 iommu_free(tbl, dma_handle, npages);
         }
 }
@@ -845,10 +845,10 @@ void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
         memset(ret, 0, size);
 
         /* Set up tces to cover the allocated range */
-        nio_pages = size >> IOMMU_PAGE_SHIFT;
-        io_order = get_iommu_order(size);
+        nio_pages = size >> tbl->it_page_shift;
+        io_order = get_iommu_order(size, tbl);
         mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
-                              mask >> IOMMU_PAGE_SHIFT, io_order, NULL);
+                              mask >> tbl->it_page_shift, io_order, NULL);
         if (mapping == DMA_ERROR_CODE) {
                 free_pages((unsigned long)ret, order);
                 return NULL;
@@ -864,7 +864,7 @@ void iommu_free_coherent(struct iommu_table *tbl, size_t size,
                 unsigned int nio_pages;
 
                 size = PAGE_ALIGN(size);
-                nio_pages = size >> IOMMU_PAGE_SHIFT;
+                nio_pages = size >> tbl->it_page_shift;
                 iommu_free(tbl, dma_handle, nio_pages);
                 size = PAGE_ALIGN(size);
                 free_pages((unsigned long)vaddr, get_order(size));
@@ -935,10 +935,10 @@ int iommu_tce_clear_param_check(struct iommu_table *tbl,
         if (tce_value)
                 return -EINVAL;
 
-        if (ioba & ~IOMMU_PAGE_MASK)
+        if (ioba & ~IOMMU_PAGE_MASK(tbl))
                 return -EINVAL;
 
-        ioba >>= IOMMU_PAGE_SHIFT;
+        ioba >>= tbl->it_page_shift;
         if (ioba < tbl->it_offset)
                 return -EINVAL;
 
@@ -955,13 +955,13 @@ int iommu_tce_put_param_check(struct iommu_table *tbl,
         if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))
                 return -EINVAL;
 
-        if (tce & ~(IOMMU_PAGE_MASK | TCE_PCI_WRITE | TCE_PCI_READ))
+        if (tce & ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))
                 return -EINVAL;
 
-        if (ioba & ~IOMMU_PAGE_MASK)
+        if (ioba & ~IOMMU_PAGE_MASK(tbl))
                 return -EINVAL;
 
-        ioba >>= IOMMU_PAGE_SHIFT;
+        ioba >>= tbl->it_page_shift;
         if (ioba < tbl->it_offset)
                 return -EINVAL;
 
@@ -1037,7 +1037,7 @@ int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
 
         /* if (unlikely(ret))
                 pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
-                                __func__, hwaddr, entry << IOMMU_PAGE_SHIFT,
+                        __func__, hwaddr, entry << IOMMU_PAGE_SHIFT(tbl),
                                 hwaddr, ret); */
 
         return ret;
@@ -1049,14 +1049,14 @@ int iommu_put_tce_user_mode(struct iommu_table *tbl, unsigned long entry,
 {
         int ret;
         struct page *page = NULL;
-        unsigned long hwaddr, offset = tce & IOMMU_PAGE_MASK & ~PAGE_MASK;
+        unsigned long hwaddr, offset = tce & IOMMU_PAGE_MASK(tbl) & ~PAGE_MASK;
         enum dma_data_direction direction = iommu_tce_direction(tce);
 
         ret = get_user_pages_fast(tce & PAGE_MASK, 1,
                         direction != DMA_TO_DEVICE, &page);
         if (unlikely(ret != 1)) {
                 /* pr_err("iommu_tce: get_user_pages_fast failed tce=%lx ioba=%lx ret=%d\n",
-                                tce, entry << IOMMU_PAGE_SHIFT, ret); */
+                                tce, entry << IOMMU_PAGE_SHIFT(tbl), ret); */
                 return -EFAULT;
         }
         hwaddr = (unsigned long) page_address(page) + offset;
@@ -1067,7 +1067,7 @@ int iommu_put_tce_user_mode(struct iommu_table *tbl, unsigned long entry,
 
         if (ret < 0)
                 pr_err("iommu_tce: %s failed ioba=%lx, tce=%lx, ret=%d\n",
-                                __func__, entry << IOMMU_PAGE_SHIFT, tce, ret);
+                        __func__, entry << tbl->it_page_shift, tce, ret);
 
         return ret;
 }
@@ -1105,7 +1105,7 @@ void iommu_release_ownership(struct iommu_table *tbl)
 }
 EXPORT_SYMBOL_GPL(iommu_release_ownership);
 
-static int iommu_add_device(struct device *dev)
+int iommu_add_device(struct device *dev)
 {
         struct iommu_table *tbl;
         int ret = 0;
@@ -1127,6 +1127,12 @@ static int iommu_add_device(struct device *dev)
         pr_debug("iommu_tce: adding %s to iommu group %d\n",
                         dev_name(dev), iommu_group_id(tbl->it_group));
 
+        if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
+                pr_err("iommu_tce: unsupported iommu page size.");
+                pr_err("%s has not been added\n", dev_name(dev));
+                return -EINVAL;
+        }
+
         ret = iommu_group_add_device(tbl->it_group, dev);
         if (ret < 0)
                 pr_err("iommu_tce: %s has not been added, ret=%d\n",
@@ -1134,52 +1140,23 @@ static int iommu_add_device(struct device *dev)
 
         return ret;
 }
+EXPORT_SYMBOL_GPL(iommu_add_device);
 
-static void iommu_del_device(struct device *dev)
-{
-        iommu_group_remove_device(dev);
-}
-
-static int iommu_bus_notifier(struct notifier_block *nb,
-                              unsigned long action, void *data)
+void iommu_del_device(struct device *dev)
 {
-        struct device *dev = data;
-
-        switch (action) {
-        case BUS_NOTIFY_ADD_DEVICE:
-                return iommu_add_device(dev);
-        case BUS_NOTIFY_DEL_DEVICE:
-                iommu_del_device(dev);
-                return 0;
-        default:
-                return 0;
+        /*
+         * Some devices might not have IOMMU table and group
+         * and we needn't detach them from the associated
+         * IOMMU groups
+         */
+        if (!dev->iommu_group) {
+                pr_debug("iommu_tce: skipping device %s with no tbl\n",
+                         dev_name(dev));
+                return;
         }
-}
 
-static struct notifier_block tce_iommu_bus_nb = {
-        .notifier_call = iommu_bus_notifier,
-};
-
-static int __init tce_iommu_init(void)
-{
-        struct pci_dev *pdev = NULL;
-
-        BUILD_BUG_ON(PAGE_SIZE < IOMMU_PAGE_SIZE);
-
-        for_each_pci_dev(pdev)
-                iommu_add_device(&pdev->dev);
-
-        bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
-        return 0;
-}
-
-subsys_initcall_sync(tce_iommu_init);
-
-#else
-
-void iommu_register_group(struct iommu_table *tbl,
-                int pci_domain_number, unsigned long pe_num)
-{
+        iommu_group_remove_device(dev);
 }
+EXPORT_SYMBOL_GPL(iommu_del_device);
 
 #endif /* CONFIG_IOMMU_API */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index ba0165615215..9729b23bfb0a 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -354,8 +354,13 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 
         seq_printf(p, "%*s: ", prec, "LOC");
         for_each_online_cpu(j)
-                seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs);
-        seq_printf(p, "  Local timer interrupts\n");
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
+        seq_printf(p, "  Local timer interrupts for timer event device\n");
+
+        seq_printf(p, "%*s: ", prec, "LOC");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
+        seq_printf(p, "  Local timer interrupts for others\n");
 
         seq_printf(p, "%*s: ", prec, "SPU");
         for_each_online_cpu(j)
@@ -389,11 +394,12 @@ int arch_show_interrupts(struct seq_file *p, int prec)
  */
 u64 arch_irq_stat_cpu(unsigned int cpu)
 {
-        u64 sum = per_cpu(irq_stat, cpu).timer_irqs;
+        u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
 
         sum += per_cpu(irq_stat, cpu).pmu_irqs;
         sum += per_cpu(irq_stat, cpu).mce_exceptions;
         sum += per_cpu(irq_stat, cpu).spurious_irqs;
+        sum += per_cpu(irq_stat, cpu).timer_irqs_others;
 #ifdef CONFIG_PPC_DOORBELL
         sum += per_cpu(irq_stat, cpu).doorbell_irqs;
 #endif
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 83e89d310734..8504657379f1 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -15,7 +15,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/kgdb.h>
 #include <linux/smp.h>
 #include <linux/signal.h>
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index db28032e320e..6a0175297b0d 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -413,13 +413,13 @@ static void kvm_map_magic_page(void *data)
 {
         u32 *features = data;
 
-        ulong in[8];
+        ulong in[8] = {0};
         ulong out[8];
 
         in[0] = KVM_MAGIC_PAGE;
         in[1] = KVM_MAGIC_PAGE;
 
-        kvm_hypercall(in, out, KVM_HCALL_TOKEN(KVM_HC_PPC_MAP_MAGIC_PAGE));
+        epapr_hypercall(in, out, KVM_HCALL_TOKEN(KVM_HC_PPC_MAP_MAGIC_PAGE));
 
         *features = out[0];
 }
@@ -711,43 +711,6 @@ static void kvm_use_magic_page(void)
                          kvm_patching_worked ? "worked" : "failed");
 }
 
-unsigned long kvm_hypercall(unsigned long *in,
-                            unsigned long *out,
-                            unsigned long nr)
-{
-        unsigned long register r0 asm("r0");
-        unsigned long register r3 asm("r3") = in[0];
-        unsigned long register r4 asm("r4") = in[1];
-        unsigned long register r5 asm("r5") = in[2];
-        unsigned long register r6 asm("r6") = in[3];
-        unsigned long register r7 asm("r7") = in[4];
-        unsigned long register r8 asm("r8") = in[5];
-        unsigned long register r9 asm("r9") = in[6];
-        unsigned long register r10 asm("r10") = in[7];
-        unsigned long register r11 asm("r11") = nr;
-        unsigned long register r12 asm("r12");
-
-        asm volatile("bl        epapr_hypercall_start"
-                     : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6),
-                       "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11),
-                       "=r"(r12)
-                     : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8),
-                       "r"(r9), "r"(r10), "r"(r11)
-                     : "memory", "cc", "xer", "ctr", "lr");
-
-        out[0] = r4;
-        out[1] = r5;
-        out[2] = r6;
-        out[3] = r7;
-        out[4] = r8;
-        out[5] = r9;
-        out[6] = r10;
-        out[7] = r11;
-
-        return r3;
-}
-EXPORT_SYMBOL_GPL(kvm_hypercall);
-
 static __init void kvm_free_tmp(void)
 {
         free_reserved_area(&kvm_tmp[kvm_tmp_index],
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
new file mode 100644
index 000000000000..cadef7e64e42
--- /dev/null
+++ b/arch/powerpc/kernel/mce.c
@@ -0,0 +1,352 @@
+/*
+ * Machine check exception handling.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2013 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#undef DEBUG
+#define pr_fmt(fmt) "mce: " fmt
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+#include <linux/export.h>
+#include <linux/irq_work.h>
+#include <asm/mce.h>
+
+static DEFINE_PER_CPU(int, mce_nest_count);
+static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event);
+
+/* Queue for delayed MCE events. */
+static DEFINE_PER_CPU(int, mce_queue_count);
+static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event_queue);
+
+static void machine_check_process_queued_event(struct irq_work *work);
+struct irq_work mce_event_process_work = {
+        .func = machine_check_process_queued_event,
+};
+
+static void mce_set_error_info(struct machine_check_event *mce,
+                               struct mce_error_info *mce_err)
+{
+        mce->error_type = mce_err->error_type;
+        switch (mce_err->error_type) {
+        case MCE_ERROR_TYPE_UE:
+                mce->u.ue_error.ue_error_type = mce_err->u.ue_error_type;
+                break;
+        case MCE_ERROR_TYPE_SLB:
+                mce->u.slb_error.slb_error_type = mce_err->u.slb_error_type;
+                break;
+        case MCE_ERROR_TYPE_ERAT:
+                mce->u.erat_error.erat_error_type = mce_err->u.erat_error_type;
+                break;
+        case MCE_ERROR_TYPE_TLB:
+                mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;
+                break;
+        case MCE_ERROR_TYPE_UNKNOWN:
+        default:
+                break;
+        }
+}
+
+/*
+ * Decode and save high level MCE information into per cpu buffer which
+ * is an array of machine_check_event structure.
+ */
+void save_mce_event(struct pt_regs *regs, long handled,
+                    struct mce_error_info *mce_err,
+                    uint64_t addr)
+{
+        uint64_t srr1;
+        int index = __get_cpu_var(mce_nest_count)++;
+        struct machine_check_event *mce = &__get_cpu_var(mce_event[index]);
+
+        /*
+         * Return if we don't have enough space to log mce event.
+         * mce_nest_count may go beyond MAX_MC_EVT but that's ok,
+         * the check below will stop buffer overrun.
+         */
+        if (index >= MAX_MC_EVT)
+                return;
+
+        /* Populate generic machine check info */
+        mce->version = MCE_V1;
+        mce->srr0 = regs->nip;
+        mce->srr1 = regs->msr;
+        mce->gpr3 = regs->gpr[3];
+        mce->in_use = 1;
+
+        mce->initiator = MCE_INITIATOR_CPU;
+        if (handled)
+                mce->disposition = MCE_DISPOSITION_RECOVERED;
+        else
+                mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;
+        mce->severity = MCE_SEV_ERROR_SYNC;
+
+        srr1 = regs->msr;
+
+        /*
+         * Populate the mce error_type and type-specific error_type.
+         */
+        mce_set_error_info(mce, mce_err);
+
+        if (!addr)
+                return;
+
+        if (mce->error_type == MCE_ERROR_TYPE_TLB) {
+                mce->u.tlb_error.effective_address_provided = true;
+                mce->u.tlb_error.effective_address = addr;
+        } else if (mce->error_type == MCE_ERROR_TYPE_SLB) {
+                mce->u.slb_error.effective_address_provided = true;
+                mce->u.slb_error.effective_address = addr;
+        } else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {
+                mce->u.erat_error.effective_address_provided = true;
+                mce->u.erat_error.effective_address = addr;
+        } else if (mce->error_type == MCE_ERROR_TYPE_UE) {
+                mce->u.ue_error.effective_address_provided = true;
+                mce->u.ue_error.effective_address = addr;
+        }
+        return;
+}
+
+/*
+ * get_mce_event:
+ *      mce     Pointer to machine_check_event structure to be filled.
+ *      release Flag to indicate whether to free the event slot or not.
+ *              0 <= do not release the mce event. Caller will invoke
+ *                   release_mce_event() once event has been consumed.
+ *              1 <= release the slot.
+ *
+ *      return  1 = success
+ *              0 = failure
+ *
+ * get_mce_event() will be called by platform specific machine check
+ * handle routine and in KVM.
+ * When we call get_mce_event(), we are still in interrupt context and
+ * preemption will not be scheduled until ret_from_expect() routine
+ * is called.
+ */
+int get_mce_event(struct machine_check_event *mce, bool release)
+{
+        int index = __get_cpu_var(mce_nest_count) - 1;
+        struct machine_check_event *mc_evt;
+        int ret = 0;
+
+        /* Sanity check */
+        if (index < 0)
+                return ret;
+
+        /* Check if we have MCE info to process. */
+        if (index < MAX_MC_EVT) {
+                mc_evt = &__get_cpu_var(mce_event[index]);
+                /* Copy the event structure and release the original */
+                if (mce)
+                        *mce = *mc_evt;
+                if (release)
+                        mc_evt->in_use = 0;
+                ret = 1;
+        }
+        /* Decrement the count to free the slot. */
+        if (release)
+                __get_cpu_var(mce_nest_count)--;
+
+        return ret;
+}
+
+void release_mce_event(void)
+{
+        get_mce_event(NULL, true);
+}
+
+/*
+ * Queue up the MCE event which then can be handled later.
+ */
+void machine_check_queue_event(void)
+{
+        int index;
+        struct machine_check_event evt;
+
+        if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
+                return;
+
+        index = __get_cpu_var(mce_queue_count)++;
+        /* If queue is full, just return for now. */
+        if (index >= MAX_MC_EVT) {
+                __get_cpu_var(mce_queue_count)--;
+                return;
+        }
+        __get_cpu_var(mce_event_queue[index]) = evt;
+
+        /* Queue irq work to process this event later. */
+        irq_work_queue(&mce_event_process_work);
+}
+
+/*
+ * process pending MCE event from the mce event queue. This function will be
+ * called during syscall exit.
+ */
+static void machine_check_process_queued_event(struct irq_work *work)
+{
+        int index;
+
+        /*
+         * For now just print it to console.
+         * TODO: log this error event to FSP or nvram.
+         */
+        while (__get_cpu_var(mce_queue_count) > 0) {
+                index = __get_cpu_var(mce_queue_count) - 1;
+                machine_check_print_event_info(
+                                &__get_cpu_var(mce_event_queue[index]));
+                __get_cpu_var(mce_queue_count)--;
+        }
+}
+
+void machine_check_print_event_info(struct machine_check_event *evt)
+{
+        const char *level, *sevstr, *subtype;
+        static const char *mc_ue_types[] = {
+                "Indeterminate",
+                "Instruction fetch",
+                "Page table walk ifetch",
+                "Load/Store",
+                "Page table walk Load/Store",
+        };
+        static const char *mc_slb_types[] = {
+                "Indeterminate",
+                "Parity",
+                "Multihit",
+        };
+        static const char *mc_erat_types[] = {
+                "Indeterminate",
+                "Parity",
+                "Multihit",
+        };
+        static const char *mc_tlb_types[] = {
+                "Indeterminate",
+                "Parity",
+                "Multihit",
+        };
+
+        /* Print things out */
+        if (evt->version != MCE_V1) {
+                pr_err("Machine Check Exception, Unknown event version %d !\n",
+                       evt->version);
+                return;
+        }
+        switch (evt->severity) {
+        case MCE_SEV_NO_ERROR:
+                level = KERN_INFO;
+                sevstr = "Harmless";
+                break;
+        case MCE_SEV_WARNING:
+                level = KERN_WARNING;
+                sevstr = "";
+                break;
+        case MCE_SEV_ERROR_SYNC:
+                level = KERN_ERR;
+                sevstr = "Severe";
+                break;
+        case MCE_SEV_FATAL:
+        default:
+                level = KERN_ERR;
+                sevstr = "Fatal";
+                break;
+        }
+
+        printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
+               evt->disposition == MCE_DISPOSITION_RECOVERED ?
+               "Recovered" : "[Not recovered");
+        printk("%s  Initiator: %s\n", level,
+               evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
+        switch (evt->error_type) {
+        case MCE_ERROR_TYPE_UE:
+                subtype = evt->u.ue_error.ue_error_type <
+                        ARRAY_SIZE(mc_ue_types) ?
+                        mc_ue_types[evt->u.ue_error.ue_error_type]
+                        : "Unknown";
+                printk("%s  Error type: UE [%s]\n", level, subtype);
+                if (evt->u.ue_error.effective_address_provided)
+                        printk("%s    Effective address: %016llx\n",
+                               level, evt->u.ue_error.effective_address);
+                if (evt->u.ue_error.physical_address_provided)
+                        printk("%s      Physial address: %016llx\n",
+                               level, evt->u.ue_error.physical_address);
+                break;
+        case MCE_ERROR_TYPE_SLB:
+                subtype = evt->u.slb_error.slb_error_type <
+                        ARRAY_SIZE(mc_slb_types) ?
+                        mc_slb_types[evt->u.slb_error.slb_error_type]
+                        : "Unknown";
+                printk("%s  Error type: SLB [%s]\n", level, subtype);
+                if (evt->u.slb_error.effective_address_provided)
+                        printk("%s    Effective address: %016llx\n",
+                               level, evt->u.slb_error.effective_address);
+                break;
+        case MCE_ERROR_TYPE_ERAT:
+                subtype = evt->u.erat_error.erat_error_type <
+                        ARRAY_SIZE(mc_erat_types) ?
+                        mc_erat_types[evt->u.erat_error.erat_error_type]
+                        : "Unknown";
+                printk("%s  Error type: ERAT [%s]\n", level, subtype);
+                if (evt->u.erat_error.effective_address_provided)
+                        printk("%s    Effective address: %016llx\n",
+                               level, evt->u.erat_error.effective_address);
+                break;
+        case MCE_ERROR_TYPE_TLB:
+                subtype = evt->u.tlb_error.tlb_error_type <
+                        ARRAY_SIZE(mc_tlb_types) ?
+                        mc_tlb_types[evt->u.tlb_error.tlb_error_type]
+                        : "Unknown";
+                printk("%s  Error type: TLB [%s]\n", level, subtype);
+                if (evt->u.tlb_error.effective_address_provided)
+                        printk("%s    Effective address: %016llx\n",
+                               level, evt->u.tlb_error.effective_address);
+                break;
+        default:
+        case MCE_ERROR_TYPE_UNKNOWN:
+                printk("%s  Error type: Unknown\n", level);
+                break;
+        }
+}
+
+uint64_t get_mce_fault_addr(struct machine_check_event *evt)
+{
+        switch (evt->error_type) {
+        case MCE_ERROR_TYPE_UE:
+                if (evt->u.ue_error.effective_address_provided)
+                        return evt->u.ue_error.effective_address;
+                break;
+        case MCE_ERROR_TYPE_SLB:
+                if (evt->u.slb_error.effective_address_provided)
+                        return evt->u.slb_error.effective_address;
+                break;
+        case MCE_ERROR_TYPE_ERAT:
+                if (evt->u.erat_error.effective_address_provided)
+                        return evt->u.erat_error.effective_address;
+                break;
+        case MCE_ERROR_TYPE_TLB:
+                if (evt->u.tlb_error.effective_address_provided)
+                        return evt->u.tlb_error.effective_address;
+                break;
+        default:
+        case MCE_ERROR_TYPE_UNKNOWN:
+                break;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(get_mce_fault_addr);
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
new file mode 100644
index 000000000000..27c93f41166f
--- /dev/null
+++ b/arch/powerpc/kernel/mce_power.c
@@ -0,0 +1,284 @@
+/*
+ * Machine check exception handling CPU-side for power7 and power8
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2013 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#undef DEBUG
+#define pr_fmt(fmt) "mce_power: " fmt
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <asm/mmu.h>
+#include <asm/mce.h>
+
+/* flush SLBs and reload */
+static void flush_and_reload_slb(void)
+{
+        struct slb_shadow *slb;
+        unsigned long i, n;
+
+        /* Invalidate all SLBs */
+        asm volatile("slbmte %0,%0; slbia" : : "r" (0));
+
+#ifdef CONFIG_KVM_BOOK3S_HANDLER
+        /*
+         * If machine check is hit when in guest or in transition, we will
+         * only flush the SLBs and continue.
+         */
+        if (get_paca()->kvm_hstate.in_guest)
+                return;
+#endif
+
+        /* For host kernel, reload the SLBs from shadow SLB buffer. */
+        slb = get_slb_shadow();
+        if (!slb)
+                return;
+
+        n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE);
+
+        /* Load up the SLB entries from shadow SLB */
+        for (i = 0; i < n; i++) {
+                unsigned long rb = be64_to_cpu(slb->save_area[i].esid);
+                unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
+
+                rb = (rb & ~0xFFFul) | i;
+                asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
+        }
+}
+
+static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
+{
+        long handled = 1;
+
+        /*
+         * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
+         * reset the error bits whenever we handle them so that at the end
+         * we can check whether we handled all of them or not.
+         * */
+        if (dsisr & slb_error_bits) {
+                flush_and_reload_slb();
+                /* reset error bits */
+                dsisr &= ~(slb_error_bits);
+        }
+        if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
+                if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
+                        cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
+                /* reset error bits */
+                dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
+        }
+        /* Any other errors we don't understand? */
+        if (dsisr & 0xffffffffUL)
+                handled = 0;
+
+        return handled;
+}
+
+static long mce_handle_derror_p7(uint64_t dsisr)
+{
+        return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
+}
+
+static long mce_handle_common_ierror(uint64_t srr1)
+{
+        long handled = 0;
+
+        switch (P7_SRR1_MC_IFETCH(srr1)) {
+        case 0:
+                break;
+        case P7_SRR1_MC_IFETCH_SLB_PARITY:
+        case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
+                /* flush and reload SLBs for SLB errors. */
+                flush_and_reload_slb();
+                handled = 1;
+                break;
+        case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
+                if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
+                        cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
+                        handled = 1;
+                }
+                break;
+        default:
+                break;
+        }
+
+        return handled;
+}
+
+static long mce_handle_ierror_p7(uint64_t srr1)
+{
+        long handled = 0;
+
+        handled = mce_handle_common_ierror(srr1);
+
+        if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
+                flush_and_reload_slb();
+                handled = 1;
+        }
+        return handled;
+}
+
+static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1)
+{
+        switch (P7_SRR1_MC_IFETCH(srr1)) {
+        case P7_SRR1_MC_IFETCH_SLB_PARITY:
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
+                break;
+        case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
+                break;
+        case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
+                mce_err->error_type = MCE_ERROR_TYPE_TLB;
+                mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
+                break;
+        case P7_SRR1_MC_IFETCH_UE:
+        case P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL:
+                mce_err->error_type = MCE_ERROR_TYPE_UE;
+                mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
+                break;
+        case P7_SRR1_MC_IFETCH_UE_TLB_RELOAD:
+                mce_err->error_type = MCE_ERROR_TYPE_UE;
+                mce_err->u.ue_error_type =
+                                MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
+                break;
+        }
+}
+
+static void mce_get_ierror_p7(struct mce_error_info *mce_err, uint64_t srr1)
+{
+        mce_get_common_ierror(mce_err, srr1);
+        if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
+        }
+}
+
+static void mce_get_derror_p7(struct mce_error_info *mce_err, uint64_t dsisr)
+{
+        if (dsisr & P7_DSISR_MC_UE) {
+                mce_err->error_type = MCE_ERROR_TYPE_UE;
+                mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
+        } else if (dsisr & P7_DSISR_MC_UE_TABLEWALK) {
+                mce_err->error_type = MCE_ERROR_TYPE_UE;
+                mce_err->u.ue_error_type =
+                                MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
+        } else if (dsisr & P7_DSISR_MC_ERAT_MULTIHIT) {
+                mce_err->error_type = MCE_ERROR_TYPE_ERAT;
+                mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
+        } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT) {
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
+        } else if (dsisr & P7_DSISR_MC_SLB_PARITY_MFSLB) {
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
+        } else if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
+                mce_err->error_type = MCE_ERROR_TYPE_TLB;
+                mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
+        } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT_PARITY) {
+                mce_err->error_type = MCE_ERROR_TYPE_SLB;
+                mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
+        }
+}
+
+long __machine_check_early_realmode_p7(struct pt_regs *regs)
+{
+        uint64_t srr1, addr;
+        long handled = 1;
+        struct mce_error_info mce_error_info = { 0 };
+
+        srr1 = regs->msr;
+
+        /*
+         * Handle memory errors depending whether this was a load/store or
+         * ifetch exception. Also, populate the mce error_type and
+         * type-specific error_type from either SRR1 or DSISR, depending
+         * whether this was a load/store or ifetch exception
+         */
+        if (P7_SRR1_MC_LOADSTORE(srr1)) {
+                handled = mce_handle_derror_p7(regs->dsisr);
+                mce_get_derror_p7(&mce_error_info, regs->dsisr);
+                addr = regs->dar;
+        } else {
+                handled = mce_handle_ierror_p7(srr1);
+                mce_get_ierror_p7(&mce_error_info, srr1);
+                addr = regs->nip;
+        }
+
+        save_mce_event(regs, handled, &mce_error_info, addr);
+        return handled;
+}
+
+static void mce_get_ierror_p8(struct mce_error_info *mce_err, uint64_t srr1)
+{
+        mce_get_common_ierror(mce_err, srr1);
+        if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
+                mce_err->error_type = MCE_ERROR_TYPE_ERAT;
+                mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
+        }
+}
+
+static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr)
+{
+        mce_get_derror_p7(mce_err, dsisr);
+        if (dsisr & P8_DSISR_MC_ERAT_MULTIHIT_SEC) {
+                mce_err->error_type = MCE_ERROR_TYPE_ERAT;
+                mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
+        }
+}
+
+static long mce_handle_ierror_p8(uint64_t srr1)
+{
+        long handled = 0;
+
+        handled = mce_handle_common_ierror(srr1);
+
+        if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
+                flush_and_reload_slb();
+                handled = 1;
+        }
+        return handled;
+}
+
+static long mce_handle_derror_p8(uint64_t dsisr)
+{
+        return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
+}
+
+long __machine_check_early_realmode_p8(struct pt_regs *regs)
+{
+        uint64_t srr1, addr;
+        long handled = 1;
+        struct mce_error_info mce_error_info = { 0 };
+
+        srr1 = regs->msr;
+
+        if (P7_SRR1_MC_LOADSTORE(srr1)) {
+                handled = mce_handle_derror_p8(regs->dsisr);
+                mce_get_derror_p8(&mce_error_info, regs->dsisr);
+                addr = regs->dar;
+        } else {
+                handled = mce_handle_ierror_p8(srr1);
+                mce_get_ierror_p8(&mce_error_info, srr1);
+                addr = regs->nip;
+        }
+
+        save_mce_event(regs, handled, &mce_error_info, addr);
+        return handled;
+}
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index e47d268727a4..879f09620f83 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -344,7 +344,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
  */
 _KPROBE(flush_icache_range)
 BEGIN_FTR_SECTION
-        isync
+        PURGE_PREFETCHED_INS
         blr                             /* for 601, do nothing */
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         li      r5,L1_CACHE_BYTES-1
@@ -448,6 +448,7 @@ _GLOBAL(invalidate_dcache_range)
  */
 _GLOBAL(__flush_dcache_icache)
 BEGIN_FTR_SECTION
+        PURGE_PREFETCHED_INS
         blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
@@ -489,6 +490,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
  */
 _GLOBAL(__flush_dcache_icache_phys)
 BEGIN_FTR_SECTION
+        PURGE_PREFETCHED_INS
         blr                                     /* for 601, do nothing */
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         mfmsr   r10
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 64bf8db12b15..3d0249599d52 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -67,6 +67,7 @@ PPC64_CACHES:
 
 _KPROBE(flush_icache_range)
 BEGIN_FTR_SECTION
+        PURGE_PREFETCHED_INS
         blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 /*
@@ -211,6 +212,11 @@ _GLOBAL(__flush_dcache_icache)
  * Different systems have different cache line sizes
  */
 
+BEGIN_FTR_SECTION
+        PURGE_PREFETCHED_INS
+        blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
+
 /* Flush the dcache */
         ld      r7,PPC64_CACHES@toc(r2)
         clrrdi  r3,r3,PAGE_SHIFT                    /* Page align */
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 0620eaaaad45..bf0aada02fe4 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -99,12 +99,28 @@ static inline void free_lppacas(void) { }
  * 3 persistent SLBs are registered here.  The buffer will be zero
  * initially, hence will all be invaild until we actually write them.
  */
-struct slb_shadow slb_shadow[] __cacheline_aligned = {
-        [0 ... (NR_CPUS-1)] = {
-                .persistent = cpu_to_be32(SLB_NUM_BOLTED),
-                .buffer_length = cpu_to_be32(sizeof(struct slb_shadow)),
-        },
-};
+static struct slb_shadow *slb_shadow;
+
+static void __init allocate_slb_shadows(int nr_cpus, int limit)
+{
+        int size = PAGE_ALIGN(sizeof(struct slb_shadow) * nr_cpus);
+        slb_shadow = __va(memblock_alloc_base(size, PAGE_SIZE, limit));
+        memset(slb_shadow, 0, size);
+}
+
+static struct slb_shadow * __init init_slb_shadow(int cpu)
+{
+        struct slb_shadow *s = &slb_shadow[cpu];
+
+        s->persistent = cpu_to_be32(SLB_NUM_BOLTED);
+        s->buffer_length = cpu_to_be32(sizeof(*s));
+
+        return s;
+}
+
+#else /* CONFIG_PPC_STD_MMU_64 */
+
+static void __init allocate_slb_shadows(int nr_cpus, int limit) { }
 
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
@@ -142,8 +158,13 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
         new_paca->__current = &init_task;
         new_paca->data_offset = 0xfeeeeeeeeeeeeeeeULL;
 #ifdef CONFIG_PPC_STD_MMU_64
-        new_paca->slb_shadow_ptr = &slb_shadow[cpu];
+        new_paca->slb_shadow_ptr = init_slb_shadow(cpu);
 #endif /* CONFIG_PPC_STD_MMU_64 */
+
+#ifdef CONFIG_PPC_BOOK3E
+        /* For now -- if we have threads this will be adjusted later */
+        new_paca->tcd_ptr = &new_paca->tcd;
+#endif
 }
 
 /* Put the paca pointer into r13 and SPRG_PACA */
@@ -190,6 +211,8 @@ void __init allocate_pacas(void)
 
         allocate_lppacas(nr_cpu_ids, limit);
 
+        allocate_slb_shadows(nr_cpu_ids, limit);
+
         /* Can't use for_each_*_cpu, as they aren't functional yet */
         for (cpu = 0; cpu < nr_cpu_ids; cpu++)
                 initialise_paca(&paca[cpu], cpu);
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index a1e3e40ca3fd..d9476c1fc959 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -835,7 +835,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
                  * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
                  * since in that case, we don't want to re-assign anything
                  */
-                pcibios_resource_to_bus(dev, &reg, res);
+                pcibios_resource_to_bus(dev->bus, &reg, res);
                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
                     (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
                         /* Only print message if not re-assigning */
@@ -886,7 +886,7 @@ static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
 
         /* Job is a bit different between memory and IO */
         if (res->flags & IORESOURCE_MEM) {
-                pcibios_resource_to_bus(dev, &region, res);
+                pcibios_resource_to_bus(dev->bus, &region, res);
 
                 /* If the BAR is non-0 then it's probably been initialized */
                 if (region.start != 0)
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index ac0b034f9ae0..83c26d829991 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -111,7 +111,7 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
                 res->name = pci_name(dev);
                 region.start = base;
                 region.end = base + size - 1;
-                pcibios_bus_to_resource(dev, res, &region);
+                pcibios_bus_to_resource(dev->bus, res, &region);
         }
 }
 
@@ -280,7 +280,7 @@ void of_scan_pci_bridge(struct pci_dev *dev)
                 res->flags = flags;
                 region.start = of_read_number(&ranges[1], 2);
                 region.end = region.start + size - 1;
-                pcibios_bus_to_resource(dev, res, &region);
+                pcibios_bus_to_resource(dev->bus, res, &region);
         }
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
                 bus->number);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 4a96556fd2d4..8d4c247f1738 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -25,7 +25,6 @@
 #include <linux/slab.h>
 #include <linux/user.h>
 #include <linux/elf.h>
-#include <linux/init.h>
 #include <linux/prctl.h>
 #include <linux/init_task.h>
 #include <linux/export.h>
@@ -74,6 +73,48 @@ struct task_struct *last_task_used_vsx = NULL;
 struct task_struct *last_task_used_spe = NULL;
 #endif
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+void giveup_fpu_maybe_transactional(struct task_struct *tsk)
+{
+        /*
+         * If we are saving the current thread's registers, and the
+         * thread is in a transactional state, set the TIF_RESTORE_TM
+         * bit so that we know to restore the registers before
+         * returning to userspace.
+         */
+        if (tsk == current && tsk->thread.regs &&
+            MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
+            !test_thread_flag(TIF_RESTORE_TM)) {
+                tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
+                set_thread_flag(TIF_RESTORE_TM);
+        }
+
+        giveup_fpu(tsk);
+}
+
+void giveup_altivec_maybe_transactional(struct task_struct *tsk)
+{
+        /*
+         * If we are saving the current thread's registers, and the
+         * thread is in a transactional state, set the TIF_RESTORE_TM
+         * bit so that we know to restore the registers before
+         * returning to userspace.
+         */
+        if (tsk == current && tsk->thread.regs &&
+            MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
+            !test_thread_flag(TIF_RESTORE_TM)) {
+                tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
+                set_thread_flag(TIF_RESTORE_TM);
+        }
+
+        giveup_altivec(tsk);
+}
+
+#else
+#define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
+#define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
+#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+
 #ifdef CONFIG_PPC_FPU
 /*
  * Make sure the floating-point register state in the
@@ -102,13 +143,13 @@ void flush_fp_to_thread(struct task_struct *tsk)
                          */
                         BUG_ON(tsk != current);
 #endif
-                        giveup_fpu(tsk);
+                        giveup_fpu_maybe_transactional(tsk);
                 }
                 preempt_enable();
         }
 }
 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
-#endif
+#endif /* CONFIG_PPC_FPU */
 
 void enable_kernel_fp(void)
 {
@@ -116,11 +157,11 @@ void enable_kernel_fp(void)
 
 #ifdef CONFIG_SMP
         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
-                giveup_fpu(current);
+                giveup_fpu_maybe_transactional(current);
         else
                 giveup_fpu(NULL);       /* just enables FP for kernel */
 #else
-        giveup_fpu(last_task_used_math);
+        giveup_fpu_maybe_transactional(last_task_used_math);
 #endif /* CONFIG_SMP */
 }
 EXPORT_SYMBOL(enable_kernel_fp);
@@ -132,11 +173,11 @@ void enable_kernel_altivec(void)
 
 #ifdef CONFIG_SMP
         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
-                giveup_altivec(current);
+                giveup_altivec_maybe_transactional(current);
         else
                 giveup_altivec_notask();
 #else
-        giveup_altivec(last_task_used_altivec);
+        giveup_altivec_maybe_transactional(last_task_used_altivec);
 #endif /* CONFIG_SMP */
 }
 EXPORT_SYMBOL(enable_kernel_altivec);
@@ -153,7 +194,7 @@ void flush_altivec_to_thread(struct task_struct *tsk)
 #ifdef CONFIG_SMP
                         BUG_ON(tsk != current);
 #endif
-                        giveup_altivec(tsk);
+                        giveup_altivec_maybe_transactional(tsk);
                 }
                 preempt_enable();
         }
@@ -182,8 +223,8 @@ EXPORT_SYMBOL(enable_kernel_vsx);
 
 void giveup_vsx(struct task_struct *tsk)
 {
-        giveup_fpu(tsk);
-        giveup_altivec(tsk);
+        giveup_fpu_maybe_transactional(tsk);
+        giveup_altivec_maybe_transactional(tsk);
         __giveup_vsx(tsk);
 }
 
@@ -479,7 +520,48 @@ static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
                 return false;
         return true;
 }
+
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+static void tm_reclaim_thread(struct thread_struct *thr,
+                              struct thread_info *ti, uint8_t cause)
+{
+        unsigned long msr_diff = 0;
+
+        /*
+         * If FP/VSX registers have been already saved to the
+         * thread_struct, move them to the transact_fp array.
+         * We clear the TIF_RESTORE_TM bit since after the reclaim
+         * the thread will no longer be transactional.
+         */
+        if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
+                msr_diff = thr->tm_orig_msr & ~thr->regs->msr;
+                if (msr_diff & MSR_FP)
+                        memcpy(&thr->transact_fp, &thr->fp_state,
+                               sizeof(struct thread_fp_state));
+                if (msr_diff & MSR_VEC)
+                        memcpy(&thr->transact_vr, &thr->vr_state,
+                               sizeof(struct thread_vr_state));
+                clear_ti_thread_flag(ti, TIF_RESTORE_TM);
+                msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
+        }
+
+        tm_reclaim(thr, thr->regs->msr, cause);
+
+        /* Having done the reclaim, we now have the checkpointed
+         * FP/VSX values in the registers.  These might be valid
+         * even if we have previously called enable_kernel_fp() or
+         * flush_fp_to_thread(), so update thr->regs->msr to
+         * indicate their current validity.
+         */
+        thr->regs->msr |= msr_diff;
+}
+
+void tm_reclaim_current(uint8_t cause)
+{
+        tm_enable();
+        tm_reclaim_thread(&current->thread, current_thread_info(), cause);
+}
+
 static inline void tm_reclaim_task(struct task_struct *tsk)
 {
         /* We have to work out if we're switching from/to a task that's in the
@@ -502,9 +584,11 @@ static inline void tm_reclaim_task(struct task_struct *tsk)
 
         /* Stash the original thread MSR, as giveup_fpu et al will
          * modify it.  We hold onto it to see whether the task used
-         * FP & vector regs.
+         * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
+         * tm_orig_msr is already set.
          */
-        thr->tm_orig_msr = thr->regs->msr;
+        if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
+                thr->tm_orig_msr = thr->regs->msr;
 
         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
                  "ccr=%lx, msr=%lx, trap=%lx)\n",
@@ -512,7 +596,7 @@ static inline void tm_reclaim_task(struct task_struct *tsk)
                  thr->regs->ccr, thr->regs->msr,
                  thr->regs->trap);
 
-        tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
+        tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 
         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
                  tsk->pid);
@@ -588,6 +672,43 @@ static inline void __switch_to_tm(struct task_struct *prev)
                 tm_reclaim_task(prev);
         }
 }
+
+/*
+ * This is called if we are on the way out to userspace and the
+ * TIF_RESTORE_TM flag is set.  It checks if we need to reload
+ * FP and/or vector state and does so if necessary.
+ * If userspace is inside a transaction (whether active or
+ * suspended) and FP/VMX/VSX instructions have ever been enabled
+ * inside that transaction, then we have to keep them enabled
+ * and keep the FP/VMX/VSX state loaded while ever the transaction
+ * continues.  The reason is that if we didn't, and subsequently
+ * got a FP/VMX/VSX unavailable interrupt inside a transaction,
+ * we don't know whether it's the same transaction, and thus we
+ * don't know which of the checkpointed state and the transactional
+ * state to use.
+ */
+void restore_tm_state(struct pt_regs *regs)
+{
+        unsigned long msr_diff;
+
+        clear_thread_flag(TIF_RESTORE_TM);
+        if (!MSR_TM_ACTIVE(regs->msr))
+                return;
+
+        msr_diff = current->thread.tm_orig_msr & ~regs->msr;
+        msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
+        if (msr_diff & MSR_FP) {
+                fp_enable();
+                load_fp_state(&current->thread.fp_state);
+                regs->msr |= current->thread.fpexc_mode;
+        }
+        if (msr_diff & MSR_VEC) {
+                vec_enable();
+                load_vr_state(&current->thread.vr_state);
+        }
+        regs->msr |= msr_diff;
+}
+
 #else
 #define tm_recheckpoint_new_task(new)
 #define __switch_to_tm(prev)
@@ -690,7 +811,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
  * schedule DABR
  */
 #ifndef CONFIG_HAVE_HW_BREAKPOINT
-        if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
+        if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
                 set_breakpoint(&new->thread.hw_brk);
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
@@ -1175,6 +1296,19 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
         if (val & PR_FP_EXC_SW_ENABLE) {
 #ifdef CONFIG_SPE
                 if (cpu_has_feature(CPU_FTR_SPE)) {
+                        /*
+                         * When the sticky exception bits are set
+                         * directly by userspace, it must call prctl
+                         * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
+                         * in the existing prctl settings) or
+                         * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
+                         * the bits being set).  <fenv.h> functions
+                         * saving and restoring the whole
+                         * floating-point environment need to do so
+                         * anyway to restore the prctl settings from
+                         * the saved environment.
+                         */
+                        tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
                         tsk->thread.fpexc_mode = val &
                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
                         return 0;
@@ -1206,9 +1340,22 @@ int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
 
         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
 #ifdef CONFIG_SPE
-                if (cpu_has_feature(CPU_FTR_SPE))
+                if (cpu_has_feature(CPU_FTR_SPE)) {
+                        /*
+                         * When the sticky exception bits are set
+                         * directly by userspace, it must call prctl
+                         * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
+                         * in the existing prctl settings) or
+                         * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
+                         * the bits being set).  <fenv.h> functions
+                         * saving and restoring the whole
+                         * floating-point environment need to do so
+                         * anyway to restore the prctl settings from
+                         * the saved environment.
+                         */
+                        tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
                         val = tsk->thread.fpexc_mode;
-                else
+                } else
                         return -EINVAL;
 #else
                 return -EINVAL;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index fa0ad8aafbcc..f58c0d3aaeb4 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -523,6 +523,20 @@ static int __init early_init_dt_scan_memory_ppc(unsigned long node,
         return early_init_dt_scan_memory(node, uname, depth, data);
 }
 
+/*
+ * For a relocatable kernel, we need to get the memstart_addr first,
+ * then use it to calculate the virtual kernel start address. This has
+ * to happen at a very early stage (before machine_init). In this case,
+ * we just want to get the memstart_address and would not like to mess the
+ * memblock at this stage. So introduce a variable to skip the memblock_add()
+ * for this reason.
+ */
+#ifdef CONFIG_RELOCATABLE
+static int add_mem_to_memblock = 1;
+#else
+#define add_mem_to_memblock 1
+#endif
+
 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 {
 #ifdef CONFIG_PPC64
@@ -543,7 +557,8 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
         }
 
         /* Add the chunk to the MEMBLOCK list */
-        memblock_add(base, size);
+        if (add_mem_to_memblock)
+                memblock_add(base, size);
 }
 
 static void __init early_reserve_mem_dt(void)
@@ -740,6 +755,30 @@ void __init early_init_devtree(void *params)
         DBG(" <- early_init_devtree()\n");
 }
 
+#ifdef CONFIG_RELOCATABLE
+/*
+ * This function run before early_init_devtree, so we have to init
+ * initial_boot_params.
+ */
+void __init early_get_first_memblock_info(void *params, phys_addr_t *size)
+{
+        /* Setup flat device-tree pointer */
+        initial_boot_params = params;
+
+        /*
+         * Scan the memory nodes and set add_mem_to_memblock to 0 to avoid
+         * mess the memblock.
+         */
+        add_mem_to_memblock = 0;
+        of_scan_flat_dt(early_init_dt_scan_root, NULL);
+        of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL);
+        add_mem_to_memblock = 1;
+
+        if (size)
+                *size = first_memblock_size;
+}
+#endif
+
 /*******
  *
  * New implementation of the OF "find" APIs, return a refcounted
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 856dd4e99bfe..f5f11a7d30e5 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -97,6 +97,36 @@ int dcache_bsize;
 int icache_bsize;
 int ucache_bsize;
 
+#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
+static void setup_tlb_core_data(void)
+{
+        int cpu;
+
+        for_each_possible_cpu(cpu) {
+                int first = cpu_first_thread_sibling(cpu);
+
+                paca[cpu].tcd_ptr = &paca[first].tcd;
+
+                /*
+                 * If we have threads, we need either tlbsrx.
+                 * or e6500 tablewalk mode, or else TLB handlers
+                 * will be racy and could produce duplicate entries.
+                 */
+                if (smt_enabled_at_boot >= 2 &&
+                    !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
+                    book3e_htw_mode != PPC_HTW_E6500) {
+                        /* Should we panic instead? */
+                        WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
+                                  __func__);
+                }
+        }
+}
+#else
+static void setup_tlb_core_data(void)
+{
+}
+#endif
+
 #ifdef CONFIG_SMP
 
 static char *smt_enabled_cmdline;
@@ -445,6 +475,7 @@ void __init setup_system(void)
 
         smp_setup_cpu_maps();
         check_smt_enabled();
+        setup_tlb_core_data();
 
 #ifdef CONFIG_SMP
         /* Release secondary cpus out of their spinloops at 0x60 now that
@@ -520,9 +551,6 @@ static void __init irqstack_early_init(void)
 #ifdef CONFIG_PPC_BOOK3E
 static void __init exc_lvl_early_init(void)
 {
-        extern unsigned int interrupt_base_book3e;
-        extern unsigned int exc_debug_debug_book3e;
-
         unsigned int i;
 
         for_each_possible_cpu(i) {
@@ -535,8 +563,7 @@ static void __init exc_lvl_early_init(void)
         }
 
         if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
-                patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
-                             (unsigned long)&exc_debug_debug_book3e, 0);
+                patch_exception(0x040, exc_debug_debug_book3e);
 }
 #else
 #define exc_lvl_early_init()
@@ -544,7 +571,8 @@ static void __init exc_lvl_early_init(void)
 
 /*
  * Stack space used when we detect a bad kernel stack pointer, and
- * early in SMP boots before relocation is enabled.
+ * early in SMP boots before relocation is enabled. Exclusive emergency
+ * stack for machine checks.
  */
 static void __init emergency_stack_init(void)
 {
@@ -567,6 +595,13 @@ static void __init emergency_stack_init(void)
                 sp  = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
                 sp += THREAD_SIZE;
                 paca[i].emergency_sp = __va(sp);
+
+#ifdef CONFIG_PPC_BOOK3S_64
+                /* emergency stack for machine check exception handling. */
+                sp  = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
+                sp += THREAD_SIZE;
+                paca[i].mc_emergency_sp = __va(sp);
+#endif
         }
 }
 
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 457e97aa2945..8fc4177ed65a 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -203,8 +203,7 @@ unsigned long get_tm_stackpointer(struct pt_regs *regs)
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         if (MSR_TM_ACTIVE(regs->msr)) {
-                tm_enable();
-                tm_reclaim(&current->thread, regs->msr, TM_CAUSE_SIGNAL);
+                tm_reclaim_current(TM_CAUSE_SIGNAL);
                 if (MSR_TM_TRANSACTIONAL(regs->msr))
                         return current->thread.ckpt_regs.gpr[1];
         }
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 68027bfa5f8e..a67e00aa3caa 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -519,6 +519,13 @@ static int save_tm_user_regs(struct pt_regs *regs,
 {
         unsigned long msr = regs->msr;
 
+        /* Remove TM bits from thread's MSR.  The MSR in the sigcontext
+         * just indicates to userland that we were doing a transaction, but we
+         * don't want to return in transactional state.  This also ensures
+         * that flush_fp_to_thread won't set TIF_RESTORE_TM again.
+         */
+        regs->msr &= ~MSR_TS_MASK;
+
         /* Make sure floating point registers are stored in regs */
         flush_fp_to_thread(current);
 
@@ -1015,29 +1022,24 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         tm_frame = &rt_sf->uc_transact.uc_mcontext;
         if (MSR_TM_ACTIVE(regs->msr)) {
+                if (__put_user((unsigned long)&rt_sf->uc_transact,
+                               &rt_sf->uc.uc_link) ||
+                    __put_user((unsigned long)tm_frame,
+                               &rt_sf->uc_transact.uc_regs))
+                        goto badframe;
                 if (save_tm_user_regs(regs, frame, tm_frame, sigret))
                         goto badframe;
         }
         else
 #endif
         {
+                if (__put_user(0, &rt_sf->uc.uc_link))
+                        goto badframe;
                 if (save_user_regs(regs, frame, tm_frame, sigret, 1))
                         goto badframe;
         }
         regs->link = tramp;
 
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        if (MSR_TM_ACTIVE(regs->msr)) {
-                if (__put_user((unsigned long)&rt_sf->uc_transact,
-                               &rt_sf->uc.uc_link)
-                    || __put_user((unsigned long)tm_frame, &rt_sf->uc_transact.uc_regs))
-                        goto badframe;
-        }
-        else
-#endif
-                if (__put_user(0, &rt_sf->uc.uc_link))
-                        goto badframe;
-
         current->thread.fp_state.fpscr = 0;     /* turn off all fp exceptions */
 
         /* create a stack frame for the caller of the handler */
@@ -1056,13 +1058,6 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
         /* enter the signal handler in native-endian mode */
         regs->msr &= ~MSR_LE;
         regs->msr |= (MSR_KERNEL & MSR_LE);
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        /* Remove TM bits from thread's MSR.  The MSR in the sigcontext
-         * just indicates to userland that we were doing a transaction, but we
-         * don't want to return in transactional state:
-         */
-        regs->msr &= ~MSR_TS_MASK;
-#endif
         return 1;
 
 badframe:
@@ -1484,13 +1479,6 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         regs->nip = (unsigned long) ka->sa.sa_handler;
         /* enter the signal handler in big-endian mode */
         regs->msr &= ~MSR_LE;
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        /* Remove TM bits from thread's MSR.  The MSR in the sigcontext
-         * just indicates to userland that we were doing a transaction, but we
-         * don't want to return in transactional state:
-         */
-        regs->msr &= ~MSR_TS_MASK;
-#endif
         return 1;
 
 badframe:
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 42991045349f..e35bf773df7a 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -192,6 +192,13 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc,
 
         BUG_ON(!MSR_TM_ACTIVE(regs->msr));
 
+        /* Remove TM bits from thread's MSR.  The MSR in the sigcontext
+         * just indicates to userland that we were doing a transaction, but we
+         * don't want to return in transactional state.  This also ensures
+         * that flush_fp_to_thread won't set TIF_RESTORE_TM again.
+         */
+        regs->msr &= ~MSR_TS_MASK;
+
         flush_fp_to_thread(current);
 
 #ifdef CONFIG_ALTIVEC
@@ -749,13 +756,6 @@ int handle_rt_signal64(int signr, struct k_sigaction *ka, siginfo_t *info,
 
         /* Make sure signal handler doesn't get spurious FP exceptions */
         current->thread.fp_state.fpscr = 0;
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        /* Remove TM bits from thread's MSR.  The MSR in the sigcontext
-         * just indicates to userland that we were doing a transaction, but we
-         * don't want to return in transactional state:
-         */
-        regs->msr &= ~MSR_TS_MASK;
-#endif
 
         /* Set up to return from userspace. */
         if (vdso64_rt_sigtramp && current->mm->context.vdso_base) {
diff --git a/arch/powerpc/kernel/smp-tbsync.c b/arch/powerpc/kernel/smp-tbsync.c
index e68fd1ae727a..7a37ecd3afa3 100644
--- a/arch/powerpc/kernel/smp-tbsync.c
+++ b/arch/powerpc/kernel/smp-tbsync.c
@@ -9,7 +9,6 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/unistd.h>
-#include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/atomic.h>
 #include <asm/smp.h>
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index c1cf4a1522d9..ac2621af3154 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -369,13 +369,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
         cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
 
-        if (smp_ops)
-                if (smp_ops->probe)
-                        max_cpus = smp_ops->probe();
-                else
-                        max_cpus = NR_CPUS;
-        else
-                max_cpus = 1;
+        if (smp_ops && smp_ops->probe)
+                smp_ops->probe();
 }
 
 void smp_prepare_boot_cpu(void)
diff --git a/arch/powerpc/kernel/swsusp_booke.S b/arch/powerpc/kernel/swsusp_booke.S
index 0f204053e5b5..553c1405ee05 100644
--- a/arch/powerpc/kernel/swsusp_booke.S
+++ b/arch/powerpc/kernel/swsusp_booke.S
@@ -74,21 +74,21 @@ _GLOBAL(swsusp_arch_suspend)
         bne     1b
 
         /* Save SPRGs */
-        mfsprg  r4,0
+        mfspr   r4,SPRN_SPRG0
         stw     r4,SL_SPRG0(r11)
-        mfsprg  r4,1
+        mfspr   r4,SPRN_SPRG1
         stw     r4,SL_SPRG1(r11)
-        mfsprg  r4,2
+        mfspr   r4,SPRN_SPRG2
         stw     r4,SL_SPRG2(r11)
-        mfsprg  r4,3
+        mfspr   r4,SPRN_SPRG3
         stw     r4,SL_SPRG3(r11)
-        mfsprg  r4,4
+        mfspr   r4,SPRN_SPRG4
         stw     r4,SL_SPRG4(r11)
-        mfsprg  r4,5
+        mfspr   r4,SPRN_SPRG5
         stw     r4,SL_SPRG5(r11)
-        mfsprg  r4,6
+        mfspr   r4,SPRN_SPRG6
         stw     r4,SL_SPRG6(r11)
-        mfsprg  r4,7
+        mfspr   r4,SPRN_SPRG7
         stw     r4,SL_SPRG7(r11)
 
         /* Call the low level suspend stuff (we should probably have made
@@ -150,21 +150,21 @@ _GLOBAL(swsusp_arch_resume)
         bl      _tlbil_all
 
         lwz     r4,SL_SPRG0(r11)
-        mtsprg  0,r4
+        mtspr   SPRN_SPRG0,r4
         lwz     r4,SL_SPRG1(r11)
-        mtsprg  1,r4
+        mtspr   SPRN_SPRG1,r4
         lwz     r4,SL_SPRG2(r11)
-        mtsprg  2,r4
+        mtspr   SPRN_SPRG2,r4
         lwz     r4,SL_SPRG3(r11)
-        mtsprg  3,r4
+        mtspr   SPRN_SPRG3,r4
         lwz     r4,SL_SPRG4(r11)
-        mtsprg  4,r4
+        mtspr   SPRN_SPRG4,r4
         lwz     r4,SL_SPRG5(r11)
-        mtsprg  5,r4
+        mtspr   SPRN_SPRG5,r4
         lwz     r4,SL_SPRG6(r11)
-        mtsprg  6,r4
+        mtspr   SPRN_SPRG6,r4
         lwz     r4,SL_SPRG7(r11)
-        mtsprg  7,r4
+        mtspr   SPRN_SPRG7,r4
 
         /* restore the MSR */
         lwz     r3,SL_MSR(r11)
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index 4e3cc47f26b9..cd9be9aa016d 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -34,7 +34,6 @@
 #include <linux/ipc.h>
 #include <linux/utsname.h>
 #include <linux/file.h>
-#include <linux/init.h>
 #include <linux/personality.h>
 
 #include <asm/uaccess.h>
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index b4e667663d9b..97e1dc917683 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -51,8 +51,6 @@ static ssize_t store_smt_snooze_delay(struct device *dev,
                 return -EINVAL;
 
         per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
-        update_smt_snooze_delay(cpu->dev.id, snooze);
-
         return count;
 }
 
@@ -86,6 +84,304 @@ __setup("smt-snooze-delay=", setup_smt_snooze_delay);
 
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_PPC_FSL_BOOK3E
+#define MAX_BIT                         63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+        u64 cycle;
+
+        if (ns >= 10000)
+                cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
+        else
+                cycle = div_u64(ns * tb_ticks_per_usec, 1000);
+
+        if (!cycle)
+                return 0;
+
+        return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+        u32 *value = val;
+
+        *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+        u32 value;
+        unsigned int cpu = dev->id;
+
+        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+        value &= PWRMGTCR0_PW20_WAIT;
+
+        return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+        u32 *value = val;
+        u32 pw20_state;
+
+        pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+        if (*value)
+                pw20_state |= PWRMGTCR0_PW20_WAIT;
+        else
+                pw20_state &= ~PWRMGTCR0_PW20_WAIT;
+
+        mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+        u32 value;
+        unsigned int cpu = dev->id;
+
+        if (kstrtou32(buf, 0, &value))
+                return -EINVAL;
+
+        if (value > 1)
+                return -EINVAL;
+
+        smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
+
+        return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+        u32 value;
+        u64 tb_cycle = 1;
+        u64 time;
+
+        unsigned int cpu = dev->id;
+
+        if (!pw20_wt) {
+                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+                value = (value & PWRMGTCR0_PW20_ENT) >>
+                                        PWRMGTCR0_PW20_ENT_SHIFT;
+
+                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
+                /* convert ms to ns */
+                if (tb_ticks_per_usec > 1000) {
+                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
+                } else {
+                        u32 rem_us;
+
+                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
+                                                &rem_us);
+                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
+                }
+        } else {
+                time = pw20_wt;
+        }
+
+        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+        u32 *value = val;
+        u32 pw20_idle;
+
+        pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+        /* Set Automatic PW20 Core Idle Count */
+        /* clear count */
+        pw20_idle &= ~PWRMGTCR0_PW20_ENT;
+
+        /* set count */
+        pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
+
+        mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+        u32 entry_bit;
+        u64 value;
+
+        unsigned int cpu = dev->id;
+
+        if (kstrtou64(buf, 0, &value))
+                return -EINVAL;
+
+        if (!value)
+                return -EINVAL;
+
+        entry_bit = get_idle_ticks_bit(value);
+        if (entry_bit > MAX_BIT)
+                return -EINVAL;
+
+        pw20_wt = value;
+
+        smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+                                &entry_bit, 1);
+
+        return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+        u32 value;
+        unsigned int cpu = dev->id;
+
+        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+        value &= PWRMGTCR0_AV_IDLE_PD_EN;
+
+        return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+        u32 *value = val;
+        u32 altivec_idle;
+
+        altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+        if (*value)
+                altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
+        else
+                altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
+
+        mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+        u32 value;
+        unsigned int cpu = dev->id;
+
+        if (kstrtou32(buf, 0, &value))
+                return -EINVAL;
+
+        if (value > 1)
+                return -EINVAL;
+
+        smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
+
+        return count;
+}
+
+static ssize_t show_altivec_idle_wait_time(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+        u32 value;
+        u64 tb_cycle = 1;
+        u64 time;
+
+        unsigned int cpu = dev->id;
+
+        if (!altivec_idle_wt) {
+                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+                value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
+                                        PWRMGTCR0_AV_IDLE_CNT_SHIFT;
+
+                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
+                /* convert ms to ns */
+                if (tb_ticks_per_usec > 1000) {
+                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
+                } else {
+                        u32 rem_us;
+
+                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
+                                                &rem_us);
+                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
+                }
+        } else {
+                time = altivec_idle_wt;
+        }
+
+        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
+}
+
+static void set_altivec_idle_wait_entry_bit(void *val)
+{
+        u32 *value = val;
+        u32 altivec_idle;
+
+        altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+        /* Set Automatic AltiVec Idle Count */
+        /* clear count */
+        altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
+
+        /* set count */
+        altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
+
+        mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle_wait_time(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t count)
+{
+        u32 entry_bit;
+        u64 value;
+
+        unsigned int cpu = dev->id;
+
+        if (kstrtou64(buf, 0, &value))
+                return -EINVAL;
+
+        if (!value)
+                return -EINVAL;
+
+        entry_bit = get_idle_ticks_bit(value);
+        if (entry_bit > MAX_BIT)
+                return -EINVAL;
+
+        altivec_idle_wt = value;
+
+        smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
+                                &entry_bit, 1);
+
+        return count;
+}
+
+/*
+ * Enable/Disable interface:
+ * 0, disable. 1, enable.
+ */
+static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
+static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
+
+/*
+ * Set wait time interface:(Nanosecond)
+ * Example: Base on TBfreq is 41MHZ.
+ * 1~48(ns): TB[63]
+ * 49~97(ns): TB[62]
+ * 98~195(ns): TB[61]
+ * 196~390(ns): TB[60]
+ * 391~780(ns): TB[59]
+ * 781~1560(ns): TB[58]
+ * ...
+ */
+static DEVICE_ATTR(pw20_wait_time, 0600,
+                        show_pw20_wait_time,
+                        store_pw20_wait_time);
+static DEVICE_ATTR(altivec_idle_wait_time, 0600,
+                        show_altivec_idle_wait_time,
+                        store_altivec_idle_wait_time);
+#endif
+
 /*
  * Enabling PMCs will slow partition context switch times so we only do
  * it the first time we write to the PMCs.
@@ -108,14 +404,14 @@ void ppc_enable_pmcs(void)
 }
 EXPORT_SYMBOL(ppc_enable_pmcs);
 
-#define SYSFS_PMCSETUP(NAME, ADDRESS) \
+#define __SYSFS_SPRSETUP(NAME, ADDRESS, EXTRA) \
 static void read_##NAME(void *val) \
 { \
         *(unsigned long *)val = mfspr(ADDRESS); \
 } \
 static void write_##NAME(void *val) \
 { \
-        ppc_enable_pmcs(); \
+        EXTRA; \
         mtspr(ADDRESS, *(unsigned long *)val);  \
 } \
 static ssize_t show_##NAME(struct device *dev, \
@@ -140,6 +436,10 @@ static ssize_t __used \
         return count; \
 }
 
+#define SYSFS_PMCSETUP(NAME, ADDRESS)   \
+        __SYSFS_SPRSETUP(NAME, ADDRESS, ppc_enable_pmcs())
+#define SYSFS_SPRSETUP(NAME, ADDRESS)   \
+        __SYSFS_SPRSETUP(NAME, ADDRESS, )
 
 /* Let's define all possible registers, we'll only hook up the ones
  * that are implemented on the current processor
@@ -175,10 +475,10 @@ SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 
 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
-SYSFS_PMCSETUP(purr, SPRN_PURR);
-SYSFS_PMCSETUP(spurr, SPRN_SPURR);
-SYSFS_PMCSETUP(dscr, SPRN_DSCR);
-SYSFS_PMCSETUP(pir, SPRN_PIR);
+SYSFS_SPRSETUP(purr, SPRN_PURR);
+SYSFS_SPRSETUP(spurr, SPRN_SPURR);
+SYSFS_SPRSETUP(dscr, SPRN_DSCR);
+SYSFS_SPRSETUP(pir, SPRN_PIR);
 
 /*
   Lets only enable read for phyp resources and
@@ -249,34 +549,34 @@ SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 #ifdef CONFIG_DEBUG_KERNEL
-SYSFS_PMCSETUP(hid0, SPRN_HID0);
-SYSFS_PMCSETUP(hid1, SPRN_HID1);
-SYSFS_PMCSETUP(hid4, SPRN_HID4);
-SYSFS_PMCSETUP(hid5, SPRN_HID5);
-SYSFS_PMCSETUP(ima0, SPRN_PA6T_IMA0);
-SYSFS_PMCSETUP(ima1, SPRN_PA6T_IMA1);
-SYSFS_PMCSETUP(ima2, SPRN_PA6T_IMA2);
-SYSFS_PMCSETUP(ima3, SPRN_PA6T_IMA3);
-SYSFS_PMCSETUP(ima4, SPRN_PA6T_IMA4);
-SYSFS_PMCSETUP(ima5, SPRN_PA6T_IMA5);
-SYSFS_PMCSETUP(ima6, SPRN_PA6T_IMA6);
-SYSFS_PMCSETUP(ima7, SPRN_PA6T_IMA7);
-SYSFS_PMCSETUP(ima8, SPRN_PA6T_IMA8);
-SYSFS_PMCSETUP(ima9, SPRN_PA6T_IMA9);
-SYSFS_PMCSETUP(imaat, SPRN_PA6T_IMAAT);
-SYSFS_PMCSETUP(btcr, SPRN_PA6T_BTCR);
-SYSFS_PMCSETUP(pccr, SPRN_PA6T_PCCR);
-SYSFS_PMCSETUP(rpccr, SPRN_PA6T_RPCCR);
-SYSFS_PMCSETUP(der, SPRN_PA6T_DER);
-SYSFS_PMCSETUP(mer, SPRN_PA6T_MER);
-SYSFS_PMCSETUP(ber, SPRN_PA6T_BER);
-SYSFS_PMCSETUP(ier, SPRN_PA6T_IER);
-SYSFS_PMCSETUP(sier, SPRN_PA6T_SIER);
-SYSFS_PMCSETUP(siar, SPRN_PA6T_SIAR);
-SYSFS_PMCSETUP(tsr0, SPRN_PA6T_TSR0);
-SYSFS_PMCSETUP(tsr1, SPRN_PA6T_TSR1);
-SYSFS_PMCSETUP(tsr2, SPRN_PA6T_TSR2);
-SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3);
+SYSFS_SPRSETUP(hid0, SPRN_HID0);
+SYSFS_SPRSETUP(hid1, SPRN_HID1);
+SYSFS_SPRSETUP(hid4, SPRN_HID4);
+SYSFS_SPRSETUP(hid5, SPRN_HID5);
+SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
+SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
+SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
+SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
+SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
+SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
+SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
+SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
+SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
+SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
+SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
+SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
+SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
+SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
+SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
+SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
+SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
+SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
+SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
+SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
+SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
+SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
+SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
+SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 #endif /* CONFIG_DEBUG_KERNEL */
 #endif /* HAS_PPC_PMC_PA6T */
 
@@ -421,6 +721,15 @@ static void register_cpu_online(unsigned int cpu)
                 device_create_file(s, &dev_attr_pir);
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_PPC_FSL_BOOK3E
+        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+                device_create_file(s, &dev_attr_pw20_state);
+                device_create_file(s, &dev_attr_pw20_wait_time);
+
+                device_create_file(s, &dev_attr_altivec_idle);
+                device_create_file(s, &dev_attr_altivec_idle_wait_time);
+        }
+#endif
         cacheinfo_cpu_online(cpu);
 }
 
@@ -493,6 +802,15 @@ static void unregister_cpu_online(unsigned int cpu)
                 device_remove_file(s, &dev_attr_pir);
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_PPC_FSL_BOOK3E
+        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+                device_remove_file(s, &dev_attr_pw20_state);
+                device_remove_file(s, &dev_attr_pw20_wait_time);
+
+                device_remove_file(s, &dev_attr_altivec_idle);
+                device_remove_file(s, &dev_attr_altivec_idle_wait_time);
+        }
+#endif
         cacheinfo_cpu_offline(cpu);
 }
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index b3b144121cc9..b3dab20acf34 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -510,7 +510,6 @@ void timer_interrupt(struct pt_regs * regs)
          */
         may_hard_irq_enable();
 
-        __get_cpu_var(irq_stat).timer_irqs++;
 
 #if defined(CONFIG_PPC32) && defined(CONFIG_PMAC)
         if (atomic_read(&ppc_n_lost_interrupts) != 0)
@@ -532,10 +531,15 @@ void timer_interrupt(struct pt_regs * regs)
                 *next_tb = ~(u64)0;
                 if (evt->event_handler)
                         evt->event_handler(evt);
+                __get_cpu_var(irq_stat).timer_irqs_event++;
         } else {
                 now = *next_tb - now;
                 if (now <= DECREMENTER_MAX)
                         set_dec((int)now);
+                /* We may have raced with new irq work */
+                if (test_irq_work_pending())
+                        set_dec(1);
+                __get_cpu_var(irq_stat).timer_irqs_others++;
         }
 
 #ifdef CONFIG_PPC64
@@ -801,8 +805,16 @@ static void __init clocksource_init(void)
 static int decrementer_set_next_event(unsigned long evt,
                                       struct clock_event_device *dev)
 {
+        /* Don't adjust the decrementer if some irq work is pending */
+        if (test_irq_work_pending())
+                return 0;
         __get_cpu_var(decrementers_next_tb) = get_tb_or_rtc() + evt;
         set_dec(evt);
+
+        /* We may have raced with new irq work */
+        if (test_irq_work_pending())
+                set_dec(1);
+
         return 0;
 }
 
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 907a472f9a9e..33cd7a0b8e73 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -285,6 +285,21 @@ void system_reset_exception(struct pt_regs *regs)
 
         /* What should we do here? We could issue a shutdown or hard reset. */
 }
+
+/*
+ * This function is called in real mode. Strictly no printk's please.
+ *
+ * regs->nip and regs->msr contains srr0 and ssr1.
+ */
+long machine_check_early(struct pt_regs *regs)
+{
+        long handled = 0;
+
+        if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
+                handled = cur_cpu_spec->machine_check_early(regs);
+        return handled;
+}
+
 #endif
 
 /*
@@ -1384,7 +1399,6 @@ void fp_unavailable_tm(struct pt_regs *regs)
 
         TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
                  regs->nip, regs->msr);
-        tm_enable();
 
         /* We can only have got here if the task started using FP after
          * beginning the transaction.  So, the transactional regs are just a
@@ -1393,8 +1407,7 @@ void fp_unavailable_tm(struct pt_regs *regs)
          * transaction, and probably retry but now with FP enabled.  So the
          * checkpointed FP registers need to be loaded.
          */
-        tm_reclaim(&current->thread, current->thread.regs->msr,
-                   TM_CAUSE_FAC_UNAV);
+        tm_reclaim_current(TM_CAUSE_FAC_UNAV);
         /* Reclaim didn't save out any FPRs to transact_fprs. */
 
         /* Enable FP for the task: */
@@ -1403,11 +1416,19 @@ void fp_unavailable_tm(struct pt_regs *regs)
         /* This loads and recheckpoints the FP registers from
          * thread.fpr[].  They will remain in registers after the
          * checkpoint so we don't need to reload them after.
+         * If VMX is in use, the VRs now hold checkpointed values,
+         * so we don't want to load the VRs from the thread_struct.
          */
-        tm_recheckpoint(&current->thread, regs->msr);
+        tm_recheckpoint(&current->thread, MSR_FP);
+
+        /* If VMX is in use, get the transactional values back */
+        if (regs->msr & MSR_VEC) {
+                do_load_up_transact_altivec(&current->thread);
+                /* At this point all the VSX state is loaded, so enable it */
+                regs->msr |= MSR_VSX;
+        }
 }
 
-#ifdef CONFIG_ALTIVEC
 void altivec_unavailable_tm(struct pt_regs *regs)
 {
         /* See the comments in fp_unavailable_tm().  This function operates
@@ -1417,18 +1438,21 @@ void altivec_unavailable_tm(struct pt_regs *regs)
         TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
                  "MSR=%lx\n",
                  regs->nip, regs->msr);
-        tm_enable();
-        tm_reclaim(&current->thread, current->thread.regs->msr,
-                   TM_CAUSE_FAC_UNAV);
+        tm_reclaim_current(TM_CAUSE_FAC_UNAV);
         regs->msr |= MSR_VEC;
-        tm_recheckpoint(&current->thread, regs->msr);
+        tm_recheckpoint(&current->thread, MSR_VEC);
         current->thread.used_vr = 1;
+
+        if (regs->msr & MSR_FP) {
+                do_load_up_transact_fpu(&current->thread);
+                regs->msr |= MSR_VSX;
+        }
 }
-#endif
 
-#ifdef CONFIG_VSX
 void vsx_unavailable_tm(struct pt_regs *regs)
 {
+        unsigned long orig_msr = regs->msr;
+
         /* See the comments in fp_unavailable_tm().  This works similarly,
          * though we're loading both FP and VEC registers in here.
          *
@@ -1440,18 +1464,30 @@ void vsx_unavailable_tm(struct pt_regs *regs)
                  "MSR=%lx\n",
                  regs->nip, regs->msr);
 
-        tm_enable();
+        current->thread.used_vsr = 1;
+
+        /* If FP and VMX are already loaded, we have all the state we need */
+        if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
+                regs->msr |= MSR_VSX;
+                return;
+        }
+
         /* This reclaims FP and/or VR regs if they're already enabled */
-        tm_reclaim(&current->thread, current->thread.regs->msr,
-                   TM_CAUSE_FAC_UNAV);
+        tm_reclaim_current(TM_CAUSE_FAC_UNAV);
 
         regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
                 MSR_VSX;
-        /* This loads & recheckpoints FP and VRs. */
-        tm_recheckpoint(&current->thread, regs->msr);
-        current->thread.used_vsr = 1;
+
+        /* This loads & recheckpoints FP and VRs; but we have
+         * to be sure not to overwrite previously-valid state.
+         */
+        tm_recheckpoint(&current->thread, regs->msr & ~orig_msr);
+
+        if (orig_msr & MSR_FP)
+                do_load_up_transact_fpu(&current->thread);
+        if (orig_msr & MSR_VEC)
+                do_load_up_transact_altivec(&current->thread);
 }
-#endif
 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 void performance_monitor_exception(struct pt_regs *regs)
diff --git a/arch/powerpc/kernel/vdso32/vdso32_wrapper.S b/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
index 6e8f507ed32b..79683d0393f5 100644
--- a/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
+++ b/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
@@ -1,4 +1,3 @@
-#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/page.h>
 
diff --git a/arch/powerpc/kernel/vdso64/vdso64_wrapper.S b/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
index b8553d62b792..8df9e2463007 100644
--- a/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
+++ b/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
@@ -1,4 +1,3 @@
-#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/page.h>
 
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 0458a9aaba9d..74f8050518d6 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -37,6 +37,16 @@ _GLOBAL(do_load_up_transact_altivec)
 #endif
 
 /*
+ * Enable use of VMX/Altivec for the caller.
+ */
+_GLOBAL(vec_enable)
+        mfmsr   r3
+        oris    r3,r3,MSR_VEC@h
+        MTMSRD(r3)
+        isync
+        blr
+
+/*
  * Load state from memory into VMX registers including VSCR.
  * Assumes the caller has enabled VMX in the MSR.
  */
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 76a64821f4a2..826d8bd9e522 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -518,16 +518,18 @@ static dma_addr_t vio_dma_iommu_map_page(struct device *dev, struct page *page,
                                          struct dma_attrs *attrs)
 {
         struct vio_dev *viodev = to_vio_dev(dev);
+        struct iommu_table *tbl;
         dma_addr_t ret = DMA_ERROR_CODE;
 
-        if (vio_cmo_alloc(viodev, roundup(size, IOMMU_PAGE_SIZE))) {
+        tbl = get_iommu_table_base(dev);
+        if (vio_cmo_alloc(viodev, roundup(size, IOMMU_PAGE_SIZE(tbl)))) {
                 atomic_inc(&viodev->cmo.allocs_failed);
                 return ret;
         }
 
         ret = dma_iommu_ops.map_page(dev, page, offset, size, direction, attrs);
         if (unlikely(dma_mapping_error(dev, ret))) {
-                vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE));
+                vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE(tbl)));
                 atomic_inc(&viodev->cmo.allocs_failed);
         }
 
@@ -540,10 +542,12 @@ static void vio_dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle,
                                      struct dma_attrs *attrs)
 {
         struct vio_dev *viodev = to_vio_dev(dev);
+        struct iommu_table *tbl;
 
+        tbl = get_iommu_table_base(dev);
         dma_iommu_ops.unmap_page(dev, dma_handle, size, direction, attrs);
 
-        vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE));
+        vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE(tbl)));
 }
 
 static int vio_dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
@@ -551,12 +555,14 @@ static int vio_dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
                                 struct dma_attrs *attrs)
 {
         struct vio_dev *viodev = to_vio_dev(dev);
+        struct iommu_table *tbl;
         struct scatterlist *sgl;
         int ret, count = 0;
         size_t alloc_size = 0;
 
+        tbl = get_iommu_table_base(dev);
         for (sgl = sglist; count < nelems; count++, sgl++)
-                alloc_size += roundup(sgl->length, IOMMU_PAGE_SIZE);
+                alloc_size += roundup(sgl->length, IOMMU_PAGE_SIZE(tbl));
 
         if (vio_cmo_alloc(viodev, alloc_size)) {
                 atomic_inc(&viodev->cmo.allocs_failed);
@@ -572,7 +578,7 @@ static int vio_dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
         }
 
         for (sgl = sglist, count = 0; count < ret; count++, sgl++)
-                alloc_size -= roundup(sgl->dma_length, IOMMU_PAGE_SIZE);
+                alloc_size -= roundup(sgl->dma_length, IOMMU_PAGE_SIZE(tbl));
         if (alloc_size)
                 vio_cmo_dealloc(viodev, alloc_size);
 
@@ -585,12 +591,14 @@ static void vio_dma_iommu_unmap_sg(struct device *dev,
                 struct dma_attrs *attrs)
 {
         struct vio_dev *viodev = to_vio_dev(dev);
+        struct iommu_table *tbl;
         struct scatterlist *sgl;
         size_t alloc_size = 0;
         int count = 0;
 
+        tbl = get_iommu_table_base(dev);
         for (sgl = sglist; count < nelems; count++, sgl++)
-                alloc_size += roundup(sgl->dma_length, IOMMU_PAGE_SIZE);
+                alloc_size += roundup(sgl->dma_length, IOMMU_PAGE_SIZE(tbl));
 
         dma_iommu_ops.unmap_sg(dev, sglist, nelems, direction, attrs);
 
@@ -706,11 +714,14 @@ static int vio_cmo_bus_probe(struct vio_dev *viodev)
 {
         struct vio_cmo_dev_entry *dev_ent;
         struct device *dev = &viodev->dev;
+        struct iommu_table *tbl;
         struct vio_driver *viodrv = to_vio_driver(dev->driver);
         unsigned long flags;
         size_t size;
         bool dma_capable = false;
 
+        tbl = get_iommu_table_base(dev);
+
         /* A device requires entitlement if it has a DMA window property */
         switch (viodev->family) {
         case VDEVICE:
@@ -736,7 +747,8 @@ static int vio_cmo_bus_probe(struct vio_dev *viodev)
                         return -EINVAL;
                 }
 
-                viodev->cmo.desired = IOMMU_PAGE_ALIGN(viodrv->get_desired_dma(viodev));
+                viodev->cmo.desired =
+                        IOMMU_PAGE_ALIGN(viodrv->get_desired_dma(viodev), tbl);
                 if (viodev->cmo.desired < VIO_CMO_MIN_ENT)
                         viodev->cmo.desired = VIO_CMO_MIN_ENT;
                 size = VIO_CMO_MIN_ENT;
@@ -1176,9 +1188,10 @@ static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev)
                             &tbl->it_index, &offset, &size);
 
         /* TCE table size - measured in tce entries */
-        tbl->it_size = size >> IOMMU_PAGE_SHIFT;
+        tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
+        tbl->it_size = size >> tbl->it_page_shift;
         /* offset for VIO should always be 0 */
-        tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
+        tbl->it_offset = offset >> tbl->it_page_shift;
         tbl->it_busno = 0;
         tbl->it_type = TCE_VB;
         tbl->it_blocksize = 16;
diff --git a/arch/powerpc/kvm/44x.c b/arch/powerpc/kvm/44x.c
index 93221e87b911..9cb4b0a36031 100644
--- a/arch/powerpc/kvm/44x.c
+++ b/arch/powerpc/kvm/44x.c
@@ -21,6 +21,8 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/export.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
 
 #include <asm/reg.h>
 #include <asm/cputable.h>
@@ -231,3 +233,5 @@ static void __exit kvmppc_44x_exit(void)
 
 module_init(kvmppc_44x_init);
 module_exit(kvmppc_44x_exit);
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 8912608b7e1b..94e597e6f15c 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -18,6 +18,8 @@
 #include <linux/err.h>
 #include <linux/export.h>
 #include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
 
 #include <asm/reg.h>
 #include <asm/cputable.h>
@@ -575,10 +577,10 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                         break;
                 case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
                         i = reg->id - KVM_REG_PPC_FPR0;
-                        val = get_reg_val(reg->id, vcpu->arch.fpr[i]);
+                        val = get_reg_val(reg->id, VCPU_FPR(vcpu, i));
                         break;
                 case KVM_REG_PPC_FPSCR:
-                        val = get_reg_val(reg->id, vcpu->arch.fpscr);
+                        val = get_reg_val(reg->id, vcpu->arch.fp.fpscr);
                         break;
 #ifdef CONFIG_ALTIVEC
                 case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
@@ -586,19 +588,30 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                                 r = -ENXIO;
                                 break;
                         }
-                        val.vval = vcpu->arch.vr[reg->id - KVM_REG_PPC_VR0];
+                        val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0];
                         break;
                 case KVM_REG_PPC_VSCR:
                         if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
                                 r = -ENXIO;
                                 break;
                         }
-                        val = get_reg_val(reg->id, vcpu->arch.vscr.u[3]);
+                        val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]);
                         break;
                 case KVM_REG_PPC_VRSAVE:
                         val = get_reg_val(reg->id, vcpu->arch.vrsave);
                         break;
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_VSX
+                case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
+                        if (cpu_has_feature(CPU_FTR_VSX)) {
+                                long int i = reg->id - KVM_REG_PPC_VSR0;
+                                val.vsxval[0] = vcpu->arch.fp.fpr[i][0];
+                                val.vsxval[1] = vcpu->arch.fp.fpr[i][1];
+                        } else {
+                                r = -ENXIO;
+                        }
+                        break;
+#endif /* CONFIG_VSX */
                 case KVM_REG_PPC_DEBUG_INST: {
                         u32 opcode = INS_TW;
                         r = copy_to_user((u32 __user *)(long)reg->addr,
@@ -654,10 +667,10 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                         break;
                 case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
                         i = reg->id - KVM_REG_PPC_FPR0;
-                        vcpu->arch.fpr[i] = set_reg_val(reg->id, val);
+                        VCPU_FPR(vcpu, i) = set_reg_val(reg->id, val);
                         break;
                 case KVM_REG_PPC_FPSCR:
-                        vcpu->arch.fpscr = set_reg_val(reg->id, val);
+                        vcpu->arch.fp.fpscr = set_reg_val(reg->id, val);
                         break;
 #ifdef CONFIG_ALTIVEC
                 case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
@@ -665,14 +678,14 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                                 r = -ENXIO;
                                 break;
                         }
-                        vcpu->arch.vr[reg->id - KVM_REG_PPC_VR0] = val.vval;
+                        vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval;
                         break;
                 case KVM_REG_PPC_VSCR:
                         if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
                                 r = -ENXIO;
                                 break;
                         }
-                        vcpu->arch.vscr.u[3] = set_reg_val(reg->id, val);
+                        vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val);
                         break;
                 case KVM_REG_PPC_VRSAVE:
                         if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
@@ -682,6 +695,17 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                         vcpu->arch.vrsave = set_reg_val(reg->id, val);
                         break;
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_VSX
+                case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
+                        if (cpu_has_feature(CPU_FTR_VSX)) {
+                                long int i = reg->id - KVM_REG_PPC_VSR0;
+                                vcpu->arch.fp.fpr[i][0] = val.vsxval[0];
+                                vcpu->arch.fp.fpr[i][1] = val.vsxval[1];
+                        } else {
+                                r = -ENXIO;
+                        }
+                        break;
+#endif /* CONFIG_VSX */
 #ifdef CONFIG_KVM_XICS
                 case KVM_REG_PPC_ICP_STATE:
                         if (!vcpu->arch.icp) {
@@ -879,3 +903,9 @@ static void kvmppc_book3s_exit(void)
 
 module_init(kvmppc_book3s_init);
 module_exit(kvmppc_book3s_exit);
+
+/* On 32bit this is our one and only kernel module */
+#ifdef CONFIG_KVM_BOOK3S_32
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
+#endif
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
index 3a0abd2e5a15..5fac89dfe4cd 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -243,6 +243,11 @@ next_pteg:
         /* Now tell our Shadow PTE code about the new page */
 
         pte = kvmppc_mmu_hpte_cache_next(vcpu);
+        if (!pte) {
+                kvm_release_pfn_clean(hpaddr >> PAGE_SHIFT);
+                r = -EAGAIN;
+                goto out;
+        }
 
         dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n",
                     orig_pte->may_write ? 'w' : '-',
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index c5d148434c08..303ece75b8e4 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -262,7 +262,7 @@ int kvmppc_mmu_hv_init(void)
 
 static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu)
 {
-        kvmppc_set_msr(vcpu, MSR_SF | MSR_ME);
+        kvmppc_set_msr(vcpu, vcpu->arch.intr_msr);
 }
 
 /*
@@ -562,7 +562,7 @@ static int kvmppc_hv_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu,
          * we just return and retry the instruction.
          */
 
-        if (instruction_is_store(vcpu->arch.last_inst) != !!is_store)
+        if (instruction_is_store(kvmppc_get_last_inst(vcpu)) != !!is_store)
                 return RESUME_GUEST;
 
         /*
diff --git a/arch/powerpc/kvm/book3s_exports.c b/arch/powerpc/kvm/book3s_exports.c
index 852989a9bad3..20d4ea8e656d 100644
--- a/arch/powerpc/kvm/book3s_exports.c
+++ b/arch/powerpc/kvm/book3s_exports.c
@@ -25,9 +25,5 @@ EXPORT_SYMBOL_GPL(kvmppc_hv_entry_trampoline);
 #endif
 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 EXPORT_SYMBOL_GPL(kvmppc_entry_trampoline);
-EXPORT_SYMBOL_GPL(kvmppc_load_up_fpu);
-#ifdef CONFIG_ALTIVEC
-EXPORT_SYMBOL_GPL(kvmppc_load_up_altivec);
-#endif
 #endif
 
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index b51d5db78068..17fc9496b6ac 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -31,6 +31,7 @@
 #include <linux/spinlock.h>
 #include <linux/page-flags.h>
 #include <linux/srcu.h>
+#include <linux/miscdevice.h>
 
 #include <asm/reg.h>
 #include <asm/cputable.h>
@@ -85,10 +86,13 @@ static void kvmppc_fast_vcpu_kick_hv(struct kvm_vcpu *vcpu)
 
         /* CPU points to the first thread of the core */
         if (cpu != me && cpu >= 0 && cpu < nr_cpu_ids) {
+#ifdef CONFIG_KVM_XICS
                 int real_cpu = cpu + vcpu->arch.ptid;
                 if (paca[real_cpu].kvm_hstate.xics_phys)
                         xics_wake_cpu(real_cpu);
-                else if (cpu_online(cpu))
+                else
+#endif
+                if (cpu_online(cpu))
                         smp_send_reschedule(cpu);
         }
         put_cpu();
@@ -182,14 +186,28 @@ int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
 
                 switch (arch_compat) {
                 case PVR_ARCH_205:
-                        pcr = PCR_ARCH_205;
+                        /*
+                         * If an arch bit is set in PCR, all the defined
+                         * higher-order arch bits also have to be set.
+                         */
+                        pcr = PCR_ARCH_206 | PCR_ARCH_205;
                         break;
                 case PVR_ARCH_206:
                 case PVR_ARCH_206p:
+                        pcr = PCR_ARCH_206;
+                        break;
+                case PVR_ARCH_207:
                         break;
                 default:
                         return -EINVAL;
                 }
+
+                if (!cpu_has_feature(CPU_FTR_ARCH_207S)) {
+                        /* POWER7 can't emulate POWER8 */
+                        if (!(pcr & PCR_ARCH_206))
+                                return -EINVAL;
+                        pcr &= ~PCR_ARCH_206;
+                }
         }
 
         spin_lock(&vc->lock);
@@ -637,6 +655,7 @@ static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 r = RESUME_GUEST;
                 break;
         case BOOK3S_INTERRUPT_EXTERNAL:
+        case BOOK3S_INTERRUPT_H_DOORBELL:
                 vcpu->stat.ext_intr_exits++;
                 r = RESUME_GUEST;
                 break;
@@ -673,12 +692,10 @@ static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 /* hcall - punt to userspace */
                 int i;
 
-                if (vcpu->arch.shregs.msr & MSR_PR) {
-                        /* sc 1 from userspace - reflect to guest syscall */
-                        kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_SYSCALL);
-                        r = RESUME_GUEST;
-                        break;
-                }
+                /* hypercall with MSR_PR has already been handled in rmode,
+                 * and never reaches here.
+                 */
+
                 run->papr_hcall.nr = kvmppc_get_gpr(vcpu, 3);
                 for (i = 0; i < 9; ++i)
                         run->papr_hcall.args[i] = kvmppc_get_gpr(vcpu, 4 + i);
@@ -708,7 +725,16 @@ static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu,
          * we don't emulate any guest instructions at this stage.
          */
         case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
-                kvmppc_core_queue_program(vcpu, 0x80000);
+                kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
+                r = RESUME_GUEST;
+                break;
+        /*
+         * This occurs if the guest (kernel or userspace), does something that
+         * is prohibited by HFSCR.  We just generate a program interrupt to
+         * the guest.
+         */
+        case BOOK3S_INTERRUPT_H_FAC_UNAVAIL:
+                kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
                 r = RESUME_GUEST;
                 break;
         default:
@@ -766,10 +792,34 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr)
 
         spin_lock(&vc->lock);
         /*
+         * If ILE (interrupt little-endian) has changed, update the
+         * MSR_LE bit in the intr_msr for each vcpu in this vcore.
+         */
+        if ((new_lpcr & LPCR_ILE) != (vc->lpcr & LPCR_ILE)) {
+                struct kvm *kvm = vcpu->kvm;
+                struct kvm_vcpu *vcpu;
+                int i;
+
+                mutex_lock(&kvm->lock);
+                kvm_for_each_vcpu(i, vcpu, kvm) {
+                        if (vcpu->arch.vcore != vc)
+                                continue;
+                        if (new_lpcr & LPCR_ILE)
+                                vcpu->arch.intr_msr |= MSR_LE;
+                        else
+                                vcpu->arch.intr_msr &= ~MSR_LE;
+                }
+                mutex_unlock(&kvm->lock);
+        }
+
+        /*
          * Userspace can only modify DPFD (default prefetch depth),
          * ILE (interrupt little-endian) and TC (translation control).
+         * On POWER8 userspace can also modify AIL (alt. interrupt loc.)
          */
         mask = LPCR_DPFD | LPCR_ILE | LPCR_TC;
+        if (cpu_has_feature(CPU_FTR_ARCH_207S))
+                mask |= LPCR_AIL;
         vc->lpcr = (vc->lpcr & ~mask) | (new_lpcr & mask);
         spin_unlock(&vc->lock);
 }
@@ -787,6 +837,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_DABR:
                 *val = get_reg_val(id, vcpu->arch.dabr);
                 break;
+        case KVM_REG_PPC_DABRX:
+                *val = get_reg_val(id, vcpu->arch.dabrx);
+                break;
         case KVM_REG_PPC_DSCR:
                 *val = get_reg_val(id, vcpu->arch.dscr);
                 break;
@@ -802,7 +855,7 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_UAMOR:
                 *val = get_reg_val(id, vcpu->arch.uamor);
                 break;
-        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRA:
+        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRS:
                 i = id - KVM_REG_PPC_MMCR0;
                 *val = get_reg_val(id, vcpu->arch.mmcr[i]);
                 break;
@@ -810,33 +863,87 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
                 i = id - KVM_REG_PPC_PMC1;
                 *val = get_reg_val(id, vcpu->arch.pmc[i]);
                 break;
+        case KVM_REG_PPC_SPMC1 ... KVM_REG_PPC_SPMC2:
+                i = id - KVM_REG_PPC_SPMC1;
+                *val = get_reg_val(id, vcpu->arch.spmc[i]);
+                break;
         case KVM_REG_PPC_SIAR:
                 *val = get_reg_val(id, vcpu->arch.siar);
                 break;
         case KVM_REG_PPC_SDAR:
                 *val = get_reg_val(id, vcpu->arch.sdar);
                 break;
-#ifdef CONFIG_VSX
-        case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
-                if (cpu_has_feature(CPU_FTR_VSX)) {
-                        /* VSX => FP reg i is stored in arch.vsr[2*i] */
-                        long int i = id - KVM_REG_PPC_FPR0;
-                        *val = get_reg_val(id, vcpu->arch.vsr[2 * i]);
-                } else {
-                        /* let generic code handle it */
-                        r = -EINVAL;
-                }
+        case KVM_REG_PPC_SIER:
+                *val = get_reg_val(id, vcpu->arch.sier);
                 break;
-        case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
-                if (cpu_has_feature(CPU_FTR_VSX)) {
-                        long int i = id - KVM_REG_PPC_VSR0;
-                        val->vsxval[0] = vcpu->arch.vsr[2 * i];
-                        val->vsxval[1] = vcpu->arch.vsr[2 * i + 1];
-                } else {
-                        r = -ENXIO;
-                }
+        case KVM_REG_PPC_IAMR:
+                *val = get_reg_val(id, vcpu->arch.iamr);
+                break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        case KVM_REG_PPC_TFHAR:
+                *val = get_reg_val(id, vcpu->arch.tfhar);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                *val = get_reg_val(id, vcpu->arch.tfiar);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                *val = get_reg_val(id, vcpu->arch.texasr);
+                break;
+#endif
+        case KVM_REG_PPC_FSCR:
+                *val = get_reg_val(id, vcpu->arch.fscr);
+                break;
+        case KVM_REG_PPC_PSPB:
+                *val = get_reg_val(id, vcpu->arch.pspb);
+                break;
+        case KVM_REG_PPC_EBBHR:
+                *val = get_reg_val(id, vcpu->arch.ebbhr);
+                break;
+        case KVM_REG_PPC_EBBRR:
+                *val = get_reg_val(id, vcpu->arch.ebbrr);
+                break;
+        case KVM_REG_PPC_BESCR:
+                *val = get_reg_val(id, vcpu->arch.bescr);
+                break;
+        case KVM_REG_PPC_TAR:
+                *val = get_reg_val(id, vcpu->arch.tar);
+                break;
+        case KVM_REG_PPC_DPDES:
+                *val = get_reg_val(id, vcpu->arch.vcore->dpdes);
+                break;
+        case KVM_REG_PPC_DAWR:
+                *val = get_reg_val(id, vcpu->arch.dawr);
+                break;
+        case KVM_REG_PPC_DAWRX:
+                *val = get_reg_val(id, vcpu->arch.dawrx);
+                break;
+        case KVM_REG_PPC_CIABR:
+                *val = get_reg_val(id, vcpu->arch.ciabr);
+                break;
+        case KVM_REG_PPC_IC:
+                *val = get_reg_val(id, vcpu->arch.ic);
+                break;
+        case KVM_REG_PPC_VTB:
+                *val = get_reg_val(id, vcpu->arch.vtb);
+                break;
+        case KVM_REG_PPC_CSIGR:
+                *val = get_reg_val(id, vcpu->arch.csigr);
+                break;
+        case KVM_REG_PPC_TACR:
+                *val = get_reg_val(id, vcpu->arch.tacr);
+                break;
+        case KVM_REG_PPC_TCSCR:
+                *val = get_reg_val(id, vcpu->arch.tcscr);
+                break;
+        case KVM_REG_PPC_PID:
+                *val = get_reg_val(id, vcpu->arch.pid);
+                break;
+        case KVM_REG_PPC_ACOP:
+                *val = get_reg_val(id, vcpu->arch.acop);
+                break;
+        case KVM_REG_PPC_WORT:
+                *val = get_reg_val(id, vcpu->arch.wort);
                 break;
-#endif /* CONFIG_VSX */
         case KVM_REG_PPC_VPA_ADDR:
                 spin_lock(&vcpu->arch.vpa_update_lock);
                 *val = get_reg_val(id, vcpu->arch.vpa.next_gpa);
@@ -890,6 +997,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_DABR:
                 vcpu->arch.dabr = set_reg_val(id, *val);
                 break;
+        case KVM_REG_PPC_DABRX:
+                vcpu->arch.dabrx = set_reg_val(id, *val) & ~DABRX_HYP;
+                break;
         case KVM_REG_PPC_DSCR:
                 vcpu->arch.dscr = set_reg_val(id, *val);
                 break;
@@ -905,7 +1015,7 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_UAMOR:
                 vcpu->arch.uamor = set_reg_val(id, *val);
                 break;
-        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRA:
+        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRS:
                 i = id - KVM_REG_PPC_MMCR0;
                 vcpu->arch.mmcr[i] = set_reg_val(id, *val);
                 break;
@@ -913,33 +1023,90 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
                 i = id - KVM_REG_PPC_PMC1;
                 vcpu->arch.pmc[i] = set_reg_val(id, *val);
                 break;
+        case KVM_REG_PPC_SPMC1 ... KVM_REG_PPC_SPMC2:
+                i = id - KVM_REG_PPC_SPMC1;
+                vcpu->arch.spmc[i] = set_reg_val(id, *val);
+                break;
         case KVM_REG_PPC_SIAR:
                 vcpu->arch.siar = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_SDAR:
                 vcpu->arch.sdar = set_reg_val(id, *val);
                 break;
-#ifdef CONFIG_VSX
-        case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
-                if (cpu_has_feature(CPU_FTR_VSX)) {
-                        /* VSX => FP reg i is stored in arch.vsr[2*i] */
-                        long int i = id - KVM_REG_PPC_FPR0;
-                        vcpu->arch.vsr[2 * i] = set_reg_val(id, *val);
-                } else {
-                        /* let generic code handle it */
-                        r = -EINVAL;
-                }
+        case KVM_REG_PPC_SIER:
+                vcpu->arch.sier = set_reg_val(id, *val);
                 break;
-        case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
-                if (cpu_has_feature(CPU_FTR_VSX)) {
-                        long int i = id - KVM_REG_PPC_VSR0;
-                        vcpu->arch.vsr[2 * i] = val->vsxval[0];
-                        vcpu->arch.vsr[2 * i + 1] = val->vsxval[1];
-                } else {
-                        r = -ENXIO;
-                }
+        case KVM_REG_PPC_IAMR:
+                vcpu->arch.iamr = set_reg_val(id, *val);
+                break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        case KVM_REG_PPC_TFHAR:
+                vcpu->arch.tfhar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                vcpu->arch.tfiar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                vcpu->arch.texasr = set_reg_val(id, *val);
+                break;
+#endif
+        case KVM_REG_PPC_FSCR:
+                vcpu->arch.fscr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_PSPB:
+                vcpu->arch.pspb = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_EBBHR:
+                vcpu->arch.ebbhr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_EBBRR:
+                vcpu->arch.ebbrr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_BESCR:
+                vcpu->arch.bescr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TAR:
+                vcpu->arch.tar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DPDES:
+                vcpu->arch.vcore->dpdes = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DAWR:
+                vcpu->arch.dawr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DAWRX:
+                vcpu->arch.dawrx = set_reg_val(id, *val) & ~DAWRX_HYP;
+                break;
+        case KVM_REG_PPC_CIABR:
+                vcpu->arch.ciabr = set_reg_val(id, *val);
+                /* Don't allow setting breakpoints in hypervisor code */
+                if ((vcpu->arch.ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
+                        vcpu->arch.ciabr &= ~CIABR_PRIV;        /* disable */
+                break;
+        case KVM_REG_PPC_IC:
+                vcpu->arch.ic = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_VTB:
+                vcpu->arch.vtb = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_CSIGR:
+                vcpu->arch.csigr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TACR:
+                vcpu->arch.tacr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TCSCR:
+                vcpu->arch.tcscr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_PID:
+                vcpu->arch.pid = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_ACOP:
+                vcpu->arch.acop = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_WORT:
+                vcpu->arch.wort = set_reg_val(id, *val);
                 break;
-#endif /* CONFIG_VSX */
         case KVM_REG_PPC_VPA_ADDR:
                 addr = set_reg_val(id, *val);
                 r = -EINVAL;
@@ -1017,6 +1184,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
         spin_lock_init(&vcpu->arch.vpa_update_lock);
         spin_lock_init(&vcpu->arch.tbacct_lock);
         vcpu->arch.busy_preempt = TB_NIL;
+        vcpu->arch.intr_msr = MSR_SF | MSR_ME;
 
         kvmppc_mmu_book3s_hv_init(vcpu);
 
@@ -1034,6 +1202,8 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
                         init_waitqueue_head(&vcore->wq);
                         vcore->preempt_tb = TB_NIL;
                         vcore->lpcr = kvm->arch.lpcr;
+                        vcore->first_vcpuid = core * threads_per_core;
+                        vcore->kvm = kvm;
                 }
                 kvm->arch.vcores[core] = vcore;
                 kvm->arch.online_vcores++;
@@ -1047,6 +1217,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
         ++vcore->num_threads;
         spin_unlock(&vcore->lock);
         vcpu->arch.vcore = vcore;
+        vcpu->arch.ptid = vcpu->vcpu_id - vcore->first_vcpuid;
 
         vcpu->arch.cpu_type = KVM_CPU_3S_64;
         kvmppc_sanity_check(vcpu);
@@ -1110,7 +1281,7 @@ static void kvmppc_end_cede(struct kvm_vcpu *vcpu)
         }
 }
 
-extern int __kvmppc_vcore_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
+extern void __kvmppc_vcore_entry(void);
 
 static void kvmppc_remove_runnable(struct kvmppc_vcore *vc,
                                    struct kvm_vcpu *vcpu)
@@ -1184,13 +1355,16 @@ static void kvmppc_start_thread(struct kvm_vcpu *vcpu)
         tpaca = &paca[cpu];
         tpaca->kvm_hstate.kvm_vcpu = vcpu;
         tpaca->kvm_hstate.kvm_vcore = vc;
-        tpaca->kvm_hstate.napping = 0;
+        tpaca->kvm_hstate.ptid = vcpu->arch.ptid;
         vcpu->cpu = vc->pcpu;
         smp_wmb();
 #if defined(CONFIG_PPC_ICP_NATIVE) && defined(CONFIG_SMP)
-        if (vcpu->arch.ptid) {
+        if (cpu != smp_processor_id()) {
+#ifdef CONFIG_KVM_XICS
                 xics_wake_cpu(cpu);
-                ++vc->n_woken;
+#endif
+                if (vcpu->arch.ptid)
+                        ++vc->n_woken;
         }
 #endif
 }
@@ -1247,10 +1421,10 @@ static int on_primary_thread(void)
  */
 static void kvmppc_run_core(struct kvmppc_vcore *vc)
 {
-        struct kvm_vcpu *vcpu, *vcpu0, *vnext;
+        struct kvm_vcpu *vcpu, *vnext;
         long ret;
         u64 now;
-        int ptid, i, need_vpa_update;
+        int i, need_vpa_update;
         int srcu_idx;
         struct kvm_vcpu *vcpus_to_update[threads_per_core];
 
@@ -1288,25 +1462,6 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
         }
 
         /*
-         * Assign physical thread IDs, first to non-ceded vcpus
-         * and then to ceded ones.
-         */
-        ptid = 0;
-        vcpu0 = NULL;
-        list_for_each_entry(vcpu, &vc->runnable_threads, arch.run_list) {
-                if (!vcpu->arch.ceded) {
-                        if (!ptid)
-                                vcpu0 = vcpu;
-                        vcpu->arch.ptid = ptid++;
-                }
-        }
-        if (!vcpu0)
-                goto out;       /* nothing to run; should never happen */
-        list_for_each_entry(vcpu, &vc->runnable_threads, arch.run_list)
-                if (vcpu->arch.ceded)
-                        vcpu->arch.ptid = ptid++;
-
-        /*
          * Make sure we are running on thread 0, and that
          * secondary threads are offline.
          */
@@ -1322,15 +1477,19 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
                 kvmppc_create_dtl_entry(vcpu, vc);
         }
 
+        /* Set this explicitly in case thread 0 doesn't have a vcpu */
+        get_paca()->kvm_hstate.kvm_vcore = vc;
+        get_paca()->kvm_hstate.ptid = 0;
+
         vc->vcore_state = VCORE_RUNNING;
         preempt_disable();
         spin_unlock(&vc->lock);
 
         kvm_guest_enter();
 
-        srcu_idx = srcu_read_lock(&vcpu0->kvm->srcu);
+        srcu_idx = srcu_read_lock(&vc->kvm->srcu);
 
-        __kvmppc_vcore_entry(NULL, vcpu0);
+        __kvmppc_vcore_entry();
 
         spin_lock(&vc->lock);
         /* disable sending of IPIs on virtual external irqs */
@@ -1345,14 +1504,14 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
         vc->vcore_state = VCORE_EXITING;
         spin_unlock(&vc->lock);
 
-        srcu_read_unlock(&vcpu0->kvm->srcu, srcu_idx);
+        srcu_read_unlock(&vc->kvm->srcu, srcu_idx);
 
         /* make sure updates to secondary vcpu structs are visible now */
         smp_mb();
         kvm_guest_exit();
 
         preempt_enable();
-        kvm_resched(vcpu);
+        cond_resched();
 
         spin_lock(&vc->lock);
         now = get_tb();
@@ -1453,7 +1612,6 @@ static int kvmppc_run_vcpu(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         if (!signal_pending(current)) {
                 if (vc->vcore_state == VCORE_RUNNING &&
                     VCORE_EXIT_COUNT(vc) == 0) {
-                        vcpu->arch.ptid = vc->n_runnable - 1;
                         kvmppc_create_dtl_entry(vcpu, vc);
                         kvmppc_start_thread(vcpu);
                 } else if (vc->vcore_state == VCORE_SLEEPING) {
@@ -2048,6 +2206,9 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
                         LPCR_VPM0 | LPCR_VPM1;
                 kvm->arch.vrma_slb_v = SLB_VSID_B_1T |
                         (VRMA_VSID << SLB_VSID_SHIFT_1T);
+                /* On POWER8 turn on online bit to enable PURR/SPURR */
+                if (cpu_has_feature(CPU_FTR_ARCH_207S))
+                        lpcr |= LPCR_ONL;
         }
         kvm->arch.lpcr = lpcr;
 
@@ -2222,3 +2383,5 @@ static void kvmppc_book3s_exit_hv(void)
 module_init(kvmppc_book3s_init_hv);
 module_exit(kvmppc_book3s_exit_hv);
 MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S
index 928142c64cb0..e873796b1a29 100644
--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -35,7 +35,7 @@
  ****************************************************************************/
 
 /* Registers:
- *  r4: vcpu pointer
+ *  none
  */
 _GLOBAL(__kvmppc_vcore_entry)
 
@@ -57,9 +57,11 @@ BEGIN_FTR_SECTION
         std     r3, HSTATE_DSCR(r13)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
+BEGIN_FTR_SECTION
         /* Save host DABR */
         mfspr   r3, SPRN_DABR
         std     r3, HSTATE_DABR(r13)
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 
         /* Hard-disable interrupts */
         mfmsr   r10
@@ -69,7 +71,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         mtmsrd  r10,1
 
         /* Save host PMU registers */
-        /* R4 is live here (vcpu pointer) but not r3 or r5 */
         li      r3, 1
         sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
         mfspr   r7, SPRN_MMCR0          /* save MMCR0 */
@@ -134,16 +135,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
          * enters the guest with interrupts enabled.
          */
 BEGIN_FTR_SECTION
+        ld      r4, HSTATE_KVM_VCPU(r13)
         ld      r0, VCPU_PENDING_EXC(r4)
         li      r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
         oris    r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
         and.    r0, r0, r7
         beq     32f
-        mr      r31, r4
         lhz     r3, PACAPACAINDEX(r13)
         bl      smp_send_reschedule
         nop
-        mr      r4, r31
 32:
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 #endif /* CONFIG_SMP */
diff --git a/arch/powerpc/kvm/book3s_hv_ras.c b/arch/powerpc/kvm/book3s_hv_ras.c
index a353c485808c..768a9f977c00 100644
--- a/arch/powerpc/kvm/book3s_hv_ras.c
+++ b/arch/powerpc/kvm/book3s_hv_ras.c
@@ -12,6 +12,7 @@
 #include <linux/kvm_host.h>
 #include <linux/kernel.h>
 #include <asm/opal.h>
+#include <asm/mce.h>
 
 /* SRR1 bits for machine check on POWER7 */
 #define SRR1_MC_LDSTERR         (1ul << (63-42))
@@ -58,18 +59,6 @@ static void reload_slb(struct kvm_vcpu *vcpu)
         }
 }
 
-/* POWER7 TLB flush */
-static void flush_tlb_power7(struct kvm_vcpu *vcpu)
-{
-        unsigned long i, rb;
-
-        rb = TLBIEL_INVAL_SET_LPID;
-        for (i = 0; i < POWER7_TLB_SETS; ++i) {
-                asm volatile("tlbiel %0" : : "r" (rb));
-                rb += 1 << TLBIEL_INVAL_SET_SHIFT;
-        }
-}
-
 /*
  * On POWER7, see if we can handle a machine check that occurred inside
  * the guest in real mode, without switching to the host partition.
@@ -79,9 +68,7 @@ static void flush_tlb_power7(struct kvm_vcpu *vcpu)
 static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
 {
         unsigned long srr1 = vcpu->arch.shregs.msr;
-#ifdef CONFIG_PPC_POWERNV
-        struct opal_machine_check_event *opal_evt;
-#endif
+        struct machine_check_event mce_evt;
         long handled = 1;
 
         if (srr1 & SRR1_MC_LDSTERR) {
@@ -96,7 +83,8 @@ static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
                                    DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI);
                 }
                 if (dsisr & DSISR_MC_TLB_MULTI) {
-                        flush_tlb_power7(vcpu);
+                        if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
+                                cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET_LPID);
                         dsisr &= ~DSISR_MC_TLB_MULTI;
                 }
                 /* Any other errors we don't understand? */
@@ -113,28 +101,38 @@ static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
                 reload_slb(vcpu);
                 break;
         case SRR1_MC_IFETCH_TLBMULTI:
-                flush_tlb_power7(vcpu);
+                if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
+                        cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET_LPID);
                 break;
         default:
                 handled = 0;
         }
 
-#ifdef CONFIG_PPC_POWERNV
         /*
-         * See if OPAL has already handled the condition.
-         * We assume that if the condition is recovered then OPAL
+         * See if we have already handled the condition in the linux host.
+         * We assume that if the condition is recovered then linux host
          * will have generated an error log event that we will pick
          * up and log later.
+         * Don't release mce event now. In case if condition is not
+         * recovered we do guest exit and go back to linux host machine
+         * check handler. Hence we need make sure that current mce event
+         * is available for linux host to consume.
          */
-        opal_evt = local_paca->opal_mc_evt;
-        if (opal_evt->version == OpalMCE_V1 &&
-            (opal_evt->severity == OpalMCE_SEV_NO_ERROR ||
-             opal_evt->disposition == OpalMCE_DISPOSITION_RECOVERED))
+        if (!get_mce_event(&mce_evt, MCE_EVENT_DONTRELEASE))
+                goto out;
+
+        if (mce_evt.version == MCE_V1 &&
+            (mce_evt.severity == MCE_SEV_NO_ERROR ||
+             mce_evt.disposition == MCE_DISPOSITION_RECOVERED))
                 handled = 1;
 
+out:
+        /*
+         * If we have handled the error, then release the mce event because
+         * we will be delivering machine check to guest.
+         */
         if (handled)
-                opal_evt->in_use = 0;
-#endif
+                release_mce_event();
 
         return handled;
 }
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 8689e2e30857..37fb3caa4c80 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -134,7 +134,7 @@ static void remove_revmap_chain(struct kvm *kvm, long pte_index,
         unlock_rmap(rmap);
 }
 
-static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
+static pte_t lookup_linux_pte_and_update(pgd_t *pgdir, unsigned long hva,
                               int writing, unsigned long *pte_sizep)
 {
         pte_t *ptep;
@@ -232,7 +232,8 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
 
                 /* Look up the Linux PTE for the backing page */
                 pte_size = psize;
-                pte = lookup_linux_pte(pgdir, hva, writing, &pte_size);
+                pte = lookup_linux_pte_and_update(pgdir, hva, writing,
+                                                  &pte_size);
                 if (pte_present(pte)) {
                         if (writing && !pte_write(pte))
                                 /* make the actual HPTE be read-only */
@@ -672,7 +673,8 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
                         memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
                         if (memslot) {
                                 hva = __gfn_to_hva_memslot(memslot, gfn);
-                                pte = lookup_linux_pte(pgdir, hva, 1, &psize);
+                                pte = lookup_linux_pte_and_update(pgdir, hva,
+                                                                  1, &psize);
                                 if (pte_present(pte) && !pte_write(pte))
                                         r = hpte_make_readonly(r);
                         }
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index be4fa04a37c9..e66d4ec04d95 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -33,6 +33,10 @@
 #error Need to fix lppaca and SLB shadow accesses in little endian mode
 #endif
 
+/* Values in HSTATE_NAPPING(r13) */
+#define NAPPING_CEDE    1
+#define NAPPING_NOVCPU  2
+
 /*
  * Call kvmppc_hv_entry in real mode.
  * Must be called with interrupts hard-disabled.
@@ -57,29 +61,23 @@ _GLOBAL(kvmppc_hv_entry_trampoline)
         RFI
 
 kvmppc_call_hv_entry:
+        ld      r4, HSTATE_KVM_VCPU(r13)
         bl      kvmppc_hv_entry
 
         /* Back from guest - restore host state and return to caller */
 
+BEGIN_FTR_SECTION
         /* Restore host DABR and DABRX */
         ld      r5,HSTATE_DABR(r13)
         li      r6,7
         mtspr   SPRN_DABR,r5
         mtspr   SPRN_DABRX,r6
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 
         /* Restore SPRG3 */
         ld      r3,PACA_SPRG3(r13)
         mtspr   SPRN_SPRG3,r3
 
-        /*
-         * Reload DEC.  HDEC interrupts were disabled when
-         * we reloaded the host's LPCR value.
-         */
-        ld      r3, HSTATE_DECEXP(r13)
-        mftb    r4
-        subf    r4, r4, r3
-        mtspr   SPRN_DEC, r4
-
         /* Reload the host's PMU registers */
         ld      r3, PACALPPACAPTR(r13)  /* is the host using the PMU? */
         lbz     r4, LPPACA_PMCINUSE(r3)
@@ -115,6 +113,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 23:
 
         /*
+         * Reload DEC.  HDEC interrupts were disabled when
+         * we reloaded the host's LPCR value.
+         */
+        ld      r3, HSTATE_DECEXP(r13)
+        mftb    r4
+        subf    r4, r4, r3
+        mtspr   SPRN_DEC, r4
+
+        /*
          * For external and machine check interrupts, we need
          * to call the Linux handler to process the interrupt.
          * We do that by jumping to absolute address 0x500 for
@@ -153,15 +160,75 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
 13:     b       machine_check_fwnmi
 
+kvmppc_primary_no_guest:
+        /* We handle this much like a ceded vcpu */
+        /* set our bit in napping_threads */
+        ld      r5, HSTATE_KVM_VCORE(r13)
+        lbz     r7, HSTATE_PTID(r13)
+        li      r0, 1
+        sld     r0, r0, r7
+        addi    r6, r5, VCORE_NAPPING_THREADS
+1:      lwarx   r3, 0, r6
+        or      r3, r3, r0
+        stwcx.  r3, 0, r6
+        bne     1b
+        /* order napping_threads update vs testing entry_exit_count */
+        isync
+        li      r12, 0
+        lwz     r7, VCORE_ENTRY_EXIT(r5)
+        cmpwi   r7, 0x100
+        bge     kvm_novcpu_exit /* another thread already exiting */
+        li      r3, NAPPING_NOVCPU
+        stb     r3, HSTATE_NAPPING(r13)
+        li      r3, 1
+        stb     r3, HSTATE_HWTHREAD_REQ(r13)
+
+        b       kvm_do_nap
+
+kvm_novcpu_wakeup:
+        ld      r1, HSTATE_HOST_R1(r13)
+        ld      r5, HSTATE_KVM_VCORE(r13)
+        li      r0, 0
+        stb     r0, HSTATE_NAPPING(r13)
+        stb     r0, HSTATE_HWTHREAD_REQ(r13)
+
+        /* check the wake reason */
+        bl      kvmppc_check_wake_reason
+        
+        /* see if any other thread is already exiting */
+        lwz     r0, VCORE_ENTRY_EXIT(r5)
+        cmpwi   r0, 0x100
+        bge     kvm_novcpu_exit
+
+        /* clear our bit in napping_threads */
+        lbz     r7, HSTATE_PTID(r13)
+        li      r0, 1
+        sld     r0, r0, r7
+        addi    r6, r5, VCORE_NAPPING_THREADS
+4:      lwarx   r7, 0, r6
+        andc    r7, r7, r0
+        stwcx.  r7, 0, r6
+        bne     4b
+
+        /* See if the wake reason means we need to exit */
+        cmpdi   r3, 0
+        bge     kvm_novcpu_exit
+
+        /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
+        ld      r4, HSTATE_KVM_VCPU(r13)
+        cmpdi   r4, 0
+        bne     kvmppc_got_guest
+
+kvm_novcpu_exit:
+        b       hdec_soon
+
 /*
- * We come in here when wakened from nap mode on a secondary hw thread.
+ * We come in here when wakened from nap mode.
  * Relocation is off and most register values are lost.
  * r13 points to the PACA.
  */
         .globl  kvm_start_guest
 kvm_start_guest:
-        ld      r1,PACAEMERGSP(r13)
-        subi    r1,r1,STACK_FRAME_OVERHEAD
         ld      r2,PACATOC(r13)
 
         li      r0,KVM_HWTHREAD_IN_KVM
@@ -173,8 +240,13 @@ kvm_start_guest:
 
         /* were we napping due to cede? */
         lbz     r0,HSTATE_NAPPING(r13)
-        cmpwi   r0,0
-        bne     kvm_end_cede
+        cmpwi   r0,NAPPING_CEDE
+        beq     kvm_end_cede
+        cmpwi   r0,NAPPING_NOVCPU
+        beq     kvm_novcpu_wakeup
+
+        ld      r1,PACAEMERGSP(r13)
+        subi    r1,r1,STACK_FRAME_OVERHEAD
 
         /*
          * We weren't napping due to cede, so this must be a secondary
@@ -184,40 +256,22 @@ kvm_start_guest:
          */
 
         /* Check the wake reason in SRR1 to see why we got here */
-        mfspr   r3,SPRN_SRR1
-        rlwinm  r3,r3,44-31,0x7         /* extract wake reason field */
-        cmpwi   r3,4                    /* was it an external interrupt? */
-        bne     27f                     /* if not */
-        ld      r5,HSTATE_XICS_PHYS(r13)
-        li      r7,XICS_XIRR            /* if it was an external interrupt, */
-        lwzcix  r8,r5,r7                /* get and ack the interrupt */
-        sync
-        clrldi. r9,r8,40                /* get interrupt source ID. */
-        beq     28f                     /* none there? */
-        cmpwi   r9,XICS_IPI             /* was it an IPI? */
-        bne     29f
-        li      r0,0xff
-        li      r6,XICS_MFRR
-        stbcix  r0,r5,r6                /* clear IPI */
-        stwcix  r8,r5,r7                /* EOI the interrupt */
-        sync                            /* order loading of vcpu after that */
+        bl      kvmppc_check_wake_reason
+        cmpdi   r3, 0
+        bge     kvm_no_guest
 
         /* get vcpu pointer, NULL if we have no vcpu to run */
         ld      r4,HSTATE_KVM_VCPU(r13)
         cmpdi   r4,0
         /* if we have no vcpu to run, go back to sleep */
         beq     kvm_no_guest
-        b       30f
 
-27:     /* XXX should handle hypervisor maintenance interrupts etc. here */
-        b       kvm_no_guest
-28:     /* SRR1 said external but ICP said nope?? */
-        b       kvm_no_guest
-29:     /* External non-IPI interrupt to offline secondary thread? help?? */
-        stw     r8,HSTATE_SAVED_XIRR(r13)
-        b       kvm_no_guest
+        /* Set HSTATE_DSCR(r13) to something sensible */
+        LOAD_REG_ADDR(r6, dscr_default)
+        ld      r6, 0(r6)
+        std     r6, HSTATE_DSCR(r13)
 
-30:     bl      kvmppc_hv_entry
+        bl      kvmppc_hv_entry
 
         /* Back from the guest, go back to nap */
         /* Clear our vcpu pointer so we don't come back in early */
@@ -229,18 +283,6 @@ kvm_start_guest:
          * visible we could be given another vcpu.
          */
         lwsync
-        /* Clear any pending IPI - we're an offline thread */
-        ld      r5, HSTATE_XICS_PHYS(r13)
-        li      r7, XICS_XIRR
-        lwzcix  r3, r5, r7              /* ack any pending interrupt */
-        rlwinm. r0, r3, 0, 0xffffff     /* any pending? */
-        beq     37f
-        sync
-        li      r0, 0xff
-        li      r6, XICS_MFRR
-        stbcix  r0, r5, r6              /* clear the IPI */
-        stwcix  r3, r5, r7              /* EOI it */
-37:     sync
 
         /* increment the nap count and then go to nap mode */
         ld      r4, HSTATE_KVM_VCORE(r13)
@@ -253,6 +295,7 @@ kvm_start_guest:
 kvm_no_guest:
         li      r0, KVM_HWTHREAD_IN_NAP
         stb     r0, HSTATE_HWTHREAD_STATE(r13)
+kvm_do_nap:
         li      r3, LPCR_PECE0
         mfspr   r4, SPRN_LPCR
         rlwimi  r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
@@ -277,7 +320,7 @@ kvmppc_hv_entry:
 
         /* Required state:
          *
-         * R4 = vcpu pointer
+         * R4 = vcpu pointer (or NULL)
          * MSR = ~IR|DR
          * R13 = PACA
          * R1 = host R1
@@ -287,122 +330,12 @@ kvmppc_hv_entry:
         std     r0, PPC_LR_STKOFF(r1)
         stdu    r1, -112(r1)
 
-        /* Set partition DABR */
-        /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
-        li      r5,3
-        ld      r6,VCPU_DABR(r4)
-        mtspr   SPRN_DABRX,r5
-        mtspr   SPRN_DABR,r6
-BEGIN_FTR_SECTION
-        isync
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-
-        /* Load guest PMU registers */
-        /* R4 is live here (vcpu pointer) */
-        li      r3, 1
-        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
-        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
-        isync
-        lwz     r3, VCPU_PMC(r4)        /* always load up guest PMU registers */
-        lwz     r5, VCPU_PMC + 4(r4)    /* to prevent information leak */
-        lwz     r6, VCPU_PMC + 8(r4)
-        lwz     r7, VCPU_PMC + 12(r4)
-        lwz     r8, VCPU_PMC + 16(r4)
-        lwz     r9, VCPU_PMC + 20(r4)
-BEGIN_FTR_SECTION
-        lwz     r10, VCPU_PMC + 24(r4)
-        lwz     r11, VCPU_PMC + 28(r4)
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-        mtspr   SPRN_PMC1, r3
-        mtspr   SPRN_PMC2, r5
-        mtspr   SPRN_PMC3, r6
-        mtspr   SPRN_PMC4, r7
-        mtspr   SPRN_PMC5, r8
-        mtspr   SPRN_PMC6, r9
-BEGIN_FTR_SECTION
-        mtspr   SPRN_PMC7, r10
-        mtspr   SPRN_PMC8, r11
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-        ld      r3, VCPU_MMCR(r4)
-        ld      r5, VCPU_MMCR + 8(r4)
-        ld      r6, VCPU_MMCR + 16(r4)
-        ld      r7, VCPU_SIAR(r4)
-        ld      r8, VCPU_SDAR(r4)
-        mtspr   SPRN_MMCR1, r5
-        mtspr   SPRN_MMCRA, r6
-        mtspr   SPRN_SIAR, r7
-        mtspr   SPRN_SDAR, r8
-        mtspr   SPRN_MMCR0, r3
-        isync
-
-        /* Load up FP, VMX and VSX registers */
-        bl      kvmppc_load_fp
-
-        ld      r14, VCPU_GPR(R14)(r4)
-        ld      r15, VCPU_GPR(R15)(r4)
-        ld      r16, VCPU_GPR(R16)(r4)
-        ld      r17, VCPU_GPR(R17)(r4)
-        ld      r18, VCPU_GPR(R18)(r4)
-        ld      r19, VCPU_GPR(R19)(r4)
-        ld      r20, VCPU_GPR(R20)(r4)
-        ld      r21, VCPU_GPR(R21)(r4)
-        ld      r22, VCPU_GPR(R22)(r4)
-        ld      r23, VCPU_GPR(R23)(r4)
-        ld      r24, VCPU_GPR(R24)(r4)
-        ld      r25, VCPU_GPR(R25)(r4)
-        ld      r26, VCPU_GPR(R26)(r4)
-        ld      r27, VCPU_GPR(R27)(r4)
-        ld      r28, VCPU_GPR(R28)(r4)
-        ld      r29, VCPU_GPR(R29)(r4)
-        ld      r30, VCPU_GPR(R30)(r4)
-        ld      r31, VCPU_GPR(R31)(r4)
-
-BEGIN_FTR_SECTION
-        /* Switch DSCR to guest value */
-        ld      r5, VCPU_DSCR(r4)
-        mtspr   SPRN_DSCR, r5
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-
-        /*
-         * Set the decrementer to the guest decrementer.
-         */
-        ld      r8,VCPU_DEC_EXPIRES(r4)
-        mftb    r7
-        subf    r3,r7,r8
-        mtspr   SPRN_DEC,r3
-        stw     r3,VCPU_DEC(r4)
-
-        ld      r5, VCPU_SPRG0(r4)
-        ld      r6, VCPU_SPRG1(r4)
-        ld      r7, VCPU_SPRG2(r4)
-        ld      r8, VCPU_SPRG3(r4)
-        mtspr   SPRN_SPRG0, r5
-        mtspr   SPRN_SPRG1, r6
-        mtspr   SPRN_SPRG2, r7
-        mtspr   SPRN_SPRG3, r8
-
         /* Save R1 in the PACA */
         std     r1, HSTATE_HOST_R1(r13)
 
-        /* Load up DAR and DSISR */
-        ld      r5, VCPU_DAR(r4)
-        lwz     r6, VCPU_DSISR(r4)
-        mtspr   SPRN_DAR, r5
-        mtspr   SPRN_DSISR, r6
-
         li      r6, KVM_GUEST_MODE_HOST_HV
         stb     r6, HSTATE_IN_GUEST(r13)
 
-BEGIN_FTR_SECTION
-        /* Restore AMR and UAMOR, set AMOR to all 1s */
-        ld      r5,VCPU_AMR(r4)
-        ld      r6,VCPU_UAMOR(r4)
-        li      r7,-1
-        mtspr   SPRN_AMR,r5
-        mtspr   SPRN_UAMOR,r6
-        mtspr   SPRN_AMOR,r7
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-
         /* Clear out SLB */
         li      r6,0
         slbmte  r6,r6
@@ -428,8 +361,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         bne     21b
 
         /* Primary thread switches to guest partition. */
-        ld      r9,VCPU_KVM(r4)         /* pointer to struct kvm */
-        lwz     r6,VCPU_PTID(r4)
+        ld      r9,VCORE_KVM(r5)        /* pointer to struct kvm */
+        lbz     r6,HSTATE_PTID(r13)
         cmpwi   r6,0
         bne     20f
         ld      r6,KVM_SDR1(r9)
@@ -457,7 +390,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         andc    r7,r7,r0
         stdcx.  r7,0,r6
         bne     23b
-        li      r6,128                  /* and flush the TLB */
+        /* Flush the TLB of any entries for this LPID */
+        /* use arch 2.07S as a proxy for POWER8 */
+BEGIN_FTR_SECTION
+        li      r6,512                  /* POWER8 has 512 sets */
+FTR_SECTION_ELSE
+        li      r6,128                  /* POWER7 has 128 sets */
+ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
         mtctr   r6
         li      r7,0x800                /* IS field = 0b10 */
         ptesync
@@ -487,6 +426,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         beq     38f
         mtspr   SPRN_PCR, r7
 38:
+
+BEGIN_FTR_SECTION
+        /* DPDES is shared between threads */
+        ld      r8, VCORE_DPDES(r5)
+        mtspr   SPRN_DPDES, r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
         li      r0,1
         stb     r0,VCORE_IN_GUEST(r5)   /* signal secondaries to continue */
         b       10f
@@ -503,32 +449,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         mtspr   SPRN_RMOR,r8
         isync
 
-        /* Increment yield count if they have a VPA */
-        ld      r3, VCPU_VPA(r4)
-        cmpdi   r3, 0
-        beq     25f
-        lwz     r5, LPPACA_YIELDCOUNT(r3)
-        addi    r5, r5, 1
-        stw     r5, LPPACA_YIELDCOUNT(r3)
-        li      r6, 1
-        stb     r6, VCPU_VPA_DIRTY(r4)
-25:
         /* Check if HDEC expires soon */
         mfspr   r3,SPRN_HDEC
-        cmpwi   r3,10
+        cmpwi   r3,512          /* 1 microsecond */
         li      r12,BOOK3S_INTERRUPT_HV_DECREMENTER
-        mr      r9,r4
         blt     hdec_soon
-
-        /* Save purr/spurr */
-        mfspr   r5,SPRN_PURR
-        mfspr   r6,SPRN_SPURR
-        std     r5,HSTATE_PURR(r13)
-        std     r6,HSTATE_SPURR(r13)
-        ld      r7,VCPU_PURR(r4)
-        ld      r8,VCPU_SPURR(r4)
-        mtspr   SPRN_PURR,r7
-        mtspr   SPRN_SPURR,r8
         b       31f
 
         /*
@@ -539,7 +464,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
          * We also have to invalidate the TLB since its
          * entries aren't tagged with the LPID.
          */
-30:     ld      r9,VCPU_KVM(r4)         /* pointer to struct kvm */
+30:     ld      r5,HSTATE_KVM_VCORE(r13)
+        ld      r9,VCORE_KVM(r5)        /* pointer to struct kvm */
 
         /* first take native_tlbie_lock */
         .section ".toc","aw"
@@ -604,7 +530,6 @@ toc_tlbie_lock:
         mfspr   r3,SPRN_HDEC
         cmpwi   r3,10
         li      r12,BOOK3S_INTERRUPT_HV_DECREMENTER
-        mr      r9,r4
         blt     hdec_soon
 
         /* Enable HDEC interrupts */
@@ -619,9 +544,14 @@ toc_tlbie_lock:
         mfspr   r0,SPRN_HID0
         mfspr   r0,SPRN_HID0
         mfspr   r0,SPRN_HID0
+31:
+        /* Do we have a guest vcpu to run? */
+        cmpdi   r4, 0
+        beq     kvmppc_primary_no_guest
+kvmppc_got_guest:
 
         /* Load up guest SLB entries */
-31:     lwz     r5,VCPU_SLB_MAX(r4)
+        lwz     r5,VCPU_SLB_MAX(r4)
         cmpwi   r5,0
         beq     9f
         mtctr   r5
@@ -632,6 +562,209 @@ toc_tlbie_lock:
         addi    r6,r6,VCPU_SLB_SIZE
         bdnz    1b
 9:
+        /* Increment yield count if they have a VPA */
+        ld      r3, VCPU_VPA(r4)
+        cmpdi   r3, 0
+        beq     25f
+        lwz     r5, LPPACA_YIELDCOUNT(r3)
+        addi    r5, r5, 1
+        stw     r5, LPPACA_YIELDCOUNT(r3)
+        li      r6, 1
+        stb     r6, VCPU_VPA_DIRTY(r4)
+25:
+
+BEGIN_FTR_SECTION
+        /* Save purr/spurr */
+        mfspr   r5,SPRN_PURR
+        mfspr   r6,SPRN_SPURR
+        std     r5,HSTATE_PURR(r13)
+        std     r6,HSTATE_SPURR(r13)
+        ld      r7,VCPU_PURR(r4)
+        ld      r8,VCPU_SPURR(r4)
+        mtspr   SPRN_PURR,r7
+        mtspr   SPRN_SPURR,r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+
+BEGIN_FTR_SECTION
+        /* Set partition DABR */
+        /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
+        lwz     r5,VCPU_DABRX(r4)
+        ld      r6,VCPU_DABR(r4)
+        mtspr   SPRN_DABRX,r5
+        mtspr   SPRN_DABR,r6
+ BEGIN_FTR_SECTION_NESTED(89)
+        isync
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+
+        /* Load guest PMU registers */
+        /* R4 is live here (vcpu pointer) */
+        li      r3, 1
+        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
+        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
+        isync
+        lwz     r3, VCPU_PMC(r4)        /* always load up guest PMU registers */
+        lwz     r5, VCPU_PMC + 4(r4)    /* to prevent information leak */
+        lwz     r6, VCPU_PMC + 8(r4)
+        lwz     r7, VCPU_PMC + 12(r4)
+        lwz     r8, VCPU_PMC + 16(r4)
+        lwz     r9, VCPU_PMC + 20(r4)
+BEGIN_FTR_SECTION
+        lwz     r10, VCPU_PMC + 24(r4)
+        lwz     r11, VCPU_PMC + 28(r4)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+        mtspr   SPRN_PMC1, r3
+        mtspr   SPRN_PMC2, r5
+        mtspr   SPRN_PMC3, r6
+        mtspr   SPRN_PMC4, r7
+        mtspr   SPRN_PMC5, r8
+        mtspr   SPRN_PMC6, r9
+BEGIN_FTR_SECTION
+        mtspr   SPRN_PMC7, r10
+        mtspr   SPRN_PMC8, r11
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+        ld      r3, VCPU_MMCR(r4)
+        ld      r5, VCPU_MMCR + 8(r4)
+        ld      r6, VCPU_MMCR + 16(r4)
+        ld      r7, VCPU_SIAR(r4)
+        ld      r8, VCPU_SDAR(r4)
+        mtspr   SPRN_MMCR1, r5
+        mtspr   SPRN_MMCRA, r6
+        mtspr   SPRN_SIAR, r7
+        mtspr   SPRN_SDAR, r8
+BEGIN_FTR_SECTION
+        ld      r5, VCPU_MMCR + 24(r4)
+        ld      r6, VCPU_SIER(r4)
+        lwz     r7, VCPU_PMC + 24(r4)
+        lwz     r8, VCPU_PMC + 28(r4)
+        ld      r9, VCPU_MMCR + 32(r4)
+        mtspr   SPRN_MMCR2, r5
+        mtspr   SPRN_SIER, r6
+        mtspr   SPRN_SPMC1, r7
+        mtspr   SPRN_SPMC2, r8
+        mtspr   SPRN_MMCRS, r9
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+        mtspr   SPRN_MMCR0, r3
+        isync
+
+        /* Load up FP, VMX and VSX registers */
+        bl      kvmppc_load_fp
+
+        ld      r14, VCPU_GPR(R14)(r4)
+        ld      r15, VCPU_GPR(R15)(r4)
+        ld      r16, VCPU_GPR(R16)(r4)
+        ld      r17, VCPU_GPR(R17)(r4)
+        ld      r18, VCPU_GPR(R18)(r4)
+        ld      r19, VCPU_GPR(R19)(r4)
+        ld      r20, VCPU_GPR(R20)(r4)
+        ld      r21, VCPU_GPR(R21)(r4)
+        ld      r22, VCPU_GPR(R22)(r4)
+        ld      r23, VCPU_GPR(R23)(r4)
+        ld      r24, VCPU_GPR(R24)(r4)
+        ld      r25, VCPU_GPR(R25)(r4)
+        ld      r26, VCPU_GPR(R26)(r4)
+        ld      r27, VCPU_GPR(R27)(r4)
+        ld      r28, VCPU_GPR(R28)(r4)
+        ld      r29, VCPU_GPR(R29)(r4)
+        ld      r30, VCPU_GPR(R30)(r4)
+        ld      r31, VCPU_GPR(R31)(r4)
+
+BEGIN_FTR_SECTION
+        /* Switch DSCR to guest value */
+        ld      r5, VCPU_DSCR(r4)
+        mtspr   SPRN_DSCR, r5
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+
+BEGIN_FTR_SECTION
+        /* Skip next section on POWER7 or PPC970 */
+        b       8f
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
+        mfmsr   r8
+        li      r0, 1
+        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
+        mtmsrd  r8
+
+        /* Load up POWER8-specific registers */
+        ld      r5, VCPU_IAMR(r4)
+        lwz     r6, VCPU_PSPB(r4)
+        ld      r7, VCPU_FSCR(r4)
+        mtspr   SPRN_IAMR, r5
+        mtspr   SPRN_PSPB, r6
+        mtspr   SPRN_FSCR, r7
+        ld      r5, VCPU_DAWR(r4)
+        ld      r6, VCPU_DAWRX(r4)
+        ld      r7, VCPU_CIABR(r4)
+        ld      r8, VCPU_TAR(r4)
+        mtspr   SPRN_DAWR, r5
+        mtspr   SPRN_DAWRX, r6
+        mtspr   SPRN_CIABR, r7
+        mtspr   SPRN_TAR, r8
+        ld      r5, VCPU_IC(r4)
+        ld      r6, VCPU_VTB(r4)
+        mtspr   SPRN_IC, r5
+        mtspr   SPRN_VTB, r6
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        ld      r5, VCPU_TFHAR(r4)
+        ld      r6, VCPU_TFIAR(r4)
+        ld      r7, VCPU_TEXASR(r4)
+        mtspr   SPRN_TFHAR, r5
+        mtspr   SPRN_TFIAR, r6
+        mtspr   SPRN_TEXASR, r7
+#endif
+        ld      r8, VCPU_EBBHR(r4)
+        mtspr   SPRN_EBBHR, r8
+        ld      r5, VCPU_EBBRR(r4)
+        ld      r6, VCPU_BESCR(r4)
+        ld      r7, VCPU_CSIGR(r4)
+        ld      r8, VCPU_TACR(r4)
+        mtspr   SPRN_EBBRR, r5
+        mtspr   SPRN_BESCR, r6
+        mtspr   SPRN_CSIGR, r7
+        mtspr   SPRN_TACR, r8
+        ld      r5, VCPU_TCSCR(r4)
+        ld      r6, VCPU_ACOP(r4)
+        lwz     r7, VCPU_GUEST_PID(r4)
+        ld      r8, VCPU_WORT(r4)
+        mtspr   SPRN_TCSCR, r5
+        mtspr   SPRN_ACOP, r6
+        mtspr   SPRN_PID, r7
+        mtspr   SPRN_WORT, r8
+8:
+
+        /*
+         * Set the decrementer to the guest decrementer.
+         */
+        ld      r8,VCPU_DEC_EXPIRES(r4)
+        mftb    r7
+        subf    r3,r7,r8
+        mtspr   SPRN_DEC,r3
+        stw     r3,VCPU_DEC(r4)
+
+        ld      r5, VCPU_SPRG0(r4)
+        ld      r6, VCPU_SPRG1(r4)
+        ld      r7, VCPU_SPRG2(r4)
+        ld      r8, VCPU_SPRG3(r4)
+        mtspr   SPRN_SPRG0, r5
+        mtspr   SPRN_SPRG1, r6
+        mtspr   SPRN_SPRG2, r7
+        mtspr   SPRN_SPRG3, r8
+
+        /* Load up DAR and DSISR */
+        ld      r5, VCPU_DAR(r4)
+        lwz     r6, VCPU_DSISR(r4)
+        mtspr   SPRN_DAR, r5
+        mtspr   SPRN_DSISR, r6
+
+BEGIN_FTR_SECTION
+        /* Restore AMR and UAMOR, set AMOR to all 1s */
+        ld      r5,VCPU_AMR(r4)
+        ld      r6,VCPU_UAMOR(r4)
+        li      r7,-1
+        mtspr   SPRN_AMR,r5
+        mtspr   SPRN_UAMOR,r6
+        mtspr   SPRN_AMOR,r7
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
         /* Restore state of CTRL run bit; assume 1 on entry */
         lwz     r5,VCPU_CTRL(r4)
@@ -647,48 +780,53 @@ toc_tlbie_lock:
         mtctr   r6
         mtxer   r7
 
+kvmppc_cede_reentry:            /* r4 = vcpu, r13 = paca */
         ld      r10, VCPU_PC(r4)
         ld      r11, VCPU_MSR(r4)
-kvmppc_cede_reentry:            /* r4 = vcpu, r13 = paca */
         ld      r6, VCPU_SRR0(r4)
         ld      r7, VCPU_SRR1(r4)
+        mtspr   SPRN_SRR0, r6
+        mtspr   SPRN_SRR1, r7
 
+deliver_guest_interrupt:
         /* r11 = vcpu->arch.msr & ~MSR_HV */
         rldicl  r11, r11, 63 - MSR_HV_LG, 1
         rotldi  r11, r11, 1 + MSR_HV_LG
         ori     r11, r11, MSR_ME
 
         /* Check if we can deliver an external or decrementer interrupt now */
-        ld      r0,VCPU_PENDING_EXC(r4)
-        lis     r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
-        and     r0,r0,r8
-        cmpdi   cr1,r0,0
-        andi.   r0,r11,MSR_EE
-        beq     cr1,11f
+        ld      r0, VCPU_PENDING_EXC(r4)
+        rldicl  r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
+        cmpdi   cr1, r0, 0
+        andi.   r8, r11, MSR_EE
 BEGIN_FTR_SECTION
-        mfspr   r8,SPRN_LPCR
-        ori     r8,r8,LPCR_MER
-        mtspr   SPRN_LPCR,r8
+        mfspr   r8, SPRN_LPCR
+        /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
+        rldimi  r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
+        mtspr   SPRN_LPCR, r8
         isync
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         beq     5f
-        li      r0,BOOK3S_INTERRUPT_EXTERNAL
-12:     mr      r6,r10
-        mr      r10,r0
-        mr      r7,r11
-        li      r11,(MSR_ME << 1) | 1   /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11,r11,63
-        b       5f
-11:     beq     5f
-        mfspr   r0,SPRN_DEC
-        cmpwi   r0,0
-        li      r0,BOOK3S_INTERRUPT_DECREMENTER
-        blt     12b
+        li      r0, BOOK3S_INTERRUPT_EXTERNAL
+        bne     cr1, 12f
+        mfspr   r0, SPRN_DEC
+        cmpwi   r0, 0
+        li      r0, BOOK3S_INTERRUPT_DECREMENTER
+        bge     5f
 
-        /* Move SRR0 and SRR1 into the respective regs */
-5:      mtspr   SPRN_SRR0, r6
-        mtspr   SPRN_SRR1, r7
+12:     mtspr   SPRN_SRR0, r10
+        mr      r10,r0
+        mtspr   SPRN_SRR1, r11
+        ld      r11, VCPU_INTR_MSR(r4)
+5:
 
+/*
+ * Required state:
+ * R4 = vcpu
+ * R10: value for HSRR0
+ * R11: value for HSRR1
+ * R13 = PACA
+ */
 fast_guest_return:
         li      r0,0
         stb     r0,VCPU_CEDED(r4)       /* cancel cede */
@@ -868,39 +1006,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         /* External interrupt, first check for host_ipi. If this is
          * set, we know the host wants us out so let's do it now
          */
-do_ext_interrupt:
         bl      kvmppc_read_intr
         cmpdi   r3, 0
         bgt     ext_interrupt_to_host
 
-        /* Allright, looks like an IPI for the guest, we need to set MER */
         /* Check if any CPU is heading out to the host, if so head out too */
         ld      r5, HSTATE_KVM_VCORE(r13)
         lwz     r0, VCORE_ENTRY_EXIT(r5)
         cmpwi   r0, 0x100
         bge     ext_interrupt_to_host
 
-        /* See if there is a pending interrupt for the guest */
-        mfspr   r8, SPRN_LPCR
-        ld      r0, VCPU_PENDING_EXC(r9)
-        /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
-        rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
-        rldimi  r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
-        beq     2f
-
-        /* And if the guest EE is set, we can deliver immediately, else
-         * we return to the guest with MER set
-         */
-        andi.   r0, r11, MSR_EE
-        beq     2f
-        mtspr   SPRN_SRR0, r10
-        mtspr   SPRN_SRR1, r11
-        li      r10, BOOK3S_INTERRUPT_EXTERNAL
-        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11, r11, 63
-2:      mr      r4, r9
-        mtspr   SPRN_LPCR, r8
-        b       fast_guest_return
+        /* Return to guest after delivering any pending interrupt */
+        mr      r4, r9
+        b       deliver_guest_interrupt
 
 ext_interrupt_to_host:
 
@@ -975,13 +1093,194 @@ BEGIN_FTR_SECTION
         mtspr   SPRN_SPURR,r4
 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
 
+        /* Save DEC */
+        mfspr   r5,SPRN_DEC
+        mftb    r6
+        extsw   r5,r5
+        add     r5,r5,r6
+        std     r5,VCPU_DEC_EXPIRES(r9)
+
+BEGIN_FTR_SECTION
+        b       8f
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
+        mfmsr   r8
+        li      r0, 1
+        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
+        mtmsrd  r8
+
+        /* Save POWER8-specific registers */
+        mfspr   r5, SPRN_IAMR
+        mfspr   r6, SPRN_PSPB
+        mfspr   r7, SPRN_FSCR
+        std     r5, VCPU_IAMR(r9)
+        stw     r6, VCPU_PSPB(r9)
+        std     r7, VCPU_FSCR(r9)
+        mfspr   r5, SPRN_IC
+        mfspr   r6, SPRN_VTB
+        mfspr   r7, SPRN_TAR
+        std     r5, VCPU_IC(r9)
+        std     r6, VCPU_VTB(r9)
+        std     r7, VCPU_TAR(r9)
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        mfspr   r5, SPRN_TFHAR
+        mfspr   r6, SPRN_TFIAR
+        mfspr   r7, SPRN_TEXASR
+        std     r5, VCPU_TFHAR(r9)
+        std     r6, VCPU_TFIAR(r9)
+        std     r7, VCPU_TEXASR(r9)
+#endif
+        mfspr   r8, SPRN_EBBHR
+        std     r8, VCPU_EBBHR(r9)
+        mfspr   r5, SPRN_EBBRR
+        mfspr   r6, SPRN_BESCR
+        mfspr   r7, SPRN_CSIGR
+        mfspr   r8, SPRN_TACR
+        std     r5, VCPU_EBBRR(r9)
+        std     r6, VCPU_BESCR(r9)
+        std     r7, VCPU_CSIGR(r9)
+        std     r8, VCPU_TACR(r9)
+        mfspr   r5, SPRN_TCSCR
+        mfspr   r6, SPRN_ACOP
+        mfspr   r7, SPRN_PID
+        mfspr   r8, SPRN_WORT
+        std     r5, VCPU_TCSCR(r9)
+        std     r6, VCPU_ACOP(r9)
+        stw     r7, VCPU_GUEST_PID(r9)
+        std     r8, VCPU_WORT(r9)
+8:
+
+        /* Save and reset AMR and UAMOR before turning on the MMU */
+BEGIN_FTR_SECTION
+        mfspr   r5,SPRN_AMR
+        mfspr   r6,SPRN_UAMOR
+        std     r5,VCPU_AMR(r9)
+        std     r6,VCPU_UAMOR(r9)
+        li      r6,0
+        mtspr   SPRN_AMR,r6
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+
+        /* Switch DSCR back to host value */
+BEGIN_FTR_SECTION
+        mfspr   r8, SPRN_DSCR
+        ld      r7, HSTATE_DSCR(r13)
+        std     r8, VCPU_DSCR(r9)
+        mtspr   SPRN_DSCR, r7
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+
+        /* Save non-volatile GPRs */
+        std     r14, VCPU_GPR(R14)(r9)
+        std     r15, VCPU_GPR(R15)(r9)
+        std     r16, VCPU_GPR(R16)(r9)
+        std     r17, VCPU_GPR(R17)(r9)
+        std     r18, VCPU_GPR(R18)(r9)
+        std     r19, VCPU_GPR(R19)(r9)
+        std     r20, VCPU_GPR(R20)(r9)
+        std     r21, VCPU_GPR(R21)(r9)
+        std     r22, VCPU_GPR(R22)(r9)
+        std     r23, VCPU_GPR(R23)(r9)
+        std     r24, VCPU_GPR(R24)(r9)
+        std     r25, VCPU_GPR(R25)(r9)
+        std     r26, VCPU_GPR(R26)(r9)
+        std     r27, VCPU_GPR(R27)(r9)
+        std     r28, VCPU_GPR(R28)(r9)
+        std     r29, VCPU_GPR(R29)(r9)
+        std     r30, VCPU_GPR(R30)(r9)
+        std     r31, VCPU_GPR(R31)(r9)
+
+        /* Save SPRGs */
+        mfspr   r3, SPRN_SPRG0
+        mfspr   r4, SPRN_SPRG1
+        mfspr   r5, SPRN_SPRG2
+        mfspr   r6, SPRN_SPRG3
+        std     r3, VCPU_SPRG0(r9)
+        std     r4, VCPU_SPRG1(r9)
+        std     r5, VCPU_SPRG2(r9)
+        std     r6, VCPU_SPRG3(r9)
+
+        /* save FP state */
+        mr      r3, r9
+        bl      kvmppc_save_fp
+
+        /* Increment yield count if they have a VPA */
+        ld      r8, VCPU_VPA(r9)        /* do they have a VPA? */
+        cmpdi   r8, 0
+        beq     25f
+        lwz     r3, LPPACA_YIELDCOUNT(r8)
+        addi    r3, r3, 1
+        stw     r3, LPPACA_YIELDCOUNT(r8)
+        li      r3, 1
+        stb     r3, VCPU_VPA_DIRTY(r9)
+25:
+        /* Save PMU registers if requested */
+        /* r8 and cr0.eq are live here */
+        li      r3, 1
+        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
+        mfspr   r4, SPRN_MMCR0          /* save MMCR0 */
+        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
+        mfspr   r6, SPRN_MMCRA
+BEGIN_FTR_SECTION
+        /* On P7, clear MMCRA in order to disable SDAR updates */
+        li      r7, 0
+        mtspr   SPRN_MMCRA, r7
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+        isync
+        beq     21f                     /* if no VPA, save PMU stuff anyway */
+        lbz     r7, LPPACA_PMCINUSE(r8)
+        cmpwi   r7, 0                   /* did they ask for PMU stuff to be saved? */
+        bne     21f
+        std     r3, VCPU_MMCR(r9)       /* if not, set saved MMCR0 to FC */
+        b       22f
+21:     mfspr   r5, SPRN_MMCR1
+        mfspr   r7, SPRN_SIAR
+        mfspr   r8, SPRN_SDAR
+        std     r4, VCPU_MMCR(r9)
+        std     r5, VCPU_MMCR + 8(r9)
+        std     r6, VCPU_MMCR + 16(r9)
+        std     r7, VCPU_SIAR(r9)
+        std     r8, VCPU_SDAR(r9)
+        mfspr   r3, SPRN_PMC1
+        mfspr   r4, SPRN_PMC2
+        mfspr   r5, SPRN_PMC3
+        mfspr   r6, SPRN_PMC4
+        mfspr   r7, SPRN_PMC5
+        mfspr   r8, SPRN_PMC6
+BEGIN_FTR_SECTION
+        mfspr   r10, SPRN_PMC7
+        mfspr   r11, SPRN_PMC8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+        stw     r3, VCPU_PMC(r9)
+        stw     r4, VCPU_PMC + 4(r9)
+        stw     r5, VCPU_PMC + 8(r9)
+        stw     r6, VCPU_PMC + 12(r9)
+        stw     r7, VCPU_PMC + 16(r9)
+        stw     r8, VCPU_PMC + 20(r9)
+BEGIN_FTR_SECTION
+        stw     r10, VCPU_PMC + 24(r9)
+        stw     r11, VCPU_PMC + 28(r9)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+BEGIN_FTR_SECTION
+        mfspr   r4, SPRN_MMCR2
+        mfspr   r5, SPRN_SIER
+        mfspr   r6, SPRN_SPMC1
+        mfspr   r7, SPRN_SPMC2
+        mfspr   r8, SPRN_MMCRS
+        std     r4, VCPU_MMCR + 24(r9)
+        std     r5, VCPU_SIER(r9)
+        stw     r6, VCPU_PMC + 24(r9)
+        stw     r7, VCPU_PMC + 28(r9)
+        std     r8, VCPU_MMCR + 32(r9)
+        lis     r4, 0x8000
+        mtspr   SPRN_MMCRS, r4
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+22:
         /* Clear out SLB */
         li      r5,0
         slbmte  r5,r5
         slbia
         ptesync
 
-hdec_soon:                      /* r9 = vcpu, r12 = trap, r13 = paca */
+hdec_soon:                      /* r12 = trap, r13 = paca */
 BEGIN_FTR_SECTION
         b       32f
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
@@ -1014,8 +1313,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
          */
         cmpwi   r3,0x100        /* Are we the first here? */
         bge     43f
-        cmpwi   r3,1            /* Are any other threads in the guest? */
-        ble     43f
         cmpwi   r12,BOOK3S_INTERRUPT_HV_DECREMENTER
         beq     40f
         li      r0,0
@@ -1026,7 +1323,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
          * doesn't wake CPUs up from nap.
          */
         lwz     r3,VCORE_NAPPING_THREADS(r5)
-        lwz     r4,VCPU_PTID(r9)
+        lbz     r4,HSTATE_PTID(r13)
         li      r0,1
         sld     r0,r0,r4
         andc.   r3,r3,r0                /* no sense IPI'ing ourselves */
@@ -1045,10 +1342,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         addi    r6,r6,PACA_SIZE
         bne     42b
 
+secondary_too_late:
         /* Secondary threads wait for primary to do partition switch */
-43:     ld      r4,VCPU_KVM(r9)         /* pointer to struct kvm */
-        ld      r5,HSTATE_KVM_VCORE(r13)
-        lwz     r3,VCPU_PTID(r9)
+43:     ld      r5,HSTATE_KVM_VCORE(r13)
+        ld      r4,VCORE_KVM(r5)        /* pointer to struct kvm */
+        lbz     r3,HSTATE_PTID(r13)
         cmpwi   r3,0
         beq     15f
         HMT_LOW
@@ -1076,6 +1374,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         mtspr   SPRN_LPID,r7
         isync
 
+BEGIN_FTR_SECTION
+        /* DPDES is shared between threads */
+        mfspr   r7, SPRN_DPDES
+        std     r7, VCORE_DPDES(r5)
+        /* clear DPDES so we don't get guest doorbells in the host */
+        li      r8, 0
+        mtspr   SPRN_DPDES, r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
         /* Subtract timebase offset from timebase */
         ld      r8,VCORE_TB_OFFSET(r5)
         cmpdi   r8,0
@@ -1113,7 +1420,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
          * We have to lock against concurrent tlbies, and
          * we have to flush the whole TLB.
          */
-32:     ld      r4,VCPU_KVM(r9)         /* pointer to struct kvm */
+32:     ld      r5,HSTATE_KVM_VCORE(r13)
+        ld      r4,VCORE_KVM(r5)        /* pointer to struct kvm */
 
         /* Take the guest's tlbie_lock */
 #ifdef __BIG_ENDIAN__
@@ -1203,6 +1511,56 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         add     r5,r5,r6
         std     r5,VCPU_DEC_EXPIRES(r9)
 
+BEGIN_FTR_SECTION
+        b       8f
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
+        mfmsr   r8
+        li      r0, 1
+        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
+        mtmsrd  r8
+
+        /* Save POWER8-specific registers */
+        mfspr   r5, SPRN_IAMR
+        mfspr   r6, SPRN_PSPB
+        mfspr   r7, SPRN_FSCR
+        std     r5, VCPU_IAMR(r9)
+        stw     r6, VCPU_PSPB(r9)
+        std     r7, VCPU_FSCR(r9)
+        mfspr   r5, SPRN_IC
+        mfspr   r6, SPRN_VTB
+        mfspr   r7, SPRN_TAR
+        std     r5, VCPU_IC(r9)
+        std     r6, VCPU_VTB(r9)
+        std     r7, VCPU_TAR(r9)
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        mfspr   r5, SPRN_TFHAR
+        mfspr   r6, SPRN_TFIAR
+        mfspr   r7, SPRN_TEXASR
+        std     r5, VCPU_TFHAR(r9)
+        std     r6, VCPU_TFIAR(r9)
+        std     r7, VCPU_TEXASR(r9)
+#endif
+        mfspr   r8, SPRN_EBBHR
+        std     r8, VCPU_EBBHR(r9)
+        mfspr   r5, SPRN_EBBRR
+        mfspr   r6, SPRN_BESCR
+        mfspr   r7, SPRN_CSIGR
+        mfspr   r8, SPRN_TACR
+        std     r5, VCPU_EBBRR(r9)
+        std     r6, VCPU_BESCR(r9)
+        std     r7, VCPU_CSIGR(r9)
+        std     r8, VCPU_TACR(r9)
+        mfspr   r5, SPRN_TCSCR
+        mfspr   r6, SPRN_ACOP
+        mfspr   r7, SPRN_PID
+        mfspr   r8, SPRN_WORT
+        std     r5, VCPU_TCSCR(r9)
+        std     r6, VCPU_ACOP(r9)
+        stw     r7, VCPU_GUEST_PID(r9)
+        std     r8, VCPU_WORT(r9)
+8:
+
         /* Save and reset AMR and UAMOR before turning on the MMU */
 BEGIN_FTR_SECTION
         mfspr   r5,SPRN_AMR
@@ -1217,130 +1575,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         li      r0, KVM_GUEST_MODE_NONE
         stb     r0, HSTATE_IN_GUEST(r13)
 
-        /* Switch DSCR back to host value */
-BEGIN_FTR_SECTION
-        mfspr   r8, SPRN_DSCR
-        ld      r7, HSTATE_DSCR(r13)
-        std     r8, VCPU_DSCR(r9)
-        mtspr   SPRN_DSCR, r7
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-
-        /* Save non-volatile GPRs */
-        std     r14, VCPU_GPR(R14)(r9)
-        std     r15, VCPU_GPR(R15)(r9)
-        std     r16, VCPU_GPR(R16)(r9)
-        std     r17, VCPU_GPR(R17)(r9)
-        std     r18, VCPU_GPR(R18)(r9)
-        std     r19, VCPU_GPR(R19)(r9)
-        std     r20, VCPU_GPR(R20)(r9)
-        std     r21, VCPU_GPR(R21)(r9)
-        std     r22, VCPU_GPR(R22)(r9)
-        std     r23, VCPU_GPR(R23)(r9)
-        std     r24, VCPU_GPR(R24)(r9)
-        std     r25, VCPU_GPR(R25)(r9)
-        std     r26, VCPU_GPR(R26)(r9)
-        std     r27, VCPU_GPR(R27)(r9)
-        std     r28, VCPU_GPR(R28)(r9)
-        std     r29, VCPU_GPR(R29)(r9)
-        std     r30, VCPU_GPR(R30)(r9)
-        std     r31, VCPU_GPR(R31)(r9)
-
-        /* Save SPRGs */
-        mfspr   r3, SPRN_SPRG0
-        mfspr   r4, SPRN_SPRG1
-        mfspr   r5, SPRN_SPRG2
-        mfspr   r6, SPRN_SPRG3
-        std     r3, VCPU_SPRG0(r9)
-        std     r4, VCPU_SPRG1(r9)
-        std     r5, VCPU_SPRG2(r9)
-        std     r6, VCPU_SPRG3(r9)
-
-        /* save FP state */
-        mr      r3, r9
-        bl      .kvmppc_save_fp
-
-        /* Increment yield count if they have a VPA */
-        ld      r8, VCPU_VPA(r9)        /* do they have a VPA? */
-        cmpdi   r8, 0
-        beq     25f
-        lwz     r3, LPPACA_YIELDCOUNT(r8)
-        addi    r3, r3, 1
-        stw     r3, LPPACA_YIELDCOUNT(r8)
-        li      r3, 1
-        stb     r3, VCPU_VPA_DIRTY(r9)
-25:
-        /* Save PMU registers if requested */
-        /* r8 and cr0.eq are live here */
-        li      r3, 1
-        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
-        mfspr   r4, SPRN_MMCR0          /* save MMCR0 */
-        mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable ints */
-        mfspr   r6, SPRN_MMCRA
-BEGIN_FTR_SECTION
-        /* On P7, clear MMCRA in order to disable SDAR updates */
-        li      r7, 0
-        mtspr   SPRN_MMCRA, r7
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-        isync
-        beq     21f                     /* if no VPA, save PMU stuff anyway */
-        lbz     r7, LPPACA_PMCINUSE(r8)
-        cmpwi   r7, 0                   /* did they ask for PMU stuff to be saved? */
-        bne     21f
-        std     r3, VCPU_MMCR(r9)       /* if not, set saved MMCR0 to FC */
-        b       22f
-21:     mfspr   r5, SPRN_MMCR1
-        mfspr   r7, SPRN_SIAR
-        mfspr   r8, SPRN_SDAR
-        std     r4, VCPU_MMCR(r9)
-        std     r5, VCPU_MMCR + 8(r9)
-        std     r6, VCPU_MMCR + 16(r9)
-        std     r7, VCPU_SIAR(r9)
-        std     r8, VCPU_SDAR(r9)
-        mfspr   r3, SPRN_PMC1
-        mfspr   r4, SPRN_PMC2
-        mfspr   r5, SPRN_PMC3
-        mfspr   r6, SPRN_PMC4
-        mfspr   r7, SPRN_PMC5
-        mfspr   r8, SPRN_PMC6
-BEGIN_FTR_SECTION
-        mfspr   r10, SPRN_PMC7
-        mfspr   r11, SPRN_PMC8
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-        stw     r3, VCPU_PMC(r9)
-        stw     r4, VCPU_PMC + 4(r9)
-        stw     r5, VCPU_PMC + 8(r9)
-        stw     r6, VCPU_PMC + 12(r9)
-        stw     r7, VCPU_PMC + 16(r9)
-        stw     r8, VCPU_PMC + 20(r9)
-BEGIN_FTR_SECTION
-        stw     r10, VCPU_PMC + 24(r9)
-        stw     r11, VCPU_PMC + 28(r9)
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-22:
         ld      r0, 112+PPC_LR_STKOFF(r1)
         addi    r1, r1, 112
         mtlr    r0
         blr
-secondary_too_late:
-        ld      r5,HSTATE_KVM_VCORE(r13)
-        HMT_LOW
-13:     lbz     r3,VCORE_IN_GUEST(r5)
-        cmpwi   r3,0
-        bne     13b
-        HMT_MEDIUM
-        li      r0, KVM_GUEST_MODE_NONE
-        stb     r0, HSTATE_IN_GUEST(r13)
-        ld      r11,PACA_SLBSHADOWPTR(r13)
-
-        .rept   SLB_NUM_BOLTED
-        ld      r5,SLBSHADOW_SAVEAREA(r11)
-        ld      r6,SLBSHADOW_SAVEAREA+8(r11)
-        andis.  r7,r5,SLB_ESID_V@h
-        beq     1f
-        slbmte  r6,r5
-1:      addi    r11,r11,16
-        .endr
-        b       22b
 
 /*
  * Check whether an HDSI is an HPTE not found fault or something else.
@@ -1386,8 +1624,7 @@ kvmppc_hdsi:
         mtspr   SPRN_SRR0, r10
         mtspr   SPRN_SRR1, r11
         li      r10, BOOK3S_INTERRUPT_DATA_STORAGE
-        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11, r11, 63
+        ld      r11, VCPU_INTR_MSR(r9)
 fast_interrupt_c_return:
 6:      ld      r7, VCPU_CTR(r9)
         lwz     r8, VCPU_XER(r9)
@@ -1456,8 +1693,7 @@ kvmppc_hisi:
 1:      mtspr   SPRN_SRR0, r10
         mtspr   SPRN_SRR1, r11
         li      r10, BOOK3S_INTERRUPT_INST_STORAGE
-        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11, r11, 63
+        ld      r11, VCPU_INTR_MSR(r9)
         b       fast_interrupt_c_return
 
 3:      ld      r6, VCPU_KVM(r9)        /* not relocated, use VRMA */
@@ -1474,7 +1710,8 @@ kvmppc_hisi:
 hcall_try_real_mode:
         ld      r3,VCPU_GPR(R3)(r9)
         andi.   r0,r11,MSR_PR
-        bne     guest_exit_cont
+        /* sc 1 from userspace - reflect to guest syscall */
+        bne     sc_1_fast_return
         clrrdi  r3,r3,2
         cmpldi  r3,hcall_real_table_end - hcall_real_table
         bge     guest_exit_cont
@@ -1495,6 +1732,14 @@ hcall_try_real_mode:
         ld      r11,VCPU_MSR(r4)
         b       fast_guest_return
 
+sc_1_fast_return:
+        mtspr   SPRN_SRR0,r10
+        mtspr   SPRN_SRR1,r11
+        li      r10, BOOK3S_INTERRUPT_SYSCALL
+        ld      r11, VCPU_INTR_MSR(r9)
+        mr      r4,r9
+        b       fast_guest_return
+
         /* We've attempted a real mode hcall, but it's punted it back
          * to userspace.  We need to restore some clobbered volatiles
          * before resuming the pass-it-to-qemu path */
@@ -1588,14 +1833,34 @@ hcall_real_table:
         .long   0               /* 0x11c */
         .long   0               /* 0x120 */
         .long   .kvmppc_h_bulk_remove - hcall_real_table
+        .long   0               /* 0x128 */
+        .long   0               /* 0x12c */
+        .long   0               /* 0x130 */
+        .long   .kvmppc_h_set_xdabr - hcall_real_table
 hcall_real_table_end:
 
 ignore_hdec:
         mr      r4,r9
         b       fast_guest_return
 
+_GLOBAL(kvmppc_h_set_xdabr)
+        andi.   r0, r5, DABRX_USER | DABRX_KERNEL
+        beq     6f
+        li      r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
+        andc.   r0, r5, r0
+        beq     3f
+6:      li      r3, H_PARAMETER
+        blr
+
 _GLOBAL(kvmppc_h_set_dabr)
+        li      r5, DABRX_USER | DABRX_KERNEL
+3:
+BEGIN_FTR_SECTION
+        b       2f
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
         std     r4,VCPU_DABR(r3)
+        stw     r5, VCPU_DABRX(r3)
+        mtspr   SPRN_DABRX, r5
         /* Work around P7 bug where DABR can get corrupted on mtspr */
 1:      mtspr   SPRN_DABR,r4
         mfspr   r5, SPRN_DABR
@@ -1605,6 +1870,17 @@ _GLOBAL(kvmppc_h_set_dabr)
         li      r3,0
         blr
 
+        /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
+2:      rlwimi  r5, r4, 5, DAWRX_DR | DAWRX_DW
+        rlwimi  r5, r4, 1, DAWRX_WT
+        clrrdi  r4, r4, 3
+        std     r4, VCPU_DAWR(r3)
+        std     r5, VCPU_DAWRX(r3)
+        mtspr   SPRN_DAWR, r4
+        mtspr   SPRN_DAWRX, r5
+        li      r3, 0
+        blr
+
 _GLOBAL(kvmppc_h_cede)
         ori     r11,r11,MSR_EE
         std     r11,VCPU_MSR(r3)
@@ -1628,7 +1904,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
          * up to the host.
          */
         ld      r5,HSTATE_KVM_VCORE(r13)
-        lwz     r6,VCPU_PTID(r3)
+        lbz     r6,HSTATE_PTID(r13)
         lwz     r8,VCORE_ENTRY_EXIT(r5)
         clrldi  r8,r8,56
         li      r0,1
@@ -1643,9 +1919,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         bne     31b
         /* order napping_threads update vs testing entry_exit_count */
         isync
-        li      r0,1
+        li      r0,NAPPING_CEDE
         stb     r0,HSTATE_NAPPING(r13)
-        mr      r4,r3
         lwz     r7,VCORE_ENTRY_EXIT(r5)
         cmpwi   r7,0x100
         bge     33f             /* another thread already exiting */
@@ -1677,16 +1952,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         std     r31, VCPU_GPR(R31)(r3)
 
         /* save FP state */
-        bl      .kvmppc_save_fp
+        bl      kvmppc_save_fp
 
         /*
-         * Take a nap until a decrementer or external interrupt occurs,
-         * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
+         * Take a nap until a decrementer or external or doobell interrupt
+         * occurs, with PECE1, PECE0 and PECEDP set in LPCR
          */
         li      r0,1
         stb     r0,HSTATE_HWTHREAD_REQ(r13)
         mfspr   r5,SPRN_LPCR
         ori     r5,r5,LPCR_PECE0 | LPCR_PECE1
+BEGIN_FTR_SECTION
+        oris    r5,r5,LPCR_PECEDP@h
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
         mtspr   SPRN_LPCR,r5
         isync
         li      r0, 0
@@ -1698,6 +1976,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         nap
         b       .
 
+33:     mr      r4, r3
+        li      r3, 0
+        li      r12, 0
+        b       34f
+
 kvm_end_cede:
         /* get vcpu pointer */
         ld      r4, HSTATE_KVM_VCPU(r13)
@@ -1727,12 +2010,15 @@ kvm_end_cede:
         ld      r29, VCPU_GPR(R29)(r4)
         ld      r30, VCPU_GPR(R30)(r4)
         ld      r31, VCPU_GPR(R31)(r4)
+ 
+        /* Check the wake reason in SRR1 to see why we got here */
+        bl      kvmppc_check_wake_reason
 
         /* clear our bit in vcore->napping_threads */
-33:     ld      r5,HSTATE_KVM_VCORE(r13)
-        lwz     r3,VCPU_PTID(r4)
+34:     ld      r5,HSTATE_KVM_VCORE(r13)
+        lbz     r7,HSTATE_PTID(r13)
         li      r0,1
-        sld     r0,r0,r3
+        sld     r0,r0,r7
         addi    r6,r5,VCORE_NAPPING_THREADS
 32:     lwarx   r7,0,r6
         andc    r7,r7,r0
@@ -1741,23 +2027,18 @@ kvm_end_cede:
         li      r0,0
         stb     r0,HSTATE_NAPPING(r13)
 
-        /* Check the wake reason in SRR1 to see why we got here */
-        mfspr   r3, SPRN_SRR1
-        rlwinm  r3, r3, 44-31, 0x7      /* extract wake reason field */
-        cmpwi   r3, 4                   /* was it an external interrupt? */
-        li      r12, BOOK3S_INTERRUPT_EXTERNAL
+        /* See if the wake reason means we need to exit */
+        stw     r12, VCPU_TRAP(r4)
         mr      r9, r4
-        ld      r10, VCPU_PC(r9)
-        ld      r11, VCPU_MSR(r9)
-        beq     do_ext_interrupt        /* if so */
+        cmpdi   r3, 0
+        bgt     guest_exit_cont
 
         /* see if any other thread is already exiting */
         lwz     r0,VCORE_ENTRY_EXIT(r5)
         cmpwi   r0,0x100
-        blt     kvmppc_cede_reentry     /* if not go back to guest */
+        bge     guest_exit_cont
 
-        /* some threads are exiting, so go to the guest exit path */
-        b       hcall_real_fallback
+        b       kvmppc_cede_reentry     /* if not go back to guest */
 
         /* cede when already previously prodded case */
 kvm_cede_prodded:
@@ -1783,11 +2064,48 @@ machine_check_realmode:
         beq     mc_cont
         /* If not, deliver a machine check.  SRR0/1 are already set */
         li      r10, BOOK3S_INTERRUPT_MACHINE_CHECK
-        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11, r11, 63
+        ld      r11, VCPU_INTR_MSR(r9)
         b       fast_interrupt_c_return
 
 /*
+ * Check the reason we woke from nap, and take appropriate action.
+ * Returns:
+ *      0 if nothing needs to be done
+ *      1 if something happened that needs to be handled by the host
+ *      -1 if there was a guest wakeup (IPI)
+ *
+ * Also sets r12 to the interrupt vector for any interrupt that needs
+ * to be handled now by the host (0x500 for external interrupt), or zero.
+ */
+kvmppc_check_wake_reason:
+        mfspr   r6, SPRN_SRR1
+BEGIN_FTR_SECTION
+        rlwinm  r6, r6, 45-31, 0xf      /* extract wake reason field (P8) */
+FTR_SECTION_ELSE
+        rlwinm  r6, r6, 45-31, 0xe      /* P7 wake reason field is 3 bits */
+ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
+        cmpwi   r6, 8                   /* was it an external interrupt? */
+        li      r12, BOOK3S_INTERRUPT_EXTERNAL
+        beq     kvmppc_read_intr        /* if so, see what it was */
+        li      r3, 0
+        li      r12, 0
+        cmpwi   r6, 6                   /* was it the decrementer? */
+        beq     0f
+BEGIN_FTR_SECTION
+        cmpwi   r6, 5                   /* privileged doorbell? */
+        beq     0f
+        cmpwi   r6, 3                   /* hypervisor doorbell? */
+        beq     3f
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+        li      r3, 1                   /* anything else, return 1 */
+0:      blr
+
+        /* hypervisor doorbell */
+3:      li      r12, BOOK3S_INTERRUPT_H_DOORBELL
+        li      r3, 1
+        blr
+
+/*
  * Determine what sort of external interrupt is pending (if any).
  * Returns:
  *      0 if no interrupt is pending
@@ -1818,7 +2136,6 @@ kvmppc_read_intr:
          * interrupts directly to the guest
          */
         cmpwi   r3, XICS_IPI            /* if there is, is it an IPI? */
-        li      r3, 1
         bne     42f
 
         /* It's an IPI, clear the MFRR and EOI it */
@@ -1844,19 +2161,25 @@ kvmppc_read_intr:
          * before exit, it will be picked up by the host ICP driver
          */
         stw     r0, HSTATE_SAVED_XIRR(r13)
+        li      r3, 1
         b       1b
 
 43:     /* We raced with the host, we need to resend that IPI, bummer */
         li      r0, IPI_PRIORITY
         stbcix  r0, r6, r8              /* set the IPI */
         sync
+        li      r3, 1
         b       1b
 
 /*
  * Save away FP, VMX and VSX registers.
  * r3 = vcpu pointer
+ * N.B. r30 and r31 are volatile across this function,
+ * thus it is not callable from C.
  */
-_GLOBAL(kvmppc_save_fp)
+kvmppc_save_fp:
+        mflr    r30
+        mr      r31,r3
         mfmsr   r5
         ori     r8,r5,MSR_FP
 #ifdef CONFIG_ALTIVEC
@@ -1871,42 +2194,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif
         mtmsrd  r8
         isync
-#ifdef CONFIG_VSX
-BEGIN_FTR_SECTION
-        reg = 0
-        .rept   32
-        li      r6,reg*16+VCPU_VSRS
-        STXVD2X(reg,R6,R3)
-        reg = reg + 1
-        .endr
-FTR_SECTION_ELSE
-#endif
-        reg = 0
-        .rept   32
-        stfd    reg,reg*8+VCPU_FPRS(r3)
-        reg = reg + 1
-        .endr
-#ifdef CONFIG_VSX
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
-#endif
-        mffs    fr0
-        stfd    fr0,VCPU_FPSCR(r3)
-
+        addi    r3,r3,VCPU_FPRS
+        bl      .store_fp_state
 #ifdef CONFIG_ALTIVEC
 BEGIN_FTR_SECTION
-        reg = 0
-        .rept   32
-        li      r6,reg*16+VCPU_VRS
-        stvx    reg,r6,r3
-        reg = reg + 1
-        .endr
-        mfvscr  vr0
-        li      r6,VCPU_VSCR
-        stvx    vr0,r6,r3
+        addi    r3,r31,VCPU_VRS
+        bl      .store_vr_state
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
         mfspr   r6,SPRN_VRSAVE
         stw     r6,VCPU_VRSAVE(r3)
+        mtlr    r30
         mtmsrd  r5
         isync
         blr
@@ -1914,9 +2212,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 /*
  * Load up FP, VMX and VSX registers
  * r4 = vcpu pointer
+ * N.B. r30 and r31 are volatile across this function,
+ * thus it is not callable from C.
  */
-        .globl  kvmppc_load_fp
 kvmppc_load_fp:
+        mflr    r30
+        mr      r31,r4
         mfmsr   r9
         ori     r8,r9,MSR_FP
 #ifdef CONFIG_ALTIVEC
@@ -1931,42 +2232,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif
         mtmsrd  r8
         isync
-        lfd     fr0,VCPU_FPSCR(r4)
-        MTFSF_L(fr0)
-#ifdef CONFIG_VSX
-BEGIN_FTR_SECTION
-        reg = 0
-        .rept   32
-        li      r7,reg*16+VCPU_VSRS
-        LXVD2X(reg,R7,R4)
-        reg = reg + 1
-        .endr
-FTR_SECTION_ELSE
-#endif
-        reg = 0
-        .rept   32
-        lfd     reg,reg*8+VCPU_FPRS(r4)
-        reg = reg + 1
-        .endr
-#ifdef CONFIG_VSX
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
-#endif
-
+        addi    r3,r4,VCPU_FPRS
+        bl      .load_fp_state
 #ifdef CONFIG_ALTIVEC
 BEGIN_FTR_SECTION
-        li      r7,VCPU_VSCR
-        lvx     vr0,r7,r4
-        mtvscr  vr0
-        reg = 0
-        .rept   32
-        li      r7,reg*16+VCPU_VRS
-        lvx     reg,r7,r4
-        reg = reg + 1
-        .endr
+        addi    r3,r31,VCPU_VRS
+        bl      .load_vr_state
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
         lwz     r7,VCPU_VRSAVE(r4)
         mtspr   SPRN_VRSAVE,r7
+        mtlr    r30
+        mr      r4,r31
         blr
 
 /*
diff --git a/arch/powerpc/kvm/book3s_paired_singles.c b/arch/powerpc/kvm/book3s_paired_singles.c
index a59a25a13218..c1abd95063f4 100644
--- a/arch/powerpc/kvm/book3s_paired_singles.c
+++ b/arch/powerpc/kvm/book3s_paired_singles.c
@@ -160,7 +160,7 @@
 
 static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt)
 {
-        kvm_cvt_df(&vcpu->arch.fpr[rt], &vcpu->arch.qpr[rt]);
+        kvm_cvt_df(&VCPU_FPR(vcpu, rt), &vcpu->arch.qpr[rt]);
 }
 
 static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store)
@@ -207,11 +207,11 @@ static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         /* put in registers */
         switch (ls_type) {
         case FPU_LS_SINGLE:
-                kvm_cvt_fd((u32*)tmp, &vcpu->arch.fpr[rs]);
+                kvm_cvt_fd((u32*)tmp, &VCPU_FPR(vcpu, rs));
                 vcpu->arch.qpr[rs] = *((u32*)tmp);
                 break;
         case FPU_LS_DOUBLE:
-                vcpu->arch.fpr[rs] = *((u64*)tmp);
+                VCPU_FPR(vcpu, rs) = *((u64*)tmp);
                 break;
         }
 
@@ -233,18 +233,18 @@ static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
         switch (ls_type) {
         case FPU_LS_SINGLE:
-                kvm_cvt_df(&vcpu->arch.fpr[rs], (u32*)tmp);
+                kvm_cvt_df(&VCPU_FPR(vcpu, rs), (u32*)tmp);
                 val = *((u32*)tmp);
                 len = sizeof(u32);
                 break;
         case FPU_LS_SINGLE_LOW:
-                *((u32*)tmp) = vcpu->arch.fpr[rs];
-                val = vcpu->arch.fpr[rs] & 0xffffffff;
+                *((u32*)tmp) = VCPU_FPR(vcpu, rs);
+                val = VCPU_FPR(vcpu, rs) & 0xffffffff;
                 len = sizeof(u32);
                 break;
         case FPU_LS_DOUBLE:
-                *((u64*)tmp) = vcpu->arch.fpr[rs];
-                val = vcpu->arch.fpr[rs];
+                *((u64*)tmp) = VCPU_FPR(vcpu, rs);
+                val = VCPU_FPR(vcpu, rs);
                 len = sizeof(u64);
                 break;
         default:
@@ -301,7 +301,7 @@ static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         emulated = EMULATE_DONE;
 
         /* put in registers */
-        kvm_cvt_fd(&tmp[0], &vcpu->arch.fpr[rs]);
+        kvm_cvt_fd(&tmp[0], &VCPU_FPR(vcpu, rs));
         vcpu->arch.qpr[rs] = tmp[1];
 
         dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0],
@@ -319,7 +319,7 @@ static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
         u32 tmp[2];
         int len = w ? sizeof(u32) : sizeof(u64);
 
-        kvm_cvt_df(&vcpu->arch.fpr[rs], &tmp[0]);
+        kvm_cvt_df(&VCPU_FPR(vcpu, rs), &tmp[0]);
         tmp[1] = vcpu->arch.qpr[rs];
 
         r = kvmppc_st(vcpu, &addr, len, tmp, true);
@@ -512,7 +512,6 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
                                                  u32 *src2, u32 *src3))
 {
         u32 *qpr = vcpu->arch.qpr;
-        u64 *fpr = vcpu->arch.fpr;
         u32 ps0_out;
         u32 ps0_in1, ps0_in2, ps0_in3;
         u32 ps1_in1, ps1_in2, ps1_in3;
@@ -521,20 +520,20 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
         WARN_ON(rc);
 
         /* PS0 */
-        kvm_cvt_df(&fpr[reg_in1], &ps0_in1);
-        kvm_cvt_df(&fpr[reg_in2], &ps0_in2);
-        kvm_cvt_df(&fpr[reg_in3], &ps0_in3);
+        kvm_cvt_df(&VCPU_FPR(vcpu, reg_in1), &ps0_in1);
+        kvm_cvt_df(&VCPU_FPR(vcpu, reg_in2), &ps0_in2);
+        kvm_cvt_df(&VCPU_FPR(vcpu, reg_in3), &ps0_in3);
 
         if (scalar & SCALAR_LOW)
                 ps0_in2 = qpr[reg_in2];
 
-        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
+        func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
 
         dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
                           ps0_in1, ps0_in2, ps0_in3, ps0_out);
 
         if (!(scalar & SCALAR_NO_PS0))
-                kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
+                kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
 
         /* PS1 */
         ps1_in1 = qpr[reg_in1];
@@ -545,7 +544,7 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
                 ps1_in2 = ps0_in2;
 
         if (!(scalar & SCALAR_NO_PS1))
-                func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
+                func(&vcpu->arch.fp.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
 
         dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
                           ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]);
@@ -561,7 +560,6 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
                                                  u32 *src2))
 {
         u32 *qpr = vcpu->arch.qpr;
-        u64 *fpr = vcpu->arch.fpr;
         u32 ps0_out;
         u32 ps0_in1, ps0_in2;
         u32 ps1_out;
@@ -571,20 +569,20 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
         WARN_ON(rc);
 
         /* PS0 */
-        kvm_cvt_df(&fpr[reg_in1], &ps0_in1);
+        kvm_cvt_df(&VCPU_FPR(vcpu, reg_in1), &ps0_in1);
 
         if (scalar & SCALAR_LOW)
                 ps0_in2 = qpr[reg_in2];
         else
-                kvm_cvt_df(&fpr[reg_in2], &ps0_in2);
+                kvm_cvt_df(&VCPU_FPR(vcpu, reg_in2), &ps0_in2);
 
-        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
+        func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
 
         if (!(scalar & SCALAR_NO_PS0)) {
                 dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n",
                                   ps0_in1, ps0_in2, ps0_out);
 
-                kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
+                kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
         }
 
         /* PS1 */
@@ -594,7 +592,7 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
         if (scalar & SCALAR_HIGH)
                 ps1_in2 = ps0_in2;
 
-        func(&vcpu->arch.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
+        func(&vcpu->arch.fp.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
 
         if (!(scalar & SCALAR_NO_PS1)) {
                 qpr[reg_out] = ps1_out;
@@ -612,7 +610,6 @@ static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
                                                  u32 *dst, u32 *src1))
 {
         u32 *qpr = vcpu->arch.qpr;
-        u64 *fpr = vcpu->arch.fpr;
         u32 ps0_out, ps0_in;
         u32 ps1_in;
 
@@ -620,17 +617,17 @@ static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
         WARN_ON(rc);
 
         /* PS0 */
-        kvm_cvt_df(&fpr[reg_in], &ps0_in);
-        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in);
+        kvm_cvt_df(&VCPU_FPR(vcpu, reg_in), &ps0_in);
+        func(&vcpu->arch.fp.fpscr, &ps0_out, &ps0_in);
 
         dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n",
                           ps0_in, ps0_out);
 
-        kvm_cvt_fd(&ps0_out, &fpr[reg_out]);
+        kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out));
 
         /* PS1 */
         ps1_in = qpr[reg_in];
-        func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in);
+        func(&vcpu->arch.fp.fpscr, &qpr[reg_out], &ps1_in);
 
         dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n",
                           ps1_in, qpr[reg_out]);
@@ -649,10 +646,10 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
         int ax_rc = inst_get_field(inst, 21, 25);
         short full_d = inst_get_field(inst, 16, 31);
 
-        u64 *fpr_d = &vcpu->arch.fpr[ax_rd];
-        u64 *fpr_a = &vcpu->arch.fpr[ax_ra];
-        u64 *fpr_b = &vcpu->arch.fpr[ax_rb];
-        u64 *fpr_c = &vcpu->arch.fpr[ax_rc];
+        u64 *fpr_d = &VCPU_FPR(vcpu, ax_rd);
+        u64 *fpr_a = &VCPU_FPR(vcpu, ax_ra);
+        u64 *fpr_b = &VCPU_FPR(vcpu, ax_rb);
+        u64 *fpr_c = &VCPU_FPR(vcpu, ax_rc);
 
         bool rcomp = (inst & 1) ? true : false;
         u32 cr = kvmppc_get_cr(vcpu);
@@ -674,11 +671,11 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
         /* Do we need to clear FE0 / FE1 here? Don't think so. */
 
 #ifdef DEBUG
-        for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
+        for (i = 0; i < ARRAY_SIZE(vcpu->arch.fp.fpr); i++) {
                 u32 f;
-                kvm_cvt_df(&vcpu->arch.fpr[i], &f);
+                kvm_cvt_df(&VCPU_FPR(vcpu, i), &f);
                 dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx    QPR[%d] = 0x%x\n",
-                        i, f, vcpu->arch.fpr[i], i, vcpu->arch.qpr[i]);
+                        i, f, VCPU_FPR(vcpu, i), i, vcpu->arch.qpr[i]);
         }
 #endif
 
@@ -764,8 +761,8 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         break;
                 }
                 case OP_4X_PS_NEG:
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
-                        vcpu->arch.fpr[ax_rd] ^= 0x8000000000000000ULL;
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
+                        VCPU_FPR(vcpu, ax_rd) ^= 0x8000000000000000ULL;
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         vcpu->arch.qpr[ax_rd] ^= 0x80000000;
                         break;
@@ -775,7 +772,7 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         break;
                 case OP_4X_PS_MR:
                         WARN_ON(rcomp);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         break;
                 case OP_4X_PS_CMPO1:
@@ -784,44 +781,44 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         break;
                 case OP_4X_PS_NABS:
                         WARN_ON(rcomp);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
-                        vcpu->arch.fpr[ax_rd] |= 0x8000000000000000ULL;
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
+                        VCPU_FPR(vcpu, ax_rd) |= 0x8000000000000000ULL;
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         vcpu->arch.qpr[ax_rd] |= 0x80000000;
                         break;
                 case OP_4X_PS_ABS:
                         WARN_ON(rcomp);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
-                        vcpu->arch.fpr[ax_rd] &= ~0x8000000000000000ULL;
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rb);
+                        VCPU_FPR(vcpu, ax_rd) &= ~0x8000000000000000ULL;
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         vcpu->arch.qpr[ax_rd] &= ~0x80000000;
                         break;
                 case OP_4X_PS_MERGE00:
                         WARN_ON(rcomp);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
-                        /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
-                        kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_ra);
+                        /* vcpu->arch.qpr[ax_rd] = VCPU_FPR(vcpu, ax_rb); */
+                        kvm_cvt_df(&VCPU_FPR(vcpu, ax_rb),
                                    &vcpu->arch.qpr[ax_rd]);
                         break;
                 case OP_4X_PS_MERGE01:
                         WARN_ON(rcomp);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_ra);
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         break;
                 case OP_4X_PS_MERGE10:
                         WARN_ON(rcomp);
-                        /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
+                        /* VCPU_FPR(vcpu, ax_rd) = vcpu->arch.qpr[ax_ra]; */
                         kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
-                                   &vcpu->arch.fpr[ax_rd]);
-                        /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
-                        kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
+                                   &VCPU_FPR(vcpu, ax_rd));
+                        /* vcpu->arch.qpr[ax_rd] = VCPU_FPR(vcpu, ax_rb); */
+                        kvm_cvt_df(&VCPU_FPR(vcpu, ax_rb),
                                    &vcpu->arch.qpr[ax_rd]);
                         break;
                 case OP_4X_PS_MERGE11:
                         WARN_ON(rcomp);
-                        /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
+                        /* VCPU_FPR(vcpu, ax_rd) = vcpu->arch.qpr[ax_ra]; */
                         kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
-                                   &vcpu->arch.fpr[ax_rd]);
+                                   &VCPU_FPR(vcpu, ax_rd));
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         break;
                 }
@@ -856,7 +853,7 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 case OP_4A_PS_SUM1:
                         emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
                                         ax_rb, ax_ra, SCALAR_NO_PS0 | SCALAR_HIGH, fps_fadds);
-                        vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rc];
+                        VCPU_FPR(vcpu, ax_rd) = VCPU_FPR(vcpu, ax_rc);
                         break;
                 case OP_4A_PS_SUM0:
                         emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
@@ -1106,45 +1103,45 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
         case 59:
                 switch (inst_get_field(inst, 21, 30)) {
                 case OP_59_FADDS:
-                        fpd_fadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FSUBS:
-                        fpd_fsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FDIVS:
-                        fpd_fdivs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fdivs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FRES:
-                        fpd_fres(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fres(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FRSQRTES:
-                        fpd_frsqrtes(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_frsqrtes(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 }
                 switch (inst_get_field(inst, 26, 30)) {
                 case OP_59_FMULS:
-                        fpd_fmuls(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
+                        fpd_fmuls(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FMSUBS:
-                        fpd_fmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fmsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FMADDS:
-                        fpd_fmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fmadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FNMSUBS:
-                        fpd_fnmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fnmsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_59_FNMADDS:
-                        fpd_fnmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fnmadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 }
@@ -1159,12 +1156,12 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         break;
                 case OP_63_MFFS:
                         /* XXX missing CR */
-                        *fpr_d = vcpu->arch.fpscr;
+                        *fpr_d = vcpu->arch.fp.fpscr;
                         break;
                 case OP_63_MTFSF:
                         /* XXX missing fm bits */
                         /* XXX missing CR */
-                        vcpu->arch.fpscr = *fpr_b;
+                        vcpu->arch.fp.fpscr = *fpr_b;
                         break;
                 case OP_63_FCMPU:
                 {
@@ -1172,7 +1169,7 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         u32 cr0_mask = 0xf0000000;
                         u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
 
-                        fpd_fcmpu(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
+                        fpd_fcmpu(&vcpu->arch.fp.fpscr, &tmp_cr, fpr_a, fpr_b);
                         cr &= ~(cr0_mask >> cr_shift);
                         cr |= (cr & cr0_mask) >> cr_shift;
                         break;
@@ -1183,40 +1180,40 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         u32 cr0_mask = 0xf0000000;
                         u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
 
-                        fpd_fcmpo(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
+                        fpd_fcmpo(&vcpu->arch.fp.fpscr, &tmp_cr, fpr_a, fpr_b);
                         cr &= ~(cr0_mask >> cr_shift);
                         cr |= (cr & cr0_mask) >> cr_shift;
                         break;
                 }
                 case OP_63_FNEG:
-                        fpd_fneg(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fneg(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         break;
                 case OP_63_FMR:
                         *fpr_d = *fpr_b;
                         break;
                 case OP_63_FABS:
-                        fpd_fabs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fabs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         break;
                 case OP_63_FCPSGN:
-                        fpd_fcpsgn(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fcpsgn(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         break;
                 case OP_63_FDIV:
-                        fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fdiv(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         break;
                 case OP_63_FADD:
-                        fpd_fadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         break;
                 case OP_63_FSUB:
-                        fpd_fsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
+                        fpd_fsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b);
                         break;
                 case OP_63_FCTIW:
-                        fpd_fctiw(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fctiw(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         break;
                 case OP_63_FCTIWZ:
-                        fpd_fctiwz(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fctiwz(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         break;
                 case OP_63_FRSP:
-                        fpd_frsp(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_frsp(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         kvmppc_sync_qpr(vcpu, ax_rd);
                         break;
                 case OP_63_FRSQRTE:
@@ -1224,39 +1221,39 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         double one = 1.0f;
 
                         /* fD = sqrt(fB) */
-                        fpd_fsqrt(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
+                        fpd_fsqrt(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b);
                         /* fD = 1.0f / fD */
-                        fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, (u64*)&one, fpr_d);
+                        fpd_fdiv(&vcpu->arch.fp.fpscr, &cr, fpr_d, (u64*)&one, fpr_d);
                         break;
                 }
                 }
                 switch (inst_get_field(inst, 26, 30)) {
                 case OP_63_FMUL:
-                        fpd_fmul(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
+                        fpd_fmul(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c);
                         break;
                 case OP_63_FSEL:
-                        fpd_fsel(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fsel(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         break;
                 case OP_63_FMSUB:
-                        fpd_fmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fmsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         break;
                 case OP_63_FMADD:
-                        fpd_fmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fmadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         break;
                 case OP_63_FNMSUB:
-                        fpd_fnmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fnmsub(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         break;
                 case OP_63_FNMADD:
-                        fpd_fnmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
+                        fpd_fnmadd(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
                         break;
                 }
                 break;
         }
 
 #ifdef DEBUG
-        for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
+        for (i = 0; i < ARRAY_SIZE(vcpu->arch.fp.fpr); i++) {
                 u32 f;
-                kvm_cvt_df(&vcpu->arch.fpr[i], &f);
+                kvm_cvt_df(&VCPU_FPR(vcpu, i), &f);
                 dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f);
         }
 #endif
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 5b9e9063cfaf..c5c052a9729c 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -41,6 +41,7 @@
 #include <linux/vmalloc.h>
 #include <linux/highmem.h>
 #include <linux/module.h>
+#include <linux/miscdevice.h>
 
 #include "book3s.h"
 
@@ -566,12 +567,6 @@ static inline int get_fpr_index(int i)
 void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr)
 {
         struct thread_struct *t = &current->thread;
-        u64 *vcpu_fpr = vcpu->arch.fpr;
-#ifdef CONFIG_VSX
-        u64 *vcpu_vsx = vcpu->arch.vsr;
-#endif
-        u64 *thread_fpr = &t->fp_state.fpr[0][0];
-        int i;
 
         /*
          * VSX instructions can access FP and vector registers, so if
@@ -594,26 +589,16 @@ void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr)
                  * both the traditional FP registers and the added VSX
                  * registers into thread.fp_state.fpr[].
                  */
-                if (current->thread.regs->msr & MSR_FP)
+                if (t->regs->msr & MSR_FP)
                         giveup_fpu(current);
-                for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
-                        vcpu_fpr[i] = thread_fpr[get_fpr_index(i)];
-
-                vcpu->arch.fpscr = t->fp_state.fpscr;
-
-#ifdef CONFIG_VSX
-                if (cpu_has_feature(CPU_FTR_VSX))
-                        for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++)
-                                vcpu_vsx[i] = thread_fpr[get_fpr_index(i) + 1];
-#endif
+                t->fp_save_area = NULL;
         }
 
 #ifdef CONFIG_ALTIVEC
         if (msr & MSR_VEC) {
                 if (current->thread.regs->msr & MSR_VEC)
                         giveup_altivec(current);
-                memcpy(vcpu->arch.vr, t->vr_state.vr, sizeof(vcpu->arch.vr));
-                vcpu->arch.vscr = t->vr_state.vscr;
+                t->vr_save_area = NULL;
         }
 #endif
 
@@ -661,12 +646,6 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
                              ulong msr)
 {
         struct thread_struct *t = &current->thread;
-        u64 *vcpu_fpr = vcpu->arch.fpr;
-#ifdef CONFIG_VSX
-        u64 *vcpu_vsx = vcpu->arch.vsr;
-#endif
-        u64 *thread_fpr = &t->fp_state.fpr[0][0];
-        int i;
 
         /* When we have paired singles, we emulate in software */
         if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)
@@ -704,27 +683,20 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
 #endif
 
         if (msr & MSR_FP) {
-                for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
-                        thread_fpr[get_fpr_index(i)] = vcpu_fpr[i];
-#ifdef CONFIG_VSX
-                for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++)
-                        thread_fpr[get_fpr_index(i) + 1] = vcpu_vsx[i];
-#endif
-                t->fp_state.fpscr = vcpu->arch.fpscr;
-                t->fpexc_mode = 0;
-                kvmppc_load_up_fpu();
+                enable_kernel_fp();
+                load_fp_state(&vcpu->arch.fp);
+                t->fp_save_area = &vcpu->arch.fp;
         }
 
         if (msr & MSR_VEC) {
 #ifdef CONFIG_ALTIVEC
-                memcpy(t->vr_state.vr, vcpu->arch.vr, sizeof(vcpu->arch.vr));
-                t->vr_state.vscr = vcpu->arch.vscr;
-                t->vrsave = -1;
-                kvmppc_load_up_altivec();
+                enable_kernel_altivec();
+                load_vr_state(&vcpu->arch.vr);
+                t->vr_save_area = &vcpu->arch.vr;
 #endif
         }
 
-        current->thread.regs->msr |= msr;
+        t->regs->msr |= msr;
         vcpu->arch.guest_owned_ext |= msr;
         kvmppc_recalc_shadow_msr(vcpu);
 
@@ -743,11 +715,15 @@ static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu)
         if (!lost_ext)
                 return;
 
-        if (lost_ext & MSR_FP)
-                kvmppc_load_up_fpu();
+        if (lost_ext & MSR_FP) {
+                enable_kernel_fp();
+                load_fp_state(&vcpu->arch.fp);
+        }
 #ifdef CONFIG_ALTIVEC
-        if (lost_ext & MSR_VEC)
-                kvmppc_load_up_altivec();
+        if (lost_ext & MSR_VEC) {
+                enable_kernel_altivec();
+                load_vr_state(&vcpu->arch.vr);
+        }
 #endif
         current->thread.regs->msr |= lost_ext;
 }
@@ -873,6 +849,7 @@ int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
         /* We're good on these - the host merely wanted to get our attention */
         case BOOK3S_INTERRUPT_DECREMENTER:
         case BOOK3S_INTERRUPT_HV_DECREMENTER:
+        case BOOK3S_INTERRUPT_DOORBELL:
                 vcpu->stat.dec_exits++;
                 r = RESUME_GUEST;
                 break;
@@ -1045,14 +1022,14 @@ program_interrupt:
                  * and if we really did time things so badly, then we just exit
                  * again due to a host external interrupt.
                  */
-                local_irq_disable();
                 s = kvmppc_prepare_to_enter(vcpu);
-                if (s <= 0) {
-                        local_irq_enable();
+                if (s <= 0)
                         r = s;
-                } else {
+                else {
+                        /* interrupts now hard-disabled */
                         kvmppc_fix_ee_before_entry();
                 }
+
                 kvmppc_handle_lost_ext(vcpu);
         }
 
@@ -1133,19 +1110,6 @@ static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_HIOR:
                 *val = get_reg_val(id, to_book3s(vcpu)->hior);
                 break;
-#ifdef CONFIG_VSX
-        case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: {
-                long int i = id - KVM_REG_PPC_VSR0;
-
-                if (!cpu_has_feature(CPU_FTR_VSX)) {
-                        r = -ENXIO;
-                        break;
-                }
-                val->vsxval[0] = vcpu->arch.fpr[i];
-                val->vsxval[1] = vcpu->arch.vsr[i];
-                break;
-        }
-#endif /* CONFIG_VSX */
         default:
                 r = -EINVAL;
                 break;
@@ -1164,19 +1128,6 @@ static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id,
                 to_book3s(vcpu)->hior = set_reg_val(id, *val);
                 to_book3s(vcpu)->hior_explicit = true;
                 break;
-#ifdef CONFIG_VSX
-        case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: {
-                long int i = id - KVM_REG_PPC_VSR0;
-
-                if (!cpu_has_feature(CPU_FTR_VSX)) {
-                        r = -ENXIO;
-                        break;
-                }
-                vcpu->arch.fpr[i] = val->vsxval[0];
-                vcpu->arch.vsr[i] = val->vsxval[1];
-                break;
-        }
-#endif /* CONFIG_VSX */
         default:
                 r = -EINVAL;
                 break;
@@ -1274,17 +1225,9 @@ static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu)
 static int kvmppc_vcpu_run_pr(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 {
         int ret;
-        struct thread_fp_state fp;
-        int fpexc_mode;
 #ifdef CONFIG_ALTIVEC
-        struct thread_vr_state vr;
         unsigned long uninitialized_var(vrsave);
-        int used_vr;
 #endif
-#ifdef CONFIG_VSX
-        int used_vsr;
-#endif
-        ulong ext_msr;
 
         /* Check if we can run the vcpu at all */
         if (!vcpu->arch.sane) {
@@ -1299,40 +1242,27 @@ static int kvmppc_vcpu_run_pr(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
          * really did time things so badly, then we just exit again due to
          * a host external interrupt.
          */
-        local_irq_disable();
         ret = kvmppc_prepare_to_enter(vcpu);
-        if (ret <= 0) {
-                local_irq_enable();
+        if (ret <= 0)
                 goto out;
-        }
+        /* interrupts now hard-disabled */
 
-        /* Save FPU state in stack */
+        /* Save FPU state in thread_struct */
         if (current->thread.regs->msr & MSR_FP)
                 giveup_fpu(current);
-        fp = current->thread.fp_state;
-        fpexc_mode = current->thread.fpexc_mode;
 
 #ifdef CONFIG_ALTIVEC
-        /* Save Altivec state in stack */
-        used_vr = current->thread.used_vr;
-        if (used_vr) {
-                if (current->thread.regs->msr & MSR_VEC)
-                        giveup_altivec(current);
-                vr = current->thread.vr_state;
-                vrsave = current->thread.vrsave;
-        }
+        /* Save Altivec state in thread_struct */
+        if (current->thread.regs->msr & MSR_VEC)
+                giveup_altivec(current);
 #endif
 
 #ifdef CONFIG_VSX
-        /* Save VSX state in stack */
-        used_vsr = current->thread.used_vsr;
-        if (used_vsr && (current->thread.regs->msr & MSR_VSX))
+        /* Save VSX state in thread_struct */
+        if (current->thread.regs->msr & MSR_VSX)
                 __giveup_vsx(current);
 #endif
 
-        /* Remember the MSR with disabled extensions */
-        ext_msr = current->thread.regs->msr;
-
         /* Preload FPU if it's enabled */
         if (vcpu->arch.shared->msr & MSR_FP)
                 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
@@ -1347,25 +1277,6 @@ static int kvmppc_vcpu_run_pr(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         /* Make sure we save the guest FPU/Altivec/VSX state */
         kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
 
-        current->thread.regs->msr = ext_msr;
-
-        /* Restore FPU/VSX state from stack */
-        current->thread.fp_state = fp;
-        current->thread.fpexc_mode = fpexc_mode;
-
-#ifdef CONFIG_ALTIVEC
-        /* Restore Altivec state from stack */
-        if (used_vr && current->thread.used_vr) {
-                current->thread.vr_state = vr;
-                current->thread.vrsave = vrsave;
-        }
-        current->thread.used_vr = used_vr;
-#endif
-
-#ifdef CONFIG_VSX
-        current->thread.used_vsr = used_vsr;
-#endif
-
 out:
         vcpu->mode = OUTSIDE_GUEST_MODE;
         return ret;
@@ -1606,4 +1517,6 @@ module_init(kvmppc_book3s_init_pr);
 module_exit(kvmppc_book3s_exit_pr);
 
 MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
 #endif
diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index c3c5231adade..9eec675220e6 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -162,51 +162,4 @@ _GLOBAL(kvmppc_entry_trampoline)
         mtsrr1  r6
         RFI
 
-#if defined(CONFIG_PPC_BOOK3S_32)
-#define STACK_LR        INT_FRAME_SIZE+4
-
-/* load_up_xxx have to run with MSR_DR=0 on Book3S_32 */
-#define MSR_EXT_START                                           \
-        PPC_STL r20, _NIP(r1);                                  \
-        mfmsr   r20;                                            \
-        LOAD_REG_IMMEDIATE(r3, MSR_DR|MSR_EE);                  \
-        andc    r3,r20,r3;              /* Disable DR,EE */     \
-        mtmsr   r3;                                             \
-        sync
-
-#define MSR_EXT_END                                             \
-        mtmsr   r20;                    /* Enable DR,EE */      \
-        sync;                                                   \
-        PPC_LL  r20, _NIP(r1)
-
-#elif defined(CONFIG_PPC_BOOK3S_64)
-#define STACK_LR        _LINK
-#define MSR_EXT_START
-#define MSR_EXT_END
-#endif
-
-/*
- * Activate current's external feature (FPU/Altivec/VSX)
- */
-#define define_load_up(what)                                    \
-                                                                \
-_GLOBAL(kvmppc_load_up_ ## what);                               \
-        PPC_STLU r1, -INT_FRAME_SIZE(r1);                       \
-        mflr    r3;                                             \
-        PPC_STL r3, STACK_LR(r1);                               \
-        MSR_EXT_START;                                          \
-                                                                \
-        bl      FUNC(load_up_ ## what);                         \
-                                                                \
-        MSR_EXT_END;                                            \
-        PPC_LL  r3, STACK_LR(r1);                               \
-        mtlr    r3;                                             \
-        addi    r1, r1, INT_FRAME_SIZE;                         \
-        blr
-
-define_load_up(fpu)
-#ifdef CONFIG_ALTIVEC
-define_load_up(altivec)
-#endif
-
 #include "book3s_segment.S"
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index bc50c97751d3..1e0cc2adfd40 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -361,6 +361,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
         beqa    BOOK3S_INTERRUPT_DECREMENTER
         cmpwi   r12, BOOK3S_INTERRUPT_PERFMON
         beqa    BOOK3S_INTERRUPT_PERFMON
+        cmpwi   r12, BOOK3S_INTERRUPT_DOORBELL
+        beqa    BOOK3S_INTERRUPT_DOORBELL
 
         RFI
 kvmppc_handler_trampoline_exit_end:
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
index 02a17dcf1610..d1acd32a64c0 100644
--- a/arch/powerpc/kvm/book3s_xics.c
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -1246,8 +1246,10 @@ static int kvmppc_xics_create(struct kvm_device *dev, u32 type)
                 kvm->arch.xics = xics;
         mutex_unlock(&kvm->lock);
 
-        if (ret)
+        if (ret) {
+                kfree(xics);
                 return ret;
+        }
 
         xics_debugfs_init(xics);
 
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 0591e05db74b..ab62109fdfa3 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -643,7 +643,7 @@ int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
                 local_irq_enable();
                 kvm_vcpu_block(vcpu);
                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
-                local_irq_disable();
+                hard_irq_disable();
 
                 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
                 r = 1;
@@ -682,34 +682,22 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 {
         int ret, s;
         struct debug_reg debug;
-#ifdef CONFIG_PPC_FPU
-        struct thread_fp_state fp;
-        int fpexc_mode;
-#endif
 
         if (!vcpu->arch.sane) {
                 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
                 return -EINVAL;
         }
 
-        local_irq_disable();
         s = kvmppc_prepare_to_enter(vcpu);
         if (s <= 0) {
-                local_irq_enable();
                 ret = s;
                 goto out;
         }
+        /* interrupts now hard-disabled */
 
 #ifdef CONFIG_PPC_FPU
         /* Save userspace FPU state in stack */
         enable_kernel_fp();
-        fp = current->thread.fp_state;
-        fpexc_mode = current->thread.fpexc_mode;
-
-        /* Restore guest FPU state to thread */
-        memcpy(current->thread.fp_state.fpr, vcpu->arch.fpr,
-               sizeof(vcpu->arch.fpr));
-        current->thread.fp_state.fpscr = vcpu->arch.fpscr;
 
         /*
          * Since we can't trap on MSR_FP in GS-mode, we consider the guest
@@ -728,6 +716,7 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         debug = current->thread.debug;
         current->thread.debug = vcpu->arch.shadow_dbg_reg;
 
+        vcpu->arch.pgdir = current->mm->pgd;
         kvmppc_fix_ee_before_entry();
 
         ret = __kvmppc_vcpu_run(kvm_run, vcpu);
@@ -743,15 +732,6 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         kvmppc_save_guest_fp(vcpu);
 
         vcpu->fpu_active = 0;
-
-        /* Save guest FPU state from thread */
-        memcpy(vcpu->arch.fpr, current->thread.fp_state.fpr,
-               sizeof(vcpu->arch.fpr));
-        vcpu->arch.fpscr = current->thread.fp_state.fpscr;
-
-        /* Restore userspace FPU state from stack */
-        current->thread.fp_state = fp;
-        current->thread.fpexc_mode = fpexc_mode;
 #endif
 
 out:
@@ -898,17 +878,6 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
         int s;
         int idx;
 
-#ifdef CONFIG_PPC64
-        WARN_ON(local_paca->irq_happened != 0);
-#endif
-
-        /*
-         * We enter with interrupts disabled in hardware, but
-         * we need to call hard_irq_disable anyway to ensure that
-         * the software state is kept in sync.
-         */
-        hard_irq_disable();
-
         /* update before a new last_exit_type is rewritten */
         kvmppc_update_timing_stats(vcpu);
 
@@ -1217,12 +1186,11 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
          * aren't already exiting to userspace for some other reason.
          */
         if (!(r & RESUME_HOST)) {
-                local_irq_disable();
                 s = kvmppc_prepare_to_enter(vcpu);
-                if (s <= 0) {
-                        local_irq_enable();
+                if (s <= 0)
                         r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
-                } else {
+                else {
+                        /* interrupts now hard-disabled */
                         kvmppc_fix_ee_before_entry();
                 }
         }
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index 09bfd9bc7cf8..b632cd35919b 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -136,7 +136,9 @@ static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
 {
 #ifdef CONFIG_PPC_FPU
         if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) {
-                load_up_fpu();
+                enable_kernel_fp();
+                load_fp_state(&vcpu->arch.fp);
+                current->thread.fp_save_area = &vcpu->arch.fp;
                 current->thread.regs->msr |= MSR_FP;
         }
 #endif
@@ -151,6 +153,7 @@ static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
 #ifdef CONFIG_PPC_FPU
         if (vcpu->fpu_active && (current->thread.regs->msr & MSR_FP))
                 giveup_fpu(current);
+        current->thread.fp_save_area = NULL;
 #endif
 }
 
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index e8ed7d659c55..e4185f6b3309 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -33,6 +33,8 @@
 
 #ifdef CONFIG_64BIT
 #include <asm/exception-64e.h>
+#include <asm/hw_irq.h>
+#include <asm/irqflags.h>
 #else
 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
 #endif
@@ -319,6 +321,8 @@ kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
         SPRN_DSRR0, SPRN_DSRR1, 0
 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
         SPRN_CSRR0, SPRN_CSRR1, 0
+kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \
+        SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 #else
 /*
  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
@@ -465,6 +469,15 @@ _GLOBAL(kvmppc_resume_host)
         mtspr   SPRN_EPCR, r3
         isync
 
+#ifdef CONFIG_64BIT
+        /*
+         * We enter with interrupts disabled in hardware, but
+         * we need to call RECONCILE_IRQ_STATE to ensure
+         * that the software state is kept in sync.
+         */
+        RECONCILE_IRQ_STATE(r3,r5)
+#endif
+
         /* Switch to kernel stack and jump to handler. */
         PPC_LL  r3, HOST_RUN(r1)
         mr      r5, r14 /* intno */
diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index 497b142f651c..2e02ed849f36 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -16,6 +16,8 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/export.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
 
 #include <asm/reg.h>
 #include <asm/cputable.h>
@@ -573,3 +575,5 @@ static void __exit kvmppc_e500_exit(void)
 
 module_init(kvmppc_e500_init);
 module_exit(kvmppc_e500_exit);
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 4fd9650eb018..a326178bdea5 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -31,11 +31,13 @@ enum vcpu_ftr {
 #define E500_TLB_NUM   2
 
 /* entry is mapped somewhere in host TLB */
-#define E500_TLB_VALID          (1 << 0)
+#define E500_TLB_VALID          (1 << 31)
 /* TLB1 entry is mapped by host TLB1, tracked by bitmaps */
-#define E500_TLB_BITMAP         (1 << 1)
+#define E500_TLB_BITMAP         (1 << 30)
 /* TLB1 entry is mapped by host TLB0 */
-#define E500_TLB_TLB0           (1 << 2)
+#define E500_TLB_TLB0           (1 << 29)
+/* bits [6-5] MAS2_X1 and MAS2_X0 and [4-0] bits for WIMGE */
+#define E500_TLB_MAS2_ATTR      (0x7f)
 
 struct tlbe_ref {
         pfn_t pfn;              /* valid only for TLB0, except briefly */
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index ebca6b88ea5e..50860e919cb8 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -127,7 +127,7 @@ static int kvmppc_e500_tlb_index(struct kvmppc_vcpu_e500 *vcpu_e500,
 }
 
 static inline void kvmppc_e500_deliver_tlb_miss(struct kvm_vcpu *vcpu,
-                unsigned int eaddr, int as)
+                gva_t eaddr, int as)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
         unsigned int victim, tsized;
diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index ecf2247b13be..dd2cc03f406f 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -65,15 +65,6 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
         return mas3;
 }
 
-static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
-{
-#ifdef CONFIG_SMP
-        return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M;
-#else
-        return mas2 & MAS2_ATTRIB_MASK;
-#endif
-}
-
 /*
  * writing shadow tlb entry to host TLB
  */
@@ -231,15 +222,15 @@ void inval_gtlbe_on_host(struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel,
                 ref->flags &= ~(E500_TLB_TLB0 | E500_TLB_VALID);
         }
 
-        /* Already invalidated in between */
-        if (!(ref->flags & E500_TLB_VALID))
-                return;
-
-        /* Guest tlbe is backed by at most one host tlbe per shadow pid. */
-        kvmppc_e500_tlbil_one(vcpu_e500, gtlbe);
+        /*
+         * If TLB entry is still valid then it's a TLB0 entry, and thus
+         * backed by at most one host tlbe per shadow pid
+         */
+        if (ref->flags & E500_TLB_VALID)
+                kvmppc_e500_tlbil_one(vcpu_e500, gtlbe);
 
         /* Mark the TLB as not backed by the host anymore */
-        ref->flags &= ~E500_TLB_VALID;
+        ref->flags = 0;
 }
 
 static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe)
@@ -249,10 +240,13 @@ static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe)
 
 static inline void kvmppc_e500_ref_setup(struct tlbe_ref *ref,
                                          struct kvm_book3e_206_tlb_entry *gtlbe,
-                                         pfn_t pfn)
+                                         pfn_t pfn, unsigned int wimg)
 {
         ref->pfn = pfn;
-        ref->flags |= E500_TLB_VALID;
+        ref->flags = E500_TLB_VALID;
+
+        /* Use guest supplied MAS2_G and MAS2_E */
+        ref->flags |= (gtlbe->mas2 & MAS2_ATTRIB_MASK) | wimg;
 
         /* Mark the page accessed */
         kvm_set_pfn_accessed(pfn);
@@ -316,8 +310,7 @@ static void kvmppc_e500_setup_stlbe(
 
         /* Force IPROT=0 for all guest mappings. */
         stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
-        stlbe->mas2 = (gvaddr & MAS2_EPN) |
-                      e500_shadow_mas2_attrib(gtlbe->mas2, pr);
+        stlbe->mas2 = (gvaddr & MAS2_EPN) | (ref->flags & E500_TLB_MAS2_ATTR);
         stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
                         e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
 
@@ -339,6 +332,10 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
         int ret = 0;
         unsigned long mmu_seq;
         struct kvm *kvm = vcpu_e500->vcpu.kvm;
+        unsigned long tsize_pages = 0;
+        pte_t *ptep;
+        unsigned int wimg = 0;
+        pgd_t *pgdir;
 
         /* used to check for invalidations in progress */
         mmu_seq = kvm->mmu_notifier_seq;
@@ -405,7 +402,7 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
                          */
 
                         for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
-                                unsigned long gfn_start, gfn_end, tsize_pages;
+                                unsigned long gfn_start, gfn_end;
                                 tsize_pages = 1 << (tsize - 2);
 
                                 gfn_start = gfn & ~(tsize_pages - 1);
@@ -447,11 +444,12 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
         }
 
         if (likely(!pfnmap)) {
-                unsigned long tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
+                tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
                 pfn = gfn_to_pfn_memslot(slot, gfn);
                 if (is_error_noslot_pfn(pfn)) {
-                        printk(KERN_ERR "Couldn't get real page for gfn %lx!\n",
-                                        (long)gfn);
+                        if (printk_ratelimit())
+                                pr_err("%s: real page not found for gfn %lx\n",
+                                       __func__, (long)gfn);
                         return -EINVAL;
                 }
 
@@ -466,7 +464,18 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
                 goto out;
         }
 
-        kvmppc_e500_ref_setup(ref, gtlbe, pfn);
+
+        pgdir = vcpu_e500->vcpu.arch.pgdir;
+        ptep = lookup_linux_ptep(pgdir, hva, &tsize_pages);
+        if (pte_present(*ptep))
+                wimg = (*ptep >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
+        else {
+                if (printk_ratelimit())
+                        pr_err("%s: pte not present: gfn %lx, pfn %lx\n",
+                                __func__, (long)gfn, pfn);
+                return -EINVAL;
+        }
+        kvmppc_e500_ref_setup(ref, gtlbe, pfn, wimg);
 
         kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize,
                                 ref, gvaddr, stlbe);
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 4132cd2fc171..17e456279224 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -16,6 +16,8 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/export.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
 
 #include <asm/reg.h>
 #include <asm/cputable.h>
@@ -391,3 +393,5 @@ static void __exit kvmppc_e500mc_exit(void)
 
 module_init(kvmppc_e500mc_init);
 module_exit(kvmppc_e500mc_exit);
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 2f9a0873b44f..c2b887be2c29 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -219,7 +219,6 @@ static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
  * lmw
  * stmw
  *
- * XXX is_bigendian should depend on MMU mapping or MSR[LE]
  */
 /* XXX Should probably auto-generate instruction decoding for a particular core
  * from opcode tables in the future. */
diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/kvm/mpic.c
index 2861ae9eaae6..efbd9962a209 100644
--- a/arch/powerpc/kvm/mpic.c
+++ b/arch/powerpc/kvm/mpic.c
@@ -1635,6 +1635,7 @@ static void mpic_destroy(struct kvm_device *dev)
 
         dev->kvm->arch.mpic = NULL;
         kfree(opp);
+        kfree(dev);
 }
 
 static int mpic_set_default_irq_routing(struct openpic *opp)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 9ae97686e9f4..3cf541a53e2a 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -68,14 +68,16 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  */
 int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
 {
-        int r = 1;
+        int r;
+
+        WARN_ON(irqs_disabled());
+        hard_irq_disable();
 
-        WARN_ON_ONCE(!irqs_disabled());
         while (true) {
                 if (need_resched()) {
                         local_irq_enable();
                         cond_resched();
-                        local_irq_disable();
+                        hard_irq_disable();
                         continue;
                 }
 
@@ -101,7 +103,7 @@ int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
                         local_irq_enable();
                         trace_kvm_check_requests(vcpu);
                         r = kvmppc_core_check_requests(vcpu);
-                        local_irq_disable();
+                        hard_irq_disable();
                         if (r > 0)
                                 continue;
                         break;
@@ -113,22 +115,12 @@ int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
                         continue;
                 }
 
-#ifdef CONFIG_PPC64
-                /* lazy EE magic */
-                hard_irq_disable();
-                if (lazy_irq_pending()) {
-                        /* Got an interrupt in between, try again */
-                        local_irq_enable();
-                        local_irq_disable();
-                        kvm_guest_exit();
-                        continue;
-                }
-#endif
-
                 kvm_guest_enter();
-                break;
+                return 1;
         }
 
+        /* return to host */
+        local_irq_enable();
         return r;
 }
 EXPORT_SYMBOL_GPL(kvmppc_prepare_to_enter);
@@ -656,14 +648,14 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,
                 kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr);
                 break;
         case KVM_MMIO_REG_FPR:
-                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
+                VCPU_FPR(vcpu, vcpu->arch.io_gpr & KVM_MMIO_REG_MASK) = gpr;
                 break;
 #ifdef CONFIG_PPC_BOOK3S
         case KVM_MMIO_REG_QPR:
                 vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
                 break;
         case KVM_MMIO_REG_FQPR:
-                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
+                VCPU_FPR(vcpu, vcpu->arch.io_gpr & KVM_MMIO_REG_MASK) = gpr;
                 vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
                 break;
 #endif
@@ -673,9 +665,19 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,
 }
 
 int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                       unsigned int rt, unsigned int bytes, int is_bigendian)
+                       unsigned int rt, unsigned int bytes,
+                       int is_default_endian)
 {
         int idx, ret;
+        int is_bigendian;
+
+        if (kvmppc_need_byteswap(vcpu)) {
+                /* Default endianness is "little endian". */
+                is_bigendian = !is_default_endian;
+        } else {
+                /* Default endianness is "big endian". */
+                is_bigendian = is_default_endian;
+        }
 
         if (bytes > sizeof(run->mmio.data)) {
                 printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__,
@@ -711,21 +713,31 @@ EXPORT_SYMBOL_GPL(kvmppc_handle_load);
 
 /* Same as above, but sign extends */
 int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                        unsigned int rt, unsigned int bytes, int is_bigendian)
+                        unsigned int rt, unsigned int bytes,
+                        int is_default_endian)
 {
         int r;
 
         vcpu->arch.mmio_sign_extend = 1;
-        r = kvmppc_handle_load(run, vcpu, rt, bytes, is_bigendian);
+        r = kvmppc_handle_load(run, vcpu, rt, bytes, is_default_endian);
 
         return r;
 }
 
 int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                        u64 val, unsigned int bytes, int is_bigendian)
+                        u64 val, unsigned int bytes, int is_default_endian)
 {
         void *data = run->mmio.data;
         int idx, ret;
+        int is_bigendian;
+
+        if (kvmppc_need_byteswap(vcpu)) {
+                /* Default endianness is "little endian". */
+                is_bigendian = !is_default_endian;
+        } else {
+                /* Default endianness is "big endian". */
+                is_bigendian = is_default_endian;
+        }
 
         if (bytes > sizeof(run->mmio.data)) {
                 printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__,
diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
index 17e5b2364312..d5edbeb8eb82 100644
--- a/arch/powerpc/lib/code-patching.c
+++ b/arch/powerpc/lib/code-patching.c
@@ -159,6 +159,21 @@ unsigned int translate_branch(const unsigned int *dest, const unsigned int *src)
         return 0;
 }
 
+#ifdef CONFIG_PPC_BOOK3E_64
+void __patch_exception(int exc, unsigned long addr)
+{
+        extern unsigned int interrupt_base_book3e;
+        unsigned int *ibase = &interrupt_base_book3e;
+
+        /* Our exceptions vectors start with a NOP and -then- a branch
+         * to deal with single stepping from userspace which stops on
+         * the second instruction. Thus we need to patch the second
+         * instruction of the exception, not the first one
+         */
+
+        patch_branch(ibase + (exc / 4) + 1, addr, 0);
+}
+#endif
 
 #ifdef CONFIG_CODE_PATCHING_SELFTEST
 
diff --git a/arch/powerpc/lib/crtsavres.S b/arch/powerpc/lib/crtsavres.S
index b2c68ce139ae..a5b30c71a8d3 100644
--- a/arch/powerpc/lib/crtsavres.S
+++ b/arch/powerpc/lib/crtsavres.S
@@ -231,6 +231,87 @@ _GLOBAL(_rest32gpr_31_x)
         mr      1,11
         blr
 
+#ifdef CONFIG_ALTIVEC
+/* Called with r0 pointing just beyond the end of the vector save area.  */
+
+_GLOBAL(_savevr_20)
+        li      r11,-192
+        stvx    vr20,r11,r0
+_GLOBAL(_savevr_21)
+        li      r11,-176
+        stvx    vr21,r11,r0
+_GLOBAL(_savevr_22)
+        li      r11,-160
+        stvx    vr22,r11,r0
+_GLOBAL(_savevr_23)
+        li      r11,-144
+        stvx    vr23,r11,r0
+_GLOBAL(_savevr_24)
+        li      r11,-128
+        stvx    vr24,r11,r0
+_GLOBAL(_savevr_25)
+        li      r11,-112
+        stvx    vr25,r11,r0
+_GLOBAL(_savevr_26)
+        li      r11,-96
+        stvx    vr26,r11,r0
+_GLOBAL(_savevr_27)
+        li      r11,-80
+        stvx    vr27,r11,r0
+_GLOBAL(_savevr_28)
+        li      r11,-64
+        stvx    vr28,r11,r0
+_GLOBAL(_savevr_29)
+        li      r11,-48
+        stvx    vr29,r11,r0
+_GLOBAL(_savevr_30)
+        li      r11,-32
+        stvx    vr30,r11,r0
+_GLOBAL(_savevr_31)
+        li      r11,-16
+        stvx    vr31,r11,r0
+        blr
+
+_GLOBAL(_restvr_20)
+        li      r11,-192
+        lvx     vr20,r11,r0
+_GLOBAL(_restvr_21)
+        li      r11,-176
+        lvx     vr21,r11,r0
+_GLOBAL(_restvr_22)
+        li      r11,-160
+        lvx     vr22,r11,r0
+_GLOBAL(_restvr_23)
+        li      r11,-144
+        lvx     vr23,r11,r0
+_GLOBAL(_restvr_24)
+        li      r11,-128
+        lvx     vr24,r11,r0
+_GLOBAL(_restvr_25)
+        li      r11,-112
+        lvx     vr25,r11,r0
+_GLOBAL(_restvr_26)
+        li      r11,-96
+        lvx     vr26,r11,r0
+_GLOBAL(_restvr_27)
+        li      r11,-80
+        lvx     vr27,r11,r0
+_GLOBAL(_restvr_28)
+        li      r11,-64
+        lvx     vr28,r11,r0
+_GLOBAL(_restvr_29)
+        li      r11,-48
+        lvx     vr29,r11,r0
+_GLOBAL(_restvr_30)
+        li      r11,-32
+        lvx     vr30,r11,r0
+_GLOBAL(_restvr_31)
+        li      r11,-16
+        lvx     vr31,r11,r0
+        blr
+
+#endif /* CONFIG_ALTIVEC */
+
 #else /* CONFIG_PPC64 */
 
         .section ".text.save.restore","ax",@progbits
@@ -356,6 +437,111 @@ _restgpr0_31:
         mtlr    r0
         blr
 
+#ifdef CONFIG_ALTIVEC
+/* Called with r0 pointing just beyond the end of the vector save area.  */
+
+.globl  _savevr_20
+_savevr_20:
+        li      r12,-192
+        stvx    vr20,r12,r0
+.globl  _savevr_21
+_savevr_21:
+        li      r12,-176
+        stvx    vr21,r12,r0
+.globl  _savevr_22
+_savevr_22:
+        li      r12,-160
+        stvx    vr22,r12,r0
+.globl  _savevr_23
+_savevr_23:
+        li      r12,-144
+        stvx    vr23,r12,r0
+.globl  _savevr_24
+_savevr_24:
+        li      r12,-128
+        stvx    vr24,r12,r0
+.globl  _savevr_25
+_savevr_25:
+        li      r12,-112
+        stvx    vr25,r12,r0
+.globl  _savevr_26
+_savevr_26:
+        li      r12,-96
+        stvx    vr26,r12,r0
+.globl  _savevr_27
+_savevr_27:
+        li      r12,-80
+        stvx    vr27,r12,r0
+.globl  _savevr_28
+_savevr_28:
+        li      r12,-64
+        stvx    vr28,r12,r0
+.globl  _savevr_29
+_savevr_29:
+        li      r12,-48
+        stvx    vr29,r12,r0
+.globl  _savevr_30
+_savevr_30:
+        li      r12,-32
+        stvx    vr30,r12,r0
+.globl  _savevr_31
+_savevr_31:
+        li      r12,-16
+        stvx    vr31,r12,r0
+        blr
+
+.globl  _restvr_20
+_restvr_20:
+        li      r12,-192
+        lvx     vr20,r12,r0
+.globl  _restvr_21
+_restvr_21:
+        li      r12,-176
+        lvx     vr21,r12,r0
+.globl  _restvr_22
+_restvr_22:
+        li      r12,-160
+        lvx     vr22,r12,r0
+.globl  _restvr_23
+_restvr_23:
+        li      r12,-144
+        lvx     vr23,r12,r0
+.globl  _restvr_24
+_restvr_24:
+        li      r12,-128
+        lvx     vr24,r12,r0
+.globl  _restvr_25
+_restvr_25:
+        li      r12,-112
+        lvx     vr25,r12,r0
+.globl  _restvr_26
+_restvr_26:
+        li      r12,-96
+        lvx     vr26,r12,r0
+.globl  _restvr_27
+_restvr_27:
+        li      r12,-80
+        lvx     vr27,r12,r0
+.globl  _restvr_28
+_restvr_28:
+        li      r12,-64
+        lvx     vr28,r12,r0
+.globl  _restvr_29
+_restvr_29:
+        li      r12,-48
+        lvx     vr29,r12,r0
+.globl  _restvr_30
+_restvr_30:
+        li      r12,-32
+        lvx     vr30,r12,r0
+.globl  _restvr_31
+_restvr_31:
+        li      r12,-16
+        lvx     vr31,r12,r0
+        blr
+
+#endif /* CONFIG_ALTIVEC */
+
 #endif /* CONFIG_PPC64 */
 
 #endif
diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c
index a73f0884d358..28337c9709ae 100644
--- a/arch/powerpc/math-emu/math_efp.c
+++ b/arch/powerpc/math-emu/math_efp.c
@@ -20,6 +20,7 @@
  */
 
 #include <linux/types.h>
+#include <linux/prctl.h>
 
 #include <asm/uaccess.h>
 #include <asm/reg.h>
@@ -275,21 +276,13 @@ int do_spe_mathemu(struct pt_regs *regs)
 
                 case EFSCTSF:
                 case EFSCTUF:
-                        if (!((vb.wp[1] >> 23) == 0xff && ((vb.wp[1] & 0x7fffff) > 0))) {
-                                /* NaN */
-                                if (((vb.wp[1] >> 23) & 0xff) == 0) {
-                                        /* denorm */
-                                        vc.wp[1] = 0x0;
-                                } else if ((vb.wp[1] >> 31) == 0) {
-                                        /* positive normal */
-                                        vc.wp[1] = (func == EFSCTSF) ?
-                                                0x7fffffff : 0xffffffff;
-                                } else { /* negative normal */
-                                        vc.wp[1] = (func == EFSCTSF) ?
-                                                0x80000000 : 0x0;
-                                }
-                        } else { /* rB is NaN */
-                                vc.wp[1] = 0x0;
+                        if (SB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                SB_e += (func == EFSCTSF ? 31 : 32);
+                                FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
+                                                (func == EFSCTSF));
                         }
                         goto update_regs;
 
@@ -306,16 +299,25 @@ int do_spe_mathemu(struct pt_regs *regs)
                 }
 
                 case EFSCTSI:
-                case EFSCTSIZ:
                 case EFSCTUI:
+                        if (SB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
+                                                ((func & 0x3) != 0));
+                        }
+                        goto update_regs;
+
+                case EFSCTSIZ:
                 case EFSCTUIZ:
-                        if (func & 0x4) {
-                                _FP_ROUND(1, SB);
+                        if (SB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
                         } else {
-                                _FP_ROUND_ZERO(1, SB);
+                                FP_TO_INT_S(vc.wp[1], SB, 32,
+                                                ((func & 0x3) != 0));
                         }
-                        FP_TO_INT_S(vc.wp[1], SB, 32,
-                                        (((func & 0x3) != 0) || SB_s));
                         goto update_regs;
 
                 default:
@@ -404,22 +406,13 @@ cmp_s:
 
                 case EFDCTSF:
                 case EFDCTUF:
-                        if (!((vb.wp[0] >> 20) == 0x7ff &&
-                           ((vb.wp[0] & 0xfffff) > 0 || (vb.wp[1] > 0)))) {
-                                /* not a NaN */
-                                if (((vb.wp[0] >> 20) & 0x7ff) == 0) {
-                                        /* denorm */
-                                        vc.wp[1] = 0x0;
-                                } else if ((vb.wp[0] >> 31) == 0) {
-                                        /* positive normal */
-                                        vc.wp[1] = (func == EFDCTSF) ?
-                                                0x7fffffff : 0xffffffff;
-                                } else { /* negative normal */
-                                        vc.wp[1] = (func == EFDCTSF) ?
-                                                0x80000000 : 0x0;
-                                }
-                        } else { /* NaN */
-                                vc.wp[1] = 0x0;
+                        if (DB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                DB_e += (func == EFDCTSF ? 31 : 32);
+                                FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
+                                                (func == EFDCTSF));
                         }
                         goto update_regs;
 
@@ -437,21 +430,35 @@ cmp_s:
 
                 case EFDCTUIDZ:
                 case EFDCTSIDZ:
-                        _FP_ROUND_ZERO(2, DB);
-                        FP_TO_INT_D(vc.dp[0], DB, 64, ((func & 0x1) == 0));
+                        if (DB_c == FP_CLS_NAN) {
+                                vc.dp[0] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_D(vc.dp[0], DB, 64,
+                                                ((func & 0x1) == 0));
+                        }
                         goto update_regs;
 
                 case EFDCTUI:
                 case EFDCTSI:
+                        if (DB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
+                                                ((func & 0x3) != 0));
+                        }
+                        goto update_regs;
+
                 case EFDCTUIZ:
                 case EFDCTSIZ:
-                        if (func & 0x4) {
-                                _FP_ROUND(2, DB);
+                        if (DB_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
                         } else {
-                                _FP_ROUND_ZERO(2, DB);
+                                FP_TO_INT_D(vc.wp[1], DB, 32,
+                                                ((func & 0x3) != 0));
                         }
-                        FP_TO_INT_D(vc.wp[1], DB, 32,
-                                        (((func & 0x3) != 0) || DB_s));
                         goto update_regs;
 
                 default:
@@ -556,37 +563,60 @@ cmp_d:
                         cmp = -1;
                         goto cmp_vs;
 
-                case EVFSCTSF:
-                        __asm__ __volatile__ ("mtspr 512, %4\n"
-                                "efsctsf %0, %2\n"
-                                "efsctsf %1, %3\n"
-                                : "=r" (vc.wp[0]), "=r" (vc.wp[1])
-                                : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
-                        goto update_regs;
-
                 case EVFSCTUF:
-                        __asm__ __volatile__ ("mtspr 512, %4\n"
-                                "efsctuf %0, %2\n"
-                                "efsctuf %1, %3\n"
-                                : "=r" (vc.wp[0]), "=r" (vc.wp[1])
-                                : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
+                case EVFSCTSF:
+                        if (SB0_c == FP_CLS_NAN) {
+                                vc.wp[0] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                SB0_e += (func == EVFSCTSF ? 31 : 32);
+                                FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
+                                                (func == EVFSCTSF));
+                        }
+                        if (SB1_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                SB1_e += (func == EVFSCTSF ? 31 : 32);
+                                FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
+                                                (func == EVFSCTSF));
+                        }
                         goto update_regs;
 
                 case EVFSCTUI:
                 case EVFSCTSI:
+                        if (SB0_c == FP_CLS_NAN) {
+                                vc.wp[0] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
+                                                ((func & 0x3) != 0));
+                        }
+                        if (SB1_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
+                                                ((func & 0x3) != 0));
+                        }
+                        goto update_regs;
+
                 case EVFSCTUIZ:
                 case EVFSCTSIZ:
-                        if (func & 0x4) {
-                                _FP_ROUND(1, SB0);
-                                _FP_ROUND(1, SB1);
+                        if (SB0_c == FP_CLS_NAN) {
+                                vc.wp[0] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
                         } else {
-                                _FP_ROUND_ZERO(1, SB0);
-                                _FP_ROUND_ZERO(1, SB1);
+                                FP_TO_INT_S(vc.wp[0], SB0, 32,
+                                                ((func & 0x3) != 0));
+                        }
+                        if (SB1_c == FP_CLS_NAN) {
+                                vc.wp[1] = 0;
+                                FP_SET_EXCEPTION(FP_EX_INVALID);
+                        } else {
+                                FP_TO_INT_S(vc.wp[1], SB1, 32,
+                                                ((func & 0x3) != 0));
                         }
-                        FP_TO_INT_S(vc.wp[0], SB0, 32,
-                                        (((func & 0x3) != 0) || SB0_s));
-                        FP_TO_INT_S(vc.wp[1], SB1, 32,
-                                        (((func & 0x3) != 0) || SB1_s));
                         goto update_regs;
 
                 default:
@@ -630,9 +660,27 @@ update_ccr:
         regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
 
 update_regs:
-        __FPU_FPSCR &= ~FP_EX_MASK;
+        /*
+         * If the "invalid" exception sticky bit was set by the
+         * processor for non-finite input, but was not set before the
+         * instruction being emulated, clear it.  Likewise for the
+         * "underflow" bit, which may have been set by the processor
+         * for exact underflow, not just inexact underflow when the
+         * flag should be set for IEEE 754 semantics.  Other sticky
+         * exceptions will only be set by the processor when they are
+         * correct according to IEEE 754 semantics, and we must not
+         * clear sticky bits that were already set before the emulated
+         * instruction as they represent the user-visible sticky
+         * exception status.  "inexact" traps to kernel are not
+         * required for IEEE semantics and are not enabled by default,
+         * so the "inexact" sticky bit may have been set by a previous
+         * instruction without the kernel being aware of it.
+         */
+        __FPU_FPSCR
+          &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;
         __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
         mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
+        current->thread.spefscr_last = __FPU_FPSCR;
 
         current->thread.evr[fc] = vc.wp[0];
         regs->gpr[fc] = vc.wp[1];
@@ -644,6 +692,23 @@ update_regs:
         pr_debug("va: %08x  %08x\n", va.wp[0], va.wp[1]);
         pr_debug("vb: %08x  %08x\n", vb.wp[0], vb.wp[1]);
 
+        if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
+                if ((FP_CUR_EXCEPTIONS & FP_EX_DIVZERO)
+                    && (current->thread.fpexc_mode & PR_FP_EXC_DIV))
+                        return 1;
+                if ((FP_CUR_EXCEPTIONS & FP_EX_OVERFLOW)
+                    && (current->thread.fpexc_mode & PR_FP_EXC_OVF))
+                        return 1;
+                if ((FP_CUR_EXCEPTIONS & FP_EX_UNDERFLOW)
+                    && (current->thread.fpexc_mode & PR_FP_EXC_UND))
+                        return 1;
+                if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT)
+                    && (current->thread.fpexc_mode & PR_FP_EXC_RES))
+                        return 1;
+                if ((FP_CUR_EXCEPTIONS & FP_EX_INVALID)
+                    && (current->thread.fpexc_mode & PR_FP_EXC_INV))
+                        return 1;
+        }
         return 0;
 
 illegal:
@@ -662,21 +727,28 @@ int speround_handler(struct pt_regs *regs)
 {
         union dw_union fgpr;
         int s_lo, s_hi;
-        unsigned long speinsn, type, fc;
+        int lo_inexact, hi_inexact;
+        int fp_result;
+        unsigned long speinsn, type, fb, fc, fptype, func;
 
         if (get_user(speinsn, (unsigned int __user *) regs->nip))
                 return -EFAULT;
         if ((speinsn >> 26) != 4)
                 return -EINVAL;         /* not an spe instruction */
 
-        type = insn_type(speinsn & 0x7ff);
+        func = speinsn & 0x7ff;
+        type = insn_type(func);
         if (type == XCR) return -ENOSYS;
 
         __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
         pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
 
+        fptype = (speinsn >> 5) & 0x7;
+
         /* No need to round if the result is exact */
-        if (!(__FPU_FPSCR & FP_EX_INEXACT))
+        lo_inexact = __FPU_FPSCR & (SPEFSCR_FG | SPEFSCR_FX);
+        hi_inexact = __FPU_FPSCR & (SPEFSCR_FGH | SPEFSCR_FXH);
+        if (!(lo_inexact || (hi_inexact && fptype == VCT)))
                 return 0;
 
         fc = (speinsn >> 21) & 0x1f;
@@ -685,9 +757,68 @@ int speround_handler(struct pt_regs *regs)
         fgpr.wp[0] = current->thread.evr[fc];
         fgpr.wp[1] = regs->gpr[fc];
 
+        fb = (speinsn >> 11) & 0x1f;
+        switch (func) {
+        case EFSCTUIZ:
+        case EFSCTSIZ:
+        case EVFSCTUIZ:
+        case EVFSCTSIZ:
+        case EFDCTUIDZ:
+        case EFDCTSIDZ:
+        case EFDCTUIZ:
+        case EFDCTSIZ:
+                /*
+                 * These instructions always round to zero,
+                 * independent of the rounding mode.
+                 */
+                return 0;
+
+        case EFSCTUI:
+        case EFSCTUF:
+        case EVFSCTUI:
+        case EVFSCTUF:
+        case EFDCTUI:
+        case EFDCTUF:
+                fp_result = 0;
+                s_lo = 0;
+                s_hi = 0;
+                break;
+
+        case EFSCTSI:
+        case EFSCTSF:
+                fp_result = 0;
+                /* Recover the sign of a zero result if possible.  */
+                if (fgpr.wp[1] == 0)
+                        s_lo = regs->gpr[fb] & SIGN_BIT_S;
+                break;
+
+        case EVFSCTSI:
+        case EVFSCTSF:
+                fp_result = 0;
+                /* Recover the sign of a zero result if possible.  */
+                if (fgpr.wp[1] == 0)
+                        s_lo = regs->gpr[fb] & SIGN_BIT_S;
+                if (fgpr.wp[0] == 0)
+                        s_hi = current->thread.evr[fb] & SIGN_BIT_S;
+                break;
+
+        case EFDCTSI:
+        case EFDCTSF:
+                fp_result = 0;
+                s_hi = s_lo;
+                /* Recover the sign of a zero result if possible.  */
+                if (fgpr.wp[1] == 0)
+                        s_hi = current->thread.evr[fb] & SIGN_BIT_S;
+                break;
+
+        default:
+                fp_result = 1;
+                break;
+        }
+
         pr_debug("round fgpr: %08x  %08x\n", fgpr.wp[0], fgpr.wp[1]);
 
-        switch ((speinsn >> 5) & 0x7) {
+        switch (fptype) {
         /* Since SPE instructions on E500 core can handle round to nearest
          * and round toward zero with IEEE-754 complied, we just need
          * to handle round toward +Inf and round toward -Inf by software.
@@ -696,25 +827,52 @@ int speround_handler(struct pt_regs *regs)
                 if ((FP_ROUNDMODE) == FP_RND_PINF) {
                         if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
                 } else { /* round to -Inf */
-                        if (s_lo) fgpr.wp[1]++; /* Z < 0, choose Z2 */
+                        if (s_lo) {
+                                if (fp_result)
+                                        fgpr.wp[1]++; /* Z < 0, choose Z2 */
+                                else
+                                        fgpr.wp[1]--; /* Z < 0, choose Z2 */
+                        }
                 }
                 break;
 
         case DPFP:
                 if (FP_ROUNDMODE == FP_RND_PINF) {
-                        if (!s_hi) fgpr.dp[0]++; /* Z > 0, choose Z1 */
+                        if (!s_hi) {
+                                if (fp_result)
+                                        fgpr.dp[0]++; /* Z > 0, choose Z1 */
+                                else
+                                        fgpr.wp[1]++; /* Z > 0, choose Z1 */
+                        }
                 } else { /* round to -Inf */
-                        if (s_hi) fgpr.dp[0]++; /* Z < 0, choose Z2 */
+                        if (s_hi) {
+                                if (fp_result)
+                                        fgpr.dp[0]++; /* Z < 0, choose Z2 */
+                                else
+                                        fgpr.wp[1]--; /* Z < 0, choose Z2 */
+                        }
                 }
                 break;
 
         case VCT:
                 if (FP_ROUNDMODE == FP_RND_PINF) {
-                        if (!s_lo) fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
-                        if (!s_hi) fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
+                        if (lo_inexact && !s_lo)
+                                fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
+                        if (hi_inexact && !s_hi)
+                                fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
                 } else { /* round to -Inf */
-                        if (s_lo) fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
-                        if (s_hi) fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
+                        if (lo_inexact && s_lo) {
+                                if (fp_result)
+                                        fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
+                                else
+                                        fgpr.wp[1]--; /* Z_low < 0, choose Z2 */
+                        }
+                        if (hi_inexact && s_hi) {
+                                if (fp_result)
+                                        fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
+                                else
+                                        fgpr.wp[0]--; /* Z_high < 0, choose Z2 */
+                        }
                 }
                 break;
 
@@ -727,6 +885,8 @@ int speround_handler(struct pt_regs *regs)
 
         pr_debug("  to fgpr: %08x  %08x\n", fgpr.wp[0], fgpr.wp[1]);
 
+        if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
+                return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0;
         return 0;
 }
 
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 07ba45b0f07c..94cd728166d3 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -52,6 +52,7 @@
 #include <asm/smp.h>
 #include <asm/machdep.h>
 #include <asm/setup.h>
+#include <asm/paca.h>
 
 #include "mmu_decl.h"
 
@@ -171,11 +172,10 @@ unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
         return 1UL << camsize;
 }
 
-unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
+static unsigned long map_mem_in_cams_addr(phys_addr_t phys, unsigned long virt,
+                                        unsigned long ram, int max_cam_idx)
 {
         int i;
-        unsigned long virt = PAGE_OFFSET;
-        phys_addr_t phys = memstart_addr;
         unsigned long amount_mapped = 0;
 
         /* Calculate CAM values */
@@ -192,9 +192,23 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
         }
         tlbcam_index = i;
 
+#ifdef CONFIG_PPC64
+        get_paca()->tcd.esel_next = i;
+        get_paca()->tcd.esel_max = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+        get_paca()->tcd.esel_first = i;
+#endif
+
         return amount_mapped;
 }
 
+unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
+{
+        unsigned long virt = PAGE_OFFSET;
+        phys_addr_t phys = memstart_addr;
+
+        return map_mem_in_cams_addr(phys, virt, ram, max_cam_idx);
+}
+
 #ifdef CONFIG_PPC32
 
 #if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
@@ -222,7 +236,9 @@ void __init adjust_total_lowmem(void)
         /* adjust lowmem size to __max_low_memory */
         ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
 
+        i = switch_to_as1();
         __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM);
+        restore_to_as0(i, 0, 0, 1);
 
         pr_info("Memory CAM mapping: ");
         for (i = 0; i < tlbcam_index - 1; i++)
@@ -241,4 +257,62 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
         /* 64M mapped initially according to head_fsl_booke.S */
         memblock_set_current_limit(min_t(u64, limit, 0x04000000));
 }
+
+#ifdef CONFIG_RELOCATABLE
+int __initdata is_second_reloc;
+notrace void __init relocate_init(u64 dt_ptr, phys_addr_t start)
+{
+        unsigned long base = KERNELBASE;
+
+        kernstart_addr = start;
+        if (is_second_reloc) {
+                virt_phys_offset = PAGE_OFFSET - memstart_addr;
+                return;
+        }
+
+        /*
+         * Relocatable kernel support based on processing of dynamic
+         * relocation entries. Before we get the real memstart_addr,
+         * We will compute the virt_phys_offset like this:
+         * virt_phys_offset = stext.run - kernstart_addr
+         *
+         * stext.run = (KERNELBASE & ~0x3ffffff) +
+         *                              (kernstart_addr & 0x3ffffff)
+         * When we relocate, we have :
+         *
+         *      (kernstart_addr & 0x3ffffff) = (stext.run & 0x3ffffff)
+         *
+         * hence:
+         *  virt_phys_offset = (KERNELBASE & ~0x3ffffff) -
+         *                              (kernstart_addr & ~0x3ffffff)
+         *
+         */
+        start &= ~0x3ffffff;
+        base &= ~0x3ffffff;
+        virt_phys_offset = base - start;
+        early_get_first_memblock_info(__va(dt_ptr), NULL);
+        /*
+         * We now get the memstart_addr, then we should check if this
+         * address is the same as what the PAGE_OFFSET map to now. If
+         * not we have to change the map of PAGE_OFFSET to memstart_addr
+         * and do a second relocation.
+         */
+        if (start != memstart_addr) {
+                int n;
+                long offset = start - memstart_addr;
+
+                is_second_reloc = 1;
+                n = switch_to_as1();
+                /* map a 64M area for the second relocation */
+                if (memstart_addr > start)
+                        map_mem_in_cams(0x4000000, CONFIG_LOWMEM_CAM_NUM);
+                else
+                        map_mem_in_cams_addr(start, PAGE_OFFSET + offset,
+                                        0x4000000, CONFIG_LOWMEM_CAM_NUM);
+                restore_to_as0(n, offset, __va(dt_ptr), 1);
+                /* We should never reach here */
+                panic("Relocation error");
+        }
+}
+#endif
 #endif
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index d3cbda62857b..1136d26a95ae 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -148,7 +148,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r30,r0               /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...) 
@@ -457,7 +460,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r3,r0                /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...)
@@ -795,7 +801,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r30,r0               /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 6176b3cdf579..de6881259aef 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -169,9 +169,10 @@ static unsigned long htab_convert_pte_flags(unsigned long pteflags)
         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
                                          (pteflags & _PAGE_DIRTY)))
                 rflags |= 1;
-
-        /* Always add C */
-        return rflags | HPTE_R_C;
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        return rflags | HPTE_R_C | HPTE_R_M;
 }
 
 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
diff --git a/arch/powerpc/mm/hugepage-hash64.c b/arch/powerpc/mm/hugepage-hash64.c
index 34de9e0cdc34..826893fcb3a7 100644
--- a/arch/powerpc/mm/hugepage-hash64.c
+++ b/arch/powerpc/mm/hugepage-hash64.c
@@ -127,7 +127,11 @@ repeat:
 
                 /* Add in WIMG bits */
                 rflags |= (new_pmd & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
-                                      _PAGE_COHERENT | _PAGE_GUARDED));
+                                      _PAGE_GUARDED));
+                /*
+                 * enable the memory coherence always
+                 */
+                rflags |= HPTE_R_M;
 
                 /* Insert into the hash table, primary slot */
                 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 74551b5e41e5..5e4ee2573903 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -8,6 +8,44 @@
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
 
+#ifdef CONFIG_PPC_FSL_BOOK3E
+#ifdef CONFIG_PPC64
+static inline int tlb1_next(void)
+{
+        struct paca_struct *paca = get_paca();
+        struct tlb_core_data *tcd;
+        int this, next;
+
+        tcd = paca->tcd_ptr;
+        this = tcd->esel_next;
+
+        next = this + 1;
+        if (next >= tcd->esel_max)
+                next = tcd->esel_first;
+
+        tcd->esel_next = next;
+        return this;
+}
+#else
+static inline int tlb1_next(void)
+{
+        int index, ncams;
+
+        ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+
+        index = __get_cpu_var(next_tlbcam_idx);
+
+        /* Just round-robin the entries and wrap when we hit the end */
+        if (unlikely(index == ncams - 1))
+                __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
+        else
+                __get_cpu_var(next_tlbcam_idx)++;
+
+        return index;
+}
+#endif /* !PPC64 */
+#endif /* FSL */
+
 static inline int mmu_get_tsize(int psize)
 {
         return mmu_psize_defs[psize].enc;
@@ -47,7 +85,7 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
         struct mm_struct *mm;
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
-        int index, ncams;
+        int index;
 #endif
 
         if (unlikely(is_kernel_addr(ea)))
@@ -77,18 +115,11 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
         }
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
-        ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
-
         /* We have to use the CAM(TLB1) on FSL parts for hugepages */
-        index = __get_cpu_var(next_tlbcam_idx);
+        index = tlb1_next();
         mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1));
-
-        /* Just round-robin the entries and wrap when we hit the end */
-        if (unlikely(index == ncams - 1))
-                __get_cpu_var(next_tlbcam_idx) = tlbcam_index;
-        else
-                __get_cpu_var(next_tlbcam_idx)++;
 #endif
+
         mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize);
         mas2 = ea & ~((1UL << shift) - 1);
         mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
@@ -103,7 +134,8 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
         if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS)) {
                 mtspr(SPRN_MAS7_MAS3, mas7_3);
         } else {
-                mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
+                if (mmu_has_feature(MMU_FTR_BIG_PHYS))
+                        mtspr(SPRN_MAS7, upper_32_bits(mas7_3));
                 mtspr(SPRN_MAS3, lower_32_bits(mas7_3));
         }
 
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 0b7fb6761015..a5bcf9301196 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -99,6 +99,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                 /* Add in WIMG bits */
                 rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
                                       _PAGE_COHERENT | _PAGE_GUARDED));
+                /*
+                 * enable the memory coherence always
+                 */
+                rflags |= HPTE_R_M;
 
                 slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
                                              mmu_psize, ssize);
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 90bb6d9409bf..eb923654ba80 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -472,12 +472,13 @@ static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
 {
         struct hugepd_freelist **batchp;
 
-        batchp = &__get_cpu_var(hugepd_freelist_cur);
+        batchp = &get_cpu_var(hugepd_freelist_cur);
 
         if (atomic_read(&tlb->mm->mm_users) < 2 ||
             cpumask_equal(mm_cpumask(tlb->mm),
                           cpumask_of(smp_processor_id()))) {
                 kmem_cache_free(hugepte_cache, hugepte);
+        put_cpu_var(hugepd_freelist_cur);
                 return;
         }
 
@@ -491,6 +492,7 @@ static void hugepd_free(struct mmu_gather *tlb, void *hugepte)
                 call_rcu_sched(&(*batchp)->rcu, hugepd_free_rcu_callback);
                 *batchp = NULL;
         }
+        put_cpu_var(hugepd_freelist_cur);
 }
 #endif
 
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 3fa93dc7fe75..4b5cd5c2594d 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -209,7 +209,7 @@ void __init do_init_bootmem(void)
         /* Place all memblock_regions in the same node and merge contiguous
          * memblock_regions
          */
-        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
+        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
 
         /* Add all physical memory to the bootmem map, mark each area
          * present.
@@ -307,6 +307,12 @@ static void __init register_page_bootmem_info(void)
 
 void __init mem_init(void)
 {
+        /*
+         * book3s is limited to 16 page sizes due to encoding this in
+         * a 4-bit field for slices.
+         */
+        BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
+
 #ifdef CONFIG_SWIOTLB
         swiotlb_init(0);
 #endif
@@ -507,7 +513,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
  * System memory should not be in /proc/iomem but various tools expect it
  * (eg kdump).
  */
-static int add_system_ram_resources(void)
+static int __init add_system_ram_resources(void)
 {
         struct memblock_region *reg;
 
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 83eb5d5f53d5..9615d82919b8 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -148,6 +148,8 @@ extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(unsigned long top);
 extern void adjust_total_lowmem(void);
+extern int switch_to_as1(void);
+extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
 #endif
 extern void loadcam_entry(unsigned int index);
 
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 078d3e00a616..30a42e24bf14 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -31,6 +31,8 @@
 #include <asm/sparsemem.h>
 #include <asm/prom.h>
 #include <asm/smp.h>
+#include <asm/cputhreads.h>
+#include <asm/topology.h>
 #include <asm/firmware.h>
 #include <asm/paca.h>
 #include <asm/hvcall.h>
@@ -152,9 +154,22 @@ static void __init get_node_active_region(unsigned long pfn,
         }
 }
 
-static void map_cpu_to_node(int cpu, int node)
+static void reset_numa_cpu_lookup_table(void)
+{
+        unsigned int cpu;
+
+        for_each_possible_cpu(cpu)
+                numa_cpu_lookup_table[cpu] = -1;
+}
+
+static void update_numa_cpu_lookup_table(unsigned int cpu, int node)
 {
         numa_cpu_lookup_table[cpu] = node;
+}
+
+static void map_cpu_to_node(int cpu, int node)
+{
+        update_numa_cpu_lookup_table(cpu, node);
 
         dbg("adding cpu %d to node %d\n", cpu, node);
 
@@ -522,11 +537,24 @@ static int of_drconf_to_nid_single(struct of_drconf_cell *drmem,
  */
 static int numa_setup_cpu(unsigned long lcpu)
 {
-        int nid = 0;
-        struct device_node *cpu = of_get_cpu_node(lcpu, NULL);
+        int nid;
+        struct device_node *cpu;
+
+        /*
+         * If a valid cpu-to-node mapping is already available, use it
+         * directly instead of querying the firmware, since it represents
+         * the most recent mapping notified to us by the platform (eg: VPHN).
+         */
+        if ((nid = numa_cpu_lookup_table[lcpu]) >= 0) {
+                map_cpu_to_node(lcpu, nid);
+                return nid;
+        }
+
+        cpu = of_get_cpu_node(lcpu, NULL);
 
         if (!cpu) {
                 WARN_ON(1);
+                nid = 0;
                 goto out;
         }
 
@@ -542,16 +570,38 @@ out:
         return nid;
 }
 
+static void verify_cpu_node_mapping(int cpu, int node)
+{
+        int base, sibling, i;
+
+        /* Verify that all the threads in the core belong to the same node */
+        base = cpu_first_thread_sibling(cpu);
+
+        for (i = 0; i < threads_per_core; i++) {
+                sibling = base + i;
+
+                if (sibling == cpu || cpu_is_offline(sibling))
+                        continue;
+
+                if (cpu_to_node(sibling) != node) {
+                        WARN(1, "CPU thread siblings %d and %d don't belong"
+                                " to the same node!\n", cpu, sibling);
+                        break;
+                }
+        }
+}
+
 static int cpu_numa_callback(struct notifier_block *nfb, unsigned long action,
                              void *hcpu)
 {
         unsigned long lcpu = (unsigned long)hcpu;
-        int ret = NOTIFY_DONE;
+        int ret = NOTIFY_DONE, nid;
 
         switch (action) {
         case CPU_UP_PREPARE:
         case CPU_UP_PREPARE_FROZEN:
-                numa_setup_cpu(lcpu);
+                nid = numa_setup_cpu(lcpu);
+                verify_cpu_node_mapping((int)lcpu, nid);
                 ret = NOTIFY_OK;
                 break;
 #ifdef CONFIG_HOTPLUG_CPU
@@ -670,7 +720,8 @@ static void __init parse_drconf_memory(struct device_node *memory)
                         node_set_online(nid);
                         sz = numa_enforce_memory_limit(base, size);
                         if (sz)
-                                memblock_set_node(base, sz, nid);
+                                memblock_set_node(base, sz,
+                                                  &memblock.memory, nid);
                 } while (--ranges);
         }
 }
@@ -760,7 +811,7 @@ new_range:
                                 continue;
                 }
 
-                memblock_set_node(start, size, nid);
+                memblock_set_node(start, size, &memblock.memory, nid);
 
                 if (--ranges)
                         goto new_range;
@@ -797,7 +848,8 @@ static void __init setup_nonnuma(void)
 
                 fake_numa_create_new_node(end_pfn, &nid);
                 memblock_set_node(PFN_PHYS(start_pfn),
-                                  PFN_PHYS(end_pfn - start_pfn), nid);
+                                  PFN_PHYS(end_pfn - start_pfn),
+                                  &memblock.memory, nid);
                 node_set_online(nid);
         }
 }
@@ -1067,6 +1119,7 @@ void __init do_init_bootmem(void)
          */
         setup_node_to_cpumask_map();
 
+        reset_numa_cpu_lookup_table();
         register_cpu_notifier(&ppc64_numa_nb);
         cpu_numa_callback(&ppc64_numa_nb, CPU_UP_PREPARE,
                           (void *)(unsigned long)boot_cpuid);
@@ -1445,6 +1498,33 @@ static int update_cpu_topology(void *data)
         return 0;
 }
 
+static int update_lookup_table(void *data)
+{
+        struct topology_update_data *update;
+
+        if (!data)
+                return -EINVAL;
+
+        /*
+         * Upon topology update, the numa-cpu lookup table needs to be updated
+         * for all threads in the core, including offline CPUs, to ensure that
+         * future hotplug operations respect the cpu-to-node associativity
+         * properly.
+         */
+        for (update = data; update; update = update->next) {
+                int nid, base, j;
+
+                nid = update->new_nid;
+                base = cpu_first_thread_sibling(update->cpu);
+
+                for (j = 0; j < threads_per_core; j++) {
+                        update_numa_cpu_lookup_table(base + j, nid);
+                }
+        }
+
+        return 0;
+}
+
 /*
  * Update the node maps and sysfs entries for each cpu whose home node
  * has changed. Returns 1 when the topology has changed, and 0 otherwise.
@@ -1513,6 +1593,14 @@ int arch_update_cpu_topology(void)
 
         stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
 
+        /*
+         * Update the numa-cpu lookup table with the new mappings, even for
+         * offline CPUs. It is best to perform this update from the stop-
+         * machine context.
+         */
+        stop_machine(update_lookup_table, &updates[0],
+                                        cpumask_of(raw_smp_processor_id()));
+
         for (ud = &updates[0]; ud; ud = ud->next) {
                 unregister_cpu_under_node(ud->cpu, ud->old_nid);
                 register_cpu_under_node(ud->cpu, ud->new_nid);
@@ -1697,7 +1785,7 @@ static const struct file_operations topology_ops = {
 static int topology_update_init(void)
 {
         start_topology_update();
-        proc_create("powerpc/topology_updates", 644, NULL, &topology_ops);
+        proc_create("powerpc/topology_updates", 0644, NULL, &topology_ops);
 
         return 0;
 }
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 841e0d00863c..c695943a513c 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -24,7 +24,6 @@
 #include <linux/kernel.h>
 #include <linux/gfp.h>
 #include <linux/mm.h>
-#include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/hardirq.h>
 #include <linux/hugetlb.h>
@@ -174,7 +173,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
                 pte_t pte)
 {
 #ifdef CONFIG_DEBUG_VM
-        WARN_ON(pte_present(*ptep));
+        WARN_ON(pte_val(*ptep) & _PAGE_PRESENT);
 #endif
         /* Note: mm->context.id might not yet have been assigned as
          * this context might not have been activated yet when this
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 5b9601715289..343a87fa78b5 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -299,6 +299,7 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
                 set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT,
                                                      __pgprot(flags)));
         }
+        smp_wmb();
         return err;
 }
 
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 9d95786aa80f..65b7b65e8708 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -33,7 +33,6 @@
 #include <linux/swap.h>
 #include <linux/stddef.h>
 #include <linux/vmalloc.h>
-#include <linux/init.h>
 #include <linux/bootmem.h>
 #include <linux/memblock.h>
 #include <linux/slab.h>
@@ -153,6 +152,18 @@ int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
                 }
 #endif /* !CONFIG_PPC_MMU_NOHASH */
         }
+
+#ifdef CONFIG_PPC_BOOK3E_64
+        /*
+         * With hardware tablewalk, a sync is needed to ensure that
+         * subsequent accesses see the PTE we just wrote.  Unlike userspace
+         * mappings, we can't tolerate spurious faults, so make sure
+         * the new PTE will be seen the first time.
+         */
+        mb();
+#else
+        smp_wmb();
+#endif
         return 0;
 }
 
@@ -687,7 +698,7 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
                 pmd_t *pmdp, pmd_t pmd)
 {
 #ifdef CONFIG_DEBUG_VM
-        WARN_ON(!pmd_none(*pmdp));
+        WARN_ON(pmd_val(*pmdp) & _PAGE_PRESENT);
         assert_spin_locked(&mm->page_table_lock);
         WARN_ON(!pmd_trans_huge(pmd));
 #endif
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 7ce9cf3b6988..b0c75cc15efc 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -408,7 +408,7 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
         if (fixed && (addr & ((1ul << pshift) - 1)))
                 return -EINVAL;
         if (fixed && addr > (mm->task_size - len))
-                return -EINVAL;
+                return -ENOMEM;
 
         /* If hint, make sure it matches our alignment restrictions */
         if (!fixed && addr) {
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 36e44b4260eb..c99f6510a0b2 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -23,7 +23,6 @@
 
 #include <linux/kernel.h>
 #include <linux/mm.h>
-#include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/hardirq.h>
 #include <asm/pgalloc.h>
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index b4113bf86353..c95eb323e9ae 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -136,7 +136,7 @@ BEGIN_MMU_FTR_SECTION
          */
         PPC_TLBSRX_DOT(0,R16)
         ldx     r14,r14,r15             /* grab pgd entry */
-        beq     normal_tlb_miss_done    /* tlb exists already, bail */
+        beq     tlb_miss_done_bolted    /* tlb exists already, bail */
 MMU_FTR_SECTION_ELSE
         ldx     r14,r14,r15             /* grab pgd entry */
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
@@ -192,6 +192,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
         mtspr   SPRN_MAS7_MAS3,r15
         tlbwe
 
+tlb_miss_done_bolted:
         TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
         tlb_epilog_bolted
         rfi
@@ -239,6 +240,178 @@ itlb_miss_fault_bolted:
         beq     tlb_miss_common_bolted
         b       itlb_miss_kernel_bolted
 
+#ifdef CONFIG_PPC_FSL_BOOK3E
+/*
+ * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
+ *
+ * Linear mapping is bolted: no virtual page table or nested TLB misses
+ * Indirect entries in TLB1, hardware loads resulting direct entries
+ *    into TLB0
+ * No HES or NV hint on TLB1, so we need to do software round-robin
+ * No tlbsrx. so we need a spinlock, and we have to deal
+ *    with MAS-damage caused by tlbsx
+ * 4K pages only
+ */
+
+        START_EXCEPTION(instruction_tlb_miss_e6500)
+        tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
+
+        ld      r11,PACA_TCD_PTR(r13)
+        srdi.   r15,r16,60              /* get region */
+        ori     r16,r16,1
+
+        TLB_MISS_STATS_SAVE_INFO_BOLTED
+        bne     tlb_miss_kernel_e6500   /* user/kernel test */
+
+        b       tlb_miss_common_e6500
+
+        START_EXCEPTION(data_tlb_miss_e6500)
+        tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
+
+        ld      r11,PACA_TCD_PTR(r13)
+        srdi.   r15,r16,60              /* get region */
+        rldicr  r16,r16,0,62
+
+        TLB_MISS_STATS_SAVE_INFO_BOLTED
+        bne     tlb_miss_kernel_e6500   /* user vs kernel check */
+
+/*
+ * This is the guts of the TLB miss handler for e6500 and derivatives.
+ * We are entered with:
+ *
+ * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
+ * r15 = crap (free to use)
+ * r14 = page table base
+ * r13 = PACA
+ * r11 = tlb_per_core ptr
+ * r10 = crap (free to use)
+ */
+tlb_miss_common_e6500:
+        /*
+         * Search if we already have an indirect entry for that virtual
+         * address, and if we do, bail out.
+         *
+         * MAS6:IND should be already set based on MAS4
+         */
+        addi    r10,r11,TCD_LOCK
+1:      lbarx   r15,0,r10
+        cmpdi   r15,0
+        bne     2f
+        li      r15,1
+        stbcx.  r15,0,r10
+        bne     1b
+        .subsection 1
+2:      lbz     r15,0(r10)
+        cmpdi   r15,0
+        bne     2b
+        b       1b
+        .previous
+
+        mfspr   r15,SPRN_MAS2
+
+        tlbsx   0,r16
+        mfspr   r10,SPRN_MAS1
+        andis.  r10,r10,MAS1_VALID@h
+        bne     tlb_miss_done_e6500
+
+        /* Undo MAS-damage from the tlbsx */
+        mfspr   r10,SPRN_MAS1
+        oris    r10,r10,MAS1_VALID@h
+        mtspr   SPRN_MAS1,r10
+        mtspr   SPRN_MAS2,r15
+
+        /* Now, we need to walk the page tables. First check if we are in
+         * range.
+         */
+        rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
+        bne-    tlb_miss_fault_e6500
+
+        rldicl  r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
+        cmpldi  cr0,r14,0
+        clrrdi  r15,r15,3
+        beq-    tlb_miss_fault_e6500 /* No PGDIR, bail */
+        ldx     r14,r14,r15             /* grab pgd entry */
+
+        rldicl  r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
+        clrrdi  r15,r15,3
+        cmpdi   cr0,r14,0
+        bge     tlb_miss_fault_e6500    /* Bad pgd entry or hugepage; bail */
+        ldx     r14,r14,r15             /* grab pud entry */
+
+        rldicl  r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
+        clrrdi  r15,r15,3
+        cmpdi   cr0,r14,0
+        bge     tlb_miss_fault_e6500
+        ldx     r14,r14,r15             /* Grab pmd entry */
+
+        mfspr   r10,SPRN_MAS0
+        cmpdi   cr0,r14,0
+        bge     tlb_miss_fault_e6500
+
+        /* Now we build the MAS for a 2M indirect page:
+         *
+         * MAS 0   :    ESEL needs to be filled by software round-robin
+         * MAS 1   :    Fully set up
+         *               - PID already updated by caller if necessary
+         *               - TSIZE for now is base ind page size always
+         *               - TID already cleared if necessary
+         * MAS 2   :    Default not 2M-aligned, need to be redone
+         * MAS 3+7 :    Needs to be done
+         */
+
+        ori     r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
+        mtspr   SPRN_MAS7_MAS3,r14
+
+        clrrdi  r15,r16,21              /* make EA 2M-aligned */
+        mtspr   SPRN_MAS2,r15
+
+        lbz     r15,TCD_ESEL_NEXT(r11)
+        lbz     r16,TCD_ESEL_MAX(r11)
+        lbz     r14,TCD_ESEL_FIRST(r11)
+        rlwimi  r10,r15,16,0x00ff0000   /* insert esel_next into MAS0 */
+        addi    r15,r15,1               /* increment esel_next */
+        mtspr   SPRN_MAS0,r10
+        cmpw    r15,r16
+        iseleq  r15,r14,r15             /* if next == last use first */
+        stb     r15,TCD_ESEL_NEXT(r11)
+
+        tlbwe
+
+tlb_miss_done_e6500:
+        .macro  tlb_unlock_e6500
+        li      r15,0
+        isync
+        stb     r15,TCD_LOCK(r11)
+        .endm
+
+        tlb_unlock_e6500
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
+        tlb_epilog_bolted
+        rfi
+
+tlb_miss_kernel_e6500:
+        mfspr   r10,SPRN_MAS1
+        ld      r14,PACA_KERNELPGD(r13)
+        cmpldi  cr0,r15,8               /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1          /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        beq+    tlb_miss_common_e6500
+
+tlb_miss_fault_e6500:
+        tlb_unlock_e6500
+        /* We need to check if it was an instruction miss */
+        andi.   r16,r16,1
+        bne     itlb_miss_fault_e6500
+dtlb_miss_fault_e6500:
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        tlb_epilog_bolted
+        b       exc_data_storage_book3e
+itlb_miss_fault_e6500:
+        TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        tlb_epilog_bolted
+        b       exc_instruction_storage_book3e
+#endif /* CONFIG_PPC_FSL_BOOK3E */
+
 /**********************************************************************
  *                                                                    *
  * TLB miss handling for Book3E with TLB reservation and HES support  *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 358d74303138..b37a58e1c92d 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -43,6 +43,7 @@
 #include <asm/tlb.h>
 #include <asm/code-patching.h>
 #include <asm/hugetlb.h>
+#include <asm/paca.h>
 
 #include "mmu_decl.h"
 
@@ -58,6 +59,10 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
                 .shift  = 12,
                 .enc    = BOOK3E_PAGESZ_4K,
         },
+        [MMU_PAGE_2M] = {
+                .shift  = 21,
+                .enc    = BOOK3E_PAGESZ_2M,
+        },
         [MMU_PAGE_4M] = {
                 .shift  = 22,
                 .enc    = BOOK3E_PAGESZ_4M,
@@ -136,7 +141,7 @@ static inline int mmu_get_tsize(int psize)
 int mmu_linear_psize;           /* Page size used for the linear mapping */
 int mmu_pte_psize;              /* Page size used for PTE pages */
 int mmu_vmemmap_psize;          /* Page size used for the virtual mem map */
-int book3e_htw_enabled;         /* Is HW tablewalk enabled ? */
+int book3e_htw_mode;            /* HW tablewalk?  Value is PPC_HTW_* */
 unsigned long linear_map_top;   /* Top of linear mapping */
 
 #endif /* CONFIG_PPC64 */
@@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
 {
         int tsize = mmu_psize_defs[mmu_pte_psize].enc;
 
-        if (book3e_htw_enabled) {
+        if (book3e_htw_mode != PPC_HTW_NONE) {
                 unsigned long start = address & PMD_MASK;
                 unsigned long end = address + PMD_SIZE;
                 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
@@ -430,7 +435,7 @@ static void setup_page_sizes(void)
                         def = &mmu_psize_defs[psize];
                         shift = def->shift;
 
-                        if (shift == 0)
+                        if (shift == 0 || shift & 1)
                                 continue;
 
                         /* adjust to be in terms of 4^shift Kb */
@@ -440,21 +445,40 @@ static void setup_page_sizes(void)
                                 def->flags |= MMU_PAGE_SIZE_DIRECT;
                 }
 
-                goto no_indirect;
+                goto out;
         }
 
         if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
-                u32 tlb1ps = mfspr(SPRN_TLB1PS);
+                u32 tlb1cfg, tlb1ps;
+
+                tlb0cfg = mfspr(SPRN_TLB0CFG);
+                tlb1cfg = mfspr(SPRN_TLB1CFG);
+                tlb1ps = mfspr(SPRN_TLB1PS);
+                eptcfg = mfspr(SPRN_EPTCFG);
+
+                if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
+                        book3e_htw_mode = PPC_HTW_E6500;
+
+                /*
+                 * We expect 4K subpage size and unrestricted indirect size.
+                 * The lack of a restriction on indirect size is a Freescale
+                 * extension, indicated by PSn = 0 but SPSn != 0.
+                 */
+                if (eptcfg != 2)
+                        book3e_htw_mode = PPC_HTW_NONE;
 
                 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
                         struct mmu_psize_def *def = &mmu_psize_defs[psize];
 
                         if (tlb1ps & (1U << (def->shift - 10))) {
                                 def->flags |= MMU_PAGE_SIZE_DIRECT;
+
+                                if (book3e_htw_mode && psize == MMU_PAGE_2M)
+                                        def->flags |= MMU_PAGE_SIZE_INDIRECT;
                         }
                 }
 
-                goto no_indirect;
+                goto out;
         }
 #endif
 
@@ -471,8 +495,11 @@ static void setup_page_sizes(void)
         }
 
         /* Indirect page sizes supported ? */
-        if ((tlb0cfg & TLBnCFG_IND) == 0)
-                goto no_indirect;
+        if ((tlb0cfg & TLBnCFG_IND) == 0 ||
+            (tlb0cfg & TLBnCFG_PT) == 0)
+                goto out;
+
+        book3e_htw_mode = PPC_HTW_IBM;
 
         /* Now, we only deal with one IND page size for each
          * direct size. Hopefully all implementations today are
@@ -497,8 +524,8 @@ static void setup_page_sizes(void)
                                 def->ind = ps + 10;
                 }
         }
- no_indirect:
 
+out:
         /* Cleanup array and print summary */
         pr_info("MMU: Supported page sizes\n");
         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
@@ -518,44 +545,27 @@ static void setup_page_sizes(void)
         }
 }
 
-static void __patch_exception(int exc, unsigned long addr)
-{
-        extern unsigned int interrupt_base_book3e;
-        unsigned int *ibase = &interrupt_base_book3e;
- 
-        /* Our exceptions vectors start with a NOP and -then- a branch
-         * to deal with single stepping from userspace which stops on
-         * the second instruction. Thus we need to patch the second
-         * instruction of the exception, not the first one
-         */
-
-        patch_branch(ibase + (exc / 4) + 1, addr, 0);
-}
-
-#define patch_exception(exc, name) do { \
-        extern unsigned int name; \
-        __patch_exception((exc), (unsigned long)&name); \
-} while (0)
-
 static void setup_mmu_htw(void)
 {
-        /* Check if HW tablewalk is present, and if yes, enable it by:
-         *
-         * - patching the TLB miss handlers to branch to the
-         *   one dedicates to it
-         *
-         * - setting the global book3e_htw_enabled
-         */
-        unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+        /*
+         * If we want to use HW tablewalk, enable it by patching the TLB miss
+         * handlers to branch to the one dedicated to it.
+         */
 
-        if ((tlb0cfg & TLBnCFG_IND) &&
-            (tlb0cfg & TLBnCFG_PT)) {
+        switch (book3e_htw_mode) {
+        case PPC_HTW_IBM:
                 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
                 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
-                book3e_htw_enabled = 1;
+                break;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+        case PPC_HTW_E6500:
+                patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
+                patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
+                break;
+#endif
         }
         pr_info("MMU: Book3E HW tablewalk %s\n",
-                book3e_htw_enabled ? "enabled" : "not supported");
+                book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
 }
 
 /*
@@ -595,8 +605,16 @@ static void __early_init_mmu(int boot_cpu)
         /* Set MAS4 based on page table setting */
 
         mas4 = 0x4 << MAS4_WIMGED_SHIFT;
-        if (book3e_htw_enabled) {
-                mas4 |= mas4 | MAS4_INDD;
+        switch (book3e_htw_mode) {
+        case PPC_HTW_E6500:
+                mas4 |= MAS4_INDD;
+                mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
+                mas4 |= MAS4_TLBSELD(1);
+                mmu_pte_psize = MMU_PAGE_2M;
+                break;
+
+        case PPC_HTW_IBM:
+                mas4 |= MAS4_INDD;
 #ifdef CONFIG_PPC_64K_PAGES
                 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
                 mmu_pte_psize = MMU_PAGE_256M;
@@ -604,13 +622,16 @@ static void __early_init_mmu(int boot_cpu)
                 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
                 mmu_pte_psize = MMU_PAGE_1M;
 #endif
-        } else {
+                break;
+
+        case PPC_HTW_NONE:
 #ifdef CONFIG_PPC_64K_PAGES
                 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
 #else
                 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
 #endif
                 mmu_pte_psize = mmu_virtual_psize;
+                break;
         }
         mtspr(SPRN_MAS4, mas4);
 
@@ -630,8 +651,11 @@ static void __early_init_mmu(int boot_cpu)
                 /* limit memory so we dont have linear faults */
                 memblock_enforce_memory_limit(linear_map_top);
 
-                patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
-                patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
+                if (book3e_htw_mode == PPC_HTW_NONE) {
+                        patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
+                        patch_exception(0x1e0,
+                                exc_instruction_tlb_miss_bolted_book3e);
+                }
         }
 #endif
 
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 626ad081639f..43ff3c797fbf 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -402,7 +402,9 @@ _GLOBAL(set_context)
  * Load TLBCAM[index] entry in to the L2 CAM MMU
  */
 _GLOBAL(loadcam_entry)
-        LOAD_REG_ADDR(r4, TLBCAM)
+        mflr    r5
+        LOAD_REG_ADDR_PIC(r4, TLBCAM)
+        mtlr    r5
         mulli   r5,r3,TLBCAM_SIZE
         add     r3,r5,r4
         lwz     r4,TLBCAM_MAS0(r3)
diff --git a/arch/powerpc/oprofile/op_model_7450.c b/arch/powerpc/oprofile/op_model_7450.c
index ff617246d128..d29b6e4e5e72 100644
--- a/arch/powerpc/oprofile/op_model_7450.c
+++ b/arch/powerpc/oprofile/op_model_7450.c
@@ -16,7 +16,6 @@
  */
 
 #include <linux/oprofile.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index b9589c19ccda..1f0ebdeea5f7 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -16,7 +16,6 @@
 
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/kthread.h>
 #include <linux/oprofile.h>
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c
index 2a82d3ed464d..14cf86fdddab 100644
--- a/arch/powerpc/oprofile/op_model_fsl_emb.c
+++ b/arch/powerpc/oprofile/op_model_fsl_emb.c
@@ -14,7 +14,6 @@
  */
 
 #include <linux/oprofile.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/oprofile/op_model_pa6t.c b/arch/powerpc/oprofile/op_model_pa6t.c
index 42f778dff919..a114a7c22d40 100644
--- a/arch/powerpc/oprofile/op_model_pa6t.c
+++ b/arch/powerpc/oprofile/op_model_pa6t.c
@@ -22,7 +22,6 @@
  */
 
 #include <linux/oprofile.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/percpu.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index f444b94935f5..962fe7b3e3fb 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -10,7 +10,6 @@
  */
 
 #include <linux/oprofile.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 #include <asm/firmware.h>
 #include <asm/ptrace.h>
diff --git a/arch/powerpc/oprofile/op_model_rs64.c b/arch/powerpc/oprofile/op_model_rs64.c
index 9b801b8c8c5a..7e5b8ed3a1b7 100644
--- a/arch/powerpc/oprofile/op_model_rs64.c
+++ b/arch/powerpc/oprofile/op_model_rs64.c
@@ -8,7 +8,6 @@
  */
 
 #include <linux/oprofile.h>
-#include <linux/init.h>
 #include <linux/smp.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cbfcb1d..5aa3f4b5332c 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,9 @@
 config PPC_MPC512x
         bool "512x-based boards"
         depends on 6xx
+        select COMMON_CLK
         select FSL_SOC
         select IPIC
-        select PPC_CLOCK
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 72fb9340e09f..01693121a2b1 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,8 @@
 #
 # Makefile for the Freescale PowerPC 512x linux kernel.
 #
-obj-y                           += clock.o mpc512x_shared.o
+obj-$(CONFIG_COMMON_CLK)        += clock-commonclk.o
+obj-y                           += mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)       += mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC512x_GENERIC)   += mpc512x_generic.o
 obj-$(CONFIG_PDM360NG)          += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
new file mode 100644
index 000000000000..6eb614a271fb
--- /dev/null
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -0,0 +1,1221 @@
+/*
+ * Copyright (C) 2013 DENX Software Engineering
+ *
+ * Gerhard Sittig, <gsi@denx.de>
+ *
+ * common clock driver support for the MPC512x platform
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/mpc5121.h>
+#include <dt-bindings/clock/mpc512x-clock.h>
+
+#include "mpc512x.h"            /* our public mpc5121_clk_init() API */
+
+/* helpers to keep the MCLK intermediates "somewhere" in our table */
+enum {
+        MCLK_IDX_MUX0,
+        MCLK_IDX_EN0,
+        MCLK_IDX_DIV0,
+        MCLK_MAX_IDX,
+};
+
+#define NR_PSCS                 12
+#define NR_MSCANS               4
+#define NR_SPDIFS               1
+#define NR_OUTCLK               4
+#define NR_MCLKS                (NR_PSCS + NR_MSCANS + NR_SPDIFS + NR_OUTCLK)
+
+/* extend the public set of clocks by adding internal slots for management */
+enum {
+        /* arrange for adjacent numbers after the public set */
+        MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
+        /* clocks which aren't announced to the public */
+        MPC512x_CLK_DDR,
+        MPC512x_CLK_MEM,
+        MPC512x_CLK_IIM,
+        /* intermediates in div+gate combos or fractional dividers */
+        MPC512x_CLK_DDR_UG,
+        MPC512x_CLK_SDHC_x4,
+        MPC512x_CLK_SDHC_UG,
+        MPC512x_CLK_SDHC2_UG,
+        MPC512x_CLK_DIU_x4,
+        MPC512x_CLK_DIU_UG,
+        MPC512x_CLK_MBX_BUS_UG,
+        MPC512x_CLK_MBX_UG,
+        MPC512x_CLK_MBX_3D_UG,
+        MPC512x_CLK_PCI_UG,
+        MPC512x_CLK_NFC_UG,
+        MPC512x_CLK_LPC_UG,
+        MPC512x_CLK_SPDIF_TX_IN,
+        /* intermediates for the mux+gate+div+mux MCLK generation */
+        MPC512x_CLK_MCLKS_FIRST,
+        MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
+                                + NR_MCLKS * MCLK_MAX_IDX,
+        /* internal, symbolic spec for the number of slots */
+        MPC512x_CLK_LAST_PRIVATE,
+};
+
+/* data required for the OF clock provider registration */
+static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
+static struct clk_onecell_data clk_data;
+
+/* CCM register access */
+static struct mpc512x_ccm __iomem *clkregs;
+static DEFINE_SPINLOCK(clklock);
+
+/* SoC variants {{{ */
+
+/*
+ * tell SoC variants apart as they are rather similar yet not identical,
+ * cache the result in an enum to not repeatedly run the expensive OF test
+ *
+ * MPC5123 is an MPC5121 without the MBX graphics accelerator
+ *
+ * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF,
+ * no PATA, no SATA, no PCI, two FECs (of different compatibility name),
+ * only 10 PSCs (of different compatibility name), two SDHCs, different
+ * NFC IP block, output clocks, system PLL status query, different CPMF
+ * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
+ * those differences can get folded into this clock provider support
+ * code and don't warrant a separate highly redundant implementation
+ */
+
+static enum soc_type {
+        MPC512x_SOC_MPC5121,
+        MPC512x_SOC_MPC5123,
+        MPC512x_SOC_MPC5125,
+} soc;
+
+static void mpc512x_clk_determine_soc(void)
+{
+        if (of_machine_is_compatible("fsl,mpc5121")) {
+                soc = MPC512x_SOC_MPC5121;
+                return;
+        }
+        if (of_machine_is_compatible("fsl,mpc5123")) {
+                soc = MPC512x_SOC_MPC5123;
+                return;
+        }
+        if (of_machine_is_compatible("fsl,mpc5125")) {
+                soc = MPC512x_SOC_MPC5125;
+                return;
+        }
+}
+
+static bool soc_has_mbx(void)
+{
+        if (soc == MPC512x_SOC_MPC5121)
+                return true;
+        return false;
+}
+
+static bool soc_has_axe(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_viu(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_spdif(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_pata(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_sata(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_pci(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return false;
+        return true;
+}
+
+static bool soc_has_fec2(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+static int soc_max_pscnum(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return 10;
+        return 12;
+}
+
+static bool soc_has_sdhc2(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+static bool soc_has_nfc_5125(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+static bool soc_has_outclk(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+static bool soc_has_cpmf_0_bypass(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+static bool soc_has_mclk_mux0_canin(void)
+{
+        if (soc == MPC512x_SOC_MPC5125)
+                return true;
+        return false;
+}
+
+/* }}} SoC variants */
+/* common clk API wrappers {{{ */
+
+/* convenience wrappers around the common clk API */
+static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
+{
+        return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mpc512x_clk_factor(
+        const char *name, const char *parent_name,
+        int mul, int div)
+{
+        int clkflags;
+
+        clkflags = CLK_SET_RATE_PARENT;
+        return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
+                                         mul, div);
+}
+
+static inline struct clk *mpc512x_clk_divider(
+        const char *name, const char *parent_name, u8 clkflags,
+        u32 __iomem *reg, u8 pos, u8 len, int divflags)
+{
+        return clk_register_divider(NULL, name, parent_name, clkflags,
+                                    reg, pos, len, divflags, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_divtable(
+        const char *name, const char *parent_name,
+        u32 __iomem *reg, u8 pos, u8 len,
+        const struct clk_div_table *divtab)
+{
+        u8 divflags;
+
+        divflags = 0;
+        return clk_register_divider_table(NULL, name, parent_name, 0,
+                                          reg, pos, len, divflags,
+                                          divtab, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_gated(
+        const char *name, const char *parent_name,
+        u32 __iomem *reg, u8 pos)
+{
+        int clkflags;
+
+        clkflags = CLK_SET_RATE_PARENT;
+        return clk_register_gate(NULL, name, parent_name, clkflags,
+                                 reg, pos, 0, &clklock);
+}
+
+static inline struct clk *mpc512x_clk_muxed(const char *name,
+        const char **parent_names, int parent_count,
+        u32 __iomem *reg, u8 pos, u8 len)
+{
+        int clkflags;
+        u8 muxflags;
+
+        clkflags = CLK_SET_RATE_PARENT;
+        muxflags = 0;
+        return clk_register_mux(NULL, name,
+                                parent_names, parent_count, clkflags,
+                                reg, pos, len, muxflags, &clklock);
+}
+
+/* }}} common clk API wrappers */
+
+/* helper to isolate a bit field from a register */
+static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
+{
+        uint32_t val;
+
+        val = in_be32(reg);
+        val >>= pos;
+        val &= (1 << len) - 1;
+        return val;
+}
+
+/* get the SPMF and translate it into the "sys pll" multiplier */
+static int get_spmf_mult(void)
+{
+        static int spmf_to_mult[] = {
+                68, 1, 12, 16, 20, 24, 28, 32,
+                36, 40, 44, 48, 52, 56, 60, 64,
+        };
+        int spmf;
+
+        spmf = get_bit_field(&clkregs->spmr, 24, 4);
+        return spmf_to_mult[spmf];
+}
+
+/*
+ * get the SYS_DIV value and translate it into a divide factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * divide ratio is fractional
+ */
+static int get_sys_div_x2(void)
+{
+        static int sysdiv_code_to_x2[] = {
+                4, 5, 6, 7, 8, 9, 10, 14,
+                12, 16, 18, 22, 20, 24, 26, 30,
+                28, 32, 34, 38, 36, 40, 42, 46,
+                44, 48, 50, 54, 52, 56, 58, 62,
+                60, 64, 66,
+        };
+        int divcode;
+
+        divcode = get_bit_field(&clkregs->scfr2, 26, 6);
+        return sysdiv_code_to_x2[divcode];
+}
+
+/*
+ * get the CPMF value and translate it into a multiplier factor
+ *
+ * values returned from here are a multiple of the real factor since the
+ * multiplier ratio is fractional
+ */
+static int get_cpmf_mult_x2(void)
+{
+        static int cpmf_to_mult_x36[] = {
+                /* 0b000 is "times 36" */
+                72, 2, 2, 3, 4, 5, 6, 7,
+        };
+        static int cpmf_to_mult_0by[] = {
+                /* 0b000 is "bypass" */
+                2, 2, 2, 3, 4, 5, 6, 7,
+        };
+
+        int *cpmf_to_mult;
+        int cpmf;
+
+        cpmf = get_bit_field(&clkregs->spmr, 16, 4);
+        if (soc_has_cpmf_0_bypass())
+                cpmf_to_mult = cpmf_to_mult_0by;
+        else
+                cpmf_to_mult = cpmf_to_mult_x36;
+        return cpmf_to_mult[cpmf];
+}
+
+/*
+ * some of the clock dividers do scale in a linear way, yet not all of
+ * their bit combinations are legal; use a divider table to get a
+ * resulting set of applicable divider values
+ */
+
+/* applies to the IPS_DIV, and PCI_DIV values */
+static struct clk_div_table divtab_2346[] = {
+        { .val = 2, .div = 2, },
+        { .val = 3, .div = 3, },
+        { .val = 4, .div = 4, },
+        { .val = 6, .div = 6, },
+        { .div = 0, },
+};
+
+/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
+static struct clk_div_table divtab_1234[] = {
+        { .val = 1, .div = 1, },
+        { .val = 2, .div = 2, },
+        { .val = 3, .div = 3, },
+        { .val = 4, .div = 4, },
+        { .div = 0, },
+};
+
+static int get_freq_from_dt(char *propname)
+{
+        struct device_node *np;
+        const unsigned int *prop;
+        int val;
+
+        val = 0;
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+        if (np) {
+                prop = of_get_property(np, propname, NULL);
+                if (prop)
+                        val = *prop;
+            of_node_put(np);
+        }
+        return val;
+}
+
+static void mpc512x_clk_preset_data(void)
+{
+        size_t i;
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                clks[i] = ERR_PTR(-ENODEV);
+}
+
+/*
+ * - receives the "bus frequency" from the caller (that's the IPS clock
+ *   rate, the historical source of clock information)
+ * - fetches the system PLL multiplier and divider values as well as the
+ *   IPS divider value from hardware
+ * - determines the REF clock rate either from the XTAL/OSC spec (if
+ *   there is a device tree node describing the oscillator) or from the
+ *   IPS bus clock (supported for backwards compatibility, such that
+ *   setups without XTAL/OSC specs keep working)
+ * - creates the "ref" clock item in the clock tree, such that
+ *   subsequent code can create the remainder of the hierarchy (REF ->
+ *   SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
+ *   values
+ */
+static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq,
+                                        int *sys_mul, int *sys_div,
+                                        int *ips_div)
+{
+        struct clk *osc_clk;
+        int calc_freq;
+
+        /* fetch mul/div factors from the hardware */
+        *sys_mul = get_spmf_mult();
+        *sys_mul *= 2;          /* compensate for the fractional divider */
+        *sys_div = get_sys_div_x2();
+        *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
+
+        /* lookup the oscillator clock for its rate */
+        osc_clk = of_clk_get_by_name(np, "osc");
+
+        /*
+         * either descend from OSC to REF (and in bypassing verify the
+         * IPS rate), or backtrack from IPS and multiplier values that
+         * were fetched from hardware to REF and thus to the OSC value
+         *
+         * in either case the REF clock gets created here and the
+         * remainder of the clock tree can get spanned from there
+         */
+        if (!IS_ERR(osc_clk)) {
+                clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
+                calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
+                calc_freq *= *sys_mul;
+                calc_freq /= *sys_div;
+                calc_freq /= 2;
+                calc_freq /= *ips_div;
+                if (bus_freq && calc_freq != bus_freq)
+                        pr_warn("calc rate %d != OF spec %d\n",
+                                calc_freq, bus_freq);
+        } else {
+                calc_freq = bus_freq;   /* start with IPS */
+                calc_freq *= *ips_div;  /* IPS -> CSB */
+                calc_freq *= 2;         /* CSB -> SYS */
+                calc_freq *= *sys_div;  /* SYS -> PLL out */
+                calc_freq /= *sys_mul;  /* PLL out -> REF == OSC */
+                clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
+        }
+}
+
+/* MCLK helpers {{{ */
+
+/*
+ * helper code for the MCLK subtree setup
+ *
+ * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
+ * suggests that all instances of the "PSC clock generation" are equal,
+ * and that one might re-use the PSC setup for MSCAN clock generation
+ * (section 5.2.5) as well, at least the logic if not the data for
+ * description
+ *
+ * the details (starting at page 5-20) show differences in the specific
+ * inputs of the first mux stage ("can clk in", "spdif tx"), and the
+ * factual non-availability of the second mux stage (it's present yet
+ * only one input is valid)
+ *
+ * the MSCAN clock related registers (starting at page 5-35) all
+ * reference "spdif clk" at the first mux stage and don't mention any
+ * "can clk" at all, which somehow is unexpected
+ *
+ * TODO re-check the document, and clarify whether the RM is correct in
+ * the overview or in the details, and whether the difference is a
+ * clipboard induced error or results from chip revisions
+ *
+ * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
+ * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
+ * first a doc update is required which better reflects reality in the
+ * SoC before the implementation should follow while no questions remain
+ */
+
+/*
+ * note that this declaration raises a checkpatch warning, but
+ * it's the very data type dictated by <linux/clk-provider.h>,
+ * "fixing" this warning will break compilation
+ */
+static const char *parent_names_mux0_spdif[] = {
+        "sys", "ref", "psc-mclk-in", "spdif-tx",
+};
+
+static const char *parent_names_mux0_canin[] = {
+        "sys", "ref", "psc-mclk-in", "can-clk-in",
+};
+
+enum mclk_type {
+        MCLK_TYPE_PSC,
+        MCLK_TYPE_MSCAN,
+        MCLK_TYPE_SPDIF,
+        MCLK_TYPE_OUTCLK,
+};
+
+struct mclk_setup_data {
+        enum mclk_type type;
+        bool has_mclk1;
+        const char *name_mux0;
+        const char *name_en0;
+        const char *name_div0;
+        const char *parent_names_mux1[2];
+        const char *name_mclk;
+};
+
+#define MCLK_SETUP_DATA_PSC(id) { \
+        MCLK_TYPE_PSC, 0, \
+        "psc" #id "-mux0", \
+        "psc" #id "-en0", \
+        "psc" #id "_mclk_div", \
+        { "psc" #id "_mclk_div", "dummy", }, \
+        "psc" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_MSCAN(id) { \
+        MCLK_TYPE_MSCAN, 0, \
+        "mscan" #id "-mux0", \
+        "mscan" #id "-en0", \
+        "mscan" #id "_mclk_div", \
+        { "mscan" #id "_mclk_div", "dummy", }, \
+        "mscan" #id "_mclk", \
+}
+
+#define MCLK_SETUP_DATA_SPDIF { \
+        MCLK_TYPE_SPDIF, 1, \
+        "spdif-mux0", \
+        "spdif-en0", \
+        "spdif_mclk_div", \
+        { "spdif_mclk_div", "spdif-rx", }, \
+        "spdif_mclk", \
+}
+
+#define MCLK_SETUP_DATA_OUTCLK(id) { \
+        MCLK_TYPE_OUTCLK, 0, \
+        "out" #id "-mux0", \
+        "out" #id "-en0", \
+        "out" #id "_mclk_div", \
+        { "out" #id "_mclk_div", "dummy", }, \
+        "out" #id "_clk", \
+}
+
+static struct mclk_setup_data mclk_psc_data[] = {
+        MCLK_SETUP_DATA_PSC(0),
+        MCLK_SETUP_DATA_PSC(1),
+        MCLK_SETUP_DATA_PSC(2),
+        MCLK_SETUP_DATA_PSC(3),
+        MCLK_SETUP_DATA_PSC(4),
+        MCLK_SETUP_DATA_PSC(5),
+        MCLK_SETUP_DATA_PSC(6),
+        MCLK_SETUP_DATA_PSC(7),
+        MCLK_SETUP_DATA_PSC(8),
+        MCLK_SETUP_DATA_PSC(9),
+        MCLK_SETUP_DATA_PSC(10),
+        MCLK_SETUP_DATA_PSC(11),
+};
+
+static struct mclk_setup_data mclk_mscan_data[] = {
+        MCLK_SETUP_DATA_MSCAN(0),
+        MCLK_SETUP_DATA_MSCAN(1),
+        MCLK_SETUP_DATA_MSCAN(2),
+        MCLK_SETUP_DATA_MSCAN(3),
+};
+
+static struct mclk_setup_data mclk_spdif_data[] = {
+        MCLK_SETUP_DATA_SPDIF,
+};
+
+static struct mclk_setup_data mclk_outclk_data[] = {
+        MCLK_SETUP_DATA_OUTCLK(0),
+        MCLK_SETUP_DATA_OUTCLK(1),
+        MCLK_SETUP_DATA_OUTCLK(2),
+        MCLK_SETUP_DATA_OUTCLK(3),
+};
+
+/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
+static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx)
+{
+        size_t clks_idx_pub, clks_idx_int;
+        u32 __iomem *mccr_reg;  /* MCLK control register (mux, en, div) */
+        int div;
+
+        /* derive a few parameters from the component type and index */
+        switch (entry->type) {
+        case MCLK_TYPE_PSC:
+                clks_idx_pub = MPC512x_CLK_PSC0_MCLK + idx;
+                clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+                             + (idx) * MCLK_MAX_IDX;
+                mccr_reg = &clkregs->psc_ccr[idx];
+                break;
+        case MCLK_TYPE_MSCAN:
+                clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + idx;
+                clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+                             + (NR_PSCS + idx) * MCLK_MAX_IDX;
+                mccr_reg = &clkregs->mscan_ccr[idx];
+                break;
+        case MCLK_TYPE_SPDIF:
+                clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
+                clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+                             + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
+                mccr_reg = &clkregs->spccr;
+                break;
+        case MCLK_TYPE_OUTCLK:
+                clks_idx_pub = MPC512x_CLK_OUT0_CLK + idx;
+                clks_idx_int = MPC512x_CLK_MCLKS_FIRST
+                             + (NR_PSCS + NR_MSCANS + NR_SPDIFS + idx)
+                             * MCLK_MAX_IDX;
+                mccr_reg = &clkregs->out_ccr[idx];
+                break;
+        default:
+                return;
+        }
+
+        /*
+         * this was grabbed from the PPC_CLOCK implementation, which
+         * enforced a specific MCLK divider while the clock was gated
+         * during setup (that's a documented hardware requirement)
+         *
+         * the PPC_CLOCK implementation might even have violated the
+         * "MCLK <= IPS" constraint, the fixed divider value of 1
+         * results in a divider of 2 and thus MCLK = SYS/2 which equals
+         * CSB which is greater than IPS; the serial port setup may have
+         * adjusted the divider which the clock setup might have left in
+         * an undesirable state
+         *
+         * initial setup is:
+         * - MCLK 0 from SYS
+         * - MCLK DIV such to not exceed the IPS clock
+         * - MCLK 0 enabled
+         * - MCLK 1 from MCLK DIV
+         */
+        div = clk_get_rate(clks[MPC512x_CLK_SYS]);
+        div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
+        out_be32(mccr_reg, (0 << 16));
+        out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
+        out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
+
+        /*
+         * create the 'struct clk' items of the MCLK's clock subtree
+         *
+         * note that by design we always create all nodes and won't take
+         * shortcuts here, because
+         * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
+         *   selectable inputs to the CFM while those who "actually use"
+         *   the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
+         *   for their bitrate
+         * - in the absence of "aliases" for clocks we need to create
+         *   individial 'struct clk' items for whatever might get
+         *   referenced or looked up, even if several of those items are
+         *   identical from the logical POV (their rate value)
+         * - for easier future maintenance and for better reflection of
+         *   the SoC's documentation, it appears appropriate to generate
+         *   clock items even for those muxers which actually are NOPs
+         *   (those with two inputs of which one is reserved)
+         */
+        clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
+                        entry->name_mux0,
+                        soc_has_mclk_mux0_canin()
+                                ? &parent_names_mux0_canin[0]
+                                : &parent_names_mux0_spdif[0],
+                        ARRAY_SIZE(parent_names_mux0_spdif),
+                        mccr_reg, 14, 2);
+        clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
+                        entry->name_en0, entry->name_mux0,
+                        mccr_reg, 16);
+        clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
+                        entry->name_div0,
+                        entry->name_en0, CLK_SET_RATE_GATE,
+                        mccr_reg, 17, 15, 0);
+        if (entry->has_mclk1) {
+                clks[clks_idx_pub] = mpc512x_clk_muxed(
+                                entry->name_mclk,
+                                &entry->parent_names_mux1[0],
+                                ARRAY_SIZE(entry->parent_names_mux1),
+                                mccr_reg, 7, 1);
+        } else {
+                clks[clks_idx_pub] = mpc512x_clk_factor(
+                                entry->name_mclk,
+                                entry->parent_names_mux1[0],
+                                1, 1);
+        }
+}
+
+/* }}} MCLK helpers */
+
+static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq)
+{
+        int sys_mul, sys_div, ips_div;
+        int mul, div;
+        size_t mclk_idx;
+        int freq;
+
+        /*
+         * developer's notes:
+         * - consider whether to handle clocks which have both gates and
+         *   dividers via intermediates or by means of composites
+         * - fractional dividers appear to not map well to composites
+         *   since they can be seen as a fixed multiplier and an
+         *   adjustable divider, while composites can only combine at
+         *   most one of a mux, div, and gate each into one 'struct clk'
+         *   item
+         * - PSC/MSCAN/SPDIF clock generation OTOH already is very
+         *   specific and cannot get mapped to componsites (at least not
+         *   a single one, maybe two of them, but then some of these
+         *   intermediate clock signals get referenced elsewhere (e.g.
+         *   in the clock frequency measurement, CFM) and thus need
+         *   publicly available names
+         * - the current source layout appropriately reflects the
+         *   hardware setup, and it works, so it's questionable whether
+         *   further changes will result in big enough a benefit
+         */
+
+        /* regardless of whether XTAL/OSC exists, have REF created */
+        mpc512x_clk_setup_ref_clock(np, busfreq, &sys_mul, &sys_div, &ips_div);
+
+        /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
+        clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
+                                                   sys_mul, sys_div);
+        clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
+        clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
+                                                     &clkregs->scfr1, 23, 3,
+                                                     divtab_2346);
+        /* now setup anything below SYS and CSB and IPS */
+
+        clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
+
+        /*
+         * the Reference Manual discusses that for SDHC only even divide
+         * ratios are supported because clock domain synchronization
+         * between 'per' and 'ipg' is broken;
+         * keep the divider's bit 0 cleared (per reset value), and only
+         * allow to setup the divider's bits 7:1, which results in that
+         * only even divide ratios can get configured upon rate changes;
+         * keep the "x4" name because this bit shift hack is an internal
+         * implementation detail, the "fractional divider with quarters"
+         * semantics remains
+         */
+        clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1);
+        clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
+                                                        &clkregs->scfr2, 1, 7,
+                                                        CLK_DIVIDER_ONE_BASED);
+        if (soc_has_sdhc2()) {
+                clks[MPC512x_CLK_SDHC2_UG] = mpc512x_clk_divider(
+                                "sdhc2-ug", "sdhc-x4", 0, &clkregs->scfr2,
+                                9, 7, CLK_DIVIDER_ONE_BASED);
+        }
+
+        clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
+        clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
+                                                       &clkregs->scfr1, 0, 8,
+                                                       CLK_DIVIDER_ONE_BASED);
+
+        /*
+         * the "power architecture PLL" was setup from data which was
+         * sampled from the reset config word, at this point in time the
+         * configuration can be considered fixed and read only (i.e. no
+         * longer adjustable, or no longer in need of adjustment), which
+         * is why we don't register a PLL here but assume fixed factors
+         */
+        mul = get_cpmf_mult_x2();
+        div = 2;        /* compensate for the fractional factor */
+        clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
+
+        if (soc_has_mbx()) {
+                clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor(
+                                "mbx-bus-ug", "csb", 1, 2);
+                clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable(
+                                "mbx-ug", "mbx-bus-ug", &clkregs->scfr1,
+                                14, 3, divtab_1234);
+                clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor(
+                                "mbx-3d-ug", "mbx-ug", 1, 1);
+        }
+        if (soc_has_pci()) {
+                clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable(
+                                "pci-ug", "csb", &clkregs->scfr1,
+                                20, 3, divtab_2346);
+        }
+        if (soc_has_nfc_5125()) {
+                /*
+                 * XXX TODO implement 5125 NFC clock setup logic,
+                 * with high/low period counters in clkregs->scfr3,
+                 * currently there are no users so it's ENOIMPL
+                 */
+                clks[MPC512x_CLK_NFC_UG] = ERR_PTR(-ENOTSUPP);
+        } else {
+                clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable(
+                                "nfc-ug", "ips", &clkregs->scfr1,
+                                8, 3, divtab_1234);
+        }
+        clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
+                                                        &clkregs->scfr1, 11, 3,
+                                                        divtab_1234);
+
+        clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
+                                                  &clkregs->sccr1, 30);
+        clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
+                                                  &clkregs->sccr1, 29);
+        if (soc_has_pata()) {
+                clks[MPC512x_CLK_PATA] = mpc512x_clk_gated(
+                                "pata", "ips", &clkregs->sccr1, 28);
+        }
+        /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */
+        for (mclk_idx = 0; mclk_idx < soc_max_pscnum(); mclk_idx++) {
+                char name[12];
+                snprintf(name, sizeof(name), "psc%d", mclk_idx);
+                clks[MPC512x_CLK_PSC0 + mclk_idx] = mpc512x_clk_gated(
+                                name, "ips", &clkregs->sccr1, 27 - mclk_idx);
+                mpc512x_clk_setup_mclk(&mclk_psc_data[mclk_idx], mclk_idx);
+        }
+        clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
+                                                       &clkregs->sccr1, 15);
+        if (soc_has_sata()) {
+                clks[MPC512x_CLK_SATA] = mpc512x_clk_gated(
+                                "sata", "ips", &clkregs->sccr1, 14);
+        }
+        clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
+                                                  &clkregs->sccr1, 13);
+        if (soc_has_pci()) {
+                clks[MPC512x_CLK_PCI] = mpc512x_clk_gated(
+                                "pci", "pci-ug", &clkregs->sccr1, 11);
+        }
+        clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
+                                                  &clkregs->sccr1, 10);
+        if (soc_has_fec2()) {
+                clks[MPC512x_CLK_FEC2] = mpc512x_clk_gated(
+                                "fec2", "ips", &clkregs->sccr1, 9);
+        }
+
+        clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
+                                                  &clkregs->sccr2, 31);
+        if (soc_has_axe()) {
+                clks[MPC512x_CLK_AXE] = mpc512x_clk_gated(
+                                "axe", "csb", &clkregs->sccr2, 30);
+        }
+        clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
+                                                  &clkregs->sccr2, 29);
+        clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
+                                                   &clkregs->sccr2, 28);
+        clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
+                                                   &clkregs->sccr2, 27);
+        clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
+                                                  &clkregs->sccr2, 26);
+        /* MSCAN differs from PSC with just one gate for multiple components */
+        clks[MPC512x_CLK_BDLC] = mpc512x_clk_gated("bdlc", "ips",
+                                                   &clkregs->sccr2, 25);
+        for (mclk_idx = 0; mclk_idx < ARRAY_SIZE(mclk_mscan_data); mclk_idx++)
+                mpc512x_clk_setup_mclk(&mclk_mscan_data[mclk_idx], mclk_idx);
+        clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
+                                                   &clkregs->sccr2, 24);
+        /* there is only one SPDIF component, which shares MCLK support code */
+        if (soc_has_spdif()) {
+                clks[MPC512x_CLK_SPDIF] = mpc512x_clk_gated(
+                                "spdif", "ips", &clkregs->sccr2, 23);
+                mpc512x_clk_setup_mclk(&mclk_spdif_data[0], 0);
+        }
+        if (soc_has_mbx()) {
+                clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated(
+                                "mbx-bus", "mbx-bus-ug", &clkregs->sccr2, 22);
+                clks[MPC512x_CLK_MBX] = mpc512x_clk_gated(
+                                "mbx", "mbx-ug", &clkregs->sccr2, 21);
+                clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated(
+                                "mbx-3d", "mbx-3d-ug", &clkregs->sccr2, 20);
+        }
+        clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
+                                                  &clkregs->sccr2, 19);
+        if (soc_has_viu()) {
+                clks[MPC512x_CLK_VIU] = mpc512x_clk_gated(
+                                "viu", "csb", &clkregs->sccr2, 18);
+        }
+        if (soc_has_sdhc2()) {
+                clks[MPC512x_CLK_SDHC2] = mpc512x_clk_gated(
+                                "sdhc-2", "sdhc2-ug", &clkregs->sccr2, 17);
+        }
+
+        if (soc_has_outclk()) {
+                size_t idx;     /* used as mclk_idx, just to trim line length */
+                for (idx = 0; idx < ARRAY_SIZE(mclk_outclk_data); idx++)
+                        mpc512x_clk_setup_mclk(&mclk_outclk_data[idx], idx);
+        }
+
+        /*
+         * externally provided clocks (when implemented in hardware,
+         * device tree may specify values which otherwise were unknown)
+         */
+        freq = get_freq_from_dt("psc_mclk_in");
+        if (!freq)
+                freq = 25000000;
+        clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
+        if (soc_has_mclk_mux0_canin()) {
+                freq = get_freq_from_dt("can_clk_in");
+                clks[MPC512x_CLK_CAN_CLK_IN] = mpc512x_clk_fixed(
+                                "can_clk_in", freq);
+        } else {
+                freq = get_freq_from_dt("spdif_tx_in");
+                clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
+                                "spdif_tx_in", freq);
+                freq = get_freq_from_dt("spdif_rx_in");
+                clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
+                                "spdif_rx_in", freq);
+        }
+
+        /* fixed frequency for AC97, always 24.567MHz */
+        clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
+
+        /*
+         * pre-enable those "internal" clock items which never get
+         * claimed by any peripheral driver, to not have the clock
+         * subsystem disable them late at startup
+         */
+        clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
+        clk_prepare_enable(clks[MPC512x_CLK_E300]);     /* PowerPC CPU */
+        clk_prepare_enable(clks[MPC512x_CLK_DDR]);      /* DRAM */
+        clk_prepare_enable(clks[MPC512x_CLK_MEM]);      /* SRAM */
+        clk_prepare_enable(clks[MPC512x_CLK_IPS]);      /* SoC periph */
+        clk_prepare_enable(clks[MPC512x_CLK_LPC]);      /* boot media */
+}
+
+/*
+ * registers the set of public clocks (those listed in the dt-bindings/
+ * header file) for OF lookups, keeps the intermediates private to us
+ */
+static void mpc5121_clk_register_of_provider(struct device_node *np)
+{
+        clk_data.clks = clks;
+        clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * temporary support for the period of time between introduction of CCF
+ * support and the adjustment of peripheral drivers to OF based lookups
+ */
+static void mpc5121_clk_provide_migration_support(void)
+{
+
+        /*
+         * pre-enable those clock items which are not yet appropriately
+         * acquired by their peripheral driver
+         *
+         * the PCI clock cannot get acquired by its peripheral driver,
+         * because for this platform the driver won't probe(), instead
+         * initialization is done from within the .setup_arch() routine
+         * at a point in time where the clock provider has not been
+         * setup yet and thus isn't available yet
+         *
+         * so we "pre-enable" the clock here, to not have the clock
+         * subsystem automatically disable this item in a late init call
+         *
+         * this PCI clock pre-enable workaround only applies when there
+         * are device tree nodes for PCI and thus the peripheral driver
+         * has attached to bridges, otherwise the PCI clock remains
+         * unused and so it gets disabled
+         */
+        clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
+        if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci"))
+                clk_prepare_enable(clks[MPC512x_CLK_PCI]);
+}
+
+/*
+ * those macros are not exactly pretty, but they encapsulate a lot
+ * of copy'n'paste heavy code which is even more ugly, and reduce
+ * the potential for inconsistencies in those many code copies
+ */
+#define FOR_NODES(compatname) \
+        for_each_compatible_node(np, NULL, compatname)
+
+#define NODE_PREP do { \
+        of_address_to_resource(np, 0, &res); \
+        snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \
+} while (0)
+
+#define NODE_CHK(clkname, clkitem, regnode, regflag) do { \
+        struct clk *clk; \
+        clk = of_clk_get_by_name(np, clkname); \
+        if (IS_ERR(clk)) { \
+                clk = clkitem; \
+                clk_register_clkdev(clk, clkname, devname); \
+                if (regnode) \
+                        clk_register_clkdev(clk, clkname, np->name); \
+                did_register |= DID_REG_ ## regflag; \
+                pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \
+                         clkname, devname, clk); \
+        } else { \
+                clk_put(clk); \
+        } \
+} while (0)
+
+/*
+ * register source code provided fallback results for clock lookups,
+ * these get consulted when OF based clock lookup fails (that is in the
+ * case of not yet adjusted device tree data, where clock related specs
+ * are missing)
+ */
+static void mpc5121_clk_provide_backwards_compat(void)
+{
+        enum did_reg_flags {
+                DID_REG_PSC     = BIT(0),
+                DID_REG_PSCFIFO = BIT(1),
+                DID_REG_NFC     = BIT(2),
+                DID_REG_CAN     = BIT(3),
+                DID_REG_I2C     = BIT(4),
+                DID_REG_DIU     = BIT(5),
+                DID_REG_VIU     = BIT(6),
+                DID_REG_FEC     = BIT(7),
+                DID_REG_USB     = BIT(8),
+                DID_REG_PATA    = BIT(9),
+        };
+
+        int did_register;
+        struct device_node *np;
+        struct resource res;
+        int idx;
+        char devname[32];
+
+        did_register = 0;
+
+        FOR_NODES(mpc512x_select_psc_compat()) {
+                NODE_PREP;
+                idx = (res.start >> 8) & 0xf;
+                NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC);
+                NODE_CHK("mclk", clks[MPC512x_CLK_PSC0_MCLK + idx], 0, PSC);
+        }
+
+        FOR_NODES("fsl,mpc5121-psc-fifo") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_PSC_FIFO], 1, PSCFIFO);
+        }
+
+        FOR_NODES("fsl,mpc5121-nfc") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_NFC], 0, NFC);
+        }
+
+        FOR_NODES("fsl,mpc5121-mscan") {
+                NODE_PREP;
+                idx = 0;
+                idx += (res.start & 0x2000) ? 2 : 0;
+                idx += (res.start & 0x0080) ? 1 : 0;
+                NODE_CHK("ipg", clks[MPC512x_CLK_BDLC], 0, CAN);
+                NODE_CHK("mclk", clks[MPC512x_CLK_MSCAN0_MCLK + idx], 0, CAN);
+        }
+
+        /*
+         * do register the 'ips', 'sys', and 'ref' names globally
+         * instead of inside each individual CAN node, as there is no
+         * potential for a name conflict (in contrast to 'ipg' and 'mclk')
+         */
+        if (did_register & DID_REG_CAN) {
+                clk_register_clkdev(clks[MPC512x_CLK_IPS], "ips", NULL);
+                clk_register_clkdev(clks[MPC512x_CLK_SYS], "sys", NULL);
+                clk_register_clkdev(clks[MPC512x_CLK_REF], "ref", NULL);
+        }
+
+        FOR_NODES("fsl,mpc5121-i2c") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_I2C], 0, I2C);
+        }
+
+        /*
+         * workaround for the fact that the I2C driver does an "anonymous"
+         * lookup (NULL name spec, which yields the first clock spec) for
+         * which we cannot register an alias -- a _global_ 'ipg' alias that
+         * is not bound to any device name and returns the I2C clock item
+         * is not a good idea
+         *
+         * so we have the lookup in the peripheral driver fail, which is
+         * silent and non-fatal, and pre-enable the clock item here such
+         * that register access is possible
+         *
+         * see commit b3bfce2b "i2c: mpc: cleanup clock API use" for
+         * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this
+         * workaround obsolete
+         */
+        if (did_register & DID_REG_I2C)
+                clk_prepare_enable(clks[MPC512x_CLK_I2C]);
+
+        FOR_NODES("fsl,mpc5121-diu") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_DIU], 1, DIU);
+        }
+
+        FOR_NODES("fsl,mpc5121-viu") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU);
+        }
+
+        /*
+         * note that 2771399a "fs_enet: cleanup clock API use" did use the
+         * "per" string for the clock lookup in contrast to the "ipg" name
+         * which most other nodes are using -- this is not a fatal thing
+         * but just something to keep in mind when doing compatibility
+         * registration, it's a non-issue with up-to-date device tree data
+         */
+        FOR_NODES("fsl,mpc5121-fec") {
+                NODE_PREP;
+                NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
+        }
+        FOR_NODES("fsl,mpc5121-fec-mdio") {
+                NODE_PREP;
+                NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
+        }
+        /*
+         * MPC5125 has two FECs: FEC1 at 0x2800, FEC2 at 0x4800;
+         * the clock items don't "form an array" since FEC2 was
+         * added only later and was not allowed to shift all other
+         * clock item indices, so the numbers aren't adjacent
+         */
+        FOR_NODES("fsl,mpc5125-fec") {
+                NODE_PREP;
+                if (res.start & 0x4000)
+                        idx = MPC512x_CLK_FEC2;
+                else
+                        idx = MPC512x_CLK_FEC;
+                NODE_CHK("per", clks[idx], 0, FEC);
+        }
+
+        FOR_NODES("fsl,mpc5121-usb2-dr") {
+                NODE_PREP;
+                idx = (res.start & 0x4000) ? 1 : 0;
+                NODE_CHK("ipg", clks[MPC512x_CLK_USB1 + idx], 0, USB);
+        }
+
+        FOR_NODES("fsl,mpc5121-pata") {
+                NODE_PREP;
+                NODE_CHK("ipg", clks[MPC512x_CLK_PATA], 0, PATA);
+        }
+
+        /*
+         * try to collapse diagnostics into a single line of output yet
+         * provide a full list of what is missing, to avoid noise in the
+         * absence of up-to-date device tree data -- backwards
+         * compatibility to old DTBs is a requirement, updates may be
+         * desirable or preferrable but are not at all mandatory
+         */
+        if (did_register) {
+                pr_notice("device tree lacks clock specs, adding fallbacks (0x%x,%s%s%s%s%s%s%s%s%s%s)\n",
+                          did_register,
+                          (did_register & DID_REG_PSC) ? " PSC" : "",
+                          (did_register & DID_REG_PSCFIFO) ? " PSCFIFO" : "",
+                          (did_register & DID_REG_NFC) ? " NFC" : "",
+                          (did_register & DID_REG_CAN) ? " CAN" : "",
+                          (did_register & DID_REG_I2C) ? " I2C" : "",
+                          (did_register & DID_REG_DIU) ? " DIU" : "",
+                          (did_register & DID_REG_VIU) ? " VIU" : "",
+                          (did_register & DID_REG_FEC) ? " FEC" : "",
+                          (did_register & DID_REG_USB) ? " USB" : "",
+                          (did_register & DID_REG_PATA) ? " PATA" : "");
+        } else {
+                pr_debug("device tree has clock specs, no fallbacks added\n");
+        }
+}
+
+int __init mpc5121_clk_init(void)
+{
+        struct device_node *clk_np;
+        int busfreq;
+
+        /* map the clock control registers */
+        clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+        if (!clk_np)
+                return -ENODEV;
+        clkregs = of_iomap(clk_np, 0);
+        WARN_ON(!clkregs);
+
+        /* determine the SoC variant we run on */
+        mpc512x_clk_determine_soc();
+
+        /* invalidate all not yet registered clock slots */
+        mpc512x_clk_preset_data();
+
+        /*
+         * have the device tree scanned for "fixed-clock" nodes (which
+         * includes the oscillator node if the board's DT provides one)
+         */
+        of_clk_init(NULL);
+
+        /*
+         * add a dummy clock for those situations where a clock spec is
+         * required yet no real clock is involved
+         */
+        clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
+
+        /*
+         * have all the real nodes in the clock tree populated from REF
+         * down to all leaves, either starting from the OSC node or from
+         * a REF root that was created from the IPS bus clock input
+         */
+        busfreq = get_freq_from_dt("bus-frequency");
+        mpc512x_clk_setup_clock_tree(clk_np, busfreq);
+
+        /* register as an OF clock provider */
+        mpc5121_clk_register_of_provider(clk_np);
+
+        /*
+         * unbreak not yet adjusted peripheral drivers during migration
+         * towards fully operational common clock support, and allow
+         * operation in the absence of clock related device tree specs
+         */
+        mpc5121_clk_provide_migration_support();
+        mpc5121_clk_provide_backwards_compat();
+
+        return 0;
+}
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index fd8a37653417..000000000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/*
- * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby <jrigby@freescale.com>
- *
- * Implements the clk api defined in include/linux/clk.h
- *
- *    Original based on linux/arch/arm/mach-integrator/clock.c
- *
- *    Copyright (C) 2004 ARM Limited.
- *    Written by Deep Blue Solutions Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <asm/mpc5xxx.h>
-#include <asm/mpc5121.h>
-#include <asm/clk_interface.h>
-
-#include "mpc512x.h"
-
-#undef CLK_DEBUG
-
-static int clocks_initialized;
-
-#define CLK_HAS_RATE    0x1     /* has rate in MHz */
-#define CLK_HAS_CTRL    0x2     /* has control reg and bit */
-
-struct clk {
-        struct list_head node;
-        char name[32];
-        int flags;
-        struct device *dev;
-        unsigned long rate;
-        struct module *owner;
-        void (*calc) (struct clk *);
-        struct clk *parent;
-        int reg, bit;           /* CLK_HAS_CTRL */
-        int div_shift;          /* only used by generic_div_clk_calc */
-};
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int dev_match;
-        int id_match;
-
-        if (dev == NULL || id == NULL)
-                return clk;
-
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(p, &clocks, node) {
-                dev_match = id_match = 0;
-
-                if (dev == p->dev)
-                        dev_match++;
-                if (strcmp(id, p->name) == 0)
-                        id_match++;
-                if ((dev_match || id_match) && try_module_get(p->owner)) {
-                        clk = p;
-                        break;
-                }
-        }
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
-}
-
-#ifdef CLK_DEBUG
-static void dump_clocks(void)
-{
-        struct clk *p;
-
-        mutex_lock(&clocks_mutex);
-        printk(KERN_INFO "CLOCKS:\n");
-        list_for_each_entry(p, &clocks, node) {
-                pr_info("  %s=%ld", p->name, p->rate);
-                if (p->parent)
-                        pr_cont(" %s=%ld", p->parent->name,
-                               p->parent->rate);
-                if (p->flags & CLK_HAS_CTRL)
-                        pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
-                pr_cont("\n");
-        }
-        mutex_unlock(&clocks_mutex);
-}
-#define DEBUG_CLK_DUMP() dump_clocks()
-#else
-#define DEBUG_CLK_DUMP()
-#endif
-
-
-static void mpc5121_clk_put(struct clk *clk)
-{
-        module_put(clk->owner);
-}
-
-#define NRPSC 12
-
-struct mpc512x_clockctl {
-        u32 spmr;               /* System PLL Mode Reg */
-        u32 sccr[2];            /* System Clk Ctrl Reg 1 & 2 */
-        u32 scfr1;              /* System Clk Freq Reg 1 */
-        u32 scfr2;              /* System Clk Freq Reg 2 */
-        u32 reserved;
-        u32 bcr;                /* Bread Crumb Reg */
-        u32 pccr[NRPSC];        /* PSC Clk Ctrl Reg 0-11 */
-        u32 spccr;              /* SPDIF Clk Ctrl Reg */
-        u32 cccr;               /* CFM Clk Ctrl Reg */
-        u32 dccr;               /* DIU Clk Cnfg Reg */
-};
-
-static struct mpc512x_clockctl __iomem *clockctl;
-
-static int mpc5121_clk_enable(struct clk *clk)
-{
-        unsigned int mask;
-
-        if (clk->flags & CLK_HAS_CTRL) {
-                mask = in_be32(&clockctl->sccr[clk->reg]);
-                mask |= 1 << clk->bit;
-                out_be32(&clockctl->sccr[clk->reg], mask);
-        }
-        return 0;
-}
-
-static void mpc5121_clk_disable(struct clk *clk)
-{
-        unsigned int mask;
-
-        if (clk->flags & CLK_HAS_CTRL) {
-                mask = in_be32(&clockctl->sccr[clk->reg]);
-                mask &= ~(1 << clk->bit);
-                out_be32(&clockctl->sccr[clk->reg], mask);
-        }
-}
-
-static unsigned long mpc5121_clk_get_rate(struct clk *clk)
-{
-        if (clk->flags & CLK_HAS_RATE)
-                return clk->rate;
-        else
-                return 0;
-}
-
-static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        return rate;
-}
-
-static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        return 0;
-}
-
-static int clk_register(struct clk *clk)
-{
-        mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-        return 0;
-}
-
-static unsigned long spmf_mult(void)
-{
-        /*
-         * Convert spmf to multiplier
-         */
-        static int spmf_to_mult[] = {
-                68, 1, 12, 16,
-                20, 24, 28, 32,
-                36, 40, 44, 48,
-                52, 56, 60, 64
-        };
-        int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
-        return spmf_to_mult[spmf];
-}
-
-static unsigned long sysdiv_div_x_2(void)
-{
-        /*
-         * Convert sysdiv to divisor x 2
-         * Some divisors have fractional parts so
-         * multiply by 2 then divide by this value
-         */
-        static int sysdiv_to_div_x_2[] = {
-                4, 5, 6, 7,
-                8, 9, 10, 14,
-                12, 16, 18, 22,
-                20, 24, 26, 30,
-                28, 32, 34, 38,
-                36, 40, 42, 46,
-                44, 48, 50, 54,
-                52, 56, 58, 62,
-                60, 64, 66,
-        };
-        int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
-        return sysdiv_to_div_x_2[sysdiv];
-}
-
-static unsigned long ref_to_sys(unsigned long rate)
-{
-        rate *= spmf_mult();
-        rate *= 2;
-        rate /= sysdiv_div_x_2();
-
-        return rate;
-}
-
-static unsigned long sys_to_ref(unsigned long rate)
-{
-        rate *= sysdiv_div_x_2();
-        rate /= 2;
-        rate /= spmf_mult();
-
-        return rate;
-}
-
-static long ips_to_ref(unsigned long rate)
-{
-        int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
-
-        rate *= ips_div;        /* csb_clk = ips_clk * ips_div */
-        rate *= 2;              /* sys_clk = csb_clk * 2 */
-        return sys_to_ref(rate);
-}
-
-static unsigned long devtree_getfreq(char *clockname)
-{
-        struct device_node *np;
-        const unsigned int *prop;
-        unsigned int val = 0;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
-        if (np) {
-                prop = of_get_property(np, clockname, NULL);
-                if (prop)
-                        val = *prop;
-            of_node_put(np);
-        }
-        return val;
-}
-
-static void ref_clk_calc(struct clk *clk)
-{
-        unsigned long rate;
-
-        rate = devtree_getfreq("bus-frequency");
-        if (rate == 0) {
-                printk(KERN_ERR "No bus-frequency in dev tree\n");
-                clk->rate = 0;
-                return;
-        }
-        clk->rate = ips_to_ref(rate);
-}
-
-static struct clk ref_clk = {
-        .name = "ref_clk",
-        .calc = ref_clk_calc,
-};
-
-
-static void sys_clk_calc(struct clk *clk)
-{
-        clk->rate = ref_to_sys(ref_clk.rate);
-}
-
-static struct clk sys_clk = {
-        .name = "sys_clk",
-        .calc = sys_clk_calc,
-};
-
-static void diu_clk_calc(struct clk *clk)
-{
-        int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
-        unsigned long rate;
-
-        rate = sys_clk.rate;
-
-        rate *= 2;
-        rate /= diudiv_x_2;
-
-        clk->rate = rate;
-}
-
-static void viu_clk_calc(struct clk *clk)
-{
-        unsigned long rate;
-
-        rate = sys_clk.rate;
-        rate /= 2;
-        clk->rate = rate;
-}
-
-static void half_clk_calc(struct clk *clk)
-{
-        clk->rate = clk->parent->rate / 2;
-}
-
-static void generic_div_clk_calc(struct clk *clk)
-{
-        int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
-
-        clk->rate = clk->parent->rate / div;
-}
-
-static void unity_clk_calc(struct clk *clk)
-{
-        clk->rate = clk->parent->rate;
-}
-
-static struct clk csb_clk = {
-        .name = "csb_clk",
-        .calc = half_clk_calc,
-        .parent = &sys_clk,
-};
-
-static void e300_clk_calc(struct clk *clk)
-{
-        int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
-        int ratex2 = clk->parent->rate * spmf;
-
-        clk->rate = ratex2 / 2;
-}
-
-static struct clk e300_clk = {
-        .name = "e300_clk",
-        .calc = e300_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk ips_clk = {
-        .name = "ips_clk",
-        .calc = generic_div_clk_calc,
-        .parent = &csb_clk,
-        .div_shift = 23,
-};
-
-/*
- * Clocks controlled by SCCR1 (.reg = 0)
- */
-static struct clk lpc_clk = {
-        .name = "lpc_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 30,
-        .calc = generic_div_clk_calc,
-        .parent = &ips_clk,
-        .div_shift = 11,
-};
-
-static struct clk nfc_clk = {
-        .name = "nfc_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 29,
-        .calc = generic_div_clk_calc,
-        .parent = &ips_clk,
-        .div_shift = 8,
-};
-
-static struct clk pata_clk = {
-        .name = "pata_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 28,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-/*
- * PSC clocks (bits 27 - 16)
- * are setup elsewhere
- */
-
-static struct clk sata_clk = {
-        .name = "sata_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 14,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-static struct clk fec_clk = {
-        .name = "fec_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 13,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-static struct clk pci_clk = {
-        .name = "pci_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 0,
-        .bit = 11,
-        .calc = generic_div_clk_calc,
-        .parent = &csb_clk,
-        .div_shift = 20,
-};
-
-/*
- * Clocks controlled by SCCR2 (.reg = 1)
- */
-static struct clk diu_clk = {
-        .name = "diu_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 31,
-        .calc = diu_clk_calc,
-};
-
-static struct clk viu_clk = {
-        .name = "viu_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 18,
-        .calc = viu_clk_calc,
-};
-
-static struct clk axe_clk = {
-        .name = "axe_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 30,
-        .calc = unity_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk usb1_clk = {
-        .name = "usb1_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 28,
-        .calc = unity_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk usb2_clk = {
-        .name = "usb2_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 27,
-        .calc = unity_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk i2c_clk = {
-        .name = "i2c_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 26,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-static struct clk mscan_clk = {
-        .name = "mscan_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 25,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-static struct clk sdhc_clk = {
-        .name = "sdhc_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 24,
-        .calc = unity_clk_calc,
-        .parent = &ips_clk,
-};
-
-static struct clk mbx_bus_clk = {
-        .name = "mbx_bus_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 22,
-        .calc = half_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk mbx_clk = {
-        .name = "mbx_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 21,
-        .calc = unity_clk_calc,
-        .parent = &csb_clk,
-};
-
-static struct clk mbx_3d_clk = {
-        .name = "mbx_3d_clk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 20,
-        .calc = generic_div_clk_calc,
-        .parent = &mbx_bus_clk,
-        .div_shift = 14,
-};
-
-static void psc_mclk_in_calc(struct clk *clk)
-{
-        clk->rate = devtree_getfreq("psc_mclk_in");
-        if (!clk->rate)
-                clk->rate = 25000000;
-}
-
-static struct clk psc_mclk_in = {
-        .name = "psc_mclk_in",
-        .calc = psc_mclk_in_calc,
-};
-
-static struct clk spdif_txclk = {
-        .name = "spdif_txclk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 23,
-};
-
-static struct clk spdif_rxclk = {
-        .name = "spdif_rxclk",
-        .flags = CLK_HAS_CTRL,
-        .reg = 1,
-        .bit = 23,
-};
-
-static void ac97_clk_calc(struct clk *clk)
-{
-        /* ac97 bit clock is always 24.567 MHz */
-        clk->rate = 24567000;
-}
-
-static struct clk ac97_clk = {
-        .name = "ac97_clk_in",
-        .calc = ac97_clk_calc,
-};
-
-static struct clk *rate_clks[] = {
-        &ref_clk,
-        &sys_clk,
-        &diu_clk,
-        &viu_clk,
-        &csb_clk,
-        &e300_clk,
-        &ips_clk,
-        &fec_clk,
-        &sata_clk,
-        &pata_clk,
-        &nfc_clk,
-        &lpc_clk,
-        &mbx_bus_clk,
-        &mbx_clk,
-        &mbx_3d_clk,
-        &axe_clk,
-        &usb1_clk,
-        &usb2_clk,
-        &i2c_clk,
-        &mscan_clk,
-        &sdhc_clk,
-        &pci_clk,
-        &psc_mclk_in,
-        &spdif_txclk,
-        &spdif_rxclk,
-        &ac97_clk,
-        NULL
-};
-
-static void rate_clk_init(struct clk *clk)
-{
-        if (clk->calc) {
-                clk->calc(clk);
-                clk->flags |= CLK_HAS_RATE;
-                clk_register(clk);
-        } else {
-                printk(KERN_WARNING
-                       "Could not initialize clk %s without a calc routine\n",
-                       clk->name);
-        }
-}
-
-static void rate_clks_init(void)
-{
-        struct clk **cpp, *clk;
-
-        cpp = rate_clks;
-        while ((clk = *cpp++))
-                rate_clk_init(clk);
-}
-
-/*
- * There are two clk enable registers with 32 enable bits each
- * psc clocks and device clocks are all stored in dev_clks
- */
-static struct clk dev_clks[2][32];
-
-/*
- * Given a psc number return the dev_clk
- * associated with it
- */
-static struct clk *psc_dev_clk(int pscnum)
-{
-        int reg, bit;
-        struct clk *clk;
-
-        reg = 0;
-        bit = 27 - pscnum;
-
-        clk = &dev_clks[reg][bit];
-        clk->reg = 0;
-        clk->bit = bit;
-        return clk;
-}
-
-/*
- * PSC clock rate calculation
- */
-static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
-{
-        unsigned long mclk_src = sys_clk.rate;
-        unsigned long mclk_div;
-
-        /*
-         * Can only change value of mclk divider
-         * when the divider is disabled.
-         *
-         * Zero is not a valid divider so minimum
-         * divider is 1
-         *
-         * disable/set divider/enable
-         */
-        out_be32(&clockctl->pccr[pscnum], 0);
-        out_be32(&clockctl->pccr[pscnum], 0x00020000);
-        out_be32(&clockctl->pccr[pscnum], 0x00030000);
-
-        if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
-                clk->rate = spdif_rxclk.rate;
-                return;
-        }
-
-        switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
-        case 0:
-                mclk_src = sys_clk.rate;
-                break;
-        case 1:
-                mclk_src = ref_clk.rate;
-                break;
-        case 2:
-                mclk_src = psc_mclk_in.rate;
-                break;
-        case 3:
-                mclk_src = spdif_txclk.rate;
-                break;
-        }
-
-        mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
-        clk->rate = mclk_src / mclk_div;
-}
-
-/*
- * Find all psc nodes in device tree and assign a clock
- * with name "psc%d_mclk" and dev pointing at the device
- * returned from of_find_device_by_node
- */
-static void psc_clks_init(void)
-{
-        struct device_node *np;
-        struct platform_device *ofdev;
-        u32 reg;
-        const char *psc_compat;
-
-        psc_compat = mpc512x_select_psc_compat();
-        if (!psc_compat)
-                return;
-
-        for_each_compatible_node(np, NULL, psc_compat) {
-                if (!of_property_read_u32(np, "reg", &reg)) {
-                        int pscnum = (reg & 0xf00) >> 8;
-                        struct clk *clk = psc_dev_clk(pscnum);
-
-                        clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
-                        ofdev = of_find_device_by_node(np);
-                        clk->dev = &ofdev->dev;
-                        /*
-                         * AC97 is special rate clock does
-                         * not go through normal path
-                         */
-                        if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
-                                clk->rate = ac97_clk.rate;
-                        else
-                                psc_calc_rate(clk, pscnum, np);
-                        sprintf(clk->name, "psc%d_mclk", pscnum);
-                        clk_register(clk);
-                        clk_enable(clk);
-                }
-        }
-}
-
-static struct clk_interface mpc5121_clk_functions = {
-        .clk_get                = mpc5121_clk_get,
-        .clk_enable             = mpc5121_clk_enable,
-        .clk_disable            = mpc5121_clk_disable,
-        .clk_get_rate           = mpc5121_clk_get_rate,
-        .clk_put                = mpc5121_clk_put,
-        .clk_round_rate         = mpc5121_clk_round_rate,
-        .clk_set_rate           = mpc5121_clk_set_rate,
-        .clk_set_parent         = NULL,
-        .clk_get_parent         = NULL,
-};
-
-int __init mpc5121_clk_init(void)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
-        if (np) {
-                clockctl = of_iomap(np, 0);
-                of_node_put(np);
-        }
-
-        if (!clockctl) {
-                printk(KERN_ERR "Could not map clock control registers\n");
-                return 0;
-        }
-
-        rate_clks_init();
-        psc_clks_init();
-
-        /* leave clockctl mapped forever */
-        /*iounmap(clockctl); */
-        DEBUG_CLK_DUMP();
-        clocks_initialized++;
-        clk_functions = mpc5121_clk_functions;
-        return 0;
-}
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 36b5652aada2..adb95f03d4d4 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -12,6 +12,7 @@
  * (at your option) any later version.
  */
 
+#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -68,98 +69,112 @@ struct fsl_diu_shared_fb {
         bool            in_use;
 };
 
-#define DIU_DIV_MASK    0x000000ff
+/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
 static void mpc512x_set_pixel_clock(unsigned int pixclock)
 {
-        unsigned long bestval, bestfreq, speed, busfreq;
-        unsigned long minpixclock, maxpixclock, pixval;
-        struct mpc512x_ccm __iomem *ccm;
         struct device_node *np;
-        u32 temp;
-        long err;
-        int i;
+        struct clk *clk_diu;
+        unsigned long epsilon, minpixclock, maxpixclock;
+        unsigned long offset, want, got, delta;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+        /* lookup and enable the DIU clock */
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
         if (!np) {
-                pr_err("Can't find clock control module.\n");
+                pr_err("Could not find DIU device tree node.\n");
                 return;
         }
-
-        ccm = of_iomap(np, 0);
+        clk_diu = of_clk_get(np, 0);
+        if (IS_ERR(clk_diu)) {
+                /* backwards compat with device trees that lack clock specs */
+                clk_diu = clk_get_sys(np->name, "ipg");
+        }
         of_node_put(np);
-        if (!ccm) {
-                pr_err("Can't map clock control module reg.\n");
+        if (IS_ERR(clk_diu)) {
+                pr_err("Could not lookup DIU clock.\n");
                 return;
         }
-
-        np = of_find_node_by_type(NULL, "cpu");
-        if (np) {
-                const unsigned int *prop =
-                        of_get_property(np, "bus-frequency", NULL);
-
-                of_node_put(np);
-                if (prop) {
-                        busfreq = *prop;
-                } else {
-                        pr_err("Can't get bus-frequency property\n");
-                        return;
-                }
-        } else {
-                pr_err("Can't find 'cpu' node.\n");
+        if (clk_prepare_enable(clk_diu)) {
+                pr_err("Could not enable DIU clock.\n");
                 return;
         }
 
-        /* Pixel Clock configuration */
-        pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
-        speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
-
-        /* Calculate the pixel clock with the smallest error */
-        /* calculate the following in steps to avoid overflow */
-        pr_debug("DIU pixclock in ps - %d\n", pixclock);
-        temp = (1000000000 / pixclock) * 1000;
-        pixclock = temp;
-        pr_debug("DIU pixclock freq - %u\n", pixclock);
-
-        temp = temp / 20; /* pixclock * 0.05 */
-        pr_debug("deviation = %d\n", temp);
-        minpixclock = pixclock - temp;
-        maxpixclock = pixclock + temp;
-        pr_debug("DIU minpixclock - %lu\n", minpixclock);
-        pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
-        pixval = speed/pixclock;
-        pr_debug("DIU pixval = %lu\n", pixval);
-
-        err = LONG_MAX;
-        bestval = pixval;
-        pr_debug("DIU bestval = %lu\n", bestval);
-
-        bestfreq = 0;
-        for (i = -1; i <= 1; i++) {
-                temp = speed / (pixval+i);
-                pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
-                        i, pixval, temp);
-                if ((temp < minpixclock) || (temp > maxpixclock))
-                        pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
-                                minpixclock, maxpixclock);
-                else if (abs(temp - pixclock) < err) {
-                        pr_debug("Entered the else if block %d\n", i);
-                        err = abs(temp - pixclock);
-                        bestval = pixval + i;
-                        bestfreq = temp;
-                }
+        /*
+         * convert the picoseconds spec into the desired clock rate,
+         * determine the acceptable clock range for the monitor (+/- 5%),
+         * do the calculation in steps to avoid integer overflow
+         */
+        pr_debug("DIU pixclock in ps - %u\n", pixclock);
+        pixclock = (1000000000 / pixclock) * 1000;
+        pr_debug("DIU pixclock freq  - %u\n", pixclock);
+        epsilon = pixclock / 20; /* pixclock * 0.05 */
+        pr_debug("DIU deviation      - %lu\n", epsilon);
+        minpixclock = pixclock - epsilon;
+        maxpixclock = pixclock + epsilon;
+        pr_debug("DIU minpixclock    - %lu\n", minpixclock);
+        pr_debug("DIU maxpixclock    - %lu\n", maxpixclock);
+
+        /*
+         * check whether the DIU supports the desired pixel clock
+         *
+         * - simply request the desired clock and see what the
+         *   platform's clock driver will make of it, assuming that it
+         *   will setup the best approximation of the requested value
+         * - try other candidate frequencies in the order of decreasing
+         *   preference (i.e. with increasing distance from the desired
+         *   pixel clock, and checking the lower frequency before the
+         *   higher frequency to not overload the hardware) until the
+         *   first match is found -- any potential subsequent match
+         *   would only be as good as the former match or typically
+         *   would be less preferrable
+         *
+         * the offset increment of pixelclock divided by 64 is an
+         * arbitrary choice -- it's simple to calculate, in the typical
+         * case we expect the first check to succeed already, in the
+         * worst case seven frequencies get tested (the exact center and
+         * three more values each to the left and to the right) before
+         * the 5% tolerance window is exceeded, resulting in fast enough
+         * execution yet high enough probability of finding a suitable
+         * value, while the error rate will be in the order of single
+         * percents
+         */
+        for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
+                want = pixclock - offset;
+                pr_debug("DIU checking clock - %lu\n", want);
+                clk_set_rate(clk_diu, want);
+                got = clk_get_rate(clk_diu);
+                delta = abs(pixclock - got);
+                if (delta < epsilon)
+                        break;
+                if (!offset)
+                        continue;
+                want = pixclock + offset;
+                pr_debug("DIU checking clock - %lu\n", want);
+                clk_set_rate(clk_diu, want);
+                got = clk_get_rate(clk_diu);
+                delta = abs(pixclock - got);
+                if (delta < epsilon)
+                        break;
         }
+        if (offset <= epsilon) {
+                pr_debug("DIU clock accepted - %lu\n", want);
+                pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+                         pixclock, got, delta, epsilon);
+                return;
+        }
+        pr_warn("DIU pixclock auto search unsuccessful\n");
 
-        pr_debug("DIU chose = %lx\n", bestval);
-        pr_debug("DIU error = %ld\n NomPixClk ", err);
-        pr_debug("DIU: Best Freq = %lx\n", bestfreq);
-        /* Modify DIU_DIV in CCM SCFR1 */
-        temp = in_be32(&ccm->scfr1);
-        pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
-        temp &= ~DIU_DIV_MASK;
-        temp |= (bestval & DIU_DIV_MASK);
-        out_be32(&ccm->scfr1, temp);
-        pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
-        iounmap(ccm);
+        /*
+         * what is the most appropriate action to take when the search
+         * for an available pixel clock which is acceptable to the
+         * monitor has failed?  disable the DIU (clock) or just provide
+         * a "best effort"?  we go with the latter
+         */
+        pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
+        clk_set_rate(clk_diu, pixclock);
+        got = clk_get_rate(clk_diu);
+        delta = abs(pixclock - got);
+        pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
+                 pixclock, got, delta, epsilon);
 }
 
 static enum fsl_diu_monitor_port
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index af54174801f7..b625a2c6f4f2 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -1,7 +1,7 @@
 config PPC_MPC52xx
         bool "52xx-based boards"
         depends on 6xx
-        select PPC_CLOCK
+        select COMMON_CLK
         select PPC_PCI_CHOICE
 
 config PPC_MPC5200_SIMPLE
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
index be7b1aa4d54c..37f7a89c10f2 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -245,7 +245,7 @@ static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id)
 
         if (dma && !write) {
                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
-                pr_err("bogus LPBFIFO IRQ (dma and not writting)\n");
+                pr_err("bogus LPBFIFO IRQ (dma and not writing)\n");
                 return IRQ_HANDLED;
         }
 
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 670a033264c0..2bdc8c862c46 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -99,7 +99,6 @@ config SBC834x
 config ASP834x
         bool "Analogue & Micro ASP 834x"
         select PPC_MPC834x
-        select REDBOOT
         help
           This enables support for the Analogue & Micro ASP 83xx
           board.
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index fd71cfdf2380..e238b6a55b15 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -11,7 +11,6 @@
  * (at your option) any later version.
  */
 
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/device.h>
diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c
index 3d9716ccd327..4b4c081df94d 100644
--- a/arch/powerpc/platforms/83xx/suspend.c
+++ b/arch/powerpc/platforms/83xx/suspend.c
@@ -10,7 +10,6 @@
  * by the Free Software Foundation.
  */
 
-#include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/types.h>
 #include <linux/ioport.h>
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 4d4634958cfb..c17aae80e7ff 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -123,6 +123,12 @@ config P1023_RDS
         help
           This option enables support for the P1023 RDS and RDB boards
 
+config TWR_P102x
+        bool "Freescale TWR-P102x"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the TWR-P1025 board.
+
 config SOCRATES
         bool "Socrates"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index dd4c0b59577b..25cebe74ac46 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
 obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
+obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
 obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index eba78c85303f..3b085c7ee539 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -9,6 +9,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
+#include <asm/qe.h>
 #include <sysdev/cpm2_pic.h>
 
 #include "mpc85xx.h"
@@ -82,3 +83,40 @@ void __init mpc85xx_cpm2_pic_init(void)
         irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!np) {
+                np = of_find_node_by_name(NULL, "qe");
+                if (!np) {
+                        pr_err("%s: Could not find Quicc Engine node\n",
+                                        __func__);
+                        return;
+                }
+        }
+
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        qe_reset();
+        of_node_put(np);
+
+        np = of_find_node_by_name(NULL, "par_io");
+        if (np) {
+                struct device_node *ucc;
+
+                par_io_init(np);
+                of_node_put(np);
+
+                for_each_node_by_name(ucc, "ucc")
+                        par_io_of_config(ucc);
+
+        }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5dc2c7f..fc51dd4092e5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,10 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621a8df5..34f3c5eb3bee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
  * All rights reserved.
  *
  * Author: Andy Fleming <afleming@freescale.com>
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
 {
         struct device_node *np;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
-        if (!np) {
-                np = of_find_node_by_name(NULL, "qe");
-                if (!np)
-                        return;
-        }
-
-        if (!of_device_is_available(np)) {
-                of_node_put(np);
-                return;
-        }
-
-        qe_reset();
-        of_node_put(np);
-
-        np = of_find_node_by_name(NULL, "par_io");
-        if (np) {
-                struct device_node *ucc;
-
-                par_io_init(np);
-                of_node_put(np);
-
-                for_each_node_by_name(ucc, "ucc")
-                        par_io_of_config(ucc);
-        }
-
+        mpc85xx_qe_init();
         mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0a3d56..e15bdd18fdb2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
 /*
  * MPC85xx RDB Board Setup
  *
- * Copyright 2009,2012 Freescale Semiconductor Inc.
+ * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -98,26 +98,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
         fsl_pci_assign_primary();
 
 #ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
-        if (!np) {
-                pr_err("%s: Could not find Quicc Engine node\n", __func__);
-                goto qe_fail;
-        }
-
-        qe_reset();
-        of_node_put(np);
-
-        np = of_find_node_by_name(NULL, "par_io");
-        if (np) {
-                struct device_node *ucc;
-
-                par_io_init(np);
-                of_node_put(np);
-
-                for_each_node_by_name(ucc, "ucc")
-                        par_io_of_config(ucc);
-
-        }
+        mpc85xx_qe_init();
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
         if (machine_is(p1025_rdb)) {
 
@@ -148,8 +129,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
 
         }
 #endif
-
-qe_fail:
 #endif  /* CONFIG_QUICC_ENGINE */
 
         printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
diff --git a/arch/powerpc/platforms/85xx/sgy_cts1000.c b/arch/powerpc/platforms/85xx/sgy_cts1000.c
index b9197cea1854..bb75add67084 100644
--- a/arch/powerpc/platforms/85xx/sgy_cts1000.c
+++ b/arch/powerpc/platforms/85xx/sgy_cts1000.c
@@ -14,7 +14,6 @@
 #include <linux/platform_device.h>
 #include <linux/device.h>
 #include <linux/module.h>
-#include <linux/init.h>
 #include <linux/of_gpio.h>
 #include <linux/of_irq.h>
 #include <linux/workqueue.h>
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 393f975ab397..6382098d6f8d 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -389,15 +389,18 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
 }
 #endif /* CONFIG_KEXEC */
 
-static void smp_85xx_setup_cpu(int cpu_nr)
+static void smp_85xx_basic_setup(int cpu_nr)
 {
-        if (smp_85xx_ops.probe == smp_mpic_probe)
-                mpic_setup_this_cpu();
-
         if (cpu_has_feature(CPU_FTR_DBELL))
                 doorbell_setup_this_cpu();
 }
 
+static void smp_85xx_setup_cpu(int cpu_nr)
+{
+        mpic_setup_this_cpu();
+        smp_85xx_basic_setup(cpu_nr);
+}
+
 static const struct of_device_id mpc85xx_smp_guts_ids[] = {
         { .compatible = "fsl,mpc8572-guts", },
         { .compatible = "fsl,p1020-guts", },
@@ -412,13 +415,14 @@ void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
 
-        smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
 
         np = of_find_node_by_type(NULL, "open-pic");
         if (np) {
                 smp_85xx_ops.probe = smp_mpic_probe;
+                smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
                 smp_85xx_ops.message_pass = smp_mpic_message_pass;
-        }
+        } else
+                smp_85xx_ops.setup_cpu = smp_85xx_basic_setup;
 
         if (cpu_has_feature(CPU_FTR_DBELL)) {
                 /*
@@ -427,6 +431,7 @@ void __init mpc85xx_smp_init(void)
                  */
                 smp_85xx_ops.message_pass = NULL;
                 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
+                smp_85xx_ops.probe = NULL;
         }
 
         np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
new file mode 100644
index 000000000000..c25ff10f05ee
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Michael Johnston <michael.johnston@freescale.com>
+ *
+ * Description:
+ * TWR-P102x Board Setup
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+
+#include <asm/pci-bridge.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/fsl_guts.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+static void __init twr_p1025_pic_init(void)
+{
+        struct mpic *mpic;
+
+#ifdef CONFIG_QUICC_ENGINE
+        struct device_node *np;
+#endif
+
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (np) {
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+                of_node_put(np);
+        } else
+                pr_err("Could not find qe-ic node\n");
+#endif
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init twr_p1025_setup_arch(void)
+{
+#ifdef CONFIG_QUICC_ENGINE
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("twr_p1025_setup_arch()", 0);
+
+        mpc85xx_smp_init();
+
+        fsl_pci_assign_primary();
+
+#ifdef CONFIG_QUICC_ENGINE
+        mpc85xx_qe_init();
+
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+        if (machine_is(twr_p1025)) {
+                struct ccsr_guts __iomem *guts;
+
+                np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
+                if (np) {
+                        guts = of_iomap(np, 0);
+                        if (!guts)
+                                pr_err("twr_p1025: could not map global utilities register\n");
+                        else {
+                        /* P1025 has pins muxed for QE and other functions. To
+                         * enable QE UEC mode, we need to set bit QE0 for UCC1
+                         * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+                         * and QE12 for QE MII management signals in PMUXCR
+                         * register.
+                         * Set QE mux bits in PMUXCR */
+                        setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                        MPC85xx_PMUXCR_QE(3) |
+                                        MPC85xx_PMUXCR_QE(9) |
+                                        MPC85xx_PMUXCR_QE(12));
+                        iounmap(guts);
+
+#if defined(CONFIG_SERIAL_QE)
+                        /* On P1025TWR board, the UCC7 acted as UART port.
+                         * However, The UCC7's CTS pin is low level in default,
+                         * it will impact the transmission in full duplex
+                         * communication. So disable the Flow control pin PA18.
+                         * The UCC7 UART just can use RXD and TXD pins.
+                         */
+                        par_io_config_pin(0, 18, 0, 0, 0, 0);
+#endif
+                        /* Drive PB29 to CPLD low - CPLD will then change
+                         * muxing from LBC to QE */
+                        par_io_config_pin(1, 29, 1, 0, 0, 0);
+                        par_io_data_set(1, 29, 0);
+                        }
+                        of_node_put(np);
+                }
+        }
+#endif
+#endif  /* CONFIG_QUICC_ENGINE */
+
+        pr_info("TWR-P1025 board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
+
+static int __init twr_p1025_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,TWR-P1025");
+}
+
+define_machine(twr_p1025) {
+        .name                   = "TWR-P1025",
+        .probe                  = twr_p1025_probe,
+        .setup_arch             = twr_p1025_setup_arch,
+        .init_IRQ               = twr_p1025_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 8dec3c0911ad..bd6f1a1cf922 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -45,7 +45,6 @@ config PPC_EP88XC
 config PPC_ADDER875
         bool "Analogue & Micro Adder 875"
         select CPM1
-        select REDBOOT
         help
           This enables support for the Analogue & Micro Adder 875
           board.
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index bca2465a9c34..434fda39bf8b 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -72,6 +72,7 @@ config PPC_BOOK3S_64
         select PPC_HAVE_PMU_SUPPORT
         select SYS_SUPPORTS_HUGETLBFS
         select HAVE_ARCH_TRANSPARENT_HUGEPAGE if PPC_64K_PAGES
+        select ARCH_SUPPORTS_NUMA_BALANCING
 
 config PPC_BOOK3E_64
         bool "Embedded processors"
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index c34ee4e60873..d4d245c0d787 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -111,7 +111,7 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
                 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
 
         if (rflags & _PAGE_NO_CACHE)
-                hpte_r &= ~_PAGE_COHERENT;
+                hpte_r &= ~HPTE_R_M;
 
         raw_spin_lock(&beat_htab_lock);
         lpar_rc = beat_read_mask(hpte_group);
@@ -337,7 +337,7 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
                 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
 
         if (rflags & _PAGE_NO_CACHE)
-                hpte_r &= ~_PAGE_COHERENT;
+                hpte_r &= ~HPTE_R_M;
 
         /* insert into not-volted entry */
         lpar_rc = beat_insert_htab_entry3(0, hpte_group, hpte_v, hpte_r,
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index b53560660b72..2b90ff8a93be 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -197,7 +197,7 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
 
         io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
 
-        for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
+        for (i = 0; i < npages; i++, uaddr += tbl->it_page_shift)
                 io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
 
         mb();
@@ -430,7 +430,7 @@ static void cell_iommu_setup_hardware(struct cbe_iommu *iommu,
 {
         cell_iommu_setup_stab(iommu, base, size, 0, 0);
         iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
-                                            IOMMU_PAGE_SHIFT);
+                                            IOMMU_PAGE_SHIFT_4K);
         cell_iommu_enable_hardware(iommu);
 }
 
@@ -487,8 +487,10 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
         window->table.it_blocksize = 16;
         window->table.it_base = (unsigned long)iommu->ptab;
         window->table.it_index = iommu->nid;
-        window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset;
-        window->table.it_size = size >> IOMMU_PAGE_SHIFT;
+        window->table.it_page_shift = IOMMU_PAGE_SHIFT_4K;
+        window->table.it_offset =
+                (offset >> window->table.it_page_shift) + pte_offset;
+        window->table.it_size = size >> window->table.it_page_shift;
 
         iommu_init_table(&window->table, iommu->nid);
 
@@ -773,7 +775,7 @@ static void __init cell_iommu_init_one(struct device_node *np,
 
         /* Setup the iommu_table */
         cell_iommu_setup_window(iommu, np, base, size,
-                                offset >> IOMMU_PAGE_SHIFT);
+                                offset >> IOMMU_PAGE_SHIFT_4K);
 }
 
 static void __init cell_disable_iommus(void)
@@ -1122,7 +1124,7 @@ static int __init cell_iommu_fixed_mapping_init(void)
 
                 cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
                 iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
-                                                    IOMMU_PAGE_SHIFT);
+                                                    IOMMU_PAGE_SHIFT_4K);
                 cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
                                              fbase, fsize);
                 cell_iommu_enable_hardware(iommu);
diff --git a/arch/powerpc/platforms/chrp/smp.c b/arch/powerpc/platforms/chrp/smp.c
index dead91b177b9..b6c9a0dcc924 100644
--- a/arch/powerpc/platforms/chrp/smp.c
+++ b/arch/powerpc/platforms/chrp/smp.c
@@ -14,7 +14,6 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/spinlock.h>
 
 #include <asm/ptrace.h>
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 302ba43d73a1..6d3c7a9fd047 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -67,6 +67,18 @@ config PPC_C2K
           This option enables support for the GE Fanuc C2K board (formerly
           an SBS board).
 
+config MVME5100
+        bool "Motorola/Emerson MVME5100"
+        depends on EMBEDDED6xx
+        select MPIC
+        select PCI
+        select PPC_INDIRECT_PCI
+        select PPC_I8259
+        select PPC_NATIVE
+        help
+          This option enables support for the Motorola (now Emerson) MVME5100
+          board.
+
 config TSI108_BRIDGE
         bool
         select PCI
@@ -113,4 +125,3 @@ config WII
         help
           Select WII if configuring for the Nintendo Wii.
           More information at: <http://gc-linux.sourceforge.net/>
-
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 66c23e423f40..cdd48d402b93 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_USBGECKO_UDBG)	+= usbgecko_udbg.o
 obj-$(CONFIG_GAMECUBE_COMMON)   += flipper-pic.o
 obj-$(CONFIG_GAMECUBE)          += gamecube.o
 obj-$(CONFIG_WII)               += wii.o hlwd-pic.o
+obj-$(CONFIG_MVME5100)          += mvme5100.o
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 6c03034dbbd3..c269caee58f9 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -15,7 +15,6 @@
 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
diff --git a/arch/powerpc/platforms/embedded6xx/mvme5100.c b/arch/powerpc/platforms/embedded6xx/mvme5100.c
new file mode 100644
index 000000000000..25e3bfb64efb
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/mvme5100.c
@@ -0,0 +1,221 @@
+/*
+ * Board setup routines for the Motorola/Emerson MVME5100.
+ *
+ * Copyright 2013 CSC Australia Pty. Ltd.
+ *
+ * Based on earlier code by:
+ *
+ *    Matt Porter, MontaVista Software Inc.
+ *    Copyright 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Author: Stephen Chivers <schivers@csc.com>
+ *
+ */
+
+#include <linux/of_platform.h>
+
+#include <asm/i8259.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpic.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+
+#define HAWK_MPIC_SIZE          0x00040000U
+#define MVME5100_PCI_MEM_OFFSET 0x00000000
+
+/* Board register addresses. */
+#define BOARD_STATUS_REG        0xfef88080
+#define BOARD_MODFAIL_REG       0xfef88090
+#define BOARD_MODRST_REG        0xfef880a0
+#define BOARD_TBEN_REG          0xfef880c0
+#define BOARD_SW_READ_REG       0xfef880e0
+#define BOARD_GEO_ADDR_REG      0xfef880e8
+#define BOARD_EXT_FEATURE1_REG  0xfef880f0
+#define BOARD_EXT_FEATURE2_REG  0xfef88100
+
+static phys_addr_t pci_membase;
+static u_char *restart;
+
+static void mvme5100_8259_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        unsigned int cascade_irq = i8259_irq();
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+
+        chip->irq_eoi(&desc->irq_data);
+}
+
+static void __init mvme5100_pic_init(void)
+{
+        struct mpic *mpic;
+        struct device_node *np;
+        struct device_node *cp = NULL;
+        unsigned int cirq;
+        unsigned long intack = 0;
+        const u32 *prop = NULL;
+
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (!np) {
+                pr_err("Could not find open-pic node\n");
+                return;
+        }
+
+        mpic = mpic_alloc(np, pci_membase, 0, 16, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_assign_isu(mpic, 0, pci_membase + 0x10000);
+
+        mpic_init(mpic);
+
+        cp = of_find_compatible_node(NULL, NULL, "chrp,iic");
+        if (cp == NULL) {
+                pr_warn("mvme5100_pic_init: couldn't find i8259\n");
+                return;
+        }
+
+        cirq = irq_of_parse_and_map(cp, 0);
+        if (cirq == NO_IRQ) {
+                pr_warn("mvme5100_pic_init: no cascade interrupt?\n");
+                return;
+        }
+
+        np = of_find_compatible_node(NULL, "pci", "mpc10x-pci");
+        if (np) {
+                prop = of_get_property(np, "8259-interrupt-acknowledge", NULL);
+
+                if (prop)
+                        intack = prop[0];
+
+                of_node_put(np);
+        }
+
+        if (intack)
+                pr_debug("mvme5100_pic_init: PCI 8259 intack at 0x%016lx\n",
+                   intack);
+
+        i8259_init(cp, intack);
+        of_node_put(cp);
+        irq_set_chained_handler(cirq, mvme5100_8259_cascade);
+}
+
+static int __init mvme5100_add_bridge(struct device_node *dev)
+{
+        const int               *bus_range;
+        int                     len;
+        struct pci_controller   *hose;
+        unsigned short          devid;
+
+        pr_info("Adding PCI host bridge %s\n", dev->full_name);
+
+        bus_range = of_get_property(dev, "bus-range", &len);
+
+        hose = pcibios_alloc_controller(dev);
+        if (hose == NULL)
+                return -ENOMEM;
+
+        hose->first_busno = bus_range ? bus_range[0] : 0;
+        hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+        setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0);
+
+        pci_process_bridge_OF_ranges(hose, dev, 1);
+
+        early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid);
+
+        if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) {
+                pr_err("HAWK PHB not present?\n");
+                return 0;
+        }
+
+        early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
+
+        if (pci_membase == 0) {
+                pr_err("HAWK PHB mibar not correctly set?\n");
+                return 0;
+        }
+
+        pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase);
+
+        return 0;
+}
+
+static struct of_device_id mvme5100_of_bus_ids[] __initdata = {
+        { .compatible = "hawk-bridge", },
+        {},
+};
+
+/*
+ * Setup the architecture
+ */
+static void __init mvme5100_setup_arch(void)
+{
+        struct device_node *np;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mvme5100_setup_arch()", 0);
+
+        for_each_compatible_node(np, "pci", "hawk-pci")
+                mvme5100_add_bridge(np);
+
+        restart = ioremap(BOARD_MODRST_REG, 4);
+}
+
+
+static void mvme5100_show_cpuinfo(struct seq_file *m)
+{
+        seq_puts(m, "Vendor\t\t: Motorola/Emerson\n");
+        seq_puts(m, "Machine\t\t: MVME5100\n");
+}
+
+static void mvme5100_restart(char *cmd)
+{
+
+        local_irq_disable();
+        mtmsr(mfmsr() | MSR_IP);
+
+        out_8((u_char *) restart, 0x01);
+
+        while (1)
+                ;
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mvme5100_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "MVME5100");
+}
+
+static int __init probe_of_platform_devices(void)
+{
+
+        of_platform_bus_probe(NULL, mvme5100_of_bus_ids, NULL);
+        return 0;
+}
+
+machine_device_initcall(mvme5100, probe_of_platform_devices);
+
+define_machine(mvme5100) {
+        .name                   = "MVME5100",
+        .probe                  = mvme5100_probe,
+        .setup_arch             = mvme5100_setup_arch,
+        .init_IRQ               = mvme5100_pic_init,
+        .show_cpuinfo           = mvme5100_show_cpuinfo,
+        .get_irq                = mpic_get_irq,
+        .restart                = mvme5100_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/pasemi/dma_lib.c b/arch/powerpc/platforms/pasemi/dma_lib.c
index f3defd8a2806..aafa01ba062f 100644
--- a/arch/powerpc/platforms/pasemi/dma_lib.c
+++ b/arch/powerpc/platforms/pasemi/dma_lib.c
@@ -18,7 +18,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/export.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 7d2d036754b5..2e576f2ae442 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -138,8 +138,11 @@ static void iommu_table_iobmap_setup(void)
         pr_debug(" -> %s\n", __func__);
         iommu_table_iobmap.it_busno = 0;
         iommu_table_iobmap.it_offset = 0;
+        iommu_table_iobmap.it_page_shift = IOBMAP_PAGE_SHIFT;
+
         /* it_size is in number of entries */
-        iommu_table_iobmap.it_size = 0x80000000 >> IOBMAP_PAGE_SHIFT;
+        iommu_table_iobmap.it_size =
+                0x80000000 >> iommu_table_iobmap.it_page_shift;
 
         /* Initialize the common IOMMU code */
         iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
diff --git a/arch/powerpc/platforms/powermac/pfunc_core.c b/arch/powerpc/platforms/powermac/pfunc_core.c
index d588e48dff74..43075081721f 100644
--- a/arch/powerpc/platforms/powermac/pfunc_core.c
+++ b/arch/powerpc/platforms/powermac/pfunc_core.c
@@ -5,7 +5,6 @@
  * FIXME: LOCKING !!!
  */
 
-#include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 9fced3f6d2dc..895e8a20a3fc 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -13,11 +13,6 @@ config PPC_POWERNV
         select ARCH_RANDOM
         default y
 
-config POWERNV_MSI
-        bool "Support PCI MSI on PowerNV platform"
-        depends on PCI_MSI
-        default y
-
 config PPC_POWERNV_RTAS
         depends on PPC_POWERNV
         bool "Support for RTAS based PowerNV platforms such as BML"
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 873fa1370dc4..8d767fde5a6a 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SMP)	+= smp.o
 obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o pci-ioda.o
 obj-$(CONFIG_EEH)       += eeh-ioda.o eeh-powernv.o
 obj-$(CONFIG_PPC_SCOM)  += opal-xscom.o
+obj-$(CONFIG_MEMORY_FAILURE)    += opal-memory-errors.o
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index d7ddcee7feb8..e1e71618b70c 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -14,7 +14,6 @@
 #include <linux/bootmem.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
@@ -578,11 +577,8 @@ static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
                 return -EIO;
         }
 
-        /*
-         * FIXME: We probably need log the error in somewhere.
-         * Lets make it up in future.
-         */
-        /* pr_info("%s", phb->diag.blob); */
+        /* The PHB diag-data is always indicative */
+        pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 
         spin_unlock_irqrestore(&phb->lock, flags);
 
@@ -670,143 +666,9 @@ static void ioda_eeh_hub_diag(struct pci_controller *hose)
         }
 }
 
-static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
-                                    struct OpalIoPhbErrorCommon *common)
-{
-        struct OpalIoP7IOCPhbErrorData *data;
-        int i;
-
-        data = (struct OpalIoP7IOCPhbErrorData *)common;
-
-        pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
-                hose->global_number, common->version);
-
-        pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
-
-        pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
-        pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
-        pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
-
-        pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
-        pr_info("  slotStatus:           %08x\n", data->slotStatus);
-        pr_info("  linkStatus:           %08x\n", data->linkStatus);
-        pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
-        pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
-
-        pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
-        pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
-        pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
-        pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
-        pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
-        pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
-        pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
-        pr_info("  sourceId:             %08x\n", data->sourceId);
-
-        pr_info("  errorClass:           %016llx\n", data->errorClass);
-        pr_info("  correlator:           %016llx\n", data->correlator);
-        pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
-        pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
-        pr_info("  lemFir:               %016llx\n", data->lemFir);
-        pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
-        pr_info("  lemWOF:               %016llx\n", data->lemWOF);
-        pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
-        pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
-        pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
-        pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
-        pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
-        pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
-        pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
-        pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
-        pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
-        pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
-        pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
-        pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
-        pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
-        pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
-        pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
-        pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
-
-        for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
-                if ((data->pestA[i] >> 63) == 0 &&
-                    (data->pestB[i] >> 63) == 0)
-                        continue;
-
-                pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
-                pr_info("          PESTB:        %016llx\n", data->pestB[i]);
-        }
-}
-
-static void ioda_eeh_phb3_phb_diag(struct pci_controller *hose,
-                                    struct OpalIoPhbErrorCommon *common)
-{
-        struct OpalIoPhb3ErrorData *data;
-        int i;
-
-        data = (struct OpalIoPhb3ErrorData*)common;
-        pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n\n",
-                hose->global_number, common->version);
-
-        pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
-
-        pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
-        pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
-        pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
-
-        pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
-        pr_info("  slotStatus:           %08x\n", data->slotStatus);
-        pr_info("  linkStatus:           %08x\n", data->linkStatus);
-        pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
-        pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
-
-        pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
-        pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
-        pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
-        pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
-        pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
-        pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
-        pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
-        pr_info("  sourceId:             %08x\n", data->sourceId);
-        pr_info("  errorClass:           %016llx\n", data->errorClass);
-        pr_info("  correlator:           %016llx\n", data->correlator);
-        pr_info("  nFir:                 %016llx\n", data->nFir);
-        pr_info("  nFirMask:             %016llx\n", data->nFirMask);
-        pr_info("  nFirWOF:              %016llx\n", data->nFirWOF);
-        pr_info("  PhbPlssr:             %016llx\n", data->phbPlssr);
-        pr_info("  PhbCsr:               %016llx\n", data->phbCsr);
-        pr_info("  lemFir:               %016llx\n", data->lemFir);
-        pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
-        pr_info("  lemWOF:               %016llx\n", data->lemWOF);
-        pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
-        pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
-        pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
-        pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
-        pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
-        pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
-        pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
-        pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
-        pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
-        pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
-        pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
-        pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
-        pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
-        pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
-        pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
-        pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
-
-        for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
-                if ((data->pestA[i] >> 63) == 0 &&
-                    (data->pestB[i] >> 63) == 0)
-                        continue;
-
-                pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
-                pr_info("          PESTB:        %016llx\n", data->pestB[i]);
-        }
-}
-
 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 {
         struct pnv_phb *phb = hose->private_data;
-        struct OpalIoPhbErrorCommon *common;
         long rc;
 
         rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
@@ -817,18 +679,7 @@ static void ioda_eeh_phb_diag(struct pci_controller *hose)
                 return;
         }
 
-        common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
-        switch (common->ioType) {
-        case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
-                ioda_eeh_p7ioc_phb_diag(hose, common);
-                break;
-        case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
-                ioda_eeh_phb3_phb_diag(hose, common);
-                break;
-        default:
-                pr_warning("%s: Unrecognized I/O chip %d\n",
-                           __func__, common->ioType);
-        }
+        pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 }
 
 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
@@ -862,11 +713,7 @@ static int ioda_eeh_get_pe(struct pci_controller *hose,
         dev.phb = hose;
         dev.pe_config_addr = pe_no;
         dev_pe = eeh_pe_get(&dev);
-        if (!dev_pe) {
-                pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
-                           __func__, hose->global_number, pe_no);
-                return -EEXIST;
-        }
+        if (!dev_pe) return -EEXIST;
 
         *pe = dev_pe;
         return 0;
@@ -884,12 +731,12 @@ static int ioda_eeh_get_pe(struct pci_controller *hose,
  */
 static int ioda_eeh_next_error(struct eeh_pe **pe)
 {
-        struct pci_controller *hose, *tmp;
+        struct pci_controller *hose;
         struct pnv_phb *phb;
         u64 frozen_pe_no;
         u16 err_type, severity;
         long rc;
-        int ret = 1;
+        int ret = EEH_NEXT_ERR_NONE;
 
         /*
          * While running here, it's safe to purge the event queue.
@@ -899,7 +746,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
         eeh_remove_event(NULL);
         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 
-        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+        list_for_each_entry(hose, &hose_list, list_node) {
                 /*
                  * If the subordinate PCI buses of the PHB has been
                  * removed, we needn't take care of it any more.
@@ -938,19 +785,19 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
                 switch (err_type) {
                 case OPAL_EEH_IOC_ERROR:
                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
-                                list_for_each_entry_safe(hose, tmp,
-                                                &hose_list, list_node) {
+                                list_for_each_entry(hose, &hose_list,
+                                                    list_node) {
                                         phb = hose->private_data;
                                         phb->eeh_state |= PNV_EEH_STATE_REMOVED;
                                 }
 
                                 pr_err("EEH: dead IOC detected\n");
-                                ret = 4;
-                                goto out;
+                                ret = EEH_NEXT_ERR_DEAD_IOC;
                         } else if (severity == OPAL_EEH_SEV_INF) {
                                 pr_info("EEH: IOC informative error "
                                         "detected\n");
                                 ioda_eeh_hub_diag(hose);
+                                ret = EEH_NEXT_ERR_NONE;
                         }
 
                         break;
@@ -962,37 +809,61 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
                                 pr_err("EEH: dead PHB#%x detected\n",
                                         hose->global_number);
                                 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
-                                ret = 3;
-                                goto out;
+                                ret = EEH_NEXT_ERR_DEAD_PHB;
                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
                                 if (ioda_eeh_get_phb_pe(hose, pe))
                                         break;
 
                                 pr_err("EEH: fenced PHB#%x detected\n",
                                         hose->global_number);
-                                ret = 2;
-                                goto out;
+                                ret = EEH_NEXT_ERR_FENCED_PHB;
                         } else if (severity == OPAL_EEH_SEV_INF) {
                                 pr_info("EEH: PHB#%x informative error "
                                         "detected\n",
                                         hose->global_number);
                                 ioda_eeh_phb_diag(hose);
+                                ret = EEH_NEXT_ERR_NONE;
                         }
 
                         break;
                 case OPAL_EEH_PE_ERROR:
-                        if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
-                                break;
+                        /*
+                         * If we can't find the corresponding PE, the
+                         * PEEV / PEST would be messy. So we force an
+                         * fenced PHB so that it can be recovered.
+                         */
+                        if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) {
+                                if (!ioda_eeh_get_phb_pe(hose, pe)) {
+                                        pr_err("EEH: Escalated fenced PHB#%x "
+                                               "detected for PE#%llx\n",
+                                                hose->global_number,
+                                                frozen_pe_no);
+                                        ret = EEH_NEXT_ERR_FENCED_PHB;
+                                } else {
+                                        ret = EEH_NEXT_ERR_NONE;
+                                }
+                        } else {
+                                pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
+                                        (*pe)->addr, (*pe)->phb->global_number);
+                                ret = EEH_NEXT_ERR_FROZEN_PE;
+                        }
 
-                        pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
-                                (*pe)->addr, (*pe)->phb->global_number);
-                        ret = 1;
-                        goto out;
+                        break;
+                default:
+                        pr_warn("%s: Unexpected error type %d\n",
+                                __func__, err_type);
                 }
+
+                /*
+                 * If we have no errors on the specific PHB or only
+                 * informative error there, we continue poking it.
+                 * Otherwise, we need actions to be taken by upper
+                 * layer.
+                 */
+                if (ret > EEH_NEXT_ERR_INF)
+                        break;
         }
 
-        ret = 0;
-out:
         return ret;
 }
 
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 73b981438cc5..a79fddc5e74e 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -344,6 +344,27 @@ static int powernv_eeh_next_error(struct eeh_pe **pe)
         return -EEXIST;
 }
 
+static int powernv_eeh_restore_config(struct device_node *dn)
+{
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
+        struct pnv_phb *phb;
+        s64 ret;
+
+        if (!edev)
+                return -EEXIST;
+
+        phb = edev->phb->private_data;
+        ret = opal_pci_reinit(phb->opal_id,
+                              OPAL_REINIT_PCI_DEV, edev->config_addr);
+        if (ret) {
+                pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
+                        __func__, edev->config_addr, ret);
+                return -EIO;
+        }
+
+        return 0;
+}
+
 static struct eeh_ops powernv_eeh_ops = {
         .name                   = "powernv",
         .init                   = powernv_eeh_init,
@@ -359,7 +380,8 @@ static struct eeh_ops powernv_eeh_ops = {
         .configure_bridge       = powernv_eeh_configure_bridge,
         .read_config            = pnv_pci_cfg_read,
         .write_config           = pnv_pci_cfg_write,
-        .next_error             = powernv_eeh_next_error
+        .next_error             = powernv_eeh_next_error,
+        .restore_config         = powernv_eeh_restore_config
 };
 
 /**
diff --git a/arch/powerpc/platforms/powernv/opal-flash.c b/arch/powerpc/platforms/powernv/opal-flash.c
index 6ffa6b1ec5b7..714ef972406b 100644
--- a/arch/powerpc/platforms/powernv/opal-flash.c
+++ b/arch/powerpc/platforms/powernv/opal-flash.c
@@ -76,8 +76,8 @@
 /* Validate buffer size */
 #define VALIDATE_BUF_SIZE       4096
 
-/* XXX: Assume candidate image size is <= 256MB */
-#define MAX_IMAGE_SIZE  0x10000000
+/* XXX: Assume candidate image size is <= 1GB */
+#define MAX_IMAGE_SIZE  0x40000000
 
 /* Flash sg list version */
 #define SG_LIST_VERSION (1UL)
@@ -103,30 +103,9 @@ struct image_header_t {
         uint32_t        size;
 };
 
-/* Scatter/gather entry */
-struct opal_sg_entry {
-        void    *data;
-        long    length;
-};
-
-/* We calculate number of entries based on PAGE_SIZE */
-#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
-
-/*
- * This struct is very similar but not identical to that
- * needed by the opal flash update. All we need to do for
- * opal is rewrite num_entries into a version/length and
- * translate the pointers to absolute.
- */
-struct opal_sg_list {
-        unsigned long num_entries;
-        struct opal_sg_list *next;
-        struct opal_sg_entry entry[SG_ENTRIES_PER_NODE];
-};
-
 struct validate_flash_t {
         int             status;         /* Return status */
-        void            *buf;           /* Candiate image buffer */
+        void            *buf;           /* Candidate image buffer */
         uint32_t        buf_size;       /* Image size */
         uint32_t        result;         /* Update results token */
 };
@@ -333,7 +312,7 @@ static struct opal_sg_list *image_data_to_sglist(void)
         addr = image_data.data;
         size = image_data.size;
 
-        sg1 = kzalloc((sizeof(struct opal_sg_list)), GFP_KERNEL);
+        sg1 = kzalloc(PAGE_SIZE, GFP_KERNEL);
         if (!sg1)
                 return NULL;
 
@@ -351,8 +330,7 @@ static struct opal_sg_list *image_data_to_sglist(void)
 
                 sg1->num_entries++;
                 if (sg1->num_entries >= SG_ENTRIES_PER_NODE) {
-                        sg1->next = kzalloc((sizeof(struct opal_sg_list)),
-                                            GFP_KERNEL);
+                        sg1->next = kzalloc(PAGE_SIZE, GFP_KERNEL);
                         if (!sg1->next) {
                                 pr_err("%s : Failed to allocate memory\n",
                                        __func__);
@@ -402,7 +380,10 @@ static int opal_flash_update(int op)
                 else
                         sg->next = NULL;
 
-                /* Make num_entries into the version/length field */
+                /*
+                 * Convert num_entries to version/length format
+                 * to satisfy OPAL.
+                 */
                 sg->num_entries = (SG_LIST_VERSION << 56) |
                         (sg->num_entries * sizeof(struct opal_sg_entry) + 16);
         }
@@ -500,7 +481,7 @@ static int alloc_image_buf(char *buffer, size_t count)
 
         memcpy(&image_header, (void *)buffer, sizeof(struct image_header_t));
         image_data.size = be32_to_cpu(image_header.size);
-        pr_debug("FLASH: Candiate image size = %u\n", image_data.size);
+        pr_debug("FLASH: Candidate image size = %u\n", image_data.size);
 
         if (image_data.size > MAX_IMAGE_SIZE) {
                 pr_warn("FLASH: Too large image\n");
diff --git a/arch/powerpc/platforms/powernv/opal-memory-errors.c b/arch/powerpc/platforms/powernv/opal-memory-errors.c
new file mode 100644
index 000000000000..ec4132239cdf
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-memory-errors.c
@@ -0,0 +1,146 @@
+/*
+ * OPAL asynchronus Memory error handling support in PowreNV.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2013 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include <asm/opal.h>
+#include <asm/cputable.h>
+
+static int opal_mem_err_nb_init;
+static LIST_HEAD(opal_memory_err_list);
+static DEFINE_SPINLOCK(opal_mem_err_lock);
+
+struct OpalMsgNode {
+        struct list_head list;
+        struct opal_msg msg;
+};
+
+static void handle_memory_error_event(struct OpalMemoryErrorData *merr_evt)
+{
+        uint64_t paddr_start, paddr_end;
+
+        pr_debug("%s: Retrived memory error event, type: 0x%x\n",
+                  __func__, merr_evt->type);
+        switch (merr_evt->type) {
+        case OPAL_MEM_ERR_TYPE_RESILIENCE:
+                paddr_start = merr_evt->u.resilience.physical_address_start;
+                paddr_end = merr_evt->u.resilience.physical_address_end;
+                break;
+        case OPAL_MEM_ERR_TYPE_DYN_DALLOC:
+                paddr_start = merr_evt->u.dyn_dealloc.physical_address_start;
+                paddr_end = merr_evt->u.dyn_dealloc.physical_address_end;
+                break;
+        default:
+                return;
+        }
+
+        for (; paddr_start < paddr_end; paddr_start += PAGE_SIZE) {
+                memory_failure(paddr_start >> PAGE_SHIFT, 0, 0);
+        }
+}
+
+static void handle_memory_error(void)
+{
+        unsigned long flags;
+        struct OpalMemoryErrorData *merr_evt;
+        struct OpalMsgNode *msg_node;
+
+        spin_lock_irqsave(&opal_mem_err_lock, flags);
+        while (!list_empty(&opal_memory_err_list)) {
+                 msg_node = list_entry(opal_memory_err_list.next,
+                                           struct OpalMsgNode, list);
+                list_del(&msg_node->list);
+                spin_unlock_irqrestore(&opal_mem_err_lock, flags);
+
+                merr_evt = (struct OpalMemoryErrorData *)
+                                        &msg_node->msg.params[0];
+                handle_memory_error_event(merr_evt);
+                kfree(msg_node);
+                spin_lock_irqsave(&opal_mem_err_lock, flags);
+        }
+        spin_unlock_irqrestore(&opal_mem_err_lock, flags);
+}
+
+static void mem_error_handler(struct work_struct *work)
+{
+        handle_memory_error();
+}
+
+static DECLARE_WORK(mem_error_work, mem_error_handler);
+
+/*
+ * opal_memory_err_event - notifier handler that queues up the opal message
+ * to be preocessed later.
+ */
+static int opal_memory_err_event(struct notifier_block *nb,
+                          unsigned long msg_type, void *msg)
+{
+        unsigned long flags;
+        struct OpalMsgNode *msg_node;
+
+        if (msg_type != OPAL_MSG_MEM_ERR)
+                return 0;
+
+        msg_node = kzalloc(sizeof(*msg_node), GFP_ATOMIC);
+        if (!msg_node) {
+                pr_err("MEMORY_ERROR: out of memory, Opal message event not"
+                       "handled\n");
+                return -ENOMEM;
+        }
+        memcpy(&msg_node->msg, msg, sizeof(struct opal_msg));
+
+        spin_lock_irqsave(&opal_mem_err_lock, flags);
+        list_add(&msg_node->list, &opal_memory_err_list);
+        spin_unlock_irqrestore(&opal_mem_err_lock, flags);
+
+        schedule_work(&mem_error_work);
+        return 0;
+}
+
+static struct notifier_block opal_mem_err_nb = {
+        .notifier_call  = opal_memory_err_event,
+        .next           = NULL,
+        .priority       = 0,
+};
+
+static int __init opal_mem_err_init(void)
+{
+        int ret;
+
+        if (!opal_mem_err_nb_init) {
+                ret = opal_message_notifier_register(
+                                        OPAL_MSG_MEM_ERR, &opal_mem_err_nb);
+                if (ret) {
+                        pr_err("%s: Can't register OPAL event notifier (%d)\n",
+                               __func__, ret);
+                        return ret;
+                }
+                opal_mem_err_nb_init = 1;
+        }
+        return 0;
+}
+subsys_initcall(opal_mem_err_init);
diff --git a/arch/powerpc/platforms/powernv/opal-rtc.c b/arch/powerpc/platforms/powernv/opal-rtc.c
index 7d07c7e80ec0..b1885db8fdf3 100644
--- a/arch/powerpc/platforms/powernv/opal-rtc.c
+++ b/arch/powerpc/platforms/powernv/opal-rtc.c
@@ -18,6 +18,7 @@
 
 #include <asm/opal.h>
 #include <asm/firmware.h>
+#include <asm/machdep.h>
 
 static void opal_to_tm(u32 y_m_d, u64 h_m_s_ms, struct rtc_time *tm)
 {
@@ -48,8 +49,11 @@ unsigned long __init opal_get_boot_time(void)
                 else
                         mdelay(10);
         }
-        if (rc != OPAL_SUCCESS)
+        if (rc != OPAL_SUCCESS) {
+                ppc_md.get_rtc_time = NULL;
+                ppc_md.set_rtc_time = NULL;
                 return 0;
+        }
         y_m_d = be32_to_cpu(__y_m_d);
         h_m_s_ms = be64_to_cpu(__h_m_s_ms);
         opal_to_tm(y_m_d, h_m_s_ms, &tm);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index e7806504e976..3e8829c40fbb 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -126,3 +126,6 @@ OPAL_CALL(opal_return_cpu,			OPAL_RETURN_CPU);
 OPAL_CALL(opal_validate_flash,                  OPAL_FLASH_VALIDATE);
 OPAL_CALL(opal_manage_flash,                    OPAL_FLASH_MANAGE);
 OPAL_CALL(opal_update_flash,                    OPAL_FLASH_UPDATE);
+OPAL_CALL(opal_get_msg,                         OPAL_GET_MSG);
+OPAL_CALL(opal_check_completion,                OPAL_CHECK_ASYNC_COMPLETION);
+OPAL_CALL(opal_sync_host_reboot,                OPAL_SYNC_HOST_REBOOT);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 1c798cd55372..65499adaecff 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -18,9 +18,12 @@
 #include <linux/interrupt.h>
 #include <linux/notifier.h>
 #include <linux/slab.h>
+#include <linux/sched.h>
 #include <linux/kobject.h>
+#include <linux/delay.h>
 #include <asm/opal.h>
 #include <asm/firmware.h>
+#include <asm/mce.h>
 
 #include "powernv.h"
 
@@ -38,6 +41,7 @@ extern u64 opal_mc_secondary_handler[];
 static unsigned int *opal_irqs;
 static unsigned int opal_irq_count;
 static ATOMIC_NOTIFIER_HEAD(opal_notifier_head);
+static struct atomic_notifier_head opal_msg_notifier_head[OPAL_MSG_TYPE_MAX];
 static DEFINE_SPINLOCK(opal_notifier_lock);
 static uint64_t last_notified_mask = 0x0ul;
 static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
@@ -88,14 +92,10 @@ static int __init opal_register_exception_handlers(void)
         if (!(powerpc_firmware_features & FW_FEATURE_OPAL))
                 return -ENODEV;
 
-        /* Hookup some exception handlers. We use the fwnmi area at 0x7000
-         * to provide the glue space to OPAL
+        /* Hookup some exception handlers except machine check. We use the
+         * fwnmi area at 0x7000 to provide the glue space to OPAL
          */
         glue = 0x7000;
-        opal_register_exception_handler(OPAL_MACHINE_CHECK_HANDLER,
-                                        __pa(opal_mc_secondary_handler[0]),
-                                        glue);
-        glue += 128;
         opal_register_exception_handler(OPAL_HYPERVISOR_MAINTENANCE_HANDLER,
                                         0, glue);
         glue += 128;
@@ -169,6 +169,95 @@ void opal_notifier_disable(void)
         atomic_set(&opal_notifier_hold, 1);
 }
 
+/*
+ * Opal message notifier based on message type. Allow subscribers to get
+ * notified for specific messgae type.
+ */
+int opal_message_notifier_register(enum OpalMessageType msg_type,
+                                        struct notifier_block *nb)
+{
+        if (!nb) {
+                pr_warning("%s: Invalid argument (%p)\n",
+                           __func__, nb);
+                return -EINVAL;
+        }
+        if (msg_type > OPAL_MSG_TYPE_MAX) {
+                pr_warning("%s: Invalid message type argument (%d)\n",
+                           __func__, msg_type);
+                return -EINVAL;
+        }
+        return atomic_notifier_chain_register(
+                                &opal_msg_notifier_head[msg_type], nb);
+}
+
+static void opal_message_do_notify(uint32_t msg_type, void *msg)
+{
+        /* notify subscribers */
+        atomic_notifier_call_chain(&opal_msg_notifier_head[msg_type],
+                                        msg_type, msg);
+}
+
+static void opal_handle_message(void)
+{
+        s64 ret;
+        /*
+         * TODO: pre-allocate a message buffer depending on opal-msg-size
+         * value in /proc/device-tree.
+         */
+        static struct opal_msg msg;
+
+        ret = opal_get_msg(__pa(&msg), sizeof(msg));
+        /* No opal message pending. */
+        if (ret == OPAL_RESOURCE)
+                return;
+
+        /* check for errors. */
+        if (ret) {
+                pr_warning("%s: Failed to retrive opal message, err=%lld\n",
+                                __func__, ret);
+                return;
+        }
+
+        /* Sanity check */
+        if (msg.msg_type > OPAL_MSG_TYPE_MAX) {
+                pr_warning("%s: Unknown message type: %u\n",
+                                __func__, msg.msg_type);
+                return;
+        }
+        opal_message_do_notify(msg.msg_type, (void *)&msg);
+}
+
+static int opal_message_notify(struct notifier_block *nb,
+                          unsigned long events, void *change)
+{
+        if (events & OPAL_EVENT_MSG_PENDING)
+                opal_handle_message();
+        return 0;
+}
+
+static struct notifier_block opal_message_nb = {
+        .notifier_call  = opal_message_notify,
+        .next           = NULL,
+        .priority       = 0,
+};
+
+static int __init opal_message_init(void)
+{
+        int ret, i;
+
+        for (i = 0; i < OPAL_MSG_TYPE_MAX; i++)
+                ATOMIC_INIT_NOTIFIER_HEAD(&opal_msg_notifier_head[i]);
+
+        ret = opal_notifier_register(&opal_message_nb);
+        if (ret) {
+                pr_err("%s: Can't register OPAL event notifier (%d)\n",
+                       __func__, ret);
+                return ret;
+        }
+        return 0;
+}
+early_initcall(opal_message_init);
+
 int opal_get_chars(uint32_t vtermno, char *buf, int count)
 {
         s64 rc;
@@ -254,119 +343,62 @@ int opal_put_chars(uint32_t vtermno, const char *data, int total_len)
         return written;
 }
 
+static int opal_recover_mce(struct pt_regs *regs,
+                                        struct machine_check_event *evt)
+{
+        int recovered = 0;
+        uint64_t ea = get_mce_fault_addr(evt);
+
+        if (!(regs->msr & MSR_RI)) {
+                /* If MSR_RI isn't set, we cannot recover */
+                recovered = 0;
+        } else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
+                /* Platform corrected itself */
+                recovered = 1;
+        } else if (ea && !is_kernel_addr(ea)) {
+                /*
+                 * Faulting address is not in kernel text. We should be fine.
+                 * We need to find which process uses this address.
+                 * For now, kill the task if we have received exception when
+                 * in userspace.
+                 *
+                 * TODO: Queue up this address for hwpoisioning later.
+                 */
+                if (user_mode(regs) && !is_global_init(current)) {
+                        _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+                        recovered = 1;
+                } else
+                        recovered = 0;
+        } else if (user_mode(regs) && !is_global_init(current) &&
+                evt->severity == MCE_SEV_ERROR_SYNC) {
+                /*
+                 * If we have received a synchronous error when in userspace
+                 * kill the task.
+                 */
+                _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+                recovered = 1;
+        }
+        return recovered;
+}
+
 int opal_machine_check(struct pt_regs *regs)
 {
-        struct opal_machine_check_event *opal_evt = get_paca()->opal_mc_evt;
-        struct opal_machine_check_event evt;
-        const char *level, *sevstr, *subtype;
-        static const char *opal_mc_ue_types[] = {
-                "Indeterminate",
-                "Instruction fetch",
-                "Page table walk ifetch",
-                "Load/Store",
-                "Page table walk Load/Store",
-        };
-        static const char *opal_mc_slb_types[] = {
-                "Indeterminate",
-                "Parity",
-                "Multihit",
-        };
-        static const char *opal_mc_erat_types[] = {
-                "Indeterminate",
-                "Parity",
-                "Multihit",
-        };
-        static const char *opal_mc_tlb_types[] = {
-                "Indeterminate",
-                "Parity",
-                "Multihit",
-        };
-
-        /* Copy the event structure and release the original */
-        evt = *opal_evt;
-        opal_evt->in_use = 0;
+        struct machine_check_event evt;
+
+        if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
+                return 0;
 
         /* Print things out */
-        if (evt.version != OpalMCE_V1) {
+        if (evt.version != MCE_V1) {
                 pr_err("Machine Check Exception, Unknown event version %d !\n",
                        evt.version);
                 return 0;
         }
-        switch(evt.severity) {
-        case OpalMCE_SEV_NO_ERROR:
-                level = KERN_INFO;
-                sevstr = "Harmless";
-                break;
-        case OpalMCE_SEV_WARNING:
-                level = KERN_WARNING;
-                sevstr = "";
-                break;
-        case OpalMCE_SEV_ERROR_SYNC:
-                level = KERN_ERR;
-                sevstr = "Severe";
-                break;
-        case OpalMCE_SEV_FATAL:
-        default:
-                level = KERN_ERR;
-                sevstr = "Fatal";
-                break;
-        }
+        machine_check_print_event_info(&evt);
 
-        printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
-               evt.disposition == OpalMCE_DISPOSITION_RECOVERED ?
-               "Recovered" : "[Not recovered");
-        printk("%s  Initiator: %s\n", level,
-               evt.initiator == OpalMCE_INITIATOR_CPU ? "CPU" : "Unknown");
-        switch(evt.error_type) {
-        case OpalMCE_ERROR_TYPE_UE:
-                subtype = evt.u.ue_error.ue_error_type <
-                        ARRAY_SIZE(opal_mc_ue_types) ?
-                        opal_mc_ue_types[evt.u.ue_error.ue_error_type]
-                        : "Unknown";
-                printk("%s  Error type: UE [%s]\n", level, subtype);
-                if (evt.u.ue_error.effective_address_provided)
-                        printk("%s    Effective address: %016llx\n",
-                               level, evt.u.ue_error.effective_address);
-                if (evt.u.ue_error.physical_address_provided)
-                        printk("%s      Physial address: %016llx\n",
-                               level, evt.u.ue_error.physical_address);
-                break;
-        case OpalMCE_ERROR_TYPE_SLB:
-                subtype = evt.u.slb_error.slb_error_type <
-                        ARRAY_SIZE(opal_mc_slb_types) ?
-                        opal_mc_slb_types[evt.u.slb_error.slb_error_type]
-                        : "Unknown";
-                printk("%s  Error type: SLB [%s]\n", level, subtype);
-                if (evt.u.slb_error.effective_address_provided)
-                        printk("%s    Effective address: %016llx\n",
-                               level, evt.u.slb_error.effective_address);
-                break;
-        case OpalMCE_ERROR_TYPE_ERAT:
-                subtype = evt.u.erat_error.erat_error_type <
-                        ARRAY_SIZE(opal_mc_erat_types) ?
-                        opal_mc_erat_types[evt.u.erat_error.erat_error_type]
-                        : "Unknown";
-                printk("%s  Error type: ERAT [%s]\n", level, subtype);
-                if (evt.u.erat_error.effective_address_provided)
-                        printk("%s    Effective address: %016llx\n",
-                               level, evt.u.erat_error.effective_address);
-                break;
-        case OpalMCE_ERROR_TYPE_TLB:
-                subtype = evt.u.tlb_error.tlb_error_type <
-                        ARRAY_SIZE(opal_mc_tlb_types) ?
-                        opal_mc_tlb_types[evt.u.tlb_error.tlb_error_type]
-                        : "Unknown";
-                printk("%s  Error type: TLB [%s]\n", level, subtype);
-                if (evt.u.tlb_error.effective_address_provided)
-                        printk("%s    Effective address: %016llx\n",
-                               level, evt.u.tlb_error.effective_address);
-                break;
-        default:
-        case OpalMCE_ERROR_TYPE_UNKNOWN:
-                printk("%s  Error type: Unknown\n", level);
-                break;
-        }
-        return evt.severity == OpalMCE_SEV_FATAL ? 0 : 1;
+        if (opal_recover_mce(regs, &evt))
+                return 1;
+        return 0;
 }
 
 static irqreturn_t opal_interrupt(int irq, void *data)
@@ -451,10 +483,25 @@ subsys_initcall(opal_init);
 void opal_shutdown(void)
 {
         unsigned int i;
+        long rc = OPAL_BUSY;
 
+        /* First free interrupts, which will also mask them */
         for (i = 0; i < opal_irq_count; i++) {
                 if (opal_irqs[i])
                         free_irq(opal_irqs[i], NULL);
                 opal_irqs[i] = 0;
         }
+
+        /*
+         * Then sync with OPAL which ensure anything that can
+         * potentially write to our memory has completed such
+         * as an ongoing dump retrieval
+         */
+        while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
+                rc = opal_sync_host_reboot();
+                if (rc == OPAL_BUSY)
+                        opal_poll_events(NULL);
+                else
+                        mdelay(10);
+        }
 }
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 2c6d173842b2..7d6dcc6d5fa9 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -460,7 +460,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
                 return;
 
         pe = &phb->ioda.pe_array[pdn->pe_number];
-        set_iommu_table_base(&pdev->dev, &pe->tce32_table);
+        set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
 }
 
 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
@@ -468,7 +468,7 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
         struct pci_dev *dev;
 
         list_for_each_entry(dev, &bus->devices, bus_list) {
-                set_iommu_table_base(&dev->dev, &pe->tce32_table);
+                set_iommu_table_base_and_group(&dev->dev, &pe->tce32_table);
                 if (dev->subordinate)
                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
         }
@@ -644,7 +644,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
         iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
 
         if (pe->pdev)
-                set_iommu_table_base(&pe->pdev->dev, tbl);
+                set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
         else
                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 
@@ -723,7 +723,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
         iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
 
         if (pe->pdev)
-                set_iommu_table_base(&pe->pdev->dev, tbl);
+                set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
         else
                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 
@@ -1144,7 +1144,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
 {
         struct pci_controller *hose;
         struct pnv_phb *phb;
-        unsigned long size, m32map_off, iomap_off, pemap_off;
+        unsigned long size, m32map_off, pemap_off, iomap_off = 0;
         const __be64 *prop64;
         const __be32 *prop32;
         int len;
@@ -1231,7 +1231,6 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
         m32map_off = size;
         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
-        iomap_off = size;
         if (phb->type == PNV_PHB_IODA1) {
                 iomap_off = size;
                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index f8b4bd8afb2e..e3807d69393e 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -92,7 +92,7 @@ static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
                                 pci_domain_nr(phb->hose->bus), phb->opal_id);
         }
 
-        set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
+        set_iommu_table_base_and_group(&pdev->dev, &phb->p5ioc2.iommu_table);
 }
 
 static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 4eb33a9ed532..b555ebc57ef5 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -124,77 +124,157 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
 }
 #endif /* CONFIG_PCI_MSI */
 
-static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
+static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
+                                         struct OpalIoPhbErrorCommon *common)
 {
-        struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
+        struct OpalIoP7IOCPhbErrorData *data;
         int i;
 
-        pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
-
-        pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);
-
-        pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
-        pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
-        pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);
-
-        pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
-        pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
-        pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
-        pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
-        pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);
-
-        pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
-        pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
-        pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
-        pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
-        pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
-        pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
-        pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
-        pr_info("  sourceId             = 0x%08x\n", data->sourceId);
-
-        pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
-        pr_info("  correlator           = 0x%016llx\n", data->correlator);
-
-        pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
-        pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
-        pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
-        pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
-        pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
-        pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
-        pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
-        pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
-        pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
-        pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
-        pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
-        pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
-        pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
-        pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
-        pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
-        pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
-        pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
-        pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
-        pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
-        pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
-        pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);
+        data = (struct OpalIoP7IOCPhbErrorData *)common;
+        pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n\n",
+                hose->global_number, common->version);
+
+        pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
+
+        pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
+        pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
+        pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
+
+        pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
+        pr_info("  slotStatus:           %08x\n", data->slotStatus);
+        pr_info("  linkStatus:           %08x\n", data->linkStatus);
+        pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
+        pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
+
+        pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
+        pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
+        pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
+        pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
+        pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
+        pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
+        pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
+        pr_info("  sourceId:             %08x\n", data->sourceId);
+        pr_info("  errorClass:           %016llx\n", data->errorClass);
+        pr_info("  correlator:           %016llx\n", data->correlator);
+        pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
+        pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
+        pr_info("  lemFir:               %016llx\n", data->lemFir);
+        pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
+        pr_info("  lemWOF:               %016llx\n", data->lemWOF);
+        pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
+        pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
+        pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
+        pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
+        pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
+        pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
+        pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
+        pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
+        pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
+        pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
+        pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
+        pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
+        pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
+        pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
+        pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
+        pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
 
         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
                 if ((data->pestA[i] >> 63) == 0 &&
                     (data->pestB[i] >> 63) == 0)
                         continue;
-                pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
-                pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
+
+                pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
+                pr_info("          PESTB:        %016llx\n", data->pestB[i]);
+        }
+}
+
+static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
+                                        struct OpalIoPhbErrorCommon *common)
+{
+        struct OpalIoPhb3ErrorData *data;
+        int i;
+
+        data = (struct OpalIoPhb3ErrorData*)common;
+        pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n\n",
+                hose->global_number, common->version);
+
+        pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
+
+        pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
+        pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
+        pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
+
+        pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
+        pr_info("  slotStatus:           %08x\n", data->slotStatus);
+        pr_info("  linkStatus:           %08x\n", data->linkStatus);
+        pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
+        pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
+
+        pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
+        pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
+        pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
+        pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
+        pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
+        pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
+        pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
+        pr_info("  sourceId:             %08x\n", data->sourceId);
+        pr_info("  errorClass:           %016llx\n", data->errorClass);
+        pr_info("  correlator:           %016llx\n", data->correlator);
+
+        pr_info("  nFir:                 %016llx\n", data->nFir);
+        pr_info("  nFirMask:             %016llx\n", data->nFirMask);
+        pr_info("  nFirWOF:              %016llx\n", data->nFirWOF);
+        pr_info("  PhbPlssr:             %016llx\n", data->phbPlssr);
+        pr_info("  PhbCsr:               %016llx\n", data->phbCsr);
+        pr_info("  lemFir:               %016llx\n", data->lemFir);
+        pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
+        pr_info("  lemWOF:               %016llx\n", data->lemWOF);
+        pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
+        pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
+        pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
+        pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
+        pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
+        pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
+        pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
+        pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
+        pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
+        pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
+        pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
+        pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
+        pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
+        pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
+        pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
+        pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
+
+        for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
+                if ((data->pestA[i] >> 63) == 0 &&
+                    (data->pestB[i] >> 63) == 0)
+                        continue;
+
+                pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
+                pr_info("          PESTB:        %016llx\n", data->pestB[i]);
         }
 }
 
-static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
+void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
+                                unsigned char *log_buff)
 {
-        switch(phb->model) {
-        case PNV_PHB_MODEL_P7IOC:
-                pnv_pci_dump_p7ioc_diag_data(phb);
+        struct OpalIoPhbErrorCommon *common;
+
+        if (!hose || !log_buff)
+                return;
+
+        common = (struct OpalIoPhbErrorCommon *)log_buff;
+        switch (common->ioType) {
+        case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
+                pnv_pci_dump_p7ioc_diag_data(hose, common);
+                break;
+        case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
+                pnv_pci_dump_phb3_diag_data(hose, common);
                 break;
         default:
-                pr_warning("PCI %d: Can't decode this PHB diag data\n",
-                           phb->hose->global_number);
+                pr_warn("%s: Unrecognized ioType %d\n",
+                        __func__, common->ioType);
         }
 }
 
@@ -222,7 +302,7 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
                  * with the normal errors generated when probing empty slots
                  */
                 if (has_diag)
-                        pnv_pci_dump_phb_diag_data(phb);
+                        pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
                 else
                         pr_warning("PCI %d: No diag data available\n",
                                    phb->hose->global_number);
@@ -484,7 +564,8 @@ void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 {
         tbl->it_blocksize = 16;
         tbl->it_base = (unsigned long)tce_mem;
-        tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
+        tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
+        tbl->it_offset = dma_offset >> tbl->it_page_shift;
         tbl->it_index = 0;
         tbl->it_size = tce_size >> 3;
         tbl->it_busno = 0;
@@ -536,7 +617,7 @@ static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
                 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
         if (!pdn->iommu_table)
                 return;
-        set_iommu_table_base(&pdev->dev, pdn->iommu_table);
+        set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
 }
 
 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
@@ -657,3 +738,32 @@ void __init pnv_pci_init(void)
         ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
 #endif
 }
+
+static int tce_iommu_bus_notifier(struct notifier_block *nb,
+                unsigned long action, void *data)
+{
+        struct device *dev = data;
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                return iommu_add_device(dev);
+        case BUS_NOTIFY_DEL_DEVICE:
+                if (dev->iommu_group)
+                        iommu_del_device(dev);
+                return 0;
+        default:
+                return 0;
+        }
+}
+
+static struct notifier_block tce_iommu_bus_nb = {
+        .notifier_call = tce_iommu_bus_notifier,
+};
+
+static int __init tce_iommu_bus_notifier_init(void)
+{
+        bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
+        return 0;
+}
+
+subsys_initcall_sync(tce_iommu_bus_notifier_init);
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 1ed8d5f40f5a..13f1942a9a5f 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -176,6 +176,7 @@ struct pnv_phb {
         union {
                 unsigned char                   blob[PNV_PCI_DIAG_BUF_SIZE];
                 struct OpalIoP7IOCPhbErrorData  p7ioc;
+                struct OpalIoPhb3ErrorData      phb3;
                 struct OpalIoP7IOCErrorData     hub_diag;
         } diag;
 
@@ -186,6 +187,8 @@ extern struct pci_ops pnv_pci_ops;
 extern struct pnv_eeh_ops ioda_eeh_ops;
 #endif
 
+void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
+                                unsigned char *log_buff);
 int pnv_pci_cfg_read(struct device_node *dn,
                      int where, int size, u32 *val);
 int pnv_pci_cfg_write(struct device_node *dn,
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 19884b2a51b4..21166f65c97c 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -26,6 +26,7 @@
 #include <linux/of_fdt.h>
 #include <linux/interrupt.h>
 #include <linux/bug.h>
+#include <linux/cpuidle.h>
 
 #include <asm/machdep.h>
 #include <asm/firmware.h>
@@ -145,8 +146,10 @@ static void pnv_shutdown(void)
         /* Let the PCI code clear up IODA tables */
         pnv_pci_shutdown();
 
-        /* And unregister all OPAL interrupts so they don't fire
-         * up while we kexec
+        /*
+         * Stop OPAL activity: Unregister all OPAL interrupts so they
+         * don't fire up while we kexec and make sure all potentially
+         * DMA'ing ops are complete (such as dump retrieval).
          */
         opal_shutdown();
 }
@@ -214,6 +217,16 @@ static int __init pnv_probe(void)
         return 1;
 }
 
+void powernv_idle(void)
+{
+        /* Hook to cpuidle framework if available, else
+         * call on default platform idle code
+         */
+        if (cpuidle_idle_call()) {
+                power7_idle();
+        }
+}
+
 define_machine(powernv) {
         .name                   = "PowerNV",
         .probe                  = pnv_probe,
@@ -223,7 +236,7 @@ define_machine(powernv) {
         .show_cpuinfo           = pnv_show_cpuinfo,
         .progress               = pnv_progress,
         .machine_shutdown       = pnv_shutdown,
-        .power_save             = power7_idle,
+        .power_save             = powernv_idle,
         .calibrate_decr         = generic_calibrate_decr,
 #ifdef CONFIG_KEXEC
         .kexec_cpu_down         = pnv_kexec_cpu_down,
diff --git a/arch/powerpc/platforms/ps3/spu.c b/arch/powerpc/platforms/ps3/spu.c
index e17fa1432d80..a0bca05e26b0 100644
--- a/arch/powerpc/platforms/ps3/spu.c
+++ b/arch/powerpc/platforms/ps3/spu.c
@@ -143,7 +143,7 @@ static void _dump_areas(unsigned int spe_id, unsigned long priv2,
         pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
 }
 
-inline u64 ps3_get_spe_id(void *arg)
+u64 ps3_get_spe_id(void *arg)
 {
         return spu_pdata(arg)->spe_id;
 }
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 62b4f8025de0..37300f6ee244 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -34,7 +34,7 @@ config PPC_SPLPAR
 
 config PSERIES_MSI
        bool
-       depends on PCI_MSI && EEH
+       depends on PCI_MSI && PPC_PSERIES && EEH
        default y
 
 config PSERIES_ENERGY
@@ -119,12 +119,3 @@ config DTL
           which are accessible through a debugfs file.
 
           Say N if you are unsure.
-
-config PSERIES_IDLE
-        bool "Cpuidle driver for pSeries platforms"
-        depends on CPU_IDLE
-        depends on PPC_PSERIES
-        default y
-        help
-          Select this option to enable processor idle state management
-          through cpuidle subsystem.
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index fbccac9cd2dc..03480796af9a 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_HCALL_STATS)	+= hvCall_inst.o
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_DTL)               += dtl.o
 obj-$(CONFIG_IO_EVENT_IRQ)      += io_event_irq.o
-obj-$(CONFIG_PSERIES_IDLE)      += processor_idle.o
 obj-$(CONFIG_LPARCFG)           += lparcfg.o
 
 ifeq ($(CONFIG_PPC_PSERIES),y)
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index 1e561bef459b..2d8bf15879fd 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -25,7 +25,6 @@
 #include <linux/errno.h>
 #include <linux/fs.h>
 #include <linux/gfp.h>
-#include <linux/init.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/oom.h>
diff --git a/arch/powerpc/platforms/pseries/dtl.c b/arch/powerpc/platforms/pseries/dtl.c
index 5db66f1fbc26..7d61498e45c0 100644
--- a/arch/powerpc/platforms/pseries/dtl.c
+++ b/arch/powerpc/platforms/pseries/dtl.c
@@ -20,7 +20,6 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/debugfs.h>
 #include <linux/spinlock.h>
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index ccb633e077b1..9ef3cc8ebc11 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -689,7 +689,9 @@ static struct eeh_ops pseries_eeh_ops = {
         .get_log                = pseries_eeh_get_log,
         .configure_bridge       = pseries_eeh_configure_bridge,
         .read_config            = pseries_eeh_read_config,
-        .write_config           = pseries_eeh_write_config
+        .write_config           = pseries_eeh_write_config,
+        .next_error             = NULL,
+        .restore_config         = NULL
 };
 
 /**
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index f253361552ae..33b552ffbe57 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -486,9 +486,10 @@ static void iommu_table_setparms(struct pci_controller *phb,
                 memset((void *)tbl->it_base, 0, *sizep);
 
         tbl->it_busno = phb->bus->number;
+        tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 
         /* Units of tce entries */
-        tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
+        tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 
         /* Test if we are going over 2GB of DMA space */
         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
@@ -499,7 +500,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
         phb->dma_window_base_cur += phb->dma_window_size;
 
         /* Set the tce table size - measured in entries */
-        tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
+        tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 
         tbl->it_index = 0;
         tbl->it_blocksize = 16;
@@ -537,11 +538,12 @@ static void iommu_table_setparms_lpar(struct pci_controller *phb,
         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 
         tbl->it_busno = phb->bus->number;
+        tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
         tbl->it_base   = 0;
         tbl->it_blocksize  = 16;
         tbl->it_type = TCE_PCI;
-        tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
-        tbl->it_size = size >> IOMMU_PAGE_SHIFT;
+        tbl->it_offset = offset >> tbl->it_page_shift;
+        tbl->it_size = size >> tbl->it_page_shift;
 }
 
 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
@@ -687,7 +689,8 @@ static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
                 iommu_table_setparms(phb, dn, tbl);
                 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
                 iommu_register_group(tbl, pci_domain_nr(phb->bus), 0);
-                set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
+                set_iommu_table_base_and_group(&dev->dev,
+                                               PCI_DN(dn)->iommu_table);
                 return;
         }
 
@@ -699,7 +702,8 @@ static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
                 dn = dn->parent;
 
         if (dn && PCI_DN(dn))
-                set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
+                set_iommu_table_base_and_group(&dev->dev,
+                                               PCI_DN(dn)->iommu_table);
         else
                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
                        pci_name(dev));
@@ -717,21 +721,6 @@ static int __init disable_ddw_setup(char *str)
 
 early_param("disable_ddw", disable_ddw_setup);
 
-static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
-{
-        int ret;
-
-        ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
-        if (ret)
-                pr_warning("%s: failed to remove DMA window: rtas returned "
-                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
-                        np->full_name, ret, ddw_avail[2], liobn);
-        else
-                pr_debug("%s: successfully removed DMA window: rtas returned "
-                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
-                        np->full_name, ret, ddw_avail[2], liobn);
-}
-
 static void remove_ddw(struct device_node *np)
 {
         struct dynamic_dma_window_prop *dwp;
@@ -761,7 +750,15 @@ static void remove_ddw(struct device_node *np)
                 pr_debug("%s successfully cleared tces in window.\n",
                          np->full_name);
 
-        __remove_ddw(np, ddw_avail, liobn);
+        ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
+        if (ret)
+                pr_warning("%s: failed to remove direct window: rtas returned "
+                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
+                        np->full_name, ret, ddw_avail[2], liobn);
+        else
+                pr_debug("%s: successfully removed direct window: rtas returned "
+                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
+                        np->full_name, ret, ddw_avail[2], liobn);
 
 delprop:
         ret = of_remove_property(np, win64);
@@ -790,68 +787,33 @@ static u64 find_existing_ddw(struct device_node *pdn)
         return dma_addr;
 }
 
-static void __restore_default_window(struct eeh_dev *edev,
-                                                u32 ddw_restore_token)
-{
-        u32 cfg_addr;
-        u64 buid;
-        int ret;
-
-        /*
-         * Get the config address and phb buid of the PE window.
-         * Rely on eeh to retrieve this for us.
-         * Retrieve them from the pci device, not the node with the
-         * dma-window property
-         */
-        cfg_addr = edev->config_addr;
-        if (edev->pe_config_addr)
-                cfg_addr = edev->pe_config_addr;
-        buid = edev->phb->buid;
-
-        do {
-                ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
-                                        BUID_HI(buid), BUID_LO(buid));
-        } while (rtas_busy_delay(ret));
-        pr_info("ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
-                 ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
-}
-
 static int find_existing_ddw_windows(void)
 {
+        int len;
         struct device_node *pdn;
+        struct direct_window *window;
         const struct dynamic_dma_window_prop *direct64;
-        const u32 *ddw_extensions;
 
         if (!firmware_has_feature(FW_FEATURE_LPAR))
                 return 0;
 
         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
-                direct64 = of_get_property(pdn, DIRECT64_PROPNAME, NULL);
+                direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
                 if (!direct64)
                         continue;
 
-                /*
-                 * We need to ensure the IOMMU table is active when we
-                 * return from the IOMMU setup so that the common code
-                 * can clear the table or find the holes. To that end,
-                 * first, remove any existing DDW configuration.
-                 */
-                remove_ddw(pdn);
+                window = kzalloc(sizeof(*window), GFP_KERNEL);
+                if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
+                        kfree(window);
+                        remove_ddw(pdn);
+                        continue;
+                }
 
-                /*
-                 * Second, if we are running on a new enough level of
-                 * firmware where the restore API is present, use it to
-                 * restore the 32-bit window, which was removed in
-                 * create_ddw.
-                 * If the API is not present, then create_ddw couldn't
-                 * have removed the 32-bit window in the first place, so
-                 * removing the DDW configuration should be sufficient.
-                 */
-                ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions",
-                                                                        NULL);
-                if (ddw_extensions && ddw_extensions[0] > 0)
-                        __restore_default_window(of_node_to_eeh_dev(pdn),
-                                                        ddw_extensions[1]);
+                window->device = pdn;
+                window->prop = direct64;
+                spin_lock(&direct_window_list_lock);
+                list_add(&window->list, &direct_window_list);
+                spin_unlock(&direct_window_list_lock);
         }
 
         return 0;
@@ -921,12 +883,6 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
         return ret;
 }
 
-static void restore_default_window(struct pci_dev *dev,
-                                        u32 ddw_restore_token)
-{
-        __restore_default_window(pci_dev_to_eeh_dev(dev), ddw_restore_token);
-}
-
 struct failed_ddw_pdn {
         struct device_node *pdn;
         struct list_head list;
@@ -954,13 +910,9 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         u64 dma_addr, max_addr;
         struct device_node *dn;
         const u32 *uninitialized_var(ddw_avail);
-        const u32 *uninitialized_var(ddw_extensions);
-        u32 ddw_restore_token = 0;
         struct direct_window *window;
         struct property *win64;
         struct dynamic_dma_window_prop *ddwprop;
-        const void *dma_window = NULL;
-        unsigned long liobn, offset, size;
         struct failed_ddw_pdn *fpdn;
 
         mutex_lock(&direct_window_init_mutex);
@@ -991,42 +943,9 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
          */
         ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
         if (!ddw_avail || len < 3 * sizeof(u32))
-                goto out_unlock;
-
-        /*
-         * the extensions property is only required to exist in certain
-         * levels of firmware and later
-         * the ibm,ddw-extensions property is a list with the first
-         * element containing the number of extensions and each
-         * subsequent entry is a value corresponding to that extension
-         */
-        ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
-        if (ddw_extensions) {
-                /*
-                 * each new defined extension length should be added to
-                 * the top of the switch so the "earlier" entries also
-                 * get picked up
-                 */
-                switch (ddw_extensions[0]) {
-                        /* ibm,reset-pe-dma-windows */
-                        case 1:
-                                ddw_restore_token = ddw_extensions[1];
-                                break;
-                }
-        }
-
-        /*
-         * Only remove the existing DMA window if we can restore back to
-         * the default state. Removing the existing window maximizes the
-         * resources available to firmware for dynamic window creation.
-         */
-        if (ddw_restore_token) {
-                dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
-                of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
-                __remove_ddw(pdn, ddw_avail, liobn);
-        }
+                goto out_failed;
 
-        /*
+       /*
          * Query if there is a second window of size to map the
          * whole partition.  Query returns number of windows, largest
          * block assigned to PE (partition endpoint), and two bitmasks
@@ -1035,7 +954,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         dn = pci_device_to_OF_node(dev);
         ret = query_ddw(dev, ddw_avail, &query);
         if (ret != 0)
-                goto out_restore_window;
+                goto out_failed;
 
         if (query.windows_available == 0) {
                 /*
@@ -1044,7 +963,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
                  * trading in for a larger page size.
                  */
                 dev_dbg(&dev->dev, "no free dynamic windows");
-                goto out_restore_window;
+                goto out_failed;
         }
         if (be32_to_cpu(query.page_size) & 4) {
                 page_shift = 24; /* 16MB */
@@ -1055,7 +974,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         } else {
                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
                           query.page_size);
-                goto out_restore_window;
+                goto out_failed;
         }
         /* verify the window * number of ptes will map the partition */
         /* check largest block * page size > max memory hotplug addr */
@@ -1064,14 +983,14 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
                           1ULL << page_shift);
-                goto out_restore_window;
+                goto out_failed;
         }
         len = order_base_2(max_addr);
         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
         if (!win64) {
                 dev_info(&dev->dev,
                         "couldn't allocate property for 64bit dma window\n");
-                goto out_restore_window;
+                goto out_failed;
         }
         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
@@ -1133,9 +1052,7 @@ out_free_prop:
         kfree(win64->value);
         kfree(win64);
 
-out_restore_window:
-        if (ddw_restore_token)
-                restore_default_window(dev, ddw_restore_token);
+out_failed:
 
         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
         if (!fpdn)
@@ -1193,7 +1110,7 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
                 pr_debug("  found DMA window, table: %p\n", pci->iommu_table);
         }
 
-        set_iommu_table_base(&dev->dev, pci->iommu_table);
+        set_iommu_table_base_and_group(&dev->dev, pci->iommu_table);
 }
 
 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 4fca3def9db9..b02af9ef3ff6 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -92,7 +92,7 @@ void vpa_init(int cpu)
          * PAPR says this feature is SLB-Buffer but firmware never
          * reports that.  All SPLPAR support SLB shadow buffer.
          */
-        addr = __pa(&slb_shadow[cpu]);
+        addr = __pa(paca[cpu].slb_shadow_ptr);
         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
                 ret = register_slb_shadow(hwcpu, addr);
                 if (ret)
@@ -153,7 +153,8 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
 
         /* Make pHyp happy */
         if ((rflags & _PAGE_NO_CACHE) && !(rflags & _PAGE_WRITETHRU))
-                hpte_r &= ~_PAGE_COHERENT;
+                hpte_r &= ~HPTE_R_M;
+
         if (firmware_has_feature(FW_FEATURE_XCMO) && !(hpte_r & HPTE_R_N))
                 flags |= H_COALESCE_CAND;
 
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
deleted file mode 100644
index a166e38bd683..000000000000
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- *  processor_idle - idle state cpuidle driver.
- *  Adapted from drivers/idle/intel_idle.c and
- *  drivers/acpi/processor_idle.c
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/moduleparam.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu.h>
-#include <linux/notifier.h>
-
-#include <asm/paca.h>
-#include <asm/reg.h>
-#include <asm/machdep.h>
-#include <asm/firmware.h>
-#include <asm/runlatch.h>
-#include <asm/plpar_wrappers.h>
-
-struct cpuidle_driver pseries_idle_driver = {
-        .name             = "pseries_idle",
-        .owner            = THIS_MODULE,
-};
-
-#define MAX_IDLE_STATE_COUNT    2
-
-static int max_idle_state = MAX_IDLE_STATE_COUNT - 1;
-static struct cpuidle_device __percpu *pseries_cpuidle_devices;
-static struct cpuidle_state *cpuidle_state_table;
-
-static inline void idle_loop_prolog(unsigned long *in_purr)
-{
-        *in_purr = mfspr(SPRN_PURR);
-        /*
-         * Indicate to the HV that we are idle. Now would be
-         * a good time to find other work to dispatch.
-         */
-        get_lppaca()->idle = 1;
-}
-
-static inline void idle_loop_epilog(unsigned long in_purr)
-{
-        u64 wait_cycles;
-
-        wait_cycles = be64_to_cpu(get_lppaca()->wait_state_cycles);
-        wait_cycles += mfspr(SPRN_PURR) - in_purr;
-        get_lppaca()->wait_state_cycles = cpu_to_be64(wait_cycles);
-        get_lppaca()->idle = 0;
-}
-
-static int snooze_loop(struct cpuidle_device *dev,
-                        struct cpuidle_driver *drv,
-                        int index)
-{
-        unsigned long in_purr;
-        int cpu = dev->cpu;
-
-        idle_loop_prolog(&in_purr);
-        local_irq_enable();
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        while ((!need_resched()) && cpu_online(cpu)) {
-                ppc64_runlatch_off();
-                HMT_low();
-                HMT_very_low();
-        }
-
-        HMT_medium();
-        clear_thread_flag(TIF_POLLING_NRFLAG);
-        smp_mb();
-
-        idle_loop_epilog(in_purr);
-
-        return index;
-}
-
-static void check_and_cede_processor(void)
-{
-        /*
-         * Ensure our interrupt state is properly tracked,
-         * also checks if no interrupt has occurred while we
-         * were soft-disabled
-         */
-        if (prep_irq_for_idle()) {
-                cede_processor();
-#ifdef CONFIG_TRACE_IRQFLAGS
-                /* Ensure that H_CEDE returns with IRQs on */
-                if (WARN_ON(!(mfmsr() & MSR_EE)))
-                        __hard_irq_enable();
-#endif
-        }
-}
-
-static int dedicated_cede_loop(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
-{
-        unsigned long in_purr;
-
-        idle_loop_prolog(&in_purr);
-        get_lppaca()->donate_dedicated_cpu = 1;
-
-        ppc64_runlatch_off();
-        HMT_medium();
-        check_and_cede_processor();
-
-        get_lppaca()->donate_dedicated_cpu = 0;
-
-        idle_loop_epilog(in_purr);
-
-        return index;
-}
-
-static int shared_cede_loop(struct cpuidle_device *dev,
-                        struct cpuidle_driver *drv,
-                        int index)
-{
-        unsigned long in_purr;
-
-        idle_loop_prolog(&in_purr);
-
-        /*
-         * Yield the processor to the hypervisor.  We return if
-         * an external interrupt occurs (which are driven prior
-         * to returning here) or if a prod occurs from another
-         * processor. When returning here, external interrupts
-         * are enabled.
-         */
-        check_and_cede_processor();
-
-        idle_loop_epilog(in_purr);
-
-        return index;
-}
-
-/*
- * States for dedicated partition case.
- */
-static struct cpuidle_state dedicated_states[MAX_IDLE_STATE_COUNT] = {
-        { /* Snooze */
-                .name = "snooze",
-                .desc = "snooze",
-                .flags = CPUIDLE_FLAG_TIME_VALID,
-                .exit_latency = 0,
-                .target_residency = 0,
-                .enter = &snooze_loop },
-        { /* CEDE */
-                .name = "CEDE",
-                .desc = "CEDE",
-                .flags = CPUIDLE_FLAG_TIME_VALID,
-                .exit_latency = 10,
-                .target_residency = 100,
-                .enter = &dedicated_cede_loop },
-};
-
-/*
- * States for shared partition case.
- */
-static struct cpuidle_state shared_states[MAX_IDLE_STATE_COUNT] = {
-        { /* Shared Cede */
-                .name = "Shared Cede",
-                .desc = "Shared Cede",
-                .flags = CPUIDLE_FLAG_TIME_VALID,
-                .exit_latency = 0,
-                .target_residency = 0,
-                .enter = &shared_cede_loop },
-};
-
-void update_smt_snooze_delay(int cpu, int residency)
-{
-        struct cpuidle_driver *drv = cpuidle_get_driver();
-        struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
-
-        if (cpuidle_state_table != dedicated_states)
-                return;
-
-        if (residency < 0) {
-                /* Disable the Nap state on that cpu */
-                if (dev)
-                        dev->states_usage[1].disable = 1;
-        } else
-                if (drv)
-                        drv->states[1].target_residency = residency;
-}
-
-static int pseries_cpuidle_add_cpu_notifier(struct notifier_block *n,
-                        unsigned long action, void *hcpu)
-{
-        int hotcpu = (unsigned long)hcpu;
-        struct cpuidle_device *dev =
-                        per_cpu_ptr(pseries_cpuidle_devices, hotcpu);
-
-        if (dev && cpuidle_get_driver()) {
-                switch (action) {
-                case CPU_ONLINE:
-                case CPU_ONLINE_FROZEN:
-                        cpuidle_pause_and_lock();
-                        cpuidle_enable_device(dev);
-                        cpuidle_resume_and_unlock();
-                        break;
-
-                case CPU_DEAD:
-                case CPU_DEAD_FROZEN:
-                        cpuidle_pause_and_lock();
-                        cpuidle_disable_device(dev);
-                        cpuidle_resume_and_unlock();
-                        break;
-
-                default:
-                        return NOTIFY_DONE;
-                }
-        }
-        return NOTIFY_OK;
-}
-
-static struct notifier_block setup_hotplug_notifier = {
-        .notifier_call = pseries_cpuidle_add_cpu_notifier,
-};
-
-/*
- * pseries_cpuidle_driver_init()
- */
-static int pseries_cpuidle_driver_init(void)
-{
-        int idle_state;
-        struct cpuidle_driver *drv = &pseries_idle_driver;
-
-        drv->state_count = 0;
-
-        for (idle_state = 0; idle_state < MAX_IDLE_STATE_COUNT; ++idle_state) {
-
-                if (idle_state > max_idle_state)
-                        break;
-
-                /* is the state not enabled? */
-                if (cpuidle_state_table[idle_state].enter == NULL)
-                        continue;
-
-                drv->states[drv->state_count] = /* structure copy */
-                        cpuidle_state_table[idle_state];
-
-                drv->state_count += 1;
-        }
-
-        return 0;
-}
-
-/* pseries_idle_devices_uninit(void)
- * unregister cpuidle devices and de-allocate memory
- */
-static void pseries_idle_devices_uninit(void)
-{
-        int i;
-        struct cpuidle_device *dev;
-
-        for_each_possible_cpu(i) {
-                dev = per_cpu_ptr(pseries_cpuidle_devices, i);
-                cpuidle_unregister_device(dev);
-        }
-
-        free_percpu(pseries_cpuidle_devices);
-        return;
-}
-
-/* pseries_idle_devices_init()
- * allocate, initialize and register cpuidle device
- */
-static int pseries_idle_devices_init(void)
-{
-        int i;
-        struct cpuidle_driver *drv = &pseries_idle_driver;
-        struct cpuidle_device *dev;
-
-        pseries_cpuidle_devices = alloc_percpu(struct cpuidle_device);
-        if (pseries_cpuidle_devices == NULL)
-                return -ENOMEM;
-
-        for_each_possible_cpu(i) {
-                dev = per_cpu_ptr(pseries_cpuidle_devices, i);
-                dev->state_count = drv->state_count;
-                dev->cpu = i;
-                if (cpuidle_register_device(dev)) {
-                        printk(KERN_DEBUG \
-                                "cpuidle_register_device %d failed!\n", i);
-                        return -EIO;
-                }
-        }
-
-        return 0;
-}
-
-/*
- * pseries_idle_probe()
- * Choose state table for shared versus dedicated partition
- */
-static int pseries_idle_probe(void)
-{
-
-        if (!firmware_has_feature(FW_FEATURE_SPLPAR))
-                return -ENODEV;
-
-        if (cpuidle_disable != IDLE_NO_OVERRIDE)
-                return -ENODEV;
-
-        if (max_idle_state == 0) {
-                printk(KERN_DEBUG "pseries processor idle disabled.\n");
-                return -EPERM;
-        }
-
-        if (lppaca_shared_proc(get_lppaca()))
-                cpuidle_state_table = shared_states;
-        else
-                cpuidle_state_table = dedicated_states;
-
-        return 0;
-}
-
-static int __init pseries_processor_idle_init(void)
-{
-        int retval;
-
-        retval = pseries_idle_probe();
-        if (retval)
-                return retval;
-
-        pseries_cpuidle_driver_init();
-        retval = cpuidle_register_driver(&pseries_idle_driver);
-        if (retval) {
-                printk(KERN_DEBUG "Registration of pseries driver failed.\n");
-                return retval;
-        }
-
-        retval = pseries_idle_devices_init();
-        if (retval) {
-                pseries_idle_devices_uninit();
-                cpuidle_unregister_driver(&pseries_idle_driver);
-                return retval;
-        }
-
-        register_cpu_notifier(&setup_hotplug_notifier);
-        printk(KERN_DEBUG "pseries_idle_driver registered\n");
-
-        return 0;
-}
-
-static void __exit pseries_processor_idle_exit(void)
-{
-
-        unregister_cpu_notifier(&setup_hotplug_notifier);
-        pseries_idle_devices_uninit();
-        cpuidle_unregister_driver(&pseries_idle_driver);
-
-        return;
-}
-
-module_init(pseries_processor_idle_init);
-module_exit(pseries_processor_idle_exit);
-
-MODULE_AUTHOR("Deepthi Dharwar <deepthi@linux.vnet.ibm.com>");
-MODULE_DESCRIPTION("Cpuidle driver for POWER");
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 6f76ae417f47..8e639d7cbda7 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -72,7 +72,7 @@
 
 int CMO_PrPSP = -1;
 int CMO_SecPSP = -1;
-unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT);
+unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
 EXPORT_SYMBOL(CMO_PageSize);
 
 int fwnmi_active;  /* TRUE if an FWNMI handler is present */
@@ -569,7 +569,7 @@ void pSeries_cmo_feature_init(void)
 {
         char *ptr, *key, *value, *end;
         int call_status;
-        int page_order = IOMMU_PAGE_SHIFT;
+        int page_order = IOMMU_PAGE_SHIFT_4K;
 
         pr_debug(" -> fw_cmo_feature_init()\n");
         spin_lock(&rtas_data_buf_lock);
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
index 62cb527493e7..9a15e5b39bb8 100644
--- a/arch/powerpc/platforms/wsp/wsp_pci.c
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -260,7 +260,7 @@ static int tce_build_wsp(struct iommu_table *tbl, long index, long npages,
                 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 
                 dma_debug("[DMA] TCE %p set to 0x%016llx (dma addr: 0x%lx)\n",
-                          tcep, *tcep, (tbl->it_offset + index) << IOMMU_PAGE_SHIFT);
+                          tcep, *tcep, (tbl->it_offset + index) << IOMMU_PAGE_SHIFT_4K);
 
                 uaddr += TCE_PAGE_SIZE;
                 index++;
@@ -381,8 +381,9 @@ static struct wsp_dma_table *wsp_pci_create_dma32_table(struct wsp_phb *phb,
 
         /* Init bits and pieces */
         tbl->table.it_blocksize = 16;
-        tbl->table.it_offset = addr >> IOMMU_PAGE_SHIFT;
-        tbl->table.it_size = size >> IOMMU_PAGE_SHIFT;
+        tbl->table.it_page_shift = IOMMU_PAGE_SHIFT_4K;
+        tbl->table.it_offset = addr >> tbl->table.it_page_shift;
+        tbl->table.it_size = size >> tbl->table.it_page_shift;
 
         /*
          * It's already blank but we clear it anyway.
@@ -449,8 +450,8 @@ static void wsp_pci_dma_dev_setup(struct pci_dev *pdev)
         if (table) {
                 pr_info("%s: Setup iommu: 32-bit DMA region 0x%08lx..0x%08lx\n",
                         pci_name(pdev),
-                        table->table.it_offset << IOMMU_PAGE_SHIFT,
-                        (table->table.it_offset << IOMMU_PAGE_SHIFT)
+                        table->table.it_offset << IOMMU_PAGE_SHIFT_4K,
+                        (table->table.it_offset << IOMMU_PAGE_SHIFT_4K)
                         + phb->dma32_region_size - 1);
                 archdata->dma_data.iommu_table_base = &table->table;
                 return;
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 13ec968be4c7..7baa70d6dc01 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -19,7 +19,7 @@ config PPC_MSI_BITMAP
         default y if MPIC
         default y if FSL_PCI
         default y if PPC4xx_MSI
-        default y if POWERNV_MSI
+        default y if PPC_POWERNV
 
 source "arch/powerpc/sysdev/xics/Kconfig"
 
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index 1c16141c031c..47b6b9f81d43 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -109,27 +109,28 @@ axon_ram_make_request(struct request_queue *queue, struct bio *bio)
         struct axon_ram_bank *bank = bio->bi_bdev->bd_disk->private_data;
         unsigned long phys_mem, phys_end;
         void *user_mem;
-        struct bio_vec *vec;
+        struct bio_vec vec;
         unsigned int transfered;
-        unsigned short idx;
+        struct bvec_iter iter;
 
-        phys_mem = bank->io_addr + (bio->bi_sector << AXON_RAM_SECTOR_SHIFT);
+        phys_mem = bank->io_addr + (bio->bi_iter.bi_sector <<
+                                    AXON_RAM_SECTOR_SHIFT);
         phys_end = bank->io_addr + bank->size;
         transfered = 0;
-        bio_for_each_segment(vec, bio, idx) {
-                if (unlikely(phys_mem + vec->bv_len > phys_end)) {
+        bio_for_each_segment(vec, bio, iter) {
+                if (unlikely(phys_mem + vec.bv_len > phys_end)) {
                         bio_io_error(bio);
                         return;
                 }
 
-                user_mem = page_address(vec->bv_page) + vec->bv_offset;
+                user_mem = page_address(vec.bv_page) + vec.bv_offset;
                 if (bio_data_dir(bio) == READ)
-                        memcpy(user_mem, (void *) phys_mem, vec->bv_len);
+                        memcpy(user_mem, (void *) phys_mem, vec.bv_len);
                 else
-                        memcpy((void *) phys_mem, user_mem, vec->bv_len);
+                        memcpy((void *) phys_mem, user_mem, vec.bv_len);
 
-                phys_mem += vec->bv_len;
-                transfered += vec->bv_len;
+                phys_mem += vec.bv_len;
+                transfered += vec.bv_len;
         }
         bio_endio(bio, 0);
 }
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 10386b676d87..a11bd1d433ad 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -27,7 +27,6 @@
  */
 
 #include <linux/stddef.h>
-#include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <linux/irq.h>
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index bd968a43a48b..62c47bb76517 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -292,6 +292,7 @@ static void iommu_table_dart_setup(void)
         iommu_table_dart.it_offset = 0;
         /* it_size is in number of entries */
         iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
+        iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;
 
         /* Initialize the common IOMMU code */
         iommu_table_dart.it_base = (unsigned long)dart_vbase;
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
index d7fc72239144..fbc885b31946 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -19,7 +19,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/compiler.h>
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 6bc5a546d49f..d631022ffb4b 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -214,10 +214,14 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
         struct fsl_lbc_ctrl *ctrl = data;
         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
         u32 status;
+        unsigned long flags;
 
+        spin_lock_irqsave(&fsl_lbc_lock, flags);
         status = in_be32(&lbc->ltesr);
-        if (!status)
+        if (!status) {
+                spin_unlock_irqrestore(&fsl_lbc_lock, flags);
                 return IRQ_NONE;
+        }
 
         out_be32(&lbc->ltesr, LTESR_CLEAR);
         out_be32(&lbc->lteatr, 0);
@@ -260,6 +264,7 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
         if (status & ~LTESR_MASK)
                 dev_err(ctrl->dev, "Unknown error: "
                         "LTESR 0x%08X\n", status);
+        spin_unlock_irqrestore(&fsl_lbc_lock, flags);
         return IRQ_HANDLED;
 }
 
@@ -298,8 +303,8 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
                 goto err;
         }
 
-        fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
-        if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
+        fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
+        if (!fsl_lbc_ctrl_dev->irq[0]) {
                 dev_err(&dev->dev, "failed to get irq resource\n");
                 ret = -ENODEV;
                 goto err;
@@ -311,20 +316,34 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
         if (ret < 0)
                 goto err;
 
-        ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
+        ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
                                 "fsl-lbc", fsl_lbc_ctrl_dev);
         if (ret != 0) {
                 dev_err(&dev->dev, "failed to install irq (%d)\n",
-                        fsl_lbc_ctrl_dev->irq);
-                ret = fsl_lbc_ctrl_dev->irq;
+                        fsl_lbc_ctrl_dev->irq[0]);
+                ret = fsl_lbc_ctrl_dev->irq[0];
                 goto err;
         }
 
+        fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
+        if (fsl_lbc_ctrl_dev->irq[1]) {
+                ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
+                                IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
+                if (ret) {
+                        dev_err(&dev->dev, "failed to install irq (%d)\n",
+                                        fsl_lbc_ctrl_dev->irq[1]);
+                        ret = fsl_lbc_ctrl_dev->irq[1];
+                        goto err1;
+                }
+        }
+
         /* Enable interrupts for any detected events */
         out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
 
         return 0;
 
+err1:
+        free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
 err:
         iounmap(fsl_lbc_ctrl_dev->regs);
         kfree(fsl_lbc_ctrl_dev);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61df8aba..a625dcf26b2b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -122,7 +122,7 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
          * address width of the SoC such that we can address any internal
          * SoC address from across PCI if needed
          */
-        if ((dev->bus == &pci_bus_type) &&
+        if ((dev_is_pci(dev)) &&
             dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
                 set_dma_ops(dev, &dma_direct_ops);
                 set_dma_offset(dev, pci64_dma_offset);
@@ -454,7 +454,7 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
         }
 }
 
-int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
+int fsl_add_bridge(struct platform_device *pdev, int is_primary)
 {
         int len;
         struct pci_controller *hose;
@@ -1035,6 +1035,7 @@ static const struct of_device_id pci_ids[] = {
         { .compatible = "fsl,mpc8548-pcie", },
         { .compatible = "fsl,mpc8610-pci", },
         { .compatible = "fsl,mpc8641-pcie", },
+        { .compatible = "fsl,qoriq-pcie", },
         { .compatible = "fsl,qoriq-pcie-v2.1", },
         { .compatible = "fsl,qoriq-pcie-v2.2", },
         { .compatible = "fsl,qoriq-pcie-v2.3", },
diff --git a/arch/powerpc/sysdev/ge/ge_pic.h b/arch/powerpc/sysdev/ge/ge_pic.h
index 6149916da3f4..908dbd9826b6 100644
--- a/arch/powerpc/sysdev/ge/ge_pic.h
+++ b/arch/powerpc/sysdev/ge/ge_pic.h
@@ -1,7 +1,6 @@
 #ifndef __GEF_PIC_H__
 #define __GEF_PIC_H__
 
-#include <linux/init.h>
 
 void gef_pic_cascade(unsigned int, struct irq_desc *);
 unsigned int gef_pic_get_irq(void);
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index 997df6a7ab5d..45598da0b321 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -8,7 +8,6 @@
  */
 #undef DEBUG
 
-#include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index c6c8b526a4f6..1f6c570d66d4 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -152,10 +152,8 @@ static struct pci_ops indirect_pci_ops =
         .write = indirect_write_config,
 };
 
-void __init
-setup_indirect_pci(struct pci_controller* hose,
-                   resource_size_t cfg_addr,
-                   resource_size_t cfg_data, u32 flags)
+void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
+                        resource_size_t cfg_data, u32 flags)
 {
         resource_size_t base = cfg_addr & PAGE_MASK;
         void __iomem *mbase;
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index b724622c3a0b..c4828c0be5bd 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -1,6 +1,5 @@
 #include <linux/kernel.h>
 #include <linux/stddef.h>
-#include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <linux/irq.h>
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 22d7d57eead9..9d9b06217f8b 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -41,6 +41,7 @@
 #define MPIC_TIMER_TCR_ROVR_OFFSET      24
 
 #define TIMER_STOP                      0x80000000
+#define GTCCR_TOG                       0x80000000
 #define TIMERS_PER_GROUP                4
 #define MAX_TICKS                       (~0U >> 1)
 #define MAX_TICKS_CASCADE               (~0U)
@@ -96,8 +97,11 @@ static void convert_ticks_to_time(struct timer_group_priv *priv,
         time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq);
         tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
 
-        time->tv_usec = (__kernel_suseconds_t)
-                div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq);
+        time->tv_usec = 0;
+
+        if (tmp_sec <= ticks)
+                time->tv_usec = (__kernel_suseconds_t)
+                        div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq);
 
         return;
 }
@@ -327,11 +331,13 @@ void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time)
         casc_priv = priv->timer[handle->num].cascade_handle;
         if (casc_priv) {
                 tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
+                tmp_ticks &= ~GTCCR_TOG;
                 ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
                 tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
                 ticks += tmp_ticks;
         } else {
                 ticks = in_be32(&priv->regs[handle->num].gtccr);
+                ticks &= ~GTCCR_TOG;
         }
 
         convert_ticks_to_time(priv, ticks, time);
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index a3a8fad8537d..c2dba7db71ad 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -448,7 +448,7 @@ static int __init mv64x60_device_setup(void)
         int err;
 
         id = 0;
-        for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
+        for_each_compatible_node(np, NULL, "marvell,mv64360-mpsc") {
                 err = mv64x60_mpsc_device_setup(np, id++);
                 if (err)
                         printk(KERN_ERR "Failed to initialize MV64x60 "
diff --git a/arch/powerpc/sysdev/mv64x60_udbg.c b/arch/powerpc/sysdev/mv64x60_udbg.c
index 50a81387e9b1..3b8734b870e9 100644
--- a/arch/powerpc/sysdev/mv64x60_udbg.c
+++ b/arch/powerpc/sysdev/mv64x60_udbg.c
@@ -85,7 +85,7 @@ static void mv64x60_udbg_init(void)
         if (!stdout)
                 return;
 
-        for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
+        for_each_compatible_node(np, NULL, "marvell,mv64360-mpsc") {
                 if (np == stdout)
                         break;
         }
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index a88807b3dd57..d09994164daf 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -16,7 +16,6 @@
 
 #include <linux/stddef.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/ioport.h>
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index 134b07d29435..621575b7e84a 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -14,7 +14,6 @@
  * option) any later version.
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/stddef.h>
 #include <linux/spinlock.h>
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index cceb2e366738..65aaf15032ae 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -13,7 +13,6 @@
  * option) any later version.
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/stddef.h>
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index 1c062f48f1ac..befaf1123f7f 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -13,7 +13,6 @@
  * option) any later version.
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/stddef.h>
diff --git a/arch/powerpc/sysdev/udbg_memcons.c b/arch/powerpc/sysdev/udbg_memcons.c
index ce5a7b489e4b..9998c0de12d0 100644
--- a/arch/powerpc/sysdev/udbg_memcons.c
+++ b/arch/powerpc/sysdev/udbg_memcons.c
@@ -18,7 +18,6 @@
  *      2 of the License, or (at your option) any later version.
  */
 
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <asm/barrier.h>
 #include <asm/page.h>
diff --git a/arch/powerpc/sysdev/xics/icp-hv.c b/arch/powerpc/sysdev/xics/icp-hv.c
index df0fc5821469..c1917cf67c3d 100644
--- a/arch/powerpc/sysdev/xics/icp-hv.c
+++ b/arch/powerpc/sysdev/xics/icp-hv.c
@@ -12,7 +12,6 @@
 #include <linux/irq.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
-#include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/of.h>
 
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index af9d3469fb99..a90731b3d44a 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2051,6 +2051,10 @@ static void dump_one_paca(int cpu)
         DUMP(p, stab_addr, "lx");
 #endif
         DUMP(p, emergency_sp, "p");
+#ifdef CONFIG_PPC_BOOK3S_64
+        DUMP(p, mc_emergency_sp, "p");
+        DUMP(p, in_mce, "x");
+#endif
         DUMP(p, data_offset, "lx");
         DUMP(p, hw_cpu_id, "x");
         DUMP(p, cpu_start, "x");
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index e9f312532526..65a07750f4f9 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -334,10 +334,10 @@ config SMP
           a system with only one CPU, like most personal computers, say N. If
           you have a system with more than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           See also the SMP-HOWTO available at
@@ -596,7 +596,7 @@ config CRASH_DUMP
 config ZFCPDUMP
         def_bool n
         prompt "zfcpdump support"
-        depends on SMP
+        depends on 64BIT && SMP
         help
           Select this option if you want to build an zfcpdump enabled kernel.
           Refer to <file:Documentation/s390/zfcpdump.txt> for more details on this.
diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c
index bcca01c9989d..200f2a1b599d 100644
--- a/arch/s390/crypto/des_s390.c
+++ b/arch/s390/crypto/des_s390.c
@@ -237,9 +237,9 @@ static int des3_setkey(struct crypto_tfm *tfm, const u8 *key,
         struct s390_des_ctx *ctx = crypto_tfm_ctx(tfm);
         u32 *flags = &tfm->crt_flags;
 
-        if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) &&
-            memcmp(&key[DES_KEY_SIZE], &key[DES_KEY_SIZE * 2],
-                   DES_KEY_SIZE)) &&
+        if (!(crypto_memneq(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) &&
+            crypto_memneq(&key[DES_KEY_SIZE], &key[DES_KEY_SIZE * 2],
+                          DES_KEY_SIZE)) &&
             (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
                 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
                 return -EINVAL;
diff --git a/arch/s390/hypfs/Makefile b/arch/s390/hypfs/Makefile
index 2e671d5004ca..06f8d95a16cd 100644
--- a/arch/s390/hypfs/Makefile
+++ b/arch/s390/hypfs/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_S390_HYPFS_FS) += s390_hypfs.o
 
-s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o hypfs_dbfs.o
+s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o hypfs_dbfs.o hypfs_sprp.o
diff --git a/arch/s390/hypfs/hypfs.h b/arch/s390/hypfs/hypfs.h
index 79f2ac55253f..b34b5ab90a31 100644
--- a/arch/s390/hypfs/hypfs.h
+++ b/arch/s390/hypfs/hypfs.h
@@ -13,6 +13,7 @@
 #include <linux/debugfs.h>
 #include <linux/workqueue.h>
 #include <linux/kref.h>
+#include <asm/hypfs.h>
 
 #define REG_FILE_MODE    0440
 #define UPDATE_FILE_MODE 0220
@@ -36,6 +37,10 @@ extern int hypfs_vm_init(void);
 extern void hypfs_vm_exit(void);
 extern int hypfs_vm_create_files(struct dentry *root);
 
+/* Set Partition-Resource Parameter */
+int hypfs_sprp_init(void);
+void hypfs_sprp_exit(void);
+
 /* debugfs interface */
 struct hypfs_dbfs_file;
 
@@ -52,6 +57,8 @@ struct hypfs_dbfs_file {
         int             (*data_create)(void **data, void **data_free_ptr,
                                        size_t *size);
         void            (*data_free)(const void *buf_free_ptr);
+        long            (*unlocked_ioctl) (struct file *, unsigned int,
+                                           unsigned long);
 
         /* Private data for hypfs_dbfs.c */
         struct hypfs_dbfs_data  *data;
diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c
index 17ab8b7b53cc..2badf2bf9cd7 100644
--- a/arch/s390/hypfs/hypfs_dbfs.c
+++ b/arch/s390/hypfs/hypfs_dbfs.c
@@ -81,9 +81,25 @@ static ssize_t dbfs_read(struct file *file, char __user *buf,
         return rc;
 }
 
+static long dbfs_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+        struct hypfs_dbfs_file *df;
+        long rc;
+
+        df = file->f_path.dentry->d_inode->i_private;
+        mutex_lock(&df->lock);
+        if (df->unlocked_ioctl)
+                rc = df->unlocked_ioctl(file, cmd, arg);
+        else
+                rc = -ENOTTY;
+        mutex_unlock(&df->lock);
+        return rc;
+}
+
 static const struct file_operations dbfs_ops = {
         .read           = dbfs_read,
         .llseek         = no_llseek,
+        .unlocked_ioctl = dbfs_ioctl,
 };
 
 int hypfs_dbfs_create_file(struct hypfs_dbfs_file *df)
diff --git a/arch/s390/hypfs/hypfs_sprp.c b/arch/s390/hypfs/hypfs_sprp.c
new file mode 100644
index 000000000000..f043c3c7e73c
--- /dev/null
+++ b/arch/s390/hypfs/hypfs_sprp.c
@@ -0,0 +1,141 @@
+/*
+ *    Hypervisor filesystem for Linux on s390.
+ *    Set Partition-Resource Parameter interface.
+ *
+ *    Copyright IBM Corp. 2013
+ *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#include <linux/compat.h>
+#include <linux/errno.h>
+#include <linux/gfp.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <asm/compat.h>
+#include <asm/sclp.h>
+#include "hypfs.h"
+
+#define DIAG304_SET_WEIGHTS     0
+#define DIAG304_QUERY_PRP       1
+#define DIAG304_SET_CAPPING     2
+
+#define DIAG304_CMD_MAX         2
+
+static unsigned long hypfs_sprp_diag304(void *data, unsigned long cmd)
+{
+        register unsigned long _data asm("2") = (unsigned long) data;
+        register unsigned long _rc asm("3");
+        register unsigned long _cmd asm("4") = cmd;
+
+        asm volatile("diag %1,%2,0x304\n"
+                     : "=d" (_rc) : "d" (_data), "d" (_cmd) : "memory");
+
+        return _rc;
+}
+
+static void hypfs_sprp_free(const void *data)
+{
+        free_page((unsigned long) data);
+}
+
+static int hypfs_sprp_create(void **data_ptr, void **free_ptr, size_t *size)
+{
+        unsigned long rc;
+        void *data;
+
+        data = (void *) get_zeroed_page(GFP_KERNEL);
+        if (!data)
+                return -ENOMEM;
+        rc = hypfs_sprp_diag304(data, DIAG304_QUERY_PRP);
+        if (rc != 1) {
+                *data_ptr = *free_ptr = NULL;
+                *size = 0;
+                free_page((unsigned long) data);
+                return -EIO;
+        }
+        *data_ptr = *free_ptr = data;
+        *size = PAGE_SIZE;
+        return 0;
+}
+
+static int __hypfs_sprp_ioctl(void __user *user_area)
+{
+        struct hypfs_diag304 diag304;
+        unsigned long cmd;
+        void __user *udata;
+        void *data;
+        int rc;
+
+        if (copy_from_user(&diag304, user_area, sizeof(diag304)))
+                return -EFAULT;
+        if ((diag304.args[0] >> 8) != 0 || diag304.args[1] > DIAG304_CMD_MAX)
+                return -EINVAL;
+
+        data = (void *) get_zeroed_page(GFP_KERNEL | GFP_DMA);
+        if (!data)
+                return -ENOMEM;
+
+        udata = (void __user *)(unsigned long) diag304.data;
+        if (diag304.args[1] == DIAG304_SET_WEIGHTS ||
+            diag304.args[1] == DIAG304_SET_CAPPING)
+                if (copy_from_user(data, udata, PAGE_SIZE)) {
+                        rc = -EFAULT;
+                        goto out;
+                }
+
+        cmd = *(unsigned long *) &diag304.args[0];
+        diag304.rc = hypfs_sprp_diag304(data, cmd);
+
+        if (diag304.args[1] == DIAG304_QUERY_PRP)
+                if (copy_to_user(udata, data, PAGE_SIZE)) {
+                        rc = -EFAULT;
+                        goto out;
+                }
+
+        rc = copy_to_user(user_area, &diag304, sizeof(diag304)) ? -EFAULT : 0;
+out:
+        free_page((unsigned long) data);
+        return rc;
+}
+
+static long hypfs_sprp_ioctl(struct file *file, unsigned int cmd,
+                               unsigned long arg)
+{
+        void __user *argp;
+
+        if (!capable(CAP_SYS_ADMIN))
+                return -EACCES;
+        if (is_compat_task())
+                argp = compat_ptr(arg);
+        else
+                argp = (void __user *) arg;
+        switch (cmd) {
+        case HYPFS_DIAG304:
+                return __hypfs_sprp_ioctl(argp);
+        default: /* unknown ioctl number */
+                return -ENOTTY;
+        }
+        return 0;
+}
+
+static struct hypfs_dbfs_file hypfs_sprp_file = {
+        .name           = "diag_304",
+        .data_create    = hypfs_sprp_create,
+        .data_free      = hypfs_sprp_free,
+        .unlocked_ioctl = hypfs_sprp_ioctl,
+};
+
+int hypfs_sprp_init(void)
+{
+        if (!sclp_has_sprp())
+                return 0;
+        return hypfs_dbfs_create_file(&hypfs_sprp_file);
+}
+
+void hypfs_sprp_exit(void)
+{
+        if (!sclp_has_sprp())
+                return;
+        hypfs_dbfs_remove_file(&hypfs_sprp_file);
+}
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index ddfe09b45134..c952b981e4f2 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -478,10 +478,14 @@ static int __init hypfs_init(void)
                 rc = -ENODATA;
                 goto fail_hypfs_diag_exit;
         }
+        if (hypfs_sprp_init()) {
+                rc = -ENODATA;
+                goto fail_hypfs_vm_exit;
+        }
         s390_kobj = kobject_create_and_add("s390", hypervisor_kobj);
         if (!s390_kobj) {
                 rc = -ENOMEM;
-                goto fail_hypfs_vm_exit;
+                goto fail_hypfs_sprp_exit;
         }
         rc = register_filesystem(&hypfs_type);
         if (rc)
@@ -490,6 +494,8 @@ static int __init hypfs_init(void)
 
 fail_filesystem:
         kobject_put(s390_kobj);
+fail_hypfs_sprp_exit:
+        hypfs_sprp_exit();
 fail_hypfs_vm_exit:
         hypfs_vm_exit();
 fail_hypfs_diag_exit:
@@ -502,11 +508,12 @@ fail_dbfs_exit:
 
 static void __exit hypfs_exit(void)
 {
-        hypfs_diag_exit();
-        hypfs_vm_exit();
-        hypfs_dbfs_exit();
         unregister_filesystem(&hypfs_type);
         kobject_put(s390_kobj);
+        hypfs_sprp_exit();
+        hypfs_vm_exit();
+        hypfs_diag_exit();
+        hypfs_dbfs_exit();
 }
 
 module_init(hypfs_init)
diff --git a/arch/s390/include/asm/Kbuild b/arch/s390/include/asm/Kbuild
index 7a5288f3479a..8386a4a1f19a 100644
--- a/arch/s390/include/asm/Kbuild
+++ b/arch/s390/include/asm/Kbuild
@@ -3,3 +3,4 @@
 generic-y += clkdev.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h
index 0f636cbdf342..4236408070e5 100644
--- a/arch/s390/include/asm/cmpxchg.h
+++ b/arch/s390/include/asm/cmpxchg.h
@@ -185,11 +185,12 @@ static inline unsigned long long __cmpxchg64(void *ptr,
 {
         register_pair rp_old = {.pair = old};
         register_pair rp_new = {.pair = new};
+        unsigned long long *ullptr = ptr;
 
         asm volatile(
                 "       cds     %0,%2,%1"
-                : "+&d" (rp_old), "=Q" (ptr)
-                : "d" (rp_new), "Q" (ptr)
+                : "+d" (rp_old), "+Q" (*ullptr)
+                : "d" (rp_new)
                 : "memory", "cc");
         return rp_old.pair;
 }
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index d5bc3750616e..eef3dd3fd9a9 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -106,9 +106,22 @@ struct kvm_s390_sie_block {
         __u64   gbea;                   /* 0x0180 */
         __u8    reserved188[24];        /* 0x0188 */
         __u32   fac;                    /* 0x01a0 */
-        __u8    reserved1a4[92];        /* 0x01a4 */
+        __u8    reserved1a4[68];        /* 0x01a4 */
+        __u64   itdba;                  /* 0x01e8 */
+        __u8    reserved1f0[16];        /* 0x01f0 */
 } __attribute__((packed));
 
+struct kvm_s390_itdb {
+        __u8    data[256];
+} __packed;
+
+struct sie_page {
+        struct kvm_s390_sie_block sie_block;
+        __u8 reserved200[1024];         /* 0x0200 */
+        struct kvm_s390_itdb itdb;      /* 0x0600 */
+        __u8 reserved700[2304];         /* 0x0700 */
+} __packed;
+
 struct kvm_vcpu_stat {
         u32 exit_userspace;
         u32 exit_null;
diff --git a/arch/s390/include/asm/sclp.h b/arch/s390/include/asm/sclp.h
index 220e171413f8..abaca2275c7a 100644
--- a/arch/s390/include/asm/sclp.h
+++ b/arch/s390/include/asm/sclp.h
@@ -54,6 +54,7 @@ int sclp_chp_read_info(struct sclp_chp_info *info);
 void sclp_get_ipl_info(struct sclp_ipl_info *info);
 bool __init sclp_has_linemode(void);
 bool __init sclp_has_vt220(void);
+bool sclp_has_sprp(void);
 int sclp_pci_configure(u32 fid);
 int sclp_pci_deconfigure(u32 fid);
 int memcpy_hsa(void *dest, unsigned long src, size_t count, int mode);
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
index 5a87d16d3e7c..d091aa1aaf11 100644
--- a/arch/s390/include/asm/sigp.h
+++ b/arch/s390/include/asm/sigp.h
@@ -5,6 +5,7 @@
 #define SIGP_SENSE                    1
 #define SIGP_EXTERNAL_CALL            2
 #define SIGP_EMERGENCY_SIGNAL         3
+#define SIGP_START                    4
 #define SIGP_STOP                     5
 #define SIGP_RESTART                  6
 #define SIGP_STOP_AND_STORE_STATUS    9
@@ -12,6 +13,7 @@
 #define SIGP_SET_PREFIX              13
 #define SIGP_STORE_STATUS_AT_ADDRESS 14
 #define SIGP_SET_ARCHITECTURE        18
+#define SIGP_COND_EMERGENCY_SIGNAL   19
 #define SIGP_SENSE_RUNNING           21
 
 /* SIGP condition codes */
diff --git a/arch/s390/include/uapi/asm/hypfs.h b/arch/s390/include/uapi/asm/hypfs.h
new file mode 100644
index 000000000000..37998b449531
--- /dev/null
+++ b/arch/s390/include/uapi/asm/hypfs.h
@@ -0,0 +1,25 @@
+/*
+ * IOCTL interface for hypfs
+ *
+ * Copyright IBM Corp. 2013
+ *
+ * Author: Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#ifndef _ASM_HYPFS_CTL_H
+#define _ASM_HYPFS_CTL_H
+
+#include <linux/types.h>
+
+struct hypfs_diag304 {
+        __u32   args[2];
+        __u64   data;
+        __u64   rc;
+} __attribute__((packed));
+
+#define HYPFS_IOCTL_MAGIC 0x10
+
+#define HYPFS_DIAG304 \
+        _IOWR(HYPFS_IOCTL_MAGIC, 0x20, struct hypfs_diag304)
+
+#endif
diff --git a/arch/s390/include/uapi/asm/socket.h b/arch/s390/include/uapi/asm/socket.h
index c286c2e868f0..e031332096d7 100644
--- a/arch/s390/include/uapi/asm/socket.h
+++ b/arch/s390/include/uapi/asm/socket.h
@@ -84,4 +84,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/s390/include/uapi/asm/statfs.h b/arch/s390/include/uapi/asm/statfs.h
index a61d538756f2..471eb09184d4 100644
--- a/arch/s390/include/uapi/asm/statfs.h
+++ b/arch/s390/include/uapi/asm/statfs.h
@@ -35,11 +35,11 @@ struct statfs {
 struct statfs64 {
         unsigned int    f_type;
         unsigned int    f_bsize;
-        unsigned long   f_blocks;
-        unsigned long   f_bfree;
-        unsigned long   f_bavail;
-        unsigned long   f_files;
-        unsigned long   f_ffree;
+        unsigned long long f_blocks;
+        unsigned long long f_bfree;
+        unsigned long long f_bavail;
+        unsigned long long f_files;
+        unsigned long long f_ffree;
         __kernel_fsid_t f_fsid;
         unsigned int    f_namelen;
         unsigned int    f_frsize;
diff --git a/arch/s390/include/uapi/asm/unistd.h b/arch/s390/include/uapi/asm/unistd.h
index 864f693c237f..5eb5c9ddb120 100644
--- a/arch/s390/include/uapi/asm/unistd.h
+++ b/arch/s390/include/uapi/asm/unistd.h
@@ -280,6 +280,8 @@
 #define __NR_s390_runtime_instr 342
 #define __NR_kcmp               343
 #define __NR_finit_module       344
+#define __NR_sched_setattr      345
+#define __NR_sched_getattr      346
 #define NR_syscalls 345
 
 /* 
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index e030d2bdec1b..db02052bd137 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -286,8 +286,8 @@ asmlinkage long sys32_getegid16(void)
 }
 
 #ifdef CONFIG_SYSVIPC
-COMPAT_SYSCALL_DEFINE5(s390_ipc, uint, call, int, first, unsigned long, second,
-                unsigned long, third, compat_uptr_t, ptr)
+COMPAT_SYSCALL_DEFINE5(s390_ipc, uint, call, int, first, compat_ulong_t, second,
+                compat_ulong_t, third, compat_uptr_t, ptr)
 {
         if (call >> 16)         /* hack for backward compatibility */
                 return -EINVAL;
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 9cb1b975b353..59c8efce1b99 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1412,3 +1412,14 @@ ENTRY(sys_finit_module_wrapper)
         llgtr   %r3,%r3                 # const char __user *
         lgfr    %r4,%r4                 # int
         jg      sys_finit_module
+
+ENTRY(sys_sched_setattr_wrapper)
+        lgfr    %r2,%r2                 # pid_t
+        llgtr   %r3,%r3                 # struct sched_attr __user *
+        jg      sys_sched_setattr
+
+ENTRY(sys_sched_getattr_wrapper)
+        lgfr    %r2,%r2                 # pid_t
+        llgtr   %r3,%r3                 # const char __user *
+        llgfr   %r3,%r3                 # unsigned int
+        jg      sys_sched_getattr
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index 913410bd74a3..143992152ec9 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -353,3 +353,5 @@ SYSCALL(sys_process_vm_writev,sys_process_vm_writev,compat_sys_process_vm_writev
 SYSCALL(sys_ni_syscall,sys_s390_runtime_instr,sys_s390_runtime_instr_wrapper)
 SYSCALL(sys_kcmp,sys_kcmp,sys_kcmp_wrapper)
 SYSCALL(sys_finit_module,sys_finit_module,sys_finit_module_wrapper)
+SYSCALL(sys_sched_setattr,sys_sched_setattr,sys_sched_setattr_wrapper) /* 345 */
+SYSCALL(sys_sched_getattr,sys_sched_getattr,sys_sched_getattr_wrapper)
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 78d967f180f4..8216c0e0b2e2 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -121,7 +121,7 @@ static int __diag_virtio_hypercall(struct kvm_vcpu *vcpu)
          * - gpr 4 contains the index on the bus (optionally)
          */
         ret = kvm_io_bus_write_cookie(vcpu->kvm, KVM_VIRTIO_CCW_NOTIFY_BUS,
-                                      vcpu->run->s.regs.gprs[2],
+                                      vcpu->run->s.regs.gprs[2] & 0xffffffff,
                                       8, &vcpu->run->s.regs.gprs[3],
                                       vcpu->run->s.regs.gprs[4]);
 
@@ -137,7 +137,7 @@ static int __diag_virtio_hypercall(struct kvm_vcpu *vcpu)
 
 int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
 {
-        int code = (vcpu->arch.sie_block->ipb & 0xfff0000) >> 16;
+        int code = kvm_s390_get_base_disp_rs(vcpu) & 0xffff;
 
         if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
                 return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 5ddbbde6f65c..eeb1ac7d8fa4 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -112,6 +112,17 @@ static int handle_instruction(struct kvm_vcpu *vcpu)
 static int handle_prog(struct kvm_vcpu *vcpu)
 {
         vcpu->stat.exit_program_interruption++;
+
+        /* Restore ITDB to Program-Interruption TDB in guest memory */
+        if (IS_TE_ENABLED(vcpu) &&
+            !(current->thread.per_flags & PER_FLAG_NO_TE) &&
+            IS_ITDB_VALID(vcpu)) {
+                copy_to_guest(vcpu, TDB_ADDR, vcpu->arch.sie_block->itdba,
+                              sizeof(struct kvm_s390_itdb));
+                memset((void *) vcpu->arch.sie_block->itdba, 0,
+                       sizeof(struct kvm_s390_itdb));
+        }
+
         trace_kvm_s390_intercept_prog(vcpu, vcpu->arch.sie_block->iprcc);
         return kvm_s390_inject_program_int(vcpu, vcpu->arch.sie_block->iprcc);
 }
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 569494e01ec6..e0676f390d57 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -395,6 +395,9 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
                                                     CPUSTAT_STOPPED |
                                                     CPUSTAT_GED);
         vcpu->arch.sie_block->ecb   = 6;
+        if (test_vfacility(50) && test_vfacility(73))
+                vcpu->arch.sie_block->ecb |= 0x10;
+
         vcpu->arch.sie_block->ecb2  = 8;
         vcpu->arch.sie_block->eca   = 0xC1002001U;
         vcpu->arch.sie_block->fac   = (int) (long) vfacilities;
@@ -411,6 +414,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
                                       unsigned int id)
 {
         struct kvm_vcpu *vcpu;
+        struct sie_page *sie_page;
         int rc = -EINVAL;
 
         if (id >= KVM_MAX_VCPUS)
@@ -422,12 +426,13 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
         if (!vcpu)
                 goto out;
 
-        vcpu->arch.sie_block = (struct kvm_s390_sie_block *)
-                                        get_zeroed_page(GFP_KERNEL);
-
-        if (!vcpu->arch.sie_block)
+        sie_page = (struct sie_page *) get_zeroed_page(GFP_KERNEL);
+        if (!sie_page)
                 goto out_free_cpu;
 
+        vcpu->arch.sie_block = &sie_page->sie_block;
+        vcpu->arch.sie_block->itdba = (unsigned long) &sie_page->itdb;
+
         vcpu->arch.sie_block->icpua = id;
         if (!kvm_is_ucontrol(kvm)) {
                 if (!kvm->arch.sca) {
@@ -732,14 +737,16 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason)
 
         if (exit_reason >= 0) {
                 rc = 0;
+        } else if (kvm_is_ucontrol(vcpu->kvm)) {
+                vcpu->run->exit_reason = KVM_EXIT_S390_UCONTROL;
+                vcpu->run->s390_ucontrol.trans_exc_code =
+                                                current->thread.gmap_addr;
+                vcpu->run->s390_ucontrol.pgm_code = 0x10;
+                rc = -EREMOTE;
         } else {
-                if (kvm_is_ucontrol(vcpu->kvm)) {
-                        rc = SIE_INTERCEPT_UCONTROL;
-                } else {
-                        VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
-                        trace_kvm_s390_sie_fault(vcpu);
-                        rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                }
+                VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
+                trace_kvm_s390_sie_fault(vcpu);
+                rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
         }
 
         memcpy(&vcpu->run->s.regs.gprs[14], &vcpu->arch.sie_block->gg14, 16);
@@ -833,16 +840,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                 rc = -EINTR;
         }
 
-#ifdef CONFIG_KVM_S390_UCONTROL
-        if (rc == SIE_INTERCEPT_UCONTROL) {
-                kvm_run->exit_reason = KVM_EXIT_S390_UCONTROL;
-                kvm_run->s390_ucontrol.trans_exc_code =
-                        current->thread.gmap_addr;
-                kvm_run->s390_ucontrol.pgm_code = 0x10;
-                rc = 0;
-        }
-#endif
-
         if (rc == -EOPNOTSUPP) {
                 /* intercept cannot be handled in-kernel, prepare kvm-run */
                 kvm_run->exit_reason         = KVM_EXIT_S390_SIEIC;
@@ -885,10 +882,11 @@ static int __guestcopy(struct kvm_vcpu *vcpu, u64 guestdest, void *from,
  * KVM_S390_STORE_STATUS_NOADDR: -> 0x1200 on 64 bit
  * KVM_S390_STORE_STATUS_PREFIXED: -> prefix
  */
-int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
+int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr)
 {
         unsigned char archmode = 1;
         int prefix;
+        u64 clkcomp;
 
         if (addr == KVM_S390_STORE_STATUS_NOADDR) {
                 if (copy_to_guest_absolute(vcpu, 163ul, &archmode, 1))
@@ -903,15 +901,6 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
         } else
                 prefix = 0;
 
-        /*
-         * The guest FPRS and ACRS are in the host FPRS/ACRS due to the lazy
-         * copying in vcpu load/put. Lets update our copies before we save
-         * it into the save area
-         */
-        save_fp_ctl(&vcpu->arch.guest_fpregs.fpc);
-        save_fp_regs(vcpu->arch.guest_fpregs.fprs);
-        save_access_regs(vcpu->run->s.regs.acrs);
-
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, fp_regs),
                         vcpu->arch.guest_fpregs.fprs, 128, prefix))
                 return -EFAULT;
@@ -941,8 +930,9 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
                         &vcpu->arch.sie_block->cputm, 8, prefix))
                 return -EFAULT;
 
+        clkcomp = vcpu->arch.sie_block->ckc >> 8;
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, clk_cmp),
-                        &vcpu->arch.sie_block->ckc, 8, prefix))
+                        &clkcomp, 8, prefix))
                 return -EFAULT;
 
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, acc_regs),
@@ -956,6 +946,20 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
         return 0;
 }
 
+int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        /*
+         * The guest FPRS and ACRS are in the host FPRS/ACRS due to the lazy
+         * copying in vcpu load/put. Lets update our copies before we save
+         * it into the save area
+         */
+        save_fp_ctl(&vcpu->arch.guest_fpregs.fpc);
+        save_fp_regs(vcpu->arch.guest_fpregs.fprs);
+        save_access_regs(vcpu->run->s.regs.acrs);
+
+        return kvm_s390_store_status_unloaded(vcpu, addr);
+}
+
 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
                                      struct kvm_enable_cap *cap)
 {
@@ -1183,8 +1187,8 @@ static int __init kvm_s390_init(void)
                 return -ENOMEM;
         }
         memcpy(vfacilities, S390_lowcore.stfle_fac_list, 16);
-        vfacilities[0] &= 0xff82fff3f47c0000UL;
-        vfacilities[1] &= 0x001c000000000000UL;
+        vfacilities[0] &= 0xff82fff3f4fc2000UL;
+        vfacilities[1] &= 0x005c000000000000UL;
         return 0;
 }
 
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index b44912a32949..f9559b0bd620 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -19,18 +19,19 @@
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
 
-/* The current code can have up to 256 pages for virtio */
-#define VIRTIODESCSPACE (256ul * 4096ul)
-
 typedef int (*intercept_handler_t)(struct kvm_vcpu *vcpu);
 
 /* declare vfacilities extern */
 extern unsigned long *vfacilities;
 
-/* negativ values are error codes, positive values for internal conditions */
-#define SIE_INTERCEPT_UCONTROL          (1<<0)
 int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu);
 
+/* Transactional Memory Execution related macros */
+#define IS_TE_ENABLED(vcpu)     ((vcpu->arch.sie_block->ecb & 0x10))
+#define TDB_ADDR                0x1800UL
+#define TDB_FORMAT1             1
+#define IS_ITDB_VALID(vcpu)     ((*(char *)vcpu->arch.sie_block->itdba == TDB_FORMAT1))
+
 #define VM_EVENT(d_kvm, d_loglevel, d_string, d_args...)\
 do { \
         debug_sprintf_event(d_kvm->arch.dbf, d_loglevel, d_string "\n", \
@@ -133,7 +134,6 @@ int __must_check kvm_s390_inject_vm(struct kvm *kvm,
 int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
                                       struct kvm_s390_interrupt *s390int);
 int __must_check kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
-int __must_check kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action);
 struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm,
                                                     u64 cr6, u64 schid);
 
@@ -150,8 +150,8 @@ int kvm_s390_handle_eb(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu);
 
 /* implemented in kvm-s390.c */
-int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu,
-                                 unsigned long addr);
+int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);
+int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr);
 void s390_vcpu_block(struct kvm_vcpu *vcpu);
 void s390_vcpu_unblock(struct kvm_vcpu *vcpu);
 void exit_sie(struct kvm_vcpu *vcpu);
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index d101dae62771..75beea632a10 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -197,7 +197,7 @@ static int handle_tpi(struct kvm_vcpu *vcpu)
         if (addr & 3)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
         cc = 0;
-        inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->run->s.regs.crs[6], 0);
+        inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->arch.sie_block->gcr[6], 0);
         if (!inti)
                 goto no_interrupt;
         cc = 1;
@@ -638,7 +638,6 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
 
 static const intercept_handler_t b9_handlers[256] = {
         [0x8d] = handle_epsw,
-        [0x9c] = handle_io_inst,
         [0xaf] = handle_pfmf,
 };
 
@@ -731,7 +730,6 @@ static int handle_lctlg(struct kvm_vcpu *vcpu)
 
 static const intercept_handler_t eb_handlers[256] = {
         [0x2f] = handle_lctlg,
-        [0x8a] = handle_io_inst,
 };
 
 int kvm_s390_handle_eb(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index bec398c57acf..87c2b3a3bd3e 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -1,7 +1,7 @@
 /*
  * handling interprocessor communication
  *
- * Copyright IBM Corp. 2008, 2009
+ * Copyright IBM Corp. 2008, 2013
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
@@ -89,6 +89,37 @@ unlock:
         return rc;
 }
 
+static int __sigp_conditional_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr,
+                                        u16 asn, u64 *reg)
+{
+        struct kvm_vcpu *dst_vcpu = NULL;
+        const u64 psw_int_mask = PSW_MASK_IO | PSW_MASK_EXT;
+        u16 p_asn, s_asn;
+        psw_t *psw;
+        u32 flags;
+
+        if (cpu_addr < KVM_MAX_VCPUS)
+                dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
+        if (!dst_vcpu)
+                return SIGP_CC_NOT_OPERATIONAL;
+        flags = atomic_read(&dst_vcpu->arch.sie_block->cpuflags);
+        psw = &dst_vcpu->arch.sie_block->gpsw;
+        p_asn = dst_vcpu->arch.sie_block->gcr[4] & 0xffff;  /* Primary ASN */
+        s_asn = dst_vcpu->arch.sie_block->gcr[3] & 0xffff;  /* Secondary ASN */
+
+        /* Deliver the emergency signal? */
+        if (!(flags & CPUSTAT_STOPPED)
+            || (psw->mask & psw_int_mask) != psw_int_mask
+            || ((flags & CPUSTAT_WAIT) && psw->addr != 0)
+            || (!(flags & CPUSTAT_WAIT) && (asn == p_asn || asn == s_asn))) {
+                return __sigp_emergency(vcpu, cpu_addr);
+        } else {
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INCORRECT_STATE;
+                return SIGP_CC_STATUS_STORED;
+        }
+}
+
 static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
@@ -130,6 +161,7 @@ unlock:
 static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
 {
         struct kvm_s390_interrupt_info *inti;
+        int rc = SIGP_CC_ORDER_CODE_ACCEPTED;
 
         inti = kzalloc(sizeof(*inti), GFP_ATOMIC);
         if (!inti)
@@ -139,6 +171,8 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
         spin_lock_bh(&li->lock);
         if ((atomic_read(li->cpuflags) & CPUSTAT_STOPPED)) {
                 kfree(inti);
+                if ((action & ACTION_STORE_ON_STOP) != 0)
+                        rc = -ESHUTDOWN;
                 goto out;
         }
         list_add_tail(&inti->list, &li->list);
@@ -150,7 +184,7 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
 out:
         spin_unlock_bh(&li->lock);
 
-        return SIGP_CC_ORDER_CODE_ACCEPTED;
+        return rc;
 }
 
 static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
@@ -174,13 +208,17 @@ static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
 unlock:
         spin_unlock(&fi->lock);
         VCPU_EVENT(vcpu, 4, "sent sigp stop to cpu %x", cpu_addr);
-        return rc;
-}
 
-int kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action)
-{
-        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
-        return __inject_sigp_stop(li, action);
+        if ((action & ACTION_STORE_ON_STOP) != 0 && rc == -ESHUTDOWN) {
+                /* If the CPU has already been stopped, we still have
+                 * to save the status when doing stop-and-store. This
+                 * has to be done after unlocking all spinlocks. */
+                struct kvm_vcpu *dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
+                rc = kvm_s390_store_status_unloaded(dst_vcpu,
+                                                KVM_S390_STORE_STATUS_NOADDR);
+        }
+
+        return rc;
 }
 
 static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
@@ -262,6 +300,37 @@ out_fi:
         return rc;
 }
 
+static int __sigp_store_status_at_addr(struct kvm_vcpu *vcpu, u16 cpu_id,
+                                        u32 addr, u64 *reg)
+{
+        struct kvm_vcpu *dst_vcpu = NULL;
+        int flags;
+        int rc;
+
+        if (cpu_id < KVM_MAX_VCPUS)
+                dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_id);
+        if (!dst_vcpu)
+                return SIGP_CC_NOT_OPERATIONAL;
+
+        spin_lock_bh(&dst_vcpu->arch.local_int.lock);
+        flags = atomic_read(dst_vcpu->arch.local_int.cpuflags);
+        spin_unlock_bh(&dst_vcpu->arch.local_int.lock);
+        if (!(flags & CPUSTAT_STOPPED)) {
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INCORRECT_STATE;
+                return SIGP_CC_STATUS_STORED;
+        }
+
+        addr &= 0x7ffffe00;
+        rc = kvm_s390_store_status_unloaded(dst_vcpu, addr);
+        if (rc == -EFAULT) {
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INVALID_PARAMETER;
+                rc = SIGP_CC_STATUS_STORED;
+        }
+        return rc;
+}
+
 static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
                                 u64 *reg)
 {
@@ -294,7 +363,8 @@ static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
         return rc;
 }
 
-static int __sigp_restart(struct kvm_vcpu *vcpu, u16 cpu_addr)
+/* Test whether the destination CPU is available and not busy */
+static int sigp_check_callable(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
         struct kvm_s390_local_interrupt *li;
@@ -313,9 +383,6 @@ static int __sigp_restart(struct kvm_vcpu *vcpu, u16 cpu_addr)
         spin_lock_bh(&li->lock);
         if (li->action_bits & ACTION_STOP_ON_STOP)
                 rc = SIGP_CC_BUSY;
-        else
-                VCPU_EVENT(vcpu, 4, "sigp restart %x to handle userspace",
-                        cpu_addr);
         spin_unlock_bh(&li->lock);
 out:
         spin_unlock(&fi->lock);
@@ -366,6 +433,10 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 rc = __sigp_stop(vcpu, cpu_addr, ACTION_STORE_ON_STOP |
                                                  ACTION_STOP_ON_STOP);
                 break;
+        case SIGP_STORE_STATUS_AT_ADDRESS:
+                rc = __sigp_store_status_at_addr(vcpu, cpu_addr, parameter,
+                                                 &vcpu->run->s.regs.gprs[r1]);
+                break;
         case SIGP_SET_ARCHITECTURE:
                 vcpu->stat.instruction_sigp_arch++;
                 rc = __sigp_set_arch(vcpu, parameter);
@@ -375,17 +446,31 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 rc = __sigp_set_prefix(vcpu, cpu_addr, parameter,
                                        &vcpu->run->s.regs.gprs[r1]);
                 break;
+        case SIGP_COND_EMERGENCY_SIGNAL:
+                rc = __sigp_conditional_emergency(vcpu, cpu_addr, parameter,
+                                                  &vcpu->run->s.regs.gprs[r1]);
+                break;
         case SIGP_SENSE_RUNNING:
                 vcpu->stat.instruction_sigp_sense_running++;
                 rc = __sigp_sense_running(vcpu, cpu_addr,
                                           &vcpu->run->s.regs.gprs[r1]);
                 break;
+        case SIGP_START:
+                rc = sigp_check_callable(vcpu, cpu_addr);
+                if (rc == SIGP_CC_ORDER_CODE_ACCEPTED)
+                        rc = -EOPNOTSUPP;    /* Handle START in user space */
+                break;
         case SIGP_RESTART:
                 vcpu->stat.instruction_sigp_restart++;
-                rc = __sigp_restart(vcpu, cpu_addr);
-                if (rc == SIGP_CC_BUSY)
-                        break;
-                /* user space must know about restart */
+                rc = sigp_check_callable(vcpu, cpu_addr);
+                if (rc == SIGP_CC_ORDER_CODE_ACCEPTED) {
+                        VCPU_EVENT(vcpu, 4,
+                                   "sigp restart %x to handle userspace",
+                                   cpu_addr);
+                        /* user space must know about restart */
+                        rc = -EOPNOTSUPP;
+                }
+                break;
         default:
                 return -EOPNOTSUPP;
         }
@@ -393,7 +478,6 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
         if (rc < 0)
                 return rc;
 
-        vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
-        vcpu->arch.sie_block->gpsw.mask |= (rc & 3ul) << 44;
+        kvm_s390_set_psw_cc(vcpu, rc);
         return 0;
 }
diff --git a/arch/s390/kvm/trace.h b/arch/s390/kvm/trace.h
index 0c991c6748ab..3db76b2daed7 100644
--- a/arch/s390/kvm/trace.h
+++ b/arch/s390/kvm/trace.h
@@ -175,6 +175,7 @@ TRACE_EVENT(kvm_s390_intercept_validity,
         {SIGP_STOP_AND_STORE_STATUS, "stop and store status"},  \
         {SIGP_SET_ARCHITECTURE, "set architecture"},            \
         {SIGP_SET_PREFIX, "set prefix"},                        \
+        {SIGP_STORE_STATUS_AT_ADDRESS, "store status at addr"}, \
         {SIGP_SENSE_RUNNING, "sense running"},                  \
         {SIGP_RESTART, "restart"}
 
diff --git a/arch/s390/lib/uaccess.h b/arch/s390/lib/uaccess.h
index 315dbe09983e..b1a22173d027 100644
--- a/arch/s390/lib/uaccess.h
+++ b/arch/s390/lib/uaccess.h
@@ -6,15 +6,6 @@
 #ifndef __ARCH_S390_LIB_UACCESS_H
 #define __ARCH_S390_LIB_UACCESS_H
 
-extern size_t copy_from_user_std(size_t, const void __user *, void *);
-extern size_t copy_to_user_std(size_t, void __user *, const void *);
-extern size_t strnlen_user_std(size_t, const char __user *);
-extern size_t strncpy_from_user_std(size_t, const char __user *, char *);
-extern int futex_atomic_cmpxchg_std(u32 *, u32 __user *, u32, u32);
-extern int futex_atomic_op_std(int, u32 __user *, int, int *);
-
-extern size_t copy_from_user_pt(size_t, const void __user *, void *);
-extern size_t copy_to_user_pt(size_t, void __user *, const void *);
 extern int futex_atomic_op_pt(int, u32 __user *, int, int *);
 extern int futex_atomic_cmpxchg_pt(u32 *, u32 __user *, u32, u32);
 
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 0632dc50da78..61ebcc9ccb34 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -153,6 +153,8 @@ static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr,
         unsigned long offset, done, size, kaddr;
         void *from, *to;
 
+        if (!mm)
+                return n;
         done = 0;
 retry:
         spin_lock(&mm->page_table_lock);
@@ -209,7 +211,7 @@ fault:
         return 0;
 }
 
-size_t copy_from_user_pt(size_t n, const void __user *from, void *to)
+static size_t copy_from_user_pt(size_t n, const void __user *from, void *to)
 {
         size_t rc;
 
@@ -221,7 +223,7 @@ size_t copy_from_user_pt(size_t n, const void __user *from, void *to)
         return rc;
 }
 
-size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
+static size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
 {
         if (segment_eq(get_fs(), KERNEL_DS))
                 return copy_in_kernel(n, to, (void __user *) from);
@@ -262,6 +264,8 @@ static size_t strnlen_user_pt(size_t count, const char __user *src)
                 return 0;
         if (segment_eq(get_fs(), KERNEL_DS))
                 return strnlen_kernel(count, src);
+        if (!mm)
+                return 0;
         done = 0;
 retry:
         spin_lock(&mm->page_table_lock);
@@ -323,6 +327,8 @@ static size_t copy_in_user_pt(size_t n, void __user *to,
 
         if (segment_eq(get_fs(), KERNEL_DS))
                 return copy_in_kernel(n, to, from);
+        if (!mm)
+                return n;
         done = 0;
 retry:
         spin_lock(&mm->page_table_lock);
@@ -411,6 +417,8 @@ int futex_atomic_op_pt(int op, u32 __user *uaddr, int oparg, int *old)
 
         if (segment_eq(get_fs(), KERNEL_DS))
                 return __futex_atomic_op_pt(op, uaddr, oparg, old);
+        if (unlikely(!current->mm))
+                return -EFAULT;
         spin_lock(&current->mm->page_table_lock);
         uaddr = (u32 __force __user *)
                 __dat_user_addr((__force unsigned long) uaddr, 1);
@@ -448,6 +456,8 @@ int futex_atomic_cmpxchg_pt(u32 *uval, u32 __user *uaddr,
 
         if (segment_eq(get_fs(), KERNEL_DS))
                 return __futex_atomic_cmpxchg_pt(uval, uaddr, oldval, newval);
+        if (unlikely(!current->mm))
+                return -EFAULT;
         spin_lock(&current->mm->page_table_lock);
         uaddr = (u32 __force __user *)
                 __dat_user_addr((__force unsigned long) uaddr, 1);
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index 0820362c7b0f..66670ff262a0 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -407,8 +407,8 @@ int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         struct msi_msg msg;
         int rc;
 
-        if (type != PCI_CAP_ID_MSIX && type != PCI_CAP_ID_MSI)
-                return -EINVAL;
+        if (type == PCI_CAP_ID_MSI && nvec > 1)
+                return 1;
         msi_vecs = min(nvec, ZPCI_MSI_VEC_MAX);
         msi_vecs = min_t(unsigned int, msi_vecs, CONFIG_PCI_NR_MSI);
 
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 305f7ee1f382..c75d06aa27c3 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -2,7 +2,6 @@ menu "Machine selection"
 
 config SCORE
        def_bool y
-       select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
        select GENERIC_IOMAP
        select GENERIC_ATOMIC64
diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild
index fe7471eb0167..146b9d5e89f8 100644
--- a/arch/score/include/asm/Kbuild
+++ b/arch/score/include/asm/Kbuild
@@ -3,6 +3,8 @@ header-y +=
 
 generic-y += barrier.h
 generic-y += clkdev.h
+generic-y += hash.h
 generic-y += trace_clock.h
 generic-y += xor.h
 generic-y += preempt.h
+
diff --git a/arch/score/lib/checksum.S b/arch/score/lib/checksum.S
index 706157edc7d5..1141f2b4a501 100644
--- a/arch/score/lib/checksum.S
+++ b/arch/score/lib/checksum.S
@@ -137,7 +137,7 @@ ENTRY(csum_partial)
         ldi r25, 0
         mv r10, r5
         cmpi.c  r5, 0x8
-        blt     small_csumcpy           /* < 8(singed) bytes to copy */
+        blt     small_csumcpy           /* < 8(signed) bytes to copy */
         cmpi.c  r5, 0x0
         beq     out
         andri.c r25, src, 0x1           /* odd buffer? */
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ce298317a73e..6357710753d5 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -701,13 +701,13 @@ config SMP
         depends on SYS_SUPPORTS_SMP
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           People using multiprocessor machines who say Y here should also say
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index fb5805745ace..eb1cf84231a2 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -321,6 +321,7 @@ config SH_CAYMAN
         bool "Hitachi Cayman"
         depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
         select SYS_SUPPORTS_PCI
+        select ARCH_MIGHT_HAVE_PC_SERIO
 
 config SH_POLARIS
         bool "SMSC Polaris"
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 122f737a901f..5bc3a15465c7 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -502,7 +502,7 @@ static struct platform_device keysc_device = {
 /* TouchScreen */
 #define IRQ0 evt2irq(0x600)
 
-static int ts_get_pendown_state(void)
+static int ts_get_pendown_state(struct device *dev)
 {
         int val = 0;
         gpio_free(GPIO_FN_INTC_IRQ0);
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index 231efbb68108..0cd7198a4524 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -35,3 +35,4 @@ generic-y += trace_clock.h
 generic-y += ucontext.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h
index 6ba91868201c..c41901465fb0 100644
--- a/arch/sh/include/asm/clkdev.h
+++ b/arch/sh/include/asm/clkdev.h
@@ -25,7 +25,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
                 return kzalloc(size, GFP_KERNEL);
 }
 
+#ifndef CONFIG_COMMON_CLK
 #define __clk_put(clk)
 #define __clk_get(clk) ({ 1; })
+#endif
 
 #endif /* __CLKDEV_H__ */
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index cbe0186b6794..4daf91c3b725 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -79,13 +79,6 @@ extern void __set_fixmap(enum fixed_addresses idx,
                          unsigned long phys, pgprot_t flags);
 extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
 
-#define set_fixmap(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
 /*
  * used by vmalloc.c.
  *
@@ -101,36 +94,8 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
 #define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
+#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NOCACHE
 
-        return __fix_to_virt(idx);
-}
+#include <asm-generic/fixmap.h>
 
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
 #endif
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 4df4d4ffe39b..3860b0be56c7 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
                          NULL, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xf8400000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(88),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xf8400000, 0x100),
+        DEFINE_RES_IRQ(88),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xf8410000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(92),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xf8410000, 0x100),
+        DEFINE_RES_IRQ(92),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xf8420000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(96),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xf8420000, 0x100),
+        DEFINE_RES_IRQ(96),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index f7f1cf2af302..63e996f9a7ed 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = {
 };
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xff804000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(220),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xff804000, 0x100),
+        DEFINE_RES_IRQ(220),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 7b84785b8962..2c6874461536 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(180),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfffe8000, 0x100),
+        DEFINE_RES_IRQ(180),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(184),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xfffe8800, 0x100),
+        DEFINE_RES_IRQ(184),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(188),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfffe9000, 0x100),
+        DEFINE_RES_IRQ(188),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(192),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfffe9800, 0x100),
+        DEFINE_RES_IRQ(192),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xfffea000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(196),
+};
+
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xfffea000, 0x100),
+        DEFINE_RES_IRQ(196),
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xfffea800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(200),
+};
+
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xfffea800, 0x100),
+        DEFINE_RES_IRQ(200),
 };
 
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
 };
 
 static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xfffeb000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(204),
+};
+
+static struct resource scif6_resources[] = {
+        DEFINE_RES_MEM(0xfffeb000, 0x100),
+        DEFINE_RES_IRQ(204),
 };
 
 static struct platform_device scif6_device = {
         .name           = "sh-sci",
         .id             = 6,
+        .resource       = scif6_resources,
+        .num_resources  = ARRAY_SIZE(scif6_resources),
         .dev            = {
                 .platform_data  = &scif6_platform_data,
         },
 };
 
 static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xfffeb800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(208),
+};
+
+static struct resource scif7_resources[] = {
+        DEFINE_RES_MEM(0xfffeb800, 0x100),
+        DEFINE_RES_IRQ(208),
 };
 
 static struct platform_device scif7_device = {
         .name           = "sh-sci",
         .id             = 7,
+        .resource       = scif7_resources,
+        .num_resources  = ARRAY_SIZE(scif7_resources),
         .dev            = {
                 .platform_data  = &scif7_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index bfc33f6a28c3..d55a0f30ada3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(192),
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfffe8000, 0x100),
+        DEFINE_RES_IRQ(192),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(196),
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xfffe8800, 0x100),
+        DEFINE_RES_IRQ(196),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(200),
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfffe9000, 0x100),
+        DEFINE_RES_IRQ(200),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(204),
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfffe9800, 0x100),
+        DEFINE_RES_IRQ(204),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a5010741de85..241e745e3ced 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(240),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfffe8000, 0x100),
+        DEFINE_RES_IRQ(240),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(244),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xfffe8800, 0x100),
+        DEFINE_RES_IRQ(244),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(248),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfffe9000, 0x100),
+        DEFINE_RES_IRQ(248),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(252),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfffe9800, 0x100),
+        DEFINE_RES_IRQ(252),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
index ce5c1b5aebfa..ad5b0f429882 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 233, 234, 235, 232 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfffe8000, 0x100),
+        DEFINE_RES_IRQ(233),
+        DEFINE_RES_IRQ(234),
+        DEFINE_RES_IRQ(235),
+        DEFINE_RES_IRQ(232),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 237, 238, 239, 236 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xfffe8800, 0x100),
+        DEFINE_RES_IRQ(237),
+        DEFINE_RES_IRQ(238),
+        DEFINE_RES_IRQ(239),
+        DEFINE_RES_IRQ(236),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 241, 242, 243, 240 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfffe9000, 0x100),
+        DEFINE_RES_IRQ(241),
+        DEFINE_RES_IRQ(242),
+        DEFINE_RES_IRQ(243),
+        DEFINE_RES_IRQ(240),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 245, 246, 247, 244 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfffe9800, 0x100),
+        DEFINE_RES_IRQ(245),
+        DEFINE_RES_IRQ(246),
+        DEFINE_RES_IRQ(247),
+        DEFINE_RES_IRQ(244),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xfffea000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 249, 250, 251, 248 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xfffea000, 0x100),
+        DEFINE_RES_IRQ(249),
+        DEFINE_RES_IRQ(250),
+        DEFINE_RES_IRQ(251),
+        DEFINE_RES_IRQ(248),
+};
+
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xfffea800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 253, 254, 255, 252 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xfffea800, 0x100),
+        DEFINE_RES_IRQ(253),
+        DEFINE_RES_IRQ(254),
+        DEFINE_RES_IRQ(255),
+        DEFINE_RES_IRQ(252),
+};
+
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
 };
 
 static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xfffeb000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 257, 258, 259, 256 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif6_resources[] = {
+        DEFINE_RES_MEM(0xfffeb000, 0x100),
+        DEFINE_RES_IRQ(257),
+        DEFINE_RES_IRQ(258),
+        DEFINE_RES_IRQ(259),
+        DEFINE_RES_IRQ(256),
+};
+
 static struct platform_device scif6_device = {
         .name           = "sh-sci",
         .id             = 6,
+        .resource       = scif6_resources,
+        .num_resources  = ARRAY_SIZE(scif6_resources),
         .dev            = {
                 .platform_data  = &scif6_platform_data,
         },
 };
 
 static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xfffeb800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 261, 262, 263, 260 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif7_resources[] = {
+        DEFINE_RES_MEM(0xfffeb800, 0x100),
+        DEFINE_RES_IRQ(261),
+        DEFINE_RES_IRQ(262),
+        DEFINE_RES_IRQ(263),
+        DEFINE_RES_IRQ(260),
+};
+
 static struct platform_device scif7_device = {
         .name           = "sh-sci",
         .id             = 7,
+        .resource       = scif7_resources,
+        .num_resources  = ARRAY_SIZE(scif7_resources),
         .dev            = {
                 .platform_data  = &scif7_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
index e82ae9d8d3bc..3995119f65dc 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
@@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xe8007000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 259, 260, 261, 258 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xe8007000, 0x100),
+        DEFINE_RES_IRQ(259),
+        DEFINE_RES_IRQ(260),
+        DEFINE_RES_IRQ(261),
+        DEFINE_RES_IRQ(258),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xe8007800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 263, 264, 265, 262 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xe8007800, 0x100),
+        DEFINE_RES_IRQ(263),
+        DEFINE_RES_IRQ(264),
+        DEFINE_RES_IRQ(265),
+        DEFINE_RES_IRQ(262),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xe8008000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 267, 268, 269, 266 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xe8008000, 0x100),
+        DEFINE_RES_IRQ(267),
+        DEFINE_RES_IRQ(268),
+        DEFINE_RES_IRQ(269),
+        DEFINE_RES_IRQ(266),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xe8008800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 271, 272, 273, 270 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xe8008800, 0x100),
+        DEFINE_RES_IRQ(271),
+        DEFINE_RES_IRQ(272),
+        DEFINE_RES_IRQ(273),
+        DEFINE_RES_IRQ(270),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xe8009000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 275, 276, 277, 274 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xe8009000, 0x100),
+        DEFINE_RES_IRQ(275),
+        DEFINE_RES_IRQ(276),
+        DEFINE_RES_IRQ(277),
+        DEFINE_RES_IRQ(274),
+};
+
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xe8009800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 279, 280, 281, 278 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xe8009800, 0x100),
+        DEFINE_RES_IRQ(279),
+        DEFINE_RES_IRQ(280),
+        DEFINE_RES_IRQ(281),
+        DEFINE_RES_IRQ(278),
+};
+
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
 };
 
 static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xe800a000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 283, 284, 285, 282 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif6_resources[] = {
+        DEFINE_RES_MEM(0xe800a000, 0x100),
+        DEFINE_RES_IRQ(283),
+        DEFINE_RES_IRQ(284),
+        DEFINE_RES_IRQ(285),
+        DEFINE_RES_IRQ(282),
+};
+
 static struct platform_device scif6_device = {
         .name           = "sh-sci",
         .id             = 6,
+        .resource       = scif6_resources,
+        .num_resources  = ARRAY_SIZE(scif6_resources),
         .dev            = {
                 .platform_data  = &scif6_platform_data,
         },
 };
 
 static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xe800a800,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
                           SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           =  { 287, 288, 289, 286 },
         .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif7_resources[] = {
+        DEFINE_RES_MEM(0xe800a800, 0x100),
+        DEFINE_RES_IRQ(287),
+        DEFINE_RES_IRQ(288),
+        DEFINE_RES_IRQ(289),
+        DEFINE_RES_IRQ(286),
+};
+
 static struct platform_device scif7_device = {
         .name           = "sh-sci",
         .id             = 7,
+        .resource       = scif7_resources,
+        .num_resources  = ARRAY_SIZE(scif7_resources),
         .dev            = {
                 .platform_data  = &scif7_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 03e4c96f2b11..c76b2543b85f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
                          NULL, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xa4410000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
                           SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
         .ops            = &sh770x_sci_port_ops,
         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xa4410000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xa4400000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
         .ops            = &sh770x_sci_port_ops,
         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xa4400000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index ba26cd9ce69b..ff1465c0519c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,20 +109,24 @@ static struct platform_device rtc_device = {
 };
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfffffe80,
         .port_reg       = 0xa4000136,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
         .ops            = &sh770x_sci_port_ops,
         .regshift       = 1,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfffffe80, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x4e0)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
@@ -131,19 +135,23 @@ static struct platform_device scif0_device = {
     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xa4000150,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
         .ops            = &sh770x_sci_port_ops,
         .regtype        = SCIx_SH3_SCIF_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xa4000150, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
@@ -152,20 +160,24 @@ static struct platform_device scif1_device = {
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xa4000140,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_IRDA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
         .ops            = &sh770x_sci_port_ops,
         .regshift       = 1,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xa4000140, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 93c9c5e24a7a..e2ce9360ed5a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -98,36 +98,44 @@ static struct platform_device rtc_device = {
 };
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xa4400000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
                           SCSCR_CKE1 | SCSCR_CKE0,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xa4400000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xa4410000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
                           SCSCR_CKE1 | SCSCR_CKE0,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xa4410000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 42d991f632b1..1d5729dc0724 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -52,38 +52,46 @@ static struct platform_device rtc_device = {
 };
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xa4430000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
         .ops            = &sh7720_sci_port_ops,
         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xa4430000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xa4438000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
         .ops            = &sh7720_sci_port_ops,
         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xa4438000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 2a5320aa73bb..a8bd778d5ac8 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -17,20 +17,24 @@
 #include <linux/io.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe80000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x700),
-                            evt2irq(0x720),
-                            evt2irq(0x760),
-                            evt2irq(0x740) },
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe80000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+        DEFINE_RES_IRQ(evt2irq(0x720)),
+        DEFINE_RES_IRQ(evt2irq(0x760)),
+        DEFINE_RES_IRQ(evt2irq(0x740)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 04a45512596f..a447a248491f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -38,36 +38,44 @@ static struct platform_device rtc_device = {
 };
 
 static struct plat_sci_port sci_platform_data = {
-        .mapbase        = 0xffe00000,
         .port_reg       = 0xffe0001C,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
         .regshift       = 2,
 };
 
+static struct resource sci_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x4e0)),
+};
+
 static struct platform_device sci_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = sci_resources,
+        .num_resources  = ARRAY_SIZE(sci_resources),
         .dev            = {
                 .platform_data  = &sci_platform_data,
         },
 };
 
 static struct plat_sci_port scif_platform_data = {
-        .mapbase        = 0xffe80000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
+};
+
+static struct resource scif_resources[] = {
+        DEFINE_RES_MEM(0xffe80000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
 };
 
 static struct platform_device scif_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif_resources,
+        .num_resources  = ARRAY_SIZE(scif_resources),
         .dev            = {
                 .platform_data  = &scif_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 98e075ada44e..1abd9fb4a386 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xfe600000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x880),
-                            evt2irq(0x8a0),
-                            evt2irq(0x8e0),
-                            evt2irq(0x8c0) },
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xfe600000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
+        DEFINE_RES_IRQ(evt2irq(0x8a0)),
+        DEFINE_RES_IRQ(evt2irq(0x8e0)),
+        DEFINE_RES_IRQ(evt2irq(0x8c0)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xfe610000,
         .flags          = UPF_BOOT_AUTOCONF,
         .type           = PORT_SCIF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
-        .irqs           = { evt2irq(0xb00),
-                            evt2irq(0xb20),
-                            evt2irq(0xb60),
-                            evt2irq(0xb40) },
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xfe610000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xb00)),
+        DEFINE_RES_IRQ(evt2irq(0xb20)),
+        DEFINE_RES_IRQ(evt2irq(0xb60)),
+        DEFINE_RES_IRQ(evt2irq(0xb40)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfe620000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0xb80),
-                            evt2irq(0xba0),
-                            evt2irq(0xbe0),
-                            evt2irq(0xbc0) },
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfe620000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xb80)),
+        DEFINE_RES_IRQ(evt2irq(0xba0)),
+        DEFINE_RES_IRQ(evt2irq(0xbe0)),
+        DEFINE_RES_IRQ(evt2irq(0xbc0)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfe480000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
-        .irqs           = { evt2irq(0xc00),
-                            evt2irq(0xc20),
-                            evt2irq(0xc40), },
         .regshift       = 2,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfe480000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
+        DEFINE_RES_IRQ(evt2irq(0xc40)),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index b91ea8300a3e..245d19254489 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -18,68 +18,84 @@
 
 /* Serial */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe20000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc40)),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xffe30000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc60)),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xffe30000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc60)),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 0bd09d51419f..6f56cbd76b20 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,18 +20,22 @@
 #include <asm/clock.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .port_reg       = 0xa405013e,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 6a868b091c2d..5a94efc8d4ce 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -179,57 +179,69 @@ struct platform_device dma_device = {
 
 /* Serial */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
         .ops            = &sh7722_sci_port_ops,
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
         .ops            = &sh7722_sci_port_ops,
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
         .ops            = &sh7722_sci_port_ops,
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe20000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc40)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 28d6fd835fe0..3c5eb0993a75 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,111 +23,138 @@
 
 /* Serial */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .port_reg       = 0xa4050160,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe10000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe20000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe20000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc40)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xa4e30000,
         .flags          = UPF_BOOT_AUTOCONF,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xa4e30000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xa4e40000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xd00)),
+};
+
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xa4e40000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xd00)),
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xa4e50000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
+};
+
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xa4e50000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xfa0)),
 };
 
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 26b74c2f9496..60ebbc6842ff 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -290,111 +290,138 @@ static struct platform_device dma1_device = {
 
 /* Serial */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc00)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe10000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc20)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe20000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe20000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xc40)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xa4e30000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xa4e30000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xa4e40000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xd00)),
+};
+
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xa4e40000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xd00)),
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xa4e50000,
         .port_reg       = SCIx_NOT_SUPPORTED,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
-        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .sampling_rate  = 8,
         .type           = PORT_SCIFA,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
+};
+
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xa4e50000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xfa0)),
 };
 
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
index f799971d453c..dad4ed1b2f94 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -25,108 +25,132 @@
 
 /* SCIF */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xFFE40000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe40000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x8c0)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id                     = 0,
+        .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xFFE41000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe41000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x8e0)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
-        .id         = 1,
+        .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xFFE42000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x900)),
         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe42000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x900)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id         = 2,
+        .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xFFE43000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x920)),
         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xffe43000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x920)),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
-        .id             = 3,
+        .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xFFE44000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x940)),
         .regtype        = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xffe44000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x940)),
+};
+
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
-        .id             = 4,
+        .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xFFE43000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x960)),
         .regtype                = SCIx_SH4_SCIF_REGTYPE,
 };
 
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xffe43000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x960)),
+};
+
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
-        .id             = 5,
+        .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9079a0f9ea9b..e43e5db53913 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -24,51 +24,63 @@
 #include <cpu/sh7757.h>
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xfe4b0000,           /* SCIF2 */
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xfe4b0000, 0x100),              /* SCIF2 */
+        DEFINE_RES_IRQ(evt2irq(0x700)),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xfe4c0000,           /* SCIF3 */
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xb80)),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xfe4c0000, 0x100),              /* SCIF3 */
+        DEFINE_RES_IRQ(evt2irq(0xb80)),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xfe4d0000,           /* SCIF4 */
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xF00)),
+};
+
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xfe4d0000, 0x100),              /* SCIF4 */
+        DEFINE_RES_IRQ(evt2irq(0xf00)),
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 1686acaaf45a..5eebbd7f4c21 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,54 +19,66 @@
 #include <linux/usb/ohci_pdriver.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe08000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xb80)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe08000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xb80)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xf00)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xf00)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 256ea7a45164..e1ba8cb74e5a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -16,170 +16,210 @@
 #include <linux/io.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xff923000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xff923000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9a0)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xff924000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xff924000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9c0)),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xff925000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xff925000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9e0)),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xff926000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xa00)),
+};
+
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xff926000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xa00)),
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xff927000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xa20)),
+};
+
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xff927000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xa20)),
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xff928000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xa40)),
+};
+
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xff928000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xa40)),
 };
 
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
 };
 
 static struct plat_sci_port scif6_platform_data = {
-        .mapbase        = 0xff929000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xa60)),
+};
+
+static struct resource scif6_resources[] = {
+        DEFINE_RES_MEM(0xff929000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xa60)),
 };
 
 static struct platform_device scif6_device = {
         .name           = "sh-sci",
         .id             = 6,
+        .resource       = scif6_resources,
+        .num_resources  = ARRAY_SIZE(scif6_resources),
         .dev            = {
                 .platform_data  = &scif6_platform_data,
         },
 };
 
 static struct plat_sci_port scif7_platform_data = {
-        .mapbase        = 0xff92a000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xa80)),
+};
+
+static struct resource scif7_resources[] = {
+        DEFINE_RES_MEM(0xff92a000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xa80)),
 };
 
 static struct platform_device scif7_device = {
         .name           = "sh-sci",
         .id             = 7,
+        .resource       = scif7_resources,
+        .num_resources  = ARRAY_SIZE(scif7_resources),
         .dev            = {
                 .platform_data  = &scif7_platform_data,
         },
 };
 
 static struct plat_sci_port scif8_platform_data = {
-        .mapbase        = 0xff92b000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xaa0)),
+};
+
+static struct resource scif8_resources[] = {
+        DEFINE_RES_MEM(0xff92b000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xaa0)),
 };
 
 static struct platform_device scif8_device = {
         .name           = "sh-sci",
         .id             = 8,
+        .resource       = scif8_resources,
+        .num_resources  = ARRAY_SIZE(scif8_resources),
         .dev            = {
                 .platform_data  = &scif8_platform_data,
         },
 };
 
 static struct plat_sci_port scif9_platform_data = {
-        .mapbase        = 0xff92c000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xac0)),
+};
+
+static struct resource scif9_resources[] = {
+        DEFINE_RES_MEM(0xff92c000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xac0)),
 };
 
 static struct platform_device scif9_device = {
         .name           = "sh-sci",
         .id             = 9,
+        .resource       = scif9_resources,
+        .num_resources  = ARRAY_SIZE(scif9_resources),
         .dev            = {
                 .platform_data  = &scif9_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index de45b704687a..668e54bafa86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -18,36 +18,44 @@
 #include <cpu/dma-register.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffe00000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0xb80)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffe10000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0xb80)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
@@ -409,9 +417,7 @@ void __init plat_early_device_setup(void)
 {
         if (mach_is_sh2007()) {
                 scif0_platform_data.scscr &= ~SCSCR_CKE1;
-                scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
                 scif1_platform_data.scscr &= ~SCSCR_CKE1;
-                scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
         }
 
         early_platform_add_devices(sh7780_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 0968ecb962e6..4aa679140209 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,108 +20,132 @@
 #include <cpu/dma-register.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffea0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffea0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffeb0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x780)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffeb0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x780)),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffec0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x980)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffec0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x980)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xffed0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xffed0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9a0)),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xffee0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xffee0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9c0)),
+};
+
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xffef0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xffef0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x9e0)),
+};
+
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index ab52d4d4484d..5d619a551a3b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -28,21 +28,25 @@
 #include <asm/mmzone.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffea0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x700),
-                            evt2irq(0x720),
-                            evt2irq(0x760),
-                            evt2irq(0x740) },
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffea0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+        DEFINE_RES_IRQ(evt2irq(0x720)),
+        DEFINE_RES_IRQ(evt2irq(0x760)),
+        DEFINE_RES_IRQ(evt2irq(0x740)),
+};
+
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
@@ -52,90 +56,119 @@ static struct platform_device scif0_device = {
  * The rest of these all have multiplexed IRQs
  */
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffeb0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x780)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffeb0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x780)),
+};
+
+static struct resource scif1_demux_resources[] = {
+        DEFINE_RES_MEM(0xffeb0000, 0x100),
+        /* Placeholders, see sh7786_devices_setup() */
+        DEFINE_RES_IRQ(0),
+        DEFINE_RES_IRQ(0),
+        DEFINE_RES_IRQ(0),
+        DEFINE_RES_IRQ(0),
+};
+
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffec0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x840)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffec0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x840)),
+};
+
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct plat_sci_port scif3_platform_data = {
-        .mapbase        = 0xffed0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x860)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif3_resources[] = {
+        DEFINE_RES_MEM(0xffed0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x860)),
+};
+
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
         .id             = 3,
+        .resource       = scif3_resources,
+        .num_resources  = ARRAY_SIZE(scif3_resources),
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct plat_sci_port scif4_platform_data = {
-        .mapbase        = 0xffee0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif4_resources[] = {
+        DEFINE_RES_MEM(0xffee0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
+};
+
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
         .id             = 4,
+        .resource       = scif4_resources,
+        .num_resources  = ARRAY_SIZE(scif4_resources),
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
 };
 
 static struct plat_sci_port scif5_platform_data = {
-        .mapbase        = 0xffef0000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 };
 
+static struct resource scif5_resources[] = {
+        DEFINE_RES_MEM(0xffef0000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x8a0)),
+};
+
 static struct platform_device scif5_device = {
         .name           = "sh-sci",
         .id             = 5,
+        .resource       = scif5_resources,
+        .num_resources  = ARRAY_SIZE(scif5_resources),
         .dev            = {
                 .platform_data  = &scif5_platform_data,
         },
@@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void)
          */
         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
         if (irq > 0) {
-                scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
-                scif1_platform_data.irqs[SCIx_ERI_IRQ] =
+                scif1_demux_resources[1].start =
                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
-                scif1_platform_data.irqs[SCIx_BRI_IRQ] =
-                        intc_irq_lookup(sh7786_intc_desc.name, BRI1);
-                scif1_platform_data.irqs[SCIx_RXI_IRQ] =
+                scif1_demux_resources[2].start =
                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
+                scif1_demux_resources[3].start = irq;
+                scif1_demux_resources[4].start =
+                        intc_irq_lookup(sh7786_intc_desc.name, BRI1);
+
+                scif1_device.resource = scif1_demux_resources;
+                scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
         }
 
         ret = platform_add_devices(sh7786_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 688f7ed1bab1..0856bcbb1da0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -28,60 +28,72 @@
  * all rather than adding infrastructure to hack around it.
  */
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = 0xffc30000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x700),
-                            evt2irq(0x720),
-                            evt2irq(0x760),
-                            evt2irq(0x740) },
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(0xffc30000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x700)),
+        DEFINE_RES_IRQ(evt2irq(0x720)),
+        DEFINE_RES_IRQ(evt2irq(0x760)),
+        DEFINE_RES_IRQ(evt2irq(0x740)),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct plat_sci_port scif1_platform_data = {
-        .mapbase        = 0xffc40000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x780),
-                            evt2irq(0x7a0),
-                            evt2irq(0x7e0),
-                            evt2irq(0x7c0) },
+};
+
+static struct resource scif1_resources[] = {
+        DEFINE_RES_MEM(0xffc40000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x780)),
+        DEFINE_RES_IRQ(evt2irq(0x7a0)),
+        DEFINE_RES_IRQ(evt2irq(0x7e0)),
+        DEFINE_RES_IRQ(evt2irq(0x7c0)),
 };
 
 static struct platform_device scif1_device = {
         .name           = "sh-sci",
         .id             = 1,
+        .resource       = scif1_resources,
+        .num_resources  = ARRAY_SIZE(scif1_resources),
         .dev            = {
                 .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct plat_sci_port scif2_platform_data = {
-        .mapbase        = 0xffc60000,
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { evt2irq(0x880),
-                            evt2irq(0x8a0),
-                            evt2irq(0x8e0),
-                            evt2irq(0x8c0) },
+};
+
+static struct resource scif2_resources[] = {
+        DEFINE_RES_MEM(0xffc60000, 0x100),
+        DEFINE_RES_IRQ(evt2irq(0x880)),
+        DEFINE_RES_IRQ(evt2irq(0x8a0)),
+        DEFINE_RES_IRQ(evt2irq(0x8e0)),
+        DEFINE_RES_IRQ(evt2irq(0x8c0)),
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
         .id             = 2,
+        .resource       = scif2_resources,
+        .num_resources  = ARRAY_SIZE(scif2_resources),
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 18419f1de963..14d68213d16b 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -17,17 +17,23 @@
 #include <asm/addrspace.h>
 
 static struct plat_sci_port scif0_platform_data = {
-        .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = { 39, 40, 42, 0 },
+};
+
+static struct resource scif0_resources[] = {
+        DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100),
+        DEFINE_RES_IRQ(39),
+        DEFINE_RES_IRQ(40),
+        DEFINE_RES_IRQ(42),
 };
 
 static struct platform_device scif0_device = {
         .name           = "sh-sci",
         .id             = 0,
+        .resource       = scif0_resources,
+        .num_resources  = ARRAY_SIZE(scif0_resources),
         .dev            = {
                 .platform_data  = &scif0_platform_data,
         },
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index 49c09c7d5b77..67a049e75ec1 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -995,29 +995,19 @@ static struct unwinder dwarf_unwinder = {
 
 static void dwarf_unwinder_cleanup(void)
 {
-        struct rb_node **fde_rb_node = &fde_root.rb_node;
-        struct rb_node **cie_rb_node = &cie_root.rb_node;
+        struct dwarf_fde *fde, *next_fde;
+        struct dwarf_cie *cie, *next_cie;
 
         /*
          * Deallocate all the memory allocated for the DWARF unwinder.
          * Traverse all the FDE/CIE lists and remove and free all the
          * memory associated with those data structures.
          */
-        while (*fde_rb_node) {
-                struct dwarf_fde *fde;
-
-                fde = rb_entry(*fde_rb_node, struct dwarf_fde, node);
-                rb_erase(*fde_rb_node, &fde_root);
+        rbtree_postorder_for_each_entry_safe(fde, next_fde, &fde_root, node)
                 kfree(fde);
-        }
 
-        while (*cie_rb_node) {
-                struct dwarf_cie *cie;
-
-                cie = rb_entry(*cie_rb_node, struct dwarf_cie, node);
-                rb_erase(*cie_rb_node, &cie_root);
+        rbtree_postorder_for_each_entry_safe(cie, next_cie, &cie_root, node)
                 kfree(cie);
-        }
 
         kmem_cache_destroy(dwarf_reg_cachep);
         kmem_cache_destroy(dwarf_frame_cachep);
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 38b313909ac9..adad46e41a1d 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -13,6 +13,7 @@
 #include <linux/kdebug.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/sched.h>
 #include <asm/cacheflush.h>
 #include <asm/traps.h>
 
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 1cf90e947dbf..de19cfa768f2 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -230,8 +230,8 @@ void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
         pmb_bolt_mapping((unsigned long)__va(start), start, end - start,
                          PAGE_KERNEL);
 
-        memblock_set_node(PFN_PHYS(start_pfn),
-                          PFN_PHYS(end_pfn - start_pfn), nid);
+        memblock_set_node(PFN_PHYS(start_pfn), PFN_PHYS(end_pfn - start_pfn),
+                          &memblock.memory, nid);
 }
 
 void __init __weak plat_early_device_setup(void)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index d4f7a6a163dc..c51efdcd07a2 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -13,6 +13,7 @@ config SPARC
         bool
         default y
         select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select OF
         select OF_PROMTREE
         select HAVE_IDE
@@ -152,10 +153,10 @@ config SMP
           a system with only one CPU, say N. If you have a system with more
           than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           People using multiprocessor machines who say Y here should also say
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
index bf390667657a..4b60a0c325ec 100644
--- a/arch/sparc/include/asm/Kbuild
+++ b/arch/sparc/include/asm/Kbuild
@@ -17,3 +17,4 @@ generic-y += trace_clock.h
 generic-y += types.h
 generic-y += word-at-a-time.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/sparc/include/uapi/asm/socket.h b/arch/sparc/include/uapi/asm/socket.h
index 0f21e9a5ca18..54d9608681b6 100644
--- a/arch/sparc/include/uapi/asm/socket.h
+++ b/arch/sparc/include/uapi/asm/socket.h
@@ -74,6 +74,8 @@
 
 #define SO_MAX_PACING_RATE      0x0031
 
+#define SO_BPF_EXTENSIONS       0x0032
+
 /* Security levels - as per NRL IPv6 - don't actually do anything */
 #define SO_SECURITY_AUTHENTICATION              0x5001
 #define SO_SECURITY_ENCRYPTION_TRANSPORT        0x5002
diff --git a/arch/sparc/include/uapi/asm/unistd.h b/arch/sparc/include/uapi/asm/unistd.h
index 62ced589bcf7..b73274fb961a 100644
--- a/arch/sparc/include/uapi/asm/unistd.h
+++ b/arch/sparc/include/uapi/asm/unistd.h
@@ -408,8 +408,10 @@
 #define __NR_kern_features      340
 #define __NR_kcmp               341
 #define __NR_finit_module       342
+#define __NR_sched_setattr      343
+#define __NR_sched_getattr      344
 
-#define NR_syscalls             343
+#define NR_syscalls             345
 
 /* Bitmask values returned from kern_features system call.  */
 #define KERN_FEATURE_MIXED_MODE_STACK   0x00000001
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
index cb5d272d658a..de1c844dfabc 100644
--- a/arch/sparc/kernel/cpumap.c
+++ b/arch/sparc/kernel/cpumap.c
@@ -6,7 +6,6 @@
 #include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/cpumask.h>
 #include <linux/spinlock.h>
 #include <asm/cpudata.h>
diff --git a/arch/sparc/kernel/ebus.c b/arch/sparc/kernel/ebus.c
index e306fb08ee5e..acf8314cec48 100644
--- a/arch/sparc/kernel/ebus.c
+++ b/arch/sparc/kernel/ebus.c
@@ -7,7 +7,6 @@
 #include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 
diff --git a/arch/sparc/kernel/hvtramp.S b/arch/sparc/kernel/hvtramp.S
index 4eb1a5a1d544..b7ddcdd1dea9 100644
--- a/arch/sparc/kernel/hvtramp.S
+++ b/arch/sparc/kernel/hvtramp.S
@@ -3,7 +3,6 @@
  * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
  */
 
-#include <linux/init.h>
 
 #include <asm/thread_info.h>
 #include <asm/hypervisor.h>
diff --git a/arch/sparc/kernel/of_device_common.c b/arch/sparc/kernel/of_device_common.c
index de199bf0cb05..3241f56331c2 100644
--- a/arch/sparc/kernel/of_device_common.c
+++ b/arch/sparc/kernel/of_device_common.c
@@ -1,7 +1,6 @@
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/of.h>
-#include <linux/init.h>
 #include <linux/export.h>
 #include <linux/mod_devicetable.h>
 #include <linux/errno.h>
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index cb021453de2a..1555bbcae1ee 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -392,7 +392,7 @@ static void apb_fake_ranges(struct pci_dev *dev,
         res->flags = IORESOURCE_IO;
         region.start = (first << 21);
         region.end = (last << 21) + ((1 << 21) - 1);
-        pcibios_bus_to_resource(dev, res, &region);
+        pcibios_bus_to_resource(dev->bus, res, &region);
 
         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
         apb_calc_first_last(map, &first, &last);
@@ -400,7 +400,7 @@ static void apb_fake_ranges(struct pci_dev *dev,
         res->flags = IORESOURCE_MEM;
         region.start = (first << 29);
         region.end = (last << 29) + ((1 << 29) - 1);
-        pcibios_bus_to_resource(dev, res, &region);
+        pcibios_bus_to_resource(dev->bus, res, &region);
 }
 
 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
@@ -491,7 +491,7 @@ static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
                 res->flags = flags;
                 region.start = GET_64BIT(ranges, 1);
                 region.end = region.start + size - 1;
-                pcibios_bus_to_resource(dev, res, &region);
+                pcibios_bus_to_resource(dev->bus, res, &region);
         }
 after_ranges:
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
@@ -1005,6 +1005,5 @@ static int __init of_pci_slot_init(void)
 
         return 0;
 }
-
-module_init(of_pci_slot_init);
+device_initcall(of_pci_slot_init);
 #endif
diff --git a/arch/sparc/kernel/pci_common.c b/arch/sparc/kernel/pci_common.c
index a6895987fb70..944a06536ecc 100644
--- a/arch/sparc/kernel/pci_common.c
+++ b/arch/sparc/kernel/pci_common.c
@@ -5,7 +5,6 @@
 
 #include <linux/string.h>
 #include <linux/slab.h>
-#include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/device.h>
 #include <linux/of_device.h>
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index fdd819dfdacf..510baec1b69b 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -22,7 +22,6 @@
 #include <linux/reboot.h>
 #include <linux/delay.h>
 #include <linux/pm.h>
-#include <linux/init.h>
 #include <linux/slab.h>
 
 #include <asm/auxio.h>
diff --git a/arch/sparc/kernel/sparc_ksyms_32.c b/arch/sparc/kernel/sparc_ksyms_32.c
index e521c54560f9..bf4ccb10a78c 100644
--- a/arch/sparc/kernel/sparc_ksyms_32.c
+++ b/arch/sparc/kernel/sparc_ksyms_32.c
@@ -6,7 +6,6 @@
  */
 
 #include <linux/module.h>
-#include <linux/init.h>
 
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c
index 9f5e24ddcc70..a92d5d2c46a3 100644
--- a/arch/sparc/kernel/sparc_ksyms_64.c
+++ b/arch/sparc/kernel/sparc_ksyms_64.c
@@ -7,7 +7,6 @@
 
 #include <linux/export.h>
 #include <linux/pci.h>
-#include <linux/init.h>
 #include <linux/bitops.h>
 
 #include <asm/cpudata.h>
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 7b87171ecf1e..151ace8766cc 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -85,4 +85,4 @@ sys_call_table:
 /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
 /*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
-/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module
+/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 6d81597064b6..4bd4e2bb26cf 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -86,7 +86,7 @@ sys_call_table32:
         .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init
 /*330*/ .word compat_sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime
         .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev
-/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module
+/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
 
 #endif /* CONFIG_COMPAT */
 
@@ -164,4 +164,4 @@ sys_call_table:
         .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
         .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
-/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module
+/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
diff --git a/arch/sparc/kernel/trampoline_32.S b/arch/sparc/kernel/trampoline_32.S
index 76dcbd3c988a..3eed99fc6989 100644
--- a/arch/sparc/kernel/trampoline_32.S
+++ b/arch/sparc/kernel/trampoline_32.S
@@ -5,7 +5,6 @@
  * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  */
 
-#include <linux/init.h>
 #include <asm/head.h>
 #include <asm/psr.h>
 #include <asm/page.h>
diff --git a/arch/sparc/kernel/trampoline_64.S b/arch/sparc/kernel/trampoline_64.S
index ad4bde3bb61e..737f8cbc7d56 100644
--- a/arch/sparc/kernel/trampoline_64.S
+++ b/arch/sparc/kernel/trampoline_64.S
@@ -4,7 +4,6 @@
  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  */
 
-#include <linux/init.h>
 
 #include <asm/head.h>
 #include <asm/asi.h>
diff --git a/arch/sparc/mm/hugetlbpage.c b/arch/sparc/mm/hugetlbpage.c
index 30963178d7e9..9bd9ce80bf77 100644
--- a/arch/sparc/mm/hugetlbpage.c
+++ b/arch/sparc/mm/hugetlbpage.c
@@ -4,7 +4,6 @@
  * Copyright (C) 2002, 2003, 2006 David S. Miller (davem@davemloft.net)
  */
 
-#include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 5322e530d09c..eafbc65c9c47 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1021,7 +1021,8 @@ static void __init add_node_ranges(void)
                                 "start[%lx] end[%lx]\n",
                                 nid, start, this_end);
 
-                        memblock_set_node(start, this_end - start, nid);
+                        memblock_set_node(start, this_end - start,
+                                          &memblock.memory, nid);
                         start = this_end;
                 }
         }
@@ -1325,7 +1326,7 @@ static void __init bootmem_init_nonnuma(void)
                (top_of_ram - total_ram) >> 20);
 
         init_node_masks_nonnuma();
-        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
+        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
         allocate_node_data(0);
         node_set_online(0);
 }
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index ad3bf4b4324d..b12cb5e72812 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/mm.h>
 #include <linux/swap.h>
diff --git a/arch/sparc/prom/p1275.c b/arch/sparc/prom/p1275.c
index 04a4540509dd..e58b81726319 100644
--- a/arch/sparc/prom/p1275.c
+++ b/arch/sparc/prom/p1275.c
@@ -5,7 +5,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/string.h>
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
index 22f3bd147fa7..3793c75e45d9 100644
--- a/arch/tile/include/asm/Kbuild
+++ b/arch/tile/include/asm/Kbuild
@@ -39,3 +39,4 @@ generic-y += trace_clock.h
 generic-y += types.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index 78f1f2ded86c..ffd4493efc78 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -281,7 +281,6 @@ long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count,
                         u32 dummy, u32 low, u32 high);
 long compat_sys_pwrite64(unsigned int fd, char __user *ubuf, size_t count,
                          u32 dummy, u32 low, u32 high);
-long compat_sys_lookup_dcookie(u32 low, u32 high, char __user *buf, size_t len);
 long compat_sys_sync_file_range2(int fd, unsigned int flags,
                                  u32 offset_lo, u32 offset_hi,
                                  u32 nbytes_lo, u32 nbytes_hi);
diff --git a/arch/tile/include/asm/fixmap.h b/arch/tile/include/asm/fixmap.h
index c6b9c1b38fd1..ffe2637aeb31 100644
--- a/arch/tile/include/asm/fixmap.h
+++ b/arch/tile/include/asm/fixmap.h
@@ -25,9 +25,6 @@
 #include <asm/kmap_types.h>
 #endif
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
 /*
  * Here we define all the compile-time 'special' virtual
  * addresses. The point is to have a constant address at
@@ -83,35 +80,7 @@ enum fixed_addresses {
 #define FIXADDR_START           (FIXADDR_TOP + PAGE_SIZE - __FIXADDR_SIZE)
 #define FIXADDR_BOOT_START      (FIXADDR_TOP + PAGE_SIZE - __FIXADDR_BOOT_SIZE)
 
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
index fdde187e6087..88a330dcdede 100644
--- a/arch/um/include/asm/Kbuild
+++ b/arch/um/include/asm/Kbuild
@@ -4,3 +4,5 @@ generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h exec.h
 generic-y += switch_to.h clkdev.h
 generic-y += trace_clock.h
 generic-y += preempt.h
+generic-y += hash.h
+generic-y += barrier.h
diff --git a/arch/um/include/asm/fixmap.h b/arch/um/include/asm/fixmap.h
index 21a423bae5e8..3094ea3c73b0 100644
--- a/arch/um/include/asm/fixmap.h
+++ b/arch/um/include/asm/fixmap.h
@@ -43,13 +43,6 @@ enum fixed_addresses {
 extern void __set_fixmap (enum fixed_addresses idx,
                           unsigned long phys, pgprot_t flags);
 
-#define set_fixmap(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
 /*
  * used by vmalloc.c.
  *
@@ -62,37 +55,6 @@ extern void __set_fixmap (enum fixed_addresses idx,
 #define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
 
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)      ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-      BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-      return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
 
 #endif
diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h
index d89b02bb6262..cbc5edd5a901 100644
--- a/arch/um/include/asm/processor-generic.h
+++ b/arch/um/include/asm/processor-generic.h
@@ -25,10 +25,8 @@ struct thread_struct {
         void *fault_addr;
         jmp_buf *fault_catcher;
         struct task_struct *prev_sched;
-        unsigned long temp_stack;
         struct arch_thread arch;
         jmp_buf switch_buf;
-        int mm_count;
         struct {
                 int op;
                 union {
@@ -52,7 +50,6 @@ struct thread_struct {
         .regs                   = EMPTY_REGS,   \
         .fault_addr             = NULL, \
         .prev_sched             = NULL, \
-        .temp_stack             = 0, \
         .arch                   = INIT_ARCH_THREAD, \
         .request                = { 0 } \
 }
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index a7ba27b2752b..25c0dba508cc 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -1,6 +1,7 @@
 config UNICORE32
         def_bool y
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select HAVE_MEMBLOCK
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_DMA_ATTRS
diff --git a/arch/unicore32/include/asm/Kbuild b/arch/unicore32/include/asm/Kbuild
index 00045cbe5c63..3ef4f9d9bf5d 100644
--- a/arch/unicore32/include/asm/Kbuild
+++ b/arch/unicore32/include/asm/Kbuild
@@ -61,3 +61,4 @@ generic-y += user.h
 generic-y += vga.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/unicore32/kernel/early_printk.c b/arch/unicore32/kernel/early_printk.c
index 9be0d5d02a9a..f2f6323c8d64 100644
--- a/arch/unicore32/kernel/early_printk.c
+++ b/arch/unicore32/kernel/early_printk.c
@@ -35,17 +35,11 @@ static struct console early_ocd_console = {
 
 static int __init setup_early_printk(char *buf)
 {
-        int keep_early;
-
         if (!buf || early_console)
                 return 0;
 
-        if (strstr(buf, "keep"))
-                keep_early = 1;
-
         early_console = &early_ocd_console;
-
-        if (keep_early)
+        if (strstr(buf, "keep"))
                 early_console->flags &= ~CON_BOOT;
         else
                 early_console->flags |= CON_BOOT;
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index ae6bc036db92..be2bde9b07cf 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -66,9 +66,6 @@ void show_mem(unsigned int filter)
         printk(KERN_DEFAULT "Mem-info:\n");
         show_free_areas(filter);
 
-        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
-                return;
-
         for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
                 unsigned int pfn1, pfn2;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3b6922ebf170..0af5250d914f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -23,6 +23,7 @@ config X86
         def_bool y
         select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
         select ARCH_MIGHT_HAVE_PC_PARPORT
+        select ARCH_MIGHT_HAVE_PC_SERIO
         select HAVE_AOUT if X86_32
         select HAVE_UNSTABLE_SCHED_CLOCK
         select ARCH_SUPPORTS_NUMA_BALANCING
@@ -279,13 +280,13 @@ config SMP
         bool "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
-          a system with only one CPU, like most personal computers, say N. If
-          you have a system with more than one CPU, say Y.
+          a system with only one CPU, say N. If you have a system with more
+          than one CPU, say Y.
 
-          If you say N here, the kernel will run on single and multiprocessor
+          If you say N here, the kernel will run on uni- and multiprocessor
           machines, but will use only one CPU of a multiprocessor machine. If
           you say Y here, the kernel will run on many, but not all,
-          singleprocessor machines. On a singleprocessor machine, the kernel
+          uniprocessor machines. On a uniprocessor machine, the kernel
           will run faster if you say N here.
 
           Note that if you say Y here and choose architecture "586" or
@@ -732,6 +733,7 @@ config APB_TIMER
 # The code disables itself when not needed.
 config DMI
         default y
+        select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
         bool "Enable DMI scanning" if EXPERT
         ---help---
           Enabled scanning of DMI to identify machine quirks. Say Y
@@ -939,7 +941,7 @@ config X86_ANCIENT_MCE
         depends on X86_32 && X86_MCE
         ---help---
           Include support for machine check handling on old Pentium 5 or WinChip
-          systems. These typically need to be enabled explicitely on the command
+          systems. These typically need to be enabled explicitly on the command
           line.
 
 config X86_MCE_THRESHOLD
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 13b22e0f681d..eeda43abed6e 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -11,6 +11,28 @@ else
         KBUILD_DEFCONFIG := $(ARCH)_defconfig
 endif
 
+# How to compile the 16-bit code.  Note we always compile for -march=i386;
+# that way we can complain to the user if the CPU is insufficient.
+#
+# The -m16 option is supported by GCC >= 4.9 and clang >= 3.5. For
+# older versions of GCC, we need to play evil and unreliable tricks to
+# attempt to ensure that our asm(".code16gcc") is first in the asm
+# output.
+CODE16GCC_CFLAGS := -m32 -include $(srctree)/arch/x86/boot/code16gcc.h \
+                    $(call cc-option, -fno-toplevel-reorder,\
+                      $(call cc-option, -fno-unit-at-a-time))
+M16_CFLAGS       := $(call cc-option, -m16, $(CODE16GCC_CFLAGS))
+
+REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -D__KERNEL__ \
+                   -DDISABLE_BRANCH_PROFILING \
+                   -Wall -Wstrict-prototypes -march=i386 -mregparm=3 \
+                   -fno-strict-aliasing -fomit-frame-pointer -fno-pic \
+                   -mno-mmx -mno-sse \
+                   $(call cc-option, -ffreestanding) \
+                   $(call cc-option, -fno-stack-protector) \
+                   $(call cc-option, -mpreferred-stack-boundary=2)
+export REALMODE_CFLAGS
+
 # BITS is used as extension for files which are available in a 32 bit
 # and a 64 bit version to simplify shared Makefiles.
 # e.g.: obj-y += foo_$(BITS).o
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index de7066918005..878df7e88cd4 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -51,20 +51,7 @@ $(obj)/cpustr.h: $(obj)/mkcpustr FORCE
 
 # ---------------------------------------------------------------------------
 
-# How to compile the 16-bit code.  Note we always compile for -march=i386,
-# that way we can complain to the user if the CPU is insufficient.
-KBUILD_CFLAGS   := $(USERINCLUDE) -m32 -g -Os -D_SETUP -D__KERNEL__ \
-                   -DDISABLE_BRANCH_PROFILING \
-                   -Wall -Wstrict-prototypes \
-                   -march=i386 -mregparm=3 \
-                   -include $(srctree)/$(src)/code16gcc.h \
-                   -fno-strict-aliasing -fomit-frame-pointer -fno-pic \
-                   -mno-mmx -mno-sse \
-                   $(call cc-option, -ffreestanding) \
-                   $(call cc-option, -fno-toplevel-reorder,\
-                   $(call cc-option, -fno-unit-at-a-time)) \
-                   $(call cc-option, -fno-stack-protector) \
-                   $(call cc-option, -mpreferred-stack-boundary=2)
+KBUILD_CFLAGS   := $(USERINCLUDE) $(REALMODE_CFLAGS) -D_SETUP
 KBUILD_AFLAGS   := $(KBUILD_CFLAGS) -D__ASSEMBLY__
 GCOV_PROFILE := n
 
diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c
index a9fcb7cfb241..431fa5f84537 100644
--- a/arch/x86/boot/cpuflags.c
+++ b/arch/x86/boot/cpuflags.c
@@ -28,20 +28,35 @@ static int has_fpu(void)
         return fsw == 0 && (fcw & 0x103f) == 0x003f;
 }
 
+/*
+ * For building the 16-bit code we want to explicitly specify 32-bit
+ * push/pop operations, rather than just saying 'pushf' or 'popf' and
+ * letting the compiler choose. But this is also included from the
+ * compressed/ directory where it may be 64-bit code, and thus needs
+ * to be 'pushfq' or 'popfq' in that case.
+ */
+#ifdef __x86_64__
+#define PUSHF "pushfq"
+#define POPF "popfq"
+#else
+#define PUSHF "pushfl"
+#define POPF "popfl"
+#endif
+
 int has_eflag(unsigned long mask)
 {
         unsigned long f0, f1;
 
-        asm volatile("pushf     \n\t"
-                     "pushf     \n\t"
+        asm volatile(PUSHF "    \n\t"
+                     PUSHF "    \n\t"
                      "pop %0    \n\t"
                      "mov %0,%1 \n\t"
                      "xor %2,%1 \n\t"
                      "push %1   \n\t"
-                     "popf      \n\t"
-                     "pushf     \n\t"
+                     POPF "     \n\t"
+                     PUSHF "    \n\t"
                      "pop %1    \n\t"
-                     "popf"
+                     POPF
                      : "=&r" (f0), "=&r" (f1)
                      : "ri" (mask));
 
diff --git a/arch/x86/boot/video.h b/arch/x86/boot/video.h
index ff339c5db311..0bb25491262d 100644
--- a/arch/x86/boot/video.h
+++ b/arch/x86/boot/video.h
@@ -80,7 +80,7 @@ struct card_info {
         u16 xmode_n;            /* Size of unprobed mode range */
 };
 
-#define __videocard struct card_info __attribute__((section(".videocards")))
+#define __videocard struct card_info __attribute__((used,section(".videocards")))
 extern struct card_info video_cards[], video_cards_end[];
 
 int mode_defined(u16 mode);     /* video.c */
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index e0fc24db234a..6ba54d640383 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -76,6 +76,7 @@ ifeq ($(avx2_supported),yes)
 endif
 
 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
+aesni-intel-$(CONFIG_64BIT) += aesni-intel_avx-x86_64.o
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
 sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
 crc32c-intel-y := crc32c-intel_glue.o
diff --git a/arch/x86/crypto/aesni-intel_avx-x86_64.S b/arch/x86/crypto/aesni-intel_avx-x86_64.S
new file mode 100644
index 000000000000..522ab68d1c88
--- /dev/null
+++ b/arch/x86/crypto/aesni-intel_avx-x86_64.S
@@ -0,0 +1,2811 @@
+########################################################################
+# Copyright (c) 2013, Intel Corporation
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the
+#   distribution.
+#
+# * Neither the name of the Intel Corporation nor the names of its
+#   contributors may be used to endorse or promote products derived from
+#   this software without specific prior written permission.
+#
+#
+# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES# LOSS OF USE, DATA, OR
+# PROFITS# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
+##
+## Authors:
+##      Erdinc Ozturk <erdinc.ozturk@intel.com>
+##      Vinodh Gopal <vinodh.gopal@intel.com>
+##      James Guilford <james.guilford@intel.com>
+##      Tim Chen <tim.c.chen@linux.intel.com>
+##
+## References:
+##       This code was derived and highly optimized from the code described in paper:
+##               Vinodh Gopal et. al. Optimized Galois-Counter-Mode Implementation
+##                      on Intel Architecture Processors. August, 2010
+##       The details of the implementation is explained in:
+##               Erdinc Ozturk et. al. Enabling High-Performance Galois-Counter-Mode
+##                      on Intel Architecture Processors. October, 2012.
+##
+## Assumptions:
+##
+##
+##
+## iv:
+##       0                   1                   2                   3
+##       0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                             Salt  (From the SA)               |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                     Initialization Vector                     |
+##       |         (This is the sequence number from IPSec header)       |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                              0x1                              |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##
+##
+##
+## AAD:
+##       AAD padded to 128 bits with 0
+##       for example, assume AAD is a u32 vector
+##
+##       if AAD is 8 bytes:
+##       AAD[3] = {A0, A1}#
+##       padded AAD in xmm register = {A1 A0 0 0}
+##
+##       0                   1                   2                   3
+##       0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                               SPI (A1)                        |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                     32-bit Sequence Number (A0)               |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                              0x0                              |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##
+##                                       AAD Format with 32-bit Sequence Number
+##
+##       if AAD is 12 bytes:
+##       AAD[3] = {A0, A1, A2}#
+##       padded AAD in xmm register = {A2 A1 A0 0}
+##
+##       0                   1                   2                   3
+##       0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                               SPI (A2)                        |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                 64-bit Extended Sequence Number {A1,A0}       |
+##       |                                                               |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##       |                              0x0                              |
+##       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+##
+##        AAD Format with 64-bit Extended Sequence Number
+##
+##
+## aadLen:
+##       from the definition of the spec, aadLen can only be 8 or 12 bytes.
+##       The code additionally supports aadLen of length 16 bytes.
+##
+## TLen:
+##       from the definition of the spec, TLen can only be 8, 12 or 16 bytes.
+##
+## poly = x^128 + x^127 + x^126 + x^121 + 1
+## throughout the code, one tab and two tab indentations are used. one tab is
+## for GHASH part, two tabs is for AES part.
+##
+
+#include <linux/linkage.h>
+#include <asm/inst.h>
+
+.data
+.align 16
+
+POLY:            .octa     0xC2000000000000000000000000000001
+POLY2:           .octa     0xC20000000000000000000001C2000000
+TWOONE:          .octa     0x00000001000000000000000000000001
+
+# order of these constants should not change.
+# more specifically, ALL_F should follow SHIFT_MASK, and ZERO should follow ALL_F
+
+SHUF_MASK:       .octa     0x000102030405060708090A0B0C0D0E0F
+SHIFT_MASK:      .octa     0x0f0e0d0c0b0a09080706050403020100
+ALL_F:           .octa     0xffffffffffffffffffffffffffffffff
+ZERO:            .octa     0x00000000000000000000000000000000
+ONE:             .octa     0x00000000000000000000000000000001
+ONEf:            .octa     0x01000000000000000000000000000000
+
+.text
+
+
+##define the fields of the gcm aes context
+#{
+#        u8 expanded_keys[16*11] store expanded keys
+#        u8 shifted_hkey_1[16]   store HashKey <<1 mod poly here
+#        u8 shifted_hkey_2[16]   store HashKey^2 <<1 mod poly here
+#        u8 shifted_hkey_3[16]   store HashKey^3 <<1 mod poly here
+#        u8 shifted_hkey_4[16]   store HashKey^4 <<1 mod poly here
+#        u8 shifted_hkey_5[16]   store HashKey^5 <<1 mod poly here
+#        u8 shifted_hkey_6[16]   store HashKey^6 <<1 mod poly here
+#        u8 shifted_hkey_7[16]   store HashKey^7 <<1 mod poly here
+#        u8 shifted_hkey_8[16]   store HashKey^8 <<1 mod poly here
+#        u8 shifted_hkey_1_k[16] store XOR HashKey <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_2_k[16] store XOR HashKey^2 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_3_k[16] store XOR HashKey^3 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_4_k[16] store XOR HashKey^4 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_5_k[16] store XOR HashKey^5 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_6_k[16] store XOR HashKey^6 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_7_k[16] store XOR HashKey^7 <<1 mod poly here (for Karatsuba purposes)
+#        u8 shifted_hkey_8_k[16] store XOR HashKey^8 <<1 mod poly here (for Karatsuba purposes)
+#} gcm_ctx#
+
+HashKey        = 16*11   # store HashKey <<1 mod poly here
+HashKey_2      = 16*12   # store HashKey^2 <<1 mod poly here
+HashKey_3      = 16*13   # store HashKey^3 <<1 mod poly here
+HashKey_4      = 16*14   # store HashKey^4 <<1 mod poly here
+HashKey_5      = 16*15   # store HashKey^5 <<1 mod poly here
+HashKey_6      = 16*16   # store HashKey^6 <<1 mod poly here
+HashKey_7      = 16*17   # store HashKey^7 <<1 mod poly here
+HashKey_8      = 16*18   # store HashKey^8 <<1 mod poly here
+HashKey_k      = 16*19   # store XOR of HashKey <<1 mod poly here (for Karatsuba purposes)
+HashKey_2_k    = 16*20   # store XOR of HashKey^2 <<1 mod poly here (for Karatsuba purposes)
+HashKey_3_k    = 16*21   # store XOR of HashKey^3 <<1 mod poly here (for Karatsuba purposes)
+HashKey_4_k    = 16*22   # store XOR of HashKey^4 <<1 mod poly here (for Karatsuba purposes)
+HashKey_5_k    = 16*23   # store XOR of HashKey^5 <<1 mod poly here (for Karatsuba purposes)
+HashKey_6_k    = 16*24   # store XOR of HashKey^6 <<1 mod poly here (for Karatsuba purposes)
+HashKey_7_k    = 16*25   # store XOR of HashKey^7 <<1 mod poly here (for Karatsuba purposes)
+HashKey_8_k    = 16*26   # store XOR of HashKey^8 <<1 mod poly here (for Karatsuba purposes)
+
+#define arg1 %rdi
+#define arg2 %rsi
+#define arg3 %rdx
+#define arg4 %rcx
+#define arg5 %r8
+#define arg6 %r9
+#define arg7 STACK_OFFSET+8*1(%r14)
+#define arg8 STACK_OFFSET+8*2(%r14)
+#define arg9 STACK_OFFSET+8*3(%r14)
+
+i = 0
+j = 0
+
+out_order = 0
+in_order = 1
+DEC = 0
+ENC = 1
+
+.macro define_reg r n
+reg_\r = %xmm\n
+.endm
+
+.macro setreg
+.altmacro
+define_reg i %i
+define_reg j %j
+.noaltmacro
+.endm
+
+# need to push 4 registers into stack to maintain
+STACK_OFFSET = 8*4
+
+TMP1 =   16*0    # Temporary storage for AAD
+TMP2 =   16*1    # Temporary storage for AES State 2 (State 1 is stored in an XMM register)
+TMP3 =   16*2    # Temporary storage for AES State 3
+TMP4 =   16*3    # Temporary storage for AES State 4
+TMP5 =   16*4    # Temporary storage for AES State 5
+TMP6 =   16*5    # Temporary storage for AES State 6
+TMP7 =   16*6    # Temporary storage for AES State 7
+TMP8 =   16*7    # Temporary storage for AES State 8
+
+VARIABLE_OFFSET = 16*8
+
+################################
+# Utility Macros
+################################
+
+# Encryption of a single block
+.macro ENCRYPT_SINGLE_BLOCK XMM0
+                vpxor    (arg1), \XMM0, \XMM0
+                i = 1
+                setreg
+.rep 9
+                vaesenc  16*i(arg1), \XMM0, \XMM0
+                i = (i+1)
+                setreg
+.endr
+                vaesenclast 16*10(arg1), \XMM0, \XMM0
+.endm
+
+#ifdef CONFIG_AS_AVX
+###############################################################################
+# GHASH_MUL MACRO to implement: Data*HashKey mod (128,127,126,121,0)
+# Input: A and B (128-bits each, bit-reflected)
+# Output: C = A*B*x mod poly, (i.e. >>1 )
+# To compute GH = GH*HashKey mod poly, give HK = HashKey<<1 mod poly as input
+# GH = GH * HK * x mod poly which is equivalent to GH*HashKey mod poly.
+###############################################################################
+.macro  GHASH_MUL_AVX GH HK T1 T2 T3 T4 T5
+
+        vpshufd         $0b01001110, \GH, \T2
+        vpshufd         $0b01001110, \HK, \T3
+        vpxor           \GH     , \T2, \T2      # T2 = (a1+a0)
+        vpxor           \HK     , \T3, \T3      # T3 = (b1+b0)
+
+        vpclmulqdq      $0x11, \HK, \GH, \T1    # T1 = a1*b1
+        vpclmulqdq      $0x00, \HK, \GH, \GH    # GH = a0*b0
+        vpclmulqdq      $0x00, \T3, \T2, \T2    # T2 = (a1+a0)*(b1+b0)
+        vpxor           \GH, \T2,\T2
+        vpxor           \T1, \T2,\T2            # T2 = a0*b1+a1*b0
+
+        vpslldq         $8, \T2,\T3             # shift-L T3 2 DWs
+        vpsrldq         $8, \T2,\T2             # shift-R T2 2 DWs
+        vpxor           \T3, \GH, \GH
+        vpxor           \T2, \T1, \T1           # <T1:GH> = GH x HK
+
+        #first phase of the reduction
+        vpslld  $31, \GH, \T2                   # packed right shifting << 31
+        vpslld  $30, \GH, \T3                   # packed right shifting shift << 30
+        vpslld  $25, \GH, \T4                   # packed right shifting shift << 25
+
+        vpxor   \T3, \T2, \T2                   # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpsrldq $4, \T2, \T5                    # shift-R T5 1 DW
+
+        vpslldq $12, \T2, \T2                   # shift-L T2 3 DWs
+        vpxor   \T2, \GH, \GH                   # first phase of the reduction complete
+
+        #second phase of the reduction
+
+        vpsrld  $1,\GH, \T2                     # packed left shifting >> 1
+        vpsrld  $2,\GH, \T3                     # packed left shifting >> 2
+        vpsrld  $7,\GH, \T4                     # packed left shifting >> 7
+        vpxor   \T3, \T2, \T2                   # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpxor   \T5, \T2, \T2
+        vpxor   \T2, \GH, \GH
+        vpxor   \T1, \GH, \GH                   # the result is in GH
+
+
+.endm
+
+.macro PRECOMPUTE_AVX HK T1 T2 T3 T4 T5 T6
+
+        # Haskey_i_k holds XORed values of the low and high parts of the Haskey_i
+        vmovdqa  \HK, \T5
+
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^2<<1 mod poly
+        vmovdqa  \T5, HashKey_2(arg1)                    #  [HashKey_2] = HashKey^2<<1 mod poly
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_2_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^3<<1 mod poly
+        vmovdqa  \T5, HashKey_3(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_3_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^4<<1 mod poly
+        vmovdqa  \T5, HashKey_4(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_4_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^5<<1 mod poly
+        vmovdqa  \T5, HashKey_5(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_5_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^6<<1 mod poly
+        vmovdqa  \T5, HashKey_6(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_6_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^7<<1 mod poly
+        vmovdqa  \T5, HashKey_7(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_7_k(arg1)
+
+        GHASH_MUL_AVX \T5, \HK, \T1, \T3, \T4, \T6, \T2  #  T5 = HashKey^8<<1 mod poly
+        vmovdqa  \T5, HashKey_8(arg1)
+        vpshufd  $0b01001110, \T5, \T1
+        vpxor    \T5, \T1, \T1
+        vmovdqa  \T1, HashKey_8_k(arg1)
+
+.endm
+
+## if a = number of total plaintext bytes
+## b = floor(a/16)
+## num_initial_blocks = b mod 4#
+## encrypt the initial num_initial_blocks blocks and apply ghash on the ciphertext
+## r10, r11, r12, rax are clobbered
+## arg1, arg2, arg3, r14 are used as a pointer only, not modified
+
+.macro INITIAL_BLOCKS_AVX num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC
+        i = (8-\num_initial_blocks)
+        setreg
+
+        mov     arg6, %r10                      # r10 = AAD
+        mov     arg7, %r12                      # r12 = aadLen
+
+
+        mov     %r12, %r11
+
+        vpxor   reg_i, reg_i, reg_i
+_get_AAD_loop\@:
+        vmovd   (%r10), \T1
+        vpslldq $12, \T1, \T1
+        vpsrldq $4, reg_i, reg_i
+        vpxor   \T1, reg_i, reg_i
+
+        add     $4, %r10
+        sub     $4, %r12
+        jg      _get_AAD_loop\@
+
+
+        cmp     $16, %r11
+        je      _get_AAD_loop2_done\@
+        mov     $16, %r12
+
+_get_AAD_loop2\@:
+        vpsrldq $4, reg_i, reg_i
+        sub     $4, %r12
+        cmp     %r11, %r12
+        jg      _get_AAD_loop2\@
+
+_get_AAD_loop2_done\@:
+
+        #byte-reflect the AAD data
+        vpshufb SHUF_MASK(%rip), reg_i, reg_i
+
+        # initialize the data pointer offset as zero
+        xor     %r11, %r11
+
+        # start AES for num_initial_blocks blocks
+        mov     arg5, %rax                     # rax = *Y0
+        vmovdqu (%rax), \CTR                   # CTR = Y0
+        vpshufb SHUF_MASK(%rip), \CTR, \CTR
+
+
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vpaddd  ONE(%rip), \CTR, \CTR           # INCR Y0
+                vmovdqa \CTR, reg_i
+                vpshufb SHUF_MASK(%rip), reg_i, reg_i   # perform a 16Byte swap
+        i = (i+1)
+        setreg
+.endr
+
+        vmovdqa  (arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vpxor   \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        j = 1
+        setreg
+.rep 9
+        vmovdqa  16*j(arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+        vaesenc \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        j = (j+1)
+        setreg
+.endr
+
+
+        vmovdqa  16*10(arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+        vaesenclast      \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vmovdqu (arg3, %r11), \T1
+                vpxor   \T1, reg_i, reg_i
+                vmovdqu reg_i, (arg2 , %r11)           # write back ciphertext for num_initial_blocks blocks
+                add     $16, %r11
+.if  \ENC_DEC == DEC
+                vmovdqa \T1, reg_i
+.endif
+                vpshufb SHUF_MASK(%rip), reg_i, reg_i  # prepare ciphertext for GHASH computations
+        i = (i+1)
+        setreg
+.endr
+
+
+        i = (8-\num_initial_blocks)
+        j = (9-\num_initial_blocks)
+        setreg
+        GHASH_MUL_AVX       reg_i, \T2, \T1, \T3, \T4, \T5, \T6
+
+.rep \num_initial_blocks
+        vpxor    reg_i, reg_j, reg_j
+        GHASH_MUL_AVX       reg_j, \T2, \T1, \T3, \T4, \T5, \T6 # apply GHASH on num_initial_blocks blocks
+        i = (i+1)
+        j = (j+1)
+        setreg
+.endr
+        # XMM8 has the combined result here
+
+        vmovdqa  \XMM8, TMP1(%rsp)
+        vmovdqa  \XMM8, \T3
+
+        cmp     $128, %r13
+        jl      _initial_blocks_done\@                  # no need for precomputed constants
+
+###############################################################################
+# Haskey_i_k holds XORed values of the low and high parts of the Haskey_i
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM1
+                vpshufb  SHUF_MASK(%rip), \XMM1, \XMM1  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM2
+                vpshufb  SHUF_MASK(%rip), \XMM2, \XMM2  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM3
+                vpshufb  SHUF_MASK(%rip), \XMM3, \XMM3  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM4
+                vpshufb  SHUF_MASK(%rip), \XMM4, \XMM4  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM5
+                vpshufb  SHUF_MASK(%rip), \XMM5, \XMM5  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM6
+                vpshufb  SHUF_MASK(%rip), \XMM6, \XMM6  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM7
+                vpshufb  SHUF_MASK(%rip), \XMM7, \XMM7  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM8
+                vpshufb  SHUF_MASK(%rip), \XMM8, \XMM8  # perform a 16Byte swap
+
+                vmovdqa  (arg1), \T_key
+                vpxor    \T_key, \XMM1, \XMM1
+                vpxor    \T_key, \XMM2, \XMM2
+                vpxor    \T_key, \XMM3, \XMM3
+                vpxor    \T_key, \XMM4, \XMM4
+                vpxor    \T_key, \XMM5, \XMM5
+                vpxor    \T_key, \XMM6, \XMM6
+                vpxor    \T_key, \XMM7, \XMM7
+                vpxor    \T_key, \XMM8, \XMM8
+
+                i = 1
+                setreg
+.rep    9       # do 9 rounds
+                vmovdqa  16*i(arg1), \T_key
+                vaesenc  \T_key, \XMM1, \XMM1
+                vaesenc  \T_key, \XMM2, \XMM2
+                vaesenc  \T_key, \XMM3, \XMM3
+                vaesenc  \T_key, \XMM4, \XMM4
+                vaesenc  \T_key, \XMM5, \XMM5
+                vaesenc  \T_key, \XMM6, \XMM6
+                vaesenc  \T_key, \XMM7, \XMM7
+                vaesenc  \T_key, \XMM8, \XMM8
+                i = (i+1)
+                setreg
+.endr
+
+
+                vmovdqa  16*i(arg1), \T_key
+                vaesenclast  \T_key, \XMM1, \XMM1
+                vaesenclast  \T_key, \XMM2, \XMM2
+                vaesenclast  \T_key, \XMM3, \XMM3
+                vaesenclast  \T_key, \XMM4, \XMM4
+                vaesenclast  \T_key, \XMM5, \XMM5
+                vaesenclast  \T_key, \XMM6, \XMM6
+                vaesenclast  \T_key, \XMM7, \XMM7
+                vaesenclast  \T_key, \XMM8, \XMM8
+
+                vmovdqu  (arg3, %r11), \T1
+                vpxor    \T1, \XMM1, \XMM1
+                vmovdqu  \XMM1, (arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM1
+                .endif
+
+                vmovdqu  16*1(arg3, %r11), \T1
+                vpxor    \T1, \XMM2, \XMM2
+                vmovdqu  \XMM2, 16*1(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM2
+                .endif
+
+                vmovdqu  16*2(arg3, %r11), \T1
+                vpxor    \T1, \XMM3, \XMM3
+                vmovdqu  \XMM3, 16*2(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM3
+                .endif
+
+                vmovdqu  16*3(arg3, %r11), \T1
+                vpxor    \T1, \XMM4, \XMM4
+                vmovdqu  \XMM4, 16*3(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM4
+                .endif
+
+                vmovdqu  16*4(arg3, %r11), \T1
+                vpxor    \T1, \XMM5, \XMM5
+                vmovdqu  \XMM5, 16*4(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM5
+                .endif
+
+                vmovdqu  16*5(arg3, %r11), \T1
+                vpxor    \T1, \XMM6, \XMM6
+                vmovdqu  \XMM6, 16*5(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM6
+                .endif
+
+                vmovdqu  16*6(arg3, %r11), \T1
+                vpxor    \T1, \XMM7, \XMM7
+                vmovdqu  \XMM7, 16*6(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM7
+                .endif
+
+                vmovdqu  16*7(arg3, %r11), \T1
+                vpxor    \T1, \XMM8, \XMM8
+                vmovdqu  \XMM8, 16*7(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM8
+                .endif
+
+                add     $128, %r11
+
+                vpshufb  SHUF_MASK(%rip), \XMM1, \XMM1     # perform a 16Byte swap
+                vpxor    TMP1(%rsp), \XMM1, \XMM1          # combine GHASHed value with the corresponding ciphertext
+                vpshufb  SHUF_MASK(%rip), \XMM2, \XMM2     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM3, \XMM3     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM4, \XMM4     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM5, \XMM5     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM6, \XMM6     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM7, \XMM7     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM8, \XMM8     # perform a 16Byte swap
+
+###############################################################################
+
+_initial_blocks_done\@:
+
+.endm
+
+# encrypt 8 blocks at a time
+# ghash the 8 previously encrypted ciphertext blocks
+# arg1, arg2, arg3 are used as pointers only, not modified
+# r11 is the data offset value
+.macro GHASH_8_ENCRYPT_8_PARALLEL_AVX T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC
+
+        vmovdqa \XMM1, \T2
+        vmovdqa \XMM2, TMP2(%rsp)
+        vmovdqa \XMM3, TMP3(%rsp)
+        vmovdqa \XMM4, TMP4(%rsp)
+        vmovdqa \XMM5, TMP5(%rsp)
+        vmovdqa \XMM6, TMP6(%rsp)
+        vmovdqa \XMM7, TMP7(%rsp)
+        vmovdqa \XMM8, TMP8(%rsp)
+
+.if \loop_idx == in_order
+                vpaddd  ONE(%rip), \CTR, \XMM1           # INCR CNT
+                vpaddd  ONE(%rip), \XMM1, \XMM2
+                vpaddd  ONE(%rip), \XMM2, \XMM3
+                vpaddd  ONE(%rip), \XMM3, \XMM4
+                vpaddd  ONE(%rip), \XMM4, \XMM5
+                vpaddd  ONE(%rip), \XMM5, \XMM6
+                vpaddd  ONE(%rip), \XMM6, \XMM7
+                vpaddd  ONE(%rip), \XMM7, \XMM8
+                vmovdqa \XMM8, \CTR
+
+                vpshufb SHUF_MASK(%rip), \XMM1, \XMM1    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM2, \XMM2    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM3, \XMM3    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM4, \XMM4    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM5, \XMM5    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM6, \XMM6    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM7, \XMM7    # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM8, \XMM8    # perform a 16Byte swap
+.else
+                vpaddd  ONEf(%rip), \CTR, \XMM1           # INCR CNT
+                vpaddd  ONEf(%rip), \XMM1, \XMM2
+                vpaddd  ONEf(%rip), \XMM2, \XMM3
+                vpaddd  ONEf(%rip), \XMM3, \XMM4
+                vpaddd  ONEf(%rip), \XMM4, \XMM5
+                vpaddd  ONEf(%rip), \XMM5, \XMM6
+                vpaddd  ONEf(%rip), \XMM6, \XMM7
+                vpaddd  ONEf(%rip), \XMM7, \XMM8
+                vmovdqa \XMM8, \CTR
+.endif
+
+
+        #######################################################################
+
+                vmovdqu (arg1), \T1
+                vpxor   \T1, \XMM1, \XMM1
+                vpxor   \T1, \XMM2, \XMM2
+                vpxor   \T1, \XMM3, \XMM3
+                vpxor   \T1, \XMM4, \XMM4
+                vpxor   \T1, \XMM5, \XMM5
+                vpxor   \T1, \XMM6, \XMM6
+                vpxor   \T1, \XMM7, \XMM7
+                vpxor   \T1, \XMM8, \XMM8
+
+        #######################################################################
+
+
+
+
+
+                vmovdqu 16*1(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+                vmovdqu 16*2(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+
+        #######################################################################
+
+        vmovdqa         HashKey_8(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T2, \T4             # T4 = a1*b1
+        vpclmulqdq      $0x00, \T5, \T2, \T7             # T7 = a0*b0
+
+        vpshufd         $0b01001110, \T2, \T6
+        vpxor           \T2, \T6, \T6
+
+        vmovdqa         HashKey_8_k(arg1), \T5
+        vpclmulqdq      $0x00, \T5, \T6, \T6
+
+                vmovdqu 16*3(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP2(%rsp), \T1
+        vmovdqa         HashKey_7(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_7_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*4(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        #######################################################################
+
+        vmovdqa         TMP3(%rsp), \T1
+        vmovdqa         HashKey_6(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_6_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*5(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP4(%rsp), \T1
+        vmovdqa         HashKey_5(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_5_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*6(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+
+        vmovdqa         TMP5(%rsp), \T1
+        vmovdqa         HashKey_4(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_4_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*7(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP6(%rsp), \T1
+        vmovdqa         HashKey_3(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_3_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+
+                vmovdqu 16*8(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP7(%rsp), \T1
+        vmovdqa         HashKey_2(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_2_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+        #######################################################################
+
+                vmovdqu 16*9(arg1), \T5
+                vaesenc \T5, \XMM1, \XMM1
+                vaesenc \T5, \XMM2, \XMM2
+                vaesenc \T5, \XMM3, \XMM3
+                vaesenc \T5, \XMM4, \XMM4
+                vaesenc \T5, \XMM5, \XMM5
+                vaesenc \T5, \XMM6, \XMM6
+                vaesenc \T5, \XMM7, \XMM7
+                vaesenc \T5, \XMM8, \XMM8
+
+        vmovdqa         TMP8(%rsp), \T1
+        vmovdqa         HashKey(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpshufd         $0b01001110, \T1, \T3
+        vpxor           \T1, \T3, \T3
+        vmovdqa         HashKey_k(arg1), \T5
+        vpclmulqdq      $0x10, \T5, \T3, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpxor           \T4, \T6, \T6
+        vpxor           \T7, \T6, \T6
+
+                vmovdqu 16*10(arg1), \T5
+
+        i = 0
+        j = 1
+        setreg
+.rep 8
+                vpxor   16*i(arg3, %r11), \T5, \T2
+                .if \ENC_DEC == ENC
+                vaesenclast     \T2, reg_j, reg_j
+                .else
+                vaesenclast     \T2, reg_j, \T3
+                vmovdqu 16*i(arg3, %r11), reg_j
+                vmovdqu \T3, 16*i(arg2, %r11)
+                .endif
+        i = (i+1)
+        j = (j+1)
+        setreg
+.endr
+        #######################################################################
+
+
+        vpslldq $8, \T6, \T3                            # shift-L T3 2 DWs
+        vpsrldq $8, \T6, \T6                            # shift-R T2 2 DWs
+        vpxor   \T3, \T7, \T7
+        vpxor   \T4, \T6, \T6                           # accumulate the results in T6:T7
+
+
+
+        #######################################################################
+        #first phase of the reduction
+        #######################################################################
+        vpslld  $31, \T7, \T2                           # packed right shifting << 31
+        vpslld  $30, \T7, \T3                           # packed right shifting shift << 30
+        vpslld  $25, \T7, \T4                           # packed right shifting shift << 25
+
+        vpxor   \T3, \T2, \T2                           # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpsrldq $4, \T2, \T1                            # shift-R T1 1 DW
+
+        vpslldq $12, \T2, \T2                           # shift-L T2 3 DWs
+        vpxor   \T2, \T7, \T7                           # first phase of the reduction complete
+        #######################################################################
+                .if \ENC_DEC == ENC
+                vmovdqu  \XMM1, 16*0(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM2, 16*1(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM3, 16*2(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM4, 16*3(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM5, 16*4(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM6, 16*5(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM7, 16*6(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM8, 16*7(arg2,%r11)         # Write to the Ciphertext buffer
+                .endif
+
+        #######################################################################
+        #second phase of the reduction
+        vpsrld  $1, \T7, \T2                            # packed left shifting >> 1
+        vpsrld  $2, \T7, \T3                            # packed left shifting >> 2
+        vpsrld  $7, \T7, \T4                            # packed left shifting >> 7
+        vpxor   \T3, \T2, \T2                           # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpxor   \T1, \T2, \T2
+        vpxor   \T2, \T7, \T7
+        vpxor   \T7, \T6, \T6                           # the result is in T6
+        #######################################################################
+
+                vpshufb SHUF_MASK(%rip), \XMM1, \XMM1   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM2, \XMM2   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM3, \XMM3   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM4, \XMM4   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM5, \XMM5   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM6, \XMM6   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM7, \XMM7   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM8, \XMM8   # perform a 16Byte swap
+
+
+        vpxor   \T6, \XMM1, \XMM1
+
+
+
+.endm
+
+
+# GHASH the last 4 ciphertext blocks.
+.macro  GHASH_LAST_8_AVX T1 T2 T3 T4 T5 T6 T7 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8
+
+        ## Karatsuba Method
+
+
+        vpshufd         $0b01001110, \XMM1, \T2
+        vpxor           \XMM1, \T2, \T2
+        vmovdqa         HashKey_8(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM1, \T6
+        vpclmulqdq      $0x00, \T5, \XMM1, \T7
+
+        vmovdqa         HashKey_8_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM2, \T2
+        vpxor           \XMM2, \T2, \T2
+        vmovdqa         HashKey_7(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM2, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM2, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_7_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM3, \T2
+        vpxor           \XMM3, \T2, \T2
+        vmovdqa         HashKey_6(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM3, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM3, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_6_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM4, \T2
+        vpxor           \XMM4, \T2, \T2
+        vmovdqa         HashKey_5(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM4, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM4, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_5_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM5, \T2
+        vpxor           \XMM5, \T2, \T2
+        vmovdqa         HashKey_4(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM5, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM5, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_4_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM6, \T2
+        vpxor           \XMM6, \T2, \T2
+        vmovdqa         HashKey_3(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM6, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM6, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_3_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM7, \T2
+        vpxor           \XMM7, \T2, \T2
+        vmovdqa         HashKey_2(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM7, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM7, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_2_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vpshufd         $0b01001110, \XMM8, \T2
+        vpxor           \XMM8, \T2, \T2
+        vmovdqa         HashKey(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \XMM8, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM8, \T4
+        vpxor           \T4, \T7, \T7
+
+        vmovdqa         HashKey_k(arg1), \T3
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+        vpxor           \T6, \XMM1, \XMM1
+        vpxor           \T7, \XMM1, \T2
+
+
+
+
+        vpslldq $8, \T2, \T4
+        vpsrldq $8, \T2, \T2
+
+        vpxor   \T4, \T7, \T7
+        vpxor   \T2, \T6, \T6   # <T6:T7> holds the result of
+                                # the accumulated carry-less multiplications
+
+        #######################################################################
+        #first phase of the reduction
+        vpslld  $31, \T7, \T2   # packed right shifting << 31
+        vpslld  $30, \T7, \T3   # packed right shifting shift << 30
+        vpslld  $25, \T7, \T4   # packed right shifting shift << 25
+
+        vpxor   \T3, \T2, \T2   # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpsrldq $4, \T2, \T1    # shift-R T1 1 DW
+
+        vpslldq $12, \T2, \T2   # shift-L T2 3 DWs
+        vpxor   \T2, \T7, \T7   # first phase of the reduction complete
+        #######################################################################
+
+
+        #second phase of the reduction
+        vpsrld  $1, \T7, \T2    # packed left shifting >> 1
+        vpsrld  $2, \T7, \T3    # packed left shifting >> 2
+        vpsrld  $7, \T7, \T4    # packed left shifting >> 7
+        vpxor   \T3, \T2, \T2   # xor the shifted versions
+        vpxor   \T4, \T2, \T2
+
+        vpxor   \T1, \T2, \T2
+        vpxor   \T2, \T7, \T7
+        vpxor   \T7, \T6, \T6   # the result is in T6
+
+.endm
+
+
+# combined for GCM encrypt and decrypt functions
+# clobbering all xmm registers
+# clobbering r10, r11, r12, r13, r14, r15
+.macro  GCM_ENC_DEC_AVX     ENC_DEC
+
+        #the number of pushes must equal STACK_OFFSET
+        push    %r12
+        push    %r13
+        push    %r14
+        push    %r15
+
+        mov     %rsp, %r14
+
+
+
+
+        sub     $VARIABLE_OFFSET, %rsp
+        and     $~63, %rsp                  # align rsp to 64 bytes
+
+
+        vmovdqu  HashKey(arg1), %xmm13      # xmm13 = HashKey
+
+        mov     arg4, %r13                  # save the number of bytes of plaintext/ciphertext
+        and     $-16, %r13                  # r13 = r13 - (r13 mod 16)
+
+        mov     %r13, %r12
+        shr     $4, %r12
+        and     $7, %r12
+        jz      _initial_num_blocks_is_0\@
+
+        cmp     $7, %r12
+        je      _initial_num_blocks_is_7\@
+        cmp     $6, %r12
+        je      _initial_num_blocks_is_6\@
+        cmp     $5, %r12
+        je      _initial_num_blocks_is_5\@
+        cmp     $4, %r12
+        je      _initial_num_blocks_is_4\@
+        cmp     $3, %r12
+        je      _initial_num_blocks_is_3\@
+        cmp     $2, %r12
+        je      _initial_num_blocks_is_2\@
+
+        jmp     _initial_num_blocks_is_1\@
+
+_initial_num_blocks_is_7\@:
+        INITIAL_BLOCKS_AVX  7, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*7, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_6\@:
+        INITIAL_BLOCKS_AVX  6, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*6, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_5\@:
+        INITIAL_BLOCKS_AVX  5, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*5, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_4\@:
+        INITIAL_BLOCKS_AVX  4, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*4, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_3\@:
+        INITIAL_BLOCKS_AVX  3, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*3, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_2\@:
+        INITIAL_BLOCKS_AVX  2, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*2, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_1\@:
+        INITIAL_BLOCKS_AVX  1, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*1, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_0\@:
+        INITIAL_BLOCKS_AVX  0, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+
+
+_initial_blocks_encrypted\@:
+        cmp     $0, %r13
+        je      _zero_cipher_left\@
+
+        sub     $128, %r13
+        je      _eight_cipher_left\@
+
+
+
+
+        vmovd   %xmm9, %r15d
+        and     $255, %r15d
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+
+
+_encrypt_by_8_new\@:
+        cmp     $(255-8), %r15d
+        jg      _encrypt_by_8\@
+
+
+
+        add     $8, %r15b
+        GHASH_8_ENCRYPT_8_PARALLEL_AVX      %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, out_order, \ENC_DEC
+        add     $128, %r11
+        sub     $128, %r13
+        jne     _encrypt_by_8_new\@
+
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        jmp     _eight_cipher_left\@
+
+_encrypt_by_8\@:
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        add     $8, %r15b
+        GHASH_8_ENCRYPT_8_PARALLEL_AVX      %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, in_order, \ENC_DEC
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        add     $128, %r11
+        sub     $128, %r13
+        jne     _encrypt_by_8_new\@
+
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+
+
+
+
+_eight_cipher_left\@:
+        GHASH_LAST_8_AVX    %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm15, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8
+
+
+_zero_cipher_left\@:
+        cmp     $16, arg4
+        jl      _only_less_than_16\@
+
+        mov     arg4, %r13
+        and     $15, %r13                            # r13 = (arg4 mod 16)
+
+        je      _multiple_of_16_bytes\@
+
+        # handle the last <16 Byte block seperately
+
+
+        vpaddd   ONE(%rip), %xmm9, %xmm9             # INCR CNT to get Yn
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Yn)
+
+        sub     $16, %r11
+        add     %r13, %r11
+        vmovdqu (arg3, %r11), %xmm1                  # receive the last <16 Byte block
+
+        lea     SHIFT_MASK+16(%rip), %r12
+        sub     %r13, %r12                           # adjust the shuffle mask pointer to be
+                                                     # able to shift 16-r13 bytes (r13 is the
+                                                     # number of bytes in plaintext mod 16)
+        vmovdqu (%r12), %xmm2                        # get the appropriate shuffle mask
+        vpshufb %xmm2, %xmm1, %xmm1                  # shift right 16-r13 bytes
+        jmp     _final_ghash_mul\@
+
+_only_less_than_16\@:
+        # check for 0 length
+        mov     arg4, %r13
+        and     $15, %r13                            # r13 = (arg4 mod 16)
+
+        je      _multiple_of_16_bytes\@
+
+        # handle the last <16 Byte block seperately
+
+
+        vpaddd  ONE(%rip), %xmm9, %xmm9              # INCR CNT to get Yn
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Yn)
+
+
+        lea     SHIFT_MASK+16(%rip), %r12
+        sub     %r13, %r12                           # adjust the shuffle mask pointer to be
+                                                     # able to shift 16-r13 bytes (r13 is the
+                                                     # number of bytes in plaintext mod 16)
+
+_get_last_16_byte_loop\@:
+        movb    (arg3, %r11),  %al
+        movb    %al,  TMP1 (%rsp , %r11)
+        add     $1, %r11
+        cmp     %r13,  %r11
+        jne     _get_last_16_byte_loop\@
+
+        vmovdqu  TMP1(%rsp), %xmm1
+
+        sub     $16, %r11
+
+_final_ghash_mul\@:
+        .if  \ENC_DEC ==  DEC
+        vmovdqa %xmm1, %xmm2
+        vpxor   %xmm1, %xmm9, %xmm9                  # Plaintext XOR E(K, Yn)
+        vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1        # get the appropriate mask to
+                                                     # mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm9, %xmm9                  # mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm2, %xmm2
+        vpshufb SHUF_MASK(%rip), %xmm2, %xmm2
+        vpxor   %xmm2, %xmm14, %xmm14
+        #GHASH computation for the last <16 Byte block
+        GHASH_MUL_AVX       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
+        sub     %r13, %r11
+        add     $16, %r11
+        .else
+        vpxor   %xmm1, %xmm9, %xmm9                  # Plaintext XOR E(K, Yn)
+        vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1        # get the appropriate mask to
+                                                     # mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm9, %xmm9                  # mask out top 16-r13 bytes of xmm9
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        vpxor   %xmm9, %xmm14, %xmm14
+        #GHASH computation for the last <16 Byte block
+        GHASH_MUL_AVX       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
+        sub     %r13, %r11
+        add     $16, %r11
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9        # shuffle xmm9 back to output as ciphertext
+        .endif
+
+
+        #############################
+        # output r13 Bytes
+        vmovq   %xmm9, %rax
+        cmp     $8, %r13
+        jle     _less_than_8_bytes_left\@
+
+        mov     %rax, (arg2 , %r11)
+        add     $8, %r11
+        vpsrldq $8, %xmm9, %xmm9
+        vmovq   %xmm9, %rax
+        sub     $8, %r13
+
+_less_than_8_bytes_left\@:
+        movb    %al, (arg2 , %r11)
+        add     $1, %r11
+        shr     $8, %rax
+        sub     $1, %r13
+        jne     _less_than_8_bytes_left\@
+        #############################
+
+_multiple_of_16_bytes\@:
+        mov     arg7, %r12                           # r12 = aadLen (number of bytes)
+        shl     $3, %r12                             # convert into number of bits
+        vmovd   %r12d, %xmm15                        # len(A) in xmm15
+
+        shl     $3, arg4                             # len(C) in bits  (*128)
+        vmovq   arg4, %xmm1
+        vpslldq $8, %xmm15, %xmm15                   # xmm15 = len(A)|| 0x0000000000000000
+        vpxor   %xmm1, %xmm15, %xmm15                # xmm15 = len(A)||len(C)
+
+        vpxor   %xmm15, %xmm14, %xmm14
+        GHASH_MUL_AVX       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6    # final GHASH computation
+        vpshufb SHUF_MASK(%rip), %xmm14, %xmm14      # perform a 16Byte swap
+
+        mov     arg5, %rax                           # rax = *Y0
+        vmovdqu (%rax), %xmm9                        # xmm9 = Y0
+
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Y0)
+
+        vpxor   %xmm14, %xmm9, %xmm9
+
+
+
+_return_T\@:
+        mov     arg8, %r10              # r10 = authTag
+        mov     arg9, %r11              # r11 = auth_tag_len
+
+        cmp     $16, %r11
+        je      _T_16\@
+
+        cmp     $12, %r11
+        je      _T_12\@
+
+_T_8\@:
+        vmovq   %xmm9, %rax
+        mov     %rax, (%r10)
+        jmp     _return_T_done\@
+_T_12\@:
+        vmovq   %xmm9, %rax
+        mov     %rax, (%r10)
+        vpsrldq $8, %xmm9, %xmm9
+        vmovd   %xmm9, %eax
+        mov     %eax, 8(%r10)
+        jmp     _return_T_done\@
+
+_T_16\@:
+        vmovdqu %xmm9, (%r10)
+
+_return_T_done\@:
+        mov     %r14, %rsp
+
+        pop     %r15
+        pop     %r14
+        pop     %r13
+        pop     %r12
+.endm
+
+
+#############################################################
+#void   aesni_gcm_precomp_avx_gen2
+#        (gcm_data     *my_ctx_data,
+#        u8     *hash_subkey)# /* H, the Hash sub key input. Data starts on a 16-byte boundary. */
+#############################################################
+ENTRY(aesni_gcm_precomp_avx_gen2)
+        #the number of pushes must equal STACK_OFFSET
+        push    %r12
+        push    %r13
+        push    %r14
+        push    %r15
+
+        mov     %rsp, %r14
+
+
+
+        sub     $VARIABLE_OFFSET, %rsp
+        and     $~63, %rsp                  # align rsp to 64 bytes
+
+        vmovdqu  (arg2), %xmm6              # xmm6 = HashKey
+
+        vpshufb  SHUF_MASK(%rip), %xmm6, %xmm6
+        ###############  PRECOMPUTATION of HashKey<<1 mod poly from the HashKey
+        vmovdqa  %xmm6, %xmm2
+        vpsllq   $1, %xmm6, %xmm6
+        vpsrlq   $63, %xmm2, %xmm2
+        vmovdqa  %xmm2, %xmm1
+        vpslldq  $8, %xmm2, %xmm2
+        vpsrldq  $8, %xmm1, %xmm1
+        vpor     %xmm2, %xmm6, %xmm6
+        #reduction
+        vpshufd  $0b00100100, %xmm1, %xmm2
+        vpcmpeqd TWOONE(%rip), %xmm2, %xmm2
+        vpand    POLY(%rip), %xmm2, %xmm2
+        vpxor    %xmm2, %xmm6, %xmm6        # xmm6 holds the HashKey<<1 mod poly
+        #######################################################################
+        vmovdqa  %xmm6, HashKey(arg1)       # store HashKey<<1 mod poly
+
+
+        PRECOMPUTE_AVX  %xmm6, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5
+
+        mov     %r14, %rsp
+
+        pop     %r15
+        pop     %r14
+        pop     %r13
+        pop     %r12
+        ret
+ENDPROC(aesni_gcm_precomp_avx_gen2)
+
+###############################################################################
+#void   aesni_gcm_enc_avx_gen2(
+#        gcm_data        *my_ctx_data,     /* aligned to 16 Bytes */
+#        u8      *out, /* Ciphertext output. Encrypt in-place is allowed.  */
+#        const   u8 *in, /* Plaintext input */
+#        u64     plaintext_len, /* Length of data in Bytes for encryption. */
+#        u8      *iv, /* Pre-counter block j0: 4 byte salt
+#                       (from Security Association) concatenated with 8 byte
+#                       Initialisation Vector (from IPSec ESP Payload)
+#                       concatenated with 0x00000001. 16-byte aligned pointer. */
+#        const   u8 *aad, /* Additional Authentication Data (AAD)*/
+#        u64     aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */
+#        u8      *auth_tag, /* Authenticated Tag output. */
+#        u64     auth_tag_len)# /* Authenticated Tag Length in bytes.
+#                               Valid values are 16 (most likely), 12 or 8. */
+###############################################################################
+ENTRY(aesni_gcm_enc_avx_gen2)
+        GCM_ENC_DEC_AVX     ENC
+        ret
+ENDPROC(aesni_gcm_enc_avx_gen2)
+
+###############################################################################
+#void   aesni_gcm_dec_avx_gen2(
+#        gcm_data        *my_ctx_data,     /* aligned to 16 Bytes */
+#        u8      *out, /* Plaintext output. Decrypt in-place is allowed.  */
+#        const   u8 *in, /* Ciphertext input */
+#        u64     plaintext_len, /* Length of data in Bytes for encryption. */
+#        u8      *iv, /* Pre-counter block j0: 4 byte salt
+#                       (from Security Association) concatenated with 8 byte
+#                       Initialisation Vector (from IPSec ESP Payload)
+#                       concatenated with 0x00000001. 16-byte aligned pointer. */
+#        const   u8 *aad, /* Additional Authentication Data (AAD)*/
+#        u64     aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */
+#        u8      *auth_tag, /* Authenticated Tag output. */
+#        u64     auth_tag_len)# /* Authenticated Tag Length in bytes.
+#                               Valid values are 16 (most likely), 12 or 8. */
+###############################################################################
+ENTRY(aesni_gcm_dec_avx_gen2)
+        GCM_ENC_DEC_AVX     DEC
+        ret
+ENDPROC(aesni_gcm_dec_avx_gen2)
+#endif /* CONFIG_AS_AVX */
+
+#ifdef CONFIG_AS_AVX2
+###############################################################################
+# GHASH_MUL MACRO to implement: Data*HashKey mod (128,127,126,121,0)
+# Input: A and B (128-bits each, bit-reflected)
+# Output: C = A*B*x mod poly, (i.e. >>1 )
+# To compute GH = GH*HashKey mod poly, give HK = HashKey<<1 mod poly as input
+# GH = GH * HK * x mod poly which is equivalent to GH*HashKey mod poly.
+###############################################################################
+.macro  GHASH_MUL_AVX2 GH HK T1 T2 T3 T4 T5
+
+        vpclmulqdq      $0x11,\HK,\GH,\T1      # T1 = a1*b1
+        vpclmulqdq      $0x00,\HK,\GH,\T2      # T2 = a0*b0
+        vpclmulqdq      $0x01,\HK,\GH,\T3      # T3 = a1*b0
+        vpclmulqdq      $0x10,\HK,\GH,\GH      # GH = a0*b1
+        vpxor           \T3, \GH, \GH
+
+
+        vpsrldq         $8 , \GH, \T3          # shift-R GH 2 DWs
+        vpslldq         $8 , \GH, \GH          # shift-L GH 2 DWs
+
+        vpxor           \T3, \T1, \T1
+        vpxor           \T2, \GH, \GH
+
+        #######################################################################
+        #first phase of the reduction
+        vmovdqa         POLY2(%rip), \T3
+
+        vpclmulqdq      $0x01, \GH, \T3, \T2
+        vpslldq         $8, \T2, \T2           # shift-L T2 2 DWs
+
+        vpxor           \T2, \GH, \GH          # first phase of the reduction complete
+        #######################################################################
+        #second phase of the reduction
+        vpclmulqdq      $0x00, \GH, \T3, \T2
+        vpsrldq         $4, \T2, \T2           # shift-R T2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R)
+
+        vpclmulqdq      $0x10, \GH, \T3, \GH
+        vpslldq         $4, \GH, \GH           # shift-L GH 1 DW (Shift-L 1-DW to obtain result with no shifts)
+
+        vpxor           \T2, \GH, \GH          # second phase of the reduction complete
+        #######################################################################
+        vpxor           \T1, \GH, \GH          # the result is in GH
+
+
+.endm
+
+.macro PRECOMPUTE_AVX2 HK T1 T2 T3 T4 T5 T6
+
+        # Haskey_i_k holds XORed values of the low and high parts of the Haskey_i
+        vmovdqa  \HK, \T5
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^2<<1 mod poly
+        vmovdqa  \T5, HashKey_2(arg1)                       #  [HashKey_2] = HashKey^2<<1 mod poly
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^3<<1 mod poly
+        vmovdqa  \T5, HashKey_3(arg1)
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^4<<1 mod poly
+        vmovdqa  \T5, HashKey_4(arg1)
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^5<<1 mod poly
+        vmovdqa  \T5, HashKey_5(arg1)
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^6<<1 mod poly
+        vmovdqa  \T5, HashKey_6(arg1)
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^7<<1 mod poly
+        vmovdqa  \T5, HashKey_7(arg1)
+
+        GHASH_MUL_AVX2 \T5, \HK, \T1, \T3, \T4, \T6, \T2    #  T5 = HashKey^8<<1 mod poly
+        vmovdqa  \T5, HashKey_8(arg1)
+
+.endm
+
+
+## if a = number of total plaintext bytes
+## b = floor(a/16)
+## num_initial_blocks = b mod 4#
+## encrypt the initial num_initial_blocks blocks and apply ghash on the ciphertext
+## r10, r11, r12, rax are clobbered
+## arg1, arg2, arg3, r14 are used as a pointer only, not modified
+
+.macro INITIAL_BLOCKS_AVX2 num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC VER
+        i = (8-\num_initial_blocks)
+        setreg
+
+        mov     arg6, %r10                       # r10 = AAD
+        mov     arg7, %r12                       # r12 = aadLen
+
+
+        mov     %r12, %r11
+
+        vpxor   reg_i, reg_i, reg_i
+_get_AAD_loop\@:
+        vmovd   (%r10), \T1
+        vpslldq $12, \T1, \T1
+        vpsrldq $4, reg_i, reg_i
+        vpxor   \T1, reg_i, reg_i
+
+        add     $4, %r10
+        sub     $4, %r12
+        jg      _get_AAD_loop\@
+
+
+        cmp     $16, %r11
+        je      _get_AAD_loop2_done\@
+        mov     $16, %r12
+
+_get_AAD_loop2\@:
+        vpsrldq $4, reg_i, reg_i
+        sub     $4, %r12
+        cmp     %r11, %r12
+        jg      _get_AAD_loop2\@
+
+_get_AAD_loop2_done\@:
+
+        #byte-reflect the AAD data
+        vpshufb SHUF_MASK(%rip), reg_i, reg_i
+
+        # initialize the data pointer offset as zero
+        xor     %r11, %r11
+
+        # start AES for num_initial_blocks blocks
+        mov     arg5, %rax                     # rax = *Y0
+        vmovdqu (%rax), \CTR                   # CTR = Y0
+        vpshufb SHUF_MASK(%rip), \CTR, \CTR
+
+
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vpaddd  ONE(%rip), \CTR, \CTR   # INCR Y0
+                vmovdqa \CTR, reg_i
+                vpshufb SHUF_MASK(%rip), reg_i, reg_i     # perform a 16Byte swap
+        i = (i+1)
+        setreg
+.endr
+
+        vmovdqa  (arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vpxor   \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        j = 1
+        setreg
+.rep 9
+        vmovdqa  16*j(arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+        vaesenc \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        j = (j+1)
+        setreg
+.endr
+
+
+        vmovdqa  16*10(arg1), \T_key
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+        vaesenclast      \T_key, reg_i, reg_i
+        i = (i+1)
+        setreg
+.endr
+
+        i = (9-\num_initial_blocks)
+        setreg
+.rep \num_initial_blocks
+                vmovdqu (arg3, %r11), \T1
+                vpxor   \T1, reg_i, reg_i
+                vmovdqu reg_i, (arg2 , %r11)           # write back ciphertext for
+                                                       # num_initial_blocks blocks
+                add     $16, %r11
+.if  \ENC_DEC == DEC
+                vmovdqa \T1, reg_i
+.endif
+                vpshufb SHUF_MASK(%rip), reg_i, reg_i  # prepare ciphertext for GHASH computations
+        i = (i+1)
+        setreg
+.endr
+
+
+        i = (8-\num_initial_blocks)
+        j = (9-\num_initial_blocks)
+        setreg
+        GHASH_MUL_AVX2       reg_i, \T2, \T1, \T3, \T4, \T5, \T6
+
+.rep \num_initial_blocks
+        vpxor    reg_i, reg_j, reg_j
+        GHASH_MUL_AVX2       reg_j, \T2, \T1, \T3, \T4, \T5, \T6  # apply GHASH on num_initial_blocks blocks
+        i = (i+1)
+        j = (j+1)
+        setreg
+.endr
+        # XMM8 has the combined result here
+
+        vmovdqa  \XMM8, TMP1(%rsp)
+        vmovdqa  \XMM8, \T3
+
+        cmp     $128, %r13
+        jl      _initial_blocks_done\@                  # no need for precomputed constants
+
+###############################################################################
+# Haskey_i_k holds XORed values of the low and high parts of the Haskey_i
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM1
+                vpshufb  SHUF_MASK(%rip), \XMM1, \XMM1  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM2
+                vpshufb  SHUF_MASK(%rip), \XMM2, \XMM2  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM3
+                vpshufb  SHUF_MASK(%rip), \XMM3, \XMM3  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM4
+                vpshufb  SHUF_MASK(%rip), \XMM4, \XMM4  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM5
+                vpshufb  SHUF_MASK(%rip), \XMM5, \XMM5  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM6
+                vpshufb  SHUF_MASK(%rip), \XMM6, \XMM6  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM7
+                vpshufb  SHUF_MASK(%rip), \XMM7, \XMM7  # perform a 16Byte swap
+
+                vpaddd   ONE(%rip), \CTR, \CTR          # INCR Y0
+                vmovdqa  \CTR, \XMM8
+                vpshufb  SHUF_MASK(%rip), \XMM8, \XMM8  # perform a 16Byte swap
+
+                vmovdqa  (arg1), \T_key
+                vpxor    \T_key, \XMM1, \XMM1
+                vpxor    \T_key, \XMM2, \XMM2
+                vpxor    \T_key, \XMM3, \XMM3
+                vpxor    \T_key, \XMM4, \XMM4
+                vpxor    \T_key, \XMM5, \XMM5
+                vpxor    \T_key, \XMM6, \XMM6
+                vpxor    \T_key, \XMM7, \XMM7
+                vpxor    \T_key, \XMM8, \XMM8
+
+                i = 1
+                setreg
+.rep    9       # do 9 rounds
+                vmovdqa  16*i(arg1), \T_key
+                vaesenc  \T_key, \XMM1, \XMM1
+                vaesenc  \T_key, \XMM2, \XMM2
+                vaesenc  \T_key, \XMM3, \XMM3
+                vaesenc  \T_key, \XMM4, \XMM4
+                vaesenc  \T_key, \XMM5, \XMM5
+                vaesenc  \T_key, \XMM6, \XMM6
+                vaesenc  \T_key, \XMM7, \XMM7
+                vaesenc  \T_key, \XMM8, \XMM8
+                i = (i+1)
+                setreg
+.endr
+
+
+                vmovdqa  16*i(arg1), \T_key
+                vaesenclast  \T_key, \XMM1, \XMM1
+                vaesenclast  \T_key, \XMM2, \XMM2
+                vaesenclast  \T_key, \XMM3, \XMM3
+                vaesenclast  \T_key, \XMM4, \XMM4
+                vaesenclast  \T_key, \XMM5, \XMM5
+                vaesenclast  \T_key, \XMM6, \XMM6
+                vaesenclast  \T_key, \XMM7, \XMM7
+                vaesenclast  \T_key, \XMM8, \XMM8
+
+                vmovdqu  (arg3, %r11), \T1
+                vpxor    \T1, \XMM1, \XMM1
+                vmovdqu  \XMM1, (arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM1
+                .endif
+
+                vmovdqu  16*1(arg3, %r11), \T1
+                vpxor    \T1, \XMM2, \XMM2
+                vmovdqu  \XMM2, 16*1(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM2
+                .endif
+
+                vmovdqu  16*2(arg3, %r11), \T1
+                vpxor    \T1, \XMM3, \XMM3
+                vmovdqu  \XMM3, 16*2(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM3
+                .endif
+
+                vmovdqu  16*3(arg3, %r11), \T1
+                vpxor    \T1, \XMM4, \XMM4
+                vmovdqu  \XMM4, 16*3(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM4
+                .endif
+
+                vmovdqu  16*4(arg3, %r11), \T1
+                vpxor    \T1, \XMM5, \XMM5
+                vmovdqu  \XMM5, 16*4(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM5
+                .endif
+
+                vmovdqu  16*5(arg3, %r11), \T1
+                vpxor    \T1, \XMM6, \XMM6
+                vmovdqu  \XMM6, 16*5(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM6
+                .endif
+
+                vmovdqu  16*6(arg3, %r11), \T1
+                vpxor    \T1, \XMM7, \XMM7
+                vmovdqu  \XMM7, 16*6(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM7
+                .endif
+
+                vmovdqu  16*7(arg3, %r11), \T1
+                vpxor    \T1, \XMM8, \XMM8
+                vmovdqu  \XMM8, 16*7(arg2 , %r11)
+                .if   \ENC_DEC == DEC
+                vmovdqa  \T1, \XMM8
+                .endif
+
+                add     $128, %r11
+
+                vpshufb  SHUF_MASK(%rip), \XMM1, \XMM1     # perform a 16Byte swap
+                vpxor    TMP1(%rsp), \XMM1, \XMM1          # combine GHASHed value with
+                                                           # the corresponding ciphertext
+                vpshufb  SHUF_MASK(%rip), \XMM2, \XMM2     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM3, \XMM3     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM4, \XMM4     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM5, \XMM5     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM6, \XMM6     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM7, \XMM7     # perform a 16Byte swap
+                vpshufb  SHUF_MASK(%rip), \XMM8, \XMM8     # perform a 16Byte swap
+
+###############################################################################
+
+_initial_blocks_done\@:
+
+
+.endm
+
+
+
+# encrypt 8 blocks at a time
+# ghash the 8 previously encrypted ciphertext blocks
+# arg1, arg2, arg3 are used as pointers only, not modified
+# r11 is the data offset value
+.macro GHASH_8_ENCRYPT_8_PARALLEL_AVX2 T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC
+
+        vmovdqa \XMM1, \T2
+        vmovdqa \XMM2, TMP2(%rsp)
+        vmovdqa \XMM3, TMP3(%rsp)
+        vmovdqa \XMM4, TMP4(%rsp)
+        vmovdqa \XMM5, TMP5(%rsp)
+        vmovdqa \XMM6, TMP6(%rsp)
+        vmovdqa \XMM7, TMP7(%rsp)
+        vmovdqa \XMM8, TMP8(%rsp)
+
+.if \loop_idx == in_order
+                vpaddd  ONE(%rip), \CTR, \XMM1            # INCR CNT
+                vpaddd  ONE(%rip), \XMM1, \XMM2
+                vpaddd  ONE(%rip), \XMM2, \XMM3
+                vpaddd  ONE(%rip), \XMM3, \XMM4
+                vpaddd  ONE(%rip), \XMM4, \XMM5
+                vpaddd  ONE(%rip), \XMM5, \XMM6
+                vpaddd  ONE(%rip), \XMM6, \XMM7
+                vpaddd  ONE(%rip), \XMM7, \XMM8
+                vmovdqa \XMM8, \CTR
+
+                vpshufb SHUF_MASK(%rip), \XMM1, \XMM1     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM2, \XMM2     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM3, \XMM3     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM4, \XMM4     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM5, \XMM5     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM6, \XMM6     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM7, \XMM7     # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM8, \XMM8     # perform a 16Byte swap
+.else
+                vpaddd  ONEf(%rip), \CTR, \XMM1            # INCR CNT
+                vpaddd  ONEf(%rip), \XMM1, \XMM2
+                vpaddd  ONEf(%rip), \XMM2, \XMM3
+                vpaddd  ONEf(%rip), \XMM3, \XMM4
+                vpaddd  ONEf(%rip), \XMM4, \XMM5
+                vpaddd  ONEf(%rip), \XMM5, \XMM6
+                vpaddd  ONEf(%rip), \XMM6, \XMM7
+                vpaddd  ONEf(%rip), \XMM7, \XMM8
+                vmovdqa \XMM8, \CTR
+.endif
+
+
+        #######################################################################
+
+                vmovdqu (arg1), \T1
+                vpxor   \T1, \XMM1, \XMM1
+                vpxor   \T1, \XMM2, \XMM2
+                vpxor   \T1, \XMM3, \XMM3
+                vpxor   \T1, \XMM4, \XMM4
+                vpxor   \T1, \XMM5, \XMM5
+                vpxor   \T1, \XMM6, \XMM6
+                vpxor   \T1, \XMM7, \XMM7
+                vpxor   \T1, \XMM8, \XMM8
+
+        #######################################################################
+
+
+
+
+
+                vmovdqu 16*1(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+                vmovdqu 16*2(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+
+        #######################################################################
+
+        vmovdqa         HashKey_8(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T2, \T4              # T4 = a1*b1
+        vpclmulqdq      $0x00, \T5, \T2, \T7              # T7 = a0*b0
+        vpclmulqdq      $0x01, \T5, \T2, \T6              # T6 = a1*b0
+        vpclmulqdq      $0x10, \T5, \T2, \T5              # T5 = a0*b1
+        vpxor           \T5, \T6, \T6
+
+                vmovdqu 16*3(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP2(%rsp), \T1
+        vmovdqa         HashKey_7(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*4(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        #######################################################################
+
+        vmovdqa         TMP3(%rsp), \T1
+        vmovdqa         HashKey_6(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*5(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP4(%rsp), \T1
+        vmovdqa         HashKey_5(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*6(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+
+        vmovdqa         TMP5(%rsp), \T1
+        vmovdqa         HashKey_4(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*7(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP6(%rsp), \T1
+        vmovdqa         HashKey_3(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+                vmovdqu 16*8(arg1), \T1
+                vaesenc \T1, \XMM1, \XMM1
+                vaesenc \T1, \XMM2, \XMM2
+                vaesenc \T1, \XMM3, \XMM3
+                vaesenc \T1, \XMM4, \XMM4
+                vaesenc \T1, \XMM5, \XMM5
+                vaesenc \T1, \XMM6, \XMM6
+                vaesenc \T1, \XMM7, \XMM7
+                vaesenc \T1, \XMM8, \XMM8
+
+        vmovdqa         TMP7(%rsp), \T1
+        vmovdqa         HashKey_2(arg1), \T5
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T4
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+
+        #######################################################################
+
+                vmovdqu 16*9(arg1), \T5
+                vaesenc \T5, \XMM1, \XMM1
+                vaesenc \T5, \XMM2, \XMM2
+                vaesenc \T5, \XMM3, \XMM3
+                vaesenc \T5, \XMM4, \XMM4
+                vaesenc \T5, \XMM5, \XMM5
+                vaesenc \T5, \XMM6, \XMM6
+                vaesenc \T5, \XMM7, \XMM7
+                vaesenc \T5, \XMM8, \XMM8
+
+        vmovdqa         TMP8(%rsp), \T1
+        vmovdqa         HashKey(arg1), \T5
+
+        vpclmulqdq      $0x00, \T5, \T1, \T3
+        vpxor           \T3, \T7, \T7
+
+        vpclmulqdq      $0x01, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x10, \T5, \T1, \T3
+        vpxor           \T3, \T6, \T6
+
+        vpclmulqdq      $0x11, \T5, \T1, \T3
+        vpxor           \T3, \T4, \T1
+
+
+                vmovdqu 16*10(arg1), \T5
+
+        i = 0
+        j = 1
+        setreg
+.rep 8
+                vpxor   16*i(arg3, %r11), \T5, \T2
+                .if \ENC_DEC == ENC
+                vaesenclast     \T2, reg_j, reg_j
+                .else
+                vaesenclast     \T2, reg_j, \T3
+                vmovdqu 16*i(arg3, %r11), reg_j
+                vmovdqu \T3, 16*i(arg2, %r11)
+                .endif
+        i = (i+1)
+        j = (j+1)
+        setreg
+.endr
+        #######################################################################
+
+
+        vpslldq $8, \T6, \T3                            # shift-L T3 2 DWs
+        vpsrldq $8, \T6, \T6                            # shift-R T2 2 DWs
+        vpxor   \T3, \T7, \T7
+        vpxor   \T6, \T1, \T1                           # accumulate the results in T1:T7
+
+
+
+        #######################################################################
+        #first phase of the reduction
+        vmovdqa         POLY2(%rip), \T3
+
+        vpclmulqdq      $0x01, \T7, \T3, \T2
+        vpslldq         $8, \T2, \T2                    # shift-L xmm2 2 DWs
+
+        vpxor           \T2, \T7, \T7                   # first phase of the reduction complete
+        #######################################################################
+                .if \ENC_DEC == ENC
+                vmovdqu  \XMM1, 16*0(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM2, 16*1(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM3, 16*2(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM4, 16*3(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM5, 16*4(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM6, 16*5(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM7, 16*6(arg2,%r11)         # Write to the Ciphertext buffer
+                vmovdqu  \XMM8, 16*7(arg2,%r11)         # Write to the Ciphertext buffer
+                .endif
+
+        #######################################################################
+        #second phase of the reduction
+        vpclmulqdq      $0x00, \T7, \T3, \T2
+        vpsrldq         $4, \T2, \T2                    # shift-R xmm2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R)
+
+        vpclmulqdq      $0x10, \T7, \T3, \T4
+        vpslldq         $4, \T4, \T4                    # shift-L xmm0 1 DW (Shift-L 1-DW to obtain result with no shifts)
+
+        vpxor           \T2, \T4, \T4                   # second phase of the reduction complete
+        #######################################################################
+        vpxor           \T4, \T1, \T1                   # the result is in T1
+
+                vpshufb SHUF_MASK(%rip), \XMM1, \XMM1   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM2, \XMM2   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM3, \XMM3   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM4, \XMM4   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM5, \XMM5   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM6, \XMM6   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM7, \XMM7   # perform a 16Byte swap
+                vpshufb SHUF_MASK(%rip), \XMM8, \XMM8   # perform a 16Byte swap
+
+
+        vpxor   \T1, \XMM1, \XMM1
+
+
+
+.endm
+
+
+# GHASH the last 4 ciphertext blocks.
+.macro  GHASH_LAST_8_AVX2 T1 T2 T3 T4 T5 T6 T7 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8
+
+        ## Karatsuba Method
+
+        vmovdqa         HashKey_8(arg1), \T5
+
+        vpshufd         $0b01001110, \XMM1, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM1, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM1, \T6
+        vpclmulqdq      $0x00, \T5, \XMM1, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_7(arg1), \T5
+        vpshufd         $0b01001110, \XMM2, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM2, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM2, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM2, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_6(arg1), \T5
+        vpshufd         $0b01001110, \XMM3, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM3, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM3, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM3, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_5(arg1), \T5
+        vpshufd         $0b01001110, \XMM4, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM4, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM4, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM4, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_4(arg1), \T5
+        vpshufd         $0b01001110, \XMM5, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM5, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM5, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM5, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_3(arg1), \T5
+        vpshufd         $0b01001110, \XMM6, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM6, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM6, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM6, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey_2(arg1), \T5
+        vpshufd         $0b01001110, \XMM7, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM7, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM7, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM7, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+
+        ######################
+
+        vmovdqa         HashKey(arg1), \T5
+        vpshufd         $0b01001110, \XMM8, \T2
+        vpshufd         $0b01001110, \T5, \T3
+        vpxor           \XMM8, \T2, \T2
+        vpxor           \T5, \T3, \T3
+
+        vpclmulqdq      $0x11, \T5, \XMM8, \T4
+        vpxor           \T4, \T6, \T6
+
+        vpclmulqdq      $0x00, \T5, \XMM8, \T4
+        vpxor           \T4, \T7, \T7
+
+        vpclmulqdq      $0x00, \T3, \T2, \T2
+
+        vpxor           \T2, \XMM1, \XMM1
+        vpxor           \T6, \XMM1, \XMM1
+        vpxor           \T7, \XMM1, \T2
+
+
+
+
+        vpslldq $8, \T2, \T4
+        vpsrldq $8, \T2, \T2
+
+        vpxor   \T4, \T7, \T7
+        vpxor   \T2, \T6, \T6                      # <T6:T7> holds the result of the
+                                                   # accumulated carry-less multiplications
+
+        #######################################################################
+        #first phase of the reduction
+        vmovdqa         POLY2(%rip), \T3
+
+        vpclmulqdq      $0x01, \T7, \T3, \T2
+        vpslldq         $8, \T2, \T2               # shift-L xmm2 2 DWs
+
+        vpxor           \T2, \T7, \T7              # first phase of the reduction complete
+        #######################################################################
+
+
+        #second phase of the reduction
+        vpclmulqdq      $0x00, \T7, \T3, \T2
+        vpsrldq         $4, \T2, \T2               # shift-R T2 1 DW (Shift-R only 1-DW to obtain 2-DWs shift-R)
+
+        vpclmulqdq      $0x10, \T7, \T3, \T4
+        vpslldq         $4, \T4, \T4               # shift-L T4 1 DW (Shift-L 1-DW to obtain result with no shifts)
+
+        vpxor           \T2, \T4, \T4              # second phase of the reduction complete
+        #######################################################################
+        vpxor           \T4, \T6, \T6              # the result is in T6
+.endm
+
+
+
+# combined for GCM encrypt and decrypt functions
+# clobbering all xmm registers
+# clobbering r10, r11, r12, r13, r14, r15
+.macro  GCM_ENC_DEC_AVX2     ENC_DEC
+
+        #the number of pushes must equal STACK_OFFSET
+        push    %r12
+        push    %r13
+        push    %r14
+        push    %r15
+
+        mov     %rsp, %r14
+
+
+
+
+        sub     $VARIABLE_OFFSET, %rsp
+        and     $~63, %rsp                         # align rsp to 64 bytes
+
+
+        vmovdqu  HashKey(arg1), %xmm13             # xmm13 = HashKey
+
+        mov     arg4, %r13                         # save the number of bytes of plaintext/ciphertext
+        and     $-16, %r13                         # r13 = r13 - (r13 mod 16)
+
+        mov     %r13, %r12
+        shr     $4, %r12
+        and     $7, %r12
+        jz      _initial_num_blocks_is_0\@
+
+        cmp     $7, %r12
+        je      _initial_num_blocks_is_7\@
+        cmp     $6, %r12
+        je      _initial_num_blocks_is_6\@
+        cmp     $5, %r12
+        je      _initial_num_blocks_is_5\@
+        cmp     $4, %r12
+        je      _initial_num_blocks_is_4\@
+        cmp     $3, %r12
+        je      _initial_num_blocks_is_3\@
+        cmp     $2, %r12
+        je      _initial_num_blocks_is_2\@
+
+        jmp     _initial_num_blocks_is_1\@
+
+_initial_num_blocks_is_7\@:
+        INITIAL_BLOCKS_AVX2  7, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*7, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_6\@:
+        INITIAL_BLOCKS_AVX2  6, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*6, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_5\@:
+        INITIAL_BLOCKS_AVX2  5, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*5, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_4\@:
+        INITIAL_BLOCKS_AVX2  4, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*4, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_3\@:
+        INITIAL_BLOCKS_AVX2  3, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*3, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_2\@:
+        INITIAL_BLOCKS_AVX2  2, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*2, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_1\@:
+        INITIAL_BLOCKS_AVX2  1, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+        sub     $16*1, %r13
+        jmp     _initial_blocks_encrypted\@
+
+_initial_num_blocks_is_0\@:
+        INITIAL_BLOCKS_AVX2  0, %xmm12, %xmm13, %xmm14, %xmm15, %xmm11, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm10, %xmm0, \ENC_DEC
+
+
+_initial_blocks_encrypted\@:
+        cmp     $0, %r13
+        je      _zero_cipher_left\@
+
+        sub     $128, %r13
+        je      _eight_cipher_left\@
+
+
+
+
+        vmovd   %xmm9, %r15d
+        and     $255, %r15d
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+
+
+_encrypt_by_8_new\@:
+        cmp     $(255-8), %r15d
+        jg      _encrypt_by_8\@
+
+
+
+        add     $8, %r15b
+        GHASH_8_ENCRYPT_8_PARALLEL_AVX2      %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, out_order, \ENC_DEC
+        add     $128, %r11
+        sub     $128, %r13
+        jne     _encrypt_by_8_new\@
+
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        jmp     _eight_cipher_left\@
+
+_encrypt_by_8\@:
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        add     $8, %r15b
+        GHASH_8_ENCRYPT_8_PARALLEL_AVX2      %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm9, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8, %xmm15, in_order, \ENC_DEC
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        add     $128, %r11
+        sub     $128, %r13
+        jne     _encrypt_by_8_new\@
+
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+
+
+
+
+_eight_cipher_left\@:
+        GHASH_LAST_8_AVX2    %xmm0, %xmm10, %xmm11, %xmm12, %xmm13, %xmm14, %xmm15, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7, %xmm8
+
+
+_zero_cipher_left\@:
+        cmp     $16, arg4
+        jl      _only_less_than_16\@
+
+        mov     arg4, %r13
+        and     $15, %r13                            # r13 = (arg4 mod 16)
+
+        je      _multiple_of_16_bytes\@
+
+        # handle the last <16 Byte block seperately
+
+
+        vpaddd   ONE(%rip), %xmm9, %xmm9             # INCR CNT to get Yn
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Yn)
+
+        sub     $16, %r11
+        add     %r13, %r11
+        vmovdqu (arg3, %r11), %xmm1                  # receive the last <16 Byte block
+
+        lea     SHIFT_MASK+16(%rip), %r12
+        sub     %r13, %r12                           # adjust the shuffle mask pointer
+                                                     # to be able to shift 16-r13 bytes
+                                                     # (r13 is the number of bytes in plaintext mod 16)
+        vmovdqu (%r12), %xmm2                        # get the appropriate shuffle mask
+        vpshufb %xmm2, %xmm1, %xmm1                  # shift right 16-r13 bytes
+        jmp     _final_ghash_mul\@
+
+_only_less_than_16\@:
+        # check for 0 length
+        mov     arg4, %r13
+        and     $15, %r13                            # r13 = (arg4 mod 16)
+
+        je      _multiple_of_16_bytes\@
+
+        # handle the last <16 Byte block seperately
+
+
+        vpaddd  ONE(%rip), %xmm9, %xmm9              # INCR CNT to get Yn
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Yn)
+
+
+        lea     SHIFT_MASK+16(%rip), %r12
+        sub     %r13, %r12                           # adjust the shuffle mask pointer to be
+                                                     # able to shift 16-r13 bytes (r13 is the
+                                                     # number of bytes in plaintext mod 16)
+
+_get_last_16_byte_loop\@:
+        movb    (arg3, %r11),  %al
+        movb    %al,  TMP1 (%rsp , %r11)
+        add     $1, %r11
+        cmp     %r13,  %r11
+        jne     _get_last_16_byte_loop\@
+
+        vmovdqu  TMP1(%rsp), %xmm1
+
+        sub     $16, %r11
+
+_final_ghash_mul\@:
+        .if  \ENC_DEC ==  DEC
+        vmovdqa %xmm1, %xmm2
+        vpxor   %xmm1, %xmm9, %xmm9                  # Plaintext XOR E(K, Yn)
+        vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1        # get the appropriate mask to mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm9, %xmm9                  # mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm2, %xmm2
+        vpshufb SHUF_MASK(%rip), %xmm2, %xmm2
+        vpxor   %xmm2, %xmm14, %xmm14
+        #GHASH computation for the last <16 Byte block
+        GHASH_MUL_AVX2       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
+        sub     %r13, %r11
+        add     $16, %r11
+        .else
+        vpxor   %xmm1, %xmm9, %xmm9                  # Plaintext XOR E(K, Yn)
+        vmovdqu ALL_F-SHIFT_MASK(%r12), %xmm1        # get the appropriate mask to mask out top 16-r13 bytes of xmm9
+        vpand   %xmm1, %xmm9, %xmm9                  # mask out top 16-r13 bytes of xmm9
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9
+        vpxor   %xmm9, %xmm14, %xmm14
+        #GHASH computation for the last <16 Byte block
+        GHASH_MUL_AVX2       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
+        sub     %r13, %r11
+        add     $16, %r11
+        vpshufb SHUF_MASK(%rip), %xmm9, %xmm9        # shuffle xmm9 back to output as ciphertext
+        .endif
+
+
+        #############################
+        # output r13 Bytes
+        vmovq   %xmm9, %rax
+        cmp     $8, %r13
+        jle     _less_than_8_bytes_left\@
+
+        mov     %rax, (arg2 , %r11)
+        add     $8, %r11
+        vpsrldq $8, %xmm9, %xmm9
+        vmovq   %xmm9, %rax
+        sub     $8, %r13
+
+_less_than_8_bytes_left\@:
+        movb    %al, (arg2 , %r11)
+        add     $1, %r11
+        shr     $8, %rax
+        sub     $1, %r13
+        jne     _less_than_8_bytes_left\@
+        #############################
+
+_multiple_of_16_bytes\@:
+        mov     arg7, %r12                           # r12 = aadLen (number of bytes)
+        shl     $3, %r12                             # convert into number of bits
+        vmovd   %r12d, %xmm15                        # len(A) in xmm15
+
+        shl     $3, arg4                             # len(C) in bits  (*128)
+        vmovq   arg4, %xmm1
+        vpslldq $8, %xmm15, %xmm15                   # xmm15 = len(A)|| 0x0000000000000000
+        vpxor   %xmm1, %xmm15, %xmm15                # xmm15 = len(A)||len(C)
+
+        vpxor   %xmm15, %xmm14, %xmm14
+        GHASH_MUL_AVX2       %xmm14, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6    # final GHASH computation
+        vpshufb SHUF_MASK(%rip), %xmm14, %xmm14              # perform a 16Byte swap
+
+        mov     arg5, %rax                           # rax = *Y0
+        vmovdqu (%rax), %xmm9                        # xmm9 = Y0
+
+        ENCRYPT_SINGLE_BLOCK    %xmm9                # E(K, Y0)
+
+        vpxor   %xmm14, %xmm9, %xmm9
+
+
+
+_return_T\@:
+        mov     arg8, %r10              # r10 = authTag
+        mov     arg9, %r11              # r11 = auth_tag_len
+
+        cmp     $16, %r11
+        je      _T_16\@
+
+        cmp     $12, %r11
+        je      _T_12\@
+
+_T_8\@:
+        vmovq   %xmm9, %rax
+        mov     %rax, (%r10)
+        jmp     _return_T_done\@
+_T_12\@:
+        vmovq   %xmm9, %rax
+        mov     %rax, (%r10)
+        vpsrldq $8, %xmm9, %xmm9
+        vmovd   %xmm9, %eax
+        mov     %eax, 8(%r10)
+        jmp     _return_T_done\@
+
+_T_16\@:
+        vmovdqu %xmm9, (%r10)
+
+_return_T_done\@:
+        mov     %r14, %rsp
+
+        pop     %r15
+        pop     %r14
+        pop     %r13
+        pop     %r12
+.endm
+
+
+#############################################################
+#void   aesni_gcm_precomp_avx_gen4
+#        (gcm_data     *my_ctx_data,
+#        u8     *hash_subkey)# /* H, the Hash sub key input.
+#                               Data starts on a 16-byte boundary. */
+#############################################################
+ENTRY(aesni_gcm_precomp_avx_gen4)
+        #the number of pushes must equal STACK_OFFSET
+        push    %r12
+        push    %r13
+        push    %r14
+        push    %r15
+
+        mov     %rsp, %r14
+
+
+
+        sub     $VARIABLE_OFFSET, %rsp
+        and     $~63, %rsp                    # align rsp to 64 bytes
+
+        vmovdqu  (arg2), %xmm6                # xmm6 = HashKey
+
+        vpshufb  SHUF_MASK(%rip), %xmm6, %xmm6
+        ###############  PRECOMPUTATION of HashKey<<1 mod poly from the HashKey
+        vmovdqa  %xmm6, %xmm2
+        vpsllq   $1, %xmm6, %xmm6
+        vpsrlq   $63, %xmm2, %xmm2
+        vmovdqa  %xmm2, %xmm1
+        vpslldq  $8, %xmm2, %xmm2
+        vpsrldq  $8, %xmm1, %xmm1
+        vpor     %xmm2, %xmm6, %xmm6
+        #reduction
+        vpshufd  $0b00100100, %xmm1, %xmm2
+        vpcmpeqd TWOONE(%rip), %xmm2, %xmm2
+        vpand    POLY(%rip), %xmm2, %xmm2
+        vpxor    %xmm2, %xmm6, %xmm6          # xmm6 holds the HashKey<<1 mod poly
+        #######################################################################
+        vmovdqa  %xmm6, HashKey(arg1)         # store HashKey<<1 mod poly
+
+
+        PRECOMPUTE_AVX2  %xmm6, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5
+
+        mov     %r14, %rsp
+
+        pop     %r15
+        pop     %r14
+        pop     %r13
+        pop     %r12
+        ret
+ENDPROC(aesni_gcm_precomp_avx_gen4)
+
+
+###############################################################################
+#void   aesni_gcm_enc_avx_gen4(
+#        gcm_data        *my_ctx_data,     /* aligned to 16 Bytes */
+#        u8      *out, /* Ciphertext output. Encrypt in-place is allowed.  */
+#        const   u8 *in, /* Plaintext input */
+#        u64     plaintext_len, /* Length of data in Bytes for encryption. */
+#        u8      *iv, /* Pre-counter block j0: 4 byte salt
+#                       (from Security Association) concatenated with 8 byte
+#                        Initialisation Vector (from IPSec ESP Payload)
+#                        concatenated with 0x00000001. 16-byte aligned pointer. */
+#        const   u8 *aad, /* Additional Authentication Data (AAD)*/
+#        u64     aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */
+#        u8      *auth_tag, /* Authenticated Tag output. */
+#        u64     auth_tag_len)# /* Authenticated Tag Length in bytes.
+#                               Valid values are 16 (most likely), 12 or 8. */
+###############################################################################
+ENTRY(aesni_gcm_enc_avx_gen4)
+        GCM_ENC_DEC_AVX2     ENC
+        ret
+ENDPROC(aesni_gcm_enc_avx_gen4)
+
+###############################################################################
+#void   aesni_gcm_dec_avx_gen4(
+#        gcm_data        *my_ctx_data,     /* aligned to 16 Bytes */
+#        u8      *out, /* Plaintext output. Decrypt in-place is allowed.  */
+#        const   u8 *in, /* Ciphertext input */
+#        u64     plaintext_len, /* Length of data in Bytes for encryption. */
+#        u8      *iv, /* Pre-counter block j0: 4 byte salt
+#                       (from Security Association) concatenated with 8 byte
+#                       Initialisation Vector (from IPSec ESP Payload)
+#                       concatenated with 0x00000001. 16-byte aligned pointer. */
+#        const   u8 *aad, /* Additional Authentication Data (AAD)*/
+#        u64     aad_len, /* Length of AAD in bytes. With RFC4106 this is going to be 8 or 12 Bytes */
+#        u8      *auth_tag, /* Authenticated Tag output. */
+#        u64     auth_tag_len)# /* Authenticated Tag Length in bytes.
+#                               Valid values are 16 (most likely), 12 or 8. */
+###############################################################################
+ENTRY(aesni_gcm_dec_avx_gen4)
+        GCM_ENC_DEC_AVX2     DEC
+        ret
+ENDPROC(aesni_gcm_dec_avx_gen4)
+
+#endif /* CONFIG_AS_AVX2 */
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index 835488b745ee..948ad0e77741 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -101,6 +101,9 @@ asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
 int crypto_fpu_init(void);
 void crypto_fpu_exit(void);
 
+#define AVX_GEN2_OPTSIZE 640
+#define AVX_GEN4_OPTSIZE 4096
+
 #ifdef CONFIG_X86_64
 asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,
                               const u8 *in, unsigned int len, u8 *iv);
@@ -150,6 +153,123 @@ asmlinkage void aesni_gcm_dec(void *ctx, u8 *out,
                         u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
                         u8 *auth_tag, unsigned long auth_tag_len);
 
+
+#ifdef CONFIG_AS_AVX
+/*
+ * asmlinkage void aesni_gcm_precomp_avx_gen2()
+ * gcm_data *my_ctx_data, context data
+ * u8 *hash_subkey,  the Hash sub key input. Data starts on a 16-byte boundary.
+ */
+asmlinkage void aesni_gcm_precomp_avx_gen2(void *my_ctx_data, u8 *hash_subkey);
+
+asmlinkage void aesni_gcm_enc_avx_gen2(void *ctx, u8 *out,
+                        const u8 *in, unsigned long plaintext_len, u8 *iv,
+                        const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
+asmlinkage void aesni_gcm_dec_avx_gen2(void *ctx, u8 *out,
+                        const u8 *in, unsigned long ciphertext_len, u8 *iv,
+                        const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
+static void aesni_gcm_enc_avx(void *ctx, u8 *out,
+                        const u8 *in, unsigned long plaintext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len)
+{
+        if (plaintext_len < AVX_GEN2_OPTSIZE) {
+                aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
+                                aad_len, auth_tag, auth_tag_len);
+        } else {
+                aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
+                aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        }
+}
+
+static void aesni_gcm_dec_avx(void *ctx, u8 *out,
+                        const u8 *in, unsigned long ciphertext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len)
+{
+        if (ciphertext_len < AVX_GEN2_OPTSIZE) {
+                aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, aad,
+                                aad_len, auth_tag, auth_tag_len);
+        } else {
+                aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
+                aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        }
+}
+#endif
+
+#ifdef CONFIG_AS_AVX2
+/*
+ * asmlinkage void aesni_gcm_precomp_avx_gen4()
+ * gcm_data *my_ctx_data, context data
+ * u8 *hash_subkey,  the Hash sub key input. Data starts on a 16-byte boundary.
+ */
+asmlinkage void aesni_gcm_precomp_avx_gen4(void *my_ctx_data, u8 *hash_subkey);
+
+asmlinkage void aesni_gcm_enc_avx_gen4(void *ctx, u8 *out,
+                        const u8 *in, unsigned long plaintext_len, u8 *iv,
+                        const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
+asmlinkage void aesni_gcm_dec_avx_gen4(void *ctx, u8 *out,
+                        const u8 *in, unsigned long ciphertext_len, u8 *iv,
+                        const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
+static void aesni_gcm_enc_avx2(void *ctx, u8 *out,
+                        const u8 *in, unsigned long plaintext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len)
+{
+        if (plaintext_len < AVX_GEN2_OPTSIZE) {
+                aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
+                                aad_len, auth_tag, auth_tag_len);
+        } else if (plaintext_len < AVX_GEN4_OPTSIZE) {
+                aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
+                aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        } else {
+                aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
+                aesni_gcm_enc_avx_gen4(ctx, out, in, plaintext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        }
+}
+
+static void aesni_gcm_dec_avx2(void *ctx, u8 *out,
+                        const u8 *in, unsigned long ciphertext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len)
+{
+        if (ciphertext_len < AVX_GEN2_OPTSIZE) {
+                aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey,
+                                aad, aad_len, auth_tag, auth_tag_len);
+        } else if (ciphertext_len < AVX_GEN4_OPTSIZE) {
+                aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
+                aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        } else {
+                aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
+                aesni_gcm_dec_avx_gen4(ctx, out, in, ciphertext_len, iv, aad,
+                                        aad_len, auth_tag, auth_tag_len);
+        }
+}
+#endif
+
+static void (*aesni_gcm_enc_tfm)(void *ctx, u8 *out,
+                        const u8 *in, unsigned long plaintext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
+static void (*aesni_gcm_dec_tfm)(void *ctx, u8 *out,
+                        const u8 *in, unsigned long ciphertext_len, u8 *iv,
+                        u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
+                        u8 *auth_tag, unsigned long auth_tag_len);
+
 static inline struct
 aesni_rfc4106_gcm_ctx *aesni_rfc4106_gcm_ctx_get(struct crypto_aead *tfm)
 {
@@ -915,7 +1035,7 @@ static int __driver_rfc4106_encrypt(struct aead_request *req)
                 dst = src;
         }
 
-        aesni_gcm_enc(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv,
+        aesni_gcm_enc_tfm(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv,
                 ctx->hash_subkey, assoc, (unsigned long)req->assoclen, dst
                 + ((unsigned long)req->cryptlen), auth_tag_len);
 
@@ -996,12 +1116,12 @@ static int __driver_rfc4106_decrypt(struct aead_request *req)
                 dst = src;
         }
 
-        aesni_gcm_dec(aes_ctx, dst, src, tempCipherLen, iv,
+        aesni_gcm_dec_tfm(aes_ctx, dst, src, tempCipherLen, iv,
                 ctx->hash_subkey, assoc, (unsigned long)req->assoclen,
                 authTag, auth_tag_len);
 
         /* Compare generated tag with passed in tag. */
-        retval = memcmp(src + tempCipherLen, authTag, auth_tag_len) ?
+        retval = crypto_memneq(src + tempCipherLen, authTag, auth_tag_len) ?
                 -EBADMSG : 0;
 
         if (one_entry_in_sg) {
@@ -1353,6 +1473,27 @@ static int __init aesni_init(void)
 
         if (!x86_match_cpu(aesni_cpu_id))
                 return -ENODEV;
+#ifdef CONFIG_X86_64
+#ifdef CONFIG_AS_AVX2
+        if (boot_cpu_has(X86_FEATURE_AVX2)) {
+                pr_info("AVX2 version of gcm_enc/dec engaged.\n");
+                aesni_gcm_enc_tfm = aesni_gcm_enc_avx2;
+                aesni_gcm_dec_tfm = aesni_gcm_dec_avx2;
+        } else
+#endif
+#ifdef CONFIG_AS_AVX
+        if (boot_cpu_has(X86_FEATURE_AVX)) {
+                pr_info("AVX version of gcm_enc/dec engaged.\n");
+                aesni_gcm_enc_tfm = aesni_gcm_enc_avx;
+                aesni_gcm_dec_tfm = aesni_gcm_dec_avx;
+        } else
+#endif
+        {
+                pr_info("SSE version of gcm_enc/dec engaged.\n");
+                aesni_gcm_enc_tfm = aesni_gcm_enc;
+                aesni_gcm_dec_tfm = aesni_gcm_dec;
+        }
+#endif
 
         err = crypto_fpu_init();
         if (err)
diff --git a/arch/x86/include/asm/dmi.h b/arch/x86/include/asm/dmi.h
index fd8f9e2ca35f..535192f6bfad 100644
--- a/arch/x86/include/asm/dmi.h
+++ b/arch/x86/include/asm/dmi.h
@@ -13,7 +13,9 @@ static __always_inline __init void *dmi_alloc(unsigned len)
 }
 
 /* Use early IO mappings for DMI because it's initialized early */
-#define dmi_ioremap early_ioremap
-#define dmi_iounmap early_iounmap
+#define dmi_early_remap         early_ioremap
+#define dmi_early_unmap         early_iounmap
+#define dmi_remap               ioremap
+#define dmi_unmap               iounmap
 
 #endif /* _ASM_X86_DMI_H */
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index e846225265ed..7252cd339175 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -175,64 +175,7 @@ static inline void __set_fixmap(enum fixed_addresses idx,
 }
 #endif
 
-#define set_fixmap(idx, phys)                           \
-        __set_fixmap(idx, phys, PAGE_KERNEL)
-
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys)                   \
-        __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
-
-#define clear_fixmap(idx)                       \
-        __set_fixmap(idx, 0, __pgprot(0))
-
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without translation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
-
-/* Return an pointer with offset calculated */
-static __always_inline unsigned long
-__set_fixmap_offset(enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags)
-{
-        __set_fixmap(idx, phys, flags);
-        return fix_to_virt(idx) + (phys & (PAGE_SIZE - 1));
-}
-
-#define set_fixmap_offset(idx, phys)                    \
-        __set_fixmap_offset(idx, phys, PAGE_KERNEL)
-
-#define set_fixmap_offset_nocache(idx, phys)                    \
-        __set_fixmap_offset(idx, phys, PAGE_KERNEL_NOCACHE)
+#include <asm-generic/fixmap.h>
 
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_X86_FIXMAP_H */
diff --git a/arch/x86/include/asm/hash.h b/arch/x86/include/asm/hash.h
new file mode 100644
index 000000000000..e8c58f88b1d4
--- /dev/null
+++ b/arch/x86/include/asm/hash.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_X86_HASH_H
+#define _ASM_X86_HASH_H
+
+struct fast_hash_ops;
+extern void setup_arch_fast_hash(struct fast_hash_ops *ops);
+
+#endif /* _ASM_X86_HASH_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index ae5d7830855c..fdf83afbb7d9 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -605,6 +605,7 @@ struct kvm_arch {
         /* fields used by HYPER-V emulation */
         u64 hv_guest_os_id;
         u64 hv_hypercall;
+        u64 hv_tsc_page;
 
         #ifdef CONFIG_KVM_MMU_AUDIT
         int audit_point;
@@ -699,6 +700,8 @@ struct kvm_x86_ops {
         void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
         void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
         void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
+        u64 (*get_dr6)(struct kvm_vcpu *vcpu);
+        void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value);
         void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
         void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
         unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index 1df115909758..c7678e43465b 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -85,28 +85,9 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
         return ret;
 }
 
-static inline uint32_t kvm_cpuid_base(void)
-{
-        if (boot_cpu_data.cpuid_level < 0)
-                return 0;       /* So we don't blow up on old processors */
-
-        if (cpu_has_hypervisor)
-                return hypervisor_cpuid_base("KVMKVMKVM\0\0\0", 0);
-
-        return 0;
-}
-
-static inline bool kvm_para_available(void)
-{
-        return kvm_cpuid_base() != 0;
-}
-
-static inline unsigned int kvm_arch_para_features(void)
-{
-        return cpuid_eax(KVM_CPUID_FEATURES);
-}
-
 #ifdef CONFIG_KVM_GUEST
+bool kvm_para_available(void);
+unsigned int kvm_arch_para_features(void);
 void __init kvm_guest_init(void);
 void kvm_async_pf_task_wait(u32 token);
 void kvm_async_pf_task_wake(u32 token);
@@ -126,6 +107,16 @@ static inline void kvm_spinlock_init(void)
 #define kvm_async_pf_task_wait(T) do {} while(0)
 #define kvm_async_pf_task_wake(T) do {} while(0)
 
+static inline bool kvm_para_available(void)
+{
+        return 0;
+}
+
+static inline unsigned int kvm_arch_para_features(void)
+{
+        return 0;
+}
+
 static inline u32 kvm_read_and_reset_pf_reason(void)
 {
         return 0;
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 401f350ef71b..cd6e1610e29e 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -781,9 +781,9 @@ static __always_inline void __ticket_unlock_kick(struct arch_spinlock *lock,
  */
 #define PV_CALLEE_SAVE_REGS_THUNK(func)                                 \
         extern typeof(func) __raw_callee_save_##func;                   \
-        static void *__##func##__ __used = func;                        \
                                                                         \
         asm(".pushsection .text;"                                       \
+            ".globl __raw_callee_save_" #func " ; "                     \
             "__raw_callee_save_" #func ": "                             \
             PV_SAVE_ALL_CALLER_REGS                                     \
             "call " #func ";"                                           \
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index aab8f671b523..7549b8b369e4 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -388,10 +388,11 @@ extern struct pv_lock_ops pv_lock_ops;
         _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
 
 /* Simple instruction patching code. */
-#define DEF_NATIVE(ops, name, code)                                     \
-        extern const char start_##ops##_##name[] __visible,             \
-                          end_##ops##_##name[] __visible;               \
-        asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
+#define NATIVE_LABEL(a,x,b) "\n\t.globl " a #x "_" #b "\n" a #x "_" #b ":\n\t"
+
+#define DEF_NATIVE(ops, name, code)                                     \
+        __visible extern const char start_##ops##_##name[], end_##ops##_##name[];       \
+        asm(NATIVE_LABEL("start_", ops, name) code NATIVE_LABEL("end_", ops, name))
 
 unsigned paravirt_patch_nop(void);
 unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len);
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 947b5c417e83..1ac6114c9ea5 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -104,7 +104,7 @@ extern void pci_iommu_alloc(void);
 struct msi_desc;
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void native_teardown_msi_irq(unsigned int irq);
-void native_restore_msi_irqs(struct pci_dev *dev, int irq);
+void native_restore_msi_irqs(struct pci_dev *dev);
 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
                   unsigned int irq_base, unsigned int irq_offset);
 #else
@@ -125,7 +125,6 @@ int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
 
 /* generic pci stuff */
 #include <asm-generic/pci.h>
-#define PCIBIOS_MAX_MEM_32 0xffffffff
 
 #ifdef CONFIG_NUMA
 /* Returns the node based on pci bus */
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index a83aa44bb1fb..1aa9ccd43223 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -121,7 +121,8 @@
 
 /* Set of bits not changed in pte_modify */
 #define _PAGE_CHG_MASK  (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT |         \
-                         _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY)
+                         _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_SOFT_DIRTY)
 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
 
 #define _PAGE_CACHE_MASK        (_PAGE_PCD | _PAGE_PWT)
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 3ba3de457d05..e1940c06ed02 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -163,9 +163,11 @@ struct thread_info {
  */
 #ifndef __ASSEMBLY__
 
-
-/* how to get the current stack pointer from C */
-register unsigned long current_stack_pointer asm("esp") __used;
+#define current_stack_pointer ({                \
+        unsigned long sp;                       \
+        asm("mov %%esp,%0" : "=g" (sp));        \
+        sp;                                     \
+})
 
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
diff --git a/arch/x86/include/asm/uv/uv.h b/arch/x86/include/asm/uv/uv.h
index 6b964a0b86d1..062921ef34e9 100644
--- a/arch/x86/include/asm/uv/uv.h
+++ b/arch/x86/include/asm/uv/uv.h
@@ -12,7 +12,6 @@ extern enum uv_system_type get_uv_system_type(void);
 extern int is_uv_system(void);
 extern void uv_cpu_init(void);
 extern void uv_nmi_init(void);
-extern void uv_register_nmi_notifier(void);
 extern void uv_system_init(void);
 extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                                  struct mm_struct *mm,
@@ -26,7 +25,6 @@ static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
 static inline int is_uv_system(void)    { return 0; }
 static inline void uv_cpu_init(void)    { }
 static inline void uv_system_init(void) { }
-static inline void uv_register_nmi_notifier(void) { }
 static inline const struct cpumask *
 uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,
                     unsigned long start, unsigned long end, unsigned int cpu)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 966502d4682e..2067264fb7f5 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -100,6 +100,7 @@
 
 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK     0x0000001f
 #define VMX_MISC_SAVE_EFER_LMA                  0x00000020
+#define VMX_MISC_ACTIVITY_HLT                   0x00000040
 
 /* VMCS Encodings */
 enum vmcs_field {
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 0f1be11e43d2..e45e4da96bf1 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -181,7 +181,7 @@ struct x86_msi_ops {
                                u8 hpet_id);
         void (*teardown_msi_irq)(unsigned int irq);
         void (*teardown_msi_irqs)(struct pci_dev *dev);
-        void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
+        void (*restore_msi_irqs)(struct pci_dev *dev);
         int  (*setup_hpet_msi)(unsigned int irq, unsigned int id);
         u32 (*msi_mask_irq)(struct msi_desc *desc, u32 mask, u32 flag);
         u32 (*msix_mask_irq)(struct msi_desc *desc, u32 flag);
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index b913915e8e63..787e1bb5aafc 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -52,7 +52,8 @@ extern unsigned long set_phys_range_identity(unsigned long pfn_s,
 extern int m2p_add_override(unsigned long mfn, struct page *page,
                             struct gnttab_map_grant_ref *kmap_op);
 extern int m2p_remove_override(struct page *page,
-                                struct gnttab_map_grant_ref *kmap_op);
+                               struct gnttab_map_grant_ref *kmap_op,
+                               unsigned long mfn);
 extern struct page *m2p_find_override(unsigned long mfn);
 extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn);
 
@@ -121,7 +122,7 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
                 pfn = m2p_find_override_pfn(mfn, ~0);
         }
 
-        /* 
+        /*
          * pfn is ~0 if there are no entries in the m2p for mfn or if the
          * entry doesn't map back to the mfn and m2p_override doesn't have a
          * valid entry for it.
@@ -167,7 +168,12 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine)
  */
 static inline unsigned long mfn_to_local_pfn(unsigned long mfn)
 {
-        unsigned long pfn = mfn_to_pfn(mfn);
+        unsigned long pfn;
+
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return mfn;
+
+        pfn = mfn_to_pfn(mfn);
         if (get_phys_to_machine(pfn) != mfn)
                 return -1; /* force !pfn_valid() */
         return pfn;
@@ -222,5 +228,6 @@ void make_lowmem_page_readonly(void *vaddr);
 void make_lowmem_page_readwrite(void *vaddr);
 
 #define xen_remap(cookie, size) ioremap((cookie), (size));
+#define xen_unmap(cookie) iounmap((cookie))
 
 #endif /* _ASM_X86_XEN_PAGE_H */
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
index b8f1c0176cbc..462efe746d77 100644
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -28,6 +28,9 @@
 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
 #define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
 
+/* A partition's reference time stamp counter (TSC) page */
+#define HV_X64_MSR_REFERENCE_TSC                0x40000021
+
 /*
  * There is a single feature flag that signifies the presence of the MSR
  * that can be used to retrieve both the local APIC Timer frequency as
@@ -198,6 +201,9 @@
 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
                 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 
+#define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
+#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
+
 #define HV_PROCESSOR_POWER_STATE_C0             0
 #define HV_PROCESSOR_POWER_STATE_C1             1
 #define HV_PROCESSOR_POWER_STATE_C2             2
@@ -210,4 +216,11 @@
 #define HV_STATUS_INVALID_ALIGNMENT             4
 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 
+typedef struct _HV_REFERENCE_TSC_PAGE {
+        __u32 tsc_sequence;
+        __u32 res1;
+        __u64 tsc_scale;
+        __s64 tsc_offset;
+} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
+
 #endif
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 59cea185ad1d..c19fc60ff062 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -528,6 +528,7 @@
 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
 #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
+#define MSR_IA32_VMX_VMFUNC             0x00000491
 
 /* VMX_BASIC bits and bitmasks */
 #define VMX_BASIC_VMCS_SIZE_SHIFT       32
diff --git a/arch/x86/include/uapi/asm/sembuf.h b/arch/x86/include/uapi/asm/sembuf.h
index ee50c801f7b7..cc2d6a3aeae7 100644
--- a/arch/x86/include/uapi/asm/sembuf.h
+++ b/arch/x86/include/uapi/asm/sembuf.h
@@ -13,12 +13,12 @@
 struct semid64_ds {
         struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
         __kernel_time_t sem_otime;      /* last semop time */
-        unsigned long   __unused1;
+        __kernel_ulong_t __unused1;
         __kernel_time_t sem_ctime;      /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;      /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
+        __kernel_ulong_t __unused2;
+        __kernel_ulong_t sem_nsems;     /* no. of semaphores in array */
+        __kernel_ulong_t __unused3;
+        __kernel_ulong_t __unused4;
 };
 
 #endif /* _ASM_X86_SEMBUF_H */
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 6c0b43bd024b..1dac94265b59 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -46,7 +46,6 @@
 
 #include "sleep.h" /* To include x86_acpi_suspend_lowlevel */
 static int __initdata acpi_force = 0;
-u32 acpi_rsdt_forced;
 int acpi_disabled;
 EXPORT_SYMBOL(acpi_disabled);
 
@@ -1034,9 +1033,7 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
 
         if (!acpi_ioapic)
                 return 0;
-        if (!dev)
-                return 0;
-        if (dev->bus != &pci_bus_type)
+        if (!dev || !dev_is_pci(dev))
                 return 0;
 
         pdev = to_pci_dev(dev);
@@ -1564,7 +1561,7 @@ static int __init parse_acpi(char *arg)
         }
         /* acpi=rsdt use RSDT instead of XSDT */
         else if (strcmp(arg, "rsdt") == 0) {
-                acpi_rsdt_forced = 1;
+                acpi_gbl_do_not_use_xsdt = TRUE;
         }
         /* "acpi=noirq" disables ACPI interrupt routing */
         else if (strcmp(arg, "noirq") == 0) {
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 5d5b9eb2b7a4..2c621a6b901a 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -20,9 +20,7 @@
 #include <asm/apic.h>
 #include <asm/ipi.h>
 
-#ifdef CONFIG_ACPI
-#include <acpi/acpi_bus.h>
-#endif
+#include <linux/acpi.h>
 
 static struct apic apic_physflat;
 static struct apic apic_flat;
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index a43f068ebec1..6ad4658de705 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -37,9 +37,6 @@
 #include <linux/kthread.h>
 #include <linux/jiffies.h>      /* time_after() */
 #include <linux/slab.h>
-#ifdef CONFIG_ACPI
-#include <acpi/acpi_bus.h>
-#endif
 #include <linux/bootmem.h>
 #include <linux/dmar.h>
 #include <linux/hpet.h>
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index ad0dc0428baf..d263b1307de1 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -980,7 +980,6 @@ void __init uv_system_init(void)
         uv_nmi_setup();
         uv_cpu_init();
         uv_scir_register_cpu_notifier();
-        uv_register_nmi_notifier();
         proc_mkdir("sgi_uv", NULL);
 
         /* register Legacy VGA I/O redirection handler */
diff --git a/arch/x86/kernel/check.c b/arch/x86/kernel/check.c
index e2dbcb7dabdd..83a7995625a6 100644
--- a/arch/x86/kernel/check.c
+++ b/arch/x86/kernel/check.c
@@ -91,7 +91,7 @@ void __init setup_bios_corruption_check(void)
 
         corruption_check_size = round_up(corruption_check_size, PAGE_SIZE);
 
-        for_each_free_mem_range(i, MAX_NUMNODES, &start, &end, NULL) {
+        for_each_free_mem_range(i, NUMA_NO_NODE, &start, &end, NULL) {
                 start = clamp_t(phys_addr_t, round_up(start, PAGE_SIZE),
                                 PAGE_SIZE, corruption_check_size);
                 end = clamp_t(phys_addr_t, round_down(end, PAGE_SIZE),
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 4a6ff747aaad..8fffd845e22b 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -433,7 +433,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
         if (c->x86 >= 0x15)
                 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
 
-        if (request_firmware(&fw, (const char *)fw_name, device)) {
+        if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
                 pr_debug("failed to load file %s\n", fw_name);
                 goto out;
         }
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 5fb2cebf556b..a276fa75d9b5 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -278,7 +278,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
         sprintf(name, "intel-ucode/%02x-%02x-%02x",
                 c->x86, c->x86_model, c->x86_mask);
 
-        if (request_firmware(&firmware, name, device)) {
+        if (request_firmware_direct(&firmware, name, device)) {
                 pr_debug("data file %s load failed\n", name);
                 return UCODE_NFOUND;
         }
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 174da5fc5a7b..988c00a1f60d 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -1120,7 +1120,7 @@ void __init memblock_find_dma_reserve(void)
                 nr_pages += end_pfn - start_pfn;
         }
 
-        for_each_free_mem_range(u, MAX_NUMNODES, &start, &end, NULL) {
+        for_each_free_mem_range(u, NUMA_NO_NODE, &start, &end, NULL) {
                 start_pfn = min_t(unsigned long, PFN_UP(start), MAX_DMA_PFN);
                 end_pfn = min_t(unsigned long, PFN_DOWN(end), MAX_DMA_PFN);
                 if (start_pfn < end_pfn)
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 6dd802c6d780..713f1b3bad52 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -500,6 +500,38 @@ void __init kvm_guest_init(void)
 #endif
 }
 
+static noinline uint32_t __kvm_cpuid_base(void)
+{
+        if (boot_cpu_data.cpuid_level < 0)
+                return 0;       /* So we don't blow up on old processors */
+
+        if (cpu_has_hypervisor)
+                return hypervisor_cpuid_base("KVMKVMKVM\0\0\0", 0);
+
+        return 0;
+}
+
+static inline uint32_t kvm_cpuid_base(void)
+{
+        static int kvm_cpuid_base = -1;
+
+        if (kvm_cpuid_base == -1)
+                kvm_cpuid_base = __kvm_cpuid_base();
+
+        return kvm_cpuid_base;
+}
+
+bool kvm_para_available(void)
+{
+        return kvm_cpuid_base() != 0;
+}
+EXPORT_SYMBOL_GPL(kvm_para_available);
+
+unsigned int kvm_arch_para_features(void)
+{
+        return cpuid_eax(kvm_cpuid_base() | KVM_CPUID_FEATURES);
+}
+
 static uint32_t __init kvm_detect(void)
 {
         return kvm_cpuid_base();
@@ -673,7 +705,7 @@ static cpumask_t waiting_cpus;
 /* Track spinlock on which a cpu is waiting */
 static DEFINE_PER_CPU(struct kvm_lock_waiting, klock_waiting);
 
-static void kvm_lock_spinning(struct arch_spinlock *lock, __ticket_t want)
+__visible void kvm_lock_spinning(struct arch_spinlock *lock, __ticket_t want)
 {
         struct kvm_lock_waiting *w;
         int cpu;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index a3acbac2ee72..19e5adb49a27 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -180,7 +180,7 @@ static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
 
 static void cyc2ns_data_init(struct cyc2ns_data *data)
 {
-        data->cyc2ns_mul = 1U << CYC2NS_SCALE_FACTOR;
+        data->cyc2ns_mul = 0;
         data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
         data->cyc2ns_offset = 0;
         data->__count = 0;
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index 992f890283e9..f6584a90aba3 100644
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -33,7 +33,7 @@
  * and vice versa.
  */
 
-static unsigned long vsmp_save_fl(void)
+asmlinkage unsigned long vsmp_save_fl(void)
 {
         unsigned long flags = native_save_fl();
 
@@ -43,7 +43,7 @@ static unsigned long vsmp_save_fl(void)
 }
 PV_CALLEE_SAVE_REGS_THUNK(vsmp_save_fl);
 
-static void vsmp_restore_fl(unsigned long flags)
+__visible void vsmp_restore_fl(unsigned long flags)
 {
         if (flags & X86_EFLAGS_IF)
                 flags &= ~X86_EFLAGS_AC;
@@ -53,7 +53,7 @@ static void vsmp_restore_fl(unsigned long flags)
 }
 PV_CALLEE_SAVE_REGS_THUNK(vsmp_restore_fl);
 
-static void vsmp_irq_disable(void)
+asmlinkage void vsmp_irq_disable(void)
 {
         unsigned long flags = native_save_fl();
 
@@ -61,7 +61,7 @@ static void vsmp_irq_disable(void)
 }
 PV_CALLEE_SAVE_REGS_THUNK(vsmp_irq_disable);
 
-static void vsmp_irq_enable(void)
+asmlinkage void vsmp_irq_enable(void)
 {
         unsigned long flags = native_save_fl();
 
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 021783b1f46a..e48b674639cc 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -136,9 +136,9 @@ void arch_teardown_msi_irq(unsigned int irq)
         x86_msi.teardown_msi_irq(irq);
 }
 
-void arch_restore_msi_irqs(struct pci_dev *dev, int irq)
+void arch_restore_msi_irqs(struct pci_dev *dev)
 {
-        x86_msi.restore_msi_irqs(dev, irq);
+        x86_msi.restore_msi_irqs(dev);
 }
 u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 {
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index b89c5db2b832..287e4c85fff9 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -80,7 +80,7 @@ config KVM_MMU_AUDIT
         depends on KVM && TRACEPOINTS
         ---help---
          This option adds a R/W kVM module parameter 'mmu_audit', which allows
-         audit  KVM MMU at runtime.
+         auditing of KVM MMU events at runtime.
 
 config KVM_DEVICE_ASSIGNMENT
         bool "KVM legacy PCI device assignment support"
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index f1e4895174b2..a2a1bb7ed8c1 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -72,4 +72,12 @@ static inline bool guest_cpuid_has_pcid(struct kvm_vcpu *vcpu)
         return best && (best->ecx & bit(X86_FEATURE_PCID));
 }
 
+static inline bool guest_cpuid_has_x2apic(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        return best && (best->ecx & bit(X86_FEATURE_X2APIC));
+}
+
 #endif
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 412a5aa0ef94..518d86471b76 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -37,6 +37,7 @@
 
 #include "irq.h"
 #include "i8254.h"
+#include "x86.h"
 
 #ifndef CONFIG_X86_64
 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
@@ -349,6 +350,23 @@ static void create_pit_timer(struct kvm *kvm, u32 val, int is_period)
         atomic_set(&ps->pending, 0);
         ps->irq_ack = 1;
 
+        /*
+         * Do not allow the guest to program periodic timers with small
+         * interval, since the hrtimers are not throttled by the host
+         * scheduler.
+         */
+        if (ps->is_periodic) {
+                s64 min_period = min_timer_period_us * 1000LL;
+
+                if (ps->period < min_period) {
+                        pr_info_ratelimited(
+                            "kvm: requested %lld ns "
+                            "i8254 timer period limited to %lld ns\n",
+                            ps->period, min_period);
+                        ps->period = min_period;
+                }
+        }
+
         hrtimer_start(&ps->timer, ktime_add_ns(ktime_get(), interval),
                       HRTIMER_MODE_ABS);
 }
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 775702f649ca..9736529ade08 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -71,9 +71,6 @@
 #define VEC_POS(v) ((v) & (32 - 1))
 #define REG_POS(v) (((v) >> 5) << 4)
 
-static unsigned int min_timer_period_us = 500;
-module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
-
 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 {
         *((u32 *) (apic->regs + reg_off)) = val;
@@ -435,7 +432,7 @@ static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
         u8 val;
         if (pv_eoi_get_user(vcpu, &val) < 0)
                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+                           (unsigned long long)vcpu->arch.pv_eoi.msr_val);
         return val & 0x1;
 }
 
@@ -443,7 +440,7 @@ static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 {
         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+                           (unsigned long long)vcpu->arch.pv_eoi.msr_val);
                 return;
         }
         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
@@ -453,7 +450,7 @@ static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 {
         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
-                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+                           (unsigned long long)vcpu->arch.pv_eoi.msr_val);
                 return;
         }
         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index c8b0d0d2da5c..6a11845fd8b9 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -65,7 +65,7 @@ bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map);
 
 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
-void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
+int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
                 struct kvm_lapic_state *s);
 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 40772ef0f2b1..e50425d0f5f7 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -2659,6 +2659,9 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
         int emulate = 0;
         gfn_t pseudo_gfn;
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                return 0;
+
         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
                 if (iterator.level == level) {
                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
@@ -2829,6 +2832,9 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
         bool ret = false;
         u64 spte = 0ull;
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                return false;
+
         if (!page_fault_can_be_fast(error_code))
                 return false;
 
@@ -3224,6 +3230,9 @@ static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
         struct kvm_shadow_walk_iterator iterator;
         u64 spte = 0ull;
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                return spte;
+
         walk_shadow_page_lockless_begin(vcpu);
         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
                 if (!is_shadow_present_pte(spte))
@@ -4510,6 +4519,9 @@ int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
         u64 spte;
         int nr_sptes = 0;
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                return nr_sptes;
+
         walk_shadow_page_lockless_begin(vcpu);
         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
                 sptes[iterator.level-1] = spte;
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index ad75d77999d0..cba218a2f08d 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -569,6 +569,9 @@ static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
         if (FNAME(gpte_changed)(vcpu, gw, top_level))
                 goto out_gpte_changed;
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                goto out_gpte_changed;
+
         for (shadow_walk_init(&it, vcpu, addr);
              shadow_walk_okay(&it) && it.level > gw->level;
              shadow_walk_next(&it)) {
@@ -820,6 +823,11 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
          */
         mmu_topup_memory_caches(vcpu);
 
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
+                WARN_ON(1);
+                return;
+        }
+
         spin_lock(&vcpu->kvm->mmu_lock);
         for_each_shadow_entry(vcpu, gva, iterator) {
                 level = iterator.level;
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index c7168a5cff1b..e81df8fce027 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1671,6 +1671,19 @@ static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
         mark_dirty(svm->vmcb, VMCB_ASID);
 }
 
+static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
+{
+        return to_svm(vcpu)->vmcb->save.dr6;
+}
+
+static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
+{
+        struct vcpu_svm *svm = to_svm(vcpu);
+
+        svm->vmcb->save.dr6 = value;
+        mark_dirty(svm->vmcb, VMCB_DR);
+}
+
 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
@@ -4286,6 +4299,8 @@ static struct kvm_x86_ops svm_x86_ops = {
         .set_idt = svm_set_idt,
         .get_gdt = svm_get_gdt,
         .set_gdt = svm_set_gdt,
+        .get_dr6 = svm_get_dr6,
+        .set_dr6 = svm_set_dr6,
         .set_dr7 = svm_set_dr7,
         .cache_reg = svm_cache_reg,
         .get_rflags = svm_get_rflags,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index da7837e1349d..a06f101ef64b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -418,6 +418,8 @@ struct vcpu_vmx {
         u64                   msr_host_kernel_gs_base;
         u64                   msr_guest_kernel_gs_base;
 #endif
+        u32 vm_entry_controls_shadow;
+        u32 vm_exit_controls_shadow;
         /*
          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
          * non-nested (L1) guest, it always points to vmcs01. For a nested
@@ -1056,7 +1058,9 @@ static inline bool is_exception(u32 intr_info)
                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 }
 
-static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
+static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
+                              u32 exit_intr_info,
+                              unsigned long exit_qualification);
 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
                         struct vmcs12 *vmcs12,
                         u32 reason, unsigned long qualification);
@@ -1326,6 +1330,62 @@ static void vmcs_set_bits(unsigned long field, u32 mask)
         vmcs_writel(field, vmcs_readl(field) | mask);
 }
 
+static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
+{
+        vmcs_write32(VM_ENTRY_CONTROLS, val);
+        vmx->vm_entry_controls_shadow = val;
+}
+
+static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
+{
+        if (vmx->vm_entry_controls_shadow != val)
+                vm_entry_controls_init(vmx, val);
+}
+
+static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
+{
+        return vmx->vm_entry_controls_shadow;
+}
+
+
+static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
+{
+        vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
+}
+
+static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
+{
+        vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
+}
+
+static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
+{
+        vmcs_write32(VM_EXIT_CONTROLS, val);
+        vmx->vm_exit_controls_shadow = val;
+}
+
+static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
+{
+        if (vmx->vm_exit_controls_shadow != val)
+                vm_exit_controls_init(vmx, val);
+}
+
+static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
+{
+        return vmx->vm_exit_controls_shadow;
+}
+
+
+static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
+{
+        vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
+}
+
+static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
+{
+        vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
+}
+
 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 {
         vmx->segment_cache.bitmask = 0;
@@ -1410,11 +1470,11 @@ static void update_exception_bitmap(struct kvm_vcpu *vcpu)
         vmcs_write32(EXCEPTION_BITMAP, eb);
 }
 
-static void clear_atomic_switch_msr_special(unsigned long entry,
-                unsigned long exit)
+static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
+                unsigned long entry, unsigned long exit)
 {
-        vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
-        vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
+        vm_entry_controls_clearbit(vmx, entry);
+        vm_exit_controls_clearbit(vmx, exit);
 }
 
 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
@@ -1425,14 +1485,15 @@ static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
         switch (msr) {
         case MSR_EFER:
                 if (cpu_has_load_ia32_efer) {
-                        clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
+                        clear_atomic_switch_msr_special(vmx,
+                                        VM_ENTRY_LOAD_IA32_EFER,
                                         VM_EXIT_LOAD_IA32_EFER);
                         return;
                 }
                 break;
         case MSR_CORE_PERF_GLOBAL_CTRL:
                 if (cpu_has_load_perf_global_ctrl) {
-                        clear_atomic_switch_msr_special(
+                        clear_atomic_switch_msr_special(vmx,
                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
                         return;
@@ -1453,14 +1514,15 @@ static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 }
 
-static void add_atomic_switch_msr_special(unsigned long entry,
-                unsigned long exit, unsigned long guest_val_vmcs,
-                unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
+static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
+                unsigned long entry, unsigned long exit,
+                unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
+                u64 guest_val, u64 host_val)
 {
         vmcs_write64(guest_val_vmcs, guest_val);
         vmcs_write64(host_val_vmcs, host_val);
-        vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
-        vmcs_set_bits(VM_EXIT_CONTROLS, exit);
+        vm_entry_controls_setbit(vmx, entry);
+        vm_exit_controls_setbit(vmx, exit);
 }
 
 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
@@ -1472,7 +1534,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
         switch (msr) {
         case MSR_EFER:
                 if (cpu_has_load_ia32_efer) {
-                        add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
+                        add_atomic_switch_msr_special(vmx,
+                                        VM_ENTRY_LOAD_IA32_EFER,
                                         VM_EXIT_LOAD_IA32_EFER,
                                         GUEST_IA32_EFER,
                                         HOST_IA32_EFER,
@@ -1482,7 +1545,7 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
                 break;
         case MSR_CORE_PERF_GLOBAL_CTRL:
                 if (cpu_has_load_perf_global_ctrl) {
-                        add_atomic_switch_msr_special(
+                        add_atomic_switch_msr_special(vmx,
                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
                                         GUEST_IA32_PERF_GLOBAL_CTRL,
@@ -1906,7 +1969,9 @@ static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
         if (!(vmcs12->exception_bitmap & (1u << nr)))
                 return 0;
 
-        nested_vmx_vmexit(vcpu);
+        nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
+                          vmcs_read32(VM_EXIT_INTR_INFO),
+                          vmcs_readl(EXIT_QUALIFICATION));
         return 1;
 }
 
@@ -2279,6 +2344,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
                 VMX_MISC_SAVE_EFER_LMA;
+        nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
         nested_vmx_misc_high = 0;
 }
 
@@ -2295,32 +2361,10 @@ static inline u64 vmx_control_msr(u32 low, u32 high)
         return low | ((u64)high << 32);
 }
 
-/*
- * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
- * also let it use VMX-specific MSRs.
- * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
- * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
- * like all other MSRs).
- */
+/* Returns 0 on success, non-0 otherwise. */
 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 {
-        if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
-                     msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
-                /*
-                 * According to the spec, processors which do not support VMX
-                 * should throw a #GP(0) when VMX capability MSRs are read.
-                 */
-                kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
-                return 1;
-        }
-
         switch (msr_index) {
-        case MSR_IA32_FEATURE_CONTROL:
-                if (nested_vmx_allowed(vcpu)) {
-                        *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
-                        break;
-                }
-                return 0;
         case MSR_IA32_VMX_BASIC:
                 /*
                  * This MSR reports some information about VMX support. We
@@ -2387,34 +2431,9 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
                 *pdata = nested_vmx_ept_caps;
                 break;
         default:
-                return 0;
-        }
-
-        return 1;
-}
-
-static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
-{
-        u32 msr_index = msr_info->index;
-        u64 data = msr_info->data;
-        bool host_initialized = msr_info->host_initiated;
-
-        if (!nested_vmx_allowed(vcpu))
-                return 0;
-
-        if (msr_index == MSR_IA32_FEATURE_CONTROL) {
-                if (!host_initialized &&
-                                to_vmx(vcpu)->nested.msr_ia32_feature_control
-                                & FEATURE_CONTROL_LOCKED)
-                        return 0;
-                to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
                 return 1;
         }
 
-        /*
-         * No need to treat VMX capability MSRs specially: If we don't handle
-         * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
-         */
         return 0;
 }
 
@@ -2460,13 +2479,20 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
         case MSR_IA32_SYSENTER_ESP:
                 data = vmcs_readl(GUEST_SYSENTER_ESP);
                 break;
+        case MSR_IA32_FEATURE_CONTROL:
+                if (!nested_vmx_allowed(vcpu))
+                        return 1;
+                data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
+                break;
+        case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
+                if (!nested_vmx_allowed(vcpu))
+                        return 1;
+                return vmx_get_vmx_msr(vcpu, msr_index, pdata);
         case MSR_TSC_AUX:
                 if (!to_vmx(vcpu)->rdtscp_enabled)
                         return 1;
                 /* Otherwise falls through */
         default:
-                if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
-                        return 0;
                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
                 if (msr) {
                         data = msr->data;
@@ -2479,6 +2505,8 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
         return 0;
 }
 
+static void vmx_leave_nested(struct kvm_vcpu *vcpu);
+
 /*
  * Writes msr value into into the appropriate "register".
  * Returns 0 on success, non-0 otherwise.
@@ -2533,6 +2561,17 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
         case MSR_IA32_TSC_ADJUST:
                 ret = kvm_set_msr_common(vcpu, msr_info);
                 break;
+        case MSR_IA32_FEATURE_CONTROL:
+                if (!nested_vmx_allowed(vcpu) ||
+                    (to_vmx(vcpu)->nested.msr_ia32_feature_control &
+                     FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
+                        return 1;
+                vmx->nested.msr_ia32_feature_control = data;
+                if (msr_info->host_initiated && data == 0)
+                        vmx_leave_nested(vcpu);
+                break;
+        case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
+                return 1; /* they are read-only */
         case MSR_TSC_AUX:
                 if (!vmx->rdtscp_enabled)
                         return 1;
@@ -2541,8 +2580,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                         return 1;
                 /* Otherwise falls through */
         default:
-                if (vmx_set_vmx_msr(vcpu, msr_info))
-                        break;
                 msr = find_msr_entry(vmx, msr_index);
                 if (msr) {
                         msr->data = data;
@@ -3182,14 +3219,10 @@ static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
         vmx_load_host_state(to_vmx(vcpu));
         vcpu->arch.efer = efer;
         if (efer & EFER_LMA) {
-                vmcs_write32(VM_ENTRY_CONTROLS,
-                             vmcs_read32(VM_ENTRY_CONTROLS) |
-                             VM_ENTRY_IA32E_MODE);
+                vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
                 msr->data = efer;
         } else {
-                vmcs_write32(VM_ENTRY_CONTROLS,
-                             vmcs_read32(VM_ENTRY_CONTROLS) &
-                             ~VM_ENTRY_IA32E_MODE);
+                vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
 
                 msr->data = efer & ~EFER_LME;
         }
@@ -3217,9 +3250,7 @@ static void enter_lmode(struct kvm_vcpu *vcpu)
 
 static void exit_lmode(struct kvm_vcpu *vcpu)
 {
-        vmcs_write32(VM_ENTRY_CONTROLS,
-                     vmcs_read32(VM_ENTRY_CONTROLS)
-                     & ~VM_ENTRY_IA32E_MODE);
+        vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
 }
 
@@ -4346,10 +4377,11 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
                 ++vmx->nmsrs;
         }
 
-        vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
+
+        vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
 
         /* 22.2.1, 20.8.1 */
-        vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
+        vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
 
         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
         set_cr4_guest_host_mask(vmx);
@@ -4360,7 +4392,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
-        u64 msr;
+        struct msr_data apic_base_msr;
 
         vmx->rmode.vm86_active = 0;
 
@@ -4368,10 +4400,11 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 
         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
         kvm_set_cr8(&vmx->vcpu, 0);
-        msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
+        apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
         if (kvm_vcpu_is_bsp(&vmx->vcpu))
-                msr |= MSR_IA32_APICBASE_BSP;
-        kvm_set_apic_base(&vmx->vcpu, msr);
+                apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
+        apic_base_msr.host_initiated = true;
+        kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
 
         vmx_segment_cache_clear(vmx);
 
@@ -4588,15 +4621,12 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
 {
         if (is_guest_mode(vcpu)) {
-                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-
                 if (to_vmx(vcpu)->nested.nested_run_pending)
                         return 0;
                 if (nested_exit_on_nmi(vcpu)) {
-                        nested_vmx_vmexit(vcpu);
-                        vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
-                        vmcs12->vm_exit_intr_info = NMI_VECTOR |
-                                INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
+                        nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
+                                          NMI_VECTOR | INTR_TYPE_NMI_INTR |
+                                          INTR_INFO_VALID_MASK, 0);
                         /*
                          * The NMI-triggered VM exit counts as injection:
                          * clear this one and block further NMIs.
@@ -4618,15 +4648,11 @@ static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
 {
         if (is_guest_mode(vcpu)) {
-                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-
                 if (to_vmx(vcpu)->nested.nested_run_pending)
                         return 0;
                 if (nested_exit_on_intr(vcpu)) {
-                        nested_vmx_vmexit(vcpu);
-                        vmcs12->vm_exit_reason =
-                                EXIT_REASON_EXTERNAL_INTERRUPT;
-                        vmcs12->vm_exit_intr_info = 0;
+                        nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
+                                          0, 0);
                         /*
                          * fall through to normal code, but now in L1, not L2
                          */
@@ -4812,7 +4838,8 @@ static int handle_exception(struct kvm_vcpu *vcpu)
                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
                 if (!(vcpu->guest_debug &
                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
-                        vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
+                        vcpu->arch.dr6 &= ~15;
+                        vcpu->arch.dr6 |= dr6;
                         kvm_queue_exception(vcpu, DB_VECTOR);
                         return 1;
                 }
@@ -5080,14 +5107,27 @@ static int handle_dr(struct kvm_vcpu *vcpu)
         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
         if (exit_qualification & TYPE_MOV_FROM_DR) {
                 unsigned long val;
-                if (!kvm_get_dr(vcpu, dr, &val))
-                        kvm_register_write(vcpu, reg, val);
+
+                if (kvm_get_dr(vcpu, dr, &val))
+                        return 1;
+                kvm_register_write(vcpu, reg, val);
         } else
-                kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
+                if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
+                        return 1;
+
         skip_emulated_instruction(vcpu);
         return 1;
 }
 
+static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.dr6;
+}
+
+static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
+{
+}
+
 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
 {
         vmcs_writel(GUEST_DR7, val);
@@ -6460,11 +6500,8 @@ static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
         int size;
         u8 b;
 
-        if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
-                return 1;
-
         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
-                return 0;
+                return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
 
         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 
@@ -6628,6 +6665,13 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
         u32 exit_reason = vmx->exit_reason;
 
+        trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
+                                vmcs_readl(EXIT_QUALIFICATION),
+                                vmx->idt_vectoring_info,
+                                intr_info,
+                                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
+                                KVM_ISA_VMX);
+
         if (vmx->nested.nested_run_pending)
                 return 0;
 
@@ -6777,7 +6821,9 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
                 return handle_invalid_guest_state(vcpu);
 
         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
-                nested_vmx_vmexit(vcpu);
+                nested_vmx_vmexit(vcpu, exit_reason,
+                                  vmcs_read32(VM_EXIT_INTR_INFO),
+                                  vmcs_readl(EXIT_QUALIFICATION));
                 return 1;
         }
 
@@ -7332,8 +7378,8 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
         struct vcpu_vmx *vmx = to_vmx(vcpu);
 
         free_vpid(vmx);
-        free_nested(vmx);
         free_loaded_vmcs(vmx->loaded_vmcs);
+        free_nested(vmx);
         kfree(vmx->guest_msrs);
         kvm_vcpu_uninit(vcpu);
         kmem_cache_free(kvm_vcpu_cache, vmx);
@@ -7518,15 +7564,14 @@ static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
                 struct x86_exception *fault)
 {
-        struct vmcs12 *vmcs12;
-        nested_vmx_vmexit(vcpu);
-        vmcs12 = get_vmcs12(vcpu);
+        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+        u32 exit_reason;
 
         if (fault->error_code & PFERR_RSVD_MASK)
-                vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
+                exit_reason = EXIT_REASON_EPT_MISCONFIG;
         else
-                vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
-        vmcs12->exit_qualification = vcpu->arch.exit_qualification;
+                exit_reason = EXIT_REASON_EPT_VIOLATION;
+        nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
         vmcs12->guest_physical_address = fault->address;
 }
 
@@ -7564,7 +7609,9 @@ static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
 
         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
-                nested_vmx_vmexit(vcpu);
+                nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
+                                  vmcs_read32(VM_EXIT_INTR_INFO),
+                                  vmcs_readl(EXIT_QUALIFICATION));
         else
                 kvm_inject_page_fault(vcpu, fault);
 }
@@ -7706,6 +7753,11 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                         else
                                 vmcs_write64(APIC_ACCESS_ADDR,
                                   page_to_phys(vmx->nested.apic_access_page));
+                } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
+                        exec_control |=
+                                SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+                        vmcs_write64(APIC_ACCESS_ADDR,
+                                page_to_phys(vcpu->kvm->arch.apic_access_page));
                 }
 
                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
@@ -7759,12 +7811,12 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
         exit_control = vmcs_config.vmexit_ctrl;
         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
                 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
-        vmcs_write32(VM_EXIT_CONTROLS, exit_control);
+        vm_exit_controls_init(vmx, exit_control);
 
         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
          * emulated by vmx_set_efer(), below.
          */
-        vmcs_write32(VM_ENTRY_CONTROLS,
+        vm_entry_controls_init(vmx, 
                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
                         ~VM_ENTRY_IA32E_MODE) |
                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
@@ -7882,7 +7934,8 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
                 return 1;
         }
 
-        if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
+        if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
+            vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
                 return 1;
         }
@@ -7994,8 +8047,6 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
 
         enter_guest_mode(vcpu);
 
-        vmx->nested.nested_run_pending = 1;
-
         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
 
         cpu = get_cpu();
@@ -8011,6 +8062,11 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
 
         prepare_vmcs02(vcpu, vmcs12);
 
+        if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
+                return kvm_emulate_halt(vcpu);
+
+        vmx->nested.nested_run_pending = 1;
+
         /*
          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
@@ -8110,7 +8166,9 @@ static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
  * which already writes to vmcs12 directly.
  */
-static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
+static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
+                           u32 exit_reason, u32 exit_intr_info,
+                           unsigned long exit_qualification)
 {
         /* update guest state fields: */
         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
@@ -8162,6 +8220,10 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
         vmcs12->guest_pending_dbg_exceptions =
                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
+        if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
+                vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
+        else
+                vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
 
         if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
             (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
@@ -8186,7 +8248,7 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
         vmcs12->vm_entry_controls =
                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
-                (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
+                (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
 
         /* TODO: These cannot have changed unless we have MSR bitmaps and
          * the relevant bit asks not to trap the change */
@@ -8201,10 +8263,10 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
         /* update exit information fields: */
 
-        vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
-        vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
+        vmcs12->vm_exit_reason = exit_reason;
+        vmcs12->exit_qualification = exit_qualification;
 
-        vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
+        vmcs12->vm_exit_intr_info = exit_intr_info;
         if ((vmcs12->vm_exit_intr_info &
              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
@@ -8370,7 +8432,9 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
  * and modify vmcs12 to make it see what it would expect to see there if
  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
  */
-static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
+static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
+                              u32 exit_intr_info,
+                              unsigned long exit_qualification)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         int cpu;
@@ -8380,7 +8444,15 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
         WARN_ON_ONCE(vmx->nested.nested_run_pending);
 
         leave_guest_mode(vcpu);
-        prepare_vmcs12(vcpu, vmcs12);
+        prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
+                       exit_qualification);
+
+        trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
+                                       vmcs12->exit_qualification,
+                                       vmcs12->idt_vectoring_info_field,
+                                       vmcs12->vm_exit_intr_info,
+                                       vmcs12->vm_exit_intr_error_code,
+                                       KVM_ISA_VMX);
 
         cpu = get_cpu();
         vmx->loaded_vmcs = &vmx->vmcs01;
@@ -8389,6 +8461,8 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
         vcpu->cpu = cpu;
         put_cpu();
 
+        vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
+        vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
         vmx_segment_cache_clear(vmx);
 
         /* if no vmcs02 cache requested, remove the one we used */
@@ -8424,6 +8498,16 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
 }
 
 /*
+ * Forcibly leave nested mode in order to be able to reset the VCPU later on.
+ */
+static void vmx_leave_nested(struct kvm_vcpu *vcpu)
+{
+        if (is_guest_mode(vcpu))
+                nested_vmx_vmexit(vcpu, -1, 0, 0);
+        free_nested(to_vmx(vcpu));
+}
+
+/*
  * L1's failure to enter L2 is a subset of a normal exit, as explained in
  * 23.7 "VM-entry failures during or after loading guest state" (this also
  * lists the acceptable exit-reason and exit-qualification parameters).
@@ -8486,6 +8570,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .set_idt = vmx_set_idt,
         .get_gdt = vmx_get_gdt,
         .set_gdt = vmx_set_gdt,
+        .get_dr6 = vmx_get_dr6,
+        .set_dr6 = vmx_set_dr6,
         .set_dr7 = vmx_set_dr7,
         .cache_reg = vmx_cache_reg,
         .get_rflags = vmx_get_rflags,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 5d004da1e35d..39c28f09dfd5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -94,6 +94,9 @@ EXPORT_SYMBOL_GPL(kvm_x86_ops);
 static bool ignore_msrs = 0;
 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 
+unsigned int min_timer_period_us = 500;
+module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
+
 bool kvm_has_tsc_control;
 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 u32  kvm_max_guest_tsc_khz;
@@ -254,10 +257,26 @@ u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 
-void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
-{
-        /* TODO: reserve bits check */
-        kvm_lapic_set_base(vcpu, data);
+int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
+{
+        u64 old_state = vcpu->arch.apic_base &
+                (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
+        u64 new_state = msr_info->data &
+                (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
+        u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
+                0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
+
+        if (!msr_info->host_initiated &&
+            ((msr_info->data & reserved_bits) != 0 ||
+             new_state == X2APIC_ENABLE ||
+             (new_state == MSR_IA32_APICBASE_ENABLE &&
+              old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
+             (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
+              old_state == 0)))
+                return 1;
+
+        kvm_lapic_set_base(vcpu, msr_info->data);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 
@@ -719,6 +738,12 @@ unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 
+static void kvm_update_dr6(struct kvm_vcpu *vcpu)
+{
+        if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
+                kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
+}
+
 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
 {
         unsigned long dr7;
@@ -747,6 +772,7 @@ static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
                 if (val & 0xffffffff00000000ULL)
                         return -1; /* #GP */
                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
+                kvm_update_dr6(vcpu);
                 break;
         case 5:
                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
@@ -788,7 +814,10 @@ static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
                         return 1;
                 /* fall through */
         case 6:
-                *val = vcpu->arch.dr6;
+                if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
+                        *val = vcpu->arch.dr6;
+                else
+                        *val = kvm_x86_ops->get_dr6(vcpu);
                 break;
         case 5:
                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
@@ -836,11 +865,12 @@ EXPORT_SYMBOL_GPL(kvm_rdpmc);
  * kvm-specific. Those are put in the beginning of the list.
  */
 
-#define KVM_SAVE_MSRS_BEGIN     10
+#define KVM_SAVE_MSRS_BEGIN     12
 static u32 msrs_to_save[] = {
         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
+        HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
         MSR_KVM_PV_EOI_EN,
         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
@@ -1275,8 +1305,6 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
         kvm->arch.last_tsc_write = data;
         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
 
-        /* Reset of TSC must disable overshoot protection below */
-        vcpu->arch.hv_clock.tsc_timestamp = 0;
         vcpu->arch.last_guest_tsc = data;
 
         /* Keep track of which generation this VCPU has synchronized to */
@@ -1484,7 +1512,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         unsigned long flags, this_tsc_khz;
         struct kvm_vcpu_arch *vcpu = &v->arch;
         struct kvm_arch *ka = &v->kvm->arch;
-        s64 kernel_ns, max_kernel_ns;
+        s64 kernel_ns;
         u64 tsc_timestamp, host_tsc;
         struct pvclock_vcpu_time_info guest_hv_clock;
         u8 pvclock_flags;
@@ -1543,37 +1571,6 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         if (!vcpu->pv_time_enabled)
                 return 0;
 
-        /*
-         * Time as measured by the TSC may go backwards when resetting the base
-         * tsc_timestamp.  The reason for this is that the TSC resolution is
-         * higher than the resolution of the other clock scales.  Thus, many
-         * possible measurments of the TSC correspond to one measurement of any
-         * other clock, and so a spread of values is possible.  This is not a
-         * problem for the computation of the nanosecond clock; with TSC rates
-         * around 1GHZ, there can only be a few cycles which correspond to one
-         * nanosecond value, and any path through this code will inevitably
-         * take longer than that.  However, with the kernel_ns value itself,
-         * the precision may be much lower, down to HZ granularity.  If the
-         * first sampling of TSC against kernel_ns ends in the low part of the
-         * range, and the second in the high end of the range, we can get:
-         *
-         * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
-         *
-         * As the sampling errors potentially range in the thousands of cycles,
-         * it is possible such a time value has already been observed by the
-         * guest.  To protect against this, we must compute the system time as
-         * observed by the guest and ensure the new system time is greater.
-         */
-        max_kernel_ns = 0;
-        if (vcpu->hv_clock.tsc_timestamp) {
-                max_kernel_ns = vcpu->last_guest_tsc -
-                                vcpu->hv_clock.tsc_timestamp;
-                max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
-                                    vcpu->hv_clock.tsc_to_system_mul,
-                                    vcpu->hv_clock.tsc_shift);
-                max_kernel_ns += vcpu->last_kernel_ns;
-        }
-
         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
                                    &vcpu->hv_clock.tsc_shift,
@@ -1581,14 +1578,6 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
                 vcpu->hw_tsc_khz = this_tsc_khz;
         }
 
-        /* with a master <monotonic time, tsc value> tuple,
-         * pvclock clock reads always increase at the (scaled) rate
-         * of guest TSC - no need to deal with sampling errors.
-         */
-        if (!use_master_clock) {
-                if (max_kernel_ns > kernel_ns)
-                        kernel_ns = max_kernel_ns;
-        }
         /* With all the info we got, fill in the values */
         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
@@ -1826,6 +1815,8 @@ static bool kvm_hv_msr_partition_wide(u32 msr)
         switch (msr) {
         case HV_X64_MSR_GUEST_OS_ID:
         case HV_X64_MSR_HYPERCALL:
+        case HV_X64_MSR_REFERENCE_TSC:
+        case HV_X64_MSR_TIME_REF_COUNT:
                 r = true;
                 break;
         }
@@ -1865,6 +1856,21 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 if (__copy_to_user((void __user *)addr, instructions, 4))
                         return 1;
                 kvm->arch.hv_hypercall = data;
+                mark_page_dirty(kvm, gfn);
+                break;
+        }
+        case HV_X64_MSR_REFERENCE_TSC: {
+                u64 gfn;
+                HV_REFERENCE_TSC_PAGE tsc_ref;
+                memset(&tsc_ref, 0, sizeof(tsc_ref));
+                kvm->arch.hv_tsc_page = data;
+                if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
+                        break;
+                gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
+                if (kvm_write_guest(kvm, data,
+                        &tsc_ref, sizeof(tsc_ref)))
+                        return 1;
+                mark_page_dirty(kvm, gfn);
                 break;
         }
         default:
@@ -1879,19 +1885,21 @@ static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 {
         switch (msr) {
         case HV_X64_MSR_APIC_ASSIST_PAGE: {
+                u64 gfn;
                 unsigned long addr;
 
                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
                         vcpu->arch.hv_vapic = data;
                         break;
                 }
-                addr = gfn_to_hva(vcpu->kvm, data >>
-                                  HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
+                gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
+                addr = gfn_to_hva(vcpu->kvm, gfn);
                 if (kvm_is_error_hva(addr))
                         return 1;
                 if (__clear_user((void __user *)addr, PAGE_SIZE))
                         return 1;
                 vcpu->arch.hv_vapic = data;
+                mark_page_dirty(vcpu->kvm, gfn);
                 break;
         }
         case HV_X64_MSR_EOI:
@@ -2017,8 +2025,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
         case 0x200 ... 0x2ff:
                 return set_msr_mtrr(vcpu, msr, data);
         case MSR_IA32_APICBASE:
-                kvm_set_apic_base(vcpu, data);
-                break;
+                return kvm_set_apic_base(vcpu, msr_info);
         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
                 return kvm_x2apic_msr_write(vcpu, msr, data);
         case MSR_IA32_TSCDEADLINE:
@@ -2291,6 +2298,14 @@ static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
         case HV_X64_MSR_HYPERCALL:
                 data = kvm->arch.hv_hypercall;
                 break;
+        case HV_X64_MSR_TIME_REF_COUNT: {
+                data =
+                     div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
+                break;
+        }
+        case HV_X64_MSR_REFERENCE_TSC:
+                data = kvm->arch.hv_tsc_page;
+                break;
         default:
                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
                 return 1;
@@ -2601,6 +2616,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_GET_TSC_KHZ:
         case KVM_CAP_KVMCLOCK_CTRL:
         case KVM_CAP_READONLY_MEM:
+        case KVM_CAP_HYPERV_TIME:
 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
         case KVM_CAP_ASSIGN_DEV_IRQ:
         case KVM_CAP_PCI_2_3:
@@ -2972,8 +2988,11 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
                                              struct kvm_debugregs *dbgregs)
 {
+        unsigned long val;
+
         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
-        dbgregs->dr6 = vcpu->arch.dr6;
+        _kvm_get_dr(vcpu, 6, &val);
+        dbgregs->dr6 = val;
         dbgregs->dr7 = vcpu->arch.dr7;
         dbgregs->flags = 0;
         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
@@ -2987,7 +3006,9 @@ static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
 
         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
         vcpu->arch.dr6 = dbgregs->dr6;
+        kvm_update_dr6(vcpu);
         vcpu->arch.dr7 = dbgregs->dr7;
+        kvm_update_dr7(vcpu);
 
         return 0;
 }
@@ -5834,6 +5855,11 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
         kvm_apic_update_tmr(vcpu, tmr);
 }
 
+/*
+ * Returns 1 to let __vcpu_run() continue the guest execution loop without
+ * exiting to the userspace.  Otherwise, the value will be returned to the
+ * userspace.
+ */
 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
 {
         int r;
@@ -6089,7 +6115,7 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                 }
                 if (need_resched()) {
                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
-                        kvm_resched(vcpu);
+                        cond_resched();
                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
                 }
         }
@@ -6401,6 +6427,7 @@ EXPORT_SYMBOL_GPL(kvm_task_switch);
 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
                                   struct kvm_sregs *sregs)
 {
+        struct msr_data apic_base_msr;
         int mmu_reset_needed = 0;
         int pending_vec, max_bits, idx;
         struct desc_ptr dt;
@@ -6424,7 +6451,9 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
 
         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
         kvm_x86_ops->set_efer(vcpu, sregs->efer);
-        kvm_set_apic_base(vcpu, sregs->apic_base);
+        apic_base_msr.data = sregs->apic_base;
+        apic_base_msr.host_initiated = true;
+        kvm_set_apic_base(vcpu, &apic_base_msr);
 
         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
@@ -6717,6 +6746,7 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
 
         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
         vcpu->arch.dr6 = DR6_FIXED_1;
+        kvm_update_dr6(vcpu);
         vcpu->arch.dr7 = DR7_FIXED_1;
         kvm_update_dr7(vcpu);
 
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 587fb9ede436..8da5823bcde6 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -125,5 +125,7 @@ int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
 #define KVM_SUPPORTED_XCR0      (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
 extern u64 host_xcr0;
 
+extern unsigned int min_timer_period_us;
+
 extern struct static_key kvm_no_apic_vcpu;
 #endif
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index bdf8532494fe..ad1fb5f53925 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -233,13 +233,13 @@ static void lguest_end_context_switch(struct task_struct *next)
  * flags word contains all kind of stuff, but in practice Linux only cares
  * about the interrupt flag.  Our "save_flags()" just returns that.
  */
-static unsigned long save_fl(void)
+asmlinkage unsigned long lguest_save_fl(void)
 {
         return lguest_data.irq_enabled;
 }
 
 /* Interrupts go off... */
-static void irq_disable(void)
+asmlinkage void lguest_irq_disable(void)
 {
         lguest_data.irq_enabled = 0;
 }
@@ -253,8 +253,8 @@ static void irq_disable(void)
  * PV_CALLEE_SAVE_REGS_THUNK(), which pushes %eax onto the stack, calls the
  * C function, then restores it.
  */
-PV_CALLEE_SAVE_REGS_THUNK(save_fl);
-PV_CALLEE_SAVE_REGS_THUNK(irq_disable);
+PV_CALLEE_SAVE_REGS_THUNK(lguest_save_fl);
+PV_CALLEE_SAVE_REGS_THUNK(lguest_irq_disable);
 /*:*/
 
 /* These are in i386_head.S */
@@ -1291,9 +1291,9 @@ __init void lguest_init(void)
          */
 
         /* Interrupt-related operations */
-        pv_irq_ops.save_fl = PV_CALLEE_SAVE(save_fl);
+        pv_irq_ops.save_fl = PV_CALLEE_SAVE(lguest_save_fl);
         pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(lg_restore_fl);
-        pv_irq_ops.irq_disable = PV_CALLEE_SAVE(irq_disable);
+        pv_irq_ops.irq_disable = PV_CALLEE_SAVE(lguest_irq_disable);
         pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(lg_irq_enable);
         pv_irq_ops.safe_halt = lguest_safe_halt;
 
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 992d63bb154f..eabcb6e6a900 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -24,7 +24,7 @@ lib-$(CONFIG_SMP) += rwlock.o
 lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
 lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o
 
-obj-y += msr.o msr-reg.o msr-reg-export.o
+obj-y += msr.o msr-reg.o msr-reg-export.o hash.o
 
 ifeq ($(CONFIG_X86_32),y)
         obj-y += atomic64_32.o
diff --git a/arch/x86/lib/hash.c b/arch/x86/lib/hash.c
new file mode 100644
index 000000000000..3056702e81fb
--- /dev/null
+++ b/arch/x86/lib/hash.c
@@ -0,0 +1,88 @@
+/*
+ * Some portions derived from code covered by the following notice:
+ *
+ * Copyright (c) 2010-2013 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/hash.h>
+
+#include <asm/processor.h>
+#include <asm/cpufeature.h>
+#include <asm/hash.h>
+
+static inline u32 crc32_u32(u32 crc, u32 val)
+{
+        asm ("crc32l %1,%0\n" : "+r" (crc) : "rm" (val));
+        return crc;
+}
+
+static u32 intel_crc4_2_hash(const void *data, u32 len, u32 seed)
+{
+        const u32 *p32 = (const u32 *) data;
+        u32 i, tmp = 0;
+
+        for (i = 0; i < len / 4; i++)
+                seed = crc32_u32(*p32++, seed);
+
+        switch (3 - (len & 0x03)) {
+        case 0:
+                tmp |= *((const u8 *) p32 + 2) << 16;
+                /* fallthrough */
+        case 1:
+                tmp |= *((const u8 *) p32 + 1) << 8;
+                /* fallthrough */
+        case 2:
+                tmp |= *((const u8 *) p32);
+                seed = crc32_u32(tmp, seed);
+        default:
+                break;
+        }
+
+        return seed;
+}
+
+static u32 intel_crc4_2_hash2(const u32 *data, u32 len, u32 seed)
+{
+        const u32 *p32 = (const u32 *) data;
+        u32 i;
+
+        for (i = 0; i < len; i++)
+                seed = crc32_u32(*p32++, seed);
+
+        return seed;
+}
+
+void setup_arch_fast_hash(struct fast_hash_ops *ops)
+{
+        if (cpu_has_xmm4_2) {
+                ops->hash  = intel_crc4_2_hash;
+                ops->hash2 = intel_crc4_2_hash2;
+        }
+}
diff --git a/arch/x86/math-emu/errors.c b/arch/x86/math-emu/errors.c
index 59d353d2c599..a5449089cd9f 100644
--- a/arch/x86/math-emu/errors.c
+++ b/arch/x86/math-emu/errors.c
@@ -330,11 +330,6 @@ asmlinkage void FPU_exception(int n)
 
         RE_ENTRANT_CHECK_OFF;
         if ((~control_word & n & CW_Exceptions) || (n == EX_INTERNAL)) {
-#ifdef PRINT_MESSAGES
-                /* My message from the sponsor */
-                printk(FPU_VERSION " " __DATE__ " (C) W. Metzenthen.\n");
-#endif /* PRINT_MESSAGES */
-
                 /* Get a name string for error reporting */
                 for (i = 0; exception_names[i].type; i++)
                         if ((exception_names[i].type & n) ==
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index 0596e8e0cc19..207d9aef662d 100644
--- a/arch/x86/mm/gup.c
+++ b/arch/x86/mm/gup.c
@@ -108,8 +108,8 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
 
 static inline void get_head_page_multiple(struct page *page, int nr)
 {
-        VM_BUG_ON(page != compound_head(page));
-        VM_BUG_ON(page_count(page) == 0);
+        VM_BUG_ON_PAGE(page != compound_head(page), page);
+        VM_BUG_ON_PAGE(page_count(page) == 0, page);
         atomic_add(nr, &page->_count);
         SetPageReferenced(page);
 }
@@ -135,7 +135,7 @@ static noinline int gup_huge_pmd(pmd_t pmd, unsigned long addr,
         head = pte_page(pte);
         page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
         do {
-                VM_BUG_ON(compound_head(page) != head);
+                VM_BUG_ON_PAGE(compound_head(page) != head, page);
                 pages[*nr] = page;
                 if (PageTail(page))
                         get_huge_page_tail(page);
@@ -212,7 +212,7 @@ static noinline int gup_huge_pud(pud_t pud, unsigned long addr,
         head = pte_page(pte);
         page = head + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
         do {
-                VM_BUG_ON(compound_head(page) != head);
+                VM_BUG_ON_PAGE(compound_head(page) != head, page);
                 pages[*nr] = page;
                 if (PageTail(page))
                         get_huge_page_tail(page);
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 5bdc5430597c..e39504878aec 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -665,7 +665,7 @@ void __init initmem_init(void)
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
 #endif
 
-        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
+        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
         sparse_memory_present_with_active_regions(0);
 
 #ifdef CONFIG_FLATMEM
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 104d56a9245f..f35c66c5959a 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -643,7 +643,7 @@ kernel_physical_mapping_init(unsigned long start,
 #ifndef CONFIG_NUMA
 void __init initmem_init(void)
 {
-        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
+        memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
 }
 #endif
 
diff --git a/arch/x86/mm/memtest.c b/arch/x86/mm/memtest.c
index 8dabbed409ee..1e9da795767a 100644
--- a/arch/x86/mm/memtest.c
+++ b/arch/x86/mm/memtest.c
@@ -74,7 +74,7 @@ static void __init do_one_pass(u64 pattern, u64 start, u64 end)
         u64 i;
         phys_addr_t this_start, this_end;
 
-        for_each_free_mem_range(i, MAX_NUMNODES, &this_start, &this_end, NULL) {
+        for_each_free_mem_range(i, NUMA_NO_NODE, &this_start, &this_end, NULL) {
                 this_start = clamp_t(phys_addr_t, this_start, start, end);
                 this_end = clamp_t(phys_addr_t, this_end, start, end);
                 if (this_start < this_end) {
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index c85da7bb6b60..81b2750f3666 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -491,7 +491,16 @@ static int __init numa_register_memblks(struct numa_meminfo *mi)
 
         for (i = 0; i < mi->nr_blks; i++) {
                 struct numa_memblk *mb = &mi->blk[i];
-                memblock_set_node(mb->start, mb->end - mb->start, mb->nid);
+                memblock_set_node(mb->start, mb->end - mb->start,
+                                  &memblock.memory, mb->nid);
+
+                /*
+                 * At this time, all memory regions reserved by memblock are
+                 * used by the kernel. Set the nid in memblock.reserved will
+                 * mark out all the nodes the kernel resides in.
+                 */
+                memblock_set_node(mb->start, mb->end - mb->start,
+                                  &memblock.reserved, mb->nid);
         }
 
         /*
@@ -553,6 +562,30 @@ static void __init numa_init_array(void)
         }
 }
 
+static void __init numa_clear_kernel_node_hotplug(void)
+{
+        int i, nid;
+        nodemask_t numa_kernel_nodes;
+        unsigned long start, end;
+        struct memblock_type *type = &memblock.reserved;
+
+        /* Mark all kernel nodes. */
+        for (i = 0; i < type->cnt; i++)
+                node_set(type->regions[i].nid, numa_kernel_nodes);
+
+        /* Clear MEMBLOCK_HOTPLUG flag for memory in kernel nodes. */
+        for (i = 0; i < numa_meminfo.nr_blks; i++) {
+                nid = numa_meminfo.blk[i].nid;
+                if (!node_isset(nid, numa_kernel_nodes))
+                        continue;
+
+                start = numa_meminfo.blk[i].start;
+                end = numa_meminfo.blk[i].end;
+
+                memblock_clear_hotplug(start, end - start);
+        }
+}
+
 static int __init numa_init(int (*init_func)(void))
 {
         int i;
@@ -565,7 +598,12 @@ static int __init numa_init(int (*init_func)(void))
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
         memset(&numa_meminfo, 0, sizeof(numa_meminfo));
-        WARN_ON(memblock_set_node(0, ULLONG_MAX, MAX_NUMNODES));
+        WARN_ON(memblock_set_node(0, ULLONG_MAX, &memblock.memory,
+                                  MAX_NUMNODES));
+        WARN_ON(memblock_set_node(0, ULLONG_MAX, &memblock.reserved,
+                                  MAX_NUMNODES));
+        /* In case that parsing SRAT failed. */
+        WARN_ON(memblock_clear_hotplug(0, ULLONG_MAX));
         numa_reset_distance();
 
         ret = init_func();
@@ -601,6 +639,16 @@ static int __init numa_init(int (*init_func)(void))
                         numa_clear_node(i);
         }
         numa_init_array();
+
+        /*
+         * At very early time, the kernel have to use some memory such as
+         * loading the kernel image. We cannot prevent this anyway. So any
+         * node the kernel resides in should be un-hotpluggable.
+         *
+         * And when we come here, numa_init() won't fail.
+         */
+        numa_clear_kernel_node_hotplug();
+
         return 0;
 }
 
diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c
index 5ecf65117e6f..1953e9c9391a 100644
--- a/arch/x86/mm/srat.c
+++ b/arch/x86/mm/srat.c
@@ -191,6 +191,11 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
                 (unsigned long long) start, (unsigned long long) end - 1,
                 hotpluggable ? " hotplug" : "");
 
+        /* Mark hotplug range in memblock. */
+        if (hotpluggable && memblock_mark_hotplug(start, ma->length))
+                pr_warn("SRAT: Failed to mark hotplug range [mem %#010Lx-%#010Lx] in memblock\n",
+                        (unsigned long long)start, (unsigned long long)end - 1);
+
         return 0;
 out_err_bad_srat:
         bad_srat();
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 082e88129712..248642f4bab7 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -12,7 +12,6 @@
 
 #include <linux/pci.h>
 #include <linux/init.h>
-#include <linux/acpi.h>
 #include <linux/sfi_acpi.h>
 #include <linux/bitmap.h>
 #include <linux/dmi.h>
diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c
index 5c90975cdf0f..43984bc1665a 100644
--- a/arch/x86/pci/mmconfig_32.c
+++ b/arch/x86/pci/mmconfig_32.c
@@ -14,7 +14,6 @@
 #include <linux/rcupdate.h>
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
-#include <acpi/acpi.h>
 
 /* Assume systems with more busses have correct MCFG */
 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 5eee4959785d..103e702ec5a7 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -337,7 +337,7 @@ out:
         return ret;
 }
 
-static void xen_initdom_restore_msi_irqs(struct pci_dev *dev, int irq)
+static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
 {
         int ret = 0;
 
diff --git a/arch/x86/platform/efi/efi-bgrt.c b/arch/x86/platform/efi/efi-bgrt.c
index 7145ec63c520..4df9591eadad 100644
--- a/arch/x86/platform/efi/efi-bgrt.c
+++ b/arch/x86/platform/efi/efi-bgrt.c
@@ -49,7 +49,8 @@ void __init efi_bgrt_init(void)
 
         image = efi_lookup_mapped_addr(bgrt_tab->image_address);
         if (!image) {
-                image = ioremap(bgrt_tab->image_address, sizeof(bmp_header));
+                image = early_memremap(bgrt_tab->image_address,
+                                       sizeof(bmp_header));
                 ioremapped = true;
                 if (!image)
                         return;
@@ -57,7 +58,7 @@ void __init efi_bgrt_init(void)
 
         memcpy_fromio(&bmp_header, image, sizeof(bmp_header));
         if (ioremapped)
-                iounmap(image);
+                early_iounmap(image, sizeof(bmp_header));
         bgrt_image_size = bmp_header.size;
 
         bgrt_image = kmalloc(bgrt_image_size, GFP_KERNEL);
@@ -65,7 +66,8 @@ void __init efi_bgrt_init(void)
                 return;
 
         if (ioremapped) {
-                image = ioremap(bgrt_tab->image_address, bmp_header.size);
+                image = early_memremap(bgrt_tab->image_address,
+                                       bmp_header.size);
                 if (!image) {
                         kfree(bgrt_image);
                         bgrt_image = NULL;
@@ -75,5 +77,5 @@ void __init efi_bgrt_init(void)
 
         memcpy_fromio(bgrt_image, image, bgrt_image_size);
         if (ioremapped)
-                iounmap(image);
+                early_iounmap(image, bmp_header.size);
 }
diff --git a/arch/x86/platform/intel-mid/device_libs/platform_ipc.h b/arch/x86/platform/intel-mid/device_libs/platform_ipc.h
index 8f568dd79605..79bb09d4f718 100644
--- a/arch/x86/platform/intel-mid/device_libs/platform_ipc.h
+++ b/arch/x86/platform/intel-mid/device_libs/platform_ipc.h
@@ -12,6 +12,7 @@
 #ifndef _PLATFORM_IPC_H_
 #define _PLATFORM_IPC_H_
 
-extern void __init ipc_device_handler(struct sfi_device_table_entry *pentry,
-                        struct devs_id *dev) __attribute__((weak));
+void __init
+ipc_device_handler(struct sfi_device_table_entry *pentry, struct devs_id *dev);
+
 #endif
diff --git a/arch/x86/platform/intel-mid/device_libs/platform_msic.h b/arch/x86/platform/intel-mid/device_libs/platform_msic.h
index 917eb56d77da..b7be1d041da2 100644
--- a/arch/x86/platform/intel-mid/device_libs/platform_msic.h
+++ b/arch/x86/platform/intel-mid/device_libs/platform_msic.h
@@ -14,6 +14,6 @@
 
 extern struct intel_msic_platform_data msic_pdata;
 
-extern void *msic_generic_platform_data(void *info,
-                        enum intel_msic_block block) __attribute__((weak));
+void *msic_generic_platform_data(void *info, enum intel_msic_block block);
+
 #endif
diff --git a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
index a537ffc16299..46aa25c8ce06 100644
--- a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
+++ b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
@@ -14,6 +14,6 @@
 /* For every CPU addition a new get_<cpuname>_ops interface needs
  * to be added.
  */
-extern void * __cpuinit get_penwell_ops(void) __attribute__((weak));
-extern void * __cpuinit get_cloverview_ops(void) __attribute__((weak));
-extern void * __init get_tangier_ops(void) __attribute__((weak));
+extern void *get_penwell_ops(void) __attribute__((weak));
+extern void *get_cloverview_ops(void) __attribute__((weak));
+extern void *get_tangier_ops(void) __attribute__((weak));
diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c
index 4f7884eebc14..23381d2174ae 100644
--- a/arch/x86/platform/intel-mid/mfld.c
+++ b/arch/x86/platform/intel-mid/mfld.c
@@ -58,18 +58,18 @@ static unsigned long __init mfld_calibrate_tsc(void)
         return 0;
 }
 
-static void __init penwell_arch_setup()
+static void __init penwell_arch_setup(void)
 {
         x86_platform.calibrate_tsc = mfld_calibrate_tsc;
         pm_power_off = mfld_power_off;
 }
 
-void * __cpuinit get_penwell_ops()
+void *get_penwell_ops(void)
 {
         return &penwell_ops;
 }
 
-void * __cpuinit get_cloverview_ops()
+void *get_cloverview_ops(void)
 {
         return &penwell_ops;
 }
diff --git a/arch/x86/platform/intel-mid/mrfl.c b/arch/x86/platform/intel-mid/mrfl.c
index 09d10159e7b7..aaca91753d32 100644
--- a/arch/x86/platform/intel-mid/mrfl.c
+++ b/arch/x86/platform/intel-mid/mrfl.c
@@ -97,7 +97,7 @@ static struct intel_mid_ops tangier_ops = {
         .arch_setup = tangier_arch_setup,
 };
 
-void * __cpuinit get_tangier_ops()
+void *get_tangier_ops(void)
 {
         return &tangier_ops;
 }
diff --git a/arch/x86/platform/olpc/olpc-xo15-sci.c b/arch/x86/platform/olpc/olpc-xo15-sci.c
index 649a12befba9..08e350e757dc 100644
--- a/arch/x86/platform/olpc/olpc-xo15-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo15-sci.c
@@ -15,8 +15,7 @@
 #include <linux/power_supply.h>
 #include <linux/olpc-ec.h>
 
-#include <acpi/acpi_bus.h>
-#include <acpi/acpi_drivers.h>
+#include <linux/acpi.h>
 #include <asm/olpc.h>
 
 #define DRV_NAME                        "olpc-xo15-sci"
diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c
index 8eeccba73130..be27da60dc8f 100644
--- a/arch/x86/platform/uv/uv_nmi.c
+++ b/arch/x86/platform/uv/uv_nmi.c
@@ -74,7 +74,6 @@ static atomic_t	uv_in_nmi;
 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
 static atomic_t uv_nmi_cpus_in_nmi = ATOMIC_INIT(-1);
 static atomic_t uv_nmi_slave_continue;
-static atomic_t uv_nmi_kexec_failed;
 static cpumask_var_t uv_nmi_cpu_mask;
 
 /* Values for uv_nmi_slave_continue */
@@ -149,7 +148,8 @@ module_param_named(retry_count, uv_nmi_retry_count, int, 0644);
  *  "dump"      - dump process stack for each cpu
  *  "ips"       - dump IP info for each cpu
  *  "kdump"     - do crash dump
- *  "kdb"       - enter KDB/KGDB (default)
+ *  "kdb"       - enter KDB (default)
+ *  "kgdb"      - enter KGDB
  */
 static char uv_nmi_action[8] = "kdb";
 module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644);
@@ -504,6 +504,7 @@ static void uv_nmi_touch_watchdogs(void)
 }
 
 #if defined(CONFIG_KEXEC)
+static atomic_t uv_nmi_kexec_failed;
 static void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
 {
         /* Call crash to dump system state */
@@ -537,18 +538,45 @@ static inline void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
 }
 #endif /* !CONFIG_KEXEC */
 
+#ifdef CONFIG_KGDB
 #ifdef CONFIG_KGDB_KDB
-/* Call KDB from NMI handler */
-static void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
+static inline int uv_nmi_kdb_reason(void)
 {
-        int ret;
+        return KDB_REASON_SYSTEM_NMI;
+}
+#else /* !CONFIG_KGDB_KDB */
+static inline int uv_nmi_kdb_reason(void)
+{
+        /* Insure user is expecting to attach gdb remote */
+        if (uv_nmi_action_is("kgdb"))
+                return 0;
+
+        pr_err("UV: NMI error: KDB is not enabled in this kernel\n");
+        return -1;
+}
+#endif /* CONFIG_KGDB_KDB */
 
+/*
+ * Call KGDB/KDB from NMI handler
+ *
+ * Note that if both KGDB and KDB are configured, then the action of 'kgdb' or
+ * 'kdb' has no affect on which is used.  See the KGDB documention for further
+ * information.
+ */
+static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
+{
         if (master) {
+                int reason = uv_nmi_kdb_reason();
+                int ret;
+
+                if (reason < 0)
+                        return;
+
                 /* call KGDB NMI handler as MASTER */
-                ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs,
-                                        &uv_nmi_slave_continue);
+                ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs, reason,
+                                &uv_nmi_slave_continue);
                 if (ret) {
-                        pr_alert("KDB returned error, is kgdboc set?\n");
+                        pr_alert("KGDB returned error, is kgdboc set?\n");
                         atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
                 }
         } else {
@@ -567,12 +595,12 @@ static void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
         uv_nmi_sync_exit(master);
 }
 
-#else /* !CONFIG_KGDB_KDB */
-static inline void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
+#else /* !CONFIG_KGDB */
+static inline void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
 {
-        pr_err("UV: NMI error: KGDB/KDB is not enabled in this kernel\n");
+        pr_err("UV: NMI error: KGDB is not enabled in this kernel\n");
 }
-#endif /* !CONFIG_KGDB_KDB */
+#endif /* !CONFIG_KGDB */
 
 /*
  * UV NMI handler
@@ -606,9 +634,9 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
         if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump"))
                 uv_nmi_dump_state(cpu, regs, master);
 
-        /* Call KDB if enabled */
-        else if (uv_nmi_action_is("kdb"))
-                uv_call_kdb(cpu, regs, master);
+        /* Call KGDB/KDB if enabled */
+        else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb"))
+                uv_call_kgdb_kdb(cpu, regs, master);
 
         /* Clear per_cpu "in nmi" flag */
         atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_OUT);
@@ -634,7 +662,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
 /*
  * NMI handler for pulling in CPUs when perf events are grabbing our NMI
  */
-int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
+static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
 {
         int ret;
 
@@ -651,7 +679,7 @@ int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
         return ret;
 }
 
-void uv_register_nmi_notifier(void)
+static void uv_register_nmi_notifier(void)
 {
         if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
                 pr_warn("UV: NMI handler failed to register\n");
@@ -695,6 +723,5 @@ void uv_nmi_setup(void)
                 uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
         }
         BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
+        uv_register_nmi_notifier();
 }
-
-
diff --git a/arch/x86/realmode/rm/Makefile b/arch/x86/realmode/rm/Makefile
index 9cac82588cbc..3497f14e4dea 100644
--- a/arch/x86/realmode/rm/Makefile
+++ b/arch/x86/realmode/rm/Makefile
@@ -64,20 +64,7 @@ $(obj)/realmode.relocs: $(obj)/realmode.elf FORCE
 
 # ---------------------------------------------------------------------------
 
-# How to compile the 16-bit code.  Note we always compile for -march=i386,
-# that way we can complain to the user if the CPU is insufficient.
-KBUILD_CFLAGS   := $(LINUXINCLUDE) -m32 -g -Os -D_SETUP -D__KERNEL__ -D_WAKEUP \
-                   -I$(srctree)/arch/x86/boot \
-                   -DDISABLE_BRANCH_PROFILING \
-                   -Wall -Wstrict-prototypes \
-                   -march=i386 -mregparm=3 \
-                   -include $(srctree)/$(src)/../../boot/code16gcc.h \
-                   -fno-strict-aliasing -fomit-frame-pointer -fno-pic \
-                   -mno-mmx -mno-sse \
-                   $(call cc-option, -ffreestanding) \
-                   $(call cc-option, -fno-toplevel-reorder,\
-                   $(call cc-option, -fno-unit-at-a-time)) \
-                   $(call cc-option, -fno-stack-protector) \
-                   $(call cc-option, -mpreferred-stack-boundary=2)
+KBUILD_CFLAGS   := $(LINUXINCLUDE) $(REALMODE_CFLAGS) -D_SETUP -D_WAKEUP \
+                   -I$(srctree)/arch/x86/boot
 KBUILD_AFLAGS   := $(KBUILD_CFLAGS) -D__ASSEMBLY__
 GCOV_PROFILE := n
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 11f9285a2ff6..cfbdbdb4e173 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -1025,6 +1025,29 @@ static void emit_relocs(int as_text, int use_real_mode)
         }
 }
 
+/*
+ * As an aid to debugging problems with different linkers
+ * print summary information about the relocs.
+ * Since different linkers tend to emit the sections in
+ * different orders we use the section names in the output.
+ */
+static int do_reloc_info(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
+                                const char *symname)
+{
+        printf("%s\t%s\t%s\t%s\n",
+                sec_name(sec->shdr.sh_info),
+                rel_type(ELF_R_TYPE(rel->r_info)),
+                symname,
+                sec_name(sym->st_shndx));
+        return 0;
+}
+
+static void print_reloc_info(void)
+{
+        printf("reloc section\treloc type\tsymbol\tsymbol section\n");
+        walk_relocs(do_reloc_info);
+}
+
 #if ELF_BITS == 64
 # define process process_64
 #else
@@ -1032,7 +1055,8 @@ static void emit_relocs(int as_text, int use_real_mode)
 #endif
 
 void process(FILE *fp, int use_real_mode, int as_text,
-             int show_absolute_syms, int show_absolute_relocs)
+             int show_absolute_syms, int show_absolute_relocs,
+             int show_reloc_info)
 {
         regex_init(use_real_mode);
         read_ehdr(fp);
@@ -1050,5 +1074,9 @@ void process(FILE *fp, int use_real_mode, int as_text,
                 print_absolute_relocs();
                 return;
         }
+        if (show_reloc_info) {
+                print_reloc_info();
+                return;
+        }
         emit_relocs(as_text, use_real_mode);
 }
diff --git a/arch/x86/tools/relocs.h b/arch/x86/tools/relocs.h
index 07cdb1eca4fa..f59590645b68 100644
--- a/arch/x86/tools/relocs.h
+++ b/arch/x86/tools/relocs.h
@@ -29,8 +29,9 @@ enum symtype {
 };
 
 void process_32(FILE *fp, int use_real_mode, int as_text,
-                int show_absolute_syms, int show_absolute_relocs);
+                int show_absolute_syms, int show_absolute_relocs,
+                int show_reloc_info);
 void process_64(FILE *fp, int use_real_mode, int as_text,
-                int show_absolute_syms, int show_absolute_relocs);
-
+                int show_absolute_syms, int show_absolute_relocs,
+                int show_reloc_info);
 #endif /* RELOCS_H */
diff --git a/arch/x86/tools/relocs_common.c b/arch/x86/tools/relocs_common.c
index 44d396823a53..acab636bcb34 100644
--- a/arch/x86/tools/relocs_common.c
+++ b/arch/x86/tools/relocs_common.c
@@ -11,12 +11,13 @@ void die(char *fmt, ...)
 
 static void usage(void)
 {
-        die("relocs [--abs-syms|--abs-relocs|--text|--realmode] vmlinux\n");
+        die("relocs [--abs-syms|--abs-relocs|--reloc-info|--text|--realmode]" \
+            " vmlinux\n");
 }
 
 int main(int argc, char **argv)
 {
-        int show_absolute_syms, show_absolute_relocs;
+        int show_absolute_syms, show_absolute_relocs, show_reloc_info;
         int as_text, use_real_mode;
         const char *fname;
         FILE *fp;
@@ -25,6 +26,7 @@ int main(int argc, char **argv)
 
         show_absolute_syms = 0;
         show_absolute_relocs = 0;
+        show_reloc_info = 0;
         as_text = 0;
         use_real_mode = 0;
         fname = NULL;
@@ -39,6 +41,10 @@ int main(int argc, char **argv)
                                 show_absolute_relocs = 1;
                                 continue;
                         }
+                        if (strcmp(arg, "--reloc-info") == 0) {
+                                show_reloc_info = 1;
+                                continue;
+                        }
                         if (strcmp(arg, "--text") == 0) {
                                 as_text = 1;
                                 continue;
@@ -67,10 +73,12 @@ int main(int argc, char **argv)
         rewind(fp);
         if (e_ident[EI_CLASS] == ELFCLASS64)
                 process_64(fp, use_real_mode, as_text,
-                           show_absolute_syms, show_absolute_relocs);
+                           show_absolute_syms, show_absolute_relocs,
+                           show_reloc_info);
         else
                 process_32(fp, use_real_mode, as_text,
-                           show_absolute_syms, show_absolute_relocs);
+                           show_absolute_syms, show_absolute_relocs,
+                           show_reloc_info);
         fclose(fp);
         return 0;
 }
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 1a3c76505649..01b90261fa38 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -51,3 +51,7 @@ config XEN_DEBUG_FS
           Enable statistics output and various tuning options in debugfs.
           Enabling this option may incur a significant performance overhead.
 
+config XEN_PVH
+        bool "Support for running as a PVH guest"
+        depends on X86_64 && XEN && XEN_PVHVM
+        def_bool n
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index fa6ade76ef3f..a4d7b647867f 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -262,8 +262,9 @@ static void __init xen_banner(void)
         struct xen_extraversion extra;
         HYPERVISOR_xen_version(XENVER_extraversion, &extra);
 
-        printk(KERN_INFO "Booting paravirtualized kernel on %s\n",
-               pv_info.name);
+        pr_info("Booting paravirtualized kernel %son %s\n",
+                xen_feature(XENFEAT_auto_translated_physmap) ?
+                        "with PVH extensions " : "", pv_info.name);
         printk(KERN_INFO "Xen version: %d.%d%s%s\n",
                version >> 16, version & 0xffff, extra.extraversion,
                xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
@@ -433,7 +434,7 @@ static void __init xen_init_cpuid_mask(void)
 
         ax = 1;
         cx = 0;
-        xen_cpuid(&ax, &bx, &cx, &dx);
+        cpuid(1, &ax, &bx, &cx, &dx);
 
         xsave_mask =
                 (1 << (X86_FEATURE_XSAVE % 32)) |
@@ -1142,8 +1143,9 @@ void xen_setup_vcpu_info_placement(void)
                 xen_vcpu_setup(cpu);
 
         /* xen_vcpu_setup managed to place the vcpu_info within the
-           percpu area for all cpus, so make use of it */
-        if (have_vcpu_info_placement) {
+         * percpu area for all cpus, so make use of it. Note that for
+         * PVH we want to use native IRQ mechanism. */
+        if (have_vcpu_info_placement && !xen_pvh_domain()) {
                 pv_irq_ops.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
                 pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(xen_restore_fl_direct);
                 pv_irq_ops.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
@@ -1407,9 +1409,49 @@ static void __init xen_boot_params_init_edd(void)
  * Set up the GDT and segment registers for -fstack-protector.  Until
  * we do this, we have to be careful not to call any stack-protected
  * function, which is most of the kernel.
+ *
+ * Note, that it is __ref because the only caller of this after init
+ * is PVH which is not going to use xen_load_gdt_boot or other
+ * __init functions.
  */
-static void __init xen_setup_stackprotector(void)
+static void __ref xen_setup_gdt(int cpu)
 {
+        if (xen_feature(XENFEAT_auto_translated_physmap)) {
+#ifdef CONFIG_X86_64
+                unsigned long dummy;
+
+                load_percpu_segment(cpu); /* We need to access per-cpu area */
+                switch_to_new_gdt(cpu); /* GDT and GS set */
+
+                /* We are switching of the Xen provided GDT to our HVM mode
+                 * GDT. The new GDT has  __KERNEL_CS with CS.L = 1
+                 * and we are jumping to reload it.
+                 */
+                asm volatile ("pushq %0\n"
+                              "leaq 1f(%%rip),%0\n"
+                              "pushq %0\n"
+                              "lretq\n"
+                              "1:\n"
+                              : "=&r" (dummy) : "0" (__KERNEL_CS));
+
+                /*
+                 * While not needed, we also set the %es, %ds, and %fs
+                 * to zero. We don't care about %ss as it is NULL.
+                 * Strictly speaking this is not needed as Xen zeros those
+                 * out (and also MSR_FS_BASE, MSR_GS_BASE, MSR_KERNEL_GS_BASE)
+                 *
+                 * Linux zeros them in cpu_init() and in secondary_startup_64
+                 * (for BSP).
+                 */
+                loadsegment(es, 0);
+                loadsegment(ds, 0);
+                loadsegment(fs, 0);
+#else
+                /* PVH: TODO Implement. */
+                BUG();
+#endif
+                return; /* PVH does not need any PV GDT ops. */
+        }
         pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot;
         pv_cpu_ops.load_gdt = xen_load_gdt_boot;
 
@@ -1420,6 +1462,46 @@ static void __init xen_setup_stackprotector(void)
         pv_cpu_ops.load_gdt = xen_load_gdt;
 }
 
+/*
+ * A PV guest starts with default flags that are not set for PVH, set them
+ * here asap.
+ */
+static void xen_pvh_set_cr_flags(int cpu)
+{
+
+        /* Some of these are setup in 'secondary_startup_64'. The others:
+         * X86_CR0_TS, X86_CR0_PE, X86_CR0_ET are set by Xen for HVM guests
+         * (which PVH shared codepaths), while X86_CR0_PG is for PVH. */
+        write_cr0(read_cr0() | X86_CR0_MP | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM);
+}
+
+/*
+ * Note, that it is ref - because the only caller of this after init
+ * is PVH which is not going to use xen_load_gdt_boot or other
+ * __init functions.
+ */
+void __ref xen_pvh_secondary_vcpu_init(int cpu)
+{
+        xen_setup_gdt(cpu);
+        xen_pvh_set_cr_flags(cpu);
+}
+
+static void __init xen_pvh_early_guest_init(void)
+{
+        if (!xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
+        if (!xen_feature(XENFEAT_hvm_callback_vector))
+                return;
+
+        xen_have_vector_callback = 1;
+        xen_pvh_set_cr_flags(0);
+
+#ifdef CONFIG_X86_32
+        BUG(); /* PVH: Implement proper support. */
+#endif
+}
+
 /* First C function to be called on Xen boot */
 asmlinkage void __init xen_start_kernel(void)
 {
@@ -1431,13 +1513,16 @@ asmlinkage void __init xen_start_kernel(void)
 
         xen_domain_type = XEN_PV_DOMAIN;
 
+        xen_setup_features();
+        xen_pvh_early_guest_init();
         xen_setup_machphys_mapping();
 
         /* Install Xen paravirt ops */
         pv_info = xen_info;
         pv_init_ops = xen_init_ops;
-        pv_cpu_ops = xen_cpu_ops;
         pv_apic_ops = xen_apic_ops;
+        if (!xen_pvh_domain())
+                pv_cpu_ops = xen_cpu_ops;
 
         x86_init.resources.memory_setup = xen_memory_setup;
         x86_init.oem.arch_setup = xen_arch_setup;
@@ -1469,17 +1554,14 @@ asmlinkage void __init xen_start_kernel(void)
         /* Work out if we support NX */
         x86_configure_nx();
 
-        xen_setup_features();
-
         /* Get mfn list */
-        if (!xen_feature(XENFEAT_auto_translated_physmap))
-                xen_build_dynamic_phys_to_machine();
+        xen_build_dynamic_phys_to_machine();
 
         /*
          * Set up kernel GDT and segment registers, mainly so that
          * -fstack-protector code can be executed.
          */
-        xen_setup_stackprotector();
+        xen_setup_gdt(0);
 
         xen_init_irq_ops();
         xen_init_cpuid_mask();
@@ -1548,14 +1630,18 @@ asmlinkage void __init xen_start_kernel(void)
         /* set the limit of our address space */
         xen_reserve_top();
 
-        /* We used to do this in xen_arch_setup, but that is too late on AMD
-         * were early_cpu_init (run before ->arch_setup()) calls early_amd_init
-         * which pokes 0xcf8 port.
-         */
-        set_iopl.iopl = 1;
-        rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
-        if (rc != 0)
-                xen_raw_printk("physdev_op failed %d\n", rc);
+        /* PVH: runs at default kernel iopl of 0 */
+        if (!xen_pvh_domain()) {
+                /*
+                 * We used to do this in xen_arch_setup, but that is too late
+                 * on AMD were early_cpu_init (run before ->arch_setup()) calls
+                 * early_amd_init which pokes 0xcf8 port.
+                 */
+                set_iopl.iopl = 1;
+                rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
+                if (rc != 0)
+                        xen_raw_printk("physdev_op failed %d\n", rc);
+        }
 
 #ifdef CONFIG_X86_32
         /* set up basic CPUID stuff */
diff --git a/arch/x86/xen/grant-table.c b/arch/x86/xen/grant-table.c
index 3a5f55d51907..c98583588580 100644
--- a/arch/x86/xen/grant-table.c
+++ b/arch/x86/xen/grant-table.c
@@ -125,3 +125,67 @@ void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
         apply_to_page_range(&init_mm, (unsigned long)shared,
                             PAGE_SIZE * nr_gframes, unmap_pte_fn, NULL);
 }
+#ifdef CONFIG_XEN_PVH
+#include <xen/balloon.h>
+#include <xen/events.h>
+#include <xen/xen.h>
+#include <linux/slab.h>
+static int __init xlated_setup_gnttab_pages(void)
+{
+        struct page **pages;
+        xen_pfn_t *pfns;
+        int rc;
+        unsigned int i;
+        unsigned long nr_grant_frames = gnttab_max_grant_frames();
+
+        BUG_ON(nr_grant_frames == 0);
+        pages = kcalloc(nr_grant_frames, sizeof(pages[0]), GFP_KERNEL);
+        if (!pages)
+                return -ENOMEM;
+
+        pfns = kcalloc(nr_grant_frames, sizeof(pfns[0]), GFP_KERNEL);
+        if (!pfns) {
+                kfree(pages);
+                return -ENOMEM;
+        }
+        rc = alloc_xenballooned_pages(nr_grant_frames, pages, 0 /* lowmem */);
+        if (rc) {
+                pr_warn("%s Couldn't balloon alloc %ld pfns rc:%d\n", __func__,
+                        nr_grant_frames, rc);
+                kfree(pages);
+                kfree(pfns);
+                return rc;
+        }
+        for (i = 0; i < nr_grant_frames; i++)
+                pfns[i] = page_to_pfn(pages[i]);
+
+        rc = arch_gnttab_map_shared(pfns, nr_grant_frames, nr_grant_frames,
+                                    &xen_auto_xlat_grant_frames.vaddr);
+
+        if (rc) {
+                pr_warn("%s Couldn't map %ld pfns rc:%d\n", __func__,
+                        nr_grant_frames, rc);
+                free_xenballooned_pages(nr_grant_frames, pages);
+                kfree(pages);
+                kfree(pfns);
+                return rc;
+        }
+        kfree(pages);
+
+        xen_auto_xlat_grant_frames.pfn = pfns;
+        xen_auto_xlat_grant_frames.count = nr_grant_frames;
+
+        return 0;
+}
+
+static int __init xen_pvh_gnttab_setup(void)
+{
+        if (!xen_pvh_domain())
+                return -ENODEV;
+
+        return xlated_setup_gnttab_pages();
+}
+/* Call it _before_ __gnttab_init as we need to initialize the
+ * xen_auto_xlat_grant_frames first. */
+core_initcall(xen_pvh_gnttab_setup);
+#endif
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 0da7f863056f..08f763de26fe 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -5,6 +5,7 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/sched.h>
 #include <xen/interface/vcpu.h>
+#include <xen/features.h>
 #include <xen/events.h>
 
 #include <asm/xen/hypercall.h>
@@ -22,7 +23,7 @@ void xen_force_evtchn_callback(void)
         (void)HYPERVISOR_xen_version(0, NULL);
 }
 
-static unsigned long xen_save_fl(void)
+asmlinkage unsigned long xen_save_fl(void)
 {
         struct vcpu_info *vcpu;
         unsigned long flags;
@@ -40,7 +41,7 @@ static unsigned long xen_save_fl(void)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_save_fl);
 
-static void xen_restore_fl(unsigned long flags)
+__visible void xen_restore_fl(unsigned long flags)
 {
         struct vcpu_info *vcpu;
 
@@ -62,7 +63,7 @@ static void xen_restore_fl(unsigned long flags)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_restore_fl);
 
-static void xen_irq_disable(void)
+asmlinkage void xen_irq_disable(void)
 {
         /* There's a one instruction preempt window here.  We need to
            make sure we're don't switch CPUs between getting the vcpu
@@ -73,7 +74,7 @@ static void xen_irq_disable(void)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_irq_disable);
 
-static void xen_irq_enable(void)
+asmlinkage void xen_irq_enable(void)
 {
         struct vcpu_info *vcpu;
 
@@ -128,6 +129,8 @@ static const struct pv_irq_ops xen_irq_ops __initconst = {
 
 void __init xen_init_irq_ops(void)
 {
-        pv_irq_ops = xen_irq_ops;
+        /* For PVH we use default pv_irq_ops settings. */
+        if (!xen_feature(XENFEAT_hvm_callback_vector))
+                pv_irq_ops = xen_irq_ops;
         x86_init.irqs.intr_init = xen_init_IRQ;
 }
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index ce563be09cc1..2423ef04ffea 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -431,7 +431,7 @@ static pteval_t iomap_pte(pteval_t val)
         return val;
 }
 
-static pteval_t xen_pte_val(pte_t pte)
+__visible pteval_t xen_pte_val(pte_t pte)
 {
         pteval_t pteval = pte.pte;
 #if 0
@@ -448,7 +448,7 @@ static pteval_t xen_pte_val(pte_t pte)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pte_val);
 
-static pgdval_t xen_pgd_val(pgd_t pgd)
+__visible pgdval_t xen_pgd_val(pgd_t pgd)
 {
         return pte_mfn_to_pfn(pgd.pgd);
 }
@@ -479,7 +479,7 @@ void xen_set_pat(u64 pat)
         WARN_ON(pat != 0x0007010600070106ull);
 }
 
-static pte_t xen_make_pte(pteval_t pte)
+__visible pte_t xen_make_pte(pteval_t pte)
 {
         phys_addr_t addr = (pte & PTE_PFN_MASK);
 #if 0
@@ -514,14 +514,14 @@ static pte_t xen_make_pte(pteval_t pte)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pte);
 
-static pgd_t xen_make_pgd(pgdval_t pgd)
+__visible pgd_t xen_make_pgd(pgdval_t pgd)
 {
         pgd = pte_pfn_to_mfn(pgd);
         return native_make_pgd(pgd);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pgd);
 
-static pmdval_t xen_pmd_val(pmd_t pmd)
+__visible pmdval_t xen_pmd_val(pmd_t pmd)
 {
         return pte_mfn_to_pfn(pmd.pmd);
 }
@@ -580,7 +580,7 @@ static void xen_pmd_clear(pmd_t *pmdp)
 }
 #endif  /* CONFIG_X86_PAE */
 
-static pmd_t xen_make_pmd(pmdval_t pmd)
+__visible pmd_t xen_make_pmd(pmdval_t pmd)
 {
         pmd = pte_pfn_to_mfn(pmd);
         return native_make_pmd(pmd);
@@ -588,13 +588,13 @@ static pmd_t xen_make_pmd(pmdval_t pmd)
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pmd);
 
 #if PAGETABLE_LEVELS == 4
-static pudval_t xen_pud_val(pud_t pud)
+__visible pudval_t xen_pud_val(pud_t pud)
 {
         return pte_mfn_to_pfn(pud.pud);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pud_val);
 
-static pud_t xen_make_pud(pudval_t pud)
+__visible pud_t xen_make_pud(pudval_t pud)
 {
         pud = pte_pfn_to_mfn(pud);
 
@@ -1198,44 +1198,40 @@ static void __init xen_cleanhighmap(unsigned long vaddr,
          * instead of somewhere later and be confusing. */
         xen_mc_flush();
 }
-#endif
-static void __init xen_pagetable_init(void)
+static void __init xen_pagetable_p2m_copy(void)
 {
-#ifdef CONFIG_X86_64
         unsigned long size;
         unsigned long addr;
-#endif
-        paging_init();
-        xen_setup_shared_info();
-#ifdef CONFIG_X86_64
-        if (!xen_feature(XENFEAT_auto_translated_physmap)) {
-                unsigned long new_mfn_list;
-
-                size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
-
-                /* On 32-bit, we get zero so this never gets executed. */
-                new_mfn_list = xen_revector_p2m_tree();
-                if (new_mfn_list && new_mfn_list != xen_start_info->mfn_list) {
-                        /* using __ka address and sticking INVALID_P2M_ENTRY! */
-                        memset((void *)xen_start_info->mfn_list, 0xff, size);
-
-                        /* We should be in __ka space. */
-                        BUG_ON(xen_start_info->mfn_list < __START_KERNEL_map);
-                        addr = xen_start_info->mfn_list;
-                        /* We roundup to the PMD, which means that if anybody at this stage is
-                         * using the __ka address of xen_start_info or xen_start_info->shared_info
-                         * they are in going to crash. Fortunatly we have already revectored
-                         * in xen_setup_kernel_pagetable and in xen_setup_shared_info. */
-                        size = roundup(size, PMD_SIZE);
-                        xen_cleanhighmap(addr, addr + size);
-
-                        size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
-                        memblock_free(__pa(xen_start_info->mfn_list), size);
-                        /* And revector! Bye bye old array */
-                        xen_start_info->mfn_list = new_mfn_list;
-                } else
-                        goto skip;
-        }
+        unsigned long new_mfn_list;
+
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
+        size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
+
+        new_mfn_list = xen_revector_p2m_tree();
+        /* No memory or already called. */
+        if (!new_mfn_list || new_mfn_list == xen_start_info->mfn_list)
+                return;
+
+        /* using __ka address and sticking INVALID_P2M_ENTRY! */
+        memset((void *)xen_start_info->mfn_list, 0xff, size);
+
+        /* We should be in __ka space. */
+        BUG_ON(xen_start_info->mfn_list < __START_KERNEL_map);
+        addr = xen_start_info->mfn_list;
+        /* We roundup to the PMD, which means that if anybody at this stage is
+         * using the __ka address of xen_start_info or xen_start_info->shared_info
+         * they are in going to crash. Fortunatly we have already revectored
+         * in xen_setup_kernel_pagetable and in xen_setup_shared_info. */
+        size = roundup(size, PMD_SIZE);
+        xen_cleanhighmap(addr, addr + size);
+
+        size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
+        memblock_free(__pa(xen_start_info->mfn_list), size);
+        /* And revector! Bye bye old array */
+        xen_start_info->mfn_list = new_mfn_list;
+
         /* At this stage, cleanup_highmap has already cleaned __ka space
          * from _brk_limit way up to the max_pfn_mapped (which is the end of
          * the ramdisk). We continue on, erasing PMD entries that point to page
@@ -1255,7 +1251,15 @@ static void __init xen_pagetable_init(void)
          * anything at this stage. */
         xen_cleanhighmap(MODULES_VADDR, roundup(MODULES_VADDR, PUD_SIZE) - 1);
 #endif
-skip:
+}
+#endif
+
+static void __init xen_pagetable_init(void)
+{
+        paging_init();
+        xen_setup_shared_info();
+#ifdef CONFIG_X86_64
+        xen_pagetable_p2m_copy();
 #endif
         xen_post_allocator_init();
 }
@@ -1753,6 +1757,10 @@ static void set_page_prot_flags(void *addr, pgprot_t prot, unsigned long flags)
         unsigned long pfn = __pa(addr) >> PAGE_SHIFT;
         pte_t pte = pfn_pte(pfn, prot);
 
+        /* For PVH no need to set R/O or R/W to pin them or unpin them. */
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
         if (HYPERVISOR_update_va_mapping((unsigned long)addr, pte, flags))
                 BUG();
 }
@@ -1863,6 +1871,7 @@ static void __init check_pt_base(unsigned long *pt_base, unsigned long *pt_end,
  * but that's enough to get __va working.  We need to fill in the rest
  * of the physical mapping once some sort of allocator has been set
  * up.
+ * NOTE: for PVH, the page tables are native.
  */
 void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
 {
@@ -1884,17 +1893,18 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
         /* Zap identity mapping */
         init_level4_pgt[0] = __pgd(0);
 
-        /* Pre-constructed entries are in pfn, so convert to mfn */
-        /* L4[272] -> level3_ident_pgt
-         * L4[511] -> level3_kernel_pgt */
-        convert_pfn_mfn(init_level4_pgt);
-
-        /* L3_i[0] -> level2_ident_pgt */
-        convert_pfn_mfn(level3_ident_pgt);
-        /* L3_k[510] -> level2_kernel_pgt
-         * L3_i[511] -> level2_fixmap_pgt */
-        convert_pfn_mfn(level3_kernel_pgt);
-
+        if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+                /* Pre-constructed entries are in pfn, so convert to mfn */
+                /* L4[272] -> level3_ident_pgt
+                 * L4[511] -> level3_kernel_pgt */
+                convert_pfn_mfn(init_level4_pgt);
+
+                /* L3_i[0] -> level2_ident_pgt */
+                convert_pfn_mfn(level3_ident_pgt);
+                /* L3_k[510] -> level2_kernel_pgt
+                 * L3_i[511] -> level2_fixmap_pgt */
+                convert_pfn_mfn(level3_kernel_pgt);
+        }
         /* We get [511][511] and have Xen's version of level2_kernel_pgt */
         l3 = m2v(pgd[pgd_index(__START_KERNEL_map)].pgd);
         l2 = m2v(l3[pud_index(__START_KERNEL_map)].pud);
@@ -1918,31 +1928,33 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
         copy_page(level2_fixmap_pgt, l2);
         /* Note that we don't do anything with level1_fixmap_pgt which
          * we don't need. */
+        if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+                /* Make pagetable pieces RO */
+                set_page_prot(init_level4_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level3_ident_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level3_kernel_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level3_user_vsyscall, PAGE_KERNEL_RO);
+                set_page_prot(level2_ident_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level2_kernel_pgt, PAGE_KERNEL_RO);
+                set_page_prot(level2_fixmap_pgt, PAGE_KERNEL_RO);
+
+                /* Pin down new L4 */
+                pin_pagetable_pfn(MMUEXT_PIN_L4_TABLE,
+                                  PFN_DOWN(__pa_symbol(init_level4_pgt)));
+
+                /* Unpin Xen-provided one */
+                pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
 
-        /* Make pagetable pieces RO */
-        set_page_prot(init_level4_pgt, PAGE_KERNEL_RO);
-        set_page_prot(level3_ident_pgt, PAGE_KERNEL_RO);
-        set_page_prot(level3_kernel_pgt, PAGE_KERNEL_RO);
-        set_page_prot(level3_user_vsyscall, PAGE_KERNEL_RO);
-        set_page_prot(level2_ident_pgt, PAGE_KERNEL_RO);
-        set_page_prot(level2_kernel_pgt, PAGE_KERNEL_RO);
-        set_page_prot(level2_fixmap_pgt, PAGE_KERNEL_RO);
-
-        /* Pin down new L4 */
-        pin_pagetable_pfn(MMUEXT_PIN_L4_TABLE,
-                          PFN_DOWN(__pa_symbol(init_level4_pgt)));
-
-        /* Unpin Xen-provided one */
-        pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
-
-        /*
-         * At this stage there can be no user pgd, and no page
-         * structure to attach it to, so make sure we just set kernel
-         * pgd.
-         */
-        xen_mc_batch();
-        __xen_write_cr3(true, __pa(init_level4_pgt));
-        xen_mc_issue(PARAVIRT_LAZY_CPU);
+                /*
+                 * At this stage there can be no user pgd, and no page
+                 * structure to attach it to, so make sure we just set kernel
+                 * pgd.
+                 */
+                xen_mc_batch();
+                __xen_write_cr3(true, __pa(init_level4_pgt));
+                xen_mc_issue(PARAVIRT_LAZY_CPU);
+        } else
+                native_write_cr3(__pa(init_level4_pgt));
 
         /* We can't that easily rip out L3 and L2, as the Xen pagetables are
          * set out this way: [L4], [L1], [L2], [L3], [L1], [L1] ...  for
@@ -2103,6 +2115,9 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 
 static void __init xen_post_allocator_init(void)
 {
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
         pv_mmu_ops.set_pte = xen_set_pte;
         pv_mmu_ops.set_pmd = xen_set_pmd;
         pv_mmu_ops.set_pud = xen_set_pud;
@@ -2207,6 +2222,15 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
 void __init xen_init_mmu_ops(void)
 {
         x86_init.paging.pagetable_init = xen_pagetable_init;
+
+        /* Optimization - we can use the HVM one but it has no idea which
+         * VCPUs are descheduled - which means that it will needlessly IPI
+         * them. Xen knows so let it do the job.
+         */
+        if (xen_feature(XENFEAT_auto_translated_physmap)) {
+                pv_mmu_ops.flush_tlb_others = xen_flush_tlb_others;
+                return;
+        }
         pv_mmu_ops = xen_mmu_ops;
 
         memset(dummy_mapping, 0xff, PAGE_SIZE);
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 2ae8699e8767..8009acbe41e4 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -280,6 +280,9 @@ void __ref xen_build_mfn_list_list(void)
 {
         unsigned long pfn;
 
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
         /* Pre-initialize p2m_top_mfn to be completely missing */
         if (p2m_top_mfn == NULL) {
                 p2m_mid_missing_mfn = extend_brk(PAGE_SIZE, PAGE_SIZE);
@@ -336,6 +339,9 @@ void __ref xen_build_mfn_list_list(void)
 
 void xen_setup_mfn_list_list(void)
 {
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
         BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
 
         HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list_list =
@@ -346,10 +352,15 @@ void xen_setup_mfn_list_list(void)
 /* Set up p2m_top to point to the domain-builder provided p2m pages */
 void __init xen_build_dynamic_phys_to_machine(void)
 {
-        unsigned long *mfn_list = (unsigned long *)xen_start_info->mfn_list;
-        unsigned long max_pfn = min(MAX_DOMAIN_PAGES, xen_start_info->nr_pages);
+        unsigned long *mfn_list;
+        unsigned long max_pfn;
         unsigned long pfn;
 
+         if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
+        mfn_list = (unsigned long *)xen_start_info->mfn_list;
+        max_pfn = min(MAX_DOMAIN_PAGES, xen_start_info->nr_pages);
         xen_max_p2m_pfn = max_pfn;
 
         p2m_missing = extend_brk(PAGE_SIZE, PAGE_SIZE);
@@ -888,13 +899,6 @@ int m2p_add_override(unsigned long mfn, struct page *page,
                                         "m2p_add_override: pfn %lx not mapped", pfn))
                         return -EINVAL;
         }
-        WARN_ON(PagePrivate(page));
-        SetPagePrivate(page);
-        set_page_private(page, mfn);
-        page->index = pfn_to_mfn(pfn);
-
-        if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn))))
-                return -ENOMEM;
 
         if (kmap_op != NULL) {
                 if (!PageHighMem(page)) {
@@ -933,19 +937,16 @@ int m2p_add_override(unsigned long mfn, struct page *page,
 }
 EXPORT_SYMBOL_GPL(m2p_add_override);
 int m2p_remove_override(struct page *page,
-                struct gnttab_map_grant_ref *kmap_op)
+                        struct gnttab_map_grant_ref *kmap_op,
+                        unsigned long mfn)
 {
         unsigned long flags;
-        unsigned long mfn;
         unsigned long pfn;
         unsigned long uninitialized_var(address);
         unsigned level;
         pte_t *ptep = NULL;
 
         pfn = page_to_pfn(page);
-        mfn = get_phys_to_machine(pfn);
-        if (mfn == INVALID_P2M_ENTRY || !(mfn & FOREIGN_FRAME_BIT))
-                return -EINVAL;
 
         if (!PageHighMem(page)) {
                 address = (unsigned long)__va(pfn << PAGE_SHIFT);
@@ -959,10 +960,7 @@ int m2p_remove_override(struct page *page,
         spin_lock_irqsave(&m2p_override_lock, flags);
         list_del(&page->lru);
         spin_unlock_irqrestore(&m2p_override_lock, flags);
-        WARN_ON(!PagePrivate(page));
-        ClearPagePrivate(page);
 
-        set_phys_to_machine(pfn, page->index);
         if (kmap_op != NULL) {
                 if (!PageHighMem(page)) {
                         struct multicall_space mcs;
diff --git a/arch/x86/xen/platform-pci-unplug.c b/arch/x86/xen/platform-pci-unplug.c
index 0a7852483ffe..a8261716d58d 100644
--- a/arch/x86/xen/platform-pci-unplug.c
+++ b/arch/x86/xen/platform-pci-unplug.c
@@ -30,10 +30,9 @@
 #define XEN_PLATFORM_ERR_PROTOCOL -2
 #define XEN_PLATFORM_ERR_BLACKLIST -3
 
-/* store the value of xen_emul_unplug after the unplug is done */
-int xen_platform_pci_unplug;
-EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 #ifdef CONFIG_XEN_PVHVM
+/* store the value of xen_emul_unplug after the unplug is done */
+static int xen_platform_pci_unplug;
 static int xen_emul_unplug;
 
 static int check_platform_magic(void)
@@ -69,6 +68,80 @@ static int check_platform_magic(void)
         return 0;
 }
 
+bool xen_has_pv_devices()
+{
+        if (!xen_domain())
+                return false;
+
+        /* PV domains always have them. */
+        if (xen_pv_domain())
+                return true;
+
+        /* And user has xen_platform_pci=0 set in guest config as
+         * driver did not modify the value. */
+        if (xen_platform_pci_unplug == 0)
+                return false;
+
+        if (xen_platform_pci_unplug & XEN_UNPLUG_NEVER)
+                return false;
+
+        if (xen_platform_pci_unplug & XEN_UNPLUG_ALL)
+                return true;
+
+        /* This is an odd one - we are going to run legacy
+         * and PV drivers at the same time. */
+        if (xen_platform_pci_unplug & XEN_UNPLUG_UNNECESSARY)
+                return true;
+
+        /* And the caller has to follow with xen_pv_{disk,nic}_devices
+         * to be certain which driver can load. */
+        return false;
+}
+EXPORT_SYMBOL_GPL(xen_has_pv_devices);
+
+static bool __xen_has_pv_device(int state)
+{
+        /* HVM domains might or might not */
+        if (xen_hvm_domain() && (xen_platform_pci_unplug & state))
+                return true;
+
+        return xen_has_pv_devices();
+}
+
+bool xen_has_pv_nic_devices(void)
+{
+        return __xen_has_pv_device(XEN_UNPLUG_ALL_NICS | XEN_UNPLUG_ALL);
+}
+EXPORT_SYMBOL_GPL(xen_has_pv_nic_devices);
+
+bool xen_has_pv_disk_devices(void)
+{
+        return __xen_has_pv_device(XEN_UNPLUG_ALL_IDE_DISKS |
+                                   XEN_UNPLUG_AUX_IDE_DISKS | XEN_UNPLUG_ALL);
+}
+EXPORT_SYMBOL_GPL(xen_has_pv_disk_devices);
+
+/*
+ * This one is odd - it determines whether you want to run PV _and_
+ * legacy (IDE) drivers together. This combination is only possible
+ * under HVM.
+ */
+bool xen_has_pv_and_legacy_disk_devices(void)
+{
+        if (!xen_domain())
+                return false;
+
+        /* N.B. This is only ever used in HVM mode */
+        if (xen_pv_domain())
+                return false;
+
+        if (xen_platform_pci_unplug & XEN_UNPLUG_UNNECESSARY)
+                return true;
+
+        return false;
+}
+EXPORT_SYMBOL_GPL(xen_has_pv_and_legacy_disk_devices);
+
 void xen_unplug_emulated_devices(void)
 {
         int r;
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index 68c054f59de6..0982233b9b84 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -27,6 +27,7 @@
 #include <xen/interface/memory.h>
 #include <xen/interface/physdev.h>
 #include <xen/features.h>
+#include "mmu.h"
 #include "xen-ops.h"
 #include "vdso.h"
 
@@ -34,7 +35,7 @@
 extern const char xen_hypervisor_callback[];
 extern const char xen_failsafe_callback[];
 #ifdef CONFIG_X86_64
-extern const char nmi[];
+extern asmlinkage void nmi(void);
 #endif
 extern void xen_sysenter_target(void);
 extern void xen_syscall_target(void);
@@ -81,6 +82,9 @@ static void __init xen_add_extra_mem(u64 start, u64 size)
 
         memblock_reserve(start, size);
 
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return;
+
         xen_max_p2m_pfn = PFN_DOWN(start + size);
         for (pfn = PFN_DOWN(start); pfn < xen_max_p2m_pfn; pfn++) {
                 unsigned long mfn = pfn_to_mfn(pfn);
@@ -103,6 +107,7 @@ static unsigned long __init xen_do_chunk(unsigned long start,
                 .domid        = DOMID_SELF
         };
         unsigned long len = 0;
+        int xlated_phys = xen_feature(XENFEAT_auto_translated_physmap);
         unsigned long pfn;
         int ret;
 
@@ -116,7 +121,7 @@ static unsigned long __init xen_do_chunk(unsigned long start,
                                 continue;
                         frame = mfn;
                 } else {
-                        if (mfn != INVALID_P2M_ENTRY)
+                        if (!xlated_phys && mfn != INVALID_P2M_ENTRY)
                                 continue;
                         frame = pfn;
                 }
@@ -154,6 +159,13 @@ static unsigned long __init xen_do_chunk(unsigned long start,
 static unsigned long __init xen_release_chunk(unsigned long start,
                                               unsigned long end)
 {
+        /*
+         * Xen already ballooned out the E820 non RAM regions for us
+         * and set them up properly in EPT.
+         */
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return end - start;
+
         return xen_do_chunk(start, end, true);
 }
 
@@ -222,7 +234,13 @@ static void __init xen_set_identity_and_release_chunk(
          * (except for the ISA region which must be 1:1 mapped) to
          * release the refcounts (in Xen) on the original frames.
          */
-        for (pfn = start_pfn; pfn <= max_pfn_mapped && pfn < end_pfn; pfn++) {
+
+        /*
+         * PVH E820 matches the hypervisor's P2M which means we need to
+         * account for the proper values of *release and *identity.
+         */
+        for (pfn = start_pfn; !xen_feature(XENFEAT_auto_translated_physmap) &&
+             pfn <= max_pfn_mapped && pfn < end_pfn; pfn++) {
                 pte_t pte = __pte_ma(0);
 
                 if (pfn < PFN_UP(ISA_END_ADDRESS))
@@ -559,20 +577,17 @@ void xen_enable_syscall(void)
 void xen_enable_nmi(void)
 {
 #ifdef CONFIG_X86_64
-        if (register_callback(CALLBACKTYPE_nmi, nmi))
+        if (register_callback(CALLBACKTYPE_nmi, (char *)nmi))
                 BUG();
 #endif
 }
-void __init xen_arch_setup(void)
+void __init xen_pvmmu_arch_setup(void)
 {
-        xen_panic_handler_init();
-
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_4gb_segments);
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_writable_pagetables);
 
-        if (!xen_feature(XENFEAT_auto_translated_physmap))
-                HYPERVISOR_vm_assist(VMASST_CMD_enable,
-                                     VMASST_TYPE_pae_extended_cr3);
+        HYPERVISOR_vm_assist(VMASST_CMD_enable,
+                             VMASST_TYPE_pae_extended_cr3);
 
         if (register_callback(CALLBACKTYPE_event, xen_hypervisor_callback) ||
             register_callback(CALLBACKTYPE_failsafe, xen_failsafe_callback))
@@ -581,6 +596,15 @@ void __init xen_arch_setup(void)
         xen_enable_sysenter();
         xen_enable_syscall();
         xen_enable_nmi();
+}
+
+/* This function is not called for HVM domains */
+void __init xen_arch_setup(void)
+{
+        xen_panic_handler_init();
+        if (!xen_feature(XENFEAT_auto_translated_physmap))
+                xen_pvmmu_arch_setup();
+
 #ifdef CONFIG_ACPI
         if (!(xen_start_info->flags & SIF_INITDOMAIN)) {
                 printk(KERN_INFO "ACPI in unprivileged domain disabled\n");
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index c36b325abd83..a18eadd8bb40 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -73,9 +73,11 @@ static void cpu_bringup(void)
         touch_softlockup_watchdog();
         preempt_disable();
 
-        xen_enable_sysenter();
-        xen_enable_syscall();
-
+        /* PVH runs in ring 0 and allows us to do native syscalls. Yay! */
+        if (!xen_feature(XENFEAT_supervisor_mode_kernel)) {
+                xen_enable_sysenter();
+                xen_enable_syscall();
+        }
         cpu = smp_processor_id();
         smp_store_cpu_info(cpu);
         cpu_data(cpu).x86_max_cores = 1;
@@ -97,8 +99,14 @@ static void cpu_bringup(void)
         wmb();                  /* make sure everything is out */
 }
 
-static void cpu_bringup_and_idle(void)
+/* Note: cpu parameter is only relevant for PVH */
+static void cpu_bringup_and_idle(int cpu)
 {
+#ifdef CONFIG_X86_64
+        if (xen_feature(XENFEAT_auto_translated_physmap) &&
+            xen_feature(XENFEAT_supervisor_mode_kernel))
+                xen_pvh_secondary_vcpu_init(cpu);
+#endif
         cpu_bringup();
         cpu_startup_entry(CPUHP_ONLINE);
 }
@@ -274,9 +282,10 @@ static void __init xen_smp_prepare_boot_cpu(void)
         native_smp_prepare_boot_cpu();
 
         if (xen_pv_domain()) {
-                /* We've switched to the "real" per-cpu gdt, so make sure the
-                   old memory can be recycled */
-                make_lowmem_page_readwrite(xen_initial_gdt);
+                if (!xen_feature(XENFEAT_writable_page_tables))
+                        /* We've switched to the "real" per-cpu gdt, so make
+                         * sure the old memory can be recycled. */
+                        make_lowmem_page_readwrite(xen_initial_gdt);
 
 #ifdef CONFIG_X86_32
                 /*
@@ -360,22 +369,21 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
 
         gdt = get_cpu_gdt_table(cpu);
 
-        ctxt->flags = VGCF_IN_KERNEL;
-        ctxt->user_regs.ss = __KERNEL_DS;
 #ifdef CONFIG_X86_32
+        /* Note: PVH is not yet supported on x86_32. */
         ctxt->user_regs.fs = __KERNEL_PERCPU;
         ctxt->user_regs.gs = __KERNEL_STACK_CANARY;
-#else
-        ctxt->gs_base_kernel = per_cpu_offset(cpu);
 #endif
         ctxt->user_regs.eip = (unsigned long)cpu_bringup_and_idle;
 
         memset(&ctxt->fpu_ctxt, 0, sizeof(ctxt->fpu_ctxt));
 
-        {
+        if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+                ctxt->flags = VGCF_IN_KERNEL;
                 ctxt->user_regs.eflags = 0x1000; /* IOPL_RING1 */
                 ctxt->user_regs.ds = __USER_DS;
                 ctxt->user_regs.es = __USER_DS;
+                ctxt->user_regs.ss = __KERNEL_DS;
 
                 xen_copy_trap_info(ctxt->trap_ctxt);
 
@@ -396,18 +404,27 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
 #ifdef CONFIG_X86_32
                 ctxt->event_callback_cs     = __KERNEL_CS;
                 ctxt->failsafe_callback_cs  = __KERNEL_CS;
+#else
+                ctxt->gs_base_kernel = per_cpu_offset(cpu);
 #endif
                 ctxt->event_callback_eip    =
                                         (unsigned long)xen_hypervisor_callback;
                 ctxt->failsafe_callback_eip =
                                         (unsigned long)xen_failsafe_callback;
+                ctxt->user_regs.cs = __KERNEL_CS;
+                per_cpu(xen_cr3, cpu) = __pa(swapper_pg_dir);
+#ifdef CONFIG_X86_32
         }
-        ctxt->user_regs.cs = __KERNEL_CS;
+#else
+        } else
+                /* N.B. The user_regs.eip (cpu_bringup_and_idle) is called with
+                 * %rdi having the cpu number - which means are passing in
+                 * as the first parameter the cpu. Subtle!
+                 */
+                ctxt->user_regs.rdi = cpu;
+#endif
         ctxt->user_regs.esp = idle->thread.sp0 - sizeof(struct pt_regs);
-
-        per_cpu(xen_cr3, cpu) = __pa(swapper_pg_dir);
         ctxt->ctrlreg[3] = xen_pfn_to_cr3(virt_to_mfn(swapper_pg_dir));
-
         if (HYPERVISOR_vcpu_op(VCPUOP_initialise, cpu, ctxt))
                 BUG();
 
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 0e36cde12f7e..581521c843a5 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -106,7 +106,7 @@ static DEFINE_PER_CPU(struct xen_lock_waiting, lock_waiting);
 static cpumask_t waiting_cpus;
 
 static bool xen_pvspin = true;
-static void xen_lock_spinning(struct arch_spinlock *lock, __ticket_t want)
+__visible void xen_lock_spinning(struct arch_spinlock *lock, __ticket_t want)
 {
         int irq = __this_cpu_read(lock_kicker_irq);
         struct xen_lock_waiting *w = &__get_cpu_var(lock_waiting);
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 12a1ca707b94..7b78f88c1707 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -446,6 +446,7 @@ void xen_setup_timer(int cpu)
                                       IRQF_PERCPU|IRQF_NOBALANCING|IRQF_TIMER|
                                       IRQF_FORCE_RESUME,
                                       name, NULL);
+        (void)xen_set_irq_priority(irq, XEN_IRQ_PRIORITY_MAX);
 
         memcpy(evt, xen_clockevent, sizeof(*evt));
 
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S
index 7faed5869e5b..485b69585540 100644
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -11,8 +11,28 @@
 #include <asm/page_types.h>
 
 #include <xen/interface/elfnote.h>
+#include <xen/interface/features.h>
 #include <asm/xen/interface.h>
 
+#ifdef CONFIG_XEN_PVH
+#define PVH_FEATURES_STR  "|writable_descriptor_tables|auto_translated_physmap|supervisor_mode_kernel"
+/* Note the lack of 'hvm_callback_vector'. Older hypervisor will
+ * balk at this being part of XEN_ELFNOTE_FEATURES, so we put it in
+ * XEN_ELFNOTE_SUPPORTED_FEATURES which older hypervisors will ignore.
+ */
+#define PVH_FEATURES ((1 << XENFEAT_writable_page_tables) | \
+                      (1 << XENFEAT_auto_translated_physmap) | \
+                      (1 << XENFEAT_supervisor_mode_kernel) | \
+                      (1 << XENFEAT_hvm_callback_vector))
+/* The XENFEAT_writable_page_tables is not stricly neccessary as we set that
+ * up regardless whether this CONFIG option is enabled or not, but it
+ * clarifies what the right flags need to be.
+ */
+#else
+#define PVH_FEATURES_STR  ""
+#define PVH_FEATURES (0)
+#endif
+
         __INIT
 ENTRY(startup_xen)
         cld
@@ -95,7 +115,10 @@ NEXT_HYPERCALL(arch_6)
 #endif
         ELFNOTE(Xen, XEN_ELFNOTE_ENTRY,          _ASM_PTR startup_xen)
         ELFNOTE(Xen, XEN_ELFNOTE_HYPERCALL_PAGE, _ASM_PTR hypercall_page)
-        ELFNOTE(Xen, XEN_ELFNOTE_FEATURES,       .asciz "!writable_page_tables|pae_pgdir_above_4gb")
+        ELFNOTE(Xen, XEN_ELFNOTE_FEATURES,       .ascii "!writable_page_tables|pae_pgdir_above_4gb"; .asciz PVH_FEATURES_STR)
+        ELFNOTE(Xen, XEN_ELFNOTE_SUPPORTED_FEATURES, .long (PVH_FEATURES) |
+                                                (1 << XENFEAT_writable_page_tables) |
+                                                (1 << XENFEAT_dom0))
         ELFNOTE(Xen, XEN_ELFNOTE_PAE_MODE,       .asciz "yes")
         ELFNOTE(Xen, XEN_ELFNOTE_LOADER,         .asciz "generic")
         ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID,
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 95f8c6142328..1cb6f4c37300 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -123,4 +123,5 @@ __visible void xen_adjust_exception_frame(void);
 
 extern int xen_panic_handler_init(void);
 
+void xen_pvh_secondary_vcpu_init(int cpu);
 #endif /* XEN_OPS_H */
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 8d24dcb7cdac..ba56e11cbf77 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,7 +9,6 @@ config XTENSA
         select GENERIC_CLOCKEVENTS
         select VIRT_TO_BUS
         select GENERIC_IRQ_SHOW
-        select GENERIC_CPU_DEVICES
         select GENERIC_SCHED_CLOCK
         select MODULES_USE_ELF_RELA
         select GENERIC_PCI_IOMAP
@@ -19,6 +18,8 @@ config XTENSA
         select IRQ_DOMAIN
         select HAVE_OPROFILE
         select HAVE_FUNCTION_TRACER
+        select HAVE_IRQ_TIME_ACCOUNTING
+        select HAVE_PERF_EVENTS
         help
           Xtensa processors are 32-bit RISC machines designed by Tensilica
           primarily for embedded systems.  These processors are both
@@ -64,6 +65,12 @@ config MMU
 config VARIANT_IRQ_SWITCH
         def_bool n
 
+config HAVE_XTENSA_GPIO32
+        def_bool n
+
+config MAY_HAVE_SMP
+        def_bool n
+
 menu "Processor type and features"
 
 choice
@@ -73,16 +80,19 @@ choice
 config XTENSA_VARIANT_FSF
         bool "fsf - default (not generic) configuration"
         select MMU
+        select HAVE_XTENSA_GPIO32
 
 config XTENSA_VARIANT_DC232B
         bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
         select MMU
+        select HAVE_XTENSA_GPIO32
         help
           This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
 
 config XTENSA_VARIANT_DC233C
         bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
         select MMU
+        select HAVE_XTENSA_GPIO32
         help
           This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
 
@@ -104,6 +114,48 @@ config XTENSA_UNALIGNED_USER
 
 source "kernel/Kconfig.preempt"
 
+config HAVE_SMP
+        bool "System Supports SMP (MX)"
+        depends on MAY_HAVE_SMP
+        select XTENSA_MX
+        help
+          This option is use to indicate that the system-on-a-chip (SOC)
+          supports Multiprocessing. Multiprocessor support implemented above
+          the CPU core definition and currently needs to be selected manually.
+
+          Multiprocessor support in implemented with external cache and
+          interrupt controlers.
+
+          The MX interrupt distributer adds Interprocessor Interrupts
+          and causes the IRQ numbers to be increased by 4 for devices
+          like the open cores ethernet driver and the serial interface.
+
+          You still have to select "Enable SMP" to enable SMP on this SOC.
+
+config SMP
+        bool "Enable Symmetric multi-processing support"
+        depends on HAVE_SMP
+        select USE_GENERIC_SMP_HELPERS
+        select GENERIC_SMP_IDLE_THREAD
+        help
+          Enabled SMP Software; allows more than one CPU/CORE
+          to be activated during startup.
+
+config NR_CPUS
+        depends on SMP
+        int "Maximum number of CPUs (2-32)"
+        range 2 32
+        default "4"
+
+config HOTPLUG_CPU
+        bool "Enable CPU hotplug support"
+        depends on SMP
+        help
+          Say Y here to allow turning CPUs off and on. CPUs can be
+          controlled through /sys/devices/system/cpu.
+
+          Say N if you want to disable CPU hotplug.
+
 config MATH_EMULATION
         bool "Math emulation"
         help
@@ -150,9 +202,6 @@ config XTENSA_CALIBRATE_CCOUNT
 config SERIAL_CONSOLE
         def_bool n
 
-config XTENSA_ISS_NETWORK
-        def_bool n
-
 menu "Bus options"
 
 config PCI
@@ -179,7 +228,6 @@ config XTENSA_PLATFORM_ISS
         depends on TTY
         select XTENSA_CALIBRATE_CCOUNT
         select SERIAL_CONSOLE
-        select XTENSA_ISS_NETWORK
         help
           ISS is an acronym for Tensilica's Instruction Set Simulator.
 
diff --git a/arch/xtensa/boot/dts/lx60.dts b/arch/xtensa/boot/dts/lx60.dts
index 2eab3658e1bd..a0f8b8ad3920 100644
--- a/arch/xtensa/boot/dts/lx60.dts
+++ b/arch/xtensa/boot/dts/lx60.dts
@@ -3,7 +3,7 @@
 /include/ "xtfpga-flash-4m.dtsi"
 
 / {
-        compatible = "xtensa,lx60";
+        compatible = "cdns,xtensa-lx60";
         memory@0 {
                 device_type = "memory";
                 reg = <0x00000000 0x04000000>;
diff --git a/arch/xtensa/boot/dts/ml605.dts b/arch/xtensa/boot/dts/ml605.dts
index 6ed51d6554e6..905c3a5035e9 100644
--- a/arch/xtensa/boot/dts/ml605.dts
+++ b/arch/xtensa/boot/dts/ml605.dts
@@ -3,7 +3,7 @@
 /include/ "xtfpga-flash-16m.dtsi"
 
 / {
-        compatible = "xtensa,ml605";
+        compatible = "cdns,xtensa-ml605";
         memory@0 {
                 device_type = "memory";
                 reg = <0x00000000 0x08000000>;
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index 7eda6ecf7eef..46b4f5eab421 100644
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -1,5 +1,5 @@
 / {
-        compatible = "xtensa,xtfpga";
+        compatible = "cdns,xtensa-xtfpga";
         #address-cells = <1>;
         #size-cells = <1>;
         interrupt-parent = <&pic>;
@@ -17,7 +17,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
                 cpu@0 {
-                        compatible = "xtensa,cpu";
+                        compatible = "cdns,xtensa-cpu";
                         reg = <0>;
                         /* Filled in by platform_setup from FPGA register
                          * clock-frequency = <100000000>;
@@ -26,7 +26,7 @@
         };
 
         pic: pic {
-                compatible = "xtensa,pic";
+                compatible = "cdns,xtensa-pic";
                 /* one cell: internal irq number,
                  * two cells: second cell == 0: internal irq number
                  *            second cell == 1: external irq number
diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild
index 228d6aee3a16..0a337e4a8370 100644
--- a/arch/xtensa/include/asm/Kbuild
+++ b/arch/xtensa/include/asm/Kbuild
@@ -8,7 +8,6 @@ generic-y += emergency-restart.h
 generic-y += errno.h
 generic-y += exec.h
 generic-y += fcntl.h
-generic-y += futex.h
 generic-y += hardirq.h
 generic-y += ioctl.h
 generic-y += irq_regs.h
@@ -29,3 +28,4 @@ generic-y += topology.h
 generic-y += trace_clock.h
 generic-y += xor.h
 generic-y += preempt.h
+generic-y += hash.h
diff --git a/arch/xtensa/include/asm/barrier.h b/arch/xtensa/include/asm/barrier.h
index e1ee6b51dfc5..0a24b04d6b21 100644
--- a/arch/xtensa/include/asm/barrier.h
+++ b/arch/xtensa/include/asm/barrier.h
@@ -13,10 +13,6 @@
 #define rmb() barrier()
 #define wmb() mb()
 
-#ifdef CONFIG_SMP
-#error smp_* not defined
-#endif
-
 #include <asm-generic/barrier.h>
 
 #endif /* _XTENSA_SYSTEM_H */
diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h
index 84afe58d5d37..7b6873ae84c2 100644
--- a/arch/xtensa/include/asm/bitops.h
+++ b/arch/xtensa/include/asm/bitops.h
@@ -22,12 +22,8 @@
 #include <asm/processor.h>
 #include <asm/byteorder.h>
 
-#ifdef CONFIG_SMP
-# error SMP not supported on this architecture
-#endif
-
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
 
 #include <asm-generic/bitops/non-atomic.h>
 
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 127cd48883c4..555a98a18453 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -1,18 +1,14 @@
 /*
- * include/asm-xtensa/cacheflush.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * (C) 2001 - 2007 Tensilica Inc.
+ * (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_CACHEFLUSH_H
 #define _XTENSA_CACHEFLUSH_H
 
-#ifdef __KERNEL__
-
 #include <linux/mm.h>
 #include <asm/processor.h>
 #include <asm/page.h>
@@ -51,7 +47,6 @@ extern void __invalidate_icache_page(unsigned long);
 extern void __invalidate_icache_range(unsigned long, unsigned long);
 extern void __invalidate_dcache_range(unsigned long, unsigned long);
 
-
 #if XCHAL_DCACHE_IS_WRITEBACK
 extern void __flush_invalidate_dcache_all(void);
 extern void __flush_dcache_page(unsigned long);
@@ -87,9 +82,22 @@ static inline void __invalidate_icache_page_alias(unsigned long virt,
  * (see also Documentation/cachetlb.txt)
  */
 
-#if (DCACHE_WAY_SIZE > PAGE_SIZE)
+#if (DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP)
+
+#ifdef CONFIG_SMP
+void flush_cache_all(void);
+void flush_cache_range(struct vm_area_struct*, ulong, ulong);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct*,
+                             unsigned long, unsigned long);
+#else
+#define flush_cache_all local_flush_cache_all
+#define flush_cache_range local_flush_cache_range
+#define flush_icache_range local_flush_icache_range
+#define flush_cache_page  local_flush_cache_page
+#endif
 
-#define flush_cache_all()                                               \
+#define local_flush_cache_all()                                         \
         do {                                                            \
                 __flush_invalidate_dcache_all();                        \
                 __invalidate_icache_all();                              \
@@ -103,9 +111,11 @@ static inline void __invalidate_icache_page_alias(unsigned long virt,
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page*);
-extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
-extern void flush_cache_page(struct vm_area_struct*,
-                             unsigned long, unsigned long);
+
+void local_flush_cache_range(struct vm_area_struct *vma,
+                unsigned long start, unsigned long end);
+void local_flush_cache_page(struct vm_area_struct *vma,
+                unsigned long address, unsigned long pfn);
 
 #else
 
@@ -119,13 +129,14 @@ extern void flush_cache_page(struct vm_area_struct*,
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
 #define flush_dcache_page(page)                         do { } while (0)
 
-#define flush_cache_page(vma,addr,pfn)                  do { } while (0)
-#define flush_cache_range(vma,start,end)                do { } while (0)
+#define flush_icache_range local_flush_icache_range
+#define flush_cache_page(vma, addr, pfn)                do { } while (0)
+#define flush_cache_range(vma, start, end)              do { } while (0)
 
 #endif
 
 /* Ensure consistency between data and instruction cache. */
-#define flush_icache_range(start,end)                                   \
+#define local_flush_icache_range(start, end)                            \
         do {                                                            \
                 __flush_dcache_range(start, (end) - (start));           \
                 __invalidate_icache_range(start,(end) - (start));       \
@@ -253,5 +264,4 @@ static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
         }
 }
 
-#endif /* __KERNEL__ */
 #endif /* _XTENSA_CACHEFLUSH_H */
diff --git a/arch/xtensa/include/asm/delay.h b/arch/xtensa/include/asm/delay.h
index 3899610c1dff..24304b39a5c7 100644
--- a/arch/xtensa/include/asm/delay.h
+++ b/arch/xtensa/include/asm/delay.h
@@ -19,23 +19,57 @@ extern unsigned long loops_per_jiffy;
 
 static inline void __delay(unsigned long loops)
 {
-        /* 2 cycles per loop. */
-        __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
-                              : "=r" (loops) : "0" (loops));
+        if (__builtin_constant_p(loops) && loops < 2)
+                __asm__ __volatile__ ("nop");
+        else if (loops >= 2)
+                /* 2 cycles per loop. */
+                __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
+                                : "+r" (loops));
 }
 
-/* For SMP/NUMA systems, change boot_cpu_data to something like
- * local_cpu_data->... where local_cpu_data points to the current
- * cpu. */
+/* Undefined function to get compile-time error */
+void __bad_udelay(void);
+void __bad_ndelay(void);
 
-static __inline__ void udelay (unsigned long usecs)
+#define __MAX_UDELAY 30000
+#define __MAX_NDELAY 30000
+
+static inline void __udelay(unsigned long usecs)
 {
         unsigned long start = get_ccount();
-        unsigned long cycles = usecs * (loops_per_jiffy / (1000000UL / HZ));
+        unsigned long cycles = (usecs * (ccount_freq >> 15)) >> 5;
 
         /* Note: all variables are unsigned (can wrap around)! */
         while (((unsigned long)get_ccount()) - start < cycles)
-                ;
+                cpu_relax();
+}
+
+static inline void udelay(unsigned long usec)
+{
+        if (__builtin_constant_p(usec) && usec >= __MAX_UDELAY)
+                __bad_udelay();
+        else
+                __udelay(usec);
+}
+
+static inline void __ndelay(unsigned long nsec)
+{
+        /*
+         * Inner shift makes sure multiplication doesn't overflow
+         * for legitimate nsec values
+         */
+        unsigned long cycles = (nsec * (ccount_freq >> 15)) >> 15;
+        __delay(cycles);
+}
+
+#define ndelay(n) ndelay(n)
+
+static inline void ndelay(unsigned long nsec)
+{
+        if (__builtin_constant_p(nsec) && nsec >= __MAX_NDELAY)
+                __bad_ndelay();
+        else
+                __ndelay(nsec);
 }
 
 #endif
diff --git a/arch/xtensa/include/asm/ftrace.h b/arch/xtensa/include/asm/ftrace.h
index 73cc3f482304..736b9d214d80 100644
--- a/arch/xtensa/include/asm/ftrace.h
+++ b/arch/xtensa/include/asm/ftrace.h
@@ -18,7 +18,7 @@
                 __asm__ __volatile__ ( \
                         "mov %0, a0\n" \
                         "mov %1, a1\n" \
-                        : "=r"(a0), "=r"(a1) : : ); \
+                        : "=r"(a0), "=r"(a1)); \
                 MAKE_PC_FROM_RA(a0, a1); })
 #ifdef CONFIG_FRAME_POINTER
 extern unsigned long return_address(unsigned level);
diff --git a/arch/xtensa/include/asm/futex.h b/arch/xtensa/include/asm/futex.h
new file mode 100644
index 000000000000..b39531babec0
--- /dev/null
+++ b/arch/xtensa/include/asm/futex.h
@@ -0,0 +1,147 @@
+/*
+ * Atomic futex routines
+ *
+ * Based on the PowerPC implementataion
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 TangoTec Ltd.
+ *
+ * Baruch Siach <baruch@tkos.co.il>
+ */
+
+#ifndef _ASM_XTENSA_FUTEX_H
+#define _ASM_XTENSA_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <linux/errno.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+        __asm__ __volatile(                             \
+        "1:     l32i    %0, %2, 0\n"                    \
+                insn "\n"                               \
+        "       wsr     %0, scompare1\n"                \
+        "2:     s32c1i  %1, %2, 0\n"                    \
+        "       bne     %1, %0, 1b\n"                   \
+        "       movi    %1, 0\n"                        \
+        "3:\n"                                          \
+        "       .section .fixup,\"ax\"\n"               \
+        "       .align 4\n"                             \
+        "4:     .long   3b\n"                           \
+        "5:     l32r    %0, 4b\n"                       \
+        "       movi    %1, %3\n"                       \
+        "       jx      %0\n"                           \
+        "       .previous\n"                            \
+        "       .section __ex_table,\"a\"\n"            \
+        "       .long 1b,5b,2b,5b\n"                    \
+        "       .previous\n"                            \
+        : "=&r" (oldval), "=&r" (ret)                   \
+        : "r" (uaddr), "I" (-EFAULT), "r" (oparg)       \
+        : "memory")
+
+static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+                return -EFAULT;
+
+#if !XCHAL_HAVE_S32C1I
+        return -ENOSYS;
+#endif
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("mov %1, %4", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("add %1, %0, %4", ret, oldval, uaddr,
+                                oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or %1, %0, %4", ret, oldval, uaddr,
+                                oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and %1, %0, %4", ret, oldval, uaddr,
+                                ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor %1, %0, %4", ret, oldval, uaddr,
+                                oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (ret)
+                return ret;
+
+        switch (cmp) {
+        case FUTEX_OP_CMP_EQ: return (oldval == cmparg);
+        case FUTEX_OP_CMP_NE: return (oldval != cmparg);
+        case FUTEX_OP_CMP_LT: return (oldval < cmparg);
+        case FUTEX_OP_CMP_GE: return (oldval >= cmparg);
+        case FUTEX_OP_CMP_LE: return (oldval <= cmparg);
+        case FUTEX_OP_CMP_GT: return (oldval > cmparg);
+        }
+
+        return -ENOSYS;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
+{
+        int ret = 0;
+        u32 prev;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+                return -EFAULT;
+
+#if !XCHAL_HAVE_S32C1I
+        return -ENOSYS;
+#endif
+
+        __asm__ __volatile__ (
+        "       # futex_atomic_cmpxchg_inatomic\n"
+        "1:     l32i    %1, %3, 0\n"
+        "       mov     %0, %5\n"
+        "       wsr     %1, scompare1\n"
+        "2:     s32c1i  %0, %3, 0\n"
+        "3:\n"
+        "       .section .fixup,\"ax\"\n"
+        "       .align 4\n"
+        "4:     .long   3b\n"
+        "5:     l32r    %1, 4b\n"
+        "       movi    %0, %6\n"
+        "       jx      %1\n"
+        "       .previous\n"
+        "       .section __ex_table,\"a\"\n"
+        "       .long 1b,5b,2b,5b\n"
+        "       .previous\n"
+        : "+r" (ret), "=&r" (prev), "+m" (*uaddr)
+        : "r" (uaddr), "r" (oldval), "r" (newval), "I" (-EFAULT)
+        : "memory");
+
+        *uval = prev;
+        return ret;
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_XTENSA_FUTEX_H */
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index 722553f17db3..600781edc8a3 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -26,6 +26,9 @@
 #include <asm/pgtable.h>
 #include <asm/vectors.h>
 
+#define CA_BYPASS       (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
+#define CA_WRITEBACK    (_PAGE_CA_WB     | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
+
 #ifdef __ASSEMBLY__
 
 #define XTENSA_HWVERSION_RC_2009_0 230000
@@ -80,8 +83,6 @@
         /* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
          * and jump to the new mapping.
          */
-#define CA_BYPASS       (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
-#define CA_WRITEBACK    (_PAGE_CA_WB     | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
 
         srli    a3, a0, 27
         slli    a3, a3, 27
@@ -123,13 +124,13 @@
         wdtlb   a4, a5
         witlb   a4, a5
 
-        movi    a5, 0xe0000006
-        movi    a4, 0xf0000000 + CA_WRITEBACK
+        movi    a5, XCHAL_KIO_CACHED_VADDR + 6
+        movi    a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
         wdtlb   a4, a5
         witlb   a4, a5
 
-        movi    a5, 0xf0000006
-        movi    a4, 0xf0000000 + CA_BYPASS
+        movi    a5, XCHAL_KIO_BYPASS_VADDR + 6
+        movi    a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS
         wdtlb   a4, a5
         witlb   a4, a5
 
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 700c2e6f2d25..2a042d430c25 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -14,20 +14,26 @@
 #ifdef __KERNEL__
 #include <asm/byteorder.h>
 #include <asm/page.h>
+#include <asm/vectors.h>
 #include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include <linux/types.h>
 
-#define XCHAL_KIO_CACHED_VADDR  0xe0000000
-#define XCHAL_KIO_BYPASS_VADDR  0xf0000000
-#define XCHAL_KIO_PADDR         0xf0000000
-#define XCHAL_KIO_SIZE          0x10000000
-
 #define IOADDR(x)               (XCHAL_KIO_BYPASS_VADDR + (x))
 #define IO_SPACE_LIMIT ~0
 
 #ifdef CONFIG_MMU
+
+#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
+extern unsigned long xtensa_kio_paddr;
+
+static inline unsigned long xtensa_get_kio_paddr(void)
+{
+        return xtensa_kio_paddr;
+}
+#endif
+
 /*
  * Return the virtual address for the specified bus memory.
  * Note that we currently don't support any address outside the KIO segment.
diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h
index 4c0ccc9c4f4c..f71f88ea7646 100644
--- a/arch/xtensa/include/asm/irq.h
+++ b/arch/xtensa/include/asm/irq.h
@@ -43,5 +43,14 @@ static __inline__ int irq_canonicalize(int irq)
 }
 
 struct irqaction;
+struct irq_domain;
+
+void migrate_irqs(void);
+int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
+                unsigned long int_irq, unsigned long ext_irq,
+                unsigned long *out_hwirq, unsigned int *out_type);
+int xtensa_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw);
+unsigned xtensa_map_ext_irq(unsigned ext_irq);
+unsigned xtensa_get_ext_irq_no(unsigned irq);
 
 #endif  /* _XTENSA_IRQ_H */
diff --git a/arch/xtensa/include/asm/mmu.h b/arch/xtensa/include/asm/mmu.h
index 8554b2c8b17a..71afe418d0e5 100644
--- a/arch/xtensa/include/asm/mmu.h
+++ b/arch/xtensa/include/asm/mmu.h
@@ -1,11 +1,9 @@
 /*
- * include/asm-xtensa/mmu.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_MMU_H
@@ -15,8 +13,10 @@
 #include <asm-generic/mmu.h>
 #else
 
-/* Default "unsigned long" context */
-typedef unsigned long mm_context_t;
+typedef struct {
+        unsigned long asid[NR_CPUS];
+        unsigned int cpu;
+} mm_context_t;
 
 #endif /* CONFIG_MMU */
 #endif  /* _XTENSA_MMU_H */
diff --git a/arch/xtensa/include/asm/mmu_context.h b/arch/xtensa/include/asm/mmu_context.h
index d43525a286bb..d33c71a8c9ec 100644
--- a/arch/xtensa/include/asm/mmu_context.h
+++ b/arch/xtensa/include/asm/mmu_context.h
@@ -1,13 +1,11 @@
 /*
- * include/asm-xtensa/mmu_context.h
- *
  * Switch an MMU context.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_MMU_CONTEXT_H
@@ -20,22 +18,25 @@
 #include <linux/stringify.h>
 #include <linux/sched.h>
 
-#include <variant/core.h>
+#include <asm/vectors.h>
 
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm-generic/mm_hooks.h>
+#include <asm-generic/percpu.h>
 
 #if (XCHAL_HAVE_TLBS != 1)
 # error "Linux must have an MMU!"
 #endif
 
-extern unsigned long asid_cache;
+DECLARE_PER_CPU(unsigned long, asid_cache);
+#define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu)
 
 /*
  * NO_CONTEXT is the invalid ASID value that we don't ever assign to
- * any user or kernel context.
+ * any user or kernel context.  We use the reserved values in the
+ * ASID_INSERT macro below.
  *
  * 0 invalid
  * 1 kernel
@@ -49,6 +50,12 @@ extern unsigned long asid_cache;
 #define ASID_MASK       ((1 << XCHAL_MMU_ASID_BITS) - 1)
 #define ASID_INSERT(x)  (0x03020001 | (((x) & ASID_MASK) << 8))
 
+#ifdef CONFIG_MMU
+void init_mmu(void);
+#else
+static inline void init_mmu(void) { }
+#endif
+
 static inline void set_rasid_register (unsigned long val)
 {
         __asm__ __volatile__ (" wsr %0, rasid\n\t"
@@ -62,64 +69,77 @@ static inline unsigned long get_rasid_register (void)
         return tmp;
 }
 
-static inline void
-__get_new_mmu_context(struct mm_struct *mm)
+static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu)
 {
-        extern void flush_tlb_all(void);
-        if (! (++asid_cache & ASID_MASK) ) {
-                flush_tlb_all(); /* start new asid cycle */
-                asid_cache += ASID_USER_FIRST;
+        unsigned long asid = cpu_asid_cache(cpu);
+        if ((++asid & ASID_MASK) == 0) {
+                /*
+                 * Start new asid cycle; continue counting with next
+                 * incarnation bits; skipping over 0, 1, 2, 3.
+                 */
+                local_flush_tlb_all();
+                asid += ASID_USER_FIRST;
         }
-        mm->context = asid_cache;
+        cpu_asid_cache(cpu) = asid;
+        mm->context.asid[cpu] = asid;
+        mm->context.cpu = cpu;
 }
 
-static inline void
-__load_mmu_context(struct mm_struct *mm)
+static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
 {
-        set_rasid_register(ASID_INSERT(mm->context));
+        /*
+         * Check if our ASID is of an older version and thus invalid.
+         */
+
+        if (mm) {
+                unsigned long asid = mm->context.asid[cpu];
+
+                if (asid == NO_CONTEXT ||
+                                ((asid ^ cpu_asid_cache(cpu)) & ~ASID_MASK))
+                        get_new_mmu_context(mm, cpu);
+        }
+}
+
+static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
+{
+        get_mmu_context(mm, cpu);
+        set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
         invalidate_page_directory();
 }
 
 /*
  * Initialize the context related info for a new mm_struct
- * instance.
+ * instance.  Valid cpu values are 0..(NR_CPUS-1), so initializing
+ * to -1 says the process has never run on any core.
  */
 
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+static inline int init_new_context(struct task_struct *tsk,
+                struct mm_struct *mm)
 {
-        mm->context = NO_CONTEXT;
+        int cpu;
+        for_each_possible_cpu(cpu) {
+                mm->context.asid[cpu] = NO_CONTEXT;
+        }
+        mm->context.cpu = -1;
         return 0;
 }
 
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void
-activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
-        /* Unconditionally get a new ASID.  */
-
-        __get_new_mmu_context(next);
-        __load_mmu_context(next);
-}
-
-
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                              struct task_struct *tsk)
 {
-        unsigned long asid = asid_cache;
-
-        /* Check if our ASID is of an older version and thus invalid */
-
-        if (next->context == NO_CONTEXT || ((next->context^asid) & ~ASID_MASK))
-                __get_new_mmu_context(next);
-
-        __load_mmu_context(next);
+        unsigned int cpu = smp_processor_id();
+        int migrated = next->context.cpu != cpu;
+        /* Flush the icache if we migrated to a new core. */
+        if (migrated) {
+                __invalidate_icache_all();
+                next->context.cpu = cpu;
+        }
+        if (migrated || prev != next)
+                activate_context(next, cpu);
 }
 
-#define deactivate_mm(tsk, mm)  do { } while(0)
+#define activate_mm(prev, next) switch_mm((prev), (next), NULL)
+#define deactivate_mm(tsk, mm)  do { } while (0)
 
 /*
  * Destroy context related info for an mm_struct that is about
diff --git a/arch/xtensa/include/asm/mxregs.h b/arch/xtensa/include/asm/mxregs.h
new file mode 100644
index 000000000000..73dcc5456f68
--- /dev/null
+++ b/arch/xtensa/include/asm/mxregs.h
@@ -0,0 +1,46 @@
+/*
+ * Xtensa MX interrupt distributor
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 - 2013 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_MXREGS_H
+#define _XTENSA_MXREGS_H
+
+/*
+ * RER/WER at, as       Read/write external register
+ *      at: value
+ *      as: address
+ *
+ * Address      Value
+ * 00nn         0...0p..p       Interrupt Routing, route IRQ n to processor p
+ * 01pp         0...0d..d       16 bits (d) 'ored' as single IPI to processor p
+ * 0180         0...0m..m       Clear enable specified by mask (m)
+ * 0184         0...0m..m       Set enable specified by mask (m)
+ * 0190         0...0x..x       8-bit IPI partition register
+ *                              VVVVVVVVPPPPUUUUUUUUUUUUUUUUU
+ *                              V (10-bit) Release/Version
+ *                              P ( 4-bit) Number of cores - 1
+ *                              U (18-bit) ID
+ * 01a0         i.......i       32-bit ConfigID
+ * 0200         0...0m..m       RunStall core 'n'
+ * 0220         c               Cache coherency enabled
+ */
+
+#define MIROUT(irq)     (0x000 + (irq))
+#define MIPICAUSE(cpu)  (0x100 + (cpu))
+#define MIPISET(cause)  (0x140 + (cause))
+#define MIENG           0x180
+#define MIENGSET        0x184
+#define MIASG           0x188   /* Read Global Assert Register */
+#define MIASGSET        0x18c   /* Set Global Addert Regiter */
+#define MIPIPART        0x190
+#define SYSCFGID        0x1a0
+#define MPSCORE         0x200
+#define CCON            0x220
+
+#endif /* _XTENSA_MXREGS_H */
diff --git a/arch/xtensa/include/asm/perf_event.h b/arch/xtensa/include/asm/perf_event.h
new file mode 100644
index 000000000000..5aa4590acaae
--- /dev/null
+++ b/arch/xtensa/include/asm/perf_event.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_XTENSA_PERF_EVENT_H
+#define __ASM_XTENSA_PERF_EVENT_H
+
+#endif /* __ASM_XTENSA_PERF_EVENT_H */
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 7e409a5b0ec5..abb59708a3b7 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -191,5 +191,25 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
 #define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
 
+#ifndef XCHAL_HAVE_EXTERN_REGS
+#define XCHAL_HAVE_EXTERN_REGS 0
+#endif
+
+#if XCHAL_HAVE_EXTERN_REGS
+
+static inline void set_er(unsigned long value, unsigned long addr)
+{
+        asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory");
+}
+
+static inline unsigned long get_er(unsigned long addr)
+{
+        register unsigned long value;
+        asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory");
+        return value;
+}
+
+#endif /* XCHAL_HAVE_EXTERN_REGS */
+
 #endif  /* __ASSEMBLY__ */
 #endif  /* _XTENSA_PROCESSOR_H */
diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h
index 81f31bc9dde0..598e752dcbcd 100644
--- a/arch/xtensa/include/asm/ptrace.h
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -59,9 +59,17 @@ struct pt_regs {
         (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
 # define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
 # define instruction_pointer(regs) ((regs)->pc)
+# define return_pointer(regs) (MAKE_PC_FROM_RA((regs)->areg[0], \
+                                               (regs)->areg[1]))
 
 # ifndef CONFIG_SMP
 #  define profile_pc(regs) instruction_pointer(regs)
+# else
+#  define profile_pc(regs)                                              \
+        ({                                                              \
+                in_lock_functions(instruction_pointer(regs)) ?          \
+                return_pointer(regs) : instruction_pointer(regs);       \
+        })
 # endif
 
 #define user_stack_pointer(regs) ((regs)->areg[1])
diff --git a/arch/xtensa/include/asm/smp.h b/arch/xtensa/include/asm/smp.h
index 83c569e3bdbd..4e43f5643891 100644
--- a/arch/xtensa/include/asm/smp.h
+++ b/arch/xtensa/include/asm/smp.h
@@ -1,27 +1,43 @@
 /*
- * include/asm-xtensa/smp.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_SMP_H
 #define _XTENSA_SMP_H
 
-extern struct xtensa_cpuinfo boot_cpu_data;
+#ifdef CONFIG_SMP
 
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
+#define cpu_logical_map(cpu)    (cpu)
 
-struct xtensa_cpuinfo {
-        unsigned long   *pgd_cache;
-        unsigned long   *pte_cache;
-        unsigned long   pgtable_cache_sz;
+struct start_info {
+        unsigned long stack;
 };
+extern struct start_info start_info;
 
-#define cpu_logical_map(cpu)    (cpu)
+struct cpumask;
+void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+void arch_send_call_function_single_ipi(int cpu);
+
+void smp_init_cpus(void);
+void secondary_init_irq(void);
+void ipi_init(void);
+struct seq_file;
+void show_ipi_list(struct seq_file *p, int prec);
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+void __cpu_die(unsigned int cpu);
+int __cpu_disable(void);
+void cpu_die(void);
+void cpu_restart(void);
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+#endif /* CONFIG_SMP */
 
 #endif  /* _XTENSA_SMP_H */
diff --git a/arch/xtensa/include/asm/spinlock.h b/arch/xtensa/include/asm/spinlock.h
index 03975906b36f..1d95fa5dcd10 100644
--- a/arch/xtensa/include/asm/spinlock.h
+++ b/arch/xtensa/include/asm/spinlock.h
@@ -28,13 +28,13 @@
  *    1         somebody owns the spinlock
  */
 
-#define __raw_spin_is_locked(x) ((x)->slock != 0)
-#define __raw_spin_unlock_wait(lock) \
-        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+#define arch_spin_is_locked(x) ((x)->slock != 0)
+#define arch_spin_unlock_wait(lock) \
+        do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -51,7 +51,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
 
 /* Returns 1 if the lock is obtained, 0 otherwise. */
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -67,7 +67,7 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
         return tmp == 0 ? 1 : 0;
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
 
@@ -96,9 +96,9 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  *  0x80000000  one writer owns the rwlock, no other writers, no readers
  */
 
-#define __raw_write_can_lock(x)  ((x)->lock == 0)
+#define arch_write_can_lock(x)  ((x)->lock == 0)
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
@@ -116,7 +116,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
 
 /* Returns 1 if the lock is obtained, 0 otherwise. */
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
@@ -133,7 +133,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
         return tmp == 0 ? 1 : 0;
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
 
@@ -145,7 +145,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
                         : "memory");
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
         unsigned long tmp;
         unsigned long result;
@@ -164,7 +164,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
 
 /* Returns 1 if the lock is obtained, 0 otherwise. */
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
         unsigned long result;
         unsigned long tmp;
@@ -184,7 +184,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
         return result == 0;
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned long tmp1, tmp2;
 
@@ -199,4 +199,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
                         : "memory");
 }
 
+#define arch_read_lock_flags(lock, flags)       arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags)      arch_write_lock(lock)
+
 #endif  /* _XTENSA_SPINLOCK_H */
diff --git a/arch/xtensa/include/asm/spinlock_types.h b/arch/xtensa/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..7ec5ce10c9e9
--- /dev/null
+++ b/arch/xtensa/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SPINLOCK_TYPES_H
+#define __ASM_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int slock;
+} arch_spinlock_t;
+
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
+
+typedef struct {
+        volatile unsigned int lock;
+} arch_rwlock_t;
+
+#define __ARCH_RW_LOCK_UNLOCKED         { 0 }
+
+#endif
diff --git a/arch/xtensa/include/asm/timex.h b/arch/xtensa/include/asm/timex.h
index 27fa3c170662..ca929e6a38b5 100644
--- a/arch/xtensa/include/asm/timex.h
+++ b/arch/xtensa/include/asm/timex.h
@@ -1,18 +1,14 @@
 /*
- * include/asm-xtensa/timex.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2008 Tensilica Inc.
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_TIMEX_H
 #define _XTENSA_TIMEX_H
 
-#ifdef __KERNEL__
-
 #include <asm/processor.h>
 #include <linux/stringify.h>
 
@@ -39,14 +35,9 @@ extern unsigned long ccount_freq;
 
 typedef unsigned long long cycles_t;
 
-/*
- * Only used for SMP.
- */
-
-extern cycles_t cacheflush_time;
-
 #define get_cycles()    (0)
 
+void local_timer_setup(unsigned cpu);
 
 /*
  * Register access.
@@ -81,5 +72,4 @@ static inline void set_linux_timer (unsigned long ccompare)
         WSR_CCOMPARE(LINUX_TIMER, ccompare);
 }
 
-#endif  /* __KERNEL__ */
 #endif  /* _XTENSA_TIMEX_H */
diff --git a/arch/xtensa/include/asm/tlbflush.h b/arch/xtensa/include/asm/tlbflush.h
index 43dd348a5a47..fc34274ce41b 100644
--- a/arch/xtensa/include/asm/tlbflush.h
+++ b/arch/xtensa/include/asm/tlbflush.h
@@ -1,18 +1,14 @@
 /*
- * include/asm-xtensa/tlbflush.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
  */
 
 #ifndef _XTENSA_TLBFLUSH_H
 #define _XTENSA_TLBFLUSH_H
 
-#ifdef __KERNEL__
-
 #include <linux/stringify.h>
 #include <asm/processor.h>
 
@@ -34,12 +30,37 @@
  *  - flush_tlb_range(mm, start, end) flushes a range of pages
  */
 
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct*);
-extern void flush_tlb_page(struct vm_area_struct*,unsigned long);
-extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long);
+void local_flush_tlb_all(void);
+void local_flush_tlb_mm(struct mm_struct *mm);
+void local_flush_tlb_page(struct vm_area_struct *vma,
+                unsigned long page);
+void local_flush_tlb_range(struct vm_area_struct *vma,
+                unsigned long start, unsigned long end);
+
+#ifdef CONFIG_SMP
+
+void flush_tlb_all(void);
+void flush_tlb_mm(struct mm_struct *);
+void flush_tlb_page(struct vm_area_struct *, unsigned long);
+void flush_tlb_range(struct vm_area_struct *, unsigned long,
+                unsigned long);
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+                unsigned long end)
+{
+        flush_tlb_all();
+}
+
+#else /* !CONFIG_SMP */
+
+#define flush_tlb_all()                    local_flush_tlb_all()
+#define flush_tlb_mm(mm)                   local_flush_tlb_mm(mm)
+#define flush_tlb_page(vma, page)          local_flush_tlb_page(vma, page)
+#define flush_tlb_range(vma, vmaddr, end)  local_flush_tlb_range(vma, vmaddr, \
+                                                                 end)
+#define flush_tlb_kernel_range(start, end) local_flush_tlb_all()
 
-#define flush_tlb_kernel_range(start,end) flush_tlb_all()
+#endif /* CONFIG_SMP */
 
 /* TLB operations. */
 
@@ -187,5 +208,4 @@ static inline unsigned long read_itlb_translation (int way)
 }
 
 #endif  /* __ASSEMBLY__ */
-#endif  /* __KERNEL__ */
 #endif  /* _XTENSA_TLBFLUSH_H */
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h
index 917488a0ab00..8c194f6af45e 100644
--- a/arch/xtensa/include/asm/traps.h
+++ b/arch/xtensa/include/asm/traps.h
@@ -19,6 +19,7 @@
  */
 extern void * __init trap_set_handler(int cause, void *handler);
 extern void do_unhandled(struct pt_regs *regs, unsigned long exccause);
+void secondary_trap_init(void);
 
 static inline void spill_registers(void)
 {
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h
index c52b656d0310..5791b45d5a5d 100644
--- a/arch/xtensa/include/asm/vectors.h
+++ b/arch/xtensa/include/asm/vectors.h
@@ -20,6 +20,17 @@
 
 #include <variant/core.h>
 
+#define XCHAL_KIO_CACHED_VADDR          0xe0000000
+#define XCHAL_KIO_BYPASS_VADDR          0xf0000000
+#define XCHAL_KIO_DEFAULT_PADDR         0xf0000000
+#define XCHAL_KIO_SIZE                  0x10000000
+
+#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
+#define XCHAL_KIO_PADDR                 xtensa_get_kio_paddr()
+#else
+#define XCHAL_KIO_PADDR                 XCHAL_KIO_DEFAULT_PADDR
+#endif
+
 #if defined(CONFIG_MMU)
 
 /* Will Become VECBASE */
@@ -30,11 +41,9 @@
 
 #if defined(XCHAL_HAVE_PTP_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
   /* MMU v3  - XCHAL_HAVE_PTP_MMU  == 1 */
-  #define PHYSICAL_MEMORY_ADDRESS       0x00000000
   #define LOAD_MEMORY_ADDRESS           0x00003000
 #else
   /* MMU V2 -  XCHAL_HAVE_PTP_MMU  == 0 */
-  #define PHYSICAL_MEMORY_ADDRESS       0xD0000000
   #define LOAD_MEMORY_ADDRESS           0xD0003000
 #endif
 
@@ -46,7 +55,6 @@
 
   /* Location of the start of the kernel text, _start */
   #define KERNELOFFSET                  0x00003000
-  #define PHYSICAL_MEMORY_ADDRESS       0x00000000
 
   /* Loaded just above possibly live vectors */
   #define LOAD_MEMORY_ADDRESS           0x00003000
@@ -54,7 +62,6 @@
 #endif /* CONFIG_MMU */
 
 #define XC_VADDR(offset)                (VIRTUAL_MEMORY_ADDRESS  + offset)
-#define XC_PADDR(offset)                (PHYSICAL_MEMORY_ADDRESS + offset)
 
 /* Used to set VECBASE register */
 #define VECBASE_RESET_VADDR             VIRTUAL_MEMORY_ADDRESS
@@ -67,7 +74,7 @@
                                                 VECBASE_RESET_VADDR)
 #define RESET_VECTOR1_VADDR             XC_VADDR(RESET_VECTOR1_VECOFS)
 
-#if XCHAL_HAVE_VECBASE
+#if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE
 
 #define USER_VECTOR_VADDR               XC_VADDR(XCHAL_USER_VECOFS)
 #define KERNEL_VECTOR_VADDR             XC_VADDR(XCHAL_KERNEL_VECOFS)
@@ -81,11 +88,9 @@
 
 #define DEBUG_VECTOR_VADDR              XC_VADDR(XCHAL_DEBUG_VECOFS)
 
-#undef  XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_NMI_VECTOR_VADDR          XC_VADDR(XCHAL_NMI_VECOFS)
+#define NMI_VECTOR_VADDR                XC_VADDR(XCHAL_NMI_VECOFS)
 
-#undef  XCHAL_INTLEVEL7_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_VADDR    XC_VADDR(XCHAL_INTLEVEL7_VECOFS)
+#define INTLEVEL7_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL7_VECOFS)
 
 /*
  * These XCHAL_* #defines from varian/core.h
diff --git a/arch/xtensa/include/uapi/asm/socket.h b/arch/xtensa/include/uapi/asm/socket.h
index 7db5c22faa68..39acec0cf0b1 100644
--- a/arch/xtensa/include/uapi/asm/socket.h
+++ b/arch/xtensa/include/uapi/asm/socket.h
@@ -89,4 +89,6 @@
 
 #define SO_MAX_PACING_RATE      47
 
+#define SO_BPF_EXTENSIONS       48
+
 #endif  /* _XTENSA_SOCKET_H */
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index f90265ec1ccc..18d962a8c0c2 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_KGDB) += xtensa-stub.o
 obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
 obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
+obj-$(CONFIG_SMP) += smp.o mxhead.o
 
 AFLAGS_head.o += -mtext-section-literals
 
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 7d740ebbe198..aeeb3cc8a410 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -19,6 +19,7 @@
 #include <asm/page.h>
 #include <asm/cacheasm.h>
 #include <asm/initialize_mmu.h>
+#include <asm/mxregs.h>
 
 #include <linux/init.h>
 #include <linux/linkage.h>
@@ -54,7 +55,7 @@ ENTRY(_start)
 
         /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
         wsr     a2, excsave1
-        _j      _SetupMMU
+        _j      _SetupOCD
 
         .align  4
         .literal_position
@@ -62,6 +63,23 @@ ENTRY(_start)
         .word   _startup
 
         .align  4
+_SetupOCD:
+        /*
+         * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
+         * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
+         * xt-gdb to single step via DEBUG exceptions received directly
+         * by ocd.
+         */
+        movi    a1, 1
+        movi    a0, 0
+        wsr     a1, windowstart
+        wsr     a0, windowbase
+        rsync
+
+        movi    a1, LOCKLEVEL
+        wsr     a1, ps
+        rsync
+
         .global _SetupMMU
 _SetupMMU:
         Offset = _SetupMMU - _start
@@ -85,24 +103,11 @@ _SetupMMU:
 
 ENDPROC(_start)
 
-        __INIT
+        __REF
         .literal_position
 
 ENTRY(_startup)
 
-        /* Disable interrupts and exceptions. */
-
-        movi    a0, LOCKLEVEL
-        wsr     a0, ps
-
-        /* Start with a fresh windowbase and windowstart.  */
-
-        movi    a1, 1
-        movi    a0, 0
-        wsr     a1, windowstart
-        wsr     a0, windowbase
-        rsync
-
         /* Set a0 to 0 for the remaining initialization. */
 
         movi    a0, 0
@@ -154,17 +159,6 @@ ENTRY(_startup)
         wsr     a0, cpenable
 #endif
 
-        /* Set PS.INTLEVEL=LOCKLEVEL, PS.WOE=0, kernel stack, PS.EXCM=0
-         *
-         * Note: PS.EXCM must be cleared before using any loop
-         *       instructions; otherwise, they are silently disabled, and
-         *       at most one iteration of the loop is executed.
-         */
-
-        movi    a1, LOCKLEVEL
-        wsr     a1, ps
-        rsync
-
         /*  Initialize the caches.
          *  a2, a3 are just working registers (clobbered).
          */
@@ -182,6 +176,37 @@ ENTRY(_startup)
 
         isync
 
+#ifdef CONFIG_HAVE_SMP
+        movi    a2, CCON        # MX External Register to Configure Cache
+        movi    a3, 1
+        wer     a3, a2
+#endif
+
+        /* Setup stack and enable window exceptions (keep irqs disabled) */
+
+        movi    a1, start_info
+        l32i    a1, a1, 0
+
+        movi    a2, (1 << PS_WOE_BIT) | LOCKLEVEL
+                                        # WOE=1, INTLEVEL=LOCKLEVEL, UM=0
+        wsr     a2, ps                  # (enable reg-windows; progmode stack)
+        rsync
+
+        /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
+
+        movi    a2, debug_exception
+        wsr     a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
+
+#ifdef CONFIG_SMP
+        /*
+         * Notice that we assume with SMP that cores have PRID
+         * supported by the cores.
+         */
+        rsr     a2, prid
+        bnez    a2, .Lboot_secondary
+
+#endif  /* CONFIG_SMP */
+
         /* Unpack data sections
          *
          * The linker script used to build the Linux kernel image
@@ -234,24 +259,7 @@ ENTRY(_startup)
         ___invalidate_icache_all a2 a3
         isync
 
-        /* Setup stack and enable window exceptions (keep irqs disabled) */
-
-        movi    a1, init_thread_union
-        addi    a1, a1, KERNEL_STACK_SIZE
-
-        movi    a2, (1 << PS_WOE_BIT) | LOCKLEVEL
-                                        # WOE=1, INTLEVEL=LOCKLEVEL, UM=0
-        wsr     a2, ps                  # (enable reg-windows; progmode stack)
-        rsync
-
-        /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
-
-        movi    a2, debug_exception
-        wsr     a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
-
-        /* Set up EXCSAVE[1] to point to the exc_table. */
-
-        movi    a6, exc_table
+        movi    a6, 0
         xsr     a6, excsave1
 
         /* init_arch kick-starts the linux kernel */
@@ -265,8 +273,93 @@ ENTRY(_startup)
 should_never_return:
         j       should_never_return
 
+#ifdef CONFIG_SMP
+.Lboot_secondary:
+
+        movi    a2, cpu_start_ccount
+1:
+        l32i    a3, a2, 0
+        beqi    a3, 0, 1b
+        movi    a3, 0
+        s32i    a3, a2, 0
+        memw
+1:
+        l32i    a3, a2, 0
+        beqi    a3, 0, 1b
+        wsr     a3, ccount
+        movi    a3, 0
+        s32i    a3, a2, 0
+        memw
+
+        movi    a6, 0
+        wsr     a6, excsave1
+
+        movi    a4, secondary_start_kernel
+        callx4  a4
+        j       should_never_return
+
+#endif  /* CONFIG_SMP */
+
 ENDPROC(_startup)
 
+#ifdef CONFIG_HOTPLUG_CPU
+
+ENTRY(cpu_restart)
+
+#if XCHAL_DCACHE_IS_WRITEBACK
+        ___flush_invalidate_dcache_all a2 a3
+#else
+        ___invalidate_dcache_all a2 a3
+#endif
+        memw
+        movi    a2, CCON        # MX External Register to Configure Cache
+        movi    a3, 0
+        wer     a3, a2
+        extw
+
+        rsr     a0, prid
+        neg     a2, a0
+        movi    a3, cpu_start_id
+        s32i    a2, a3, 0
+#if XCHAL_DCACHE_IS_WRITEBACK
+        dhwbi   a3, 0
+#endif
+1:
+        l32i    a2, a3, 0
+        dhi     a3, 0
+        bne     a2, a0, 1b
+
+        /*
+         * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
+         * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
+         * xt-gdb to single step via DEBUG exceptions received directly
+         * by ocd.
+         */
+        movi    a1, 1
+        movi    a0, 0
+        wsr     a1, windowstart
+        wsr     a0, windowbase
+        rsync
+
+        movi    a1, LOCKLEVEL
+        wsr     a1, ps
+        rsync
+
+        j       _startup
+
+ENDPROC(cpu_restart)
+
+#endif  /* CONFIG_HOTPLUG_CPU */
+
+/*
+ * DATA section
+ */
+
+        .section ".data.init.refok"
+        .align  4
+ENTRY(start_info)
+        .long   init_thread_union + KERNEL_STACK_SIZE
+
 /*
  * BSS section
  */
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 6f4f9749cff7..482868a2de6e 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -4,7 +4,7 @@
  * Xtensa built-in interrupt controller and some generic functions copied
  * from i386.
  *
- * Copyright (C) 2002 - 2006 Tensilica, Inc.
+ * Copyright (C) 2002 - 2013 Tensilica, Inc.
  * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  *
  *
@@ -18,36 +18,27 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel_stat.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/xtensa-mx.h>
+#include <linux/irqchip/xtensa-pic.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 
+#include <asm/mxregs.h>
 #include <asm/uaccess.h>
 #include <asm/platform.h>
 
-static unsigned int cached_irq_mask;
-
 atomic_t irq_err_count;
 
-static struct irq_domain *root_domain;
-
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- */
-
 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
 {
-        struct pt_regs *old_regs = set_irq_regs(regs);
-        int irq = irq_find_mapping(root_domain, hwirq);
+        int irq = irq_find_mapping(NULL, hwirq);
 
         if (hwirq >= NR_IRQS) {
                 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
                                 __func__, hwirq);
         }
 
-        irq_enter();
-
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
         /* Debugging check for stack overflow: is there less than 1KB free? */
         {
@@ -62,95 +53,69 @@ asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
         }
 #endif
         generic_handle_irq(irq);
-
-        irq_exit();
-        set_irq_regs(old_regs);
 }
 
 int arch_show_interrupts(struct seq_file *p, int prec)
 {
+#ifdef CONFIG_SMP
+        show_ipi_list(p, prec);
+#endif
         seq_printf(p, "%*s: ", prec, "ERR");
         seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
         return 0;
 }
 
-static void xtensa_irq_mask(struct irq_data *d)
-{
-        cached_irq_mask &= ~(1 << d->hwirq);
-        set_sr (cached_irq_mask, intenable);
-}
-
-static void xtensa_irq_unmask(struct irq_data *d)
-{
-        cached_irq_mask |= 1 << d->hwirq;
-        set_sr (cached_irq_mask, intenable);
-}
-
-static void xtensa_irq_enable(struct irq_data *d)
-{
-        variant_irq_enable(d->hwirq);
-        xtensa_irq_unmask(d);
-}
-
-static void xtensa_irq_disable(struct irq_data *d)
-{
-        xtensa_irq_mask(d);
-        variant_irq_disable(d->hwirq);
-}
-
-static void xtensa_irq_ack(struct irq_data *d)
-{
-        set_sr(1 << d->hwirq, intclear);
-}
-
-static int xtensa_irq_retrigger(struct irq_data *d)
+int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
+                unsigned long int_irq, unsigned long ext_irq,
+                unsigned long *out_hwirq, unsigned int *out_type)
 {
-        set_sr(1 << d->hwirq, intset);
-        return 1;
+        if (WARN_ON(intsize < 1 || intsize > 2))
+                return -EINVAL;
+        if (intsize == 2 && intspec[1] == 1) {
+                int_irq = xtensa_map_ext_irq(ext_irq);
+                if (int_irq < XCHAL_NUM_INTERRUPTS)
+                        *out_hwirq = int_irq;
+                else
+                        return -EINVAL;
+        } else {
+                *out_hwirq = int_irq;
+        }
+        *out_type = IRQ_TYPE_NONE;
+        return 0;
 }
 
-static struct irq_chip xtensa_irq_chip = {
-        .name           = "xtensa",
-        .irq_enable     = xtensa_irq_enable,
-        .irq_disable    = xtensa_irq_disable,
-        .irq_mask       = xtensa_irq_mask,
-        .irq_unmask     = xtensa_irq_unmask,
-        .irq_ack        = xtensa_irq_ack,
-        .irq_retrigger  = xtensa_irq_retrigger,
-};
-
-static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
+int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
                 irq_hw_number_t hw)
 {
+        struct irq_chip *irq_chip = d->host_data;
         u32 mask = 1 << hw;
 
         if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
-                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                irq_set_chip_and_handler_name(irq, irq_chip,
                                 handle_simple_irq, "level");
                 irq_set_status_flags(irq, IRQ_LEVEL);
         } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
-                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                irq_set_chip_and_handler_name(irq, irq_chip,
                                 handle_edge_irq, "edge");
                 irq_clear_status_flags(irq, IRQ_LEVEL);
         } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
-                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                irq_set_chip_and_handler_name(irq, irq_chip,
                                 handle_level_irq, "level");
                 irq_set_status_flags(irq, IRQ_LEVEL);
         } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
-                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
-                                handle_edge_irq, "edge");
+                irq_set_chip_and_handler_name(irq, irq_chip,
+                                handle_percpu_irq, "timer");
                 irq_clear_status_flags(irq, IRQ_LEVEL);
         } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
                 /* XCHAL_INTTYPE_MASK_NMI */
-
-                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
+                irq_set_chip_and_handler_name(irq, irq_chip,
                                 handle_level_irq, "level");
                 irq_set_status_flags(irq, IRQ_LEVEL);
         }
         return 0;
 }
 
-static unsigned map_ext_irq(unsigned ext_irq)
+unsigned xtensa_map_ext_irq(unsigned ext_irq)
 {
         unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
                 XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
@@ -163,55 +128,77 @@ static unsigned map_ext_irq(unsigned ext_irq)
         return XCHAL_NUM_INTERRUPTS;
 }
 
-/*
- * Device Tree IRQ specifier translation function which works with one or
- * two cell bindings. First cell value maps directly to the hwirq number.
- * Second cell if present specifies whether hwirq number is external (1) or
- * internal (0).
- */
-int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
-                const u32 *intspec, unsigned int intsize,
-                unsigned long *out_hwirq, unsigned int *out_type)
+unsigned xtensa_get_ext_irq_no(unsigned irq)
 {
-        if (WARN_ON(intsize < 1 || intsize > 2))
-                return -EINVAL;
-        if (intsize == 2 && intspec[1] == 1) {
-                unsigned int_irq = map_ext_irq(intspec[0]);
-                if (int_irq < XCHAL_NUM_INTERRUPTS)
-                        *out_hwirq = int_irq;
-                else
-                        return -EINVAL;
-        } else {
-                *out_hwirq = intspec[0];
-        }
-        *out_type = IRQ_TYPE_NONE;
-        return 0;
+        unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
+                XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
+                ((1u << irq) - 1);
+        return hweight32(mask);
 }
 
-static const struct irq_domain_ops xtensa_irq_domain_ops = {
-        .xlate = xtensa_irq_domain_xlate,
-        .map = xtensa_irq_map,
-};
-
 void __init init_IRQ(void)
 {
-        struct device_node *intc = NULL;
-
-        cached_irq_mask = 0;
-        set_sr(~0, intclear);
-
 #ifdef CONFIG_OF
-        /* The interrupt controller device node is mandatory */
-        intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
-        BUG_ON(!intc);
-
-        root_domain = irq_domain_add_linear(intc, NR_IRQS,
-                        &xtensa_irq_domain_ops, NULL);
+        irqchip_init();
+#else
+#ifdef CONFIG_HAVE_SMP
+        xtensa_mx_init_legacy(NULL);
 #else
-        root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
-                        &xtensa_irq_domain_ops, NULL);
+        xtensa_pic_init_legacy(NULL);
+#endif
 #endif
-        irq_set_default_host(root_domain);
 
+#ifdef CONFIG_SMP
+        ipi_init();
+#endif
         variant_init_irq();
 }
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&desc->lock, flags);
+        if (chip->irq_set_affinity)
+                chip->irq_set_affinity(data, cpumask_of(cpu), false);
+        raw_spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+/*
+ * The CPU has been marked offline.  Migrate IRQs off this CPU.  If
+ * the affinity settings do not allow other CPUs, force them onto any
+ * available CPU.
+ */
+void migrate_irqs(void)
+{
+        unsigned int i, cpu = smp_processor_id();
+        struct irq_desc *desc;
+
+        for_each_irq_desc(i, desc) {
+                struct irq_data *data = irq_desc_get_irq_data(desc);
+                unsigned int newcpu;
+
+                if (irqd_is_per_cpu(data))
+                        continue;
+
+                if (!cpumask_test_cpu(cpu, data->affinity))
+                        continue;
+
+                newcpu = cpumask_any_and(data->affinity, cpu_online_mask);
+
+                if (newcpu >= nr_cpu_ids) {
+                        pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
+                                            i, cpu);
+
+                        cpumask_setall(data->affinity);
+                        newcpu = cpumask_any_and(data->affinity,
+                                                 cpu_online_mask);
+                }
+
+                route_irq(data, i, newcpu);
+        }
+}
+#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/xtensa/kernel/mxhead.S b/arch/xtensa/kernel/mxhead.S
new file mode 100644
index 000000000000..77a161a112c5
--- /dev/null
+++ b/arch/xtensa/kernel/mxhead.S
@@ -0,0 +1,85 @@
+/*
+ * Xtensa Secondary Processors startup code.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 - 2013 Tensilica Inc.
+ *
+ * Joe Taylor <joe@tensilica.com>
+ * Chris Zankel <chris@zankel.net>
+ * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
+ * Pete Delaney <piet@tensilica.com>
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/cacheasm.h>
+#include <asm/initialize_mmu.h>
+#include <asm/mxregs.h>
+#include <asm/regs.h>
+
+
+        .section .SecondaryResetVector.text, "ax"
+
+
+ENTRY(_SecondaryResetVector)
+        _j _SetupOCD
+
+        .begin  no-absolute-literals
+        .literal_position
+
+_SetupOCD:
+        /*
+         * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
+         * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
+         * xt-gdb to single step via DEBUG exceptions received directly
+         * by ocd.
+         */
+        movi    a1, 1
+        movi    a0, 0
+        wsr     a1, windowstart
+        wsr     a0, windowbase
+        rsync
+
+        movi    a1, LOCKLEVEL
+        wsr     a1, ps
+        rsync
+
+_SetupMMU:
+        Offset = _SetupMMU - _SecondaryResetVector
+
+#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
+        initialize_mmu
+#endif
+
+        /*
+         * Start Secondary Processors with NULL pointer to boot params.
+         */
+        movi    a2, 0                           #  a2 == NULL
+        movi    a3, _startup
+        jx      a3
+
+        .end    no-absolute-literals
+
+
+        .section        .SecondaryResetVector.remapped_text, "ax"
+        .global         _RemappedSecondaryResetVector
+
+        .org 0                                  # Need to do org before literals
+
+_RemappedSecondaryResetVector:
+        .begin  no-absolute-literals
+        .literal_position
+
+        _j      _RemappedSetupMMU
+        . = _RemappedSecondaryResetVector + Offset
+
+_RemappedSetupMMU:
+
+#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
+        initialize_mmu
+#endif
+
+        .end    no-absolute-literals
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 6e2b6638122d..7d12af1317f1 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -21,6 +21,8 @@
 #include <linux/screen_info.h>
 #include <linux/bootmem.h>
 #include <linux/kernel.h>
+#include <linux/percpu.h>
+#include <linux/cpu.h>
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 
@@ -37,6 +39,7 @@
 #endif
 
 #include <asm/bootparam.h>
+#include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/timex.h>
@@ -45,6 +48,7 @@
 #include <asm/setup.h>
 #include <asm/param.h>
 #include <asm/traps.h>
+#include <asm/smp.h>
 
 #include <platform/hardware.h>
 
@@ -85,12 +89,6 @@ static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 
 sysmem_info_t __initdata sysmem;
 
-#ifdef CONFIG_MMU
-extern void init_mmu(void);
-#else
-static inline void init_mmu(void) { }
-#endif
-
 extern int mem_reserve(unsigned long, unsigned long, int);
 extern void bootmem_init(void);
 extern void zones_init(void);
@@ -214,6 +212,42 @@ static int __init parse_bootparam(const bp_tag_t* tag)
 #ifdef CONFIG_OF
 bool __initdata dt_memory_scan = false;
 
+#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
+unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
+EXPORT_SYMBOL(xtensa_kio_paddr);
+
+static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        const __be32 *ranges;
+        unsigned long len;
+
+        if (depth > 1)
+                return 0;
+
+        if (!of_flat_dt_is_compatible(node, "simple-bus"))
+                return 0;
+
+        ranges = of_get_flat_dt_prop(node, "ranges", &len);
+        if (!ranges)
+                return 1;
+        if (len == 0)
+                return 1;
+
+        xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
+        /* round down to nearest 256MB boundary */
+        xtensa_kio_paddr &= 0xf0000000;
+
+        return 1;
+}
+#else
+static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        return 1;
+}
+#endif
+
 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 {
         if (!dt_memory_scan)
@@ -234,6 +268,7 @@ void __init early_init_devtree(void *params)
                 dt_memory_scan = true;
 
         early_init_dt_scan(params);
+        of_scan_flat_dt(xtensa_dt_io_area, NULL);
 
         if (!command_line[0])
                 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
@@ -241,7 +276,7 @@ void __init early_init_devtree(void *params)
 
 static int __init xtensa_device_probe(void)
 {
-        of_platform_populate(NULL, NULL, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         return 0;
 }
 
@@ -354,7 +389,8 @@ static inline int probed_compare_swap(int *v, int cmp, int set)
 
 /* Handle probed exception */
 
-void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
+static void __init do_probed_exception(struct pt_regs *regs,
+                unsigned long exccause)
 {
         if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
                 regs->pc += 3;          /* skip the s32c1i instruction */
@@ -366,7 +402,7 @@ void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
 
 /* Simple test of S32C1I (soc bringup assist) */
 
-void __init check_s32c1i(void)
+static int __init check_s32c1i(void)
 {
         int n, cause1, cause2;
         void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
@@ -421,24 +457,21 @@ void __init check_s32c1i(void)
         trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
         trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
         trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
+        return 0;
 }
 
 #else /* XCHAL_HAVE_S32C1I */
 
 /* This condition should not occur with a commercially deployed processor.
    Display reminder for early engr test or demo chips / FPGA bitstreams */
-void __init check_s32c1i(void)
+static int __init check_s32c1i(void)
 {
         pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
+        return 0;
 }
 
 #endif /* XCHAL_HAVE_S32C1I */
-#else /* CONFIG_S32C1I_SELFTEST */
-
-void __init check_s32c1i(void)
-{
-}
-
+early_initcall(check_s32c1i);
 #endif /* CONFIG_S32C1I_SELFTEST */
 
 
@@ -447,8 +480,6 @@ void __init setup_arch(char **cmdline_p)
         strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
         *cmdline_p = command_line;
 
-        check_s32c1i();
-
         /* Reserve some memory regions */
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -505,6 +536,10 @@ void __init setup_arch(char **cmdline_p)
 
         platform_setup(cmdline_p);
 
+#ifdef CONFIG_SMP
+        smp_init_cpus();
+#endif
+
         paging_init();
         zones_init();
 
@@ -521,6 +556,22 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+static DEFINE_PER_CPU(struct cpu, cpu_data);
+
+static int __init topology_init(void)
+{
+        int i;
+
+        for_each_possible_cpu(i) {
+                struct cpu *cpu = &per_cpu(cpu_data, i);
+                cpu->hotpluggable = !!i;
+                register_cpu(cpu, i);
+        }
+
+        return 0;
+}
+subsys_initcall(topology_init);
+
 void machine_restart(char * cmd)
 {
         platform_restart();
@@ -546,21 +597,27 @@ void machine_power_off(void)
 static int
 c_show(struct seq_file *f, void *slot)
 {
+        char buf[NR_CPUS * 5];
+
+        cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
         /* high-level stuff */
-        seq_printf(f,"processor\t: 0\n"
-                     "vendor_id\t: Tensilica\n"
-                     "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
-                     "core ID\t\t: " XCHAL_CORE_ID "\n"
-                     "build ID\t: 0x%x\n"
-                     "byte order\t: %s\n"
-                     "cpu MHz\t\t: %lu.%02lu\n"
-                     "bogomips\t: %lu.%02lu\n",
-                     XCHAL_BUILD_UNIQUE_ID,
-                     XCHAL_HAVE_BE ?  "big" : "little",
-                     ccount_freq/1000000,
-                     (ccount_freq/10000) % 100,
-                     loops_per_jiffy/(500000/HZ),
-                     (loops_per_jiffy/(5000/HZ)) % 100);
+        seq_printf(f, "CPU count\t: %u\n"
+                      "CPU list\t: %s\n"
+                      "vendor_id\t: Tensilica\n"
+                      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
+                      "core ID\t\t: " XCHAL_CORE_ID "\n"
+                      "build ID\t: 0x%x\n"
+                      "byte order\t: %s\n"
+                      "cpu MHz\t\t: %lu.%02lu\n"
+                      "bogomips\t: %lu.%02lu\n",
+                      num_online_cpus(),
+                      buf,
+                      XCHAL_BUILD_UNIQUE_ID,
+                      XCHAL_HAVE_BE ?  "big" : "little",
+                      ccount_freq/1000000,
+                      (ccount_freq/10000) % 100,
+                      loops_per_jiffy/(500000/HZ),
+                      (loops_per_jiffy/(5000/HZ)) % 100);
 
         seq_printf(f,"flags\t\t: "
 #if XCHAL_HAVE_NMI
@@ -672,7 +729,7 @@ c_show(struct seq_file *f, void *slot)
 static void *
 c_start(struct seq_file *f, loff_t *pos)
 {
-        return (void *) ((*pos == 0) ? (void *)1 : NULL);
+        return (*pos == 0) ? (void *)1 : NULL;
 }
 
 static void *
@@ -688,10 +745,10 @@ c_stop(struct seq_file *f, void *v)
 
 const struct seq_operations cpuinfo_op =
 {
-        start:  c_start,
-        next:   c_next,
-        stop:   c_stop,
-        show:   c_show
+        .start  = c_start,
+        .next   = c_next,
+        .stop   = c_stop,
+        .show   = c_show,
 };
 
 #endif /* CONFIG_PROC_FS */
diff --git a/arch/xtensa/kernel/smp.c b/arch/xtensa/kernel/smp.c
new file mode 100644
index 000000000000..aa8bd8717927
--- /dev/null
+++ b/arch/xtensa/kernel/smp.c
@@ -0,0 +1,592 @@
+/*
+ * Xtensa SMP support functions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 - 2013 Tensilica Inc.
+ *
+ * Chris Zankel <chris@zankel.net>
+ * Joe Taylor <joe@tensilica.com>
+ * Pete Delaney <piet@tensilica.com
+ */
+
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/kdebug.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/seq_file.h>
+#include <linux/smp.h>
+#include <linux/thread_info.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/mmu_context.h>
+#include <asm/mxregs.h>
+#include <asm/platform.h>
+#include <asm/tlbflush.h>
+#include <asm/traps.h>
+
+#ifdef CONFIG_SMP
+# if XCHAL_HAVE_S32C1I == 0
+#  error "The S32C1I option is required for SMP."
+# endif
+#endif
+
+static void system_invalidate_dcache_range(unsigned long start,
+                unsigned long size);
+static void system_flush_invalidate_dcache_range(unsigned long start,
+                unsigned long size);
+
+/* IPI (Inter Process Interrupt) */
+
+#define IPI_IRQ 0
+
+static irqreturn_t ipi_interrupt(int irq, void *dev_id);
+static struct irqaction ipi_irqaction = {
+        .handler =      ipi_interrupt,
+        .flags =        IRQF_PERCPU,
+        .name =         "ipi",
+};
+
+void ipi_init(void)
+{
+        unsigned irq = irq_create_mapping(NULL, IPI_IRQ);
+        setup_irq(irq, &ipi_irqaction);
+}
+
+static inline unsigned int get_core_count(void)
+{
+        /* Bits 18..21 of SYSCFGID contain the core count minus 1. */
+        unsigned int syscfgid = get_er(SYSCFGID);
+        return ((syscfgid >> 18) & 0xf) + 1;
+}
+
+static inline int get_core_id(void)
+{
+        /* Bits 0...18 of SYSCFGID contain the core id  */
+        unsigned int core_id = get_er(SYSCFGID);
+        return core_id & 0x3fff;
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        unsigned i;
+
+        for (i = 0; i < max_cpus; ++i)
+                set_cpu_present(i, true);
+}
+
+void __init smp_init_cpus(void)
+{
+        unsigned i;
+        unsigned int ncpus = get_core_count();
+        unsigned int core_id = get_core_id();
+
+        pr_info("%s: Core Count = %d\n", __func__, ncpus);
+        pr_info("%s: Core Id = %d\n", __func__, core_id);
+
+        for (i = 0; i < ncpus; ++i)
+                set_cpu_possible(i, true);
+}
+
+void __init smp_prepare_boot_cpu(void)
+{
+        unsigned int cpu = smp_processor_id();
+        BUG_ON(cpu != 0);
+        cpu_asid_cache(cpu) = ASID_USER_FIRST;
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+}
+
+static int boot_secondary_processors = 1; /* Set with xt-gdb via .xt-gdb */
+static DECLARE_COMPLETION(cpu_running);
+
+void secondary_start_kernel(void)
+{
+        struct mm_struct *mm = &init_mm;
+        unsigned int cpu = smp_processor_id();
+
+        init_mmu();
+
+#ifdef CONFIG_DEBUG_KERNEL
+        if (boot_secondary_processors == 0) {
+                pr_debug("%s: boot_secondary_processors:%d; Hanging cpu:%d\n",
+                        __func__, boot_secondary_processors, cpu);
+                for (;;)
+                        __asm__ __volatile__ ("waiti " __stringify(LOCKLEVEL));
+        }
+
+        pr_debug("%s: boot_secondary_processors:%d; Booting cpu:%d\n",
+                __func__, boot_secondary_processors, cpu);
+#endif
+        /* Init EXCSAVE1 */
+
+        secondary_trap_init();
+
+        /* All kernel threads share the same mm context. */
+
+        atomic_inc(&mm->mm_users);
+        atomic_inc(&mm->mm_count);
+        current->active_mm = mm;
+        cpumask_set_cpu(cpu, mm_cpumask(mm));
+        enter_lazy_tlb(mm, current);
+
+        preempt_disable();
+        trace_hardirqs_off();
+
+        calibrate_delay();
+
+        notify_cpu_starting(cpu);
+
+        secondary_init_irq();
+        local_timer_setup(cpu);
+
+        set_cpu_online(cpu, true);
+
+        local_irq_enable();
+
+        complete(&cpu_running);
+
+        cpu_startup_entry(CPUHP_ONLINE);
+}
+
+static void mx_cpu_start(void *p)
+{
+        unsigned cpu = (unsigned)p;
+        unsigned long run_stall_mask = get_er(MPSCORE);
+
+        set_er(run_stall_mask & ~(1u << cpu), MPSCORE);
+        pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n",
+                        __func__, cpu, run_stall_mask, get_er(MPSCORE));
+}
+
+static void mx_cpu_stop(void *p)
+{
+        unsigned cpu = (unsigned)p;
+        unsigned long run_stall_mask = get_er(MPSCORE);
+
+        set_er(run_stall_mask | (1u << cpu), MPSCORE);
+        pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n",
+                        __func__, cpu, run_stall_mask, get_er(MPSCORE));
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+unsigned long cpu_start_id __cacheline_aligned;
+#endif
+unsigned long cpu_start_ccount;
+
+static int boot_secondary(unsigned int cpu, struct task_struct *ts)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+        unsigned long ccount;
+        int i;
+
+#ifdef CONFIG_HOTPLUG_CPU
+        cpu_start_id = cpu;
+        system_flush_invalidate_dcache_range(
+                        (unsigned long)&cpu_start_id, sizeof(cpu_start_id));
+#endif
+        smp_call_function_single(0, mx_cpu_start, (void *)cpu, 1);
+
+        for (i = 0; i < 2; ++i) {
+                do
+                        ccount = get_ccount();
+                while (!ccount);
+
+                cpu_start_ccount = ccount;
+
+                while (time_before(jiffies, timeout)) {
+                        mb();
+                        if (!cpu_start_ccount)
+                                break;
+                }
+
+                if (cpu_start_ccount) {
+                        smp_call_function_single(0, mx_cpu_stop,
+                                        (void *)cpu, 1);
+                        cpu_start_ccount = 0;
+                        return -EIO;
+                }
+        }
+        return 0;
+}
+
+int __cpu_up(unsigned int cpu, struct task_struct *idle)
+{
+        int ret = 0;
+
+        if (cpu_asid_cache(cpu) == 0)
+                cpu_asid_cache(cpu) = ASID_USER_FIRST;
+
+        start_info.stack = (unsigned long)task_pt_regs(idle);
+        wmb();
+
+        pr_debug("%s: Calling wakeup_secondary(cpu:%d, idle:%p, sp: %08lx)\n",
+                        __func__, cpu, idle, start_info.stack);
+
+        ret = boot_secondary(cpu, idle);
+        if (ret == 0) {
+                wait_for_completion_timeout(&cpu_running,
+                                msecs_to_jiffies(1000));
+                if (!cpu_online(cpu))
+                        ret = -EIO;
+        }
+
+        if (ret)
+                pr_err("CPU %u failed to boot\n", cpu);
+
+        return ret;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+/*
+ * __cpu_disable runs on the processor to be shutdown.
+ */
+int __cpu_disable(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        /*
+         * Take this CPU offline.  Once we clear this, we can't return,
+         * and we must not schedule until we're ready to give up the cpu.
+         */
+        set_cpu_online(cpu, false);
+
+        /*
+         * OK - migrate IRQs away from this CPU
+         */
+        migrate_irqs();
+
+        /*
+         * Flush user cache and TLB mappings, and then remove this CPU
+         * from the vm mask set of all processes.
+         */
+        local_flush_cache_all();
+        local_flush_tlb_all();
+        invalidate_page_directory();
+
+        clear_tasks_mm_cpumask(cpu);
+
+        return 0;
+}
+
+static void platform_cpu_kill(unsigned int cpu)
+{
+        smp_call_function_single(0, mx_cpu_stop, (void *)cpu, true);
+}
+
+/*
+ * called on the thread which is asking for a CPU to be shutdown -
+ * waits until shutdown has completed, or it is timed out.
+ */
+void __cpu_die(unsigned int cpu)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+        while (time_before(jiffies, timeout)) {
+                system_invalidate_dcache_range((unsigned long)&cpu_start_id,
+                                sizeof(cpu_start_id));
+                if (cpu_start_id == -cpu) {
+                        platform_cpu_kill(cpu);
+                        return;
+                }
+        }
+        pr_err("CPU%u: unable to kill\n", cpu);
+}
+
+void arch_cpu_idle_dead(void)
+{
+        cpu_die();
+}
+/*
+ * Called from the idle thread for the CPU which has been shutdown.
+ *
+ * Note that we disable IRQs here, but do not re-enable them
+ * before returning to the caller. This is also the behaviour
+ * of the other hotplug-cpu capable cores, so presumably coming
+ * out of idle fixes this.
+ */
+void __ref cpu_die(void)
+{
+        idle_task_exit();
+        local_irq_disable();
+        __asm__ __volatile__(
+                        "       movi    a2, cpu_restart\n"
+                        "       jx      a2\n");
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+enum ipi_msg_type {
+        IPI_RESCHEDULE = 0,
+        IPI_CALL_FUNC,
+        IPI_CPU_STOP,
+        IPI_MAX
+};
+
+static const struct {
+        const char *short_text;
+        const char *long_text;
+} ipi_text[] = {
+        { .short_text = "RES", .long_text = "Rescheduling interrupts" },
+        { .short_text = "CAL", .long_text = "Function call interrupts" },
+        { .short_text = "DIE", .long_text = "CPU shutdown interrupts" },
+};
+
+struct ipi_data {
+        unsigned long ipi_count[IPI_MAX];
+};
+
+static DEFINE_PER_CPU(struct ipi_data, ipi_data);
+
+static void send_ipi_message(const struct cpumask *callmask,
+                enum ipi_msg_type msg_id)
+{
+        int index;
+        unsigned long mask = 0;
+
+        for_each_cpu(index, callmask)
+                if (index != smp_processor_id())
+                        mask |= 1 << index;
+
+        set_er(mask, MIPISET(msg_id));
+}
+
+void arch_send_call_function_ipi_mask(const struct cpumask *mask)
+{
+        send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+        send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+void smp_send_reschedule(int cpu)
+{
+        send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void smp_send_stop(void)
+{
+        struct cpumask targets;
+
+        cpumask_copy(&targets, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &targets);
+        send_ipi_message(&targets, IPI_CPU_STOP);
+}
+
+static void ipi_cpu_stop(unsigned int cpu)
+{
+        set_cpu_online(cpu, false);
+        machine_halt();
+}
+
+irqreturn_t ipi_interrupt(int irq, void *dev_id)
+{
+        unsigned int cpu = smp_processor_id();
+        struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
+        unsigned int msg;
+        unsigned i;
+
+        msg = get_er(MIPICAUSE(cpu));
+        for (i = 0; i < IPI_MAX; i++)
+                if (msg & (1 << i)) {
+                        set_er(1 << i, MIPICAUSE(cpu));
+                        ++ipi->ipi_count[i];
+                }
+
+        if (msg & (1 << IPI_RESCHEDULE))
+                scheduler_ipi();
+        if (msg & (1 << IPI_CALL_FUNC))
+                generic_smp_call_function_interrupt();
+        if (msg & (1 << IPI_CPU_STOP))
+                ipi_cpu_stop(cpu);
+
+        return IRQ_HANDLED;
+}
+
+void show_ipi_list(struct seq_file *p, int prec)
+{
+        unsigned int cpu;
+        unsigned i;
+
+        for (i = 0; i < IPI_MAX; ++i) {
+                seq_printf(p, "%*s:", prec, ipi_text[i].short_text);
+                for_each_online_cpu(cpu)
+                        seq_printf(p, " %10lu",
+                                        per_cpu(ipi_data, cpu).ipi_count[i]);
+                seq_printf(p, "   %s\n", ipi_text[i].long_text);
+        }
+}
+
+int setup_profiling_timer(unsigned int multiplier)
+{
+        pr_debug("setup_profiling_timer %d\n", multiplier);
+        return 0;
+}
+
+/* TLB flush functions */
+
+struct flush_data {
+        struct vm_area_struct *vma;
+        unsigned long addr1;
+        unsigned long addr2;
+};
+
+static void ipi_flush_tlb_all(void *arg)
+{
+        local_flush_tlb_all();
+}
+
+void flush_tlb_all(void)
+{
+        on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+static void ipi_flush_tlb_mm(void *arg)
+{
+        local_flush_tlb_mm(arg);
+}
+
+void flush_tlb_mm(struct mm_struct *mm)
+{
+        on_each_cpu(ipi_flush_tlb_mm, mm, 1);
+}
+
+static void ipi_flush_tlb_page(void *arg)
+{
+        struct flush_data *fd = arg;
+        local_flush_tlb_page(fd->vma, fd->addr1);
+}
+
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+        struct flush_data fd = {
+                .vma = vma,
+                .addr1 = addr,
+        };
+        on_each_cpu(ipi_flush_tlb_page, &fd, 1);
+}
+
+static void ipi_flush_tlb_range(void *arg)
+{
+        struct flush_data *fd = arg;
+        local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
+}
+
+void flush_tlb_range(struct vm_area_struct *vma,
+                     unsigned long start, unsigned long end)
+{
+        struct flush_data fd = {
+                .vma = vma,
+                .addr1 = start,
+                .addr2 = end,
+        };
+        on_each_cpu(ipi_flush_tlb_range, &fd, 1);
+}
+
+/* Cache flush functions */
+
+static void ipi_flush_cache_all(void *arg)
+{
+        local_flush_cache_all();
+}
+
+void flush_cache_all(void)
+{
+        on_each_cpu(ipi_flush_cache_all, NULL, 1);
+}
+
+static void ipi_flush_cache_page(void *arg)
+{
+        struct flush_data *fd = arg;
+        local_flush_cache_page(fd->vma, fd->addr1, fd->addr2);
+}
+
+void flush_cache_page(struct vm_area_struct *vma,
+                     unsigned long address, unsigned long pfn)
+{
+        struct flush_data fd = {
+                .vma = vma,
+                .addr1 = address,
+                .addr2 = pfn,
+        };
+        on_each_cpu(ipi_flush_cache_page, &fd, 1);
+}
+
+static void ipi_flush_cache_range(void *arg)
+{
+        struct flush_data *fd = arg;
+        local_flush_cache_range(fd->vma, fd->addr1, fd->addr2);
+}
+
+void flush_cache_range(struct vm_area_struct *vma,
+                     unsigned long start, unsigned long end)
+{
+        struct flush_data fd = {
+                .vma = vma,
+                .addr1 = start,
+                .addr2 = end,
+        };
+        on_each_cpu(ipi_flush_cache_range, &fd, 1);
+}
+
+static void ipi_flush_icache_range(void *arg)
+{
+        struct flush_data *fd = arg;
+        local_flush_icache_range(fd->addr1, fd->addr2);
+}
+
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+        struct flush_data fd = {
+                .addr1 = start,
+                .addr2 = end,
+        };
+        on_each_cpu(ipi_flush_icache_range, &fd, 1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void ipi_invalidate_dcache_range(void *arg)
+{
+        struct flush_data *fd = arg;
+        __invalidate_dcache_range(fd->addr1, fd->addr2);
+}
+
+static void system_invalidate_dcache_range(unsigned long start,
+                unsigned long size)
+{
+        struct flush_data fd = {
+                .addr1 = start,
+                .addr2 = size,
+        };
+        on_each_cpu(ipi_invalidate_dcache_range, &fd, 1);
+}
+
+static void ipi_flush_invalidate_dcache_range(void *arg)
+{
+        struct flush_data *fd = arg;
+        __flush_invalidate_dcache_range(fd->addr1, fd->addr2);
+}
+
+static void system_flush_invalidate_dcache_range(unsigned long start,
+                unsigned long size)
+{
+        struct flush_data fd = {
+                .addr1 = start,
+                .addr2 = size,
+        };
+        on_each_cpu(ipi_flush_invalidate_dcache_range, &fd, 1);
+}
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index 9af3dd88ad7e..08b769d3b3a1 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -36,7 +36,7 @@ static cycle_t ccount_read(struct clocksource *cs)
         return (cycle_t)get_ccount();
 }
 
-static u32 notrace ccount_sched_clock_read(void)
+static u64 notrace ccount_sched_clock_read(void)
 {
         return get_ccount();
 }
@@ -46,24 +46,19 @@ static struct clocksource ccount_clocksource = {
         .rating = 200,
         .read = ccount_read,
         .mask = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
 static int ccount_timer_set_next_event(unsigned long delta,
                 struct clock_event_device *dev);
 static void ccount_timer_set_mode(enum clock_event_mode mode,
                 struct clock_event_device *evt);
-static struct ccount_timer_t {
+struct ccount_timer {
         struct clock_event_device evt;
         int irq_enabled;
-} ccount_timer = {
-        .evt = {
-                .name           = "ccount_clockevent",
-                .features       = CLOCK_EVT_FEAT_ONESHOT,
-                .rating         = 300,
-                .set_next_event = ccount_timer_set_next_event,
-                .set_mode       = ccount_timer_set_mode,
-        },
+        char name[24];
 };
+static DEFINE_PER_CPU(struct ccount_timer, ccount_timer);
 
 static int ccount_timer_set_next_event(unsigned long delta,
                 struct clock_event_device *dev)
@@ -84,8 +79,8 @@ static int ccount_timer_set_next_event(unsigned long delta,
 static void ccount_timer_set_mode(enum clock_event_mode mode,
                 struct clock_event_device *evt)
 {
-        struct ccount_timer_t *timer =
-                container_of(evt, struct ccount_timer_t, evt);
+        struct ccount_timer *timer =
+                container_of(evt, struct ccount_timer, evt);
 
         /*
          * There is no way to disable the timer interrupt at the device level,
@@ -117,9 +112,28 @@ static struct irqaction timer_irqaction = {
         .handler =      timer_interrupt,
         .flags =        IRQF_TIMER,
         .name =         "timer",
-        .dev_id =       &ccount_timer,
 };
 
+void local_timer_setup(unsigned cpu)
+{
+        struct ccount_timer *timer = &per_cpu(ccount_timer, cpu);
+        struct clock_event_device *clockevent = &timer->evt;
+
+        timer->irq_enabled = 1;
+        clockevent->name = timer->name;
+        snprintf(timer->name, sizeof(timer->name), "ccount_clockevent_%u", cpu);
+        clockevent->features = CLOCK_EVT_FEAT_ONESHOT;
+        clockevent->rating = 300;
+        clockevent->set_next_event = ccount_timer_set_next_event;
+        clockevent->set_mode = ccount_timer_set_mode;
+        clockevent->cpumask = cpumask_of(cpu);
+        clockevent->irq = irq_create_mapping(NULL, LINUX_TIMER_INT);
+        if (WARN(!clockevent->irq, "error: can't map timer irq"))
+                return;
+        clockevents_config_and_register(clockevent, ccount_freq,
+                                        0xf, 0xffffffff);
+}
+
 void __init time_init(void)
 {
 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
@@ -131,28 +145,21 @@ void __init time_init(void)
         ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL;
 #endif
         clocksource_register_hz(&ccount_clocksource, ccount_freq);
-
-        ccount_timer.evt.cpumask = cpumask_of(0);
-        ccount_timer.evt.irq = irq_create_mapping(NULL, LINUX_TIMER_INT);
-        if (WARN(!ccount_timer.evt.irq, "error: can't map timer irq"))
-                return;
-        clockevents_config_and_register(&ccount_timer.evt, ccount_freq, 0xf,
-                        0xffffffff);
-        setup_irq(ccount_timer.evt.irq, &timer_irqaction);
-        ccount_timer.irq_enabled = 1;
-
-        setup_sched_clock(ccount_sched_clock_read, 32, ccount_freq);
+        local_timer_setup(0);
+        setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);
+        sched_clock_register(ccount_sched_clock_read, 32, ccount_freq);
+        clocksource_of_init();
 }
 
 /*
  * The timer interrupt is called HZ times per second.
  */
 
-irqreturn_t timer_interrupt (int irq, void *dev_id)
+irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
-        struct ccount_timer_t *timer = dev_id;
-        struct clock_event_device *evt = &timer->evt;
+        struct clock_event_device *evt = &this_cpu_ptr(&ccount_timer)->evt;
 
+        set_linux_timer(get_linux_timer());
         evt->event_handler(evt);
 
         /* Allow platform to do something useful (Wdog). */
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index 3e8a05c874cd..eebbfd8c26fc 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -157,7 +157,7 @@ COPROCESSOR(7),
  * 2. it is a temporary memory buffer for the exception handlers.
  */
 
-unsigned long exc_table[EXC_TABLE_SIZE/4];
+DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]);
 
 void die(const char*, struct pt_regs*, long);
 
@@ -212,6 +212,9 @@ void do_interrupt(struct pt_regs *regs)
                 XCHAL_INTLEVEL6_MASK,
                 XCHAL_INTLEVEL7_MASK,
         };
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        irq_enter();
 
         for (;;) {
                 unsigned intread = get_sr(interrupt);
@@ -227,21 +230,13 @@ void do_interrupt(struct pt_regs *regs)
                 }
 
                 if (level == 0)
-                        return;
-
-                /*
-                 * Clear the interrupt before processing, in case it's
-                 *  edge-triggered or software-generated
-                 */
-                while (int_at_level) {
-                        unsigned i = __ffs(int_at_level);
-                        unsigned mask = 1 << i;
-
-                        int_at_level ^= mask;
-                        set_sr(mask, intclear);
-                        do_IRQ(i, regs);
-                }
+                        break;
+
+                do_IRQ(__ffs(int_at_level), regs);
         }
+
+        irq_exit();
+        set_irq_regs(old_regs);
 }
 
 /*
@@ -318,17 +313,31 @@ do_debug(struct pt_regs *regs)
 }
 
 
+static void set_handler(int idx, void *handler)
+{
+        unsigned int cpu;
+
+        for_each_possible_cpu(cpu)
+                per_cpu(exc_table, cpu)[idx] = (unsigned long)handler;
+}
+
 /* Set exception C handler - for temporary use when probing exceptions */
 
 void * __init trap_set_handler(int cause, void *handler)
 {
-        unsigned long *entry = &exc_table[EXC_TABLE_DEFAULT / 4 + cause];
-        void *previous = (void *)*entry;
-        *entry = (unsigned long)handler;
+        void *previous = (void *)per_cpu(exc_table, 0)[
+                EXC_TABLE_DEFAULT / 4 + cause];
+        set_handler(EXC_TABLE_DEFAULT / 4 + cause, handler);
         return previous;
 }
 
 
+static void trap_init_excsave(void)
+{
+        unsigned long excsave1 = (unsigned long)this_cpu_ptr(exc_table);
+        __asm__ __volatile__("wsr  %0, excsave1\n" : : "a" (excsave1));
+}
+
 /*
  * Initialize dispatch tables.
  *
@@ -342,8 +351,6 @@ void * __init trap_set_handler(int cause, void *handler)
  * See vectors.S for more details.
  */
 
-#define set_handler(idx,handler) (exc_table[idx] = (unsigned long) (handler))
-
 void __init trap_init(void)
 {
         int i;
@@ -373,10 +380,15 @@ void __init trap_init(void)
         }
 
         /* Initialize EXCSAVE_1 to hold the address of the exception table. */
+        trap_init_excsave();
+}
 
-        i = (unsigned long)exc_table;
-        __asm__ __volatile__("wsr  %0, excsave1\n" : : "a" (i));
+#ifdef CONFIG_SMP
+void secondary_trap_init(void)
+{
+        trap_init_excsave();
 }
+#endif
 
 /*
  * This function dumps the current valid window frame and other base registers.
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index 21acd11b5df2..ee32c0085dff 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -165,6 +165,13 @@ SECTIONS
                    .DoubleExceptionVector.text);
     RELOCATE_ENTRY(_DebugInterruptVector_text,
                    .DebugInterruptVector.text);
+#if defined(CONFIG_SMP)
+    RELOCATE_ENTRY(_SecondaryResetVector_literal,
+                   .SecondaryResetVector.literal);
+    RELOCATE_ENTRY(_SecondaryResetVector_text,
+                   .SecondaryResetVector.text);
+#endif
+
   
     __boot_reloc_table_end = ABSOLUTE(.) ;
 
@@ -272,6 +279,25 @@ SECTIONS
                   .DoubleExceptionVector.literal)
 
   . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;
+
+#if defined(CONFIG_SMP)
+
+  SECTION_VECTOR (_SecondaryResetVector_literal,
+                  .SecondaryResetVector.literal,
+                  RESET_VECTOR1_VADDR - 4,
+                  SIZEOF(.DoubleExceptionVector.text),
+                  .DoubleExceptionVector.text)
+
+  SECTION_VECTOR (_SecondaryResetVector_text,
+                  .SecondaryResetVector.text,
+                  RESET_VECTOR1_VADDR,
+                  4,
+                  .SecondaryResetVector.literal)
+
+  . = LOADADDR(.SecondaryResetVector.text)+SIZEOF(.SecondaryResetVector.text);
+
+#endif
+
   . = ALIGN(PAGE_SIZE);
 
   __init_end = .;
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 81edeab82d17..ba4c47f291b1 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -118,7 +118,7 @@ void flush_dcache_page(struct page *page)
  * For now, flush the whole cache. FIXME??
  */
 
-void flush_cache_range(struct vm_area_struct* vma,
+void local_flush_cache_range(struct vm_area_struct *vma,
                        unsigned long start, unsigned long end)
 {
         __flush_invalidate_dcache_all();
@@ -132,7 +132,7 @@ void flush_cache_range(struct vm_area_struct* vma,
  * alias versions of the cache flush functions.
  */
 
-void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
+void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
                       unsigned long pfn)
 {
         /* Note that we have to use the 'alias' address to avoid multi-hit */
@@ -159,8 +159,7 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 
         /* Invalidate old entry in TLBs */
 
-        invalidate_itlb_mapping(addr);
-        invalidate_dtlb_mapping(addr);
+        flush_tlb_page(vma, addr);
 
 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index 70fa7bc42b4a..b57c4f91f487 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -21,7 +21,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgalloc.h>
 
-unsigned long asid_cache = ASID_USER_FIRST;
+DEFINE_PER_CPU(unsigned long, asid_cache) = ASID_USER_FIRST;
 void bad_page_fault(struct pt_regs*, unsigned long, int);
 
 #undef DEBUG_PAGE_FAULT
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index d97ed1ba7b0a..1f68558dbcc2 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -140,7 +140,7 @@ ENTRY(clear_user_page)
 
         /* Setup a temporary DTLB with the color of the VPN */
 
-        movi    a4, -PAGE_OFFSET + (PAGE_KERNEL | _PAGE_HW_WRITE)
+        movi    a4, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
         movi    a5, TLBTEMP_BASE_1                      # virt
         add     a6, a2, a4                              # ppn
         add     a2, a5, a3                              # add 'color'
@@ -194,7 +194,7 @@ ENTRY(copy_user_page)
         or      a9, a9, a8
         slli    a4, a4, PAGE_SHIFT
         s32i    a9, a5, PAGE_FLAGS
-        movi    a5, -PAGE_OFFSET + (PAGE_KERNEL | _PAGE_HW_WRITE)
+        movi    a5, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
 
         beqz    a6, 1f
 
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index c43771c974be..36ec171698b8 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -13,6 +13,8 @@
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
 #include <asm/page.h>
+#include <asm/initialize_mmu.h>
+#include <asm/io.h>
 
 void __init paging_init(void)
 {
@@ -22,7 +24,7 @@ void __init paging_init(void)
 /*
  * Flush the mmu and reset associated register to default values.
  */
-void __init init_mmu(void)
+void init_mmu(void)
 {
 #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
         /*
@@ -37,7 +39,21 @@ void __init init_mmu(void)
         set_itlbcfg_register(0);
         set_dtlbcfg_register(0);
 #endif
-        flush_tlb_all();
+#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
+        /*
+         * Update the IO area mapping in case xtensa_kio_paddr has changed
+         */
+        write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
+                        XCHAL_KIO_CACHED_VADDR + 6);
+        write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
+                        XCHAL_KIO_CACHED_VADDR + 6);
+        write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
+                        XCHAL_KIO_BYPASS_VADDR + 6);
+        write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
+                        XCHAL_KIO_BYPASS_VADDR + 6);
+#endif
+
+        local_flush_tlb_all();
 
         /* Set rasid register to a known value. */
 
diff --git a/arch/xtensa/mm/tlb.c b/arch/xtensa/mm/tlb.c
index ca9d2366bf12..ade623826788 100644
--- a/arch/xtensa/mm/tlb.c
+++ b/arch/xtensa/mm/tlb.c
@@ -48,7 +48,7 @@ static inline void __flush_dtlb_all (void)
 }
 
 
-void flush_tlb_all (void)
+void local_flush_tlb_all(void)
 {
         __flush_itlb_all();
         __flush_dtlb_all();
@@ -60,19 +60,23 @@ void flush_tlb_all (void)
  * a new context will be assigned to it.
  */
 
-void flush_tlb_mm(struct mm_struct *mm)
+void local_flush_tlb_mm(struct mm_struct *mm)
 {
+        int cpu = smp_processor_id();
+
         if (mm == current->active_mm) {
                 unsigned long flags;
                 local_irq_save(flags);
-                __get_new_mmu_context(mm);
-                __load_mmu_context(mm);
+                mm->context.asid[cpu] = NO_CONTEXT;
+                activate_context(mm, cpu);
                 local_irq_restore(flags);
+        } else {
+                mm->context.asid[cpu] = NO_CONTEXT;
+                mm->context.cpu = -1;
         }
-        else
-                mm->context = 0;
 }
 
+
 #define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2)
 #define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2)
 #if _ITLB_ENTRIES > _DTLB_ENTRIES
@@ -81,24 +85,26 @@ void flush_tlb_mm(struct mm_struct *mm)
 # define _TLB_ENTRIES _DTLB_ENTRIES
 #endif
 
-void flush_tlb_range (struct vm_area_struct *vma,
-                      unsigned long start, unsigned long end)
+void local_flush_tlb_range(struct vm_area_struct *vma,
+                unsigned long start, unsigned long end)
 {
+        int cpu = smp_processor_id();
         struct mm_struct *mm = vma->vm_mm;
         unsigned long flags;
 
-        if (mm->context == NO_CONTEXT)
+        if (mm->context.asid[cpu] == NO_CONTEXT)
                 return;
 
 #if 0
         printk("[tlbrange<%02lx,%08lx,%08lx>]\n",
-                        (unsigned long)mm->context, start, end);
+                        (unsigned long)mm->context.asid[cpu], start, end);
 #endif
         local_irq_save(flags);
 
         if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) {
                 int oldpid = get_rasid_register();
-                set_rasid_register (ASID_INSERT(mm->context));
+
+                set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
                 start &= PAGE_MASK;
                 if (vma->vm_flags & VM_EXEC)
                         while(start < end) {
@@ -114,24 +120,25 @@ void flush_tlb_range (struct vm_area_struct *vma,
 
                 set_rasid_register(oldpid);
         } else {
-                flush_tlb_mm(mm);
+                local_flush_tlb_mm(mm);
         }
         local_irq_restore(flags);
 }
 
-void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
+        int cpu = smp_processor_id();
         struct mm_struct* mm = vma->vm_mm;
         unsigned long flags;
         int oldpid;
 
-        if(mm->context == NO_CONTEXT)
+        if (mm->context.asid[cpu] == NO_CONTEXT)
                 return;
 
         local_irq_save(flags);
 
         oldpid = get_rasid_register();
-        set_rasid_register(ASID_INSERT(mm->context));
+        set_rasid_register(ASID_INSERT(mm->context.asid[cpu]));
 
         if (vma->vm_flags & VM_EXEC)
                 invalidate_itlb_mapping(page);
diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c
index e9e1aad8c271..d05f8feeb8d7 100644
--- a/arch/xtensa/platforms/iss/network.c
+++ b/arch/xtensa/platforms/iss/network.c
@@ -38,7 +38,7 @@
 #define DRIVER_NAME "iss-netdev"
 #define ETH_MAX_PACKET 1500
 #define ETH_HEADER_OTHER 14
-#define ISS_NET_TIMER_VALUE (2 * HZ)
+#define ISS_NET_TIMER_VALUE (HZ / 10)
 
 
 static DEFINE_SPINLOCK(opened_lock);
@@ -56,8 +56,6 @@ static LIST_HEAD(devices);
 
 struct tuntap_info {
         char dev_name[IFNAMSIZ];
-        int fixed_config;
-        unsigned char gw[ETH_ALEN];
         int fd;
 };
 
@@ -67,7 +65,6 @@ struct tuntap_info {
 /* This structure contains out private information for the driver. */
 
 struct iss_net_private {
-
         struct list_head device_list;
         struct list_head opened_list;
 
@@ -83,9 +80,6 @@ struct iss_net_private {
         int index;
         int mtu;
 
-        unsigned char mac[ETH_ALEN];
-        int have_mac;
-
         struct {
                 union {
                         struct tuntap_info tuntap;
@@ -118,68 +112,48 @@ static char *split_if_spec(char *str, ...)
                         *arg = str;
                 if (end == NULL)
                         return NULL;
-                *end ++ = '\0';
+                *end++ = '\0';
                 str = end;
         }
         va_end(ap);
         return str;
 }
 
+/* Set Ethernet address of the specified device. */
 
-#if 0
-/* Adjust SKB. */
-
-struct sk_buff *ether_adjust_skb(struct sk_buff *skb, int extra)
+static void setup_etheraddr(struct net_device *dev, char *str)
 {
-        if ((skb != NULL) && (skb_tailroom(skb) < extra)) {
-                struct sk_buff *skb2;
-
-                skb2 = skb_copy_expand(skb, 0, extra, GFP_ATOMIC);
-                dev_kfree_skb(skb);
-                skb = skb2;
-        }
-        if (skb != NULL)
-                skb_put(skb, extra);
-
-        return skb;
-}
-#endif
+        unsigned char *addr = dev->dev_addr;
 
-/* Return the IP address as a string for a given device. */
+        if (str == NULL)
+                goto random;
 
-static void dev_ip_addr(void *d, char *buf, char *bin_buf)
-{
-        struct net_device *dev = d;
-        struct in_device *ip = dev->ip_ptr;
-        struct in_ifaddr *in;
-        __be32 addr;
-
-        if ((ip == NULL) || ((in = ip->ifa_list) == NULL)) {
-                printk(KERN_WARNING "Device not assigned an IP address!\n");
-                return;
+        if (!mac_pton(str, addr)) {
+                pr_err("%s: failed to parse '%s' as an ethernet address\n",
+                       dev->name, str);
+                goto random;
         }
-
-        addr = in->ifa_address;
-        sprintf(buf, "%d.%d.%d.%d", addr & 0xff, (addr >> 8) & 0xff,
-                (addr >> 16) & 0xff, addr >> 24);
-
-        if (bin_buf) {
-                bin_buf[0] = addr & 0xff;
-                bin_buf[1] = (addr >> 8) & 0xff;
-                bin_buf[2] = (addr >> 16) & 0xff;
-                bin_buf[3] = addr >> 24;
+        if (is_multicast_ether_addr(addr)) {
+                pr_err("%s: attempt to assign a multicast ethernet address\n",
+                       dev->name);
+                goto random;
         }
+        if (!is_valid_ether_addr(addr)) {
+                pr_err("%s: attempt to assign an invalid ethernet address\n",
+                       dev->name);
+                goto random;
+        }
+        if (!is_local_ether_addr(addr))
+                pr_warn("%s: assigning a globally valid ethernet address\n",
+                        dev->name);
+        return;
+
+random:
+        pr_info("%s: choosing a random ethernet address\n",
+                dev->name);
+        eth_hw_addr_random(dev);
 }
 
-/* Set Ethernet address of the specified device. */
-
-static void inline set_ether_mac(void *d, unsigned char *addr)
-{
-        struct net_device *dev = d;
-        memcpy(dev->dev_addr, addr, ETH_ALEN);
-}
-
-
 /* ======================= TUNTAP TRANSPORT INTERFACE ====================== */
 
 static int tuntap_open(struct iss_net_private *lp)
@@ -189,24 +163,21 @@ static int tuntap_open(struct iss_net_private *lp)
         int err = -EINVAL;
         int fd;
 
-        /* We currently only support a fixed configuration. */
-
-        if (!lp->tp.info.tuntap.fixed_config)
-                return -EINVAL;
-
-        if ((fd = simc_open("/dev/net/tun", 02, 0)) < 0) {      /* O_RDWR */
-                printk("Failed to open /dev/net/tun, returned %d "
-                       "(errno = %d)\n", fd, errno);
+        fd = simc_open("/dev/net/tun", 02, 0); /* O_RDWR */
+        if (fd < 0) {
+                pr_err("%s: failed to open /dev/net/tun, returned %d (errno = %d)\n",
+                       lp->dev->name, fd, errno);
                 return fd;
         }
 
-        memset(&ifr, 0, sizeof ifr);
+        memset(&ifr, 0, sizeof(ifr));
         ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
-        strlcpy(ifr.ifr_name, dev_name, sizeof ifr.ifr_name);
+        strlcpy(ifr.ifr_name, dev_name, sizeof(ifr.ifr_name));
 
-        if ((err = simc_ioctl(fd, TUNSETIFF, (void*) &ifr)) < 0) {
-                printk("Failed to set interface, returned %d "
-                       "(errno = %d)\n", err, errno);
+        err = simc_ioctl(fd, TUNSETIFF, &ifr);
+        if (err < 0) {
+                pr_err("%s: failed to set interface %s, returned %d (errno = %d)\n",
+                       lp->dev->name, dev_name, err, errno);
                 simc_close(fd);
                 return err;
         }
@@ -217,27 +188,17 @@ static int tuntap_open(struct iss_net_private *lp)
 
 static void tuntap_close(struct iss_net_private *lp)
 {
-#if 0
-        if (lp->tp.info.tuntap.fixed_config)
-                iter_addresses(lp->tp.info.tuntap.dev, close_addr, lp->host.dev_name);
-#endif
         simc_close(lp->tp.info.tuntap.fd);
         lp->tp.info.tuntap.fd = -1;
 }
 
-static int tuntap_read (struct iss_net_private *lp, struct sk_buff **skb)
+static int tuntap_read(struct iss_net_private *lp, struct sk_buff **skb)
 {
-#if 0
-        *skb = ether_adjust_skb(*skb, ETH_HEADER_OTHER);
-        if (*skb == NULL)
-                return -ENOMEM;
-#endif
-
         return simc_read(lp->tp.info.tuntap.fd,
                         (*skb)->data, (*skb)->dev->mtu + ETH_HEADER_OTHER);
 }
 
-static int tuntap_write (struct iss_net_private *lp, struct sk_buff **skb)
+static int tuntap_write(struct iss_net_private *lp, struct sk_buff **skb)
 {
         return simc_write(lp->tp.info.tuntap.fd, (*skb)->data, (*skb)->len);
 }
@@ -253,45 +214,45 @@ static int tuntap_poll(struct iss_net_private *lp)
 }
 
 /*
- * Currently only a device name is supported.
- * ethX=tuntap[,[mac address][,[device name]]]
+ * ethX=tuntap,[mac address],device name
  */
 
 static int tuntap_probe(struct iss_net_private *lp, int index, char *init)
 {
-        const int len = strlen(TRANSPORT_TUNTAP_NAME);
+        struct net_device *dev = lp->dev;
         char *dev_name = NULL, *mac_str = NULL, *rem = NULL;
 
         /* Transport should be 'tuntap': ethX=tuntap,mac,dev_name */
 
-        if (strncmp(init, TRANSPORT_TUNTAP_NAME, len))
+        if (strncmp(init, TRANSPORT_TUNTAP_NAME,
+                    sizeof(TRANSPORT_TUNTAP_NAME) - 1))
                 return 0;
 
-        if (*(init += strlen(TRANSPORT_TUNTAP_NAME)) == ',') {
-                if ((rem=split_if_spec(init+1, &mac_str, &dev_name)) != NULL) {
-                        printk("Extra garbage on specification : '%s'\n", rem);
+        init += sizeof(TRANSPORT_TUNTAP_NAME) - 1;
+        if (*init == ',') {
+                rem = split_if_spec(init + 1, &mac_str, &dev_name);
+                if (rem != NULL) {
+                        pr_err("%s: extra garbage on specification : '%s'\n",
+                               dev->name, rem);
                         return 0;
                 }
         } else if (*init != '\0') {
-                printk("Invalid argument: %s. Skipping device!\n", init);
+                pr_err("%s: invalid argument: %s. Skipping device!\n",
+                       dev->name, init);
                 return 0;
         }
 
-        if (dev_name) {
-                strncpy(lp->tp.info.tuntap.dev_name, dev_name,
-                         sizeof lp->tp.info.tuntap.dev_name);
-                lp->tp.info.tuntap.fixed_config = 1;
-        } else
-                strcpy(lp->tp.info.tuntap.dev_name, TRANSPORT_TUNTAP_NAME);
+        if (!dev_name) {
+                pr_err("%s: missing tuntap device name\n", dev->name);
+                return 0;
+        }
 
+        strlcpy(lp->tp.info.tuntap.dev_name, dev_name,
+                sizeof(lp->tp.info.tuntap.dev_name));
 
-#if 0
-        if (setup_etheraddr(mac_str, lp->mac))
-                lp->have_mac = 1;
-#endif
-        lp->mtu = TRANSPORT_TUNTAP_MTU;
+        setup_etheraddr(dev, mac_str);
 
-        //lp->info.tuntap.gate_addr = gate_addr;
+        lp->mtu = TRANSPORT_TUNTAP_MTU;
 
         lp->tp.info.tuntap.fd = -1;
 
@@ -302,13 +263,6 @@ static int tuntap_probe(struct iss_net_private *lp, int index, char *init)
         lp->tp.protocol = tuntap_protocol;
         lp->tp.poll = tuntap_poll;
 
-        printk("TUN/TAP backend - ");
-#if 0
-        if (lp->host.gate_addr != NULL)
-                printk("IP = %s", lp->host.gate_addr);
-#endif
-        printk("\n");
-
         return 1;
 }
 
@@ -327,7 +281,8 @@ static int iss_net_rx(struct net_device *dev)
 
         /* Try to allocate memory, if it fails, try again next round. */
 
-        if ((skb = dev_alloc_skb(dev->mtu + 2 + ETH_HEADER_OTHER)) == NULL) {
+        skb = dev_alloc_skb(dev->mtu + 2 + ETH_HEADER_OTHER);
+        if (skb == NULL) {
                 lp->stats.rx_dropped++;
                 return 0;
         }
@@ -347,7 +302,6 @@ static int iss_net_rx(struct net_device *dev)
 
                 lp->stats.rx_bytes += skb->len;
                 lp->stats.rx_packets++;
-        //      netif_rx(skb);
                 netif_rx_ni(skb);
                 return pkt_len;
         }
@@ -378,11 +332,11 @@ static int iss_net_poll(void)
                 spin_unlock(&lp->lock);
 
                 if (err < 0) {
-                        printk(KERN_ERR "Device '%s' read returned %d, "
-                               "shutting it down\n", lp->dev->name, err);
+                        pr_err("Device '%s' read returned %d, shutting it down\n",
+                               lp->dev->name, err);
                         dev_close(lp->dev);
                 } else {
-                        // FIXME reactivate_fd(lp->fd, ISS_ETH_IRQ);
+                        /* FIXME reactivate_fd(lp->fd, ISS_ETH_IRQ); */
                 }
         }
 
@@ -393,14 +347,11 @@ static int iss_net_poll(void)
 
 static void iss_net_timer(unsigned long priv)
 {
-        struct iss_net_private* lp = (struct iss_net_private*) priv;
+        struct iss_net_private *lp = (struct iss_net_private *)priv;
 
         spin_lock(&lp->lock);
-
         iss_net_poll();
-
         mod_timer(&lp->timer, jiffies + lp->timer_val);
-
         spin_unlock(&lp->lock);
 }
 
@@ -408,19 +359,14 @@ static void iss_net_timer(unsigned long priv)
 static int iss_net_open(struct net_device *dev)
 {
         struct iss_net_private *lp = netdev_priv(dev);
-        char addr[sizeof "255.255.255.255\0"];
         int err;
 
         spin_lock(&lp->lock);
 
-        if ((err = lp->tp.open(lp)) < 0)
+        err = lp->tp.open(lp);
+        if (err < 0)
                 goto out;
 
-        if (!lp->have_mac) {
-                dev_ip_addr(dev, addr, &lp->mac[2]);
-                set_ether_mac(dev, lp->mac);
-        }
-
         netif_start_queue(dev);
 
         /* clear buffer - it can happen that the host side of the interface
@@ -448,7 +394,6 @@ out:
 static int iss_net_close(struct net_device *dev)
 {
         struct iss_net_private *lp = netdev_priv(dev);
-printk("iss_net_close!\n");
         netif_stop_queue(dev);
         spin_lock(&lp->lock);
 
@@ -490,7 +435,7 @@ static int iss_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         } else {
                 netif_start_queue(dev);
-                printk(KERN_ERR "iss_net_start_xmit: failed(%d)\n", len);
+                pr_err("%s: %s failed(%d)\n", dev->name, __func__, len);
         }
 
         spin_unlock_irqrestore(&lp->lock, flags);
@@ -508,56 +453,27 @@ static struct net_device_stats *iss_net_get_stats(struct net_device *dev)
 
 static void iss_net_set_multicast_list(struct net_device *dev)
 {
-#if 0
-        if (dev->flags & IFF_PROMISC)
-                return;
-        else if (!netdev_mc_empty(dev))
-                dev->flags |= IFF_ALLMULTI;
-        else
-                dev->flags &= ~IFF_ALLMULTI;
-#endif
 }
 
 static void iss_net_tx_timeout(struct net_device *dev)
 {
-#if 0
-        dev->trans_start = jiffies;
-        netif_wake_queue(dev);
-#endif
 }
 
 static int iss_net_set_mac(struct net_device *dev, void *addr)
 {
-#if 0
         struct iss_net_private *lp = netdev_priv(dev);
         struct sockaddr *hwaddr = addr;
 
+        if (!is_valid_ether_addr(hwaddr->sa_data))
+                return -EADDRNOTAVAIL;
         spin_lock(&lp->lock);
         memcpy(dev->dev_addr, hwaddr->sa_data, ETH_ALEN);
         spin_unlock(&lp->lock);
-#endif
-
         return 0;
 }
 
 static int iss_net_change_mtu(struct net_device *dev, int new_mtu)
 {
-#if 0
-        struct iss_net_private *lp = netdev_priv(dev);
-        int err = 0;
-
-        spin_lock(&lp->lock);
-
-        // FIXME not needed new_mtu = transport_set_mtu(new_mtu, &lp->user);
-
-        if (new_mtu < 0)
-                err = new_mtu;
-        else
-                dev->mtu = new_mtu;
-
-        spin_unlock(&lp->lock);
-        return err;
-#endif
         return -EINVAL;
 }
 
@@ -582,7 +498,6 @@ static const struct net_device_ops iss_netdev_ops = {
         .ndo_validate_addr      = eth_validate_addr,
         .ndo_change_mtu         = iss_net_change_mtu,
         .ndo_set_mac_address    = iss_net_set_mac,
-        //.ndo_do_ioctl         = iss_net_ioctl,
         .ndo_tx_timeout         = iss_net_tx_timeout,
         .ndo_set_rx_mode        = iss_net_set_multicast_list,
 };
@@ -593,24 +508,29 @@ static int iss_net_configure(int index, char *init)
         struct iss_net_private *lp;
         int err;
 
-        if ((dev = alloc_etherdev(sizeof *lp)) == NULL) {
-                printk(KERN_ERR "eth_configure: failed to allocate device\n");
+        dev = alloc_etherdev(sizeof(*lp));
+        if (dev == NULL) {
+                pr_err("eth_configure: failed to allocate device\n");
                 return 1;
         }
 
         /* Initialize private element. */
 
         lp = netdev_priv(dev);
-        *lp = ((struct iss_net_private) {
+        *lp = (struct iss_net_private) {
                 .device_list            = LIST_HEAD_INIT(lp->device_list),
                 .opened_list            = LIST_HEAD_INIT(lp->opened_list),
                 .lock                   = __SPIN_LOCK_UNLOCKED(lp.lock),
                 .dev                    = dev,
                 .index                  = index,
-                //.fd                   = -1,
-                .mac                    = { 0xfe, 0xfd, 0x0, 0x0, 0x0, 0x0 },
-                .have_mac               = 0,
-                });
+                };
+
+        /*
+         * If this name ends up conflicting with an existing registered
+         * netdevice, that is OK, register_netdev{,ice}() will notice this
+         * and fail.
+         */
+        snprintf(dev->name, sizeof(dev->name), "eth%d", index);
 
         /*
          * Try all transport protocols.
@@ -618,14 +538,12 @@ static int iss_net_configure(int index, char *init)
          */
 
         if (!tuntap_probe(lp, index, init)) {
-                printk("Invalid arguments. Skipping device!\n");
+                pr_err("%s: invalid arguments. Skipping device!\n",
+                       dev->name);
                 goto errout;
         }
 
-        printk(KERN_INFO "Netdevice %d ", index);
-        if (lp->have_mac)
-                printk("(%pM) ", lp->mac);
-        printk(": ");
+        pr_info("Netdevice %d (%pM)\n", index, dev->dev_addr);
 
         /* sysfs register */
 
@@ -641,14 +559,7 @@ static int iss_net_configure(int index, char *init)
         lp->pdev.id = index;
         lp->pdev.name = DRIVER_NAME;
         platform_device_register(&lp->pdev);
-        SET_NETDEV_DEV(dev,&lp->pdev.dev);
-
-        /*
-         * If this name ends up conflicting with an existing registered
-         * netdevice, that is OK, register_netdev{,ice}() will notice this
-         * and fail.
-         */
-        snprintf(dev->name, sizeof dev->name, "eth%d", index);
+        SET_NETDEV_DEV(dev, &lp->pdev.dev);
 
         dev->netdev_ops = &iss_netdev_ops;
         dev->mtu = lp->mtu;
@@ -660,7 +571,7 @@ static int iss_net_configure(int index, char *init)
         rtnl_unlock();
 
         if (err) {
-                printk("Error registering net device!\n");
+                pr_err("%s: error registering net device!\n", dev->name);
                 /* XXX: should we call ->remove() here? */
                 free_netdev(dev);
                 return 1;
@@ -669,16 +580,11 @@ static int iss_net_configure(int index, char *init)
         init_timer(&lp->tl);
         lp->tl.function = iss_net_user_timer_expire;
 
-#if 0
-        if (lp->have_mac)
-                set_ether_mac(dev, lp->mac);
-#endif
         return 0;
 
 errout:
-        // FIXME: unregister; free, etc..
+        /* FIXME: unregister; free, etc.. */
         return -EIO;
-
 }
 
 /* ------------------------------------------------------------------------- */
@@ -706,21 +612,22 @@ static int __init iss_net_setup(char *str)
         struct iss_net_init *new;
         struct list_head *ele;
         char *end;
-        int n;
+        int rc;
+        unsigned n;
 
-        n = simple_strtoul(str, &end, 0);
-        if (end == str) {
-                printk(ERR "Failed to parse '%s'\n", str);
-                return 1;
-        }
-        if (n < 0) {
-                printk(ERR "Device %d is negative\n", n);
+        end = strchr(str, '=');
+        if (!end) {
+                printk(ERR "Expected '=' after device number\n");
                 return 1;
         }
-        if (*(str = end) != '=') {
-                printk(ERR "Expected '=' after device number\n");
+        *end = 0;
+        rc = kstrtouint(str, 0, &n);
+        *end = '=';
+        if (rc < 0) {
+                printk(ERR "Failed to parse '%s'\n", str);
                 return 1;
         }
+        str = end;
 
         spin_lock(&devices_lock);
 
@@ -733,13 +640,13 @@ static int __init iss_net_setup(char *str)
         spin_unlock(&devices_lock);
 
         if (device && device->index == n) {
-                printk(ERR "Device %d already configured\n", n);
+                printk(ERR "Device %u already configured\n", n);
                 return 1;
         }
 
         new = alloc_bootmem(sizeof(*new));
         if (new == NULL) {
-                printk("Alloc_bootmem failed\n");
+                printk(ERR "Alloc_bootmem failed\n");
                 return 1;
         }
 
@@ -753,7 +660,7 @@ static int __init iss_net_setup(char *str)
 
 #undef ERR
 
-__setup("eth=", iss_net_setup);
+__setup("eth", iss_net_setup);
 
 /*
  * Initialize all ISS Ethernet devices previously registered in iss_net_setup.
diff --git a/arch/xtensa/platforms/iss/simdisk.c b/arch/xtensa/platforms/iss/simdisk.c
index 8c6e819cd8ed..48eebacdf5fe 100644
--- a/arch/xtensa/platforms/iss/simdisk.c
+++ b/arch/xtensa/platforms/iss/simdisk.c
@@ -103,18 +103,18 @@ static void simdisk_transfer(struct simdisk *dev, unsigned long sector,
 
 static int simdisk_xfer_bio(struct simdisk *dev, struct bio *bio)
 {
-        int i;
-        struct bio_vec *bvec;
-        sector_t sector = bio->bi_sector;
+        struct bio_vec bvec;
+        struct bvec_iter iter;
+        sector_t sector = bio->bi_iter.bi_sector;
 
-        bio_for_each_segment(bvec, bio, i) {
-                char *buffer = __bio_kmap_atomic(bio, i);
-                unsigned len = bvec->bv_len >> SECTOR_SHIFT;
+        bio_for_each_segment(bvec, bio, iter) {
+                char *buffer = __bio_kmap_atomic(bio, iter);
+                unsigned len = bvec.bv_len >> SECTOR_SHIFT;
 
                 simdisk_transfer(dev, sector, len, buffer,
                                 bio_data_dir(bio) == WRITE);
                 sector += len;
-                __bio_kunmap_atomic(bio);
+                __bio_kunmap_atomic(buffer);
         }
         return 0;
 }
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
index 4416773cbde5..aeb316b7ff88 100644
--- a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
+++ b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
@@ -15,10 +15,6 @@
 #ifndef __XTENSA_XTAVNET_HARDWARE_H
 #define __XTENSA_XTAVNET_HARDWARE_H
 
-/* By default NO_IRQ is defined to 0 in Linux, but we use the
-   interrupt 0 for UART... */
-#define NO_IRQ                 -1
-
 /* Memory configuration. */
 
 #define PLATFORM_DEFAULT_MEM_START 0x00000000
@@ -30,7 +26,7 @@
 
 /* Default assignment of LX60 devices to external interrupts. */
 
-#ifdef CONFIG_ARCH_HAS_SMP
+#ifdef CONFIG_XTENSA_MX
 #define DUART16552_INTNUM       XCHAL_EXTINT3_NUM
 #define OETH_IRQ                XCHAL_EXTINT4_NUM
 #else
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index 74bb74fa3f87..800227862fe8 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -168,7 +168,7 @@ void __init platform_calibrate_ccount(void)
         long clk_freq = 0;
 #ifdef CONFIG_OF
         struct device_node *cpu =
-                of_find_compatible_node(NULL, NULL, "xtensa,cpu");
+                of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
         if (cpu) {
                 u32 freq;
                 update_clock_frequency(cpu);
@@ -194,7 +194,7 @@ void __init platform_calibrate_ccount(void)
  *  Ethernet -- OpenCores Ethernet MAC (ethoc driver)
  */
 
-static struct resource ethoc_res[] __initdata = {
+static struct resource ethoc_res[] = {
         [0] = { /* register space */
                 .start = OETH_REGS_PADDR,
                 .end   = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
@@ -212,7 +212,7 @@ static struct resource ethoc_res[] __initdata = {
         },
 };
 
-static struct ethoc_platform_data ethoc_pdata __initdata = {
+static struct ethoc_platform_data ethoc_pdata = {
         /*
          * The MAC address for these boards is 00:50:c2:13:6f:xx.
          * The last byte (here as zero) is read from the DIP switches on the
@@ -222,7 +222,7 @@ static struct ethoc_platform_data ethoc_pdata __initdata = {
         .phy_id = -1,
 };
 
-static struct platform_device ethoc_device __initdata = {
+static struct platform_device ethoc_device = {
         .name = "ethoc",
         .id = -1,
         .num_resources = ARRAY_SIZE(ethoc_res),
@@ -236,13 +236,13 @@ static struct platform_device ethoc_device __initdata = {
  *  UART
  */
 
-static struct resource serial_resource __initdata = {
+static struct resource serial_resource = {
         .start  = DUART16552_PADDR,
         .end    = DUART16552_PADDR + 0x1f,
         .flags  = IORESOURCE_MEM,
 };
 
-static struct plat_serial8250_port serial_platform_data[] __initdata = {
+static struct plat_serial8250_port serial_platform_data[] = {
         [0] = {
                 .mapbase        = DUART16552_PADDR,
                 .irq            = DUART16552_INTNUM,
@@ -255,7 +255,7 @@ static struct plat_serial8250_port serial_platform_data[] __initdata = {
         { },
 };
 
-static struct platform_device xtavnet_uart __initdata = {
+static struct platform_device xtavnet_uart = {
         .name           = "serial8250",
         .id             = PLAT8250_DEV_PLATFORM,
         .dev            = {
diff --git a/arch/xtensa/variants/s6000/include/variant/irq.h b/arch/xtensa/variants/s6000/include/variant/irq.h
index 97d6fc48deff..39ca751a6255 100644
--- a/arch/xtensa/variants/s6000/include/variant/irq.h
+++ b/arch/xtensa/variants/s6000/include/variant/irq.h
@@ -1,7 +1,6 @@
 #ifndef _XTENSA_S6000_IRQ_H
 #define _XTENSA_S6000_IRQ_H
 
-#define NO_IRQ          (-1)
 #define VARIANT_NR_IRQS 8 /* GPIO interrupts */
 
 extern void variant_irq_enable(unsigned int irq);