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authorSascha Hauer <s.hauer@pengutronix.de>2010-02-04 05:18:09 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2010-02-04 05:18:09 -0500
commit9fd96bbb6a3a1fd9ba24e84a2d7ccc6ccb6beb60 (patch)
treeb0f46e9a9164f75efb59ca241ca16b6ce03be0b6 /arch
parent5c17ef878fa25e04b1e8f1d8f5fa8b267753472c (diff)
parente27bf72465f4d867a2aea33cad5e9e255c4d92ff (diff)
Merge branch 'imx/master' of git://git.pengutronix.de/git/ukl/linux-2.6 into mxc-master
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx1/Makefile1
-rw-r--r--arch/arm/mach-mx1/mach-mx1ads.c4
-rw-r--r--arch/arm/mach-mx2/Makefile1
-rw-r--r--arch/arm/mach-mx2/mach-cpuimx27.c2
-rw-r--r--arch/arm/mach-mx2/mach-imx27lite.c2
-rw-r--r--arch/arm/mach-mx2/mach-mx21ads.c2
-rw-r--r--arch/arm/mach-mx2/mach-mx27_3ds.c2
-rw-r--r--arch/arm/mach-mx2/mach-mx27ads.c2
-rw-r--r--arch/arm/mach-mx2/mach-mxt_td60.c2
-rw-r--r--arch/arm/mach-mx2/mach-pca100.c2
-rw-r--r--arch/arm/mach-mx2/mach-pcm038.c2
-rw-r--r--arch/arm/mach-mx2/serial.c48
-rw-r--r--arch/arm/mach-mx25/Makefile2
-rw-r--r--arch/arm/mach-mx25/mach-mx25pdk.c (renamed from arch/arm/mach-mx25/mx25pdk.c)2
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c2
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c2
-rw-r--r--arch/arm/mach-mx3/mach-mx35pdk.c2
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c2
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c2
-rw-r--r--arch/arm/mach-mx3/mach-qong.c2
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c2
-rw-r--r--arch/arm/plat-mxc/clock.c1
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h387
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h58
32 files changed, 349 insertions, 242 deletions
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
index 297d17210e11..fc2ddf82441b 100644
--- a/arch/arm/mach-mx1/Makefile
+++ b/arch/arm/mach-mx1/Makefile
@@ -4,6 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
7obj-y += generic.o clock.o devices.o 8obj-y += generic.o clock.o devices.o
8 9
9# Support for CMOS sensor interface 10# Support for CMOS sensor interface
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index a39433afb512..69831aa274ff 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
147 /* Maintainer: Sascha Hauer, Pengutronix */ 147 /* Maintainer: Sascha Hauer, Pengutronix */
148 .phys_io = IMX_IO_PHYS, 148 .phys_io = IMX_IO_PHYS,
149 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 149 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
150 .boot_params = PHYS_OFFSET + 0x100, 150 .boot_params = MX1_PHYS_OFFSET + 0x100,
151 .map_io = mx1_map_io, 151 .map_io = mx1_map_io,
152 .init_irq = mx1_init_irq, 152 .init_irq = mx1_init_irq,
153 .timer = &mx1ads_timer, 153 .timer = &mx1ads_timer,
@@ -157,7 +157,7 @@ MACHINE_END
157MACHINE_START(MXLADS, "Freescale MXLADS") 157MACHINE_START(MXLADS, "Freescale MXLADS")
158 .phys_io = IMX_IO_PHYS, 158 .phys_io = IMX_IO_PHYS,
159 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 159 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
160 .boot_params = PHYS_OFFSET + 0x100, 160 .boot_params = MX1_PHYS_OFFSET + 0x100,
161 .map_io = mx1_map_io, 161 .map_io = mx1_map_io,
162 .init_irq = mx1_init_irq, 162 .init_irq = mx1_init_irq,
163 .timer = &mx1ads_timer, 163 .timer = &mx1ads_timer,
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index a9c94e39e321..e8910903b24f 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -7,7 +7,6 @@
7obj-y := generic.o devices.o serial.o 7obj-y := generic.o devices.o serial.o
8CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 8CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10CFLAGS_serial.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
11 10
12obj-$(CONFIG_MACH_MX21) += clock_imx21.o 11obj-$(CONFIG_MACH_MX21) += clock_imx21.o
13 12
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
index 8e4f3d08e32c..92fd1bf7a638 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-mx2/mach-cpuimx27.c
@@ -226,7 +226,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
227 .phys_io = MX27_AIPI_BASE_ADDR, 227 .phys_io = MX27_AIPI_BASE_ADDR,
228 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 228 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
229 .boot_params = PHYS_OFFSET + 0x100, 229 .boot_params = MX27_PHYS_OFFSET + 0x100,
230 .map_io = mx27_map_io, 230 .map_io = mx27_map_io,
231 .init_irq = mx27_init_irq, 231 .init_irq = mx27_init_irq,
232 .init_machine = eukrea_cpuimx27_init, 232 .init_machine = eukrea_cpuimx27_init,
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c
index ca6ab1265f3e..621c2c1046ea 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-mx2/mach-imx27lite.c
@@ -87,7 +87,7 @@ static struct sys_timer mx27lite_timer = {
87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
88 .phys_io = MX27_AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = MX27_PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27lite_init, 93 .init_machine = mx27lite_init,
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c
index eb4a6e855595..d5eb8065df3e 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-mx2/mach-mx21ads.c
@@ -286,7 +286,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
286 /* maintainer: Freescale Semiconductor, Inc. */ 286 /* maintainer: Freescale Semiconductor, Inc. */
287 .phys_io = MX21_AIPI_BASE_ADDR, 287 .phys_io = MX21_AIPI_BASE_ADDR,
288 .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
289 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = MX21_PHYS_OFFSET + 0x100,
290 .map_io = mx21ads_map_io, 290 .map_io = mx21ads_map_io,
291 .init_irq = mx21_init_irq, 291 .init_irq = mx21_init_irq,
292 .init_machine = mx21ads_board_init, 292 .init_machine = mx21ads_board_init,
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c
index 595fea46b6f7..8c975f6514ad 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -87,7 +87,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
87 /* maintainer: Freescale Semiconductor, Inc. */ 87 /* maintainer: Freescale Semiconductor, Inc. */
88 .phys_io = MX27_AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = MX27_PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27pdk_init, 93 .init_machine = mx27pdk_init,
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c
index 385fc1c9ad38..808ca271a829 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-mx2/mach-mx27ads.c
@@ -336,7 +336,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
336 /* maintainer: Freescale Semiconductor, Inc. */ 336 /* maintainer: Freescale Semiconductor, Inc. */
337 .phys_io = MX27_AIPI_BASE_ADDR, 337 .phys_io = MX27_AIPI_BASE_ADDR,
338 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 338 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
339 .boot_params = PHYS_OFFSET + 0x100, 339 .boot_params = MX27_PHYS_OFFSET + 0x100,
340 .map_io = mx27ads_map_io, 340 .map_io = mx27ads_map_io,
341 .init_irq = mx27_init_irq, 341 .init_irq = mx27_init_irq,
342 .init_machine = mx27ads_board_init, 342 .init_machine = mx27ads_board_init,
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c
index 9ed4e492fc73..df954d879cc3 100644
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-mx2/mach-mxt_td60.c
@@ -286,7 +286,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
286 /* maintainer: Maxtrack Industrial */ 286 /* maintainer: Maxtrack Industrial */
287 .phys_io = MX27_AIPI_BASE_ADDR, 287 .phys_io = MX27_AIPI_BASE_ADDR,
288 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
289 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = MX27_PHYS_OFFSET + 0x100,
290 .map_io = mx27_map_io, 290 .map_io = mx27_map_io,
291 .init_irq = mx27_init_irq, 291 .init_irq = mx27_init_irq,
292 .init_machine = mxt_td60_board_init, 292 .init_machine = mxt_td60_board_init,
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 55dbf5a64e00..9279b42b24b5 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -235,7 +235,7 @@ static struct sys_timer pca100_timer = {
235MACHINE_START(PCA100, "phyCARD-i.MX27") 235MACHINE_START(PCA100, "phyCARD-i.MX27")
236 .phys_io = MX27_AIPI_BASE_ADDR, 236 .phys_io = MX27_AIPI_BASE_ADDR,
237 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 237 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
238 .boot_params = PHYS_OFFSET + 0x100, 238 .boot_params = MX27_PHYS_OFFSET + 0x100,
239 .map_io = mx27_map_io, 239 .map_io = mx27_map_io,
240 .init_irq = mx27_init_irq, 240 .init_irq = mx27_init_irq,
241 .init_machine = pca100_init, 241 .init_machine = pca100_init,
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 9636bb82f1e9..e055d9dd6101 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -328,7 +328,7 @@ static struct sys_timer pcm038_timer = {
328MACHINE_START(PCM038, "phyCORE-i.MX27") 328MACHINE_START(PCM038, "phyCORE-i.MX27")
329 .phys_io = MX27_AIPI_BASE_ADDR, 329 .phys_io = MX27_AIPI_BASE_ADDR,
330 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 330 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
331 .boot_params = PHYS_OFFSET + 0x100, 331 .boot_params = MX27_PHYS_OFFSET + 0x100,
332 .map_io = mx27_map_io, 332 .map_io = mx27_map_io,
333 .init_irq = mx27_init_irq, 333 .init_irq = mx27_init_irq,
334 .init_machine = pcm038_init, 334 .init_machine = pcm038_init,
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index 40a485cdc10e..1c0c835b2252 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -26,12 +26,12 @@
26 26
27static struct resource uart0[] = { 27static struct resource uart0[] = {
28 { 28 {
29 .start = UART1_BASE_ADDR, 29 .start = MX2x_UART1_BASE_ADDR,
30 .end = UART1_BASE_ADDR + 0x0B5, 30 .end = MX2x_UART1_BASE_ADDR + 0x0B5,
31 .flags = IORESOURCE_MEM, 31 .flags = IORESOURCE_MEM,
32 }, { 32 }, {
33 .start = MXC_INT_UART1, 33 .start = MX2x_INT_UART1,
34 .end = MXC_INT_UART1, 34 .end = MX2x_INT_UART1,
35 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
36 }, 36 },
37}; 37};
@@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = {
45 45
46static struct resource uart1[] = { 46static struct resource uart1[] = {
47 { 47 {
48 .start = UART2_BASE_ADDR, 48 .start = MX2x_UART2_BASE_ADDR,
49 .end = UART2_BASE_ADDR + 0x0B5, 49 .end = MX2x_UART2_BASE_ADDR + 0x0B5,
50 .flags = IORESOURCE_MEM, 50 .flags = IORESOURCE_MEM,
51 }, { 51 }, {
52 .start = MXC_INT_UART2, 52 .start = MX2x_INT_UART2,
53 .end = MXC_INT_UART2, 53 .end = MX2x_INT_UART2,
54 .flags = IORESOURCE_IRQ, 54 .flags = IORESOURCE_IRQ,
55 }, 55 },
56}; 56};
@@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = {
64 64
65static struct resource uart2[] = { 65static struct resource uart2[] = {
66 { 66 {
67 .start = UART3_BASE_ADDR, 67 .start = MX2x_UART3_BASE_ADDR,
68 .end = UART3_BASE_ADDR + 0x0B5, 68 .end = MX2x_UART3_BASE_ADDR + 0x0B5,
69 .flags = IORESOURCE_MEM, 69 .flags = IORESOURCE_MEM,
70 }, { 70 }, {
71 .start = MXC_INT_UART3, 71 .start = MX2x_INT_UART3,
72 .end = MXC_INT_UART3, 72 .end = MX2x_INT_UART3,
73 .flags = IORESOURCE_IRQ, 73 .flags = IORESOURCE_IRQ,
74 }, 74 },
75}; 75};
@@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = {
83 83
84static struct resource uart3[] = { 84static struct resource uart3[] = {
85 { 85 {
86 .start = UART4_BASE_ADDR, 86 .start = MX2x_UART4_BASE_ADDR,
87 .end = UART4_BASE_ADDR + 0x0B5, 87 .end = MX2x_UART4_BASE_ADDR + 0x0B5,
88 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
89 }, { 89 }, {
90 .start = MXC_INT_UART4, 90 .start = MX2x_INT_UART4,
91 .end = MXC_INT_UART4, 91 .end = MX2x_INT_UART4,
92 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
93 }, 93 },
94}; 94};
@@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = {
103#ifdef CONFIG_MACH_MX27 103#ifdef CONFIG_MACH_MX27
104static struct resource uart4[] = { 104static struct resource uart4[] = {
105 { 105 {
106 .start = UART5_BASE_ADDR, 106 .start = MX27_UART5_BASE_ADDR,
107 .end = UART5_BASE_ADDR + 0x0B5, 107 .end = MX27_UART5_BASE_ADDR + 0x0B5,
108 .flags = IORESOURCE_MEM, 108 .flags = IORESOURCE_MEM,
109 }, { 109 }, {
110 .start = MXC_INT_UART5, 110 .start = MX27_INT_UART5,
111 .end = MXC_INT_UART5, 111 .end = MX27_INT_UART5,
112 .flags = IORESOURCE_IRQ, 112 .flags = IORESOURCE_IRQ,
113 }, 113 },
114}; 114};
@@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = {
122 122
123static struct resource uart5[] = { 123static struct resource uart5[] = {
124 { 124 {
125 .start = UART6_BASE_ADDR, 125 .start = MX27_UART6_BASE_ADDR,
126 .end = UART6_BASE_ADDR + 0x0B5, 126 .end = MX27_UART6_BASE_ADDR + 0x0B5,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, { 128 }, {
129 .start = MXC_INT_UART6, 129 .start = MX27_INT_UART6,
130 .end = MXC_INT_UART6, 130 .end = MX27_INT_UART6,
131 .flags = IORESOURCE_IRQ, 131 .flags = IORESOURCE_IRQ,
132 }, 132 },
133}; 133};
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index fe23836a9f3d..10cebc5ced8c 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,3 @@
1obj-y := mm.o devices.o 1obj-y := mm.o devices.o
2obj-$(CONFIG_ARCH_MX25) += clock.o 2obj-$(CONFIG_ARCH_MX25) += clock.o
3obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o 3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c
index f4e8b984af72..10be38eb82a8 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25pdk.c
@@ -110,7 +110,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
110 /* Maintainer: Freescale Semiconductor, Inc. */ 110 /* Maintainer: Freescale Semiconductor, Inc. */
111 .phys_io = MX25_AIPS1_BASE_ADDR, 111 .phys_io = MX25_AIPS1_BASE_ADDR,
112 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 112 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
113 .boot_params = PHYS_OFFSET + 0x100, 113 .boot_params = MX25_PHYS_OFFSET + 0x100,
114 .map_io = mx25_map_io, 114 .map_io = mx25_map_io,
115 .init_irq = mx25_init_irq, 115 .init_irq = mx25_init_irq,
116 .init_machine = mx25pdk_init, 116 .init_machine = mx25pdk_init,
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 1fed146324f5..3d72b0b89705 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -408,7 +408,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
408 /* Maintainer: Alberto Panizzo */ 408 /* Maintainer: Alberto Panizzo */
409 .phys_io = MX31_AIPS1_BASE_ADDR, 409 .phys_io = MX31_AIPS1_BASE_ADDR,
410 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 410 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
411 .boot_params = PHYS_OFFSET + 0x00000100, 411 .boot_params = MX3x_PHYS_OFFSET + 0x100,
412 .map_io = mx31_map_io, 412 .map_io = mx31_map_io,
413 .init_irq = mx31_init_irq, 413 .init_irq = mx31_init_irq,
414 .timer = &armadillo5x0_timer, 414 .timer = &armadillo5x0_timer,
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 2484dddca549..f085d5d1a6de 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -265,7 +265,7 @@ static struct sys_timer kzm_timer = {
265MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 265MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
266 .phys_io = MX31_AIPS1_BASE_ADDR, 266 .phys_io = MX31_AIPS1_BASE_ADDR,
267 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 267 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
268 .boot_params = PHYS_OFFSET + 0x100, 268 .boot_params = MX3x_PHYS_OFFSET + 0x100,
269 .map_io = kzm_map_io, 269 .map_io = kzm_map_io,
270 .init_irq = mx31_init_irq, 270 .init_irq = mx31_init_irq,
271 .init_machine = kzm_board_init, 271 .init_machine = kzm_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 88af58514a76..b88c18ad7698 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -258,7 +258,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
258 /* Maintainer: Freescale Semiconductor, Inc. */ 258 /* Maintainer: Freescale Semiconductor, Inc. */
259 .phys_io = MX31_AIPS1_BASE_ADDR, 259 .phys_io = MX31_AIPS1_BASE_ADDR,
260 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 260 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
261 .boot_params = PHYS_OFFSET + 0x100, 261 .boot_params = MX3x_PHYS_OFFSET + 0x100,
262 .map_io = mx31pdk_map_io, 262 .map_io = mx31pdk_map_io,
263 .init_irq = mx31_init_irq, 263 .init_irq = mx31_init_irq,
264 .init_machine = mxc_board_init, 264 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 59de37887f33..2f02df212b66 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -537,7 +537,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
537 /* Maintainer: Freescale Semiconductor, Inc. */ 537 /* Maintainer: Freescale Semiconductor, Inc. */
538 .phys_io = MX31_AIPS1_BASE_ADDR, 538 .phys_io = MX31_AIPS1_BASE_ADDR,
539 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 539 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
540 .boot_params = PHYS_OFFSET + 0x100, 540 .boot_params = MX3x_PHYS_OFFSET + 0x100,
541 .map_io = mx31ads_map_io, 541 .map_io = mx31ads_map_io,
542 .init_irq = mx31ads_init_irq, 542 .init_irq = mx31ads_init_irq,
543 .init_machine = mxc_board_init, 543 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 9225cb72dd01..80847b04c063 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -197,7 +197,7 @@ static struct sys_timer mx31lilly_timer = {
197MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 197MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
198 .phys_io = MX31_AIPS1_BASE_ADDR, 198 .phys_io = MX31_AIPS1_BASE_ADDR,
199 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 199 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
200 .boot_params = PHYS_OFFSET + 0x100, 200 .boot_params = MX3x_PHYS_OFFSET + 0x100,
201 .map_io = mx31_map_io, 201 .map_io = mx31_map_io,
202 .init_irq = mx31_init_irq, 202 .init_irq = mx31_init_irq,
203 .init_machine = mx31lilly_board_init, 203 .init_machine = mx31lilly_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 8589e3d1dada..2b6d11400877 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -289,7 +289,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
289 /* Maintainer: Freescale Semiconductor, Inc. */ 289 /* Maintainer: Freescale Semiconductor, Inc. */
290 .phys_io = MX31_AIPS1_BASE_ADDR, 290 .phys_io = MX31_AIPS1_BASE_ADDR,
291 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 291 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
292 .boot_params = PHYS_OFFSET + 0x100, 292 .boot_params = MX3x_PHYS_OFFSET + 0x100,
293 .map_io = mx31lite_map_io, 293 .map_io = mx31lite_map_io,
294 .init_irq = mx31_init_irq, 294 .init_irq = mx31_init_irq,
295 .init_machine = mxc_board_init, 295 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 63f991f8817f..fe18cd513cd7 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -571,7 +571,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
571 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 571 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
572 .phys_io = MX31_AIPS1_BASE_ADDR, 572 .phys_io = MX31_AIPS1_BASE_ADDR,
573 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 573 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
574 .boot_params = PHYS_OFFSET + 0x100, 574 .boot_params = MX3x_PHYS_OFFSET + 0x100,
575 .map_io = mx31_map_io, 575 .map_io = mx31_map_io,
576 .init_irq = mx31_init_irq, 576 .init_irq = mx31_init_irq,
577 .init_machine = mxc_board_init, 577 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c
index 2d11bf053c78..bcac84d4dca4 100644
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35pdk.c
@@ -108,7 +108,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
108 /* Maintainer: Freescale Semiconductor, Inc */ 108 /* Maintainer: Freescale Semiconductor, Inc */
109 .phys_io = MX35_AIPS1_BASE_ADDR, 109 .phys_io = MX35_AIPS1_BASE_ADDR,
110 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 110 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
111 .boot_params = PHYS_OFFSET + 0x100, 111 .boot_params = MX3x_PHYS_OFFSET + 0x100,
112 .map_io = mx35_map_io, 112 .map_io = mx35_map_io,
113 .init_irq = mx35_init_irq, 113 .init_irq = mx35_init_irq,
114 .init_machine = mxc_board_init, 114 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index d9bd7d2b0ade..21f54811a630 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -638,7 +638,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
638 /* Maintainer: Pengutronix */ 638 /* Maintainer: Pengutronix */
639 .phys_io = MX31_AIPS1_BASE_ADDR, 639 .phys_io = MX31_AIPS1_BASE_ADDR,
640 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 640 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
641 .boot_params = PHYS_OFFSET + 0x100, 641 .boot_params = MX3x_PHYS_OFFSET + 0x100,
642 .map_io = mx31_map_io, 642 .map_io = mx31_map_io,
643 .init_irq = mx31_init_irq, 643 .init_irq = mx31_init_irq,
644 .init_machine = mxc_board_init, 644 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 1212194fb9c2..25942b8e8bed 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -250,7 +250,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
250 /* Maintainer: Pengutronix */ 250 /* Maintainer: Pengutronix */
251 .phys_io = MX35_AIPS1_BASE_ADDR, 251 .phys_io = MX35_AIPS1_BASE_ADDR,
252 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 252 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
253 .boot_params = PHYS_OFFSET + 0x100, 253 .boot_params = MX3x_PHYS_OFFSET + 0x100,
254 .map_io = mx35_map_io, 254 .map_io = mx35_map_io,
255 .init_irq = mx35_init_irq, 255 .init_irq = mx35_init_irq,
256 .init_machine = mxc_board_init, 256 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index fdb819ae0e60..e5b5b8323a17 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -275,7 +275,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
275 /* Maintainer: DENX Software Engineering GmbH */ 275 /* Maintainer: DENX Software Engineering GmbH */
276 .phys_io = MX31_AIPS1_BASE_ADDR, 276 .phys_io = MX31_AIPS1_BASE_ADDR,
277 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 277 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
278 .boot_params = PHYS_OFFSET + 0x100, 278 .boot_params = MX3x_PHYS_OFFSET + 0x100,
279 .map_io = mx31_map_io, 279 .map_io = mx31_map_io,
280 .init_irq = mx31_init_irq, 280 .init_irq = mx31_init_irq,
281 .init_machine = mxc_board_init, 281 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 7dbe4ca12efd..69816ba82930 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -55,7 +55,7 @@ struct sys_timer zn5_timer = {
55MACHINE_START(MAGX_ZN5, "Motorola Zn5") 55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .phys_io = MXC91231_AIPS1_BASE_ADDR, 56 .phys_io = MXC91231_AIPS1_BASE_ADDR,
57 .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 57 .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
58 .boot_params = PHYS_OFFSET + 0x100, 58 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
59 .map_io = mxc91231_map_io, 59 .map_io = mxc91231_map_io,
60 .init_irq = mxc91231_init_irq, 60 .init_irq = mxc91231_init_irq,
61 .timer = &zn5_timer, 61 .timer = &zn5_timer,
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 9e8fbd57495c..323ff8ccc877 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk)
56 __clk_disable(clk->parent); 56 __clk_disable(clk->parent);
57 __clk_disable(clk->secondary); 57 __clk_disable(clk->secondary);
58 58
59 WARN_ON(!clk->usecount);
59 if (!(--clk->usecount) && clk->disable) 60 if (!(--clk->usecount) && clk->disable)
60 clk->disable(clk); 61 clk->disable(clk);
61} 62}
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 21e0f077268c..916d4fcb2ef2 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -51,7 +51,7 @@
51#endif 51#endif
52#include <mach/mxc91231.h> 52#include <mach/mxc91231.h>
53#define UART_PADDR MXC91231_UART2_BASE_ADDR 53#define UART_PADDR MXC91231_UART2_BASE_ADDR
54#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) 54#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
55#endif 55#endif
56 .macro addruart,rx 56 .macro addruart,rx
57 mrc p15, 0, \rx, c1, c0 57 mrc p15, 0, \rx, c1, c0
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index d3afafdcc0e5..002eb91ab235 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -11,21 +11,27 @@
11#ifndef __ASM_ARCH_MXC_MEMORY_H__ 11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__ 12#define __ASM_ARCH_MXC_MEMORY_H__
13 13
14#if defined CONFIG_ARCH_MX1 14#define MX1_PHYS_OFFSET UL(0x08000000)
15#define PHYS_OFFSET UL(0x08000000) 15#define MX21_PHYS_OFFSET UL(0xc0000000)
16#elif defined CONFIG_ARCH_MX2 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#ifdef CONFIG_MACH_MX21 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define PHYS_OFFSET UL(0xC0000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#endif 19#define MXC91231_PHYS_OFFSET UL(0x90000000)
20#ifdef CONFIG_MACH_MX27 20
21#define PHYS_OFFSET UL(0xA0000000) 21#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
22#endif 22# if defined CONFIG_ARCH_MX1
23#elif defined CONFIG_ARCH_MX3 23# define PHYS_OFFSET MX1_PHYS_OFFSET
24#define PHYS_OFFSET UL(0x80000000) 24# elif defined CONFIG_MACH_MX21
25#elif defined CONFIG_ARCH_MX25 25# define PHYS_OFFSET MX21_PHYS_OFFSET
26#define PHYS_OFFSET UL(0x80000000) 26# elif defined CONFIG_ARCH_MX25
27#elif defined CONFIG_ARCH_MXC91231 27# define PHYS_OFFSET MX25_PHYS_OFFSET
28#define PHYS_OFFSET UL(0x90000000) 28# elif defined CONFIG_MACH_MX27
29# define PHYS_OFFSET MX27_PHYS_OFFSET
30# elif defined CONFIG_ARCH_MX3
31# define PHYS_OFFSET MX3x_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MXC91231
33# define PHYS_OFFSET MXC91231_PHYS_OFFSET
34# endif
29#endif 35#endif
30 36
31#if defined(CONFIG_MX1_VIDEO) 37#if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index b652a9c25865..5eba7e6785de 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -17,148 +17,281 @@
17/* 17/*
18 * Memory map 18 * Memory map
19 */ 19 */
20#define IMX_IO_PHYS 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define IMX_IO_SIZE 0x00100000 21#define MX1_IO_SIZE SZ_1M
22#define IMX_IO_BASE VMALLOC_END 22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 23
24#define IMX_CS0_PHYS 0x10000000 24#define MX1_CS0_PHYS 0x10000000
25#define IMX_CS0_SIZE 0x02000000 25#define MX1_CS0_SIZE 0x02000000
26 26
27#define IMX_CS1_PHYS 0x12000000 27#define MX1_CS1_PHYS 0x12000000
28#define IMX_CS1_SIZE 0x01000000 28#define MX1_CS1_SIZE 0x01000000
29 29
30#define IMX_CS2_PHYS 0x13000000 30#define MX1_CS2_PHYS 0x13000000
31#define IMX_CS2_SIZE 0x01000000 31#define MX1_CS2_SIZE 0x01000000
32 32
33#define IMX_CS3_PHYS 0x14000000 33#define MX1_CS3_PHYS 0x14000000
34#define IMX_CS3_SIZE 0x01000000 34#define MX1_CS3_SIZE 0x01000000
35 35
36#define IMX_CS4_PHYS 0x15000000 36#define MX1_CS4_PHYS 0x15000000
37#define IMX_CS4_SIZE 0x01000000 37#define MX1_CS4_SIZE 0x01000000
38 38
39#define IMX_CS5_PHYS 0x16000000 39#define MX1_CS5_PHYS 0x16000000
40#define IMX_CS5_SIZE 0x01000000 40#define MX1_CS5_SIZE 0x01000000
41 41
42/* 42/*
43 * Register BASEs, based on OFFSETs 43 * Register BASEs, based on OFFSETs
44 */ 44 */
45#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) 45#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
46#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) 46#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
47#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) 47#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
48#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) 48#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
49#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) 49#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
50#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) 50#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
51#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) 51#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
52#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) 52#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
53#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) 53#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
54#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) 54#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
55#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) 55#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
56#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) 56#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
57#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) 57#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
58#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) 58#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
59#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) 59#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
60#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) 60#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
61#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) 61#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
62#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) 62#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
63#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) 63#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
64#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) 64#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
65#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) 65#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
66#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) 66#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
67#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) 67#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
68#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) 68#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) 69#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
70#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) 70#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
71#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) 71#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
72#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) 72#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
73#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) 73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 74
75/* macro to get at IO space when running virtually */ 75/* macro to get at IO space when running virtually */
76#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) 76#define MX1_IO_ADDRESS(x) ( \
77 77 IMX_IO_ADDRESS(x, MX1_IO))
78/* define macros needed for entry-macro.S */
79#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
80 78
81/* fixed interrput numbers */ 79/* fixed interrput numbers */
82#define INT_SOFTINT 0 80#define MX1_INT_SOFTINT 0
83#define CSI_INT 6 81#define MX1_CSI_INT 6
84#define DSPA_MAC_INT 7 82#define MX1_DSPA_MAC_INT 7
85#define DSPA_INT 8 83#define MX1_DSPA_INT 8
86#define COMP_INT 9 84#define MX1_COMP_INT 9
87#define MSHC_XINT 10 85#define MX1_MSHC_XINT 10
88#define GPIO_INT_PORTA 11 86#define MX1_GPIO_INT_PORTA 11
89#define GPIO_INT_PORTB 12 87#define MX1_GPIO_INT_PORTB 12
90#define GPIO_INT_PORTC 13 88#define MX1_GPIO_INT_PORTC 13
91#define LCDC_INT 14 89#define MX1_LCDC_INT 14
92#define SIM_INT 15 90#define MX1_SIM_INT 15
93#define SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
94#define RTC_INT 17 92#define MX1_RTC_INT 17
95#define RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
96#define UART2_MINT_PFERR 19 94#define MX1_UART2_MINT_PFERR 19
97#define UART2_MINT_RTS 20 95#define MX1_UART2_MINT_RTS 20
98#define UART2_MINT_DTR 21 96#define MX1_UART2_MINT_DTR 21
99#define UART2_MINT_UARTC 22 97#define MX1_UART2_MINT_UARTC 22
100#define UART2_MINT_TX 23 98#define MX1_UART2_MINT_TX 23
101#define UART2_MINT_RX 24 99#define MX1_UART2_MINT_RX 24
102#define UART1_MINT_PFERR 25 100#define MX1_UART1_MINT_PFERR 25
103#define UART1_MINT_RTS 26 101#define MX1_UART1_MINT_RTS 26
104#define UART1_MINT_DTR 27 102#define MX1_UART1_MINT_DTR 27
105#define UART1_MINT_UARTC 28 103#define MX1_UART1_MINT_UARTC 28
106#define UART1_MINT_TX 29 104#define MX1_UART1_MINT_TX 29
107#define UART1_MINT_RX 30 105#define MX1_UART1_MINT_RX 30
108#define VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
109#define VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
110#define PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
111#define PWM_INT 34 109#define MX1_PWM_INT 34
112#define SDHC_INT 35 110#define MX1_SDHC_INT 35
113#define I2C_INT 39 111#define MX1_I2C_INT 39
114#define CSPI_INT 41 112#define MX1_CSPI_INT 41
115#define SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
116#define SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
117#define SSI_RX_INT 44 115#define MX1_SSI_RX_INT 44
118#define SSI_RX_ERR_INT 45 116#define MX1_SSI_RX_ERR_INT 45
119#define TOUCH_INT 46 117#define MX1_TOUCH_INT 46
120#define USBD_INT0 47 118#define MX1_USBD_INT0 47
121#define USBD_INT1 48 119#define MX1_USBD_INT1 48
122#define USBD_INT2 49 120#define MX1_USBD_INT2 49
123#define USBD_INT3 50 121#define MX1_USBD_INT3 50
124#define USBD_INT4 51 122#define MX1_USBD_INT4 51
125#define USBD_INT5 52 123#define MX1_USBD_INT5 52
126#define USBD_INT6 53 124#define MX1_USBD_INT6 53
127#define BTSYS_INT 55 125#define MX1_BTSYS_INT 55
128#define BTTIM_INT 56 126#define MX1_BTTIM_INT 56
129#define BTWUI_INT 57 127#define MX1_BTWUI_INT 57
130#define TIM2_INT 58 128#define MX1_TIM2_INT 58
131#define TIM1_INT 59 129#define MX1_TIM1_INT 59
132#define DMA_ERR 60 130#define MX1_DMA_ERR 60
133#define DMA_INT 61 131#define MX1_DMA_INT 61
134#define GPIO_INT_PORTD 62 132#define MX1_GPIO_INT_PORTD 62
135#define WDT_INT 63 133#define MX1_WDT_INT 63
136 134
137/* DMA */ 135/* DMA */
138#define DMA_REQ_UART3_T 2 136#define MX1_DMA_REQ_UART3_T 2
139#define DMA_REQ_UART3_R 3 137#define MX1_DMA_REQ_UART3_R 3
140#define DMA_REQ_SSI2_T 4 138#define MX1_DMA_REQ_SSI2_T 4
141#define DMA_REQ_SSI2_R 5 139#define MX1_DMA_REQ_SSI2_R 5
142#define DMA_REQ_CSI_STAT 6 140#define MX1_DMA_REQ_CSI_STAT 6
143#define DMA_REQ_CSI_R 7 141#define MX1_DMA_REQ_CSI_R 7
144#define DMA_REQ_MSHC 8 142#define MX1_DMA_REQ_MSHC 8
145#define DMA_REQ_DSPA_DCT_DOUT 9 143#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
146#define DMA_REQ_DSPA_DCT_DIN 10 144#define MX1_DMA_REQ_DSPA_DCT_DIN 10
147#define DMA_REQ_DSPA_MAC 11 145#define MX1_DMA_REQ_DSPA_MAC 11
148#define DMA_REQ_EXT 12 146#define MX1_DMA_REQ_EXT 12
149#define DMA_REQ_SDHC 13 147#define MX1_DMA_REQ_SDHC 13
150#define DMA_REQ_SPI1_R 14 148#define MX1_DMA_REQ_SPI1_R 14
151#define DMA_REQ_SPI1_T 15 149#define MX1_DMA_REQ_SPI1_T 15
152#define DMA_REQ_SSI_T 16 150#define MX1_DMA_REQ_SSI_T 16
153#define DMA_REQ_SSI_R 17 151#define MX1_DMA_REQ_SSI_R 17
154#define DMA_REQ_ASP_DAC 18 152#define MX1_DMA_REQ_ASP_DAC 18
155#define DMA_REQ_ASP_ADC 19 153#define MX1_DMA_REQ_ASP_ADC 19
156#define DMA_REQ_USP_EP(x) (20 + (x)) 154#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
157#define DMA_REQ_SPI2_R 26 155#define MX1_DMA_REQ_SPI2_R 26
158#define DMA_REQ_SPI2_T 27 156#define MX1_DMA_REQ_SPI2_T 27
159#define DMA_REQ_UART2_T 28 157#define MX1_DMA_REQ_UART2_T 28
160#define DMA_REQ_UART2_R 29 158#define MX1_DMA_REQ_UART2_R 29
161#define DMA_REQ_UART1_T 30 159#define MX1_DMA_REQ_UART1_T 30
162#define DMA_REQ_UART1_R 31 160#define MX1_DMA_REQ_UART1_R 31
161
162/*
163 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
164 * to not break drivers/usb/gadget/imx_udc. Should go
165 * away after this driver uses the new name.
166 */
167#define USBD_INT0 MX1_USBD_INT0
168
169#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
170/* these should go away */
171#define IMX_IO_PHYS MX1_IO_BASE_ADDR
172#define IMX_IO_SIZE MX1_IO_SIZE
173#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
174#define IMX_CS0_PHYS MX1_CS0_PHYS
175#define IMX_CS0_SIZE MX1_CS0_SIZE
176#define IMX_CS1_PHYS MX1_CS1_PHYS
177#define IMX_CS1_SIZE MX1_CS1_SIZE
178#define IMX_CS2_PHYS MX1_CS2_PHYS
179#define IMX_CS2_SIZE MX1_CS2_SIZE
180#define IMX_CS3_PHYS MX1_CS3_PHYS
181#define IMX_CS3_SIZE MX1_CS3_SIZE
182#define IMX_CS4_PHYS MX1_CS4_PHYS
183#define IMX_CS4_SIZE MX1_CS4_SIZE
184#define IMX_CS5_PHYS MX1_CS5_PHYS
185#define IMX_CS5_SIZE MX1_CS5_SIZE
186#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
187#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
188#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
189#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
190#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
191#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
192#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
194#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
195#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
196#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
197#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
198#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
199#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
200#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
201#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
202#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
203#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
204#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
205#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
206#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
207#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
208#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
209#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
210#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
211#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
212#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
213#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
214#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
215#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
216#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
217#define INT_SOFTINT MX1_INT_SOFTINT
218#define CSI_INT MX1_CSI_INT
219#define DSPA_MAC_INT MX1_DSPA_MAC_INT
220#define DSPA_INT MX1_DSPA_INT
221#define COMP_INT MX1_COMP_INT
222#define MSHC_XINT MX1_MSHC_XINT
223#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
224#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
225#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
226#define LCDC_INT MX1_LCDC_INT
227#define SIM_INT MX1_SIM_INT
228#define SIM_DATA_INT MX1_SIM_DATA_INT
229#define RTC_INT MX1_RTC_INT
230#define RTC_SAMINT MX1_RTC_SAMINT
231#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
232#define UART2_MINT_RTS MX1_UART2_MINT_RTS
233#define UART2_MINT_DTR MX1_UART2_MINT_DTR
234#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
235#define UART2_MINT_TX MX1_UART2_MINT_TX
236#define UART2_MINT_RX MX1_UART2_MINT_RX
237#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
238#define UART1_MINT_RTS MX1_UART1_MINT_RTS
239#define UART1_MINT_DTR MX1_UART1_MINT_DTR
240#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
241#define UART1_MINT_TX MX1_UART1_MINT_TX
242#define UART1_MINT_RX MX1_UART1_MINT_RX
243#define VOICE_DAC_INT MX1_VOICE_DAC_INT
244#define VOICE_ADC_INT MX1_VOICE_ADC_INT
245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT
249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
252#define SSI_RX_INT MX1_SSI_RX_INT
253#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
254#define TOUCH_INT MX1_TOUCH_INT
255#define USBD_INT1 MX1_USBD_INT1
256#define USBD_INT2 MX1_USBD_INT2
257#define USBD_INT3 MX1_USBD_INT3
258#define USBD_INT4 MX1_USBD_INT4
259#define USBD_INT5 MX1_USBD_INT5
260#define USBD_INT6 MX1_USBD_INT6
261#define BTSYS_INT MX1_BTSYS_INT
262#define BTTIM_INT MX1_BTTIM_INT
263#define BTWUI_INT MX1_BTWUI_INT
264#define TIM2_INT MX1_TIM2_INT
265#define TIM1_INT MX1_TIM1_INT
266#define DMA_ERR MX1_DMA_ERR
267#define DMA_INT MX1_DMA_INT
268#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
269#define WDT_INT MX1_WDT_INT
270#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
271#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
272#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
273#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
274#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
275#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
276#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
277#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
278#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
279#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
280#define DMA_REQ_EXT MX1_DMA_REQ_EXT
281#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
282#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
283#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
284#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
285#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
286#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
287#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
288#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
289#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
290#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
291#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
292#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
293#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
294#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
295#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
163 296
164#endif /* ifndef __MACH_MX1_H__ */ 297#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 61052a33979c..4ef9d5332b4a 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -27,8 +27,8 @@
27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ 27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
28 IMX_IO_ADDRESS(x, MX25_AVIC)) 28 IMX_IO_ADDRESS(x, MX25_AVIC))
29 29
30#define UART1_BASE_ADDR 0x43f90000 30#define MX25_UART1_BASE_ADDR 0x43f90000
31#define UART2_BASE_ADDR 0x43f94000 31#define MX25_UART2_BASE_ADDR 0x43f94000
32 32
33#define MX25_FEC_BASE_ADDR 0x50038000 33#define MX25_FEC_BASE_ADDR 0x50038000
34#define MX25_NFC_BASE_ADDR 0xbb000000 34#define MX25_NFC_BASE_ADDR 0xbb000000
@@ -38,4 +38,9 @@
38#define MX25_INT_FEC 57 38#define MX25_INT_FEC 57
39#define MX25_INT_NANDFC 33 39#define MX25_INT_NANDFC 33
40 40
41#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
42#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
43#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR
44#endif
45
41#endif /* ifndef __MACH_MX25_H__ */ 46#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 81484d1ef232..5182b986b785 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -184,60 +184,22 @@
184#define MXC91231_CS4_BASE_ADDR 0xB4000000 184#define MXC91231_CS4_BASE_ADDR 0xB4000000
185#define MXC91231_CS5_BASE_ADDR 0xB6000000 185#define MXC91231_CS5_BASE_ADDR 0xB6000000
186 186
187/* Is given address belongs to the specified memory region? */
188#define ADDRESS_IN_REGION(addr, start, size) \
189 (((addr) >= (start)) && ((addr) < (start)+(size)))
190
191/* Is given address belongs to the specified named `module'? */
192#define MXC91231_IS_MODULE(addr, module) \
193 ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
194 MXC91231_ ## module ## _SIZE)
195/* 187/*
196 * This macro defines the physical to virtual address mapping for all the 188 * This macro defines the physical to virtual address mapping for all the
197 * peripheral modules. It is used by passing in the physical address as x 189 * peripheral modules. It is used by passing in the physical address as x
198 * and returning the virtual address. If the physical address is not mapped, 190 * and returning the virtual address. If the physical address is not mapped,
199 * it returns 0xDEADBEEF 191 * it returns 0.
200 */
201
202#define MXC91231_IO_ADDRESS(x) \
203 (void __iomem *) \
204 (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
205 MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
206 MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
207 MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
208 MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
209 MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
210 MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
211 MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
212 0xDEADBEEF)
213
214
215/*
216 * define the address mapping macros: in physical address order
217 */ 192 */
218#define MXC91231_L2CC_IO_ADDRESS(x) \
219 (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
220
221#define MXC91231_AIPS1_IO_ADDRESS(x) \
222 (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
223
224#define MXC91231_SPBA0_IO_ADDRESS(x) \
225 (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
226
227#define MXC91231_SPBA1_IO_ADDRESS(x) \
228 (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
229
230#define MXC91231_AIPS2_IO_ADDRESS(x) \
231 (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
232
233#define MXC91231_ROMP_IO_ADDRESS(x) \
234 (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
235
236#define MXC91231_AVIC_IO_ADDRESS(x) \
237 (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
238 193
239#define MXC91231_X_MEMC_IO_ADDRESS(x) \ 194#define MXC91231_IO_ADDRESS(x) ( \
240 (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) 195 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
196 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
197 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
198 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
199 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
200 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
201 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
202 IMX_IO_ADDRESS(x, MXC91231_AIPS2))
241 203
242/* 204/*
243 * Interrupt numbers 205 * Interrupt numbers
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 10:18:54 -0500