x86: unmask CPUID levels on Intel CPUs, fix

Impact: fix boot hang on pre-model-15 Intel CPUs

rdmsrl_safe() does not work in very early bootup code yet, because we
dont have the pagefault handler installed yet so exception section
does not get parsed. rdmsr_safe() will just crash and hang the bootup.

So limit the MSR_IA32_MISC_ENABLE MSR read to those CPU types that
support it.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 11 insertions, 8 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 43c1dcf0bec7..549f2ada55f5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -29,14 +29,17 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
-        u64 misc_enable;
-
-        /* Unmask CPUID levels if masked */
-        if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
-            (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
-                misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-                wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-                c->cpuid_level = cpuid_eax(0);
+        /* Unmask CPUID levels if masked: */
+        if (c->x86 == 6 && c->x86_model >= 15) {
+                u64 misc_enable;
+
+                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+                if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+                        misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                        c->cpuid_level = cpuid_eax(0);
+                }
         }
 
         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||