diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-03-24 07:01:52 -0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-04-11 14:29:09 -0400 |
| commit | 8e4cb9aac2ada7f8a986606703c34e2d573bb876 (patch) | |
| tree | de9f5ee073353e9253df9dcaa91145254fbe45cc /arch | |
| parent | c6c56697ae4bf1226263c19e8353343d7083f40e (diff) | |
ARM: AM43xx: fix dpll init in bypass mode
On AM43xx, if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.
omap2_init_dpll_parent() has similar issue.
Add the missing soc_is_am43xx() check to make the code work on AM43xx.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 2649ce445845..332af927f4d3 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
| @@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) | |||
| 209 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | 209 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
| 210 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | 210 | v == OMAP3XXX_EN_DPLL_FRBYPASS) |
| 211 | return 1; | 211 | return 1; |
| 212 | } else if (soc_is_am33xx() || cpu_is_omap44xx()) { | 212 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { |
| 213 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | 213 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || |
| 214 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | 214 | v == OMAP4XXX_EN_DPLL_FRBYPASS || |
| 215 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | 215 | v == OMAP4XXX_EN_DPLL_MNBYPASS) |
| @@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | |||
| 255 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | 255 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
| 256 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | 256 | v == OMAP3XXX_EN_DPLL_FRBYPASS) |
| 257 | return __clk_get_rate(dd->clk_bypass); | 257 | return __clk_get_rate(dd->clk_bypass); |
| 258 | } else if (soc_is_am33xx() || cpu_is_omap44xx()) { | 258 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { |
| 259 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | 259 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || |
| 260 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | 260 | v == OMAP4XXX_EN_DPLL_FRBYPASS || |
| 261 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | 261 | v == OMAP4XXX_EN_DPLL_MNBYPASS) |