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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-07-14 11:23:29 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-07-18 07:30:14 -0400
commit8cf2389bc4456057a4d9663d22429fb677f1b13e (patch)
treef4c25ee98fed26110709e4ddb330e30c3d87bd07 /arch
parent6b076991dca9817e75c37e2f0db6d52611ea42fa (diff)
ARM: 8100/1: Fix preemption disable in iwmmxt_task_enable()
commit 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()") introduced macros {inc,dec}_preempt_count to iwmmxt_task_enable to make it run with preemption disabled. Unfortunately, other functions in iwmmxt.S also use concan_{save,dump,load} sections located in iwmmxt_task_enable() to deal with iWMMXt coprocessor. This causes an unbalanced preempt_count due to excessive dec_preempt_count and destroyed return addresses in callers of concan_ labels due to a register collision: Linux version 3.16.0-rc3-00062-gd92a333-dirty (jef@armhf) (gcc version 4.8.3 (Debian 4.8.3-4) ) #5 PREEMPT Thu Jul 3 19:46:39 CEST 2014 CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache Machine model: SolidRun CuBox ... PJ4 iWMMXt v2 coprocessor enabled. ... Unable to handle kernel paging request at virtual address fffffffe pgd = bb25c000 [fffffffe] *pgd=3bfde821, *pte=00000000, *ppte=00000000 Internal error: Oops: 80000007 [#1] PREEMPT ARM Modules linked in: CPU: 0 PID: 62 Comm: startpar Not tainted 3.16.0-rc3-00062-gd92a333-dirty #5 task: bb230b80 ti: bb256000 task.ti: bb256000 PC is at 0xfffffffe LR is at iwmmxt_task_copy+0x44/0x4c pc : [<fffffffe>] lr : [<800130ac>] psr: 40000033 sp : bb257de8 ip : 00000013 fp : bb257ea4 r10: bb256000 r9 : fffffdfe r8 : 76e898e6 r7 : bb257ec8 r6 : bb256000 r5 : 7ea12760 r4 : 000000a0 r3 : ffffffff r2 : 00000003 r1 : bb257df8 r0 : 00000000 Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user Control: 10c5387d Table: 3b25c019 DAC: 00000015 Process startpar (pid: 62, stack limit = 0xbb256248) This patch fixes the issue by moving concan_{save,dump,load} into separate code sections and make iwmmxt_task_enable() call them in the same way the other functions use concan_ symbols. The test for valid ownership is moved to concan_save and is safe for the other user of it, iwmmxt_task_disable(). The register collision is also resolved by moving concan_ symbols as {inc,dec}_preempt_count are now local to iwmmxt_task_enable(). Fixes: 431a84b1a4f7 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()") Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/iwmmxt.S23
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a5599cfc43cb..2b32978ae905 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -94,13 +94,19 @@ ENTRY(iwmmxt_task_enable)
94 94
95 mrc p15, 0, r2, c2, c0, 0 95 mrc p15, 0, r2, c2, c0, 0
96 mov r2, r2 @ cpwait 96 mov r2, r2 @ cpwait
97 bl concan_save
97 98
98 teq r1, #0 @ test for last ownership 99#ifdef CONFIG_PREEMPT_COUNT
99 mov lr, r9 @ normal exit from exception 100 get_thread_info r10
100 beq concan_load @ no owner, skip save 101#endif
1024: dec_preempt_count r10, r3
103 mov pc, r9 @ normal exit from exception
101 104
102concan_save: 105concan_save:
103 106
107 teq r1, #0 @ test for last ownership
108 beq concan_load @ no owner, skip save
109
104 tmrc r2, wCon 110 tmrc r2, wCon
105 111
106 @ CUP? wCx 112 @ CUP? wCx
@@ -138,7 +144,7 @@ concan_dump:
138 wstrd wR15, [r1, #MMX_WR15] 144 wstrd wR15, [r1, #MMX_WR15]
139 145
1402: teq r0, #0 @ anything to load? 1462: teq r0, #0 @ anything to load?
141 beq 3f 147 moveq pc, lr @ if not, return
142 148
143concan_load: 149concan_load:
144 150
@@ -171,14 +177,9 @@ concan_load:
171 @ clear CUP/MUP (only if r1 != 0) 177 @ clear CUP/MUP (only if r1 != 0)
172 teq r1, #0 178 teq r1, #0
173 mov r2, #0 179 mov r2, #0
174 beq 3f 180 moveq pc, lr
175 tmcr wCon, r2
176 181
1773: 182 tmcr wCon, r2
178#ifdef CONFIG_PREEMPT_COUNT
179 get_thread_info r10
180#endif
1814: dec_preempt_count r10, r3
182 mov pc, lr 183 mov pc, lr
183 184
184/* 185/*