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authorkiran.padwal@smartplayin.com <kiran.padwal@smartplayin.com>2014-09-17 06:30:25 -0400
committerKumar Gala <galak@codeaurora.org>2014-09-17 18:24:20 -0400
commit8c3166f5d74b7936d29dc44f778e759c1b9fb43a (patch)
tree6f8803064d5bc42f1359c57c46ec03803c4ab26f /arch
parent0be5fef161151b8841d3e3d33d815695384a9451 (diff)
ARM: DT: apq8064: Add i2c device nodes
This patch adds i2c pinctrl DT node for IFC6410 board. It also adds necessary DT support for i2c eeprom which is present on IFC6410. Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts27
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi42
2 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 27c7dfeec186..b396c8311b27 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -5,6 +5,33 @@
5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; 5 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
6 6
7 soc { 7 soc {
8 pinctrl@800000 {
9 i2c1_pins: i2c1 {
10 mux {
11 pins = "gpio20", "gpio21";
12 function = "gsbi1";
13 };
14 };
15 };
16
17 gsbi@12440000 {
18 status = "okay";
19 qcom,mode = <GSBI_PROT_I2C>;
20
21 i2c@12460000 {
22 status = "okay";
23 clock-frequency = <200000>;
24 pinctrl-0 = <&i2c1_pins>;
25 pinctrl-names = "default";
26
27 eeprom: eeprom@52 {
28 compatible = "atmel,24c128";
29 reg = <0x52>;
30 pagesize = <32>;
31 };
32 };
33 };
34
8 gsbi@16600000 { 35 gsbi@16600000 {
9 status = "ok"; 36 status = "ok";
10 qcom,mode = <GSBI_PROT_I2C_UART>; 37 qcom,mode = <GSBI_PROT_I2C_UART>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index f31d20b3ceb4..b3154c071652 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -163,6 +163,48 @@
163 regulator; 163 regulator;
164 }; 164 };
165 165
166 gsbi1: gsbi@12440000 {
167 status = "disabled";
168 compatible = "qcom,gsbi-v1.0.0";
169 reg = <0x12440000 0x100>;
170 clocks = <&gcc GSBI1_H_CLK>;
171 clock-names = "iface";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 i2c1: i2c@12460000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x12460000 0x1000>;
179 interrupts = <0 194 IRQ_TYPE_NONE>;
180 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
181 clock-names = "core", "iface";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185 };
186
187 gsbi2: gsbi@12480000 {
188 status = "disabled";
189 compatible = "qcom,gsbi-v1.0.0";
190 reg = <0x12480000 0x100>;
191 clocks = <&gcc GSBI2_H_CLK>;
192 clock-names = "iface";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges;
196
197 i2c2: i2c@124a0000 {
198 compatible = "qcom,i2c-qup-v1.1.1";
199 reg = <0x124a0000 0x1000>;
200 interrupts = <0 196 IRQ_TYPE_NONE>;
201 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
202 clock-names = "core", "iface";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 };
206 };
207
166 gsbi7: gsbi@16600000 { 208 gsbi7: gsbi@16600000 {
167 status = "disabled"; 209 status = "disabled";
168 compatible = "qcom,gsbi-v1.0.0"; 210 compatible = "qcom,gsbi-v1.0.0";