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authorDavid Brown <davidb@codeaurora.org>2011-01-04 14:02:59 -0500
committerDavid Brown <davidb@codeaurora.org>2011-01-21 18:27:50 -0500
commit8bb06444804c58dffcb5d048381c6378d2b007f7 (patch)
tree2397d12f923ffce2cbb78df59d576506c63d814a /arch
parent8c27e6f305242ffab0c88eed5dea8394b8ce86d0 (diff)
msm: Generalize QGIC registers
The QGIC registers are mapped to the same virtual addresses across targets, only the physical address changes. Move the BASE address out of target-specific files, and add a SOC name to the base addresses. Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h2
-rw-r--r--arch/arm/mach-msm/io.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index d5482d65bb37..5bd18db11aea 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -35,13 +35,11 @@
35 * 35 *
36 */ 36 */
37 37
38#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) 38#define MSM8X60_QGIC_DIST_PHYS 0x02080000
39#define MSM_QGIC_DIST_PHYS 0x02080000 39#define MSM8X60_QGIC_DIST_SIZE SZ_4K
40#define MSM_QGIC_DIST_SIZE SZ_4K
41 40
42#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) 41#define MSM8X60_QGIC_CPU_PHYS 0x02081000
43#define MSM_QGIC_CPU_PHYS 0x02081000 42#define MSM8X60_QGIC_CPU_SIZE SZ_4K
44#define MSM_QGIC_CPU_SIZE SZ_4K
45 43
46#define MSM_ACC_BASE IOMEM(0xF0002000) 44#define MSM_ACC_BASE IOMEM(0xF0002000)
47#define MSM_ACC_PHYS 0x02001000 45#define MSM_ACC_PHYS 0x02001000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 0243bd0c3656..bb42de31886c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,8 @@
55 55
56/* Virtual addressses shared across all MSM targets. */ 56/* Virtual addressses shared across all MSM targets. */
57#define MSM_CSR_BASE IOMEM(0xE0001000) 57#define MSM_CSR_BASE IOMEM(0xE0001000)
58#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
59#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
58#define MSM_TMR_BASE IOMEM(0xF0200000) 60#define MSM_TMR_BASE IOMEM(0xF0200000)
59#define MSM_TMR0_BASE IOMEM(0xF0201000) 61#define MSM_TMR0_BASE IOMEM(0xF0201000)
60 62
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 97dcd8c43ab0..49692bb375a2 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -103,8 +103,8 @@ void __init msm_map_qsd8x50_io(void)
103 103
104#ifdef CONFIG_ARCH_MSM8X60 104#ifdef CONFIG_ARCH_MSM8X60
105static struct map_desc msm8x60_io_desc[] __initdata = { 105static struct map_desc msm8x60_io_desc[] __initdata = {
106 MSM_DEVICE(QGIC_DIST), 106 MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
107 MSM_DEVICE(QGIC_CPU), 107 MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
108 MSM_CHIP_DEVICE(TMR, MSM8X60), 108 MSM_CHIP_DEVICE(TMR, MSM8X60),
109 MSM_CHIP_DEVICE(TMR0, MSM8X60), 109 MSM_CHIP_DEVICE(TMR0, MSM8X60),
110 MSM_DEVICE(ACC), 110 MSM_DEVICE(ACC),