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authorFabio Estevam <fabio.estevam@freescale.com>2013-06-09 21:07:47 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-07-15 10:28:52 -0400
commit84bb08472520882394fe16d7a3548793302563de (patch)
treebb951caf06a634a0575af0dbe2705f836abda718 /arch
parent15968f1bd4341cfa54023348a4e0b94798211742 (diff)
ARM: dts: imx51-babbage: Pass a real clock to the codec
On imx51_babbage the codec clock is activated via GPIO4_26. Provide a real clock to the sgtl5000 codec via device tree. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 6dd9486c755b..ad3471ca17c7 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -61,6 +61,16 @@
61 mux-int-port = <2>; 61 mux-int-port = <2>;
62 mux-ext-port = <3>; 62 mux-ext-port = <3>;
63 }; 63 };
64
65 clocks {
66 clk_26M: codec_clock {
67 compatible = "fixed-clock";
68 reg=<0>;
69 #clock-cells = <0>;
70 clock-frequency = <26000000>;
71 gpios = <&gpio4 26 1>;
72 };
73 };
64}; 74};
65 75
66&esdhc1 { 76&esdhc1 {
@@ -229,6 +239,7 @@
229 MX51_PAD_EIM_A27__GPIO2_21 0x5 239 MX51_PAD_EIM_A27__GPIO2_21 0x5
230 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 240 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
231 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 241 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
242 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
232 >; 243 >;
233 }; 244 };
234 }; 245 };
@@ -255,7 +266,7 @@
255 sgtl5000: codec@0a { 266 sgtl5000: codec@0a {
256 compatible = "fsl,sgtl5000"; 267 compatible = "fsl,sgtl5000";
257 reg = <0x0a>; 268 reg = <0x0a>;
258 clock-frequency = <26000000>; 269 clocks = <&clk_26M>;
259 VDDA-supply = <&vdig_reg>; 270 VDDA-supply = <&vdig_reg>;
260 VDDIO-supply = <&vvideo_reg>; 271 VDDIO-supply = <&vvideo_reg>;
261 }; 272 };