Merge branch 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
  ARM: mach-shmobile: AG5EVM LCDC / MIPI-DSI platform data
  ARM: mach-shmobile: sh73a0 CPGA fix for PLL CFG bit
  ARM: mach-shmobile: mackerel: clarify shdi/mmcif switch settings
  ARM: mach-shmobile: sh73a0 CPGA fix for IrDA MSTP
  ARM: mach-shmobile: sh73a0 CPGA fix for FRQCRA M3
  ARM: mach-shmobile: remove sh7367 on-chip set_irq_type()
  ARM: mach-shmobile: sh7372 INTCS MFIS2 interrupt update
  ARM: mach-shmobile: ag5evm: Add IrDA support
  ARM: mach-shmobile: clock-sh7372: fixup pllc2 set_rate
  mmc: sh_mmcif: Convert to __raw_xxx() I/O accessors.
  ARM: mach-shmobile: ag5evm requires GPIOLIB
  ARM: mach-shmobile: fix cpu_base of gic_init() on sh73a0

8 files changed, 220 insertions, 17 deletions

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4d1b4c5c9389..0c8f6cf3e948 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -60,6 +60,8 @@ endchoice
 
 config MACH_AG5EVM
         bool "AG5EVM board"
+        select ARCH_REQUIRE_GPIOLIB
+        select SH_LCD_MIPI_DSI
         depends on ARCH_SH73A0
 
 config MACH_MACKEREL
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index c18a740a4159..2123b96b5638 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -34,9 +34,10 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
-
+#include <linux/sh_clk.h>
+#include <video/sh_mobile_lcdc.h>
+#include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
-
 #include <mach/hardware.h>
 #include <mach/sh73a0.h>
 #include <mach/common.h>
@@ -183,11 +184,165 @@ static struct platform_device mmc_device = {
         .resource       = sh_mmcif_resources,
 };
 
+/* IrDA */
+static struct resource irda_resources[] = {
+        [0] = {
+                .start  = 0xE6D00000,
+                .end    = 0xE6D01FD4 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(95),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device irda_device = {
+        .name           = "sh_irda",
+        .id             = 0,
+        .resource       = irda_resources,
+        .num_resources  = ARRAY_SIZE(irda_resources),
+};
+
+static unsigned char lcd_backlight_seq[3][2] = {
+        { 0x04, 0x07 },
+        { 0x23, 0x80 },
+        { 0x03, 0x01 },
+};
+
+static void lcd_backlight_on(void)
+{
+        struct i2c_adapter *a;
+        struct i2c_msg msg;
+        int k;
+
+        a = i2c_get_adapter(1);
+        for (k = 0; a && k < 3; k++) {
+                msg.addr = 0x6d;
+                msg.buf = &lcd_backlight_seq[k][0];
+                msg.len = 2;
+                msg.flags = 0;
+                if (i2c_transfer(a, &msg, 1) != 1)
+                        break;
+        }
+}
+
+static void lcd_backlight_reset(void)
+{
+        gpio_set_value(GPIO_PORT235, 0);
+        mdelay(24);
+        gpio_set_value(GPIO_PORT235, 1);
+}
+
+static void lcd_on(void *board_data, struct fb_info *info)
+{
+        lcd_backlight_on();
+}
+
+static void lcd_off(void *board_data)
+{
+        lcd_backlight_reset();
+}
+
+/* LCDC0 */
+static const struct fb_videomode lcdc0_modes[] = {
+        {
+                .name           = "R63302(QHD)",
+                .xres           = 544,
+                .yres           = 961,
+                .left_margin    = 72,
+                .right_margin   = 600,
+                .hsync_len      = 16,
+                .upper_margin   = 8,
+                .lower_margin   = 8,
+                .vsync_len      = 2,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+        },
+};
+
+static struct sh_mobile_lcdc_info lcdc0_info = {
+        .clock_source = LCDC_CLK_PERIPHERAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .interface_type = RGB24,
+                .clock_divider = 1,
+                .flags = LCDC_FLAGS_DWPOL,
+                .lcd_size_cfg.width = 44,
+                .lcd_size_cfg.height = 79,
+                .bpp = 16,
+                .lcd_cfg = lcdc0_modes,
+                .num_cfg = ARRAY_SIZE(lcdc0_modes),
+                .board_cfg = {
+                        .display_on = lcd_on,
+                        .display_off = lcd_off,
+                },
+        }
+};
+
+static struct resource lcdc0_resources[] = {
+        [0] = {
+                .name   = "LCDC0",
+                .start  = 0xfe940000, /* P4-only space */
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc0_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc0_resources),
+        .resource       = lcdc0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &lcdc0_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+/* MIPI-DSI */
+static struct resource mipidsi0_resources[] = {
+        [0] = {
+                .start  = 0xfeab0000,
+                .end    = 0xfeab3fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xfeab4000,
+                .end    = 0xfeab7fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct sh_mipi_dsi_info mipidsi0_info = {
+        .data_format    = MIPI_RGB888,
+        .lcd_chan       = &lcdc0_info.ch[0],
+        .vsynw_offset   = 20,
+        .clksrc         = 1,
+        .flags          = SH_MIPI_DSI_HSABM,
+};
+
+static struct platform_device mipidsi0_device = {
+        .name           = "sh-mipi-dsi",
+        .num_resources  = ARRAY_SIZE(mipidsi0_resources),
+        .resource       = mipidsi0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &mipidsi0_info,
+        },
+};
+
 static struct platform_device *ag5evm_devices[] __initdata = {
         &eth_device,
         &keysc_device,
         &fsi_device,
         &mmc_device,
+        &irda_device,
+        &lcdc0_device,
+        &mipidsi0_device,
 };
 
 static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -224,6 +379,8 @@ void __init ag5evm_init_irq(void)
         __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
 }
 
+#define DSI0PHYCR       0xe615006c
+
 static void __init ag5evm_init(void)
 {
         sh73a0_pinmux_init();
@@ -287,6 +444,25 @@ static void __init ag5evm_init(void)
         gpio_request(GPIO_FN_FSIAISLD, NULL);
         gpio_request(GPIO_FN_FSIAOSLD, NULL);
 
+        /* IrDA */
+        gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
+        gpio_request(GPIO_FN_PORT242_IRDA_IN,  NULL);
+        gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
+
+        /* LCD panel */
+        gpio_request(GPIO_PORT217, NULL); /* RESET */
+        gpio_direction_output(GPIO_PORT217, 0);
+        mdelay(1);
+        gpio_set_value(GPIO_PORT217, 1);
+
+        /* LCD backlight controller */
+        gpio_request(GPIO_PORT235, NULL); /* RESET */
+        gpio_direction_output(GPIO_PORT235, 0);
+        lcd_backlight_reset();
+
+        /* MIPI-DSI clock setup */
+        __raw_writel(0x2a809010, DSI0PHYCR);
+
 #ifdef CONFIG_CACHE_L2X0
         /* Shared attribute override enable, 64K*8way */
         l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 686b304a7708..ef4613b993a2 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -347,7 +347,6 @@ static void __init g3evm_init(void)
         gpio_request(GPIO_FN_IRDA_OUT, NULL);
         gpio_request(GPIO_FN_IRDA_IN, NULL);
         gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
-        set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
 
         sh7367_add_standard_devices();
 
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7b15d21f0f68..fb4213a4e15a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -169,9 +169,8 @@
  *      SW1     |       SW33
  *              | bit1 | bit2 | bit3 | bit4
  * -------------+------+------+------+-------
- * MMC0   OFF   |  OFF |  ON  |  ON  |  X
- * MMC1   ON    |  OFF |  ON  |  X   | ON
- * SDHI1  OFF   |  ON  |   X  |  OFF | ON
+ * MMC0   OFF   |  OFF |   X  |  ON  |  X       (Use MMCIF)
+ * SDHI1  OFF   |  ON  |   X  |  OFF |  X       (Use MFD_SH_MOBILE_SDHI)
  *
  */
 
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 9aa8d68d1a9c..e9731b5a73ed 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -234,7 +234,9 @@ static int pllc2_set_rate(struct clk *clk, unsigned long rate)
 
         value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
 
-        __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
+        __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
+
+        clk->rate = clk->freq_table[idx].frequency;
 
         return 0;
 }
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 720a71433be6..ddd4a1b775f0 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
 {
         unsigned long mult = 1;
 
-        if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+        if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
                 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+                /* handle CFG bit for PLL1 and PLL2 */
+                switch (clk->enable_bit) {
+                case 1:
+                case 2:
+                        if (__raw_readl(clk->enable_reg) & (1 << 20))
+                                mult *= 2;
+                }
+        }
 
         return clk->parent->rate * mult;
 }
@@ -212,7 +220,7 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
         [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
-        [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
         [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
         [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
@@ -255,10 +263,10 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 
 enum { MSTP001,
-        MSTP125, MSTP116,
+        MSTP125, MSTP118, MSTP116, MSTP100,
         MSTP219,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP331, MSTP329, MSTP323, MSTP312,
+        MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
         MSTP411, MSTP410, MSTP403,
         MSTP_NR };
 
@@ -268,7 +276,9 @@ enum { MSTP001,
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+        [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
         [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
@@ -279,6 +289,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
         [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
         [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
         [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
@@ -288,16 +299,25 @@ static struct clk mstp_clks[MSTP_NR] = {
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
         /* main clocks */
         CLKDEV_CON_ID("r_clk", &r_clk),
 
+        /* DIV6 clocks */
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
@@ -308,6 +328,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index f78a1ead71a5..ca5f9d17b39a 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -365,6 +365,7 @@ static struct intc_desc intca_desc __initdata = {
 
 enum {
         UNUSED_INTCS = 0,
+        ENABLED_INTCS,
 
         INTCS,
 
@@ -413,7 +414,7 @@ enum {
         CMT4,
         DSITX1_DSITX1_0,
         DSITX1_DSITX1_1,
-        /* MFIS2 */
+        MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
         CPORTS2R,
         /* CEC */
         JPU6E,
@@ -477,7 +478,7 @@ static struct intc_vect intcs_vectors[] = {
         INTCS_VECT(CMT4, 0x1980),
         INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
         INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
-        /* MFIS2 */
+        INTCS_VECT(MFIS2_INTCS, 0x1a00),
         INTCS_VECT(CPORTS2R, 0x1a20),
         /* CEC */
         INTCS_VECT(JPU6E, 0x1a80),
@@ -543,7 +544,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
             CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
         { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
-          { 0, CPORTS2R, 0, 0,
+          { MFIS2_INTCS, CPORTS2R, 0, 0,
             JPU6E, 0, 0, 0 } },
         { 0xffd20104, 0, 16, /* INTAMASK */
           { 0, 0, 0, 0, 0, 0, 0, 0,
@@ -571,7 +572,8 @@ static struct intc_prio_reg intcs_prio_registers[] = {
         { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
         { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
                                                DSITX1_DSITX1_1, 0 } },
-        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
+        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
+                                               0, 0 } },
         { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
 };
 
@@ -590,6 +592,7 @@ static struct resource intcs_resources[] __initdata = {
 
 static struct intc_desc intcs_desc __initdata = {
         .name = "sh7372-intcs",
+        .force_enable = ENABLED_INTCS,
         .resource = intcs_resources,
         .num_resources = ARRAY_SIZE(intcs_resources),
         .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 322d8d57cbcf..5d0e1503ece6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,10 +252,11 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
 
 void __init sh73a0_init_irq(void)
 {
-        void __iomem *gic_base = __io(0xf0001000);
+        void __iomem *gic_dist_base = __io(0xf0001000);
+        void __iomem *gic_cpu_base = __io(0xf0000100);
         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 
-        gic_init(0, 29, gic_base, gic_base);
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
 
         register_intc_controller(&intcs_desc);