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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:56:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:56:08 -0500
commit7e21774db5cc9cf8fe93a64a2f0c6cf47db8ab24 (patch)
tree460812792bc3b23789a83968b7bad840cc3eb047 /arch
parent0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3 (diff)
parent2e84d75116c17c2034e917b411250d2d11755435 (diff)
Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts1
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts1
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi1
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi4
-rw-r--r--arch/arm/include/asm/clkdev.h2
-rw-r--r--arch/blackfin/include/asm/clkdev.h2
-rw-r--r--arch/mips/include/asm/clkdev.h2
-rw-r--r--arch/sh/include/asm/clkdev.h2
9 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 8aad5f72ced7..9804fcb71f8c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -116,6 +116,7 @@
116 max77686: pmic@09 { 116 max77686: pmic@09 {
117 compatible = "maxim,max77686"; 117 compatible = "maxim,max77686";
118 reg = <0x09>; 118 reg = <0x09>;
119 #clock-cells = <1>;
119 120
120 voltage-regulators { 121 voltage-regulators {
121 ldo1_reg: LDO1 { 122 ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 890ad275cb85..4f851ccf40eb 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -139,6 +139,7 @@
139 interrupt-parent = <&gpx0>; 139 interrupt-parent = <&gpx0>;
140 interrupts = <7 0>; 140 interrupts = <7 0>;
141 reg = <0x09>; 141 reg = <0x09>;
142 #clock-cells = <1>;
142 143
143 voltage-regulators { 144 voltage-regulators {
144 ldo1_reg: ldo1 { 145 ldo1_reg: ldo1 {
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 9a61494f45f5..2c1560d52f1a 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -49,6 +49,7 @@
49 pinctrl-0 = <&max77686_irq>; 49 pinctrl-0 = <&max77686_irq>;
50 wakeup-source; 50 wakeup-source;
51 reg = <0x09>; 51 reg = <0x09>;
52 #clock-cells = <1>;
52 53
53 voltage-regulators { 54 voltage-regulators {
54 ldo1_reg: LDO1 { 55 ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 587dd3e36f6c..b7dec41e32af 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -90,6 +90,8 @@
90 compatible = "samsung,exynos5250-audss-clock"; 90 compatible = "samsung,exynos5250-audss-clock";
91 reg = <0x03810000 0x0C>; 91 reg = <0x03810000 0x0C>;
92 #clock-cells = <1>; 92 #clock-cells = <1>;
93 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
94 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
93 }; 95 };
94 96
95 timer { 97 timer {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 11dd202c54bb..8db792b26f79 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -119,8 +119,8 @@
119 compatible = "samsung,exynos5420-audss-clock"; 119 compatible = "samsung,exynos5420-audss-clock";
120 reg = <0x03810000 0x0C>; 120 reg = <0x03810000 0x0C>;
121 #clock-cells = <1>; 121 #clock-cells = <1>;
122 clocks = <&clock 148>; 122 clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
123 clock-names = "sclk_audio"; 123 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
124 }; 124 };
125 125
126 codec@11000000 { 126 codec@11000000 {
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 80751c15c300..4e8a4b27d7c7 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -14,12 +14,14 @@
14 14
15#include <linux/slab.h> 15#include <linux/slab.h>
16 16
17#ifndef CONFIG_COMMON_CLK
17#ifdef CONFIG_HAVE_MACH_CLKDEV 18#ifdef CONFIG_HAVE_MACH_CLKDEV
18#include <mach/clkdev.h> 19#include <mach/clkdev.h>
19#else 20#else
20#define __clk_get(clk) ({ 1; }) 21#define __clk_get(clk) ({ 1; })
21#define __clk_put(clk) do { } while (0) 22#define __clk_put(clk) do { } while (0)
22#endif 23#endif
24#endif
23 25
24static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) 26static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
25{ 27{
diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
index 9053beda8c50..7ac2436856a5 100644
--- a/arch/blackfin/include/asm/clkdev.h
+++ b/arch/blackfin/include/asm/clkdev.h
@@ -8,7 +8,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
8 return kzalloc(size, GFP_KERNEL); 8 return kzalloc(size, GFP_KERNEL);
9} 9}
10 10
11#ifndef CONFIG_COMMON_CLK
11#define __clk_put(clk) 12#define __clk_put(clk)
12#define __clk_get(clk) ({ 1; }) 13#define __clk_get(clk) ({ 1; })
14#endif
13 15
14#endif 16#endif
diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
index 262475414e5f..1b3ad7b09dc1 100644
--- a/arch/mips/include/asm/clkdev.h
+++ b/arch/mips/include/asm/clkdev.h
@@ -14,8 +14,10 @@
14 14
15#include <linux/slab.h> 15#include <linux/slab.h>
16 16
17#ifndef CONFIG_COMMON_CLK
17#define __clk_get(clk) ({ 1; }) 18#define __clk_get(clk) ({ 1; })
18#define __clk_put(clk) do { } while (0) 19#define __clk_put(clk) do { } while (0)
20#endif
19 21
20static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) 22static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
21{ 23{
diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h
index 6ba91868201c..c41901465fb0 100644
--- a/arch/sh/include/asm/clkdev.h
+++ b/arch/sh/include/asm/clkdev.h
@@ -25,7 +25,9 @@ static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
25 return kzalloc(size, GFP_KERNEL); 25 return kzalloc(size, GFP_KERNEL);
26} 26}
27 27
28#ifndef CONFIG_COMMON_CLK
28#define __clk_put(clk) 29#define __clk_put(clk)
29#define __clk_get(clk) ({ 1; }) 30#define __clk_get(clk) ({ 1; })
31#endif
30 32
31#endif /* __CLKDEV_H__ */ 33#endif /* __CLKDEV_H__ */