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authorKukjin Kim <kgene.kim@samsung.com>2011-02-14 02:33:10 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-02-21 23:51:14 -0500
commit7d30e8b3815f804139271dfc31962ab74ce89650 (patch)
tree711d4830705e0147cb8184ca1a8e6e3c97bc02fe /arch
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
ARM: EXYNOS4: Add EXYNOS4 CPU initialization support
This patch adds EXYNOS4 CPU support files in mach-exynos4, and basically they are moved from mach-s5pv310 so that it can support Samsung's new CPU name, EXYNOS4. The EXYNOS4 ingegrates a ARM Cortex A9 multi-core. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos4/cpu.c (renamed from arch/arm/mach-s5pv310/cpu.c)87
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c (renamed from arch/arm/mach-s5pv310/cpufreq.c)100
-rw-r--r--arch/arm/mach-exynos4/dma.c (renamed from arch/arm/mach-s5pv310/dma.c)50
-rw-r--r--arch/arm/mach-exynos4/gpiolib.c (renamed from arch/arm/mach-s5pv310/gpiolib.c)154
-rw-r--r--arch/arm/mach-exynos4/headsmp.S (renamed from arch/arm/mach-s5pv310/headsmp.S)6
-rw-r--r--arch/arm/mach-exynos4/hotplug.c (renamed from arch/arm/mach-s5pv310/hotplug.c)2
-rw-r--r--arch/arm/mach-exynos4/include/mach/debug-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/debug-macro.S)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/dma.h (renamed from arch/arm/mach-s5pv310/include/mach/dma.h)0
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/entry-macro.S)4
-rw-r--r--arch/arm/mach-exynos4/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-exynos4/include/mach/hardware.h (renamed from arch/arm/mach-s5pv310/include/mach/hardware.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/io.h (renamed from arch/arm/mach-s5pv310/include/mach/io.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h144
-rw-r--r--arch/arm/mach-exynos4/include/mach/memory.h (renamed from arch/arm/mach-s5pv310/include/mach/memory.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mem.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-mem.h)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-pmu.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-sysmmu.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/smp.h (renamed from arch/arm/mach-s5pv310/include/mach/smp.h)2
-rw-r--r--arch/arm/mach-exynos4/include/mach/sysmmu.h (renamed from arch/arm/mach-s5pv310/include/mach/sysmmu.h)18
-rw-r--r--arch/arm/mach-exynos4/include/mach/system.h (renamed from arch/arm/mach-s5pv310/include/mach/system.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/timex.h (renamed from arch/arm/mach-s5pv310/include/mach/timex.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/uncompress.h (renamed from arch/arm/mach-s5pv310/include/mach/uncompress.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/vmalloc.h (renamed from arch/arm/mach-s5pv310/include/mach/vmalloc.h)8
-rw-r--r--arch/arm/mach-exynos4/init.c (renamed from arch/arm/mach-s5pv310/init.c)10
-rw-r--r--arch/arm/mach-exynos4/platsmp.c (renamed from arch/arm/mach-s5pv310/platsmp.c)12
-rw-r--r--arch/arm/mach-exynos4/setup-i2c0.c (renamed from arch/arm/mach-s5pv310/setup-i2c0.c)4
-rw-r--r--arch/arm/mach-s5pv310/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/plat-s5p/cpu.c25
-rw-r--r--arch/arm/plat-s5p/include/plat/exynos4.h34
-rw-r--r--arch/arm/plat-s5p/include/plat/s5pv310.h34
33 files changed, 637 insertions, 629 deletions
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0db0fb65bd70..b0ec6d3d3774 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/cpu.c 1/* linux/arch/arm/mach-exynos4/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
19 19
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/clock.h> 21#include <plat/clock.h>
22#include <plat/s5pv310.h> 22#include <plat/exynos4.h>
23#include <plat/sdhci.h> 23#include <plat/sdhci.h>
24 24
25#include <mach/regs-irq.h> 25#include <mach/regs-irq.h>
@@ -29,55 +29,55 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); 29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
30 30
31/* Initial IO mappings */ 31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = { 32static struct map_desc exynos4_iodesc[] __initdata = {
33 { 33 {
34 .virtual = (unsigned long)S5P_VA_SYSRAM, 34 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), 35 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
36 .length = SZ_4K, 36 .length = SZ_4K,
37 .type = MT_DEVICE, 37 .type = MT_DEVICE,
38 }, { 38 }, {
39 .virtual = (unsigned long)S5P_VA_CMU, 39 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU), 40 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
41 .length = SZ_128K, 41 .length = SZ_128K,
42 .type = MT_DEVICE, 42 .type = MT_DEVICE,
43 }, { 43 }, {
44 .virtual = (unsigned long)S5P_VA_PMU, 44 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU), 45 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
46 .length = SZ_64K, 46 .length = SZ_64K,
47 .type = MT_DEVICE, 47 .type = MT_DEVICE,
48 }, { 48 }, {
49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), 50 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
51 .length = SZ_4K, 51 .length = SZ_4K,
52 .type = MT_DEVICE, 52 .type = MT_DEVICE,
53 }, { 53 }, {
54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
55 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), 55 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
56 .length = SZ_8K, 56 .length = SZ_8K,
57 .type = MT_DEVICE, 57 .type = MT_DEVICE,
58 }, { 58 }, {
59 .virtual = (unsigned long)S5P_VA_L2CC, 59 .virtual = (unsigned long)S5P_VA_L2CC,
60 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 60 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
61 .length = SZ_4K, 61 .length = SZ_4K,
62 .type = MT_DEVICE, 62 .type = MT_DEVICE,
63 }, { 63 }, {
64 .virtual = (unsigned long)S5P_VA_GPIO1, 64 .virtual = (unsigned long)S5P_VA_GPIO1,
65 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1), 65 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
66 .length = SZ_4K, 66 .length = SZ_4K,
67 .type = MT_DEVICE, 67 .type = MT_DEVICE,
68 }, { 68 }, {
69 .virtual = (unsigned long)S5P_VA_GPIO2, 69 .virtual = (unsigned long)S5P_VA_GPIO2,
70 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2), 70 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
71 .length = SZ_4K, 71 .length = SZ_4K,
72 .type = MT_DEVICE, 72 .type = MT_DEVICE,
73 }, { 73 }, {
74 .virtual = (unsigned long)S5P_VA_GPIO3, 74 .virtual = (unsigned long)S5P_VA_GPIO3,
75 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3), 75 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
76 .length = SZ_256, 76 .length = SZ_256,
77 .type = MT_DEVICE, 77 .type = MT_DEVICE,
78 }, { 78 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0, 79 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0), 80 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
81 .length = SZ_4K, 81 .length = SZ_4K,
82 .type = MT_DEVICE, 82 .type = MT_DEVICE,
83 }, { 83 }, {
@@ -87,13 +87,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
87 .type = MT_DEVICE, 87 .type = MT_DEVICE,
88 }, { 88 }, {
89 .virtual = (unsigned long)S5P_VA_SROMC, 89 .virtual = (unsigned long)S5P_VA_SROMC,
90 .pfn = __phys_to_pfn(S5PV310_PA_SROMC), 90 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
91 .length = SZ_4K, 91 .length = SZ_4K,
92 .type = MT_DEVICE, 92 .type = MT_DEVICE,
93 }, 93 },
94}; 94};
95 95
96static void s5pv310_idle(void) 96static void exynos4_idle(void)
97{ 97{
98 if (!need_resched()) 98 if (!need_resched())
99 cpu_do_idle(); 99 cpu_do_idle();
@@ -101,32 +101,33 @@ static void s5pv310_idle(void)
101 local_irq_enable(); 101 local_irq_enable();
102} 102}
103 103
104/* s5pv310_map_io 104/*
105 * exynos4_map_io
105 * 106 *
106 * register the standard cpu IO areas 107 * register the standard cpu IO areas
107*/ 108 */
108void __init s5pv310_map_io(void) 109void __init exynos4_map_io(void)
109{ 110{
110 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); 111 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
111 112
112 /* initialize device information early */ 113 /* initialize device information early */
113 s5pv310_default_sdhci0(); 114 exynos4_default_sdhci0();
114 s5pv310_default_sdhci1(); 115 exynos4_default_sdhci1();
115 s5pv310_default_sdhci2(); 116 exynos4_default_sdhci2();
116 s5pv310_default_sdhci3(); 117 exynos4_default_sdhci3();
117} 118}
118 119
119void __init s5pv310_init_clocks(int xtal) 120void __init exynos4_init_clocks(int xtal)
120{ 121{
121 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 122 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
122 123
123 s3c24xx_register_baseclocks(xtal); 124 s3c24xx_register_baseclocks(xtal);
124 s5p_register_clocks(xtal); 125 s5p_register_clocks(xtal);
125 s5pv310_register_clocks(); 126 exynos4_register_clocks();
126 s5pv310_setup_clocks(); 127 exynos4_setup_clocks();
127} 128}
128 129
129void __init s5pv310_init_irq(void) 130void __init exynos4_init_irq(void)
130{ 131{
131 int irq; 132 int irq;
132 133
@@ -148,29 +149,29 @@ void __init s5pv310_init_irq(void)
148 } 149 }
149 150
150 /* The parameters of s5p_init_irq() are for VIC init. 151 /* The parameters of s5p_init_irq() are for VIC init.
151 * Theses parameters should be NULL and 0 because S5PV310 152 * Theses parameters should be NULL and 0 because EXYNOS4
152 * uses GIC instead of VIC. 153 * uses GIC instead of VIC.
153 */ 154 */
154 s5p_init_irq(NULL, 0); 155 s5p_init_irq(NULL, 0);
155} 156}
156 157
157struct sysdev_class s5pv310_sysclass = { 158struct sysdev_class exynos4_sysclass = {
158 .name = "s5pv310-core", 159 .name = "exynos4-core",
159}; 160};
160 161
161static struct sys_device s5pv310_sysdev = { 162static struct sys_device exynos4_sysdev = {
162 .cls = &s5pv310_sysclass, 163 .cls = &exynos4_sysclass,
163}; 164};
164 165
165static int __init s5pv310_core_init(void) 166static int __init exynos4_core_init(void)
166{ 167{
167 return sysdev_class_register(&s5pv310_sysclass); 168 return sysdev_class_register(&exynos4_sysclass);
168} 169}
169 170
170core_initcall(s5pv310_core_init); 171core_initcall(exynos4_core_init);
171 172
172#ifdef CONFIG_CACHE_L2X0 173#ifdef CONFIG_CACHE_L2X0
173static int __init s5pv310_l2x0_cache_init(void) 174static int __init exynos4_l2x0_cache_init(void)
174{ 175{
175 /* TAG, Data Latency Control: 2cycle */ 176 /* TAG, Data Latency Control: 2cycle */
176 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 177 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -188,15 +189,15 @@ static int __init s5pv310_l2x0_cache_init(void)
188 return 0; 189 return 0;
189} 190}
190 191
191early_initcall(s5pv310_l2x0_cache_init); 192early_initcall(exynos4_l2x0_cache_init);
192#endif 193#endif
193 194
194int __init s5pv310_init(void) 195int __init exynos4_init(void)
195{ 196{
196 printk(KERN_INFO "S5PV310: Initializing architecture\n"); 197 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
197 198
198 /* set idle function */ 199 /* set idle function */
199 pm_idle = s5pv310_idle; 200 pm_idle = exynos4_idle;
200 201
201 return sysdev_register(&s5pv310_sysdev); 202 return sysdev_register(&exynos4_sysdev);
202} 203}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
index b04cbc731128..174f080b500d 100644
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ b/arch/arm/mach-exynos4/cpufreq.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c 1/* linux/arch/arm/mach-exynos4/cpufreq.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - CPU frequency scaling support 6 * EXYNOS4 - CPU frequency scaling support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -39,7 +39,7 @@ static struct regulator *int_regulator;
39static struct cpufreq_freqs freqs; 39static struct cpufreq_freqs freqs;
40static unsigned int memtype; 40static unsigned int memtype;
41 41
42enum s5pv310_memory_type { 42enum exynos4_memory_type {
43 DDR2 = 4, 43 DDR2 = 4,
44 LPDDR2, 44 LPDDR2,
45 DDR3, 45 DDR3,
@@ -49,7 +49,7 @@ enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END, 49 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50}; 50};
51 51
52static struct cpufreq_frequency_table s5pv310_freq_table[] = { 52static struct cpufreq_frequency_table exynos4_freq_table[] = {
53 {L0, 1000*1000}, 53 {L0, 1000*1000},
54 {L1, 800*1000}, 54 {L1, 800*1000},
55 {L2, 400*1000}, 55 {L2, 400*1000},
@@ -160,7 +160,7 @@ struct cpufreq_voltage_table {
160 unsigned int int_volt; 160 unsigned int int_volt;
161}; 161};
162 162
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { 163static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
164 { 164 {
165 .index = L0, 165 .index = L0,
166 .arm_volt = 1200000, 166 .arm_volt = 1200000,
@@ -180,7 +180,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
180 }, 180 },
181}; 181};
182 182
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { 183static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */ 184 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1), 185 ((250 << 16) | (6 << 8) | 1),
186 186
@@ -194,17 +194,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
194 ((200 << 16) | (6 << 8) | 4), 194 ((200 << 16) | (6 << 8) | 4),
195}; 195};
196 196
197int s5pv310_verify_speed(struct cpufreq_policy *policy) 197int exynos4_verify_speed(struct cpufreq_policy *policy)
198{ 198{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); 199 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
200} 200}
201 201
202unsigned int s5pv310_getspeed(unsigned int cpu) 202unsigned int exynos4_getspeed(unsigned int cpu)
203{ 203{
204 return clk_get_rate(cpu_clk) / 1000; 204 return clk_get_rate(cpu_clk) / 1000;
205} 205}
206 206
207void s5pv310_set_clkdiv(unsigned int div_index) 207void exynos4_set_clkdiv(unsigned int div_index)
208{ 208{
209 unsigned int tmp; 209 unsigned int tmp;
210 210
@@ -321,7 +321,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
321 } while (tmp & 0x11); 321 } while (tmp & 0x11);
322} 322}
323 323
324static void s5pv310_set_apll(unsigned int index) 324static void exynos4_set_apll(unsigned int index)
325{ 325{
326 unsigned int tmp; 326 unsigned int tmp;
327 327
@@ -340,7 +340,7 @@ static void s5pv310_set_apll(unsigned int index)
340 /* 3. Change PLL PMS values */ 340 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0); 341 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index]; 343 tmp |= exynos4_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0); 344 __raw_writel(tmp, S5P_APLL_CON0);
345 345
346 /* 4. wait_lock_time */ 346 /* 4. wait_lock_time */
@@ -357,77 +357,77 @@ static void s5pv310_set_apll(unsigned int index)
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); 357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358} 358}
359 359
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) 360static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
361{ 361{
362 unsigned int tmp; 362 unsigned int tmp;
363 363
364 if (old_index > new_index) { 364 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */ 365 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) { 366 if (freqs.new == exynos4_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */ 367 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index); 368 exynos4_set_clkdiv(new_index);
369 369
370 /* 2. Change the apll m,p,s value */ 370 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index); 371 exynos4_set_apll(new_index);
372 } else { 372 } else {
373 /* 1. Change the system clock divider values */ 373 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index); 374 exynos4_set_clkdiv(new_index);
375 375
376 /* 2. Change just s value in apll m,p,s value */ 376 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0); 377 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0); 378 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 379 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0); 380 __raw_writel(tmp, S5P_APLL_CON0);
381 } 381 }
382 } 382 }
383 383
384 else if (old_index < new_index) { 384 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */ 385 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) { 386 if (freqs.old == exynos4_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */ 387 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index); 388 exynos4_set_apll(new_index);
389 389
390 /* 2. Change the system clock divider values */ 390 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index); 391 exynos4_set_clkdiv(new_index);
392 } else { 392 } else {
393 /* 1. Change just s value in apll m,p,s value */ 393 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0); 394 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0); 395 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 396 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0); 397 __raw_writel(tmp, S5P_APLL_CON0);
398 398
399 /* 2. Change the system clock divider values */ 399 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index); 400 exynos4_set_clkdiv(new_index);
401 } 401 }
402 } 402 }
403} 403}
404 404
405static int s5pv310_target(struct cpufreq_policy *policy, 405static int exynos4_target(struct cpufreq_policy *policy,
406 unsigned int target_freq, 406 unsigned int target_freq,
407 unsigned int relation) 407 unsigned int relation)
408{ 408{
409 unsigned int index, old_index; 409 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt; 410 unsigned int arm_volt, int_volt;
411 411
412 freqs.old = s5pv310_getspeed(policy->cpu); 412 freqs.old = exynos4_getspeed(policy->cpu);
413 413
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 414 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
415 freqs.old, relation, &old_index)) 415 freqs.old, relation, &old_index))
416 return -EINVAL; 416 return -EINVAL;
417 417
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 418 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
419 target_freq, relation, &index)) 419 target_freq, relation, &index))
420 return -EINVAL; 420 return -EINVAL;
421 421
422 freqs.new = s5pv310_freq_table[index].frequency; 422 freqs.new = exynos4_freq_table[index].frequency;
423 freqs.cpu = policy->cpu; 423 freqs.cpu = policy->cpu;
424 424
425 if (freqs.new == freqs.old) 425 if (freqs.new == freqs.old)
426 return 0; 426 return 0;
427 427
428 /* get the voltage value */ 428 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt; 429 arm_volt = exynos4_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt; 430 int_volt = exynos4_volt_table[index].int_volt;
431 431
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433 433
@@ -441,7 +441,7 @@ static int s5pv310_target(struct cpufreq_policy *policy,
441 } 441 }
442 442
443 /* Clock Configuration Procedure */ 443 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index); 444 exynos4_set_frequency(old_index, index);
445 445
446 /* control regulator */ 446 /* control regulator */
447 if (freqs.new < freqs.old) { 447 if (freqs.new < freqs.old) {
@@ -458,52 +458,52 @@ static int s5pv310_target(struct cpufreq_policy *policy,
458} 458}
459 459
460#ifdef CONFIG_PM 460#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, 461static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg) 462 pm_message_t pmsg)
463{ 463{
464 return 0; 464 return 0;
465} 465}
466 466
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) 467static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
468{ 468{
469 return 0; 469 return 0;
470} 470}
471#endif 471#endif
472 472
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) 473static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{ 474{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); 475 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
476 476
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); 477 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
478 478
479 /* set the transition latency value */ 479 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000; 480 policy->cpuinfo.transition_latency = 100000;
481 481
482 /* 482 /*
483 * S5PV310 multi-core processors has 2 cores 483 * EXYNOS4 multi-core processors has 2 cores
484 * that the frequency cannot be set independently. 484 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed. 485 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus. 486 * So the affected cpu is all of the cpus.
487 */ 487 */
488 cpumask_setall(policy->cpus); 488 cpumask_setall(policy->cpus);
489 489
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); 490 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
491} 491}
492 492
493static struct cpufreq_driver s5pv310_driver = { 493static struct cpufreq_driver exynos4_driver = {
494 .flags = CPUFREQ_STICKY, 494 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed, 495 .verify = exynos4_verify_speed,
496 .target = s5pv310_target, 496 .target = exynos4_target,
497 .get = s5pv310_getspeed, 497 .get = exynos4_getspeed,
498 .init = s5pv310_cpufreq_cpu_init, 498 .init = exynos4_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq", 499 .name = "exynos4_cpufreq",
500#ifdef CONFIG_PM 500#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend, 501 .suspend = exynos4_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume, 502 .resume = exynos4_cpufreq_resume,
503#endif 503#endif
504}; 504};
505 505
506static int __init s5pv310_cpufreq_init(void) 506static int __init exynos4_cpufreq_init(void)
507{ 507{
508 cpu_clk = clk_get(NULL, "armclk"); 508 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk)) 509 if (IS_ERR(cpu_clk))
@@ -550,7 +550,7 @@ static int __init s5pv310_cpufreq_init(void)
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); 550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 } 551 }
552 552
553 return cpufreq_register_driver(&s5pv310_driver); 553 return cpufreq_register_driver(&exynos4_driver);
554 554
555out: 555out:
556 if (!IS_ERR(cpu_clk)) 556 if (!IS_ERR(cpu_clk))
@@ -577,4 +577,4 @@ out:
577 577
578 return -EINVAL; 578 return -EINVAL;
579} 579}
580late_initcall(s5pv310_cpufreq_init); 580late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-exynos4/dma.c
index 20066c7c9e56..564bb530f332 100644
--- a/arch/arm/mach-s5pv310/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -30,10 +34,10 @@
30 34
31static u64 dma_dmamask = DMA_BIT_MASK(32); 35static u64 dma_dmamask = DMA_BIT_MASK(32);
32 36
33static struct resource s5pv310_pdma0_resource[] = { 37static struct resource exynos4_pdma0_resource[] = {
34 [0] = { 38 [0] = {
35 .start = S5PV310_PA_PDMA0, 39 .start = EXYNOS4_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K, 40 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
38 }, 42 },
39 [1] = { 43 [1] = {
@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
43 }, 47 },
44}; 48};
45 49
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { 50static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
47 .peri = { 51 .peri = {
48 [0] = DMACH_PCM0_RX, 52 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX, 53 [1] = DMACH_PCM0_TX,
@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
80 }, 84 },
81}; 85};
82 86
83static struct platform_device s5pv310_device_pdma0 = { 87static struct platform_device exynos4_device_pdma0 = {
84 .name = "s3c-pl330", 88 .name = "s3c-pl330",
85 .id = 0, 89 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource), 90 .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
87 .resource = s5pv310_pdma0_resource, 91 .resource = exynos4_pdma0_resource,
88 .dev = { 92 .dev = {
89 .dma_mask = &dma_dmamask, 93 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 94 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata, 95 .platform_data = &exynos4_pdma0_pdata,
92 }, 96 },
93}; 97};
94 98
95static struct resource s5pv310_pdma1_resource[] = { 99static struct resource exynos4_pdma1_resource[] = {
96 [0] = { 100 [0] = {
97 .start = S5PV310_PA_PDMA1, 101 .start = EXYNOS4_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K, 102 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
100 }, 104 },
101 [1] = { 105 [1] = {
@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
105 }, 109 },
106}; 110};
107 111
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { 112static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
109 .peri = { 113 .peri = {
110 [0] = DMACH_PCM0_RX, 114 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX, 115 [1] = DMACH_PCM0_TX,
@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
142 }, 146 },
143}; 147};
144 148
145static struct platform_device s5pv310_device_pdma1 = { 149static struct platform_device exynos4_device_pdma1 = {
146 .name = "s3c-pl330", 150 .name = "s3c-pl330",
147 .id = 1, 151 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource), 152 .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
149 .resource = s5pv310_pdma1_resource, 153 .resource = exynos4_pdma1_resource,
150 .dev = { 154 .dev = {
151 .dma_mask = &dma_dmamask, 155 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32), 156 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata, 157 .platform_data = &exynos4_pdma1_pdata,
154 }, 158 },
155}; 159};
156 160
157static struct platform_device *s5pv310_dmacs[] __initdata = { 161static struct platform_device *exynos4_dmacs[] __initdata = {
158 &s5pv310_device_pdma0, 162 &exynos4_device_pdma0,
159 &s5pv310_device_pdma1, 163 &exynos4_device_pdma1,
160}; 164};
161 165
162static int __init s5pv310_dma_init(void) 166static int __init exynos4_dma_init(void)
163{ 167{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs)); 168 platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
165 169
166 return 0; 170 return 0;
167} 171}
168arch_initcall(s5pv310_dma_init); 172arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
index 55217b8923ec..c46fdc57d94c 100644
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ b/arch/arm/mach-exynos4/gpiolib.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c 1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - GPIOlib support 6 * EXYNOS4 - GPIOlib support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -43,159 +43,159 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure 43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here. 44 * uses the above macro and depends on the banks being listed in order here.
45 */ 45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = { 46static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
47 { 47 {
48 .chip = { 48 .chip = {
49 .base = S5PV310_GPA0(0), 49 .base = EXYNOS4_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR, 50 .ngpio = EXYNOS4_GPIO_A0_NR,
51 .label = "GPA0", 51 .label = "GPA0",
52 }, 52 },
53 }, { 53 }, {
54 .chip = { 54 .chip = {
55 .base = S5PV310_GPA1(0), 55 .base = EXYNOS4_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR, 56 .ngpio = EXYNOS4_GPIO_A1_NR,
57 .label = "GPA1", 57 .label = "GPA1",
58 }, 58 },
59 }, { 59 }, {
60 .chip = { 60 .chip = {
61 .base = S5PV310_GPB(0), 61 .base = EXYNOS4_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR, 62 .ngpio = EXYNOS4_GPIO_B_NR,
63 .label = "GPB", 63 .label = "GPB",
64 }, 64 },
65 }, { 65 }, {
66 .chip = { 66 .chip = {
67 .base = S5PV310_GPC0(0), 67 .base = EXYNOS4_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR, 68 .ngpio = EXYNOS4_GPIO_C0_NR,
69 .label = "GPC0", 69 .label = "GPC0",
70 }, 70 },
71 }, { 71 }, {
72 .chip = { 72 .chip = {
73 .base = S5PV310_GPC1(0), 73 .base = EXYNOS4_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR, 74 .ngpio = EXYNOS4_GPIO_C1_NR,
75 .label = "GPC1", 75 .label = "GPC1",
76 }, 76 },
77 }, { 77 }, {
78 .chip = { 78 .chip = {
79 .base = S5PV310_GPD0(0), 79 .base = EXYNOS4_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR, 80 .ngpio = EXYNOS4_GPIO_D0_NR,
81 .label = "GPD0", 81 .label = "GPD0",
82 }, 82 },
83 }, { 83 }, {
84 .chip = { 84 .chip = {
85 .base = S5PV310_GPD1(0), 85 .base = EXYNOS4_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR, 86 .ngpio = EXYNOS4_GPIO_D1_NR,
87 .label = "GPD1", 87 .label = "GPD1",
88 }, 88 },
89 }, { 89 }, {
90 .chip = { 90 .chip = {
91 .base = S5PV310_GPE0(0), 91 .base = EXYNOS4_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR, 92 .ngpio = EXYNOS4_GPIO_E0_NR,
93 .label = "GPE0", 93 .label = "GPE0",
94 }, 94 },
95 }, { 95 }, {
96 .chip = { 96 .chip = {
97 .base = S5PV310_GPE1(0), 97 .base = EXYNOS4_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR, 98 .ngpio = EXYNOS4_GPIO_E1_NR,
99 .label = "GPE1", 99 .label = "GPE1",
100 }, 100 },
101 }, { 101 }, {
102 .chip = { 102 .chip = {
103 .base = S5PV310_GPE2(0), 103 .base = EXYNOS4_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR, 104 .ngpio = EXYNOS4_GPIO_E2_NR,
105 .label = "GPE2", 105 .label = "GPE2",
106 }, 106 },
107 }, { 107 }, {
108 .chip = { 108 .chip = {
109 .base = S5PV310_GPE3(0), 109 .base = EXYNOS4_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR, 110 .ngpio = EXYNOS4_GPIO_E3_NR,
111 .label = "GPE3", 111 .label = "GPE3",
112 }, 112 },
113 }, { 113 }, {
114 .chip = { 114 .chip = {
115 .base = S5PV310_GPE4(0), 115 .base = EXYNOS4_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR, 116 .ngpio = EXYNOS4_GPIO_E4_NR,
117 .label = "GPE4", 117 .label = "GPE4",
118 }, 118 },
119 }, { 119 }, {
120 .chip = { 120 .chip = {
121 .base = S5PV310_GPF0(0), 121 .base = EXYNOS4_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR, 122 .ngpio = EXYNOS4_GPIO_F0_NR,
123 .label = "GPF0", 123 .label = "GPF0",
124 }, 124 },
125 }, { 125 }, {
126 .chip = { 126 .chip = {
127 .base = S5PV310_GPF1(0), 127 .base = EXYNOS4_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR, 128 .ngpio = EXYNOS4_GPIO_F1_NR,
129 .label = "GPF1", 129 .label = "GPF1",
130 }, 130 },
131 }, { 131 }, {
132 .chip = { 132 .chip = {
133 .base = S5PV310_GPF2(0), 133 .base = EXYNOS4_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR, 134 .ngpio = EXYNOS4_GPIO_F2_NR,
135 .label = "GPF2", 135 .label = "GPF2",
136 }, 136 },
137 }, { 137 }, {
138 .chip = { 138 .chip = {
139 .base = S5PV310_GPF3(0), 139 .base = EXYNOS4_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR, 140 .ngpio = EXYNOS4_GPIO_F3_NR,
141 .label = "GPF3", 141 .label = "GPF3",
142 }, 142 },
143 }, 143 },
144}; 144};
145 145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 146static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
147 { 147 {
148 .chip = { 148 .chip = {
149 .base = S5PV310_GPJ0(0), 149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR, 150 .ngpio = EXYNOS4_GPIO_J0_NR,
151 .label = "GPJ0", 151 .label = "GPJ0",
152 }, 152 },
153 }, { 153 }, {
154 .chip = { 154 .chip = {
155 .base = S5PV310_GPJ1(0), 155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR, 156 .ngpio = EXYNOS4_GPIO_J1_NR,
157 .label = "GPJ1", 157 .label = "GPJ1",
158 }, 158 },
159 }, { 159 }, {
160 .chip = { 160 .chip = {
161 .base = S5PV310_GPK0(0), 161 .base = EXYNOS4_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR, 162 .ngpio = EXYNOS4_GPIO_K0_NR,
163 .label = "GPK0", 163 .label = "GPK0",
164 }, 164 },
165 }, { 165 }, {
166 .chip = { 166 .chip = {
167 .base = S5PV310_GPK1(0), 167 .base = EXYNOS4_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR, 168 .ngpio = EXYNOS4_GPIO_K1_NR,
169 .label = "GPK1", 169 .label = "GPK1",
170 }, 170 },
171 }, { 171 }, {
172 .chip = { 172 .chip = {
173 .base = S5PV310_GPK2(0), 173 .base = EXYNOS4_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR, 174 .ngpio = EXYNOS4_GPIO_K2_NR,
175 .label = "GPK2", 175 .label = "GPK2",
176 }, 176 },
177 }, { 177 }, {
178 .chip = { 178 .chip = {
179 .base = S5PV310_GPK3(0), 179 .base = EXYNOS4_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR, 180 .ngpio = EXYNOS4_GPIO_K3_NR,
181 .label = "GPK3", 181 .label = "GPK3",
182 }, 182 },
183 }, { 183 }, {
184 .chip = { 184 .chip = {
185 .base = S5PV310_GPL0(0), 185 .base = EXYNOS4_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR, 186 .ngpio = EXYNOS4_GPIO_L0_NR,
187 .label = "GPL0", 187 .label = "GPL0",
188 }, 188 },
189 }, { 189 }, {
190 .chip = { 190 .chip = {
191 .base = S5PV310_GPL1(0), 191 .base = EXYNOS4_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR, 192 .ngpio = EXYNOS4_GPIO_L1_NR,
193 .label = "GPL1", 193 .label = "GPL1",
194 }, 194 },
195 }, { 195 }, {
196 .chip = { 196 .chip = {
197 .base = S5PV310_GPL2(0), 197 .base = EXYNOS4_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR, 198 .ngpio = EXYNOS4_GPIO_L2_NR,
199 .label = "GPL2", 199 .label = "GPL2",
200 }, 200 },
201 }, { 201 }, {
@@ -203,8 +203,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
203 .config = &gpio_cfg_noint, 203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0), 204 .irq_base = IRQ_EINT(0),
205 .chip = { 205 .chip = {
206 .base = S5PV310_GPX0(0), 206 .base = EXYNOS4_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR, 207 .ngpio = EXYNOS4_GPIO_X0_NR,
208 .label = "GPX0", 208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq, 209 .to_irq = samsung_gpiolib_to_irq,
210 }, 210 },
@@ -213,8 +213,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
213 .config = &gpio_cfg_noint, 213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8), 214 .irq_base = IRQ_EINT(8),
215 .chip = { 215 .chip = {
216 .base = S5PV310_GPX1(0), 216 .base = EXYNOS4_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR, 217 .ngpio = EXYNOS4_GPIO_X1_NR,
218 .label = "GPX1", 218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq, 219 .to_irq = samsung_gpiolib_to_irq,
220 }, 220 },
@@ -223,8 +223,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
223 .config = &gpio_cfg_noint, 223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16), 224 .irq_base = IRQ_EINT(16),
225 .chip = { 225 .chip = {
226 .base = S5PV310_GPX2(0), 226 .base = EXYNOS4_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR, 227 .ngpio = EXYNOS4_GPIO_X2_NR,
228 .label = "GPX2", 228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq, 229 .to_irq = samsung_gpiolib_to_irq,
230 }, 230 },
@@ -233,25 +233,25 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
233 .config = &gpio_cfg_noint, 233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24), 234 .irq_base = IRQ_EINT(24),
235 .chip = { 235 .chip = {
236 .base = S5PV310_GPX3(0), 236 .base = EXYNOS4_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR, 237 .ngpio = EXYNOS4_GPIO_X3_NR,
238 .label = "GPX3", 238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq, 239 .to_irq = samsung_gpiolib_to_irq,
240 }, 240 },
241 }, 241 },
242}; 242};
243 243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = { 244static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
245 { 245 {
246 .chip = { 246 .chip = {
247 .base = S5PV310_GPZ(0), 247 .base = EXYNOS4_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR, 248 .ngpio = EXYNOS4_GPIO_Z_NR,
249 .label = "GPZ", 249 .label = "GPZ",
250 }, 250 },
251 }, 251 },
252}; 252};
253 253
254static __init int s5pv310_gpiolib_init(void) 254static __init int exynos4_gpiolib_init(void)
255{ 255{
256 struct s3c_gpio_chip *chip; 256 struct s3c_gpio_chip *chip;
257 int i; 257 int i;
@@ -259,8 +259,8 @@ static __init int s5pv310_gpiolib_init(void)
259 259
260 /* GPIO part 1 */ 260 /* GPIO part 1 */
261 261
262 chip = s5pv310_gpio_part1_4bit; 262 chip = exynos4_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit); 263 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
264 264
265 for (i = 0; i < nr_chips; i++, chip++) { 265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL) 266 if (chip->config == NULL)
@@ -269,12 +269,12 @@ static __init int s5pv310_gpiolib_init(void)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20; 269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 } 270 }
271 271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips); 272 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
273 273
274 /* GPIO part 2 */ 274 /* GPIO part 2 */
275 275
276 chip = s5pv310_gpio_part2_4bit; 276 chip = exynos4_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit); 277 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
278 278
279 for (i = 0; i < nr_chips; i++, chip++) { 279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL) 280 if (chip->config == NULL)
@@ -283,12 +283,12 @@ static __init int s5pv310_gpiolib_init(void)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20; 283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 } 284 }
285 285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips); 286 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
287 287
288 /* GPIO part 3 */ 288 /* GPIO part 3 */
289 289
290 chip = s5pv310_gpio_part3_4bit; 290 chip = exynos4_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit); 291 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
292 292
293 for (i = 0; i < nr_chips; i++, chip++) { 293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL) 294 if (chip->config == NULL)
@@ -297,8 +297,8 @@ static __init int s5pv310_gpiolib_init(void)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20; 297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 } 298 }
299 299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips); 300 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
301 301
302 return 0; 302 return 0;
303} 303}
304core_initcall(s5pv310_gpiolib_init); 304core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
index 164b7b045713..6c6cfc50c46b 100644
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ b/arch/arm/mach-exynos4/headsmp.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/headsmp.S 2 * linux/arch/arm/mach-exynos4/headsmp.S
3 * 3 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S 4 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 * 5 *
@@ -16,11 +16,11 @@
16 __INIT 16 __INIT
17 17
18/* 18/*
19 * s5pv310 specific entry point for secondary CPUs. This provides 19 * exynos4 specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're 20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise. 21 * ready for them to initialise.
22 */ 22 */
23ENTRY(s5pv310_secondary_startup) 23ENTRY(exynos4_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5 24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15 25 and r0, r0, #15
26 adr r4, 1f 26 adr r4, 1f
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index c24235c89eed..4c42f9ce1c53 100644
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -1,4 +1,4 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c 1/* linux arch/arm/mach-exynos4/hotplug.c
2 * 2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c 3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 * 4 *
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index b0d920c474d3..58bbd049a6c4 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S 1/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S 6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 * 7 *
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index e600e1d522df..d8f38c2e5654 100644
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -1,8 +1,8 @@
1/* arch/arm/mach-s5pv310/include/mach/entry-macro.S 1/* arch/arm/mach-exynos4/include/mach/entry-macro.S
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S 3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 * 4 *
5 * Low-level IRQ helper macros for S5PV310 platforms 5 * Low-level IRQ helper macros for EXYNOS4 platforms
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
new file mode 100644
index 000000000000..16082998bcd8
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -0,0 +1,135 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define EXYNOS4_GPIO_A0_NR (8)
25#define EXYNOS4_GPIO_A1_NR (6)
26#define EXYNOS4_GPIO_B_NR (8)
27#define EXYNOS4_GPIO_C0_NR (5)
28#define EXYNOS4_GPIO_C1_NR (5)
29#define EXYNOS4_GPIO_D0_NR (4)
30#define EXYNOS4_GPIO_D1_NR (4)
31#define EXYNOS4_GPIO_E0_NR (5)
32#define EXYNOS4_GPIO_E1_NR (8)
33#define EXYNOS4_GPIO_E2_NR (6)
34#define EXYNOS4_GPIO_E3_NR (8)
35#define EXYNOS4_GPIO_E4_NR (8)
36#define EXYNOS4_GPIO_F0_NR (8)
37#define EXYNOS4_GPIO_F1_NR (8)
38#define EXYNOS4_GPIO_F2_NR (8)
39#define EXYNOS4_GPIO_F3_NR (6)
40#define EXYNOS4_GPIO_J0_NR (8)
41#define EXYNOS4_GPIO_J1_NR (5)
42#define EXYNOS4_GPIO_K0_NR (7)
43#define EXYNOS4_GPIO_K1_NR (7)
44#define EXYNOS4_GPIO_K2_NR (7)
45#define EXYNOS4_GPIO_K3_NR (7)
46#define EXYNOS4_GPIO_L0_NR (8)
47#define EXYNOS4_GPIO_L1_NR (3)
48#define EXYNOS4_GPIO_L2_NR (8)
49#define EXYNOS4_GPIO_X0_NR (8)
50#define EXYNOS4_GPIO_X1_NR (8)
51#define EXYNOS4_GPIO_X2_NR (8)
52#define EXYNOS4_GPIO_X3_NR (8)
53#define EXYNOS4_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define EXYNOS4_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 EXYNOS4_GPIO_A0_START = 0,
62 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
63 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
64 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
65 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
66 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
67 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
68 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
69 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
70 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
71 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
72 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
73 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
74 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
75 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
76 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
77 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
78 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
79 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
80 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
81 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
82 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
83 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
84 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
85 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
86 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
87 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
88 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
89 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
90 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
91};
92
93/* EXYNOS4 GPIO number definitions */
94#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
95#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
96#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
97#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
98#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
99#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
100#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
101#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
102#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
103#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
104#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
105#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
106#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
107#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
108#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
109#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
110#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
111#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
112#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
113#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
114#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
115#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
116#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
117#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
118#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
119#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
120#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
121#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
122#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
123#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
124
125/* the end of the EXYNOS4 specific gpios */
126#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END EXYNOS4_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h
index 28ff9881f1a6..5109eb232f23 100644
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ b/arch/arm/mach-exynos4/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h 1/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Hardware support 6 * EXYNOS4 - Hardware support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h
index 8a7f9128391f..d5478d247535 100644
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ b/arch/arm/mach-exynos4/include/mach/io.h
@@ -1,13 +1,13 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/io.h 1/* linux/arch/arm/mach-exynos4/include/mach/io.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h 8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 * 9 *
10 * Default IO routines for S5PV310 10 * Default IO routines for EXYNOS4
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
new file mode 100644
index 000000000000..80a41e03cc17
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -0,0 +1,144 @@
1/* linux/arch/arm/mach-exynos4/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define EXYNOS4_PA_SYSRAM 0x02020000
27
28#define EXYNOS4_PA_I2S0 0x03830000
29#define EXYNOS4_PA_I2S1 0xE3100000
30#define EXYNOS4_PA_I2S2 0xE2A00000
31
32#define EXYNOS4_PA_PCM0 0x03840000
33#define EXYNOS4_PA_PCM1 0x13980000
34#define EXYNOS4_PA_PCM2 0x13990000
35
36#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define EXYNOS4_PA_ONENAND 0x0C000000
39#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
40
41#define EXYNOS4_PA_CHIPID 0x10000000
42
43#define EXYNOS4_PA_SYSCON 0x10010000
44#define EXYNOS4_PA_PMU 0x10020000
45#define EXYNOS4_PA_CMU 0x10030000
46
47#define EXYNOS4_PA_WATCHDOG 0x10060000
48#define EXYNOS4_PA_RTC 0x10070000
49
50#define EXYNOS4_PA_DMC0 0x10400000
51
52#define EXYNOS4_PA_COMBINER 0x10448000
53
54#define EXYNOS4_PA_COREPERI 0x10500000
55#define EXYNOS4_PA_GIC_CPU 0x10500100
56#define EXYNOS4_PA_TWD 0x10500600
57#define EXYNOS4_PA_GIC_DIST 0x10501000
58#define EXYNOS4_PA_L2CC 0x10502000
59
60#define EXYNOS4_PA_MDMA 0x10810000
61#define EXYNOS4_PA_PDMA0 0x12680000
62#define EXYNOS4_PA_PDMA1 0x12690000
63
64#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
65#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
66#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
67#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
68#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
69#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
70#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
71#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
72#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
73#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
74#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
75#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
76#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
77#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
78#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
79#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
80
81#define EXYNOS4_PA_GPIO1 0x11400000
82#define EXYNOS4_PA_GPIO2 0x11000000
83#define EXYNOS4_PA_GPIO3 0x03860000
84
85#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
86#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
87
88#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define EXYNOS4_PA_SROMC 0x12570000
91
92#define EXYNOS4_PA_UART 0x13800000
93
94#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define EXYNOS4_PA_AC97 0x139A0000
97
98#define EXYNOS4_PA_TIMER 0x139D0000
99
100#define EXYNOS4_PA_SDRAM 0x40000000
101
102#define EXYNOS4_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
110#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
111#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
112#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
113#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
114#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
115#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
116#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
117#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
118#define S3C_PA_RTC EXYNOS4_PA_RTC
119#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
120
121#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
125#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
126#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
127#define S5P_PA_SROMC EXYNOS4_PA_SROMC
128#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
129#define S5P_PA_TIMER EXYNOS4_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART EXYNOS4_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h
index 1dffb4823245..39b47d06f9bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ b/arch/arm/mach-exynos4/include/mach/memory.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/memory.h 1/* linux/arch/arm/mach-exynos4/include/mach/memory.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Memory definitions 6 * EXYNOS4 - Memory definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..1401b21663a5
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21
22#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
24
25#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
27
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h
index 834227140eaa..0368b5a27252 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mem.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - SROMC and DMC register definitions 6 * EXYNOS4 - SROMC and DMC register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index fb333d0f6073..2ddd6175dfa0 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Power management unit definition 6 * EXYNOS4 - Power management unit definition
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -18,7 +18,7 @@
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19 19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) 20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) 21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) 23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) 24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
index 0b28e81a16f7..b6aef863b9d6 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - System MMU register 6 * EXYNOS4 - System MMU register
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
index 393ccbd52c4a..a463dcebcfd3 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-exynos4/include/mach/smp.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/smp.h 1/* linux/arch/arm/mach-exynos4/include/mach/smp.h
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h 3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/ 4*/
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h
index 598fc5c9211b..1428adad8379 100644
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/sysmmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Samsung sysmmu driver for S5PV310 6 * Samsung sysmmu driver for EXYNOS4
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -13,10 +13,10 @@
13#ifndef __ASM_ARM_ARCH_SYSMMU_H 13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ 14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15 15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16 16#define EXYNOS4_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM 17#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
18 18
19enum s5pv310_sysmmu_ips { 19enum exynos4_sysmmu_ips {
20 SYSMMU_MDMA, 20 SYSMMU_MDMA,
21 SYSMMU_SSS, 21 SYSMMU_SSS,
22 SYSMMU_FIMC0, 22 SYSMMU_FIMC0,
@@ -35,7 +35,7 @@ enum s5pv310_sysmmu_ips {
35 SYSMMU_MFC_R, 35 SYSMMU_MFC_R,
36}; 36};
37 37
38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = { 38static char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
39 "SYSMMU_MDMA" , 39 "SYSMMU_MDMA" ,
40 "SYSMMU_SSS" , 40 "SYSMMU_SSS" ,
41 "SYSMMU_FIMC0" , 41 "SYSMMU_FIMC0" ,
@@ -54,7 +54,7 @@ static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
54 "SYSMMU_MFC_R" , 54 "SYSMMU_MFC_R" ,
55}; 55};
56 56
57typedef enum s5pv310_sysmmu_ips sysmmu_ips; 57typedef enum exynos4_sysmmu_ips sysmmu_ips;
58 58
59struct sysmmu_tt_info { 59struct sysmmu_tt_info {
60 unsigned long *pgd; 60 unsigned long *pgd;
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h
index d10c009cf0f1..5e3220c18fc7 100644
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ b/arch/arm/mach-exynos4/include/mach/system.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/system.h 1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - system support header 6 * EXYNOS4 - system support header
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h
index bd2359b952b4..6d138750a708 100644
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ b/arch/arm/mach-exynos4/include/mach/timex.h
@@ -1,14 +1,14 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/timex.h 1/* linux/arch/arm/mach-exynos4/include/mach/timex.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright (c) 2003-2010 Simtec Electronics 6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
8 * 8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h 9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 * 10 *
11 * S5PV310 - time parameters 11 * EXYNOS4 - time parameters
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h
index 59593c1e2416..21d97bcd9acb 100644
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos4/include/mach/uncompress.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h 1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - uncompress code 6 * EXYNOS4 - uncompress code
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h
index 65759fb97581..284330e571d2 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-exynos4/include/mach/vmalloc.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h 1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
@@ -11,7 +11,7 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * S5PV310 vmalloc definition 14 * EXYNOS4 vmalloc definition
15*/ 15*/
16 16
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-exynos4/init.c
index 182dcf42cfb4..cf91f50e43ab 100644
--- a/arch/arm/mach-s5pv310/init.c
+++ b/arch/arm/mach-exynos4/init.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/init.c 1/* linux/arch/arm/mach-exynos4/init.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
@@ -14,7 +14,7 @@
14#include <plat/devs.h> 14#include <plat/devs.h>
15#include <plat/regs-serial.h> 15#include <plat/regs-serial.h>
16 16
17static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { 17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = { 18 [0] = {
19 .name = "uclk1", 19 .name = "uclk1",
20 .divisor = 1, 20 .divisor = 1,
@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
24}; 24};
25 25
26/* uart registration process */ 26/* uart registration process */
27void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{ 28{
29 struct s3c2410_uartcfg *tcfg = cfg; 29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt; 30 u32 ucnt;
@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) { 33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1; 34 tcfg->has_fracval = 1;
35 tcfg->clocks = s5pv310_serial_clocks; 35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks); 36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 } 37 }
38 } 38 }
39 39
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 34093b069f67..6d35878ec1aa 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/platsmp.c 1/* linux/arch/arm/mach-exynos4/platsmp.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * 7 *
@@ -28,7 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30 30
31extern void s5pv310_secondary_startup(void); 31extern void exynos4_secondary_startup(void);
32 32
33/* 33/*
34 * control for which core is the next to come out of the secondary 34 * control for which core is the next to come out of the secondary
@@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
139 /* sanity check */ 139 /* sanity check */
140 if (ncores > NR_CPUS) { 140 if (ncores > NR_CPUS) {
141 printk(KERN_WARNING 141 printk(KERN_WARNING
142 "S5PV310: no. of cores (%d) greater than configured " 142 "EXYNOS4: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n", 143 "maximum of %d - clipping\n",
144 ncores, NR_CPUS); 144 ncores, NR_CPUS);
145 ncores = NR_CPUS; 145 ncores = NR_CPUS;
@@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
168 * until it receives a soft interrupt, and then the 168 * until it receives a soft interrupt, and then the
169 * secondary CPU branches to this address. 169 * secondary CPU branches to this address.
170 */ 170 */
171 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); 171 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
172} 172}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-exynos4/setup-i2c0.c
index f47f8f3152ec..d395bd17c38b 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-exynos4/setup-i2c0.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c0.c 2 * linux/arch/arm/mach-exynos4/setup-i2c0.c
3 * 3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 5 * http://www.samsung.com/
@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
21 21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 23{
24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2, 24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 26}
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define S5PV310_GPIO_A0_NR (8)
25#define S5PV310_GPIO_A1_NR (6)
26#define S5PV310_GPIO_B_NR (8)
27#define S5PV310_GPIO_C0_NR (5)
28#define S5PV310_GPIO_C1_NR (5)
29#define S5PV310_GPIO_D0_NR (4)
30#define S5PV310_GPIO_D1_NR (4)
31#define S5PV310_GPIO_E0_NR (5)
32#define S5PV310_GPIO_E1_NR (8)
33#define S5PV310_GPIO_E2_NR (6)
34#define S5PV310_GPIO_E3_NR (8)
35#define S5PV310_GPIO_E4_NR (8)
36#define S5PV310_GPIO_F0_NR (8)
37#define S5PV310_GPIO_F1_NR (8)
38#define S5PV310_GPIO_F2_NR (8)
39#define S5PV310_GPIO_F3_NR (6)
40#define S5PV310_GPIO_J0_NR (8)
41#define S5PV310_GPIO_J1_NR (5)
42#define S5PV310_GPIO_K0_NR (7)
43#define S5PV310_GPIO_K1_NR (7)
44#define S5PV310_GPIO_K2_NR (7)
45#define S5PV310_GPIO_K3_NR (7)
46#define S5PV310_GPIO_L0_NR (8)
47#define S5PV310_GPIO_L1_NR (3)
48#define S5PV310_GPIO_L2_NR (8)
49#define S5PV310_GPIO_X0_NR (8)
50#define S5PV310_GPIO_X1_NR (8)
51#define S5PV310_GPIO_X2_NR (8)
52#define S5PV310_GPIO_X3_NR (8)
53#define S5PV310_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define S5PV310_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 S5PV310_GPIO_A0_START = 0,
62 S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
63 S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
64 S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
65 S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
66 S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
67 S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
68 S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
69 S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
70 S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
71 S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
72 S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
73 S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
74 S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
75 S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
76 S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
77 S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
78 S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
79 S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
80 S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
81 S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
82 S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
83 S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
84 S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
85 S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
86 S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
87 S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
88 S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
89 S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
90 S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
91};
92
93/* S5PV310 GPIO number definitions */
94#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
95#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
96#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
97#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
98#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
99#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
100#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
101#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
102#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
103#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
104#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
105#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
106#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
107#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
108#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
109#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
110#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
111#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
112#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
113#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
114#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
115#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
116#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
117#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
118#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
119#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
120#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
121#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
122#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
123#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
124
125/* the end of the S5PV310 specific gpios */
126#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END S5PV310_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define S5PV310_PA_SYSRAM 0x02025000
27
28#define S5PV310_PA_I2S0 0x03830000
29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PV310_PA_I2S2 0xE2A00000
31
32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
35
36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41#define S5PV310_PA_CHIPID 0x10000000
42
43#define S5PV310_PA_SYSCON 0x10010000
44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
46
47#define S5PV310_PA_WATCHDOG 0x10060000
48#define S5PV310_PA_RTC 0x10070000
49
50#define S5PV310_PA_DMC0 0x10400000
51
52#define S5PV310_PA_COMBINER 0x10448000
53
54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
59
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
66#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
67#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
68#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
69#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
70#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
71#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
72#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
73#define S5PV310_PA_SYSMMU_PCIe 0x12620000
74#define S5PV310_PA_SYSMMU_G2D 0x12A20000
75#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
76#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
77#define S5PV310_PA_SYSMMU_TV 0x12E20000
78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81#define S5PV310_PA_GPIO1 0x11400000
82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
110#define S3C_PA_IIC S5PV310_PA_IIC(0)
111#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
112#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
113#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
114#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
115#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
116#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118#define S3C_PA_RTC S5PV310_PA_RTC
119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 047d31c1bbd8..c3bfe9b13acf 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/cpu.c 1/* linux/arch/arm/plat-s5p/cpu.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P CPU Support 6 * S5P CPU Support
7 * 7 *
@@ -12,17 +12,20 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/map.h> 15
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 17#include <asm/mach/map.h>
18
19#include <mach/map.h>
18#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21
19#include <plat/cpu.h> 22#include <plat/cpu.h>
20#include <plat/s5p6440.h> 23#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 24#include <plat/s5p6442.h>
22#include <plat/s5p6450.h> 25#include <plat/s5p6450.h>
23#include <plat/s5pc100.h> 26#include <plat/s5pc100.h>
24#include <plat/s5pv210.h> 27#include <plat/s5pv210.h>
25#include <plat/s5pv310.h> 28#include <plat/exynos4.h>
26 29
27/* table of supported CPUs */ 30/* table of supported CPUs */
28 31
@@ -31,7 +34,7 @@ static const char name_s5p6442[] = "S5P6442";
31static const char name_s5p6450[] = "S5P6450"; 34static const char name_s5p6450[] = "S5P6450";
32static const char name_s5pc100[] = "S5PC100"; 35static const char name_s5pc100[] = "S5PC100";
33static const char name_s5pv210[] = "S5PV210/S5PC110"; 36static const char name_s5pv210[] = "S5PV210/S5PC110";
34static const char name_s5pv310[] = "S5PV310"; 37static const char name_exynos4210[] = "EXYNOS4210";
35 38
36static struct cpu_table cpu_ids[] __initdata = { 39static struct cpu_table cpu_ids[] __initdata = {
37 { 40 {
@@ -75,13 +78,13 @@ static struct cpu_table cpu_ids[] __initdata = {
75 .init = s5pv210_init, 78 .init = s5pv210_init,
76 .name = name_s5pv210, 79 .name = name_s5pv210,
77 }, { 80 }, {
78 .idcode = 0x43200000, 81 .idcode = 0x43210000,
79 .idmask = 0xfffff000, 82 .idmask = 0xfffff000,
80 .map_io = s5pv310_map_io, 83 .map_io = exynos4_map_io,
81 .init_clocks = s5pv310_init_clocks, 84 .init_clocks = exynos4_init_clocks,
82 .init_uarts = s5pv310_init_uarts, 85 .init_uarts = exynos4_init_uarts,
83 .init = s5pv310_init, 86 .init = exynos4_init,
84 .name = name_s5pv310, 87 .name = name_exynos4210,
85 }, 88 },
86}; 89};
87 90
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
new file mode 100644
index 000000000000..907caab53dcf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -0,0 +1,34 @@
1/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4_setup_clocks(void);
18
19#ifdef CONFIG_CPU_EXYNOS4210
20
21extern int exynos4_init(void);
22extern void exynos4_init_irq(void);
23extern void exynos4_map_io(void);
24extern void exynos4_init_clocks(int xtal);
25extern struct sys_timer exynos4_timer;
26
27#define exynos4_init_uarts exynos4_common_init_uarts
28
29#else
30#define exynos4_init_clocks NULL
31#define exynos4_init_uarts NULL
32#define exynos4_map_io NULL
33#define exynos4_init NULL
34#endif
diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h
deleted file mode 100644
index 769c991ceb37..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5pv310.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pv310 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PV310 related SoCs */
14
15extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pv310_register_clocks(void);
17extern void s5pv310_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PV310
20
21extern int s5pv310_init(void);
22extern void s5pv310_init_irq(void);
23extern void s5pv310_map_io(void);
24extern void s5pv310_init_clocks(int xtal);
25extern struct sys_timer s5pv310_timer;
26
27#define s5pv310_init_uarts s5pv310_common_init_uarts
28
29#else
30#define s5pv310_init_clocks NULL
31#define s5pv310_init_uarts NULL
32#define s5pv310_map_io NULL
33#define s5pv310_init NULL
34#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 18:24:52 -0500