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authorJonas Gorski <jogo@openwrt.org>2013-06-18 04:34:32 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-07-01 09:10:59 -0400
commit7ac836ce2aa7b931f6347e554cb65f9e9cc1da57 (patch)
tree13b99f09142adc6265dc5cf69b9574b411926471 /arch
parenta068dde168e0c618e1dc2151a0922254ec3bbf04 (diff)
MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
BCM6328 has a OTP which tells us if the second core is available. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/5490/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/bcm63xx/prom.c6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h7
3 files changed, 14 insertions, 1 deletions
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 3b21454c56a0..8ac4e095e68e 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -69,7 +69,11 @@ void __init prom_init(void)
69 * for now. 69 * for now.
70 */ 70 */
71 if (BCMCPU_IS_6328()) { 71 if (BCMCPU_IS_6328()) {
72 bmips_smp_enabled = 0; 72 reg = bcm_readl(BCM_6328_OTP_BASE +
73 OTP_USER_BITS_6328_REG(3));
74
75 if (reg & OTP_6328_REG3_TP1_DISABLED)
76 bmips_smp_enabled = 0;
73 } else if (BCMCPU_IS_6358()) { 77 } else if (BCMCPU_IS_6358()) {
74 bmips_smp_enabled = 0; 78 bmips_smp_enabled = 0;
75 } 79 }
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 9d3c08e4a7e4..22390a2a0661 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -296,6 +296,8 @@ enum bcm63xx_regs_set {
296#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 296#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
297#define BCM_6328_RNG_BASE (0xdeadbeef) 297#define BCM_6328_RNG_BASE (0xdeadbeef)
298#define BCM_6328_MISC_BASE (0xb0001800) 298#define BCM_6328_MISC_BASE (0xb0001800)
299#define BCM_6328_OTP_BASE (0xb0000600)
300
299/* 301/*
300 * 6338 register sets base address 302 * 6338 register sets base address
301 */ 303 */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 654213746b32..018628fe6f15 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1477,4 +1477,11 @@
1477 1477
1478#define PCIE_DEVICE_OFFSET 0x8000 1478#define PCIE_DEVICE_OFFSET 0x8000
1479 1479
1480/*************************************************************************
1481 * _REG relative to RSET_OTP
1482 *************************************************************************/
1483
1484#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
1485#define OTP_6328_REG3_TP1_DISABLED BIT(9)
1486
1480#endif /* BCM63XX_REGS_H_ */ 1487#endif /* BCM63XX_REGS_H_ */