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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2010-04-21 10:11:33 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-06 18:02:07 -0400
commit7a9978a1e2225507025a8b90b4289d506a416bd9 (patch)
tree163a66035df8ed7a510ad692eaf7259c885a932e /arch
parent280faffb4e059b3f453e297af7060d9c277c0ca9 (diff)
DaVinci: move IDE platform device to its proper place
The IDE platform device is registered in three different places (2 board files for DM644x and in dm646x.c for DM646x) while both the IDE base address and the IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE platform seems to be in devices.c. Merge the IDE platform data and registration code and create davinci_init_ide() in place of dm646x_init_ide()... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c33
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c34
-rw-r--r--arch/arm/mach-davinci/devices.c44
-rw-r--r--arch/arm/mach-davinci/dm646x.c32
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h3
7 files changed, 49 insertions, 100 deletions
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d028bab6f981..73c0b04a75ff 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -41,8 +41,6 @@
41#define DM644X_EVM_PHY_MASK (0x2) 41#define DM644X_EVM_PHY_MASK (0x2)
42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
43 43
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define LXT971_PHY_ID (0x001378e2) 44#define LXT971_PHY_ID (0x001378e2)
47#define LXT971_PHY_MASK (0xfffffff0) 45#define LXT971_PHY_MASK (0xfffffff0)
48 46
@@ -252,32 +250,6 @@ static struct platform_device rtc_dev = {
252 .id = -1, 250 .id = -1,
253}; 251};
254 252
255static struct resource ide_resources[] = {
256 {
257 .start = DAVINCI_CFC_ATA_BASE,
258 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
259 .flags = IORESOURCE_MEM,
260 },
261 {
262 .start = IRQ_IDE,
263 .end = IRQ_IDE,
264 .flags = IORESOURCE_IRQ,
265 },
266};
267
268static u64 ide_dma_mask = DMA_BIT_MASK(32);
269
270static struct platform_device ide_dev = {
271 .name = "palm_bk3710",
272 .id = -1,
273 .resource = ide_resources,
274 .num_resources = ARRAY_SIZE(ide_resources),
275 .dev = {
276 .dma_mask = &ide_dma_mask,
277 .coherent_dma_mask = DMA_BIT_MASK(32),
278 },
279};
280
281static struct snd_platform_data dm644x_evm_snd_data; 253static struct snd_platform_data dm644x_evm_snd_data;
282 254
283/*----------------------------------------------------------------------*/ 255/*----------------------------------------------------------------------*/
@@ -698,10 +670,7 @@ static __init void davinci_evm_init(void)
698 pr_warning("WARNING: both IDE and Flash are " 670 pr_warning("WARNING: both IDE and Flash are "
699 "enabled, but they share AEMIF pins.\n" 671 "enabled, but they share AEMIF pins.\n"
700 "\tDisable IDE for NAND/NOR support.\n"); 672 "\tDisable IDE for NAND/NOR support.\n");
701 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 673 davinci_init_ide();
702 davinci_cfg_reg(DM644X_ATAEN);
703 davinci_cfg_reg(DM644X_HDIREN);
704 platform_device_register(&ide_dev);
705 } else if (HAS_NAND || HAS_NOR) { 674 } else if (HAS_NAND || HAS_NOR) {
706 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 675 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
707 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 676 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index b22e22cefcdd..e2ac06fac02a 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -733,7 +733,7 @@ static __init void evm_init(void)
733 platform_device_register(&davinci_nand_device); 733 platform_device_register(&davinci_nand_device);
734 734
735 if (HAS_ATA) 735 if (HAS_ATA)
736 dm646x_init_ide(); 736 davinci_init_ide();
737 737
738 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; 738 soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
739 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; 739 soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5afe37e3a4cb..875770cdea0a 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,6 +31,7 @@
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#include <mach/dm644x.h> 33#include <mach/dm644x.h>
34#include <mach/common.h>
34#include <mach/i2c.h> 35#include <mach/i2c.h>
35#include <mach/serial.h> 36#include <mach/serial.h>
36#include <mach/mux.h> 37#include <mach/mux.h>
@@ -41,8 +42,6 @@
41#define NEUROS_OSD2_PHY_MASK 0x2 42#define NEUROS_OSD2_PHY_MASK 0x2
42#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 43#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
43 44
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define LXT971_PHY_ID 0x001378e2 45#define LXT971_PHY_ID 0x001378e2
47#define LXT971_PHY_MASK 0xfffffff0 46#define LXT971_PHY_MASK 0xfffffff0
48 47
@@ -127,32 +126,6 @@ static struct platform_device davinci_fb_device = {
127 .num_resources = 0, 126 .num_resources = 0,
128}; 127};
129 128
130static struct resource ide_resources[] = {
131 {
132 .start = DAVINCI_CFC_ATA_BASE,
133 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = IRQ_IDE,
138 .end = IRQ_IDE,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143static u64 ide_dma_mask = DMA_BIT_MASK(32);
144
145static struct platform_device ide_dev = {
146 .name = "palm_bk3710",
147 .id = -1,
148 .resource = ide_resources,
149 .num_resources = ARRAY_SIZE(ide_resources),
150 .dev = {
151 .dma_mask = &ide_dma_mask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 },
154};
155
156static struct snd_platform_data dm644x_ntosd2_snd_data; 129static struct snd_platform_data dm644x_ntosd2_snd_data;
157 130
158static struct gpio_led ntosd2_leds[] = { 131static struct gpio_led ntosd2_leds[] = {
@@ -256,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
256 pr_warning("WARNING: both IDE and Flash are " 229 pr_warning("WARNING: both IDE and Flash are "
257 "enabled, but they share AEMIF pins.\n" 230 "enabled, but they share AEMIF pins.\n"
258 "\tDisable IDE for NAND/NOR support.\n"); 231 "\tDisable IDE for NAND/NOR support.\n");
259 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 232 davinci_init_ide();
260 davinci_cfg_reg(DM644X_ATAEN);
261 davinci_cfg_reg(DM644X_HDIREN);
262 platform_device_register(&ide_dev);
263 } else if (HAS_NAND) { 233 } else if (HAS_NAND) {
264 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 234 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
265 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 235 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index ef28080b1fda..d9c82ee434e0 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -26,6 +26,7 @@
26#include "clock.h" 26#include "clock.h"
27 27
28#define DAVINCI_I2C_BASE 0x01C21000 28#define DAVINCI_I2C_BASE 0x01C21000
29#define DAVINCI_ATA_BASE 0x01C66000
29#define DAVINCI_MMCSD0_BASE 0x01E10000 30#define DAVINCI_MMCSD0_BASE 0x01E10000
30#define DM355_MMCSD0_BASE 0x01E11000 31#define DM355_MMCSD0_BASE 0x01E11000
31#define DM355_MMCSD1_BASE 0x01E00000 32#define DM355_MMCSD1_BASE 0x01E00000
@@ -60,6 +61,49 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
60 (void) platform_device_register(&davinci_i2c_device); 61 (void) platform_device_register(&davinci_i2c_device);
61} 62}
62 63
64static struct resource ide_resources[] = {
65 {
66 .start = DAVINCI_ATA_BASE,
67 .end = DAVINCI_ATA_BASE + 0x7ff,
68 .flags = IORESOURCE_MEM,
69 },
70 {
71 .start = IRQ_IDE,
72 .end = IRQ_IDE,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static u64 ide_dma_mask = DMA_BIT_MASK(32);
78
79static struct platform_device ide_device = {
80 .name = "palm_bk3710",
81 .id = -1,
82 .resource = ide_resources,
83 .num_resources = ARRAY_SIZE(ide_resources),
84 .dev = {
85 .dma_mask = &ide_dma_mask,
86 .coherent_dma_mask = DMA_BIT_MASK(32),
87 },
88};
89
90void __init davinci_init_ide(void)
91{
92 if (cpu_is_davinci_dm644x()) {
93 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
94 davinci_cfg_reg(DM644X_ATAEN);
95 davinci_cfg_reg(DM644X_HDIREN);
96 } else if (cpu_is_davinci_dm646x()) {
97 /* IRQ_DM646X_IDE is the same as IRQ_IDE */
98 davinci_cfg_reg(DM646X_ATAEN);
99 } else {
100 WARN_ON(1);
101 return;
102 }
103
104 platform_device_register(&ide_device);
105}
106
63#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) 107#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
64 108
65static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); 109static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index b67b997d0bbc..a0b373957838 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -596,32 +596,6 @@ static struct platform_device dm646x_edma_device = {
596 .resource = edma_resources, 596 .resource = edma_resources,
597}; 597};
598 598
599static struct resource ide_resources[] = {
600 {
601 .start = DM646X_ATA_REG_BASE,
602 .end = DM646X_ATA_REG_BASE + 0x7ff,
603 .flags = IORESOURCE_MEM,
604 },
605 {
606 .start = IRQ_DM646X_IDE,
607 .end = IRQ_DM646X_IDE,
608 .flags = IORESOURCE_IRQ,
609 },
610};
611
612static u64 ide_dma_mask = DMA_BIT_MASK(32);
613
614static struct platform_device ide_dev = {
615 .name = "palm_bk3710",
616 .id = -1,
617 .resource = ide_resources,
618 .num_resources = ARRAY_SIZE(ide_resources),
619 .dev = {
620 .dma_mask = &ide_dma_mask,
621 .coherent_dma_mask = DMA_BIT_MASK(32),
622 },
623};
624
625static struct resource dm646x_mcasp0_resources[] = { 599static struct resource dm646x_mcasp0_resources[] = {
626 { 600 {
627 .name = "mcasp0", 601 .name = "mcasp0",
@@ -867,12 +841,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
867 .sram_len = SZ_32K, 841 .sram_len = SZ_32K,
868}; 842};
869 843
870void __init dm646x_init_ide(void)
871{
872 davinci_cfg_reg(DM646X_ATAEN);
873 platform_device_register(&ide_dev);
874}
875
876void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) 844void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
877{ 845{
878 dm646x_mcasp0_device.dev.platform_data = pdata; 846 dm646x_mcasp0_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index d88104e6d66b..884dc726e9b9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -70,6 +70,7 @@ struct davinci_soc_info {
70extern struct davinci_soc_info davinci_soc_info; 70extern struct davinci_soc_info davinci_soc_info;
71 71
72extern void davinci_common_init(struct davinci_soc_info *soc_info); 72extern void davinci_common_init(struct davinci_soc_info *soc_info);
73extern void davinci_init_ide(void);
73 74
74/* standard place to map on-chip SRAMs; they *may* support DMA */ 75/* standard place to map on-chip SRAMs; they *may* support DMA */
75#define SRAM_VIRT 0xfffe0000 76#define SRAM_VIRT 0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 4d62db7b6f94..add6f794a362 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -25,13 +25,10 @@
25#define DM646X_EMAC_MDIO_OFFSET (0x4000) 25#define DM646X_EMAC_MDIO_OFFSET (0x4000)
26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) 26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
27 27
28#define DM646X_ATA_REG_BASE (0x01C66000)
29
30#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 28#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
31#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 29#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
32 30
33void __init dm646x_init(void); 31void __init dm646x_init(void);
34void __init dm646x_init_ide(void);
35void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
36void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
37void __init dm646x_board_setup_refclk(struct clk *clk); 34void __init dm646x_board_setup_refclk(struct clk *clk);