diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-09-15 01:18:20 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 21:10:18 -0500 |
commit | 7a2bd1cc3926327c0393deb52e8300af75b1c9e1 (patch) | |
tree | 0e075412a394f2de3270104e2689f39cfda18a5c /arch | |
parent | ed1ebc4948fdfe4c68865e5543b4a68e5a55973b (diff) |
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
OMAP2420 and OMAP2430 chips each have two on-chip APLLs. When locked,
one APLL generates a 96 MHz rate; the other, a 54 MHz rate.
Previously we treated these clocks as fixed-rate clocks at the locked
rates, but this isn't quite right. The locked rate should be returned
when the APLL is locked, and a zero rate should be returned when the
APLL is stopped. This patch adds the infrastructure that will be used
by the CCF changes.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_apll.c | 35 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 4 |
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 1bd15275dbf9..76a958c6e5bc 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c | |||
@@ -39,6 +39,27 @@ | |||
39 | /* Private functions */ | 39 | /* Private functions */ |
40 | 40 | ||
41 | #ifdef CONFIG_COMMON_CLK | 41 | #ifdef CONFIG_COMMON_CLK |
42 | /** | ||
43 | * omap2xxx_clk_apll_locked - is the APLL locked? | ||
44 | * @hw: struct clk_hw * of the APLL to check | ||
45 | * | ||
46 | * If the APLL IP block referred to by @hw indicates that it's locked, | ||
47 | * return true; otherwise, return false. | ||
48 | */ | ||
49 | static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) | ||
50 | { | ||
51 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | ||
52 | u32 r, apll_mask; | ||
53 | |||
54 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
55 | |||
56 | r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
57 | |||
58 | return ((r & apll_mask) == apll_mask) ? true : false; | ||
59 | } | ||
60 | #endif | ||
61 | |||
62 | #ifdef CONFIG_COMMON_CLK | ||
42 | int omap2_clk_apll96_enable(struct clk_hw *hw) | 63 | int omap2_clk_apll96_enable(struct clk_hw *hw) |
43 | #else | 64 | #else |
44 | static int _apll96_enable(struct clk *clk) | 65 | static int _apll96_enable(struct clk *clk) |
@@ -110,6 +131,20 @@ static void _apll54_disable(struct clk *clk) | |||
110 | omap2xxx_cm_apll54_disable(); | 131 | omap2xxx_cm_apll54_disable(); |
111 | } | 132 | } |
112 | 133 | ||
134 | #ifdef CONFIG_COMMON_CLK | ||
135 | unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, | ||
136 | unsigned long parent_rate) | ||
137 | { | ||
138 | return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0; | ||
139 | } | ||
140 | |||
141 | unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, | ||
142 | unsigned long parent_rate) | ||
143 | { | ||
144 | return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0; | ||
145 | } | ||
146 | #endif | ||
147 | |||
113 | /* Public data */ | 148 | /* Public data */ |
114 | #ifdef CONFIG_COMMON_CLK | 149 | #ifdef CONFIG_COMMON_CLK |
115 | const struct clk_hw_omap_ops clkhwops_apll54 = { | 150 | const struct clk_hw_omap_ops clkhwops_apll54 = { |
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 58581511d795..82147c49a8de 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -27,6 +27,10 @@ unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, | |||
27 | int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, | 27 | int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, |
28 | unsigned long parent_rate); | 28 | unsigned long parent_rate); |
29 | void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); | 29 | void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); |
30 | unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, | ||
31 | unsigned long parent_rate); | ||
32 | unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, | ||
33 | unsigned long parent_rate); | ||
30 | #else | 34 | #else |
31 | unsigned long omap2_table_mpu_recalc(struct clk *clk); | 35 | unsigned long omap2_table_mpu_recalc(struct clk *clk); |
32 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); | 36 | int omap2_select_table_rate(struct clk *clk, unsigned long rate); |