diff options
author | Avi Kivity <avi@redhat.com> | 2011-09-07 09:41:36 -0400 |
---|---|---|
committer | Avi Kivity <avi@redhat.com> | 2011-09-25 12:52:33 -0400 |
commit | 761441b9f42159409d56f74dcc7ce5538d9efd69 (patch) | |
tree | 33f143f22a38465f7b99ac95194eb86f914ef32d /arch | |
parent | a31b9ceadb61487042dec92f662736ccddadc75f (diff) |
KVM: x86 emulator: simplify emulate_2op_cl()
emulate_2op_cl() is always called with the same parameters. Simplify
by passing just the emulation context.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kvm/emulate.c | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 458914d0f4b0..0b338849c689 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c | |||
@@ -263,40 +263,37 @@ struct gprefix { | |||
263 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | 263 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") |
264 | 264 | ||
265 | /* Instruction has three operands and one operand is stored in ECX register */ | 265 | /* Instruction has three operands and one operand is stored in ECX register */ |
266 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | 266 | #define __emulate_2op_cl(_op, ctxt, _suffix, _type) \ |
267 | do { \ | 267 | do { \ |
268 | unsigned long _tmp; \ | 268 | unsigned long _tmp; \ |
269 | _type _clv = (_cl).val; \ | 269 | _type _clv = (ctxt)->src2.val; \ |
270 | _type _srcv = (_src).val; \ | 270 | _type _srcv = (ctxt)->src.val; \ |
271 | _type _dstv = (_dst).val; \ | 271 | _type _dstv = (ctxt)->dst.val; \ |
272 | \ | 272 | \ |
273 | __asm__ __volatile__ ( \ | 273 | __asm__ __volatile__ ( \ |
274 | _PRE_EFLAGS("0", "5", "2") \ | 274 | _PRE_EFLAGS("0", "5", "2") \ |
275 | _op _suffix " %4,%1 \n" \ | 275 | _op _suffix " %4,%1 \n" \ |
276 | _POST_EFLAGS("0", "5", "2") \ | 276 | _POST_EFLAGS("0", "5", "2") \ |
277 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | 277 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
278 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | 278 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
279 | ); \ | 279 | ); \ |
280 | \ | 280 | \ |
281 | (_cl).val = (unsigned long) _clv; \ | 281 | (ctxt)->src2.val = (unsigned long) _clv; \ |
282 | (_src).val = (unsigned long) _srcv; \ | 282 | (ctxt)->src2.val = (unsigned long) _srcv; \ |
283 | (_dst).val = (unsigned long) _dstv; \ | 283 | (ctxt)->dst.val = (unsigned long) _dstv; \ |
284 | } while (0) | 284 | } while (0) |
285 | 285 | ||
286 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | 286 | #define emulate_2op_cl(ctxt, _op) \ |
287 | do { \ | 287 | do { \ |
288 | switch ((_dst).bytes) { \ | 288 | switch ((ctxt)->dst.bytes) { \ |
289 | case 2: \ | 289 | case 2: \ |
290 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | 290 | __emulate_2op_cl(_op, ctxt, "w", u16); \ |
291 | "w", unsigned short); \ | ||
292 | break; \ | 291 | break; \ |
293 | case 4: \ | 292 | case 4: \ |
294 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | 293 | __emulate_2op_cl(_op, ctxt, "l", u32); \ |
295 | "l", unsigned int); \ | ||
296 | break; \ | 294 | break; \ |
297 | case 8: \ | 295 | case 8: \ |
298 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | 296 | ON64(__emulate_2op_cl(_op, ctxt, "q", ulong)); \ |
299 | "q", unsigned long)); \ | ||
300 | break; \ | 297 | break; \ |
301 | } \ | 298 | } \ |
302 | } while (0) | 299 | } while (0) |
@@ -4123,7 +4120,7 @@ twobyte_insn: | |||
4123 | break; | 4120 | break; |
4124 | case 0xa4: /* shld imm8, r, r/m */ | 4121 | case 0xa4: /* shld imm8, r, r/m */ |
4125 | case 0xa5: /* shld cl, r, r/m */ | 4122 | case 0xa5: /* shld cl, r, r/m */ |
4126 | emulate_2op_cl("shld", ctxt->src2, ctxt->src, ctxt->dst, ctxt->eflags); | 4123 | emulate_2op_cl(ctxt, "shld"); |
4127 | break; | 4124 | break; |
4128 | case 0xa8: /* push gs */ | 4125 | case 0xa8: /* push gs */ |
4129 | rc = emulate_push_sreg(ctxt, VCPU_SREG_GS); | 4126 | rc = emulate_push_sreg(ctxt, VCPU_SREG_GS); |
@@ -4137,7 +4134,7 @@ twobyte_insn: | |||
4137 | break; | 4134 | break; |
4138 | case 0xac: /* shrd imm8, r, r/m */ | 4135 | case 0xac: /* shrd imm8, r, r/m */ |
4139 | case 0xad: /* shrd cl, r, r/m */ | 4136 | case 0xad: /* shrd cl, r, r/m */ |
4140 | emulate_2op_cl("shrd", ctxt->src2, ctxt->src, ctxt->dst, ctxt->eflags); | 4137 | emulate_2op_cl(ctxt, "shrd"); |
4141 | break; | 4138 | break; |
4142 | case 0xae: /* clflush */ | 4139 | case 0xae: /* clflush */ |
4143 | break; | 4140 | break; |