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authorDavid Daney <david.daney@cavium.com>2011-11-22 09:46:49 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:28 -0500
commit751c9f684963d2a066a79d8022c0e79e1159291b (patch)
tree9a196a7c5bab11fe4e089e691e2f00593e51826a /arch
parent506d24be55d510c7ff79a0cdcabd00649b979bc9 (diff)
MIPS: Oceton: Update model detection code for new chips.
Several newer chips were not covered, update the code to detect them. This necessitates updating cvmx-mio-defs.h as well, because it has new and required definitions. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2939/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cavium-octeon/executive/octeon-model.c119
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h1033
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h215
3 files changed, 1179 insertions, 188 deletions
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index c8d35684504e..f4c1b36fdf65 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,10 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28/*
29 * File defining functions for working with different Octeon
30 * models.
31 */
32#include <asm/octeon/octeon.h> 28#include <asm/octeon/octeon.h>
33 29
34/** 30/**
@@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
69 char fuse_model[10]; 65 char fuse_model[10];
70 uint32_t fuse_data = 0; 66 uint32_t fuse_data = 0;
71 67
72 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 68 fus3.u64 = 0;
69 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
70 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
73 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); 71 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
74 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); 72 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
75 73 num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
76 num_cores = cvmx_octeon_num_cores();
77 74
78 /* Make sure the non existent devices look disabled */ 75 /* Make sure the non existent devices look disabled */
79 switch ((chip_id >> 8) & 0xff) { 76 switch ((chip_id >> 8) & 0xff) {
@@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
108 * Assume pass number is encoded using <5:3><2:0>. Exceptions 105 * Assume pass number is encoded using <5:3><2:0>. Exceptions
109 * will be fixed later. 106 * will be fixed later.
110 */ 107 */
111 sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7); 108 sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
112 109
113 /* 110 /*
114 * Use the number of cores to determine the last 2 digits of 111 * Use the number of cores to determine the last 2 digits of
@@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
116 * later. 113 * later.
117 */ 114 */
118 switch (num_cores) { 115 switch (num_cores) {
116 case 32:
117 core_model = "80";
118 break;
119 case 24:
120 core_model = "70";
121 break;
119 case 16: 122 case 16:
120 core_model = "60"; 123 core_model = "60";
121 break; 124 break;
@@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
246 break; 249 break;
247 case 3: /* CN58XX */ 250 case 3: /* CN58XX */
248 family = "58"; 251 family = "58";
249 /* Special case. 4 core, no crypto */ 252 /* Special case. 4 core, half cache (CP with half cache) */
250 if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto) 253 if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
251 core_model = "29"; 254 core_model = "29";
252 255
253 /* Pass 1 uses different encodings for pass numbers */ 256 /* Pass 1 uses different encodings for pass numbers */
@@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
285 suffix = "NSP"; 288 suffix = "NSP";
286 if (fus_dat3.s.nozip) 289 if (fus_dat3.s.nozip)
287 suffix = "SCP"; 290 suffix = "SCP";
291
292 if (fus_dat3.s.bar2_en)
293 suffix = "NSPB2";
288 } 294 }
289 if (fus3.cn56xx.crip_1024k) 295 if (fus3.cn56xx.crip_1024k)
290 family = "54"; 296 family = "54";
@@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
301 else 307 else
302 family = "52"; 308 family = "52";
303 break; 309 break;
310 case 0x93: /* CN61XX */
311 family = "61";
312 if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
313 suffix = "AP";
314 if (fus_dat2.cn61xx.nocrypto)
315 suffix = "CP";
316 else if (fus_dat2.cn61xx.dorm_crypto)
317 suffix = "DAP";
318 else if (fus_dat3.cn61xx.nozip)
319 suffix = "SCP";
320 break;
321 case 0x90: /* CN63XX */
322 family = "63";
323 if (fus_dat3.s.l2c_crip == 2)
324 family = "62";
325 if (num_cores == 6) /* Other core counts match generic */
326 core_model = "35";
327 if (fus_dat2.cn63xx.nocrypto)
328 suffix = "CP";
329 else if (fus_dat2.cn63xx.dorm_crypto)
330 suffix = "DAP";
331 else if (fus_dat3.cn63xx.nozip)
332 suffix = "SCP";
333 else
334 suffix = "AAP";
335 break;
336 case 0x92: /* CN66XX */
337 family = "66";
338 if (num_cores == 6) /* Other core counts match generic */
339 core_model = "35";
340 if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
341 suffix = "AP";
342 if (fus_dat2.cn66xx.nocrypto)
343 suffix = "CP";
344 else if (fus_dat2.cn66xx.dorm_crypto)
345 suffix = "DAP";
346 else if (fus_dat3.cn66xx.nozip)
347 suffix = "SCP";
348 else
349 suffix = "AAP";
350 break;
351 case 0x91: /* CN68XX */
352 family = "68";
353 if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
354 suffix = "CP";
355 else if (fus_dat2.cn68xx.dorm_crypto)
356 suffix = "DAP";
357 else if (fus_dat3.cn68xx.nozip)
358 suffix = "SCP";
359 else if (fus_dat2.cn68xx.nocrypto)
360 suffix = "SP";
361 else
362 suffix = "AAP";
363 break;
304 default: 364 default:
305 family = "XX"; 365 family = "XX";
306 core_model = "XX"; 366 core_model = "XX";
@@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
310 } 370 }
311 371
312 clock_mhz = octeon_get_clock_rate() / 1000000; 372 clock_mhz = octeon_get_clock_rate() / 1000000;
313
314 if (family[0] != '3') { 373 if (family[0] != '3') {
374 int fuse_base = 384 / 8;
375 if (family[0] == '6')
376 fuse_base = 832 / 8;
377
315 /* Check for model in fuses, overrides normal decode */ 378 /* Check for model in fuses, overrides normal decode */
316 /* This is _not_ valid for Octeon CN3XXX models */ 379 /* This is _not_ valid for Octeon CN3XXX models */
317 fuse_data |= cvmx_fuse_read_byte(51); 380 fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
318 fuse_data = fuse_data << 8; 381 fuse_data = fuse_data << 8;
319 fuse_data |= cvmx_fuse_read_byte(50); 382 fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
320 fuse_data = fuse_data << 8; 383 fuse_data = fuse_data << 8;
321 fuse_data |= cvmx_fuse_read_byte(49); 384 fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
322 fuse_data = fuse_data << 8; 385 fuse_data = fuse_data << 8;
323 fuse_data |= cvmx_fuse_read_byte(48); 386 fuse_data |= cvmx_fuse_read_byte(fuse_base);
324 if (fuse_data & 0x7ffff) { 387 if (fuse_data & 0x7ffff) {
325 int model = fuse_data & 0x3fff; 388 int model = fuse_data & 0x3fff;
326 int suffix = (fuse_data >> 14) & 0x1f; 389 int suffix = (fuse_data >> 14) & 0x1f;
327 if (suffix && model) { 390 if (suffix && model) {
328 /* 391 /* Have both number and suffix in fuses, so both */
329 * Have both number and suffix in 392 sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
330 * fuses, so both
331 */
332 sprintf(fuse_model, "%d%c",
333 model, 'A' + suffix - 1);
334 core_model = ""; 393 core_model = "";
335 family = fuse_model; 394 family = fuse_model;
336 } else if (suffix && !model) { 395 } else if (suffix && !model) {
337 /* 396 /* Only have suffix, so add suffix to 'normal' model number */
338 * Only have suffix, so add suffix to 397 sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
339 * 'normal' model number.
340 */
341 sprintf(fuse_model, "%s%c", core_model,
342 'A' + suffix - 1);
343 core_model = fuse_model; 398 core_model = fuse_model;
344 } else { 399 } else {
345 /* 400 /* Don't have suffix, so just use model from fuses */
346 * Don't have suffix, so just use
347 * model from fuses.
348 */
349 sprintf(fuse_model, "%d", model); 401 sprintf(fuse_model, "%d", model);
350 core_model = ""; 402 core_model = "";
351 family = fuse_model; 403 family = fuse_model;
352 } 404 }
353 } 405 }
354 } 406 }
355 sprintf(buffer, "CN%s%sp%s-%d-%s", 407 sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
356 family, core_model, pass, clock_mhz, suffix);
357 return buffer; 408 return buffer;
358} 409}
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 52b14a333ad4..b1774126736d 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -43,6 +43,22 @@
43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
46#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 62#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
47#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 63#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
48#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 64#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -60,6 +76,7 @@
60#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 76#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
61#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 77#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
62#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 78#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
79#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
63#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 80#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
64#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 81#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
65#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 82#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -68,14 +85,25 @@
68#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 85#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
69#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 86#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
70#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 87#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
88#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
71#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 92#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
72#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 93#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
73#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 94#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
74#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 95#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
75#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 96#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
97#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
98#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
99#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
100#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
76#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 101#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
102#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
77#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 103#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
78#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 104#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
105#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
106#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
79#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 107#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
80#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 108#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
81#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 109#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat {
183 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 211 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
184 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 212 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
185 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 213 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
214 struct cvmx_mio_boot_bist_stat_cn61xx {
215 uint64_t reserved_12_63:52;
216 uint64_t stat:12;
217 } cn61xx;
186 struct cvmx_mio_boot_bist_stat_cn63xx { 218 struct cvmx_mio_boot_bist_stat_cn63xx {
187 uint64_t reserved_9_63:55; 219 uint64_t reserved_9_63:55;
188 uint64_t stat:9; 220 uint64_t stat:9;
189 } cn63xx; 221 } cn63xx;
190 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 222 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
223 struct cvmx_mio_boot_bist_stat_cn66xx {
224 uint64_t reserved_10_63:54;
225 uint64_t stat:10;
226 } cn66xx;
227 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
228 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
191}; 229};
192 230
193union cvmx_mio_boot_comp { 231union cvmx_mio_boot_comp {
@@ -204,12 +242,16 @@ union cvmx_mio_boot_comp {
204 struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 242 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
205 struct cvmx_mio_boot_comp_cn50xx cn56xx; 243 struct cvmx_mio_boot_comp_cn50xx cn56xx;
206 struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 244 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
207 struct cvmx_mio_boot_comp_cn63xx { 245 struct cvmx_mio_boot_comp_cn61xx {
208 uint64_t reserved_12_63:52; 246 uint64_t reserved_12_63:52;
209 uint64_t pctl:6; 247 uint64_t pctl:6;
210 uint64_t nctl:6; 248 uint64_t nctl:6;
211 } cn63xx; 249 } cn61xx;
212 struct cvmx_mio_boot_comp_cn63xx cn63xxp1; 250 struct cvmx_mio_boot_comp_cn61xx cn63xx;
251 struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
252 struct cvmx_mio_boot_comp_cn61xx cn66xx;
253 struct cvmx_mio_boot_comp_cn61xx cn68xx;
254 struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
213}; 255};
214 256
215union cvmx_mio_boot_dma_cfgx { 257union cvmx_mio_boot_dma_cfgx {
@@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx {
230 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 272 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
231 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 273 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
232 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 274 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
275 struct cvmx_mio_boot_dma_cfgx_s cn61xx;
233 struct cvmx_mio_boot_dma_cfgx_s cn63xx; 276 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
234 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 277 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
278 struct cvmx_mio_boot_dma_cfgx_s cn66xx;
279 struct cvmx_mio_boot_dma_cfgx_s cn68xx;
280 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
235}; 281};
236 282
237union cvmx_mio_boot_dma_intx { 283union cvmx_mio_boot_dma_intx {
@@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx {
245 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 291 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
246 struct cvmx_mio_boot_dma_intx_s cn56xx; 292 struct cvmx_mio_boot_dma_intx_s cn56xx;
247 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 293 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
294 struct cvmx_mio_boot_dma_intx_s cn61xx;
248 struct cvmx_mio_boot_dma_intx_s cn63xx; 295 struct cvmx_mio_boot_dma_intx_s cn63xx;
249 struct cvmx_mio_boot_dma_intx_s cn63xxp1; 296 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
297 struct cvmx_mio_boot_dma_intx_s cn66xx;
298 struct cvmx_mio_boot_dma_intx_s cn68xx;
299 struct cvmx_mio_boot_dma_intx_s cn68xxp1;
250}; 300};
251 301
252union cvmx_mio_boot_dma_int_enx { 302union cvmx_mio_boot_dma_int_enx {
@@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx {
260 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 310 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
261 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 311 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
262 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 312 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
313 struct cvmx_mio_boot_dma_int_enx_s cn61xx;
263 struct cvmx_mio_boot_dma_int_enx_s cn63xx; 314 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
264 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 315 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
316 struct cvmx_mio_boot_dma_int_enx_s cn66xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn68xx;
318 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
265}; 319};
266 320
267union cvmx_mio_boot_dma_timx { 321union cvmx_mio_boot_dma_timx {
@@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx {
287 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 341 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
288 struct cvmx_mio_boot_dma_timx_s cn56xx; 342 struct cvmx_mio_boot_dma_timx_s cn56xx;
289 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 343 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
344 struct cvmx_mio_boot_dma_timx_s cn61xx;
290 struct cvmx_mio_boot_dma_timx_s cn63xx; 345 struct cvmx_mio_boot_dma_timx_s cn63xx;
291 struct cvmx_mio_boot_dma_timx_s cn63xxp1; 346 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
347 struct cvmx_mio_boot_dma_timx_s cn66xx;
348 struct cvmx_mio_boot_dma_timx_s cn68xx;
349 struct cvmx_mio_boot_dma_timx_s cn68xxp1;
292}; 350};
293 351
294union cvmx_mio_boot_err { 352union cvmx_mio_boot_err {
@@ -309,8 +367,12 @@ union cvmx_mio_boot_err {
309 struct cvmx_mio_boot_err_s cn56xxp1; 367 struct cvmx_mio_boot_err_s cn56xxp1;
310 struct cvmx_mio_boot_err_s cn58xx; 368 struct cvmx_mio_boot_err_s cn58xx;
311 struct cvmx_mio_boot_err_s cn58xxp1; 369 struct cvmx_mio_boot_err_s cn58xxp1;
370 struct cvmx_mio_boot_err_s cn61xx;
312 struct cvmx_mio_boot_err_s cn63xx; 371 struct cvmx_mio_boot_err_s cn63xx;
313 struct cvmx_mio_boot_err_s cn63xxp1; 372 struct cvmx_mio_boot_err_s cn63xxp1;
373 struct cvmx_mio_boot_err_s cn66xx;
374 struct cvmx_mio_boot_err_s cn68xx;
375 struct cvmx_mio_boot_err_s cn68xxp1;
314}; 376};
315 377
316union cvmx_mio_boot_int { 378union cvmx_mio_boot_int {
@@ -331,8 +393,12 @@ union cvmx_mio_boot_int {
331 struct cvmx_mio_boot_int_s cn56xxp1; 393 struct cvmx_mio_boot_int_s cn56xxp1;
332 struct cvmx_mio_boot_int_s cn58xx; 394 struct cvmx_mio_boot_int_s cn58xx;
333 struct cvmx_mio_boot_int_s cn58xxp1; 395 struct cvmx_mio_boot_int_s cn58xxp1;
396 struct cvmx_mio_boot_int_s cn61xx;
334 struct cvmx_mio_boot_int_s cn63xx; 397 struct cvmx_mio_boot_int_s cn63xx;
335 struct cvmx_mio_boot_int_s cn63xxp1; 398 struct cvmx_mio_boot_int_s cn63xxp1;
399 struct cvmx_mio_boot_int_s cn66xx;
400 struct cvmx_mio_boot_int_s cn68xx;
401 struct cvmx_mio_boot_int_s cn68xxp1;
336}; 402};
337 403
338union cvmx_mio_boot_loc_adr { 404union cvmx_mio_boot_loc_adr {
@@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr {
353 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 419 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
354 struct cvmx_mio_boot_loc_adr_s cn58xx; 420 struct cvmx_mio_boot_loc_adr_s cn58xx;
355 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 421 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
422 struct cvmx_mio_boot_loc_adr_s cn61xx;
356 struct cvmx_mio_boot_loc_adr_s cn63xx; 423 struct cvmx_mio_boot_loc_adr_s cn63xx;
357 struct cvmx_mio_boot_loc_adr_s cn63xxp1; 424 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
425 struct cvmx_mio_boot_loc_adr_s cn66xx;
426 struct cvmx_mio_boot_loc_adr_s cn68xx;
427 struct cvmx_mio_boot_loc_adr_s cn68xxp1;
358}; 428};
359 429
360union cvmx_mio_boot_loc_cfgx { 430union cvmx_mio_boot_loc_cfgx {
@@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx {
377 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 447 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
378 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 448 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
379 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 449 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
450 struct cvmx_mio_boot_loc_cfgx_s cn61xx;
380 struct cvmx_mio_boot_loc_cfgx_s cn63xx; 451 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
381 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 452 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
453 struct cvmx_mio_boot_loc_cfgx_s cn66xx;
454 struct cvmx_mio_boot_loc_cfgx_s cn68xx;
455 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
382}; 456};
383 457
384union cvmx_mio_boot_loc_dat { 458union cvmx_mio_boot_loc_dat {
@@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat {
397 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 471 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
398 struct cvmx_mio_boot_loc_dat_s cn58xx; 472 struct cvmx_mio_boot_loc_dat_s cn58xx;
399 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 473 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
474 struct cvmx_mio_boot_loc_dat_s cn61xx;
400 struct cvmx_mio_boot_loc_dat_s cn63xx; 475 struct cvmx_mio_boot_loc_dat_s cn63xx;
401 struct cvmx_mio_boot_loc_dat_s cn63xxp1; 476 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
477 struct cvmx_mio_boot_loc_dat_s cn66xx;
478 struct cvmx_mio_boot_loc_dat_s cn68xx;
479 struct cvmx_mio_boot_loc_dat_s cn68xxp1;
402}; 480};
403 481
404union cvmx_mio_boot_pin_defs { 482union cvmx_mio_boot_pin_defs {
405 uint64_t u64; 483 uint64_t u64;
406 struct cvmx_mio_boot_pin_defs_s { 484 struct cvmx_mio_boot_pin_defs_s {
407 uint64_t reserved_16_63:48; 485 uint64_t reserved_32_63:32;
486 uint64_t user1:16;
408 uint64_t ale:1; 487 uint64_t ale:1;
409 uint64_t width:1; 488 uint64_t width:1;
410 uint64_t dmack_p2:1; 489 uint64_t dmack_p2:1;
@@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs {
412 uint64_t dmack_p0:1; 491 uint64_t dmack_p0:1;
413 uint64_t term:2; 492 uint64_t term:2;
414 uint64_t nand:1; 493 uint64_t nand:1;
415 uint64_t reserved_0_7:8; 494 uint64_t user0:8;
416 } s; 495 } s;
417 struct cvmx_mio_boot_pin_defs_cn52xx { 496 struct cvmx_mio_boot_pin_defs_cn52xx {
418 uint64_t reserved_16_63:48; 497 uint64_t reserved_16_63:48;
@@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs {
435 uint64_t term:2; 514 uint64_t term:2;
436 uint64_t reserved_0_8:9; 515 uint64_t reserved_0_8:9;
437 } cn56xx; 516 } cn56xx;
517 struct cvmx_mio_boot_pin_defs_cn61xx {
518 uint64_t reserved_32_63:32;
519 uint64_t user1:16;
520 uint64_t ale:1;
521 uint64_t width:1;
522 uint64_t reserved_13_13:1;
523 uint64_t dmack_p1:1;
524 uint64_t dmack_p0:1;
525 uint64_t term:2;
526 uint64_t nand:1;
527 uint64_t user0:8;
528 } cn61xx;
438 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 529 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
439 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 530 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
531 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
532 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
533 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
440}; 534};
441 535
442union cvmx_mio_boot_reg_cfgx { 536union cvmx_mio_boot_reg_cfgx {
@@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx {
498 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 592 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
499 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 593 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 594 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
595 struct cvmx_mio_boot_reg_cfgx_s cn61xx;
501 struct cvmx_mio_boot_reg_cfgx_s cn63xx; 596 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
502 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 597 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
598 struct cvmx_mio_boot_reg_cfgx_s cn66xx;
599 struct cvmx_mio_boot_reg_cfgx_s cn68xx;
600 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
503}; 601};
504 602
505union cvmx_mio_boot_reg_timx { 603union cvmx_mio_boot_reg_timx {
@@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx {
544 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 642 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
545 struct cvmx_mio_boot_reg_timx_s cn58xx; 643 struct cvmx_mio_boot_reg_timx_s cn58xx;
546 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 644 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
645 struct cvmx_mio_boot_reg_timx_s cn61xx;
547 struct cvmx_mio_boot_reg_timx_s cn63xx; 646 struct cvmx_mio_boot_reg_timx_s cn63xx;
548 struct cvmx_mio_boot_reg_timx_s cn63xxp1; 647 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
648 struct cvmx_mio_boot_reg_timx_s cn66xx;
649 struct cvmx_mio_boot_reg_timx_s cn68xx;
650 struct cvmx_mio_boot_reg_timx_s cn68xxp1;
549}; 651};
550 652
551union cvmx_mio_boot_thr { 653union cvmx_mio_boot_thr {
@@ -574,8 +676,231 @@ union cvmx_mio_boot_thr {
574 struct cvmx_mio_boot_thr_s cn56xxp1; 676 struct cvmx_mio_boot_thr_s cn56xxp1;
575 struct cvmx_mio_boot_thr_cn30xx cn58xx; 677 struct cvmx_mio_boot_thr_cn30xx cn58xx;
576 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 678 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
679 struct cvmx_mio_boot_thr_s cn61xx;
577 struct cvmx_mio_boot_thr_s cn63xx; 680 struct cvmx_mio_boot_thr_s cn63xx;
578 struct cvmx_mio_boot_thr_s cn63xxp1; 681 struct cvmx_mio_boot_thr_s cn63xxp1;
682 struct cvmx_mio_boot_thr_s cn66xx;
683 struct cvmx_mio_boot_thr_s cn68xx;
684 struct cvmx_mio_boot_thr_s cn68xxp1;
685};
686
687union cvmx_mio_emm_buf_dat {
688 uint64_t u64;
689 struct cvmx_mio_emm_buf_dat_s {
690 uint64_t dat:64;
691 } s;
692 struct cvmx_mio_emm_buf_dat_s cn61xx;
693};
694
695union cvmx_mio_emm_buf_idx {
696 uint64_t u64;
697 struct cvmx_mio_emm_buf_idx_s {
698 uint64_t reserved_17_63:47;
699 uint64_t inc:1;
700 uint64_t reserved_7_15:9;
701 uint64_t buf_num:1;
702 uint64_t offset:6;
703 } s;
704 struct cvmx_mio_emm_buf_idx_s cn61xx;
705};
706
707union cvmx_mio_emm_cfg {
708 uint64_t u64;
709 struct cvmx_mio_emm_cfg_s {
710 uint64_t reserved_17_63:47;
711 uint64_t boot_fail:1;
712 uint64_t reserved_4_15:12;
713 uint64_t bus_ena:4;
714 } s;
715 struct cvmx_mio_emm_cfg_s cn61xx;
716};
717
718union cvmx_mio_emm_cmd {
719 uint64_t u64;
720 struct cvmx_mio_emm_cmd_s {
721 uint64_t reserved_62_63:2;
722 uint64_t bus_id:2;
723 uint64_t cmd_val:1;
724 uint64_t reserved_56_58:3;
725 uint64_t dbuf:1;
726 uint64_t offset:6;
727 uint64_t reserved_43_48:6;
728 uint64_t ctype_xor:2;
729 uint64_t rtype_xor:3;
730 uint64_t cmd_idx:6;
731 uint64_t arg:32;
732 } s;
733 struct cvmx_mio_emm_cmd_s cn61xx;
734};
735
736union cvmx_mio_emm_dma {
737 uint64_t u64;
738 struct cvmx_mio_emm_dma_s {
739 uint64_t reserved_62_63:2;
740 uint64_t bus_id:2;
741 uint64_t dma_val:1;
742 uint64_t sector:1;
743 uint64_t dat_null:1;
744 uint64_t thres:6;
745 uint64_t rel_wr:1;
746 uint64_t rw:1;
747 uint64_t multi:1;
748 uint64_t block_cnt:16;
749 uint64_t card_addr:32;
750 } s;
751 struct cvmx_mio_emm_dma_s cn61xx;
752};
753
754union cvmx_mio_emm_int {
755 uint64_t u64;
756 struct cvmx_mio_emm_int_s {
757 uint64_t reserved_7_63:57;
758 uint64_t switch_err:1;
759 uint64_t switch_done:1;
760 uint64_t dma_err:1;
761 uint64_t cmd_err:1;
762 uint64_t dma_done:1;
763 uint64_t cmd_done:1;
764 uint64_t buf_done:1;
765 } s;
766 struct cvmx_mio_emm_int_s cn61xx;
767};
768
769union cvmx_mio_emm_int_en {
770 uint64_t u64;
771 struct cvmx_mio_emm_int_en_s {
772 uint64_t reserved_7_63:57;
773 uint64_t switch_err:1;
774 uint64_t switch_done:1;
775 uint64_t dma_err:1;
776 uint64_t cmd_err:1;
777 uint64_t dma_done:1;
778 uint64_t cmd_done:1;
779 uint64_t buf_done:1;
780 } s;
781 struct cvmx_mio_emm_int_en_s cn61xx;
782};
783
784union cvmx_mio_emm_modex {
785 uint64_t u64;
786 struct cvmx_mio_emm_modex_s {
787 uint64_t reserved_49_63:15;
788 uint64_t hs_timing:1;
789 uint64_t reserved_43_47:5;
790 uint64_t bus_width:3;
791 uint64_t reserved_36_39:4;
792 uint64_t power_class:4;
793 uint64_t clk_hi:16;
794 uint64_t clk_lo:16;
795 } s;
796 struct cvmx_mio_emm_modex_s cn61xx;
797};
798
799union cvmx_mio_emm_rca {
800 uint64_t u64;
801 struct cvmx_mio_emm_rca_s {
802 uint64_t reserved_16_63:48;
803 uint64_t card_rca:16;
804 } s;
805 struct cvmx_mio_emm_rca_s cn61xx;
806};
807
808union cvmx_mio_emm_rsp_hi {
809 uint64_t u64;
810 struct cvmx_mio_emm_rsp_hi_s {
811 uint64_t dat:64;
812 } s;
813 struct cvmx_mio_emm_rsp_hi_s cn61xx;
814};
815
816union cvmx_mio_emm_rsp_lo {
817 uint64_t u64;
818 struct cvmx_mio_emm_rsp_lo_s {
819 uint64_t dat:64;
820 } s;
821 struct cvmx_mio_emm_rsp_lo_s cn61xx;
822};
823
824union cvmx_mio_emm_rsp_sts {
825 uint64_t u64;
826 struct cvmx_mio_emm_rsp_sts_s {
827 uint64_t reserved_62_63:2;
828 uint64_t bus_id:2;
829 uint64_t cmd_val:1;
830 uint64_t switch_val:1;
831 uint64_t dma_val:1;
832 uint64_t dma_pend:1;
833 uint64_t reserved_29_55:27;
834 uint64_t dbuf_err:1;
835 uint64_t reserved_24_27:4;
836 uint64_t dbuf:1;
837 uint64_t blk_timeout:1;
838 uint64_t blk_crc_err:1;
839 uint64_t rsp_busybit:1;
840 uint64_t stp_timeout:1;
841 uint64_t stp_crc_err:1;
842 uint64_t stp_bad_sts:1;
843 uint64_t stp_val:1;
844 uint64_t rsp_timeout:1;
845 uint64_t rsp_crc_err:1;
846 uint64_t rsp_bad_sts:1;
847 uint64_t rsp_val:1;
848 uint64_t rsp_type:3;
849 uint64_t cmd_type:2;
850 uint64_t cmd_idx:6;
851 uint64_t cmd_done:1;
852 } s;
853 struct cvmx_mio_emm_rsp_sts_s cn61xx;
854};
855
856union cvmx_mio_emm_sample {
857 uint64_t u64;
858 struct cvmx_mio_emm_sample_s {
859 uint64_t reserved_26_63:38;
860 uint64_t cmd_cnt:10;
861 uint64_t reserved_10_15:6;
862 uint64_t dat_cnt:10;
863 } s;
864 struct cvmx_mio_emm_sample_s cn61xx;
865};
866
867union cvmx_mio_emm_sts_mask {
868 uint64_t u64;
869 struct cvmx_mio_emm_sts_mask_s {
870 uint64_t reserved_32_63:32;
871 uint64_t sts_msk:32;
872 } s;
873 struct cvmx_mio_emm_sts_mask_s cn61xx;
874};
875
876union cvmx_mio_emm_switch {
877 uint64_t u64;
878 struct cvmx_mio_emm_switch_s {
879 uint64_t reserved_62_63:2;
880 uint64_t bus_id:2;
881 uint64_t switch_exe:1;
882 uint64_t switch_err0:1;
883 uint64_t switch_err1:1;
884 uint64_t switch_err2:1;
885 uint64_t reserved_49_55:7;
886 uint64_t hs_timing:1;
887 uint64_t reserved_43_47:5;
888 uint64_t bus_width:3;
889 uint64_t reserved_36_39:4;
890 uint64_t power_class:4;
891 uint64_t clk_hi:16;
892 uint64_t clk_lo:16;
893 } s;
894 struct cvmx_mio_emm_switch_s cn61xx;
895};
896
897union cvmx_mio_emm_wdog {
898 uint64_t u64;
899 struct cvmx_mio_emm_wdog_s {
900 uint64_t reserved_26_63:38;
901 uint64_t clk_cnt:26;
902 } s;
903 struct cvmx_mio_emm_wdog_s cn61xx;
579}; 904};
580 905
581union cvmx_mio_fus_bnk_datx { 906union cvmx_mio_fus_bnk_datx {
@@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx {
590 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 915 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
591 struct cvmx_mio_fus_bnk_datx_s cn58xx; 916 struct cvmx_mio_fus_bnk_datx_s cn58xx;
592 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 917 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
918 struct cvmx_mio_fus_bnk_datx_s cn61xx;
593 struct cvmx_mio_fus_bnk_datx_s cn63xx; 919 struct cvmx_mio_fus_bnk_datx_s cn63xx;
594 struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 920 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
921 struct cvmx_mio_fus_bnk_datx_s cn66xx;
922 struct cvmx_mio_fus_bnk_datx_s cn68xx;
923 struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
595}; 924};
596 925
597union cvmx_mio_fus_dat0 { 926union cvmx_mio_fus_dat0 {
@@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 {
611 struct cvmx_mio_fus_dat0_s cn56xxp1; 940 struct cvmx_mio_fus_dat0_s cn56xxp1;
612 struct cvmx_mio_fus_dat0_s cn58xx; 941 struct cvmx_mio_fus_dat0_s cn58xx;
613 struct cvmx_mio_fus_dat0_s cn58xxp1; 942 struct cvmx_mio_fus_dat0_s cn58xxp1;
943 struct cvmx_mio_fus_dat0_s cn61xx;
614 struct cvmx_mio_fus_dat0_s cn63xx; 944 struct cvmx_mio_fus_dat0_s cn63xx;
615 struct cvmx_mio_fus_dat0_s cn63xxp1; 945 struct cvmx_mio_fus_dat0_s cn63xxp1;
946 struct cvmx_mio_fus_dat0_s cn66xx;
947 struct cvmx_mio_fus_dat0_s cn68xx;
948 struct cvmx_mio_fus_dat0_s cn68xxp1;
616}; 949};
617 950
618union cvmx_mio_fus_dat1 { 951union cvmx_mio_fus_dat1 {
@@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 {
632 struct cvmx_mio_fus_dat1_s cn56xxp1; 965 struct cvmx_mio_fus_dat1_s cn56xxp1;
633 struct cvmx_mio_fus_dat1_s cn58xx; 966 struct cvmx_mio_fus_dat1_s cn58xx;
634 struct cvmx_mio_fus_dat1_s cn58xxp1; 967 struct cvmx_mio_fus_dat1_s cn58xxp1;
968 struct cvmx_mio_fus_dat1_s cn61xx;
635 struct cvmx_mio_fus_dat1_s cn63xx; 969 struct cvmx_mio_fus_dat1_s cn63xx;
636 struct cvmx_mio_fus_dat1_s cn63xxp1; 970 struct cvmx_mio_fus_dat1_s cn63xxp1;
971 struct cvmx_mio_fus_dat1_s cn66xx;
972 struct cvmx_mio_fus_dat1_s cn68xx;
973 struct cvmx_mio_fus_dat1_s cn68xxp1;
637}; 974};
638 975
639union cvmx_mio_fus_dat2 { 976union cvmx_mio_fus_dat2 {
640 uint64_t u64; 977 uint64_t u64;
641 struct cvmx_mio_fus_dat2_s { 978 struct cvmx_mio_fus_dat2_s {
642 uint64_t reserved_35_63:29; 979 uint64_t reserved_48_63:16;
980 uint64_t fus118:1;
981 uint64_t rom_info:10;
982 uint64_t power_limit:2;
643 uint64_t dorm_crypto:1; 983 uint64_t dorm_crypto:1;
644 uint64_t fus318:1; 984 uint64_t fus318:1;
645 uint64_t raid_en:1; 985 uint64_t raid_en:1;
@@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 {
747 uint64_t pp_dis:16; 1087 uint64_t pp_dis:16;
748 } cn58xx; 1088 } cn58xx;
749 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 1089 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
1090 struct cvmx_mio_fus_dat2_cn61xx {
1091 uint64_t reserved_48_63:16;
1092 uint64_t fus118:1;
1093 uint64_t rom_info:10;
1094 uint64_t power_limit:2;
1095 uint64_t dorm_crypto:1;
1096 uint64_t fus318:1;
1097 uint64_t raid_en:1;
1098 uint64_t reserved_29_31:3;
1099 uint64_t nodfa_cp2:1;
1100 uint64_t nomul:1;
1101 uint64_t nocrypto:1;
1102 uint64_t reserved_24_25:2;
1103 uint64_t chip_id:8;
1104 uint64_t reserved_4_15:12;
1105 uint64_t pp_dis:4;
1106 } cn61xx;
750 struct cvmx_mio_fus_dat2_cn63xx { 1107 struct cvmx_mio_fus_dat2_cn63xx {
751 uint64_t reserved_35_63:29; 1108 uint64_t reserved_35_63:29;
752 uint64_t dorm_crypto:1; 1109 uint64_t dorm_crypto:1;
@@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 {
762 uint64_t pp_dis:6; 1119 uint64_t pp_dis:6;
763 } cn63xx; 1120 } cn63xx;
764 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 1121 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
1122 struct cvmx_mio_fus_dat2_cn66xx {
1123 uint64_t reserved_48_63:16;
1124 uint64_t fus118:1;
1125 uint64_t rom_info:10;
1126 uint64_t power_limit:2;
1127 uint64_t dorm_crypto:1;
1128 uint64_t fus318:1;
1129 uint64_t raid_en:1;
1130 uint64_t reserved_29_31:3;
1131 uint64_t nodfa_cp2:1;
1132 uint64_t nomul:1;
1133 uint64_t nocrypto:1;
1134 uint64_t reserved_24_25:2;
1135 uint64_t chip_id:8;
1136 uint64_t reserved_10_15:6;
1137 uint64_t pp_dis:10;
1138 } cn66xx;
1139 struct cvmx_mio_fus_dat2_cn68xx {
1140 uint64_t reserved_37_63:27;
1141 uint64_t power_limit:2;
1142 uint64_t dorm_crypto:1;
1143 uint64_t fus318:1;
1144 uint64_t raid_en:1;
1145 uint64_t reserved_29_31:3;
1146 uint64_t nodfa_cp2:1;
1147 uint64_t nomul:1;
1148 uint64_t nocrypto:1;
1149 uint64_t reserved_24_25:2;
1150 uint64_t chip_id:8;
1151 uint64_t reserved_0_15:16;
1152 } cn68xx;
1153 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
765}; 1154};
766 1155
767union cvmx_mio_fus_dat3 { 1156union cvmx_mio_fus_dat3 {
@@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 {
834 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 1223 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
835 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 1224 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
836 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 1225 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
837 struct cvmx_mio_fus_dat3_cn63xx { 1226 struct cvmx_mio_fus_dat3_cn61xx {
838 uint64_t reserved_58_63:6; 1227 uint64_t reserved_58_63:6;
839 uint64_t pll_ctl:10; 1228 uint64_t pll_ctl:10;
840 uint64_t dfa_info_dte:3; 1229 uint64_t dfa_info_dte:3;
@@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 {
853 uint64_t nozip:1; 1242 uint64_t nozip:1;
854 uint64_t nodfa_dte:1; 1243 uint64_t nodfa_dte:1;
855 uint64_t reserved_0_23:24; 1244 uint64_t reserved_0_23:24;
856 } cn63xx; 1245 } cn61xx;
857 struct cvmx_mio_fus_dat3_cn63xx cn63xxp1; 1246 struct cvmx_mio_fus_dat3_cn61xx cn63xx;
1247 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
1248 struct cvmx_mio_fus_dat3_cn61xx cn66xx;
1249 struct cvmx_mio_fus_dat3_cn61xx cn68xx;
1250 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
858}; 1251};
859 1252
860union cvmx_mio_fus_ema { 1253union cvmx_mio_fus_ema {
@@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema {
875 uint64_t ema:2; 1268 uint64_t ema:2;
876 } cn58xx; 1269 } cn58xx;
877 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 1270 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
1271 struct cvmx_mio_fus_ema_s cn61xx;
878 struct cvmx_mio_fus_ema_s cn63xx; 1272 struct cvmx_mio_fus_ema_s cn63xx;
879 struct cvmx_mio_fus_ema_s cn63xxp1; 1273 struct cvmx_mio_fus_ema_s cn63xxp1;
1274 struct cvmx_mio_fus_ema_s cn66xx;
1275 struct cvmx_mio_fus_ema_s cn68xx;
1276 struct cvmx_mio_fus_ema_s cn68xxp1;
880}; 1277};
881 1278
882union cvmx_mio_fus_pdf { 1279union cvmx_mio_fus_pdf {
@@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf {
890 struct cvmx_mio_fus_pdf_s cn56xx; 1287 struct cvmx_mio_fus_pdf_s cn56xx;
891 struct cvmx_mio_fus_pdf_s cn56xxp1; 1288 struct cvmx_mio_fus_pdf_s cn56xxp1;
892 struct cvmx_mio_fus_pdf_s cn58xx; 1289 struct cvmx_mio_fus_pdf_s cn58xx;
1290 struct cvmx_mio_fus_pdf_s cn61xx;
893 struct cvmx_mio_fus_pdf_s cn63xx; 1291 struct cvmx_mio_fus_pdf_s cn63xx;
894 struct cvmx_mio_fus_pdf_s cn63xxp1; 1292 struct cvmx_mio_fus_pdf_s cn63xxp1;
1293 struct cvmx_mio_fus_pdf_s cn66xx;
1294 struct cvmx_mio_fus_pdf_s cn68xx;
1295 struct cvmx_mio_fus_pdf_s cn68xxp1;
895}; 1296};
896 1297
897union cvmx_mio_fus_pll { 1298union cvmx_mio_fus_pll {
898 uint64_t u64; 1299 uint64_t u64;
899 struct cvmx_mio_fus_pll_s { 1300 struct cvmx_mio_fus_pll_s {
900 uint64_t reserved_8_63:56; 1301 uint64_t reserved_48_63:16;
1302 uint64_t rclk_align_r:8;
1303 uint64_t rclk_align_l:8;
1304 uint64_t reserved_8_31:24;
901 uint64_t c_cout_rst:1; 1305 uint64_t c_cout_rst:1;
902 uint64_t c_cout_sel:2; 1306 uint64_t c_cout_sel:2;
903 uint64_t pnr_cout_rst:1; 1307 uint64_t pnr_cout_rst:1;
@@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll {
916 struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 1320 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
917 struct cvmx_mio_fus_pll_cn50xx cn58xx; 1321 struct cvmx_mio_fus_pll_cn50xx cn58xx;
918 struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 1322 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
919 struct cvmx_mio_fus_pll_s cn63xx; 1323 struct cvmx_mio_fus_pll_cn61xx {
920 struct cvmx_mio_fus_pll_s cn63xxp1; 1324 uint64_t reserved_8_63:56;
1325 uint64_t c_cout_rst:1;
1326 uint64_t c_cout_sel:2;
1327 uint64_t pnr_cout_rst:1;
1328 uint64_t pnr_cout_sel:2;
1329 uint64_t rfslip:1;
1330 uint64_t fbslip:1;
1331 } cn61xx;
1332 struct cvmx_mio_fus_pll_cn61xx cn63xx;
1333 struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
1334 struct cvmx_mio_fus_pll_cn61xx cn66xx;
1335 struct cvmx_mio_fus_pll_s cn68xx;
1336 struct cvmx_mio_fus_pll_s cn68xxp1;
921}; 1337};
922 1338
923union cvmx_mio_fus_prog { 1339union cvmx_mio_fus_prog {
@@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog {
941 struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 1357 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
942 struct cvmx_mio_fus_prog_cn30xx cn58xx; 1358 struct cvmx_mio_fus_prog_cn30xx cn58xx;
943 struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 1359 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
1360 struct cvmx_mio_fus_prog_s cn61xx;
944 struct cvmx_mio_fus_prog_s cn63xx; 1361 struct cvmx_mio_fus_prog_s cn63xx;
945 struct cvmx_mio_fus_prog_s cn63xxp1; 1362 struct cvmx_mio_fus_prog_s cn63xxp1;
1363 struct cvmx_mio_fus_prog_s cn66xx;
1364 struct cvmx_mio_fus_prog_s cn68xx;
1365 struct cvmx_mio_fus_prog_s cn68xxp1;
946}; 1366};
947 1367
948union cvmx_mio_fus_prog_times { 1368union cvmx_mio_fus_prog_times {
@@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times {
969 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 1389 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
970 struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 1390 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
971 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 1391 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
972 struct cvmx_mio_fus_prog_times_cn63xx { 1392 struct cvmx_mio_fus_prog_times_cn61xx {
973 uint64_t reserved_35_63:29; 1393 uint64_t reserved_35_63:29;
974 uint64_t vgate_pin:1; 1394 uint64_t vgate_pin:1;
975 uint64_t fsrc_pin:1; 1395 uint64_t fsrc_pin:1;
@@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times {
978 uint64_t sclk_lo:4; 1398 uint64_t sclk_lo:4;
979 uint64_t sclk_hi:15; 1399 uint64_t sclk_hi:15;
980 uint64_t setup:6; 1400 uint64_t setup:6;
981 } cn63xx; 1401 } cn61xx;
982 struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1; 1402 struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
1403 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
1404 struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
1405 struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
1406 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
983}; 1407};
984 1408
985union cvmx_mio_fus_rcmd { 1409union cvmx_mio_fus_rcmd {
@@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd {
1013 struct cvmx_mio_fus_rcmd_s cn56xxp1; 1437 struct cvmx_mio_fus_rcmd_s cn56xxp1;
1014 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 1438 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
1015 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 1439 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
1440 struct cvmx_mio_fus_rcmd_s cn61xx;
1016 struct cvmx_mio_fus_rcmd_s cn63xx; 1441 struct cvmx_mio_fus_rcmd_s cn63xx;
1017 struct cvmx_mio_fus_rcmd_s cn63xxp1; 1442 struct cvmx_mio_fus_rcmd_s cn63xxp1;
1443 struct cvmx_mio_fus_rcmd_s cn66xx;
1444 struct cvmx_mio_fus_rcmd_s cn68xx;
1445 struct cvmx_mio_fus_rcmd_s cn68xxp1;
1018}; 1446};
1019 1447
1020union cvmx_mio_fus_read_times { 1448union cvmx_mio_fus_read_times {
@@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times {
1027 uint64_t sdh:4; 1455 uint64_t sdh:4;
1028 uint64_t setup:10; 1456 uint64_t setup:10;
1029 } s; 1457 } s;
1458 struct cvmx_mio_fus_read_times_s cn61xx;
1030 struct cvmx_mio_fus_read_times_s cn63xx; 1459 struct cvmx_mio_fus_read_times_s cn63xx;
1031 struct cvmx_mio_fus_read_times_s cn63xxp1; 1460 struct cvmx_mio_fus_read_times_s cn63xxp1;
1461 struct cvmx_mio_fus_read_times_s cn66xx;
1462 struct cvmx_mio_fus_read_times_s cn68xx;
1463 struct cvmx_mio_fus_read_times_s cn68xxp1;
1032}; 1464};
1033 1465
1034union cvmx_mio_fus_repair_res0 { 1466union cvmx_mio_fus_repair_res0 {
@@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 {
1040 uint64_t repair1:18; 1472 uint64_t repair1:18;
1041 uint64_t repair0:18; 1473 uint64_t repair0:18;
1042 } s; 1474 } s;
1475 struct cvmx_mio_fus_repair_res0_s cn61xx;
1043 struct cvmx_mio_fus_repair_res0_s cn63xx; 1476 struct cvmx_mio_fus_repair_res0_s cn63xx;
1044 struct cvmx_mio_fus_repair_res0_s cn63xxp1; 1477 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
1478 struct cvmx_mio_fus_repair_res0_s cn66xx;
1479 struct cvmx_mio_fus_repair_res0_s cn68xx;
1480 struct cvmx_mio_fus_repair_res0_s cn68xxp1;
1045}; 1481};
1046 1482
1047union cvmx_mio_fus_repair_res1 { 1483union cvmx_mio_fus_repair_res1 {
@@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 {
1052 uint64_t repair4:18; 1488 uint64_t repair4:18;
1053 uint64_t repair3:18; 1489 uint64_t repair3:18;
1054 } s; 1490 } s;
1491 struct cvmx_mio_fus_repair_res1_s cn61xx;
1055 struct cvmx_mio_fus_repair_res1_s cn63xx; 1492 struct cvmx_mio_fus_repair_res1_s cn63xx;
1056 struct cvmx_mio_fus_repair_res1_s cn63xxp1; 1493 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
1494 struct cvmx_mio_fus_repair_res1_s cn66xx;
1495 struct cvmx_mio_fus_repair_res1_s cn68xx;
1496 struct cvmx_mio_fus_repair_res1_s cn68xxp1;
1057}; 1497};
1058 1498
1059union cvmx_mio_fus_repair_res2 { 1499union cvmx_mio_fus_repair_res2 {
@@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 {
1062 uint64_t reserved_18_63:46; 1502 uint64_t reserved_18_63:46;
1063 uint64_t repair6:18; 1503 uint64_t repair6:18;
1064 } s; 1504 } s;
1505 struct cvmx_mio_fus_repair_res2_s cn61xx;
1065 struct cvmx_mio_fus_repair_res2_s cn63xx; 1506 struct cvmx_mio_fus_repair_res2_s cn63xx;
1066 struct cvmx_mio_fus_repair_res2_s cn63xxp1; 1507 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
1508 struct cvmx_mio_fus_repair_res2_s cn66xx;
1509 struct cvmx_mio_fus_repair_res2_s cn68xx;
1510 struct cvmx_mio_fus_repair_res2_s cn68xxp1;
1067}; 1511};
1068 1512
1069union cvmx_mio_fus_spr_repair_res { 1513union cvmx_mio_fus_spr_repair_res {
@@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res {
1084 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 1528 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
1085 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 1529 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
1086 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 1530 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
1531 struct cvmx_mio_fus_spr_repair_res_s cn61xx;
1087 struct cvmx_mio_fus_spr_repair_res_s cn63xx; 1532 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
1088 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 1533 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
1534 struct cvmx_mio_fus_spr_repair_res_s cn66xx;
1535 struct cvmx_mio_fus_spr_repair_res_s cn68xx;
1536 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
1089}; 1537};
1090 1538
1091union cvmx_mio_fus_spr_repair_sum { 1539union cvmx_mio_fus_spr_repair_sum {
@@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum {
1104 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 1552 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
1105 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 1553 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
1106 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 1554 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
1555 struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
1107 struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 1556 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
1108 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 1557 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
1558 struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
1559 struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
1560 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
1561};
1562
1563union cvmx_mio_fus_tgg {
1564 uint64_t u64;
1565 struct cvmx_mio_fus_tgg_s {
1566 uint64_t val:1;
1567 uint64_t dat:63;
1568 } s;
1569 struct cvmx_mio_fus_tgg_s cn61xx;
1570 struct cvmx_mio_fus_tgg_s cn66xx;
1109}; 1571};
1110 1572
1111union cvmx_mio_fus_unlock { 1573union cvmx_mio_fus_unlock {
@@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr {
1141 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 1603 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1142 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 1604 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1143 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 1605 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1144 struct cvmx_mio_fus_wadr_cn63xx { 1606 struct cvmx_mio_fus_wadr_cn61xx {
1145 uint64_t reserved_4_63:60; 1607 uint64_t reserved_4_63:60;
1146 uint64_t addr:4; 1608 uint64_t addr:4;
1147 } cn63xx; 1609 } cn61xx;
1148 struct cvmx_mio_fus_wadr_cn63xx cn63xxp1; 1610 struct cvmx_mio_fus_wadr_cn61xx cn63xx;
1611 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
1612 struct cvmx_mio_fus_wadr_cn61xx cn66xx;
1613 struct cvmx_mio_fus_wadr_cn61xx cn68xx;
1614 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
1149}; 1615};
1150 1616
1151union cvmx_mio_gpio_comp { 1617union cvmx_mio_gpio_comp {
@@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp {
1155 uint64_t pctl:6; 1621 uint64_t pctl:6;
1156 uint64_t nctl:6; 1622 uint64_t nctl:6;
1157 } s; 1623 } s;
1624 struct cvmx_mio_gpio_comp_s cn61xx;
1158 struct cvmx_mio_gpio_comp_s cn63xx; 1625 struct cvmx_mio_gpio_comp_s cn63xx;
1159 struct cvmx_mio_gpio_comp_s cn63xxp1; 1626 struct cvmx_mio_gpio_comp_s cn63xxp1;
1627 struct cvmx_mio_gpio_comp_s cn66xx;
1628 struct cvmx_mio_gpio_comp_s cn68xx;
1629 struct cvmx_mio_gpio_comp_s cn68xxp1;
1160}; 1630};
1161 1631
1162union cvmx_mio_ndf_dma_cfg { 1632union cvmx_mio_ndf_dma_cfg {
@@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg {
1174 uint64_t adr:36; 1644 uint64_t adr:36;
1175 } s; 1645 } s;
1176 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 1646 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1647 struct cvmx_mio_ndf_dma_cfg_s cn61xx;
1177 struct cvmx_mio_ndf_dma_cfg_s cn63xx; 1648 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
1178 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 1649 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
1650 struct cvmx_mio_ndf_dma_cfg_s cn66xx;
1651 struct cvmx_mio_ndf_dma_cfg_s cn68xx;
1652 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
1179}; 1653};
1180 1654
1181union cvmx_mio_ndf_dma_int { 1655union cvmx_mio_ndf_dma_int {
@@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int {
1185 uint64_t done:1; 1659 uint64_t done:1;
1186 } s; 1660 } s;
1187 struct cvmx_mio_ndf_dma_int_s cn52xx; 1661 struct cvmx_mio_ndf_dma_int_s cn52xx;
1662 struct cvmx_mio_ndf_dma_int_s cn61xx;
1188 struct cvmx_mio_ndf_dma_int_s cn63xx; 1663 struct cvmx_mio_ndf_dma_int_s cn63xx;
1189 struct cvmx_mio_ndf_dma_int_s cn63xxp1; 1664 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
1665 struct cvmx_mio_ndf_dma_int_s cn66xx;
1666 struct cvmx_mio_ndf_dma_int_s cn68xx;
1667 struct cvmx_mio_ndf_dma_int_s cn68xxp1;
1190}; 1668};
1191 1669
1192union cvmx_mio_ndf_dma_int_en { 1670union cvmx_mio_ndf_dma_int_en {
@@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en {
1196 uint64_t done:1; 1674 uint64_t done:1;
1197 } s; 1675 } s;
1198 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 1676 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1677 struct cvmx_mio_ndf_dma_int_en_s cn61xx;
1199 struct cvmx_mio_ndf_dma_int_en_s cn63xx; 1678 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
1200 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 1679 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
1680 struct cvmx_mio_ndf_dma_int_en_s cn66xx;
1681 struct cvmx_mio_ndf_dma_int_en_s cn68xx;
1682 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
1201}; 1683};
1202 1684
1203union cvmx_mio_pll_ctl { 1685union cvmx_mio_pll_ctl {
@@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting {
1220 struct cvmx_mio_pll_setting_s cn31xx; 1702 struct cvmx_mio_pll_setting_s cn31xx;
1221}; 1703};
1222 1704
1705union cvmx_mio_ptp_ckout_hi_incr {
1706 uint64_t u64;
1707 struct cvmx_mio_ptp_ckout_hi_incr_s {
1708 uint64_t nanosec:32;
1709 uint64_t frnanosec:32;
1710 } s;
1711 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
1712 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
1713 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
1714};
1715
1716union cvmx_mio_ptp_ckout_lo_incr {
1717 uint64_t u64;
1718 struct cvmx_mio_ptp_ckout_lo_incr_s {
1719 uint64_t nanosec:32;
1720 uint64_t frnanosec:32;
1721 } s;
1722 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
1723 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
1724 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
1725};
1726
1727union cvmx_mio_ptp_ckout_thresh_hi {
1728 uint64_t u64;
1729 struct cvmx_mio_ptp_ckout_thresh_hi_s {
1730 uint64_t nanosec:64;
1731 } s;
1732 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
1733 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
1734 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
1735};
1736
1737union cvmx_mio_ptp_ckout_thresh_lo {
1738 uint64_t u64;
1739 struct cvmx_mio_ptp_ckout_thresh_lo_s {
1740 uint64_t reserved_32_63:32;
1741 uint64_t frnanosec:32;
1742 } s;
1743 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
1744 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
1745 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
1746};
1747
1223union cvmx_mio_ptp_clock_cfg { 1748union cvmx_mio_ptp_clock_cfg {
1224 uint64_t u64; 1749 uint64_t u64;
1225 struct cvmx_mio_ptp_clock_cfg_s { 1750 struct cvmx_mio_ptp_clock_cfg_s {
1226 uint64_t reserved_24_63:40; 1751 uint64_t reserved_42_63:22;
1752 uint64_t pps:1;
1753 uint64_t ckout:1;
1754 uint64_t ext_clk_edge:2;
1755 uint64_t ckout_out4:1;
1756 uint64_t pps_out:5;
1757 uint64_t pps_inv:1;
1758 uint64_t pps_en:1;
1759 uint64_t ckout_out:4;
1760 uint64_t ckout_inv:1;
1761 uint64_t ckout_en:1;
1227 uint64_t evcnt_in:6; 1762 uint64_t evcnt_in:6;
1228 uint64_t evcnt_edge:1; 1763 uint64_t evcnt_edge:1;
1229 uint64_t evcnt_en:1; 1764 uint64_t evcnt_en:1;
@@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg {
1234 uint64_t ext_clk_en:1; 1769 uint64_t ext_clk_en:1;
1235 uint64_t ptp_en:1; 1770 uint64_t ptp_en:1;
1236 } s; 1771 } s;
1237 struct cvmx_mio_ptp_clock_cfg_s cn63xx; 1772 struct cvmx_mio_ptp_clock_cfg_s cn61xx;
1238 struct cvmx_mio_ptp_clock_cfg_s cn63xxp1; 1773 struct cvmx_mio_ptp_clock_cfg_cn63xx {
1774 uint64_t reserved_24_63:40;
1775 uint64_t evcnt_in:6;
1776 uint64_t evcnt_edge:1;
1777 uint64_t evcnt_en:1;
1778 uint64_t tstmp_in:6;
1779 uint64_t tstmp_edge:1;
1780 uint64_t tstmp_en:1;
1781 uint64_t ext_clk_in:6;
1782 uint64_t ext_clk_en:1;
1783 uint64_t ptp_en:1;
1784 } cn63xx;
1785 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
1786 struct cvmx_mio_ptp_clock_cfg_cn66xx {
1787 uint64_t reserved_40_63:24;
1788 uint64_t ext_clk_edge:2;
1789 uint64_t ckout_out4:1;
1790 uint64_t pps_out:5;
1791 uint64_t pps_inv:1;
1792 uint64_t pps_en:1;
1793 uint64_t ckout_out:4;
1794 uint64_t ckout_inv:1;
1795 uint64_t ckout_en:1;
1796 uint64_t evcnt_in:6;
1797 uint64_t evcnt_edge:1;
1798 uint64_t evcnt_en:1;
1799 uint64_t tstmp_in:6;
1800 uint64_t tstmp_edge:1;
1801 uint64_t tstmp_en:1;
1802 uint64_t ext_clk_in:6;
1803 uint64_t ext_clk_en:1;
1804 uint64_t ptp_en:1;
1805 } cn66xx;
1806 struct cvmx_mio_ptp_clock_cfg_s cn68xx;
1807 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
1239}; 1808};
1240 1809
1241union cvmx_mio_ptp_clock_comp { 1810union cvmx_mio_ptp_clock_comp {
@@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp {
1244 uint64_t nanosec:32; 1813 uint64_t nanosec:32;
1245 uint64_t frnanosec:32; 1814 uint64_t frnanosec:32;
1246 } s; 1815 } s;
1816 struct cvmx_mio_ptp_clock_comp_s cn61xx;
1247 struct cvmx_mio_ptp_clock_comp_s cn63xx; 1817 struct cvmx_mio_ptp_clock_comp_s cn63xx;
1248 struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 1818 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
1819 struct cvmx_mio_ptp_clock_comp_s cn66xx;
1820 struct cvmx_mio_ptp_clock_comp_s cn68xx;
1821 struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
1249}; 1822};
1250 1823
1251union cvmx_mio_ptp_clock_hi { 1824union cvmx_mio_ptp_clock_hi {
@@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi {
1253 struct cvmx_mio_ptp_clock_hi_s { 1826 struct cvmx_mio_ptp_clock_hi_s {
1254 uint64_t nanosec:64; 1827 uint64_t nanosec:64;
1255 } s; 1828 } s;
1829 struct cvmx_mio_ptp_clock_hi_s cn61xx;
1256 struct cvmx_mio_ptp_clock_hi_s cn63xx; 1830 struct cvmx_mio_ptp_clock_hi_s cn63xx;
1257 struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 1831 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
1832 struct cvmx_mio_ptp_clock_hi_s cn66xx;
1833 struct cvmx_mio_ptp_clock_hi_s cn68xx;
1834 struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
1258}; 1835};
1259 1836
1260union cvmx_mio_ptp_clock_lo { 1837union cvmx_mio_ptp_clock_lo {
@@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo {
1263 uint64_t reserved_32_63:32; 1840 uint64_t reserved_32_63:32;
1264 uint64_t frnanosec:32; 1841 uint64_t frnanosec:32;
1265 } s; 1842 } s;
1843 struct cvmx_mio_ptp_clock_lo_s cn61xx;
1266 struct cvmx_mio_ptp_clock_lo_s cn63xx; 1844 struct cvmx_mio_ptp_clock_lo_s cn63xx;
1267 struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 1845 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
1846 struct cvmx_mio_ptp_clock_lo_s cn66xx;
1847 struct cvmx_mio_ptp_clock_lo_s cn68xx;
1848 struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
1268}; 1849};
1269 1850
1270union cvmx_mio_ptp_evt_cnt { 1851union cvmx_mio_ptp_evt_cnt {
@@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt {
1272 struct cvmx_mio_ptp_evt_cnt_s { 1853 struct cvmx_mio_ptp_evt_cnt_s {
1273 uint64_t cntr:64; 1854 uint64_t cntr:64;
1274 } s; 1855 } s;
1856 struct cvmx_mio_ptp_evt_cnt_s cn61xx;
1275 struct cvmx_mio_ptp_evt_cnt_s cn63xx; 1857 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
1276 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 1858 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
1859 struct cvmx_mio_ptp_evt_cnt_s cn66xx;
1860 struct cvmx_mio_ptp_evt_cnt_s cn68xx;
1861 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
1862};
1863
1864union cvmx_mio_ptp_pps_hi_incr {
1865 uint64_t u64;
1866 struct cvmx_mio_ptp_pps_hi_incr_s {
1867 uint64_t nanosec:32;
1868 uint64_t frnanosec:32;
1869 } s;
1870 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
1871 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
1872 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
1873};
1874
1875union cvmx_mio_ptp_pps_lo_incr {
1876 uint64_t u64;
1877 struct cvmx_mio_ptp_pps_lo_incr_s {
1878 uint64_t nanosec:32;
1879 uint64_t frnanosec:32;
1880 } s;
1881 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
1882 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
1883 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
1884};
1885
1886union cvmx_mio_ptp_pps_thresh_hi {
1887 uint64_t u64;
1888 struct cvmx_mio_ptp_pps_thresh_hi_s {
1889 uint64_t nanosec:64;
1890 } s;
1891 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
1892 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
1893 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
1894};
1895
1896union cvmx_mio_ptp_pps_thresh_lo {
1897 uint64_t u64;
1898 struct cvmx_mio_ptp_pps_thresh_lo_s {
1899 uint64_t reserved_32_63:32;
1900 uint64_t frnanosec:32;
1901 } s;
1902 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
1903 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
1904 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
1277}; 1905};
1278 1906
1279union cvmx_mio_ptp_timestamp { 1907union cvmx_mio_ptp_timestamp {
@@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp {
1281 struct cvmx_mio_ptp_timestamp_s { 1909 struct cvmx_mio_ptp_timestamp_s {
1282 uint64_t nanosec:64; 1910 uint64_t nanosec:64;
1283 } s; 1911 } s;
1912 struct cvmx_mio_ptp_timestamp_s cn61xx;
1284 struct cvmx_mio_ptp_timestamp_s cn63xx; 1913 struct cvmx_mio_ptp_timestamp_s cn63xx;
1285 struct cvmx_mio_ptp_timestamp_s cn63xxp1; 1914 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
1915 struct cvmx_mio_ptp_timestamp_s cn66xx;
1916 struct cvmx_mio_ptp_timestamp_s cn68xx;
1917 struct cvmx_mio_ptp_timestamp_s cn68xxp1;
1918};
1919
1920union cvmx_mio_qlmx_cfg {
1921 uint64_t u64;
1922 struct cvmx_mio_qlmx_cfg_s {
1923 uint64_t reserved_12_63:52;
1924 uint64_t qlm_spd:4;
1925 uint64_t reserved_4_7:4;
1926 uint64_t qlm_cfg:4;
1927 } s;
1928 struct cvmx_mio_qlmx_cfg_cn61xx {
1929 uint64_t reserved_12_63:52;
1930 uint64_t qlm_spd:4;
1931 uint64_t reserved_2_7:6;
1932 uint64_t qlm_cfg:2;
1933 } cn61xx;
1934 struct cvmx_mio_qlmx_cfg_s cn66xx;
1935 struct cvmx_mio_qlmx_cfg_cn68xx {
1936 uint64_t reserved_12_63:52;
1937 uint64_t qlm_spd:4;
1938 uint64_t reserved_3_7:5;
1939 uint64_t qlm_cfg:3;
1940 } cn68xx;
1941 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
1286}; 1942};
1287 1943
1288union cvmx_mio_rst_boot { 1944union cvmx_mio_rst_boot {
1289 uint64_t u64; 1945 uint64_t u64;
1290 struct cvmx_mio_rst_boot_s { 1946 struct cvmx_mio_rst_boot_s {
1291 uint64_t reserved_36_63:28; 1947 uint64_t chipkill:1;
1948 uint64_t jtcsrdis:1;
1949 uint64_t ejtagdis:1;
1950 uint64_t romen:1;
1951 uint64_t ckill_ppdis:1;
1952 uint64_t jt_tstmode:1;
1953 uint64_t reserved_50_57:8;
1954 uint64_t lboot_ext:2;
1955 uint64_t reserved_44_47:4;
1956 uint64_t qlm4_spd:4;
1957 uint64_t qlm3_spd:4;
1292 uint64_t c_mul:6; 1958 uint64_t c_mul:6;
1293 uint64_t pnr_mul:6; 1959 uint64_t pnr_mul:6;
1294 uint64_t qlm2_spd:4; 1960 uint64_t qlm2_spd:4;
@@ -1298,32 +1964,168 @@ union cvmx_mio_rst_boot {
1298 uint64_t rboot:1; 1964 uint64_t rboot:1;
1299 uint64_t rboot_pin:1; 1965 uint64_t rboot_pin:1;
1300 } s; 1966 } s;
1301 struct cvmx_mio_rst_boot_s cn63xx; 1967 struct cvmx_mio_rst_boot_cn61xx {
1302 struct cvmx_mio_rst_boot_s cn63xxp1; 1968 uint64_t chipkill:1;
1969 uint64_t jtcsrdis:1;
1970 uint64_t ejtagdis:1;
1971 uint64_t romen:1;
1972 uint64_t ckill_ppdis:1;
1973 uint64_t jt_tstmode:1;
1974 uint64_t reserved_50_57:8;
1975 uint64_t lboot_ext:2;
1976 uint64_t reserved_36_47:12;
1977 uint64_t c_mul:6;
1978 uint64_t pnr_mul:6;
1979 uint64_t qlm2_spd:4;
1980 uint64_t qlm1_spd:4;
1981 uint64_t qlm0_spd:4;
1982 uint64_t lboot:10;
1983 uint64_t rboot:1;
1984 uint64_t rboot_pin:1;
1985 } cn61xx;
1986 struct cvmx_mio_rst_boot_cn63xx {
1987 uint64_t reserved_36_63:28;
1988 uint64_t c_mul:6;
1989 uint64_t pnr_mul:6;
1990 uint64_t qlm2_spd:4;
1991 uint64_t qlm1_spd:4;
1992 uint64_t qlm0_spd:4;
1993 uint64_t lboot:10;
1994 uint64_t rboot:1;
1995 uint64_t rboot_pin:1;
1996 } cn63xx;
1997 struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
1998 struct cvmx_mio_rst_boot_cn66xx {
1999 uint64_t chipkill:1;
2000 uint64_t jtcsrdis:1;
2001 uint64_t ejtagdis:1;
2002 uint64_t romen:1;
2003 uint64_t ckill_ppdis:1;
2004 uint64_t reserved_50_58:9;
2005 uint64_t lboot_ext:2;
2006 uint64_t reserved_36_47:12;
2007 uint64_t c_mul:6;
2008 uint64_t pnr_mul:6;
2009 uint64_t qlm2_spd:4;
2010 uint64_t qlm1_spd:4;
2011 uint64_t qlm0_spd:4;
2012 uint64_t lboot:10;
2013 uint64_t rboot:1;
2014 uint64_t rboot_pin:1;
2015 } cn66xx;
2016 struct cvmx_mio_rst_boot_cn68xx {
2017 uint64_t reserved_59_63:5;
2018 uint64_t jt_tstmode:1;
2019 uint64_t reserved_44_57:14;
2020 uint64_t qlm4_spd:4;
2021 uint64_t qlm3_spd:4;
2022 uint64_t c_mul:6;
2023 uint64_t pnr_mul:6;
2024 uint64_t qlm2_spd:4;
2025 uint64_t qlm1_spd:4;
2026 uint64_t qlm0_spd:4;
2027 uint64_t lboot:10;
2028 uint64_t rboot:1;
2029 uint64_t rboot_pin:1;
2030 } cn68xx;
2031 struct cvmx_mio_rst_boot_cn68xxp1 {
2032 uint64_t reserved_44_63:20;
2033 uint64_t qlm4_spd:4;
2034 uint64_t qlm3_spd:4;
2035 uint64_t c_mul:6;
2036 uint64_t pnr_mul:6;
2037 uint64_t qlm2_spd:4;
2038 uint64_t qlm1_spd:4;
2039 uint64_t qlm0_spd:4;
2040 uint64_t lboot:10;
2041 uint64_t rboot:1;
2042 uint64_t rboot_pin:1;
2043 } cn68xxp1;
1303}; 2044};
1304 2045
1305union cvmx_mio_rst_cfg { 2046union cvmx_mio_rst_cfg {
1306 uint64_t u64; 2047 uint64_t u64;
1307 struct cvmx_mio_rst_cfg_s { 2048 struct cvmx_mio_rst_cfg_s {
2049 uint64_t reserved_3_63:61;
2050 uint64_t cntl_clr_bist:1;
2051 uint64_t warm_clr_bist:1;
2052 uint64_t soft_clr_bist:1;
2053 } s;
2054 struct cvmx_mio_rst_cfg_cn61xx {
1308 uint64_t bist_delay:58; 2055 uint64_t bist_delay:58;
1309 uint64_t reserved_3_5:3; 2056 uint64_t reserved_3_5:3;
1310 uint64_t cntl_clr_bist:1; 2057 uint64_t cntl_clr_bist:1;
1311 uint64_t warm_clr_bist:1; 2058 uint64_t warm_clr_bist:1;
1312 uint64_t soft_clr_bist:1; 2059 uint64_t soft_clr_bist:1;
1313 } s; 2060 } cn61xx;
1314 struct cvmx_mio_rst_cfg_s cn63xx; 2061 struct cvmx_mio_rst_cfg_cn61xx cn63xx;
1315 struct cvmx_mio_rst_cfg_cn63xxp1 { 2062 struct cvmx_mio_rst_cfg_cn63xxp1 {
1316 uint64_t bist_delay:58; 2063 uint64_t bist_delay:58;
1317 uint64_t reserved_2_5:4; 2064 uint64_t reserved_2_5:4;
1318 uint64_t warm_clr_bist:1; 2065 uint64_t warm_clr_bist:1;
1319 uint64_t soft_clr_bist:1; 2066 uint64_t soft_clr_bist:1;
1320 } cn63xxp1; 2067 } cn63xxp1;
2068 struct cvmx_mio_rst_cfg_cn61xx cn66xx;
2069 struct cvmx_mio_rst_cfg_cn68xx {
2070 uint64_t bist_delay:56;
2071 uint64_t reserved_3_7:5;
2072 uint64_t cntl_clr_bist:1;
2073 uint64_t warm_clr_bist:1;
2074 uint64_t soft_clr_bist:1;
2075 } cn68xx;
2076 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
2077};
2078
2079union cvmx_mio_rst_ckill {
2080 uint64_t u64;
2081 struct cvmx_mio_rst_ckill_s {
2082 uint64_t reserved_47_63:17;
2083 uint64_t timer:47;
2084 } s;
2085 struct cvmx_mio_rst_ckill_s cn61xx;
2086 struct cvmx_mio_rst_ckill_s cn66xx;
2087};
2088
2089union cvmx_mio_rst_cntlx {
2090 uint64_t u64;
2091 struct cvmx_mio_rst_cntlx_s {
2092 uint64_t reserved_13_63:51;
2093 uint64_t in_rev_ln:1;
2094 uint64_t rev_lanes:1;
2095 uint64_t gen1_only:1;
2096 uint64_t prst_link:1;
2097 uint64_t rst_done:1;
2098 uint64_t rst_link:1;
2099 uint64_t host_mode:1;
2100 uint64_t prtmode:2;
2101 uint64_t rst_drv:1;
2102 uint64_t rst_rcv:1;
2103 uint64_t rst_chip:1;
2104 uint64_t rst_val:1;
2105 } s;
2106 struct cvmx_mio_rst_cntlx_s cn61xx;
2107 struct cvmx_mio_rst_cntlx_cn66xx {
2108 uint64_t reserved_10_63:54;
2109 uint64_t prst_link:1;
2110 uint64_t rst_done:1;
2111 uint64_t rst_link:1;
2112 uint64_t host_mode:1;
2113 uint64_t prtmode:2;
2114 uint64_t rst_drv:1;
2115 uint64_t rst_rcv:1;
2116 uint64_t rst_chip:1;
2117 uint64_t rst_val:1;
2118 } cn66xx;
2119 struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
1321}; 2120};
1322 2121
1323union cvmx_mio_rst_ctlx { 2122union cvmx_mio_rst_ctlx {
1324 uint64_t u64; 2123 uint64_t u64;
1325 struct cvmx_mio_rst_ctlx_s { 2124 struct cvmx_mio_rst_ctlx_s {
1326 uint64_t reserved_10_63:54; 2125 uint64_t reserved_13_63:51;
2126 uint64_t in_rev_ln:1;
2127 uint64_t rev_lanes:1;
2128 uint64_t gen1_only:1;
1327 uint64_t prst_link:1; 2129 uint64_t prst_link:1;
1328 uint64_t rst_done:1; 2130 uint64_t rst_done:1;
1329 uint64_t rst_link:1; 2131 uint64_t rst_link:1;
@@ -1334,7 +2136,19 @@ union cvmx_mio_rst_ctlx {
1334 uint64_t rst_chip:1; 2136 uint64_t rst_chip:1;
1335 uint64_t rst_val:1; 2137 uint64_t rst_val:1;
1336 } s; 2138 } s;
1337 struct cvmx_mio_rst_ctlx_s cn63xx; 2139 struct cvmx_mio_rst_ctlx_s cn61xx;
2140 struct cvmx_mio_rst_ctlx_cn63xx {
2141 uint64_t reserved_10_63:54;
2142 uint64_t prst_link:1;
2143 uint64_t rst_done:1;
2144 uint64_t rst_link:1;
2145 uint64_t host_mode:1;
2146 uint64_t prtmode:2;
2147 uint64_t rst_drv:1;
2148 uint64_t rst_rcv:1;
2149 uint64_t rst_chip:1;
2150 uint64_t rst_val:1;
2151 } cn63xx;
1338 struct cvmx_mio_rst_ctlx_cn63xxp1 { 2152 struct cvmx_mio_rst_ctlx_cn63xxp1 {
1339 uint64_t reserved_9_63:55; 2153 uint64_t reserved_9_63:55;
1340 uint64_t rst_done:1; 2154 uint64_t rst_done:1;
@@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx {
1346 uint64_t rst_chip:1; 2160 uint64_t rst_chip:1;
1347 uint64_t rst_val:1; 2161 uint64_t rst_val:1;
1348 } cn63xxp1; 2162 } cn63xxp1;
2163 struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
2164 struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
2165 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
1349}; 2166};
1350 2167
1351union cvmx_mio_rst_delay { 2168union cvmx_mio_rst_delay {
1352 uint64_t u64; 2169 uint64_t u64;
1353 struct cvmx_mio_rst_delay_s { 2170 struct cvmx_mio_rst_delay_s {
1354 uint64_t reserved_32_63:32; 2171 uint64_t reserved_32_63:32;
1355 uint64_t soft_rst_dly:16;
1356 uint64_t warm_rst_dly:16; 2172 uint64_t warm_rst_dly:16;
2173 uint64_t soft_rst_dly:16;
1357 } s; 2174 } s;
2175 struct cvmx_mio_rst_delay_s cn61xx;
1358 struct cvmx_mio_rst_delay_s cn63xx; 2176 struct cvmx_mio_rst_delay_s cn63xx;
1359 struct cvmx_mio_rst_delay_s cn63xxp1; 2177 struct cvmx_mio_rst_delay_s cn63xxp1;
2178 struct cvmx_mio_rst_delay_s cn66xx;
2179 struct cvmx_mio_rst_delay_s cn68xx;
2180 struct cvmx_mio_rst_delay_s cn68xxp1;
1360}; 2181};
1361 2182
1362union cvmx_mio_rst_int { 2183union cvmx_mio_rst_int {
@@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int {
1365 uint64_t reserved_10_63:54; 2186 uint64_t reserved_10_63:54;
1366 uint64_t perst1:1; 2187 uint64_t perst1:1;
1367 uint64_t perst0:1; 2188 uint64_t perst0:1;
1368 uint64_t reserved_2_7:6; 2189 uint64_t reserved_4_7:4;
2190 uint64_t rst_link3:1;
2191 uint64_t rst_link2:1;
1369 uint64_t rst_link1:1; 2192 uint64_t rst_link1:1;
1370 uint64_t rst_link0:1; 2193 uint64_t rst_link0:1;
1371 } s; 2194 } s;
1372 struct cvmx_mio_rst_int_s cn63xx; 2195 struct cvmx_mio_rst_int_cn61xx {
1373 struct cvmx_mio_rst_int_s cn63xxp1; 2196 uint64_t reserved_10_63:54;
2197 uint64_t perst1:1;
2198 uint64_t perst0:1;
2199 uint64_t reserved_2_7:6;
2200 uint64_t rst_link1:1;
2201 uint64_t rst_link0:1;
2202 } cn61xx;
2203 struct cvmx_mio_rst_int_cn61xx cn63xx;
2204 struct cvmx_mio_rst_int_cn61xx cn63xxp1;
2205 struct cvmx_mio_rst_int_s cn66xx;
2206 struct cvmx_mio_rst_int_cn61xx cn68xx;
2207 struct cvmx_mio_rst_int_cn61xx cn68xxp1;
1374}; 2208};
1375 2209
1376union cvmx_mio_rst_int_en { 2210union cvmx_mio_rst_int_en {
@@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en {
1379 uint64_t reserved_10_63:54; 2213 uint64_t reserved_10_63:54;
1380 uint64_t perst1:1; 2214 uint64_t perst1:1;
1381 uint64_t perst0:1; 2215 uint64_t perst0:1;
1382 uint64_t reserved_2_7:6; 2216 uint64_t reserved_4_7:4;
2217 uint64_t rst_link3:1;
2218 uint64_t rst_link2:1;
1383 uint64_t rst_link1:1; 2219 uint64_t rst_link1:1;
1384 uint64_t rst_link0:1; 2220 uint64_t rst_link0:1;
1385 } s; 2221 } s;
1386 struct cvmx_mio_rst_int_en_s cn63xx; 2222 struct cvmx_mio_rst_int_en_cn61xx {
1387 struct cvmx_mio_rst_int_en_s cn63xxp1; 2223 uint64_t reserved_10_63:54;
2224 uint64_t perst1:1;
2225 uint64_t perst0:1;
2226 uint64_t reserved_2_7:6;
2227 uint64_t rst_link1:1;
2228 uint64_t rst_link0:1;
2229 } cn61xx;
2230 struct cvmx_mio_rst_int_en_cn61xx cn63xx;
2231 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
2232 struct cvmx_mio_rst_int_en_s cn66xx;
2233 struct cvmx_mio_rst_int_en_cn61xx cn68xx;
2234 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
1388}; 2235};
1389 2236
1390union cvmx_mio_twsx_int { 2237union cvmx_mio_twsx_int {
@@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int {
1424 struct cvmx_mio_twsx_int_s cn56xxp1; 2271 struct cvmx_mio_twsx_int_s cn56xxp1;
1425 struct cvmx_mio_twsx_int_s cn58xx; 2272 struct cvmx_mio_twsx_int_s cn58xx;
1426 struct cvmx_mio_twsx_int_s cn58xxp1; 2273 struct cvmx_mio_twsx_int_s cn58xxp1;
2274 struct cvmx_mio_twsx_int_s cn61xx;
1427 struct cvmx_mio_twsx_int_s cn63xx; 2275 struct cvmx_mio_twsx_int_s cn63xx;
1428 struct cvmx_mio_twsx_int_s cn63xxp1; 2276 struct cvmx_mio_twsx_int_s cn63xxp1;
2277 struct cvmx_mio_twsx_int_s cn66xx;
2278 struct cvmx_mio_twsx_int_s cn68xx;
2279 struct cvmx_mio_twsx_int_s cn68xxp1;
1429}; 2280};
1430 2281
1431union cvmx_mio_twsx_sw_twsi { 2282union cvmx_mio_twsx_sw_twsi {
@@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi {
1455 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 2306 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1456 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 2307 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1457 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 2308 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
2309 struct cvmx_mio_twsx_sw_twsi_s cn61xx;
1458 struct cvmx_mio_twsx_sw_twsi_s cn63xx; 2310 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
1459 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 2311 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
2312 struct cvmx_mio_twsx_sw_twsi_s cn66xx;
2313 struct cvmx_mio_twsx_sw_twsi_s cn68xx;
2314 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
1460}; 2315};
1461 2316
1462union cvmx_mio_twsx_sw_twsi_ext { 2317union cvmx_mio_twsx_sw_twsi_ext {
@@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext {
1477 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 2332 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1478 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 2333 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1479 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 2334 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
2335 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
1480 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 2336 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
1481 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 2337 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
2338 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
2339 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
2340 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
1482}; 2341};
1483 2342
1484union cvmx_mio_twsx_twsi_sw { 2343union cvmx_mio_twsx_twsi_sw {
@@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw {
1499 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 2358 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1500 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 2359 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1501 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 2360 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
2361 struct cvmx_mio_twsx_twsi_sw_s cn61xx;
1502 struct cvmx_mio_twsx_twsi_sw_s cn63xx; 2362 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
1503 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 2363 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
2364 struct cvmx_mio_twsx_twsi_sw_s cn66xx;
2365 struct cvmx_mio_twsx_twsi_sw_s cn68xx;
2366 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
1504}; 2367};
1505 2368
1506union cvmx_mio_uartx_dlh { 2369union cvmx_mio_uartx_dlh {
@@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh {
1520 struct cvmx_mio_uartx_dlh_s cn56xxp1; 2383 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1521 struct cvmx_mio_uartx_dlh_s cn58xx; 2384 struct cvmx_mio_uartx_dlh_s cn58xx;
1522 struct cvmx_mio_uartx_dlh_s cn58xxp1; 2385 struct cvmx_mio_uartx_dlh_s cn58xxp1;
2386 struct cvmx_mio_uartx_dlh_s cn61xx;
1523 struct cvmx_mio_uartx_dlh_s cn63xx; 2387 struct cvmx_mio_uartx_dlh_s cn63xx;
1524 struct cvmx_mio_uartx_dlh_s cn63xxp1; 2388 struct cvmx_mio_uartx_dlh_s cn63xxp1;
2389 struct cvmx_mio_uartx_dlh_s cn66xx;
2390 struct cvmx_mio_uartx_dlh_s cn68xx;
2391 struct cvmx_mio_uartx_dlh_s cn68xxp1;
1525}; 2392};
1526 2393
1527union cvmx_mio_uartx_dll { 2394union cvmx_mio_uartx_dll {
@@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll {
1541 struct cvmx_mio_uartx_dll_s cn56xxp1; 2408 struct cvmx_mio_uartx_dll_s cn56xxp1;
1542 struct cvmx_mio_uartx_dll_s cn58xx; 2409 struct cvmx_mio_uartx_dll_s cn58xx;
1543 struct cvmx_mio_uartx_dll_s cn58xxp1; 2410 struct cvmx_mio_uartx_dll_s cn58xxp1;
2411 struct cvmx_mio_uartx_dll_s cn61xx;
1544 struct cvmx_mio_uartx_dll_s cn63xx; 2412 struct cvmx_mio_uartx_dll_s cn63xx;
1545 struct cvmx_mio_uartx_dll_s cn63xxp1; 2413 struct cvmx_mio_uartx_dll_s cn63xxp1;
2414 struct cvmx_mio_uartx_dll_s cn66xx;
2415 struct cvmx_mio_uartx_dll_s cn68xx;
2416 struct cvmx_mio_uartx_dll_s cn68xxp1;
1546}; 2417};
1547 2418
1548union cvmx_mio_uartx_far { 2419union cvmx_mio_uartx_far {
@@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far {
1562 struct cvmx_mio_uartx_far_s cn56xxp1; 2433 struct cvmx_mio_uartx_far_s cn56xxp1;
1563 struct cvmx_mio_uartx_far_s cn58xx; 2434 struct cvmx_mio_uartx_far_s cn58xx;
1564 struct cvmx_mio_uartx_far_s cn58xxp1; 2435 struct cvmx_mio_uartx_far_s cn58xxp1;
2436 struct cvmx_mio_uartx_far_s cn61xx;
1565 struct cvmx_mio_uartx_far_s cn63xx; 2437 struct cvmx_mio_uartx_far_s cn63xx;
1566 struct cvmx_mio_uartx_far_s cn63xxp1; 2438 struct cvmx_mio_uartx_far_s cn63xxp1;
2439 struct cvmx_mio_uartx_far_s cn66xx;
2440 struct cvmx_mio_uartx_far_s cn68xx;
2441 struct cvmx_mio_uartx_far_s cn68xxp1;
1567}; 2442};
1568 2443
1569union cvmx_mio_uartx_fcr { 2444union cvmx_mio_uartx_fcr {
@@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr {
1588 struct cvmx_mio_uartx_fcr_s cn56xxp1; 2463 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1589 struct cvmx_mio_uartx_fcr_s cn58xx; 2464 struct cvmx_mio_uartx_fcr_s cn58xx;
1590 struct cvmx_mio_uartx_fcr_s cn58xxp1; 2465 struct cvmx_mio_uartx_fcr_s cn58xxp1;
2466 struct cvmx_mio_uartx_fcr_s cn61xx;
1591 struct cvmx_mio_uartx_fcr_s cn63xx; 2467 struct cvmx_mio_uartx_fcr_s cn63xx;
1592 struct cvmx_mio_uartx_fcr_s cn63xxp1; 2468 struct cvmx_mio_uartx_fcr_s cn63xxp1;
2469 struct cvmx_mio_uartx_fcr_s cn66xx;
2470 struct cvmx_mio_uartx_fcr_s cn68xx;
2471 struct cvmx_mio_uartx_fcr_s cn68xxp1;
1593}; 2472};
1594 2473
1595union cvmx_mio_uartx_htx { 2474union cvmx_mio_uartx_htx {
@@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx {
1609 struct cvmx_mio_uartx_htx_s cn56xxp1; 2488 struct cvmx_mio_uartx_htx_s cn56xxp1;
1610 struct cvmx_mio_uartx_htx_s cn58xx; 2489 struct cvmx_mio_uartx_htx_s cn58xx;
1611 struct cvmx_mio_uartx_htx_s cn58xxp1; 2490 struct cvmx_mio_uartx_htx_s cn58xxp1;
2491 struct cvmx_mio_uartx_htx_s cn61xx;
1612 struct cvmx_mio_uartx_htx_s cn63xx; 2492 struct cvmx_mio_uartx_htx_s cn63xx;
1613 struct cvmx_mio_uartx_htx_s cn63xxp1; 2493 struct cvmx_mio_uartx_htx_s cn63xxp1;
2494 struct cvmx_mio_uartx_htx_s cn66xx;
2495 struct cvmx_mio_uartx_htx_s cn68xx;
2496 struct cvmx_mio_uartx_htx_s cn68xxp1;
1614}; 2497};
1615 2498
1616union cvmx_mio_uartx_ier { 2499union cvmx_mio_uartx_ier {
@@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier {
1635 struct cvmx_mio_uartx_ier_s cn56xxp1; 2518 struct cvmx_mio_uartx_ier_s cn56xxp1;
1636 struct cvmx_mio_uartx_ier_s cn58xx; 2519 struct cvmx_mio_uartx_ier_s cn58xx;
1637 struct cvmx_mio_uartx_ier_s cn58xxp1; 2520 struct cvmx_mio_uartx_ier_s cn58xxp1;
2521 struct cvmx_mio_uartx_ier_s cn61xx;
1638 struct cvmx_mio_uartx_ier_s cn63xx; 2522 struct cvmx_mio_uartx_ier_s cn63xx;
1639 struct cvmx_mio_uartx_ier_s cn63xxp1; 2523 struct cvmx_mio_uartx_ier_s cn63xxp1;
2524 struct cvmx_mio_uartx_ier_s cn66xx;
2525 struct cvmx_mio_uartx_ier_s cn68xx;
2526 struct cvmx_mio_uartx_ier_s cn68xxp1;
1640}; 2527};
1641 2528
1642union cvmx_mio_uartx_iir { 2529union cvmx_mio_uartx_iir {
@@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir {
1658 struct cvmx_mio_uartx_iir_s cn56xxp1; 2545 struct cvmx_mio_uartx_iir_s cn56xxp1;
1659 struct cvmx_mio_uartx_iir_s cn58xx; 2546 struct cvmx_mio_uartx_iir_s cn58xx;
1660 struct cvmx_mio_uartx_iir_s cn58xxp1; 2547 struct cvmx_mio_uartx_iir_s cn58xxp1;
2548 struct cvmx_mio_uartx_iir_s cn61xx;
1661 struct cvmx_mio_uartx_iir_s cn63xx; 2549 struct cvmx_mio_uartx_iir_s cn63xx;
1662 struct cvmx_mio_uartx_iir_s cn63xxp1; 2550 struct cvmx_mio_uartx_iir_s cn63xxp1;
2551 struct cvmx_mio_uartx_iir_s cn66xx;
2552 struct cvmx_mio_uartx_iir_s cn68xx;
2553 struct cvmx_mio_uartx_iir_s cn68xxp1;
1663}; 2554};
1664 2555
1665union cvmx_mio_uartx_lcr { 2556union cvmx_mio_uartx_lcr {
@@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr {
1685 struct cvmx_mio_uartx_lcr_s cn56xxp1; 2576 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1686 struct cvmx_mio_uartx_lcr_s cn58xx; 2577 struct cvmx_mio_uartx_lcr_s cn58xx;
1687 struct cvmx_mio_uartx_lcr_s cn58xxp1; 2578 struct cvmx_mio_uartx_lcr_s cn58xxp1;
2579 struct cvmx_mio_uartx_lcr_s cn61xx;
1688 struct cvmx_mio_uartx_lcr_s cn63xx; 2580 struct cvmx_mio_uartx_lcr_s cn63xx;
1689 struct cvmx_mio_uartx_lcr_s cn63xxp1; 2581 struct cvmx_mio_uartx_lcr_s cn63xxp1;
2582 struct cvmx_mio_uartx_lcr_s cn66xx;
2583 struct cvmx_mio_uartx_lcr_s cn68xx;
2584 struct cvmx_mio_uartx_lcr_s cn68xxp1;
1690}; 2585};
1691 2586
1692union cvmx_mio_uartx_lsr { 2587union cvmx_mio_uartx_lsr {
@@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr {
1713 struct cvmx_mio_uartx_lsr_s cn56xxp1; 2608 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1714 struct cvmx_mio_uartx_lsr_s cn58xx; 2609 struct cvmx_mio_uartx_lsr_s cn58xx;
1715 struct cvmx_mio_uartx_lsr_s cn58xxp1; 2610 struct cvmx_mio_uartx_lsr_s cn58xxp1;
2611 struct cvmx_mio_uartx_lsr_s cn61xx;
1716 struct cvmx_mio_uartx_lsr_s cn63xx; 2612 struct cvmx_mio_uartx_lsr_s cn63xx;
1717 struct cvmx_mio_uartx_lsr_s cn63xxp1; 2613 struct cvmx_mio_uartx_lsr_s cn63xxp1;
2614 struct cvmx_mio_uartx_lsr_s cn66xx;
2615 struct cvmx_mio_uartx_lsr_s cn68xx;
2616 struct cvmx_mio_uartx_lsr_s cn68xxp1;
1718}; 2617};
1719 2618
1720union cvmx_mio_uartx_mcr { 2619union cvmx_mio_uartx_mcr {
@@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr {
1739 struct cvmx_mio_uartx_mcr_s cn56xxp1; 2638 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1740 struct cvmx_mio_uartx_mcr_s cn58xx; 2639 struct cvmx_mio_uartx_mcr_s cn58xx;
1741 struct cvmx_mio_uartx_mcr_s cn58xxp1; 2640 struct cvmx_mio_uartx_mcr_s cn58xxp1;
2641 struct cvmx_mio_uartx_mcr_s cn61xx;
1742 struct cvmx_mio_uartx_mcr_s cn63xx; 2642 struct cvmx_mio_uartx_mcr_s cn63xx;
1743 struct cvmx_mio_uartx_mcr_s cn63xxp1; 2643 struct cvmx_mio_uartx_mcr_s cn63xxp1;
2644 struct cvmx_mio_uartx_mcr_s cn66xx;
2645 struct cvmx_mio_uartx_mcr_s cn68xx;
2646 struct cvmx_mio_uartx_mcr_s cn68xxp1;
1744}; 2647};
1745 2648
1746union cvmx_mio_uartx_msr { 2649union cvmx_mio_uartx_msr {
@@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr {
1767 struct cvmx_mio_uartx_msr_s cn56xxp1; 2670 struct cvmx_mio_uartx_msr_s cn56xxp1;
1768 struct cvmx_mio_uartx_msr_s cn58xx; 2671 struct cvmx_mio_uartx_msr_s cn58xx;
1769 struct cvmx_mio_uartx_msr_s cn58xxp1; 2672 struct cvmx_mio_uartx_msr_s cn58xxp1;
2673 struct cvmx_mio_uartx_msr_s cn61xx;
1770 struct cvmx_mio_uartx_msr_s cn63xx; 2674 struct cvmx_mio_uartx_msr_s cn63xx;
1771 struct cvmx_mio_uartx_msr_s cn63xxp1; 2675 struct cvmx_mio_uartx_msr_s cn63xxp1;
2676 struct cvmx_mio_uartx_msr_s cn66xx;
2677 struct cvmx_mio_uartx_msr_s cn68xx;
2678 struct cvmx_mio_uartx_msr_s cn68xxp1;
1772}; 2679};
1773 2680
1774union cvmx_mio_uartx_rbr { 2681union cvmx_mio_uartx_rbr {
@@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr {
1788 struct cvmx_mio_uartx_rbr_s cn56xxp1; 2695 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1789 struct cvmx_mio_uartx_rbr_s cn58xx; 2696 struct cvmx_mio_uartx_rbr_s cn58xx;
1790 struct cvmx_mio_uartx_rbr_s cn58xxp1; 2697 struct cvmx_mio_uartx_rbr_s cn58xxp1;
2698 struct cvmx_mio_uartx_rbr_s cn61xx;
1791 struct cvmx_mio_uartx_rbr_s cn63xx; 2699 struct cvmx_mio_uartx_rbr_s cn63xx;
1792 struct cvmx_mio_uartx_rbr_s cn63xxp1; 2700 struct cvmx_mio_uartx_rbr_s cn63xxp1;
2701 struct cvmx_mio_uartx_rbr_s cn66xx;
2702 struct cvmx_mio_uartx_rbr_s cn68xx;
2703 struct cvmx_mio_uartx_rbr_s cn68xxp1;
1793}; 2704};
1794 2705
1795union cvmx_mio_uartx_rfl { 2706union cvmx_mio_uartx_rfl {
@@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl {
1809 struct cvmx_mio_uartx_rfl_s cn56xxp1; 2720 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1810 struct cvmx_mio_uartx_rfl_s cn58xx; 2721 struct cvmx_mio_uartx_rfl_s cn58xx;
1811 struct cvmx_mio_uartx_rfl_s cn58xxp1; 2722 struct cvmx_mio_uartx_rfl_s cn58xxp1;
2723 struct cvmx_mio_uartx_rfl_s cn61xx;
1812 struct cvmx_mio_uartx_rfl_s cn63xx; 2724 struct cvmx_mio_uartx_rfl_s cn63xx;
1813 struct cvmx_mio_uartx_rfl_s cn63xxp1; 2725 struct cvmx_mio_uartx_rfl_s cn63xxp1;
2726 struct cvmx_mio_uartx_rfl_s cn66xx;
2727 struct cvmx_mio_uartx_rfl_s cn68xx;
2728 struct cvmx_mio_uartx_rfl_s cn68xxp1;
1814}; 2729};
1815 2730
1816union cvmx_mio_uartx_rfw { 2731union cvmx_mio_uartx_rfw {
@@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw {
1832 struct cvmx_mio_uartx_rfw_s cn56xxp1; 2747 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1833 struct cvmx_mio_uartx_rfw_s cn58xx; 2748 struct cvmx_mio_uartx_rfw_s cn58xx;
1834 struct cvmx_mio_uartx_rfw_s cn58xxp1; 2749 struct cvmx_mio_uartx_rfw_s cn58xxp1;
2750 struct cvmx_mio_uartx_rfw_s cn61xx;
1835 struct cvmx_mio_uartx_rfw_s cn63xx; 2751 struct cvmx_mio_uartx_rfw_s cn63xx;
1836 struct cvmx_mio_uartx_rfw_s cn63xxp1; 2752 struct cvmx_mio_uartx_rfw_s cn63xxp1;
2753 struct cvmx_mio_uartx_rfw_s cn66xx;
2754 struct cvmx_mio_uartx_rfw_s cn68xx;
2755 struct cvmx_mio_uartx_rfw_s cn68xxp1;
1837}; 2756};
1838 2757
1839union cvmx_mio_uartx_sbcr { 2758union cvmx_mio_uartx_sbcr {
@@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr {
1853 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 2772 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1854 struct cvmx_mio_uartx_sbcr_s cn58xx; 2773 struct cvmx_mio_uartx_sbcr_s cn58xx;
1855 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 2774 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
2775 struct cvmx_mio_uartx_sbcr_s cn61xx;
1856 struct cvmx_mio_uartx_sbcr_s cn63xx; 2776 struct cvmx_mio_uartx_sbcr_s cn63xx;
1857 struct cvmx_mio_uartx_sbcr_s cn63xxp1; 2777 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
2778 struct cvmx_mio_uartx_sbcr_s cn66xx;
2779 struct cvmx_mio_uartx_sbcr_s cn68xx;
2780 struct cvmx_mio_uartx_sbcr_s cn68xxp1;
1858}; 2781};
1859 2782
1860union cvmx_mio_uartx_scr { 2783union cvmx_mio_uartx_scr {
@@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr {
1874 struct cvmx_mio_uartx_scr_s cn56xxp1; 2797 struct cvmx_mio_uartx_scr_s cn56xxp1;
1875 struct cvmx_mio_uartx_scr_s cn58xx; 2798 struct cvmx_mio_uartx_scr_s cn58xx;
1876 struct cvmx_mio_uartx_scr_s cn58xxp1; 2799 struct cvmx_mio_uartx_scr_s cn58xxp1;
2800 struct cvmx_mio_uartx_scr_s cn61xx;
1877 struct cvmx_mio_uartx_scr_s cn63xx; 2801 struct cvmx_mio_uartx_scr_s cn63xx;
1878 struct cvmx_mio_uartx_scr_s cn63xxp1; 2802 struct cvmx_mio_uartx_scr_s cn63xxp1;
2803 struct cvmx_mio_uartx_scr_s cn66xx;
2804 struct cvmx_mio_uartx_scr_s cn68xx;
2805 struct cvmx_mio_uartx_scr_s cn68xxp1;
1879}; 2806};
1880 2807
1881union cvmx_mio_uartx_sfe { 2808union cvmx_mio_uartx_sfe {
@@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe {
1895 struct cvmx_mio_uartx_sfe_s cn56xxp1; 2822 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1896 struct cvmx_mio_uartx_sfe_s cn58xx; 2823 struct cvmx_mio_uartx_sfe_s cn58xx;
1897 struct cvmx_mio_uartx_sfe_s cn58xxp1; 2824 struct cvmx_mio_uartx_sfe_s cn58xxp1;
2825 struct cvmx_mio_uartx_sfe_s cn61xx;
1898 struct cvmx_mio_uartx_sfe_s cn63xx; 2826 struct cvmx_mio_uartx_sfe_s cn63xx;
1899 struct cvmx_mio_uartx_sfe_s cn63xxp1; 2827 struct cvmx_mio_uartx_sfe_s cn63xxp1;
2828 struct cvmx_mio_uartx_sfe_s cn66xx;
2829 struct cvmx_mio_uartx_sfe_s cn68xx;
2830 struct cvmx_mio_uartx_sfe_s cn68xxp1;
1900}; 2831};
1901 2832
1902union cvmx_mio_uartx_srr { 2833union cvmx_mio_uartx_srr {
@@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr {
1918 struct cvmx_mio_uartx_srr_s cn56xxp1; 2849 struct cvmx_mio_uartx_srr_s cn56xxp1;
1919 struct cvmx_mio_uartx_srr_s cn58xx; 2850 struct cvmx_mio_uartx_srr_s cn58xx;
1920 struct cvmx_mio_uartx_srr_s cn58xxp1; 2851 struct cvmx_mio_uartx_srr_s cn58xxp1;
2852 struct cvmx_mio_uartx_srr_s cn61xx;
1921 struct cvmx_mio_uartx_srr_s cn63xx; 2853 struct cvmx_mio_uartx_srr_s cn63xx;
1922 struct cvmx_mio_uartx_srr_s cn63xxp1; 2854 struct cvmx_mio_uartx_srr_s cn63xxp1;
2855 struct cvmx_mio_uartx_srr_s cn66xx;
2856 struct cvmx_mio_uartx_srr_s cn68xx;
2857 struct cvmx_mio_uartx_srr_s cn68xxp1;
1923}; 2858};
1924 2859
1925union cvmx_mio_uartx_srt { 2860union cvmx_mio_uartx_srt {
@@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt {
1939 struct cvmx_mio_uartx_srt_s cn56xxp1; 2874 struct cvmx_mio_uartx_srt_s cn56xxp1;
1940 struct cvmx_mio_uartx_srt_s cn58xx; 2875 struct cvmx_mio_uartx_srt_s cn58xx;
1941 struct cvmx_mio_uartx_srt_s cn58xxp1; 2876 struct cvmx_mio_uartx_srt_s cn58xxp1;
2877 struct cvmx_mio_uartx_srt_s cn61xx;
1942 struct cvmx_mio_uartx_srt_s cn63xx; 2878 struct cvmx_mio_uartx_srt_s cn63xx;
1943 struct cvmx_mio_uartx_srt_s cn63xxp1; 2879 struct cvmx_mio_uartx_srt_s cn63xxp1;
2880 struct cvmx_mio_uartx_srt_s cn66xx;
2881 struct cvmx_mio_uartx_srt_s cn68xx;
2882 struct cvmx_mio_uartx_srt_s cn68xxp1;
1944}; 2883};
1945 2884
1946union cvmx_mio_uartx_srts { 2885union cvmx_mio_uartx_srts {
@@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts {
1960 struct cvmx_mio_uartx_srts_s cn56xxp1; 2899 struct cvmx_mio_uartx_srts_s cn56xxp1;
1961 struct cvmx_mio_uartx_srts_s cn58xx; 2900 struct cvmx_mio_uartx_srts_s cn58xx;
1962 struct cvmx_mio_uartx_srts_s cn58xxp1; 2901 struct cvmx_mio_uartx_srts_s cn58xxp1;
2902 struct cvmx_mio_uartx_srts_s cn61xx;
1963 struct cvmx_mio_uartx_srts_s cn63xx; 2903 struct cvmx_mio_uartx_srts_s cn63xx;
1964 struct cvmx_mio_uartx_srts_s cn63xxp1; 2904 struct cvmx_mio_uartx_srts_s cn63xxp1;
2905 struct cvmx_mio_uartx_srts_s cn66xx;
2906 struct cvmx_mio_uartx_srts_s cn68xx;
2907 struct cvmx_mio_uartx_srts_s cn68xxp1;
1965}; 2908};
1966 2909
1967union cvmx_mio_uartx_stt { 2910union cvmx_mio_uartx_stt {
@@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt {
1981 struct cvmx_mio_uartx_stt_s cn56xxp1; 2924 struct cvmx_mio_uartx_stt_s cn56xxp1;
1982 struct cvmx_mio_uartx_stt_s cn58xx; 2925 struct cvmx_mio_uartx_stt_s cn58xx;
1983 struct cvmx_mio_uartx_stt_s cn58xxp1; 2926 struct cvmx_mio_uartx_stt_s cn58xxp1;
2927 struct cvmx_mio_uartx_stt_s cn61xx;
1984 struct cvmx_mio_uartx_stt_s cn63xx; 2928 struct cvmx_mio_uartx_stt_s cn63xx;
1985 struct cvmx_mio_uartx_stt_s cn63xxp1; 2929 struct cvmx_mio_uartx_stt_s cn63xxp1;
2930 struct cvmx_mio_uartx_stt_s cn66xx;
2931 struct cvmx_mio_uartx_stt_s cn68xx;
2932 struct cvmx_mio_uartx_stt_s cn68xxp1;
1986}; 2933};
1987 2934
1988union cvmx_mio_uartx_tfl { 2935union cvmx_mio_uartx_tfl {
@@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl {
2002 struct cvmx_mio_uartx_tfl_s cn56xxp1; 2949 struct cvmx_mio_uartx_tfl_s cn56xxp1;
2003 struct cvmx_mio_uartx_tfl_s cn58xx; 2950 struct cvmx_mio_uartx_tfl_s cn58xx;
2004 struct cvmx_mio_uartx_tfl_s cn58xxp1; 2951 struct cvmx_mio_uartx_tfl_s cn58xxp1;
2952 struct cvmx_mio_uartx_tfl_s cn61xx;
2005 struct cvmx_mio_uartx_tfl_s cn63xx; 2953 struct cvmx_mio_uartx_tfl_s cn63xx;
2006 struct cvmx_mio_uartx_tfl_s cn63xxp1; 2954 struct cvmx_mio_uartx_tfl_s cn63xxp1;
2955 struct cvmx_mio_uartx_tfl_s cn66xx;
2956 struct cvmx_mio_uartx_tfl_s cn68xx;
2957 struct cvmx_mio_uartx_tfl_s cn68xxp1;
2007}; 2958};
2008 2959
2009union cvmx_mio_uartx_tfr { 2960union cvmx_mio_uartx_tfr {
@@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr {
2023 struct cvmx_mio_uartx_tfr_s cn56xxp1; 2974 struct cvmx_mio_uartx_tfr_s cn56xxp1;
2024 struct cvmx_mio_uartx_tfr_s cn58xx; 2975 struct cvmx_mio_uartx_tfr_s cn58xx;
2025 struct cvmx_mio_uartx_tfr_s cn58xxp1; 2976 struct cvmx_mio_uartx_tfr_s cn58xxp1;
2977 struct cvmx_mio_uartx_tfr_s cn61xx;
2026 struct cvmx_mio_uartx_tfr_s cn63xx; 2978 struct cvmx_mio_uartx_tfr_s cn63xx;
2027 struct cvmx_mio_uartx_tfr_s cn63xxp1; 2979 struct cvmx_mio_uartx_tfr_s cn63xxp1;
2980 struct cvmx_mio_uartx_tfr_s cn66xx;
2981 struct cvmx_mio_uartx_tfr_s cn68xx;
2982 struct cvmx_mio_uartx_tfr_s cn68xxp1;
2028}; 2983};
2029 2984
2030union cvmx_mio_uartx_thr { 2985union cvmx_mio_uartx_thr {
@@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr {
2044 struct cvmx_mio_uartx_thr_s cn56xxp1; 2999 struct cvmx_mio_uartx_thr_s cn56xxp1;
2045 struct cvmx_mio_uartx_thr_s cn58xx; 3000 struct cvmx_mio_uartx_thr_s cn58xx;
2046 struct cvmx_mio_uartx_thr_s cn58xxp1; 3001 struct cvmx_mio_uartx_thr_s cn58xxp1;
3002 struct cvmx_mio_uartx_thr_s cn61xx;
2047 struct cvmx_mio_uartx_thr_s cn63xx; 3003 struct cvmx_mio_uartx_thr_s cn63xx;
2048 struct cvmx_mio_uartx_thr_s cn63xxp1; 3004 struct cvmx_mio_uartx_thr_s cn63xxp1;
3005 struct cvmx_mio_uartx_thr_s cn66xx;
3006 struct cvmx_mio_uartx_thr_s cn68xx;
3007 struct cvmx_mio_uartx_thr_s cn68xxp1;
2049}; 3008};
2050 3009
2051union cvmx_mio_uartx_usr { 3010union cvmx_mio_uartx_usr {
@@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr {
2069 struct cvmx_mio_uartx_usr_s cn56xxp1; 3028 struct cvmx_mio_uartx_usr_s cn56xxp1;
2070 struct cvmx_mio_uartx_usr_s cn58xx; 3029 struct cvmx_mio_uartx_usr_s cn58xx;
2071 struct cvmx_mio_uartx_usr_s cn58xxp1; 3030 struct cvmx_mio_uartx_usr_s cn58xxp1;
3031 struct cvmx_mio_uartx_usr_s cn61xx;
2072 struct cvmx_mio_uartx_usr_s cn63xx; 3032 struct cvmx_mio_uartx_usr_s cn63xx;
2073 struct cvmx_mio_uartx_usr_s cn63xxp1; 3033 struct cvmx_mio_uartx_usr_s cn63xxp1;
3034 struct cvmx_mio_uartx_usr_s cn66xx;
3035 struct cvmx_mio_uartx_usr_s cn68xx;
3036 struct cvmx_mio_uartx_usr_s cn68xxp1;
2074}; 3037};
2075 3038
2076union cvmx_mio_uart2_dlh { 3039union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 700f88e31cad..4e338a4d9424 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -24,14 +24,6 @@
24 * This file may also be available under a different license from Cavium. 24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__ 27#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__ 28#define __OCTEON_MODEL_H__
37 29
@@ -52,6 +44,8 @@
52 * for internal use only, and may change without notice. 44 * for internal use only, and may change without notice.
53 */ 45 */
54 46
47#define OCTEON_FAMILY_MASK 0x00ffff00
48
55/* Flag bits in top byte */ 49/* Flag bits in top byte */
56/* Ignores revision in model checks */ 50/* Ignores revision in model checks */
57#define OM_IGNORE_REVISION 0x01000000 51#define OM_IGNORE_REVISION 0x01000000
@@ -63,21 +57,48 @@
63#define OM_IGNORE_MINOR_REVISION 0x08000000 57#define OM_IGNORE_MINOR_REVISION 0x08000000
64#define OM_FLAG_MASK 0xff000000 58#define OM_FLAG_MASK 0xff000000
65 59
66#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */ 60/* Match all cn5XXX Octeon models. */
67#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */ 61#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000
62/* Match all cn6XXX Octeon models. */
63#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
68 64
69/* 65/*
70 * CN6XXX models with new revision encoding 66 * CN6XXX models with new revision encoding
71 */ 67 */
68#define OCTEON_CN68XX_PASS1_0 0x000d9100
69#define OCTEON_CN68XX_PASS1_1 0x000d9101
70#define OCTEON_CN68XX_PASS1_2 0x000d9102
71#define OCTEON_CN68XX_PASS2_0 0x000d9108
72
73#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
74#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
75#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
76
77#define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X
78#define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X
79
80#define OCTEON_CN66XX_PASS1_0 0x000d9200
81#define OCTEON_CN66XX_PASS1_2 0x000d9202
82
83#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
84#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
85
72#define OCTEON_CN63XX_PASS1_0 0x000d9000 86#define OCTEON_CN63XX_PASS1_0 0x000d9000
73#define OCTEON_CN63XX_PASS1_1 0x000d9001 87#define OCTEON_CN63XX_PASS1_1 0x000d9001
74#define OCTEON_CN63XX_PASS1_2 0x000d9002 88#define OCTEON_CN63XX_PASS1_2 0x000d9002
75#define OCTEON_CN63XX_PASS2_0 0x000d9008 89#define OCTEON_CN63XX_PASS2_0 0x000d9008
90#define OCTEON_CN63XX_PASS2_1 0x000d9009
91#define OCTEON_CN63XX_PASS2_2 0x000d900a
76 92
77#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) 93#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
78#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 94#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
79#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) 95#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
80 96
97#define OCTEON_CN61XX_PASS1_0 0x000d9300
98
99#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
100#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
101
81/* 102/*
82 * CN5XXX models with new revision encoding 103 * CN5XXX models with new revision encoding
83 */ 104 */
@@ -90,10 +111,8 @@
90#define OCTEON_CN58XX_PASS2_3 0x000d030b 111#define OCTEON_CN58XX_PASS2_3 0x000d030b
91 112
92#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) 113#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
93#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ 114#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
94 | OM_IGNORE_MINOR_REVISION) 115#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
95#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
96 | OM_IGNORE_MINOR_REVISION)
97#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X 116#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
98#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X 117#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
99 118
@@ -103,10 +122,8 @@
103#define OCTEON_CN56XX_PASS2_1 0x000d0409 122#define OCTEON_CN56XX_PASS2_1 0x000d0409
104 123
105#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) 124#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
106#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ 125#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
107 | OM_IGNORE_MINOR_REVISION) 126#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
108#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
109 | OM_IGNORE_MINOR_REVISION)
110#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X 127#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
111#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X 128#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
112 129
@@ -125,8 +142,7 @@
125#define OCTEON_CN50XX_PASS1_0 0x000d0600 142#define OCTEON_CN50XX_PASS1_0 0x000d0600
126 143
127#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) 144#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
128#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ 145#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
129 | OM_IGNORE_MINOR_REVISION)
130#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X 146#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
131 147
132/* 148/*
@@ -138,10 +154,8 @@
138#define OCTEON_CN52XX_PASS2_0 0x000d0708 154#define OCTEON_CN52XX_PASS2_0 0x000d0708
139 155
140#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) 156#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
141#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ 157#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
142 | OM_IGNORE_MINOR_REVISION) 158#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
143#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
144 | OM_IGNORE_MINOR_REVISION)
145#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X 159#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
146#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X 160#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
147 161
@@ -174,28 +188,23 @@
174#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) 188#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) 189#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) 190#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
177#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ 191#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
178 | OM_CHECK_SUBMODEL)
179 192
180#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) 193#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) 194#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) 195#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
183#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ 196#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
184 | OM_CHECK_SUBMODEL)
185 197
186#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) 198#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
187#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) 199#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
188#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) 200#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
189#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ 201#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
190 | OM_CHECK_SUBMODEL)
191
192
193
194/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
195#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
196 | OM_MATCH_PREVIOUS_MODELS \
197 | OM_IGNORE_REVISION)
198 202
203/*
204 * This matches the complete family of CN3xxx CPUs, and not subsequent
205 * models
206 */
207#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
199#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) 208#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
200#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) 209#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
201 210
@@ -221,90 +230,55 @@
221#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 230#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
222#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f 231#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
223#define OCTEON_38XX_MODEL_MASK 0x00ffff10 232#define OCTEON_38XX_MODEL_MASK 0x00ffff10
224#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ 233#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
225 | OCTEON_38XX_MODEL_MASK)
226 234
227/* CN5XXX and later use different layout of bits in the revision ID field */ 235/* CN5XXX and later use different layout of bits in the revision ID field */
228#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK 236#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
229#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f 237#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
230#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 238#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
231#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ 239#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
232 | OCTEON_58XX_MODEL_MASK) 240#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
233#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
234 & 0x00fffff8)
235#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 241#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
236 242
237#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
238
239/* NOTE: This is for internal (to this file) use only. */
240static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
241 uint32_t chip_model)
242{
243 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
244
245 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
246 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
247 __OCTEON_MATCH_MASK__(chip_model, arg_model,
248 OCTEON_38XX_MODEL_MASK))
249 return 1;
250 if (((arg_model & OM_FLAG_MASK) == 0) &&
251 __OCTEON_MATCH_MASK__(chip_model, arg_model,
252 OCTEON_38XX_FAMILY_REV_MASK))
253 return 1;
254 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
255 __OCTEON_MATCH_MASK__(chip_model, arg_model,
256 OCTEON_38XX_FAMILY_MASK))
257 return 1;
258 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
259 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
260 OCTEON_38XX_MODEL_REV_MASK))
261 return 1;
262 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
263 ((chip_model & OCTEON_38XX_MODEL_MASK) <
264 (arg_model & OCTEON_38XX_MODEL_MASK)))
265 return 1;
266 } else {
267 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
268 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
269 OCTEON_58XX_MODEL_MASK))
270 return 1;
271 if (((arg_model & OM_FLAG_MASK) == 0) &&
272 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
273 OCTEON_58XX_FAMILY_REV_MASK))
274 return 1;
275 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
276 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
277 OCTEON_58XX_MODEL_MINOR_REV_MASK))
278 return 1;
279 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
280 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
281 OCTEON_58XX_FAMILY_MASK))
282 return 1;
283 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
284 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
285 OCTEON_58XX_MODEL_REV_MASK))
286 return 1;
287
288 if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
289 ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
290 return 1;
291
292 if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
293 ((chip_model) >= OCTEON_CN63XX_PASS1_0))
294 return 1;
295
296 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
297 ((chip_model & OCTEON_58XX_MODEL_MASK) <
298 (arg_model & OCTEON_58XX_MODEL_MASK)))
299 return 1;
300 }
301 return 0;
302}
303
304/* forward declarations */ 243/* forward declarations */
305static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); 244static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
306static inline uint64_t cvmx_read_csr(uint64_t csr_addr); 245static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
307 246
247#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
248
249/* NOTE: This for internal use only! */
250#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
251((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \
252 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
253 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
254 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
255 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
256 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
257 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
258 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
259 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
260 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
261 && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
262 )) || \
263 (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \
264 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
265 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
266 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
267 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
268 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
269 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
270 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
271 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
272 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
273 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
274 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
275 && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
276 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
277 && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
278 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
279 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
280 )))
281
308/* NOTE: This for internal use only!!!!! */ 282/* NOTE: This for internal use only!!!!! */
309static inline int __octeon_is_model_runtime__(uint32_t model) 283static inline int __octeon_is_model_runtime__(uint32_t model)
310{ 284{
@@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
312 286
313 /* 287 /*
314 * Check for special case of mismarked 3005 samples. We only 288 * Check for special case of mismarked 3005 samples. We only
315 * need to check if the sub model isn't being ignored. 289 * need to check if the sub model isn't being ignored
316 */ 290 */
317 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { 291 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
318 if (cpuid == OCTEON_CN3010_PASS1 \ 292 if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
319 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
320 cpuid |= 0x10; 293 cpuid |= 0x10;
321 } 294 }
322 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); 295 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
323} 296}
324 297
325/* 298/*
326 * The OCTEON_IS_MODEL macro should be used for all Octeon model 299 * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
327 * checking done in a program. This should be kept runtime if at all 300 * in a program.
328 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be 301 * This should be kept runtime if at all possible and must be conditionalized
329 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking 302 * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
330 * support is required. 303 *
304 * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
305 * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
306 * I.e.:
307 * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
331 */ 308 */
332#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) 309#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
333#define OCTEON_IS_COMMON_BINARY() 1 310#define OCTEON_IS_COMMON_BINARY() 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 03:21:17 -0500