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authorDavid Daney <david.daney@cavium.com>2012-07-05 12:12:38 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-23 08:54:52 -0400
commit736b1c9c957e38b80d2e36b2ed196fa1c07468bc (patch)
tree23603989a3dcd7723a0be7448648bc5f8584ceee /arch
parentab25383983fb8d7786696f5371e75e79c3e9a405 (diff)
MIPS: Octeon: Add device tree source files.
The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/3937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cavium-octeon/.gitignore2
-rw-r--r--arch/mips/cavium-octeon/Makefile13
-rw-r--r--arch/mips/cavium-octeon/octeon_3xxx.dts571
-rw-r--r--arch/mips/cavium-octeon/octeon_68xx.dts625
4 files changed, 1211 insertions, 0 deletions
diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore
new file mode 100644
index 000000000000..39c968605ff6
--- /dev/null
+++ b/arch/mips/cavium-octeon/.gitignore
@@ -0,0 +1,2 @@
1*.dtb.S
2*.dtb
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 19eb0434269f..1e37522cc21f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o
15obj-y += executive/ 15obj-y += executive/
16 16
17obj-$(CONFIG_SMP) += smp.o 17obj-$(CONFIG_SMP) += smp.o
18
19DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
20DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
21
22obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES))
23
24$(obj)/%.dtb: $(src)/%.dts FORCE
25 $(call if_changed_dep,dtc)
26
27# Let's keep the .dtb files around in case we want to look at them.
28.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES))
29
30clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES))
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
new file mode 100644
index 000000000000..f28b2d0fde22
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -0,0 +1,571 @@
1/dts-v1/;
2/*
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
4 *
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
8 */
9/ {
10 compatible = "cavium,octeon-3860";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu: interrupt-controller@1070000000000 {
22 compatible = "cavium,octeon-3860-ciu";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 1)
26 * 2) Bit within the register (0..63)
27 */
28 #interrupt-cells = <2>;
29 reg = <0x10700 0x00000000 0x0 0x7000>;
30 };
31
32 gpio: gpio-controller@1070000000800 {
33 #gpio-cells = <2>;
34 compatible = "cavium,octeon-3860-gpio";
35 reg = <0x10700 0x00000800 0x0 0x100>;
36 gpio-controller;
37 /* Interrupts are specified by two parts:
38 * 1) GPIO pin number (0..15)
39 * 2) Triggering (1 - edge rising
40 * 2 - edge falling
41 * 4 - level active high
42 * 8 - level active low)
43 */
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 /* The GPIO pin connect to 16 consecutive CUI bits */
47 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
48 <0 20>, <0 21>, <0 22>, <0 23>,
49 <0 24>, <0 25>, <0 26>, <0 27>,
50 <0 28>, <0 29>, <0 30>, <0 31>;
51 };
52
53 smi0: mdio@1180000001800 {
54 compatible = "cavium,octeon-3860-mdio";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 reg = <0x11800 0x00001800 0x0 0x40>;
58
59 phy0: ethernet-phy@0 {
60 compatible = "marvell,88e1118";
61 marvell,reg-init =
62 /* Fix rx and tx clock transition timing */
63 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
64 /* Adjust LED drive. */
65 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
66 /* irq, blink-activity, blink-link */
67 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
68 reg = <0>;
69 };
70
71 phy1: ethernet-phy@1 {
72 compatible = "marvell,88e1118";
73 marvell,reg-init =
74 /* Fix rx and tx clock transition timing */
75 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
76 /* Adjust LED drive. */
77 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
78 /* irq, blink-activity, blink-link */
79 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
80 reg = <1>;
81 };
82
83 phy2: ethernet-phy@2 {
84 reg = <2>;
85 compatible = "marvell,88e1149r";
86 marvell,reg-init = <3 0x10 0 0x5777>,
87 <3 0x11 0 0x00aa>,
88 <3 0x12 0 0x4105>,
89 <3 0x13 0 0x0a60>;
90 };
91 phy3: ethernet-phy@3 {
92 reg = <3>;
93 compatible = "marvell,88e1149r";
94 marvell,reg-init = <3 0x10 0 0x5777>,
95 <3 0x11 0 0x00aa>,
96 <3 0x12 0 0x4105>,
97 <3 0x13 0 0x0a60>;
98 };
99 phy4: ethernet-phy@4 {
100 reg = <4>;
101 compatible = "marvell,88e1149r";
102 marvell,reg-init = <3 0x10 0 0x5777>,
103 <3 0x11 0 0x00aa>,
104 <3 0x12 0 0x4105>,
105 <3 0x13 0 0x0a60>;
106 };
107 phy5: ethernet-phy@5 {
108 reg = <5>;
109 compatible = "marvell,88e1149r";
110 marvell,reg-init = <3 0x10 0 0x5777>,
111 <3 0x11 0 0x00aa>,
112 <3 0x12 0 0x4105>,
113 <3 0x13 0 0x0a60>;
114 };
115
116 phy6: ethernet-phy@6 {
117 reg = <6>;
118 compatible = "marvell,88e1149r";
119 marvell,reg-init = <3 0x10 0 0x5777>,
120 <3 0x11 0 0x00aa>,
121 <3 0x12 0 0x4105>,
122 <3 0x13 0 0x0a60>;
123 };
124 phy7: ethernet-phy@7 {
125 reg = <7>;
126 compatible = "marvell,88e1149r";
127 marvell,reg-init = <3 0x10 0 0x5777>,
128 <3 0x11 0 0x00aa>,
129 <3 0x12 0 0x4105>,
130 <3 0x13 0 0x0a60>;
131 };
132 phy8: ethernet-phy@8 {
133 reg = <8>;
134 compatible = "marvell,88e1149r";
135 marvell,reg-init = <3 0x10 0 0x5777>,
136 <3 0x11 0 0x00aa>,
137 <3 0x12 0 0x4105>,
138 <3 0x13 0 0x0a60>;
139 };
140 phy9: ethernet-phy@9 {
141 reg = <9>;
142 compatible = "marvell,88e1149r";
143 marvell,reg-init = <3 0x10 0 0x5777>,
144 <3 0x11 0 0x00aa>,
145 <3 0x12 0 0x4105>,
146 <3 0x13 0 0x0a60>;
147 };
148 };
149
150 smi1: mdio@1180000001900 {
151 compatible = "cavium,octeon-3860-mdio";
152 #address-cells = <1>;
153 #size-cells = <0>;
154 reg = <0x11800 0x00001900 0x0 0x40>;
155
156 phy100: ethernet-phy@1 {
157 reg = <1>;
158 compatible = "marvell,88e1149r";
159 marvell,reg-init = <3 0x10 0 0x5777>,
160 <3 0x11 0 0x00aa>,
161 <3 0x12 0 0x4105>,
162 <3 0x13 0 0x0a60>;
163 interrupt-parent = <&gpio>;
164 interrupts = <12 8>; /* Pin 12, active low */
165 };
166 phy101: ethernet-phy@2 {
167 reg = <2>;
168 compatible = "marvell,88e1149r";
169 marvell,reg-init = <3 0x10 0 0x5777>,
170 <3 0x11 0 0x00aa>,
171 <3 0x12 0 0x4105>,
172 <3 0x13 0 0x0a60>;
173 interrupt-parent = <&gpio>;
174 interrupts = <12 8>; /* Pin 12, active low */
175 };
176 phy102: ethernet-phy@3 {
177 reg = <3>;
178 compatible = "marvell,88e1149r";
179 marvell,reg-init = <3 0x10 0 0x5777>,
180 <3 0x11 0 0x00aa>,
181 <3 0x12 0 0x4105>,
182 <3 0x13 0 0x0a60>;
183 interrupt-parent = <&gpio>;
184 interrupts = <12 8>; /* Pin 12, active low */
185 };
186 phy103: ethernet-phy@4 {
187 reg = <4>;
188 compatible = "marvell,88e1149r";
189 marvell,reg-init = <3 0x10 0 0x5777>,
190 <3 0x11 0 0x00aa>,
191 <3 0x12 0 0x4105>,
192 <3 0x13 0 0x0a60>;
193 interrupt-parent = <&gpio>;
194 interrupts = <12 8>; /* Pin 12, active low */
195 };
196 };
197
198 mix0: ethernet@1070000100000 {
199 compatible = "cavium,octeon-5750-mix";
200 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
201 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
202 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
203 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
204 cell-index = <0>;
205 interrupts = <0 62>, <1 46>;
206 local-mac-address = [ 00 00 00 00 00 00 ];
207 phy-handle = <&phy0>;
208 };
209
210 mix1: ethernet@1070000100800 {
211 compatible = "cavium,octeon-5750-mix";
212 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
213 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
214 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
215 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
216 cell-index = <1>;
217 interrupts = <1 18>, < 1 46>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 phy-handle = <&phy1>;
220 };
221
222 pip: pip@11800a0000000 {
223 compatible = "cavium,octeon-3860-pip";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x11800 0xa0000000 0x0 0x2000>;
227
228 interface@0 {
229 compatible = "cavium,octeon-3860-pip-interface";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>; /* interface */
233
234 ethernet@0 {
235 compatible = "cavium,octeon-3860-pip-port";
236 reg = <0x0>; /* Port */
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 phy-handle = <&phy2>;
239 cavium,alt-phy-handle = <&phy100>;
240 };
241 ethernet@1 {
242 compatible = "cavium,octeon-3860-pip-port";
243 reg = <0x1>; /* Port */
244 local-mac-address = [ 00 00 00 00 00 00 ];
245 phy-handle = <&phy3>;
246 cavium,alt-phy-handle = <&phy101>;
247 };
248 ethernet@2 {
249 compatible = "cavium,octeon-3860-pip-port";
250 reg = <0x2>; /* Port */
251 local-mac-address = [ 00 00 00 00 00 00 ];
252 phy-handle = <&phy4>;
253 cavium,alt-phy-handle = <&phy102>;
254 };
255 ethernet@3 {
256 compatible = "cavium,octeon-3860-pip-port";
257 reg = <0x3>; /* Port */
258 local-mac-address = [ 00 00 00 00 00 00 ];
259 phy-handle = <&phy5>;
260 cavium,alt-phy-handle = <&phy103>;
261 };
262 ethernet@4 {
263 compatible = "cavium,octeon-3860-pip-port";
264 reg = <0x4>; /* Port */
265 local-mac-address = [ 00 00 00 00 00 00 ];
266 };
267 ethernet@5 {
268 compatible = "cavium,octeon-3860-pip-port";
269 reg = <0x5>; /* Port */
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 };
272 ethernet@6 {
273 compatible = "cavium,octeon-3860-pip-port";
274 reg = <0x6>; /* Port */
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 };
277 ethernet@7 {
278 compatible = "cavium,octeon-3860-pip-port";
279 reg = <0x7>; /* Port */
280 local-mac-address = [ 00 00 00 00 00 00 ];
281 };
282 ethernet@8 {
283 compatible = "cavium,octeon-3860-pip-port";
284 reg = <0x8>; /* Port */
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 };
287 ethernet@9 {
288 compatible = "cavium,octeon-3860-pip-port";
289 reg = <0x9>; /* Port */
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 };
292 ethernet@a {
293 compatible = "cavium,octeon-3860-pip-port";
294 reg = <0xa>; /* Port */
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 };
297 ethernet@b {
298 compatible = "cavium,octeon-3860-pip-port";
299 reg = <0xb>; /* Port */
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 };
302 ethernet@c {
303 compatible = "cavium,octeon-3860-pip-port";
304 reg = <0xc>; /* Port */
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 };
307 ethernet@d {
308 compatible = "cavium,octeon-3860-pip-port";
309 reg = <0xd>; /* Port */
310 local-mac-address = [ 00 00 00 00 00 00 ];
311 };
312 ethernet@e {
313 compatible = "cavium,octeon-3860-pip-port";
314 reg = <0xe>; /* Port */
315 local-mac-address = [ 00 00 00 00 00 00 ];
316 };
317 ethernet@f {
318 compatible = "cavium,octeon-3860-pip-port";
319 reg = <0xf>; /* Port */
320 local-mac-address = [ 00 00 00 00 00 00 ];
321 };
322 };
323
324 interface@1 {
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <1>; /* interface */
329
330 ethernet@0 {
331 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 phy-handle = <&phy6>;
335 };
336 ethernet@1 {
337 compatible = "cavium,octeon-3860-pip-port";
338 reg = <0x1>; /* Port */
339 local-mac-address = [ 00 00 00 00 00 00 ];
340 phy-handle = <&phy7>;
341 };
342 ethernet@2 {
343 compatible = "cavium,octeon-3860-pip-port";
344 reg = <0x2>; /* Port */
345 local-mac-address = [ 00 00 00 00 00 00 ];
346 phy-handle = <&phy8>;
347 };
348 ethernet@3 {
349 compatible = "cavium,octeon-3860-pip-port";
350 reg = <0x3>; /* Port */
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 phy-handle = <&phy9>;
353 };
354 };
355 };
356
357 twsi0: i2c@1180000001000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "cavium,octeon-3860-twsi";
361 reg = <0x11800 0x00001000 0x0 0x200>;
362 interrupts = <0 45>;
363 clock-frequency = <100000>;
364
365 rtc@68 {
366 compatible = "dallas,ds1337";
367 reg = <0x68>;
368 };
369 tmp@4c {
370 compatible = "ti,tmp421";
371 reg = <0x4c>;
372 };
373 };
374
375 twsi1: i2c@1180000001200 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "cavium,octeon-3860-twsi";
379 reg = <0x11800 0x00001200 0x0 0x200>;
380 interrupts = <0 59>;
381 clock-frequency = <100000>;
382 };
383
384 uart0: serial@1180000000800 {
385 compatible = "cavium,octeon-3860-uart","ns16550";
386 reg = <0x11800 0x00000800 0x0 0x400>;
387 clock-frequency = <0>;
388 current-speed = <115200>;
389 reg-shift = <3>;
390 interrupts = <0 34>;
391 };
392
393 uart1: serial@1180000000c00 {
394 compatible = "cavium,octeon-3860-uart","ns16550";
395 reg = <0x11800 0x00000c00 0x0 0x400>;
396 clock-frequency = <0>;
397 current-speed = <115200>;
398 reg-shift = <3>;
399 interrupts = <0 35>;
400 };
401
402 uart2: serial@1180000000400 {
403 compatible = "cavium,octeon-3860-uart","ns16550";
404 reg = <0x11800 0x00000400 0x0 0x400>;
405 clock-frequency = <0>;
406 current-speed = <115200>;
407 reg-shift = <3>;
408 interrupts = <1 16>;
409 };
410
411 bootbus: bootbus@1180000000000 {
412 compatible = "cavium,octeon-3860-bootbus";
413 reg = <0x11800 0x00000000 0x0 0x200>;
414 /* The chip select number and offset */
415 #address-cells = <2>;
416 /* The size of the chip select region */
417 #size-cells = <1>;
418 ranges = <0 0 0x0 0x1f400000 0xc00000>,
419 <1 0 0x10000 0x30000000 0>,
420 <2 0 0x10000 0x40000000 0>,
421 <3 0 0x10000 0x50000000 0>,
422 <4 0 0x0 0x1d020000 0x10000>,
423 <5 0 0x0 0x1d040000 0x10000>,
424 <6 0 0x0 0x1d050000 0x10000>,
425 <7 0 0x10000 0x90000000 0>;
426
427 cavium,cs-config@0 {
428 compatible = "cavium,octeon-3860-bootbus-config";
429 cavium,cs-index = <0>;
430 cavium,t-adr = <20>;
431 cavium,t-ce = <60>;
432 cavium,t-oe = <60>;
433 cavium,t-we = <45>;
434 cavium,t-rd-hld = <35>;
435 cavium,t-wr-hld = <45>;
436 cavium,t-pause = <0>;
437 cavium,t-wait = <0>;
438 cavium,t-page = <35>;
439 cavium,t-rd-dly = <0>;
440
441 cavium,pages = <0>;
442 cavium,bus-width = <8>;
443 };
444 cavium,cs-config@4 {
445 compatible = "cavium,octeon-3860-bootbus-config";
446 cavium,cs-index = <4>;
447 cavium,t-adr = <320>;
448 cavium,t-ce = <320>;
449 cavium,t-oe = <320>;
450 cavium,t-we = <320>;
451 cavium,t-rd-hld = <320>;
452 cavium,t-wr-hld = <320>;
453 cavium,t-pause = <320>;
454 cavium,t-wait = <320>;
455 cavium,t-page = <320>;
456 cavium,t-rd-dly = <0>;
457
458 cavium,pages = <0>;
459 cavium,bus-width = <8>;
460 };
461 cavium,cs-config@5 {
462 compatible = "cavium,octeon-3860-bootbus-config";
463 cavium,cs-index = <5>;
464 cavium,t-adr = <5>;
465 cavium,t-ce = <300>;
466 cavium,t-oe = <125>;
467 cavium,t-we = <150>;
468 cavium,t-rd-hld = <100>;
469 cavium,t-wr-hld = <30>;
470 cavium,t-pause = <0>;
471 cavium,t-wait = <30>;
472 cavium,t-page = <320>;
473 cavium,t-rd-dly = <0>;
474
475 cavium,pages = <0>;
476 cavium,bus-width = <16>;
477 };
478 cavium,cs-config@6 {
479 compatible = "cavium,octeon-3860-bootbus-config";
480 cavium,cs-index = <6>;
481 cavium,t-adr = <5>;
482 cavium,t-ce = <300>;
483 cavium,t-oe = <270>;
484 cavium,t-we = <150>;
485 cavium,t-rd-hld = <100>;
486 cavium,t-wr-hld = <70>;
487 cavium,t-pause = <0>;
488 cavium,t-wait = <0>;
489 cavium,t-page = <320>;
490 cavium,t-rd-dly = <0>;
491
492 cavium,pages = <0>;
493 cavium,wait-mode;
494 cavium,bus-width = <16>;
495 };
496
497 flash0: nor@0,0 {
498 compatible = "cfi-flash";
499 reg = <0 0 0x800000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 };
503
504 led0: led-display@4,0 {
505 compatible = "avago,hdsp-253x";
506 reg = <4 0x20 0x20>, <4 0 0x20>;
507 };
508
509 cf0: compact-flash@5,0 {
510 compatible = "cavium,ebt3000-compact-flash";
511 reg = <5 0 0x10000>, <6 0 0x10000>;
512 cavium,bus-width = <16>;
513 cavium,true-ide;
514 cavium,dma-engine-handle = <&dma0>;
515 };
516 };
517
518 dma0: dma-engine@1180000000100 {
519 compatible = "cavium,octeon-5750-bootbus-dma";
520 reg = <0x11800 0x00000100 0x0 0x8>;
521 interrupts = <0 63>;
522 };
523 dma1: dma-engine@1180000000108 {
524 compatible = "cavium,octeon-5750-bootbus-dma";
525 reg = <0x11800 0x00000108 0x0 0x8>;
526 interrupts = <0 63>;
527 };
528
529 uctl: uctl@118006f000000 {
530 compatible = "cavium,octeon-6335-uctl";
531 reg = <0x11800 0x6f000000 0x0 0x100>;
532 ranges; /* Direct mapping */
533 #address-cells = <2>;
534 #size-cells = <2>;
535 /* 12MHz, 24MHz and 48MHz allowed */
536 refclk-frequency = <12000000>;
537 /* Either "crystal" or "external" */
538 refclk-type = "crystal";
539
540 ehci@16f0000000000 {
541 compatible = "cavium,octeon-6335-ehci","usb-ehci";
542 reg = <0x16f00 0x00000000 0x0 0x100>;
543 interrupts = <0 56>;
544 big-endian-regs;
545 };
546 ohci@16f0000000400 {
547 compatible = "cavium,octeon-6335-ohci","usb-ohci";
548 reg = <0x16f00 0x00000400 0x0 0x100>;
549 interrupts = <0 56>;
550 big-endian-regs;
551 };
552 };
553 };
554
555 aliases {
556 mix0 = &mix0;
557 mix1 = &mix1;
558 pip = &pip;
559 smi0 = &smi0;
560 smi1 = &smi1;
561 twsi0 = &twsi0;
562 twsi1 = &twsi1;
563 uart0 = &uart0;
564 uart1 = &uart1;
565 uart2 = &uart2;
566 flash0 = &flash0;
567 cf0 = &cf0;
568 uctl = &uctl;
569 led0 = &led0;
570 };
571 };
diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts
new file mode 100644
index 000000000000..1839468932b6
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_68xx.dts
@@ -0,0 +1,625 @@
1/dts-v1/;
2/*
3 * OCTEON 68XX device tree skeleton.
4 *
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
8 */
9/ {
10 compatible = "cavium,octeon-6880";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu2>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu2: interrupt-controller@1070100000000 {
22 compatible = "cavium,octeon-6880-ciu2";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 7)
26 * 2) Bit within the register (0..63)
27 */
28 #address-cells = <0>;
29 #interrupt-cells = <2>;
30 reg = <0x10701 0x00000000 0x0 0x4000000>;
31 };
32
33 gpio: gpio-controller@1070000000800 {
34 #gpio-cells = <2>;
35 compatible = "cavium,octeon-3860-gpio";
36 reg = <0x10700 0x00000800 0x0 0x100>;
37 gpio-controller;
38 /* Interrupts are specified by two parts:
39 * 1) GPIO pin number (0..15)
40 * 2) Triggering (1 - edge rising
41 * 2 - edge falling
42 * 4 - level active high
43 * 8 - level active low)
44 */
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 /* The GPIO pins connect to 16 consecutive CUI bits */
48 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
49 <7 4>, <7 5>, <7 6>, <7 7>,
50 <7 8>, <7 9>, <7 10>, <7 11>,
51 <7 12>, <7 13>, <7 14>, <7 15>;
52 };
53
54 smi0: mdio@1180000003800 {
55 compatible = "cavium,octeon-3860-mdio";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 reg = <0x11800 0x00003800 0x0 0x40>;
59
60 phy0: ethernet-phy@6 {
61 compatible = "marvell,88e1118";
62 marvell,reg-init =
63 /* Fix rx and tx clock transition timing */
64 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
65 /* Adjust LED drive. */
66 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
67 /* irq, blink-activity, blink-link */
68 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
69 reg = <6>;
70 };
71
72 phy1: ethernet-phy@1 {
73 cavium,qlm-trim = "4,sgmii";
74 reg = <1>;
75 compatible = "marvell,88e1149r";
76 marvell,reg-init = <3 0x10 0 0x5777>,
77 <3 0x11 0 0x00aa>,
78 <3 0x12 0 0x4105>,
79 <3 0x13 0 0x0a60>;
80 };
81 phy2: ethernet-phy@2 {
82 cavium,qlm-trim = "4,sgmii";
83 reg = <2>;
84 compatible = "marvell,88e1149r";
85 marvell,reg-init = <3 0x10 0 0x5777>,
86 <3 0x11 0 0x00aa>,
87 <3 0x12 0 0x4105>,
88 <3 0x13 0 0x0a60>;
89 };
90 phy3: ethernet-phy@3 {
91 cavium,qlm-trim = "4,sgmii";
92 reg = <3>;
93 compatible = "marvell,88e1149r";
94 marvell,reg-init = <3 0x10 0 0x5777>,
95 <3 0x11 0 0x00aa>,
96 <3 0x12 0 0x4105>,
97 <3 0x13 0 0x0a60>;
98 };
99 phy4: ethernet-phy@4 {
100 cavium,qlm-trim = "4,sgmii";
101 reg = <4>;
102 compatible = "marvell,88e1149r";
103 marvell,reg-init = <3 0x10 0 0x5777>,
104 <3 0x11 0 0x00aa>,
105 <3 0x12 0 0x4105>,
106 <3 0x13 0 0x0a60>;
107 };
108 };
109
110 smi1: mdio@1180000003880 {
111 compatible = "cavium,octeon-3860-mdio";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x11800 0x00003880 0x0 0x40>;
115
116 phy41: ethernet-phy@1 {
117 cavium,qlm-trim = "0,sgmii";
118 reg = <1>;
119 compatible = "marvell,88e1149r";
120 marvell,reg-init = <3 0x10 0 0x5777>,
121 <3 0x11 0 0x00aa>,
122 <3 0x12 0 0x4105>,
123 <3 0x13 0 0x0a60>;
124 };
125 phy42: ethernet-phy@2 {
126 cavium,qlm-trim = "0,sgmii";
127 reg = <2>;
128 compatible = "marvell,88e1149r";
129 marvell,reg-init = <3 0x10 0 0x5777>,
130 <3 0x11 0 0x00aa>,
131 <3 0x12 0 0x4105>,
132 <3 0x13 0 0x0a60>;
133 };
134 phy43: ethernet-phy@3 {
135 cavium,qlm-trim = "0,sgmii";
136 reg = <3>;
137 compatible = "marvell,88e1149r";
138 marvell,reg-init = <3 0x10 0 0x5777>,
139 <3 0x11 0 0x00aa>,
140 <3 0x12 0 0x4105>,
141 <3 0x13 0 0x0a60>;
142 };
143 phy44: ethernet-phy@4 {
144 cavium,qlm-trim = "0,sgmii";
145 reg = <4>;
146 compatible = "marvell,88e1149r";
147 marvell,reg-init = <3 0x10 0 0x5777>,
148 <3 0x11 0 0x00aa>,
149 <3 0x12 0 0x4105>,
150 <3 0x13 0 0x0a60>;
151 };
152 };
153
154 smi2: mdio@1180000003900 {
155 compatible = "cavium,octeon-3860-mdio";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0x11800 0x00003900 0x0 0x40>;
159
160 phy21: ethernet-phy@1 {
161 cavium,qlm-trim = "2,sgmii";
162 reg = <1>;
163 compatible = "marvell,88e1149r";
164 marvell,reg-init = <3 0x10 0 0x5777>,
165 <3 0x11 0 0x00aa>,
166 <3 0x12 0 0x4105>,
167 <3 0x13 0 0x0a60>;
168 };
169 phy22: ethernet-phy@2 {
170 cavium,qlm-trim = "2,sgmii";
171 reg = <2>;
172 compatible = "marvell,88e1149r";
173 marvell,reg-init = <3 0x10 0 0x5777>,
174 <3 0x11 0 0x00aa>,
175 <3 0x12 0 0x4105>,
176 <3 0x13 0 0x0a60>;
177 };
178 phy23: ethernet-phy@3 {
179 cavium,qlm-trim = "2,sgmii";
180 reg = <3>;
181 compatible = "marvell,88e1149r";
182 marvell,reg-init = <3 0x10 0 0x5777>,
183 <3 0x11 0 0x00aa>,
184 <3 0x12 0 0x4105>,
185 <3 0x13 0 0x0a60>;
186 };
187 phy24: ethernet-phy@4 {
188 cavium,qlm-trim = "2,sgmii";
189 reg = <4>;
190 compatible = "marvell,88e1149r";
191 marvell,reg-init = <3 0x10 0 0x5777>,
192 <3 0x11 0 0x00aa>,
193 <3 0x12 0 0x4105>,
194 <3 0x13 0 0x0a60>;
195 };
196 };
197
198 smi3: mdio@1180000003980 {
199 compatible = "cavium,octeon-3860-mdio";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x11800 0x00003980 0x0 0x40>;
203
204 phy11: ethernet-phy@1 {
205 cavium,qlm-trim = "3,sgmii";
206 reg = <1>;
207 compatible = "marvell,88e1149r";
208 marvell,reg-init = <3 0x10 0 0x5777>,
209 <3 0x11 0 0x00aa>,
210 <3 0x12 0 0x4105>,
211 <3 0x13 0 0x0a60>;
212 };
213 phy12: ethernet-phy@2 {
214 cavium,qlm-trim = "3,sgmii";
215 reg = <2>;
216 compatible = "marvell,88e1149r";
217 marvell,reg-init = <3 0x10 0 0x5777>,
218 <3 0x11 0 0x00aa>,
219 <3 0x12 0 0x4105>,
220 <3 0x13 0 0x0a60>;
221 };
222 phy13: ethernet-phy@3 {
223 cavium,qlm-trim = "3,sgmii";
224 reg = <3>;
225 compatible = "marvell,88e1149r";
226 marvell,reg-init = <3 0x10 0 0x5777>,
227 <3 0x11 0 0x00aa>,
228 <3 0x12 0 0x4105>,
229 <3 0x13 0 0x0a60>;
230 };
231 phy14: ethernet-phy@4 {
232 cavium,qlm-trim = "3,sgmii";
233 reg = <4>;
234 compatible = "marvell,88e1149r";
235 marvell,reg-init = <3 0x10 0 0x5777>,
236 <3 0x11 0 0x00aa>,
237 <3 0x12 0 0x4105>,
238 <3 0x13 0 0x0a60>;
239 };
240 };
241
242 mix0: ethernet@1070000100000 {
243 compatible = "cavium,octeon-5750-mix";
244 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
245 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
246 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
247 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
248 cell-index = <0>;
249 interrupts = <6 40>, <6 32>;
250 local-mac-address = [ 00 00 00 00 00 00 ];
251 phy-handle = <&phy0>;
252 };
253
254 pip: pip@11800a0000000 {
255 compatible = "cavium,octeon-3860-pip";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0x11800 0xa0000000 0x0 0x2000>;
259
260 interface@4 {
261 compatible = "cavium,octeon-3860-pip-interface";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 reg = <0x4>; /* interface */
265
266 ethernet@0 {
267 compatible = "cavium,octeon-3860-pip-port";
268 reg = <0x0>; /* Port */
269 local-mac-address = [ 00 00 00 00 00 00 ];
270 phy-handle = <&phy1>;
271 };
272 ethernet@1 {
273 compatible = "cavium,octeon-3860-pip-port";
274 reg = <0x1>; /* Port */
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 phy-handle = <&phy2>;
277 };
278 ethernet@2 {
279 compatible = "cavium,octeon-3860-pip-port";
280 reg = <0x2>; /* Port */
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 phy-handle = <&phy3>;
283 };
284 ethernet@3 {
285 compatible = "cavium,octeon-3860-pip-port";
286 reg = <0x3>; /* Port */
287 local-mac-address = [ 00 00 00 00 00 00 ];
288 phy-handle = <&phy4>;
289 };
290 };
291
292 interface@3 {
293 compatible = "cavium,octeon-3860-pip-interface";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <0x3>; /* interface */
297
298 ethernet@0 {
299 compatible = "cavium,octeon-3860-pip-port";
300 reg = <0x0>; /* Port */
301 local-mac-address = [ 00 00 00 00 00 00 ];
302 phy-handle = <&phy11>;
303 };
304 ethernet@1 {
305 compatible = "cavium,octeon-3860-pip-port";
306 reg = <0x1>; /* Port */
307 local-mac-address = [ 00 00 00 00 00 00 ];
308 phy-handle = <&phy12>;
309 };
310 ethernet@2 {
311 compatible = "cavium,octeon-3860-pip-port";
312 reg = <0x2>; /* Port */
313 local-mac-address = [ 00 00 00 00 00 00 ];
314 phy-handle = <&phy13>;
315 };
316 ethernet@3 {
317 compatible = "cavium,octeon-3860-pip-port";
318 reg = <0x3>; /* Port */
319 local-mac-address = [ 00 00 00 00 00 00 ];
320 phy-handle = <&phy14>;
321 };
322 };
323
324 interface@2 {
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0x2>; /* interface */
329
330 ethernet@0 {
331 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 phy-handle = <&phy21>;
335 };
336 ethernet@1 {
337 compatible = "cavium,octeon-3860-pip-port";
338 reg = <0x1>; /* Port */
339 local-mac-address = [ 00 00 00 00 00 00 ];
340 phy-handle = <&phy22>;
341 };
342 ethernet@2 {
343 compatible = "cavium,octeon-3860-pip-port";
344 reg = <0x2>; /* Port */
345 local-mac-address = [ 00 00 00 00 00 00 ];
346 phy-handle = <&phy23>;
347 };
348 ethernet@3 {
349 compatible = "cavium,octeon-3860-pip-port";
350 reg = <0x3>; /* Port */
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 phy-handle = <&phy24>;
353 };
354 };
355
356 interface@1 {
357 compatible = "cavium,octeon-3860-pip-interface";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <0x1>; /* interface */
361
362 ethernet@0 {
363 compatible = "cavium,octeon-3860-pip-port";
364 reg = <0x0>; /* Port */
365 local-mac-address = [ 00 00 00 00 00 00 ];
366 };
367 };
368
369 interface@0 {
370 compatible = "cavium,octeon-3860-pip-interface";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x0>; /* interface */
374
375 ethernet@0 {
376 compatible = "cavium,octeon-3860-pip-port";
377 reg = <0x0>; /* Port */
378 local-mac-address = [ 00 00 00 00 00 00 ];
379 phy-handle = <&phy41>;
380 };
381 ethernet@1 {
382 compatible = "cavium,octeon-3860-pip-port";
383 reg = <0x1>; /* Port */
384 local-mac-address = [ 00 00 00 00 00 00 ];
385 phy-handle = <&phy42>;
386 };
387 ethernet@2 {
388 compatible = "cavium,octeon-3860-pip-port";
389 reg = <0x2>; /* Port */
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 phy-handle = <&phy43>;
392 };
393 ethernet@3 {
394 compatible = "cavium,octeon-3860-pip-port";
395 reg = <0x3>; /* Port */
396 local-mac-address = [ 00 00 00 00 00 00 ];
397 phy-handle = <&phy44>;
398 };
399 };
400 };
401
402 twsi0: i2c@1180000001000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "cavium,octeon-3860-twsi";
406 reg = <0x11800 0x00001000 0x0 0x200>;
407 interrupts = <3 32>;
408 clock-frequency = <100000>;
409
410 rtc@68 {
411 compatible = "dallas,ds1337";
412 reg = <0x68>;
413 };
414 tmp@4c {
415 compatible = "ti,tmp421";
416 reg = <0x4c>;
417 };
418 };
419
420 twsi1: i2c@1180000001200 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "cavium,octeon-3860-twsi";
424 reg = <0x11800 0x00001200 0x0 0x200>;
425 interrupts = <3 33>;
426 clock-frequency = <100000>;
427 };
428
429 uart0: serial@1180000000800 {
430 compatible = "cavium,octeon-3860-uart","ns16550";
431 reg = <0x11800 0x00000800 0x0 0x400>;
432 clock-frequency = <0>;
433 current-speed = <115200>;
434 reg-shift = <3>;
435 interrupts = <3 36>;
436 };
437
438 uart1: serial@1180000000c00 {
439 compatible = "cavium,octeon-3860-uart","ns16550";
440 reg = <0x11800 0x00000c00 0x0 0x400>;
441 clock-frequency = <0>;
442 current-speed = <115200>;
443 reg-shift = <3>;
444 interrupts = <3 37>;
445 };
446
447 bootbus: bootbus@1180000000000 {
448 compatible = "cavium,octeon-3860-bootbus";
449 reg = <0x11800 0x00000000 0x0 0x200>;
450 /* The chip select number and offset */
451 #address-cells = <2>;
452 /* The size of the chip select region */
453 #size-cells = <1>;
454 ranges = <0 0 0 0x1f400000 0xc00000>,
455 <1 0 0x10000 0x30000000 0>,
456 <2 0 0x10000 0x40000000 0>,
457 <3 0 0x10000 0x50000000 0>,
458 <4 0 0 0x1d020000 0x10000>,
459 <5 0 0 0x1d040000 0x10000>,
460 <6 0 0 0x1d050000 0x10000>,
461 <7 0 0x10000 0x90000000 0>;
462
463 cavium,cs-config@0 {
464 compatible = "cavium,octeon-3860-bootbus-config";
465 cavium,cs-index = <0>;
466 cavium,t-adr = <10>;
467 cavium,t-ce = <50>;
468 cavium,t-oe = <50>;
469 cavium,t-we = <35>;
470 cavium,t-rd-hld = <25>;
471 cavium,t-wr-hld = <35>;
472 cavium,t-pause = <0>;
473 cavium,t-wait = <300>;
474 cavium,t-page = <25>;
475 cavium,t-rd-dly = <0>;
476
477 cavium,pages = <0>;
478 cavium,bus-width = <8>;
479 };
480 cavium,cs-config@4 {
481 compatible = "cavium,octeon-3860-bootbus-config";
482 cavium,cs-index = <4>;
483 cavium,t-adr = <320>;
484 cavium,t-ce = <320>;
485 cavium,t-oe = <320>;
486 cavium,t-we = <320>;
487 cavium,t-rd-hld = <320>;
488 cavium,t-wr-hld = <320>;
489 cavium,t-pause = <320>;
490 cavium,t-wait = <320>;
491 cavium,t-page = <320>;
492 cavium,t-rd-dly = <0>;
493
494 cavium,pages = <0>;
495 cavium,bus-width = <8>;
496 };
497 cavium,cs-config@5 {
498 compatible = "cavium,octeon-3860-bootbus-config";
499 cavium,cs-index = <5>;
500 cavium,t-adr = <0>;
501 cavium,t-ce = <300>;
502 cavium,t-oe = <125>;
503 cavium,t-we = <150>;
504 cavium,t-rd-hld = <100>;
505 cavium,t-wr-hld = <300>;
506 cavium,t-pause = <0>;
507 cavium,t-wait = <300>;
508 cavium,t-page = <310>;
509 cavium,t-rd-dly = <0>;
510
511 cavium,pages = <0>;
512 cavium,bus-width = <16>;
513 };
514 cavium,cs-config@6 {
515 compatible = "cavium,octeon-3860-bootbus-config";
516 cavium,cs-index = <6>;
517 cavium,t-adr = <0>;
518 cavium,t-ce = <30>;
519 cavium,t-oe = <125>;
520 cavium,t-we = <150>;
521 cavium,t-rd-hld = <100>;
522 cavium,t-wr-hld = <30>;
523 cavium,t-pause = <0>;
524 cavium,t-wait = <30>;
525 cavium,t-page = <310>;
526 cavium,t-rd-dly = <0>;
527
528 cavium,pages = <0>;
529 cavium,wait-mode;
530 cavium,bus-width = <16>;
531 };
532
533 flash0: nor@0,0 {
534 compatible = "cfi-flash";
535 reg = <0 0 0x800000>;
536 #address-cells = <1>;
537 #size-cells = <1>;
538
539 partition@0 {
540 label = "bootloader";
541 reg = <0 0x200000>;
542 read-only;
543 };
544 partition@200000 {
545 label = "kernel";
546 reg = <0x200000 0x200000>;
547 };
548 partition@400000 {
549 label = "cramfs";
550 reg = <0x400000 0x3fe000>;
551 };
552 partition@7fe000 {
553 label = "environment";
554 reg = <0x7fe000 0x2000>;
555 read-only;
556 };
557 };
558
559 led0: led-display@4,0 {
560 compatible = "avago,hdsp-253x";
561 reg = <4 0x20 0x20>, <4 0 0x20>;
562 };
563
564 compact-flash@5,0 {
565 compatible = "cavium,ebt3000-compact-flash";
566 reg = <5 0 0x10000>, <6 0 0x10000>;
567 cavium,bus-width = <16>;
568 cavium,true-ide;
569 cavium,dma-engine-handle = <&dma0>;
570 };
571 };
572
573 dma0: dma-engine@1180000000100 {
574 compatible = "cavium,octeon-5750-bootbus-dma";
575 reg = <0x11800 0x00000100 0x0 0x8>;
576 interrupts = <0 63>;
577 };
578 dma1: dma-engine@1180000000108 {
579 compatible = "cavium,octeon-5750-bootbus-dma";
580 reg = <0x11800 0x00000108 0x0 0x8>;
581 interrupts = <0 63>;
582 };
583
584 uctl: uctl@118006f000000 {
585 compatible = "cavium,octeon-6335-uctl";
586 reg = <0x11800 0x6f000000 0x0 0x100>;
587 ranges; /* Direct mapping */
588 #address-cells = <2>;
589 #size-cells = <2>;
590 /* 12MHz, 24MHz and 48MHz allowed */
591 refclk-frequency = <12000000>;
592 /* Either "crystal" or "external" */
593 refclk-type = "crystal";
594
595 ehci@16f0000000000 {
596 compatible = "cavium,octeon-6335-ehci","usb-ehci";
597 reg = <0x16f00 0x00000000 0x0 0x100>;
598 interrupts = <3 44>;
599 big-endian-regs;
600 };
601 ohci@16f0000000400 {
602 compatible = "cavium,octeon-6335-ohci","usb-ohci";
603 reg = <0x16f00 0x00000400 0x0 0x100>;
604 interrupts = <3 44>;
605 big-endian-regs;
606 };
607 };
608 };
609
610 aliases {
611 mix0 = &mix0;
612 pip = &pip;
613 smi0 = &smi0;
614 smi1 = &smi1;
615 smi2 = &smi2;
616 smi3 = &smi3;
617 twsi0 = &twsi0;
618 twsi1 = &twsi1;
619 uart0 = &uart0;
620 uart1 = &uart1;
621 uctl = &uctl;
622 led0 = &led0;
623 flash0 = &flash0;
624 };
625 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 04:48:26 -0500