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authorUlrich Hecht <ulrich.hecht@gmail.com>2013-05-31 11:57:02 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-11 02:30:30 -0400
commit729cb826d45cc2e58bb0256b66f1a8e42173bf54 (patch)
tree42557a45828337376dc8dce726e5d7cd8bc85cd9 /arch
parentc02f846938fe64800240e97cb113a2bff0149c92 (diff)
ARM: shmobile: r8a7790: HSCIF support
Adds support for HSCIF0 and HSCIF1 on the r8a7790. Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index b393592edc83..379bce698a29 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -181,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = {
181/* MSTP */ 181/* MSTP */
182enum { 182enum {
183 MSTP721, MSTP720, 183 MSTP721, MSTP720,
184 MSTP717, MSTP716,
184 MSTP304, 185 MSTP304,
185 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 186 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
186 MSTP_NR 187 MSTP_NR
@@ -196,6 +197,8 @@ static struct clk mstp_clks[MSTP_NR] = {
196 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 197 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
197 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 198 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
198 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ 199 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
200 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
201 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
199}; 202};
200 203
201static struct clk_lookup lookups[] = { 204static struct clk_lookup lookups[] = {
@@ -249,6 +252,8 @@ static struct clk_lookup lookups[] = {
249 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), 252 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
250 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), 253 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
251 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), 254 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
255 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
256 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
252}; 257};
253 258
254#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 259#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \