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authorThomas Abraham <thomas.abraham@linaro.org>2013-03-09 03:03:05 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-03-25 05:17:12 -0400
commit6e6aac7590f902d14d90bace3fd4990d57b4979d (patch)
treed07a40dfd3ed44c010861ac924bd58674e91fd9a /arch
parentf2585b1cce24d7bc5b4a1de582bf81e43813f840 (diff)
ARM: EXYNOS: Migrate clock support to common clock framework
Remove Samsung specific clock support in Exynos4/5 and migrate to use common clock framework. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-exynos/Makefile4
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1601
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h35
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c187
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c201
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1645
-rw-r--r--arch/arm/mach-exynos/common.c41
-rw-r--r--arch/arm/mach-exynos/common.h7
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h107
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c1
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c1
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c5
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c1
-rw-r--r--arch/arm/mach-exynos/mach-origen.c1
-rw-r--r--arch/arm/mach-exynos/mach-smdk4x12.c1
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c1
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c1
-rw-r--r--arch/arm/plat-samsung/Kconfig4
19 files changed, 10 insertions, 3835 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee414be31b4d..e232412d14a5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -865,6 +865,7 @@ config ARCH_EXYNOS
865 select ARCH_HAS_HOLES_MEMORYMODEL 865 select ARCH_HAS_HOLES_MEMORYMODEL
866 select ARCH_SPARSEMEM_ENABLE 866 select ARCH_SPARSEMEM_ENABLE
867 select CLKDEV_LOOKUP 867 select CLKDEV_LOOKUP
868 select COMMON_CLK
868 select CPU_V7 869 select CPU_V7
869 select GENERIC_CLOCKEVENTS 870 select GENERIC_CLOCKEVENTS
870 select HAVE_CLK 871 select HAVE_CLK
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index daf289b21486..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj- :=
13# Core 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS) += common.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
20 16
21obj-$(CONFIG_PM) += pm.o 17obj-$(CONFIG_PM) += pm.o
22obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 18obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27
28#include "common.h"
29#include "clock-exynos4.h"
30
31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
34 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
39 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
40 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
41 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
42 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
43 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
44 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
45 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
46 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
48 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
49 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
50 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
51 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
52 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
53 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
64 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
65 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
74 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
75 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
83 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
84 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
85 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
86 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
88 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
89 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
90 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
93 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
94};
95#endif
96
97static struct clk exynos4_clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m",
99 .rate = 27000000,
100};
101
102static struct clk exynos4_clk_sclk_hdmiphy = {
103 .name = "sclk_hdmiphy",
104};
105
106static struct clk exynos4_clk_sclk_usbphy0 = {
107 .name = "sclk_usbphy0",
108 .rate = 27000000,
109};
110
111static struct clk exynos4_clk_sclk_usbphy1 = {
112 .name = "sclk_usbphy1",
113};
114
115static struct clk dummy_apb_pclk = {
116 .name = "apb_pclk",
117 .id = -1,
118};
119
120static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
123}
124
125static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
128}
129
130static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
133}
134
135int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
138}
139
140static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
143}
144
145static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
148}
149
150static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
153}
154
155static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
158}
159
160static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
163}
164
165static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
168}
169
170int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
173}
174
175static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
178}
179
180int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
183}
184
185int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
188}
189
190static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
193}
194
195static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
198}
199
200int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
203}
204
205static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
206{
207 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
208}
209
210static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
211{
212 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
213}
214
215/* Core list of CMU_CPU side */
216
217static struct clksrc_clk exynos4_clk_mout_apll = {
218 .clk = {
219 .name = "mout_apll",
220 },
221 .sources = &clk_src_apll,
222 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
223};
224
225static struct clksrc_clk exynos4_clk_sclk_apll = {
226 .clk = {
227 .name = "sclk_apll",
228 .parent = &exynos4_clk_mout_apll.clk,
229 },
230 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
231};
232
233static struct clksrc_clk exynos4_clk_mout_epll = {
234 .clk = {
235 .name = "mout_epll",
236 },
237 .sources = &clk_src_epll,
238 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
239};
240
241struct clksrc_clk exynos4_clk_mout_mpll = {
242 .clk = {
243 .name = "mout_mpll",
244 },
245 .sources = &clk_src_mpll,
246
247 /* reg_src will be added in each SoCs' clock */
248};
249
250static struct clk *exynos4_clkset_moutcore_list[] = {
251 [0] = &exynos4_clk_mout_apll.clk,
252 [1] = &exynos4_clk_mout_mpll.clk,
253};
254
255static struct clksrc_sources exynos4_clkset_moutcore = {
256 .sources = exynos4_clkset_moutcore_list,
257 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
258};
259
260static struct clksrc_clk exynos4_clk_moutcore = {
261 .clk = {
262 .name = "moutcore",
263 },
264 .sources = &exynos4_clkset_moutcore,
265 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
266};
267
268static struct clksrc_clk exynos4_clk_coreclk = {
269 .clk = {
270 .name = "core_clk",
271 .parent = &exynos4_clk_moutcore.clk,
272 },
273 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
274};
275
276static struct clksrc_clk exynos4_clk_armclk = {
277 .clk = {
278 .name = "armclk",
279 .parent = &exynos4_clk_coreclk.clk,
280 },
281};
282
283static struct clksrc_clk exynos4_clk_aclk_corem0 = {
284 .clk = {
285 .name = "aclk_corem0",
286 .parent = &exynos4_clk_coreclk.clk,
287 },
288 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
289};
290
291static struct clksrc_clk exynos4_clk_aclk_cores = {
292 .clk = {
293 .name = "aclk_cores",
294 .parent = &exynos4_clk_coreclk.clk,
295 },
296 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
297};
298
299static struct clksrc_clk exynos4_clk_aclk_corem1 = {
300 .clk = {
301 .name = "aclk_corem1",
302 .parent = &exynos4_clk_coreclk.clk,
303 },
304 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
305};
306
307static struct clksrc_clk exynos4_clk_periphclk = {
308 .clk = {
309 .name = "periphclk",
310 .parent = &exynos4_clk_coreclk.clk,
311 },
312 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
313};
314
315/* Core list of CMU_CORE side */
316
317static struct clk *exynos4_clkset_corebus_list[] = {
318 [0] = &exynos4_clk_mout_mpll.clk,
319 [1] = &exynos4_clk_sclk_apll.clk,
320};
321
322struct clksrc_sources exynos4_clkset_mout_corebus = {
323 .sources = exynos4_clkset_corebus_list,
324 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
325};
326
327static struct clksrc_clk exynos4_clk_mout_corebus = {
328 .clk = {
329 .name = "mout_corebus",
330 },
331 .sources = &exynos4_clkset_mout_corebus,
332 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
333};
334
335static struct clksrc_clk exynos4_clk_sclk_dmc = {
336 .clk = {
337 .name = "sclk_dmc",
338 .parent = &exynos4_clk_mout_corebus.clk,
339 },
340 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
341};
342
343static struct clksrc_clk exynos4_clk_aclk_cored = {
344 .clk = {
345 .name = "aclk_cored",
346 .parent = &exynos4_clk_sclk_dmc.clk,
347 },
348 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
349};
350
351static struct clksrc_clk exynos4_clk_aclk_corep = {
352 .clk = {
353 .name = "aclk_corep",
354 .parent = &exynos4_clk_aclk_cored.clk,
355 },
356 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
357};
358
359static struct clksrc_clk exynos4_clk_aclk_acp = {
360 .clk = {
361 .name = "aclk_acp",
362 .parent = &exynos4_clk_mout_corebus.clk,
363 },
364 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
365};
366
367static struct clksrc_clk exynos4_clk_pclk_acp = {
368 .clk = {
369 .name = "pclk_acp",
370 .parent = &exynos4_clk_aclk_acp.clk,
371 },
372 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
373};
374
375/* Core list of CMU_TOP side */
376
377struct clk *exynos4_clkset_aclk_top_list[] = {
378 [0] = &exynos4_clk_mout_mpll.clk,
379 [1] = &exynos4_clk_sclk_apll.clk,
380};
381
382static struct clksrc_sources exynos4_clkset_aclk = {
383 .sources = exynos4_clkset_aclk_top_list,
384 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
385};
386
387static struct clksrc_clk exynos4_clk_aclk_200 = {
388 .clk = {
389 .name = "aclk_200",
390 },
391 .sources = &exynos4_clkset_aclk,
392 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
393 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
394};
395
396static struct clksrc_clk exynos4_clk_aclk_100 = {
397 .clk = {
398 .name = "aclk_100",
399 },
400 .sources = &exynos4_clkset_aclk,
401 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
402 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
403};
404
405static struct clksrc_clk exynos4_clk_aclk_160 = {
406 .clk = {
407 .name = "aclk_160",
408 },
409 .sources = &exynos4_clkset_aclk,
410 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
411 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
412};
413
414struct clksrc_clk exynos4_clk_aclk_133 = {
415 .clk = {
416 .name = "aclk_133",
417 },
418 .sources = &exynos4_clkset_aclk,
419 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
420 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
421};
422
423static struct clk *exynos4_clkset_vpllsrc_list[] = {
424 [0] = &clk_fin_vpll,
425 [1] = &exynos4_clk_sclk_hdmi27m,
426};
427
428static struct clksrc_sources exynos4_clkset_vpllsrc = {
429 .sources = exynos4_clkset_vpllsrc_list,
430 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
431};
432
433static struct clksrc_clk exynos4_clk_vpllsrc = {
434 .clk = {
435 .name = "vpll_src",
436 .enable = exynos4_clksrc_mask_top_ctrl,
437 .ctrlbit = (1 << 0),
438 },
439 .sources = &exynos4_clkset_vpllsrc,
440 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
441};
442
443static struct clk *exynos4_clkset_sclk_vpll_list[] = {
444 [0] = &exynos4_clk_vpllsrc.clk,
445 [1] = &clk_fout_vpll,
446};
447
448static struct clksrc_sources exynos4_clkset_sclk_vpll = {
449 .sources = exynos4_clkset_sclk_vpll_list,
450 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
451};
452
453static struct clksrc_clk exynos4_clk_sclk_vpll = {
454 .clk = {
455 .name = "sclk_vpll",
456 },
457 .sources = &exynos4_clkset_sclk_vpll,
458 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
459};
460
461static struct clk exynos4_init_clocks_off[] = {
462 {
463 .name = "timers",
464 .parent = &exynos4_clk_aclk_100.clk,
465 .enable = exynos4_clk_ip_peril_ctrl,
466 .ctrlbit = (1<<24),
467 }, {
468 .name = "csis",
469 .devname = "s5p-mipi-csis.0",
470 .enable = exynos4_clk_ip_cam_ctrl,
471 .ctrlbit = (1 << 4),
472 }, {
473 .name = "csis",
474 .devname = "s5p-mipi-csis.1",
475 .enable = exynos4_clk_ip_cam_ctrl,
476 .ctrlbit = (1 << 5),
477 }, {
478 .name = "jpeg",
479 .id = 0,
480 .enable = exynos4_clk_ip_cam_ctrl,
481 .ctrlbit = (1 << 6),
482 }, {
483 .name = "fimc",
484 .devname = "exynos4-fimc.0",
485 .enable = exynos4_clk_ip_cam_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "fimc",
489 .devname = "exynos4-fimc.1",
490 .enable = exynos4_clk_ip_cam_ctrl,
491 .ctrlbit = (1 << 1),
492 }, {
493 .name = "fimc",
494 .devname = "exynos4-fimc.2",
495 .enable = exynos4_clk_ip_cam_ctrl,
496 .ctrlbit = (1 << 2),
497 }, {
498 .name = "fimc",
499 .devname = "exynos4-fimc.3",
500 .enable = exynos4_clk_ip_cam_ctrl,
501 .ctrlbit = (1 << 3),
502 }, {
503 .name = "tsi",
504 .enable = exynos4_clk_ip_fsys_ctrl,
505 .ctrlbit = (1 << 4),
506 }, {
507 .name = "hsmmc",
508 .devname = "exynos4-sdhci.0",
509 .parent = &exynos4_clk_aclk_133.clk,
510 .enable = exynos4_clk_ip_fsys_ctrl,
511 .ctrlbit = (1 << 5),
512 }, {
513 .name = "hsmmc",
514 .devname = "exynos4-sdhci.1",
515 .parent = &exynos4_clk_aclk_133.clk,
516 .enable = exynos4_clk_ip_fsys_ctrl,
517 .ctrlbit = (1 << 6),
518 }, {
519 .name = "hsmmc",
520 .devname = "exynos4-sdhci.2",
521 .parent = &exynos4_clk_aclk_133.clk,
522 .enable = exynos4_clk_ip_fsys_ctrl,
523 .ctrlbit = (1 << 7),
524 }, {
525 .name = "hsmmc",
526 .devname = "exynos4-sdhci.3",
527 .parent = &exynos4_clk_aclk_133.clk,
528 .enable = exynos4_clk_ip_fsys_ctrl,
529 .ctrlbit = (1 << 8),
530 }, {
531 .name = "biu",
532 .parent = &exynos4_clk_aclk_133.clk,
533 .enable = exynos4_clk_ip_fsys_ctrl,
534 .ctrlbit = (1 << 9),
535 }, {
536 .name = "onenand",
537 .enable = exynos4_clk_ip_fsys_ctrl,
538 .ctrlbit = (1 << 15),
539 }, {
540 .name = "nfcon",
541 .enable = exynos4_clk_ip_fsys_ctrl,
542 .ctrlbit = (1 << 16),
543 }, {
544 .name = "dac",
545 .devname = "s5p-sdo",
546 .enable = exynos4_clk_ip_tv_ctrl,
547 .ctrlbit = (1 << 2),
548 }, {
549 .name = "mixer",
550 .devname = "s5p-mixer",
551 .enable = exynos4_clk_ip_tv_ctrl,
552 .ctrlbit = (1 << 1),
553 }, {
554 .name = "vp",
555 .devname = "s5p-mixer",
556 .enable = exynos4_clk_ip_tv_ctrl,
557 .ctrlbit = (1 << 0),
558 }, {
559 .name = "hdmi",
560 .devname = "exynos4-hdmi",
561 .enable = exynos4_clk_ip_tv_ctrl,
562 .ctrlbit = (1 << 3),
563 }, {
564 .name = "hdmiphy",
565 .devname = "exynos4-hdmi",
566 .enable = exynos4_clk_hdmiphy_ctrl,
567 .ctrlbit = (1 << 0),
568 }, {
569 .name = "dacphy",
570 .devname = "s5p-sdo",
571 .enable = exynos4_clk_dac_ctrl,
572 .ctrlbit = (1 << 0),
573 }, {
574 .name = "adc",
575 .enable = exynos4_clk_ip_peril_ctrl,
576 .ctrlbit = (1 << 15),
577 }, {
578 .name = "tmu_apbif",
579 .enable = exynos4_clk_ip_perir_ctrl,
580 .ctrlbit = (1 << 17),
581 }, {
582 .name = "keypad",
583 .enable = exynos4_clk_ip_perir_ctrl,
584 .ctrlbit = (1 << 16),
585 }, {
586 .name = "rtc",
587 .enable = exynos4_clk_ip_perir_ctrl,
588 .ctrlbit = (1 << 15),
589 }, {
590 .name = "watchdog",
591 .parent = &exynos4_clk_aclk_100.clk,
592 .enable = exynos4_clk_ip_perir_ctrl,
593 .ctrlbit = (1 << 14),
594 }, {
595 .name = "usbhost",
596 .enable = exynos4_clk_ip_fsys_ctrl ,
597 .ctrlbit = (1 << 12),
598 }, {
599 .name = "otg",
600 .enable = exynos4_clk_ip_fsys_ctrl,
601 .ctrlbit = (1 << 13),
602 }, {
603 .name = "spi",
604 .devname = "exynos4210-spi.0",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 16),
607 }, {
608 .name = "spi",
609 .devname = "exynos4210-spi.1",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 17),
612 }, {
613 .name = "spi",
614 .devname = "exynos4210-spi.2",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 18),
617 }, {
618 .name = "iis",
619 .devname = "samsung-i2s.1",
620 .enable = exynos4_clk_ip_peril_ctrl,
621 .ctrlbit = (1 << 20),
622 }, {
623 .name = "iis",
624 .devname = "samsung-i2s.2",
625 .enable = exynos4_clk_ip_peril_ctrl,
626 .ctrlbit = (1 << 21),
627 }, {
628 .name = "pcm",
629 .devname = "samsung-pcm.1",
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 22),
632 }, {
633 .name = "pcm",
634 .devname = "samsung-pcm.2",
635 .enable = exynos4_clk_ip_peril_ctrl,
636 .ctrlbit = (1 << 23),
637 }, {
638 .name = "slimbus",
639 .enable = exynos4_clk_ip_peril_ctrl,
640 .ctrlbit = (1 << 25),
641 }, {
642 .name = "spdif",
643 .devname = "samsung-spdif",
644 .enable = exynos4_clk_ip_peril_ctrl,
645 .ctrlbit = (1 << 26),
646 }, {
647 .name = "ac97",
648 .devname = "samsung-ac97",
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 27),
651 }, {
652 .name = "mfc",
653 .devname = "s5p-mfc",
654 .enable = exynos4_clk_ip_mfc_ctrl,
655 .ctrlbit = (1 << 0),
656 }, {
657 .name = "i2c",
658 .devname = "s3c2440-i2c.0",
659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 6),
662 }, {
663 .name = "i2c",
664 .devname = "s3c2440-i2c.1",
665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 7),
668 }, {
669 .name = "i2c",
670 .devname = "s3c2440-i2c.2",
671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 8),
674 }, {
675 .name = "i2c",
676 .devname = "s3c2440-i2c.3",
677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 9),
680 }, {
681 .name = "i2c",
682 .devname = "s3c2440-i2c.4",
683 .parent = &exynos4_clk_aclk_100.clk,
684 .enable = exynos4_clk_ip_peril_ctrl,
685 .ctrlbit = (1 << 10),
686 }, {
687 .name = "i2c",
688 .devname = "s3c2440-i2c.5",
689 .parent = &exynos4_clk_aclk_100.clk,
690 .enable = exynos4_clk_ip_peril_ctrl,
691 .ctrlbit = (1 << 11),
692 }, {
693 .name = "i2c",
694 .devname = "s3c2440-i2c.6",
695 .parent = &exynos4_clk_aclk_100.clk,
696 .enable = exynos4_clk_ip_peril_ctrl,
697 .ctrlbit = (1 << 12),
698 }, {
699 .name = "i2c",
700 .devname = "s3c2440-i2c.7",
701 .parent = &exynos4_clk_aclk_100.clk,
702 .enable = exynos4_clk_ip_peril_ctrl,
703 .ctrlbit = (1 << 13),
704 }, {
705 .name = "i2c",
706 .devname = "s3c2440-hdmiphy-i2c",
707 .parent = &exynos4_clk_aclk_100.clk,
708 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 14),
710 }, {
711 .name = "sysmmu",
712 .devname = "exynos-sysmmu.0",
713 .enable = exynos4_clk_ip_mfc_ctrl,
714 .ctrlbit = (1 << 1),
715 }, {
716 .name = "sysmmu",
717 .devname = "exynos-sysmmu.1",
718 .enable = exynos4_clk_ip_mfc_ctrl,
719 .ctrlbit = (1 << 2),
720 }, {
721 .name = "sysmmu",
722 .devname = "exynos-sysmmu.2",
723 .enable = exynos4_clk_ip_tv_ctrl,
724 .ctrlbit = (1 << 4),
725 }, {
726 .name = "sysmmu",
727 .devname = "exynos-sysmmu.3",
728 .enable = exynos4_clk_ip_cam_ctrl,
729 .ctrlbit = (1 << 11),
730 }, {
731 .name = "sysmmu",
732 .devname = "exynos-sysmmu.4",
733 .enable = exynos4_clk_ip_image_ctrl,
734 .ctrlbit = (1 << 4),
735 }, {
736 .name = "sysmmu",
737 .devname = "exynos-sysmmu.5",
738 .enable = exynos4_clk_ip_cam_ctrl,
739 .ctrlbit = (1 << 7),
740 }, {
741 .name = "sysmmu",
742 .devname = "exynos-sysmmu.6",
743 .enable = exynos4_clk_ip_cam_ctrl,
744 .ctrlbit = (1 << 8),
745 }, {
746 .name = "sysmmu",
747 .devname = "exynos-sysmmu.7",
748 .enable = exynos4_clk_ip_cam_ctrl,
749 .ctrlbit = (1 << 9),
750 }, {
751 .name = "sysmmu",
752 .devname = "exynos-sysmmu.8",
753 .enable = exynos4_clk_ip_cam_ctrl,
754 .ctrlbit = (1 << 10),
755 }, {
756 .name = "sysmmu",
757 .devname = "exynos-sysmmu.10",
758 .enable = exynos4_clk_ip_lcd0_ctrl,
759 .ctrlbit = (1 << 4),
760 }
761};
762
763static struct clk exynos4_init_clocks_on[] = {
764 {
765 .name = "uart",
766 .devname = "s5pv210-uart.0",
767 .enable = exynos4_clk_ip_peril_ctrl,
768 .ctrlbit = (1 << 0),
769 }, {
770 .name = "uart",
771 .devname = "s5pv210-uart.1",
772 .enable = exynos4_clk_ip_peril_ctrl,
773 .ctrlbit = (1 << 1),
774 }, {
775 .name = "uart",
776 .devname = "s5pv210-uart.2",
777 .enable = exynos4_clk_ip_peril_ctrl,
778 .ctrlbit = (1 << 2),
779 }, {
780 .name = "uart",
781 .devname = "s5pv210-uart.3",
782 .enable = exynos4_clk_ip_peril_ctrl,
783 .ctrlbit = (1 << 3),
784 }, {
785 .name = "uart",
786 .devname = "s5pv210-uart.4",
787 .enable = exynos4_clk_ip_peril_ctrl,
788 .ctrlbit = (1 << 4),
789 }, {
790 .name = "uart",
791 .devname = "s5pv210-uart.5",
792 .enable = exynos4_clk_ip_peril_ctrl,
793 .ctrlbit = (1 << 5),
794 }
795};
796
797static struct clk exynos4_clk_pdma0 = {
798 .name = "dma",
799 .devname = "dma-pl330.0",
800 .enable = exynos4_clk_ip_fsys_ctrl,
801 .ctrlbit = (1 << 0),
802};
803
804static struct clk exynos4_clk_pdma1 = {
805 .name = "dma",
806 .devname = "dma-pl330.1",
807 .enable = exynos4_clk_ip_fsys_ctrl,
808 .ctrlbit = (1 << 1),
809};
810
811static struct clk exynos4_clk_mdma1 = {
812 .name = "dma",
813 .devname = "dma-pl330.2",
814 .enable = exynos4_clk_ip_image_ctrl,
815 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
816};
817
818static struct clk exynos4_clk_fimd0 = {
819 .name = "fimd",
820 .devname = "exynos4-fb.0",
821 .enable = exynos4_clk_ip_lcd0_ctrl,
822 .ctrlbit = (1 << 0),
823};
824
825struct clk *exynos4_clkset_group_list[] = {
826 [0] = &clk_ext_xtal_mux,
827 [1] = &clk_xusbxti,
828 [2] = &exynos4_clk_sclk_hdmi27m,
829 [3] = &exynos4_clk_sclk_usbphy0,
830 [4] = &exynos4_clk_sclk_usbphy1,
831 [5] = &exynos4_clk_sclk_hdmiphy,
832 [6] = &exynos4_clk_mout_mpll.clk,
833 [7] = &exynos4_clk_mout_epll.clk,
834 [8] = &exynos4_clk_sclk_vpll.clk,
835};
836
837struct clksrc_sources exynos4_clkset_group = {
838 .sources = exynos4_clkset_group_list,
839 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
840};
841
842static struct clk *exynos4_clkset_mout_g2d0_list[] = {
843 [0] = &exynos4_clk_mout_mpll.clk,
844 [1] = &exynos4_clk_sclk_apll.clk,
845};
846
847struct clksrc_sources exynos4_clkset_mout_g2d0 = {
848 .sources = exynos4_clkset_mout_g2d0_list,
849 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
850};
851
852static struct clk *exynos4_clkset_mout_g2d1_list[] = {
853 [0] = &exynos4_clk_mout_epll.clk,
854 [1] = &exynos4_clk_sclk_vpll.clk,
855};
856
857struct clksrc_sources exynos4_clkset_mout_g2d1 = {
858 .sources = exynos4_clkset_mout_g2d1_list,
859 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
860};
861
862static struct clk *exynos4_clkset_mout_mfc0_list[] = {
863 [0] = &exynos4_clk_mout_mpll.clk,
864 [1] = &exynos4_clk_sclk_apll.clk,
865};
866
867static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
868 .sources = exynos4_clkset_mout_mfc0_list,
869 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
870};
871
872static struct clksrc_clk exynos4_clk_mout_mfc0 = {
873 .clk = {
874 .name = "mout_mfc0",
875 },
876 .sources = &exynos4_clkset_mout_mfc0,
877 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
878};
879
880static struct clk *exynos4_clkset_mout_mfc1_list[] = {
881 [0] = &exynos4_clk_mout_epll.clk,
882 [1] = &exynos4_clk_sclk_vpll.clk,
883};
884
885static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
886 .sources = exynos4_clkset_mout_mfc1_list,
887 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
888};
889
890static struct clksrc_clk exynos4_clk_mout_mfc1 = {
891 .clk = {
892 .name = "mout_mfc1",
893 },
894 .sources = &exynos4_clkset_mout_mfc1,
895 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
896};
897
898static struct clk *exynos4_clkset_mout_mfc_list[] = {
899 [0] = &exynos4_clk_mout_mfc0.clk,
900 [1] = &exynos4_clk_mout_mfc1.clk,
901};
902
903static struct clksrc_sources exynos4_clkset_mout_mfc = {
904 .sources = exynos4_clkset_mout_mfc_list,
905 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
906};
907
908static struct clk *exynos4_clkset_sclk_dac_list[] = {
909 [0] = &exynos4_clk_sclk_vpll.clk,
910 [1] = &exynos4_clk_sclk_hdmiphy,
911};
912
913static struct clksrc_sources exynos4_clkset_sclk_dac = {
914 .sources = exynos4_clkset_sclk_dac_list,
915 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
916};
917
918static struct clksrc_clk exynos4_clk_sclk_dac = {
919 .clk = {
920 .name = "sclk_dac",
921 .enable = exynos4_clksrc_mask_tv_ctrl,
922 .ctrlbit = (1 << 8),
923 },
924 .sources = &exynos4_clkset_sclk_dac,
925 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
926};
927
928static struct clksrc_clk exynos4_clk_sclk_pixel = {
929 .clk = {
930 .name = "sclk_pixel",
931 .parent = &exynos4_clk_sclk_vpll.clk,
932 },
933 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
934};
935
936static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
937 [0] = &exynos4_clk_sclk_pixel.clk,
938 [1] = &exynos4_clk_sclk_hdmiphy,
939};
940
941static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
942 .sources = exynos4_clkset_sclk_hdmi_list,
943 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
944};
945
946static struct clksrc_clk exynos4_clk_sclk_hdmi = {
947 .clk = {
948 .name = "sclk_hdmi",
949 .enable = exynos4_clksrc_mask_tv_ctrl,
950 .ctrlbit = (1 << 0),
951 },
952 .sources = &exynos4_clkset_sclk_hdmi,
953 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
954};
955
956static struct clk *exynos4_clkset_sclk_mixer_list[] = {
957 [0] = &exynos4_clk_sclk_dac.clk,
958 [1] = &exynos4_clk_sclk_hdmi.clk,
959};
960
961static struct clksrc_sources exynos4_clkset_sclk_mixer = {
962 .sources = exynos4_clkset_sclk_mixer_list,
963 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
964};
965
966static struct clksrc_clk exynos4_clk_sclk_mixer = {
967 .clk = {
968 .name = "sclk_mixer",
969 .enable = exynos4_clksrc_mask_tv_ctrl,
970 .ctrlbit = (1 << 4),
971 },
972 .sources = &exynos4_clkset_sclk_mixer,
973 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
974};
975
976static struct clksrc_clk *exynos4_sclk_tv[] = {
977 &exynos4_clk_sclk_dac,
978 &exynos4_clk_sclk_pixel,
979 &exynos4_clk_sclk_hdmi,
980 &exynos4_clk_sclk_mixer,
981};
982
983static struct clksrc_clk exynos4_clk_dout_mmc0 = {
984 .clk = {
985 .name = "dout_mmc0",
986 },
987 .sources = &exynos4_clkset_group,
988 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
989 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
990};
991
992static struct clksrc_clk exynos4_clk_dout_mmc1 = {
993 .clk = {
994 .name = "dout_mmc1",
995 },
996 .sources = &exynos4_clkset_group,
997 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
998 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
999};
1000
1001static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1002 .clk = {
1003 .name = "dout_mmc2",
1004 },
1005 .sources = &exynos4_clkset_group,
1006 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1007 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1008};
1009
1010static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1011 .clk = {
1012 .name = "dout_mmc3",
1013 },
1014 .sources = &exynos4_clkset_group,
1015 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1016 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1017};
1018
1019static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1020 .clk = {
1021 .name = "dout_mmc4",
1022 },
1023 .sources = &exynos4_clkset_group,
1024 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1025 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1026};
1027
1028static struct clksrc_clk exynos4_clksrcs[] = {
1029 {
1030 .clk = {
1031 .name = "sclk_pwm",
1032 .enable = exynos4_clksrc_mask_peril0_ctrl,
1033 .ctrlbit = (1 << 24),
1034 },
1035 .sources = &exynos4_clkset_group,
1036 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1037 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1038 }, {
1039 .clk = {
1040 .name = "sclk_csis",
1041 .devname = "s5p-mipi-csis.0",
1042 .enable = exynos4_clksrc_mask_cam_ctrl,
1043 .ctrlbit = (1 << 24),
1044 },
1045 .sources = &exynos4_clkset_group,
1046 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1047 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_csis",
1051 .devname = "s5p-mipi-csis.1",
1052 .enable = exynos4_clksrc_mask_cam_ctrl,
1053 .ctrlbit = (1 << 28),
1054 },
1055 .sources = &exynos4_clkset_group,
1056 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1057 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1058 }, {
1059 .clk = {
1060 .name = "sclk_cam0",
1061 .enable = exynos4_clksrc_mask_cam_ctrl,
1062 .ctrlbit = (1 << 16),
1063 },
1064 .sources = &exynos4_clkset_group,
1065 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1066 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1067 }, {
1068 .clk = {
1069 .name = "sclk_cam1",
1070 .enable = exynos4_clksrc_mask_cam_ctrl,
1071 .ctrlbit = (1 << 20),
1072 },
1073 .sources = &exynos4_clkset_group,
1074 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1075 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1076 }, {
1077 .clk = {
1078 .name = "sclk_fimc",
1079 .devname = "exynos4-fimc.0",
1080 .enable = exynos4_clksrc_mask_cam_ctrl,
1081 .ctrlbit = (1 << 0),
1082 },
1083 .sources = &exynos4_clkset_group,
1084 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1085 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1086 }, {
1087 .clk = {
1088 .name = "sclk_fimc",
1089 .devname = "exynos4-fimc.1",
1090 .enable = exynos4_clksrc_mask_cam_ctrl,
1091 .ctrlbit = (1 << 4),
1092 },
1093 .sources = &exynos4_clkset_group,
1094 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1096 }, {
1097 .clk = {
1098 .name = "sclk_fimc",
1099 .devname = "exynos4-fimc.2",
1100 .enable = exynos4_clksrc_mask_cam_ctrl,
1101 .ctrlbit = (1 << 8),
1102 },
1103 .sources = &exynos4_clkset_group,
1104 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1105 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1106 }, {
1107 .clk = {
1108 .name = "sclk_fimc",
1109 .devname = "exynos4-fimc.3",
1110 .enable = exynos4_clksrc_mask_cam_ctrl,
1111 .ctrlbit = (1 << 12),
1112 },
1113 .sources = &exynos4_clkset_group,
1114 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1115 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1116 }, {
1117 .clk = {
1118 .name = "sclk_fimd",
1119 .devname = "exynos4-fb.0",
1120 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1121 .ctrlbit = (1 << 0),
1122 },
1123 .sources = &exynos4_clkset_group,
1124 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1125 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1126 }, {
1127 .clk = {
1128 .name = "sclk_mfc",
1129 .devname = "s5p-mfc",
1130 },
1131 .sources = &exynos4_clkset_mout_mfc,
1132 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1133 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1134 }, {
1135 .clk = {
1136 .name = "ciu",
1137 .parent = &exynos4_clk_dout_mmc4.clk,
1138 .enable = exynos4_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 16),
1140 },
1141 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1142 }
1143};
1144
1145static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1146 .clk = {
1147 .name = "uclk1",
1148 .devname = "exynos4210-uart.0",
1149 .enable = exynos4_clksrc_mask_peril0_ctrl,
1150 .ctrlbit = (1 << 0),
1151 },
1152 .sources = &exynos4_clkset_group,
1153 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1154 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1155};
1156
1157static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1158 .clk = {
1159 .name = "uclk1",
1160 .devname = "exynos4210-uart.1",
1161 .enable = exynos4_clksrc_mask_peril0_ctrl,
1162 .ctrlbit = (1 << 4),
1163 },
1164 .sources = &exynos4_clkset_group,
1165 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1166 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1167};
1168
1169static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1170 .clk = {
1171 .name = "uclk1",
1172 .devname = "exynos4210-uart.2",
1173 .enable = exynos4_clksrc_mask_peril0_ctrl,
1174 .ctrlbit = (1 << 8),
1175 },
1176 .sources = &exynos4_clkset_group,
1177 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1178 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1179};
1180
1181static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1182 .clk = {
1183 .name = "uclk1",
1184 .devname = "exynos4210-uart.3",
1185 .enable = exynos4_clksrc_mask_peril0_ctrl,
1186 .ctrlbit = (1 << 12),
1187 },
1188 .sources = &exynos4_clkset_group,
1189 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1190 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1191};
1192
1193static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1194 .clk = {
1195 .name = "sclk_mmc",
1196 .devname = "exynos4-sdhci.0",
1197 .parent = &exynos4_clk_dout_mmc0.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl,
1199 .ctrlbit = (1 << 0),
1200 },
1201 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1202};
1203
1204static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1205 .clk = {
1206 .name = "sclk_mmc",
1207 .devname = "exynos4-sdhci.1",
1208 .parent = &exynos4_clk_dout_mmc1.clk,
1209 .enable = exynos4_clksrc_mask_fsys_ctrl,
1210 .ctrlbit = (1 << 4),
1211 },
1212 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1213};
1214
1215static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1216 .clk = {
1217 .name = "sclk_mmc",
1218 .devname = "exynos4-sdhci.2",
1219 .parent = &exynos4_clk_dout_mmc2.clk,
1220 .enable = exynos4_clksrc_mask_fsys_ctrl,
1221 .ctrlbit = (1 << 8),
1222 },
1223 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1224};
1225
1226static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1227 .clk = {
1228 .name = "sclk_mmc",
1229 .devname = "exynos4-sdhci.3",
1230 .parent = &exynos4_clk_dout_mmc3.clk,
1231 .enable = exynos4_clksrc_mask_fsys_ctrl,
1232 .ctrlbit = (1 << 12),
1233 },
1234 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1235};
1236
1237static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1238 .clk = {
1239 .name = "mdout_spi",
1240 .devname = "exynos4210-spi.0",
1241 },
1242 .sources = &exynos4_clkset_group,
1243 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1244 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1245};
1246
1247static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1248 .clk = {
1249 .name = "mdout_spi",
1250 .devname = "exynos4210-spi.1",
1251 },
1252 .sources = &exynos4_clkset_group,
1253 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255};
1256
1257static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1258 .clk = {
1259 .name = "mdout_spi",
1260 .devname = "exynos4210-spi.2",
1261 },
1262 .sources = &exynos4_clkset_group,
1263 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1265};
1266
1267static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1268 .clk = {
1269 .name = "sclk_spi",
1270 .devname = "exynos4210-spi.0",
1271 .parent = &exynos4_clk_mdout_spi0.clk,
1272 .enable = exynos4_clksrc_mask_peril1_ctrl,
1273 .ctrlbit = (1 << 16),
1274 },
1275 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1276};
1277
1278static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1279 .clk = {
1280 .name = "sclk_spi",
1281 .devname = "exynos4210-spi.1",
1282 .parent = &exynos4_clk_mdout_spi1.clk,
1283 .enable = exynos4_clksrc_mask_peril1_ctrl,
1284 .ctrlbit = (1 << 20),
1285 },
1286 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1287};
1288
1289static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1290 .clk = {
1291 .name = "sclk_spi",
1292 .devname = "exynos4210-spi.2",
1293 .parent = &exynos4_clk_mdout_spi2.clk,
1294 .enable = exynos4_clksrc_mask_peril1_ctrl,
1295 .ctrlbit = (1 << 24),
1296 },
1297 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1298};
1299
1300/* Clock initialization code */
1301static struct clksrc_clk *exynos4_sysclks[] = {
1302 &exynos4_clk_mout_apll,
1303 &exynos4_clk_sclk_apll,
1304 &exynos4_clk_mout_epll,
1305 &exynos4_clk_mout_mpll,
1306 &exynos4_clk_moutcore,
1307 &exynos4_clk_coreclk,
1308 &exynos4_clk_armclk,
1309 &exynos4_clk_aclk_corem0,
1310 &exynos4_clk_aclk_cores,
1311 &exynos4_clk_aclk_corem1,
1312 &exynos4_clk_periphclk,
1313 &exynos4_clk_mout_corebus,
1314 &exynos4_clk_sclk_dmc,
1315 &exynos4_clk_aclk_cored,
1316 &exynos4_clk_aclk_corep,
1317 &exynos4_clk_aclk_acp,
1318 &exynos4_clk_pclk_acp,
1319 &exynos4_clk_vpllsrc,
1320 &exynos4_clk_sclk_vpll,
1321 &exynos4_clk_aclk_200,
1322 &exynos4_clk_aclk_100,
1323 &exynos4_clk_aclk_160,
1324 &exynos4_clk_aclk_133,
1325 &exynos4_clk_dout_mmc0,
1326 &exynos4_clk_dout_mmc1,
1327 &exynos4_clk_dout_mmc2,
1328 &exynos4_clk_dout_mmc3,
1329 &exynos4_clk_dout_mmc4,
1330 &exynos4_clk_mout_mfc0,
1331 &exynos4_clk_mout_mfc1,
1332};
1333
1334static struct clk *exynos4_clk_cdev[] = {
1335 &exynos4_clk_pdma0,
1336 &exynos4_clk_pdma1,
1337 &exynos4_clk_mdma1,
1338 &exynos4_clk_fimd0,
1339};
1340
1341static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1342 &exynos4_clk_sclk_uart0,
1343 &exynos4_clk_sclk_uart1,
1344 &exynos4_clk_sclk_uart2,
1345 &exynos4_clk_sclk_uart3,
1346 &exynos4_clk_sclk_mmc0,
1347 &exynos4_clk_sclk_mmc1,
1348 &exynos4_clk_sclk_mmc2,
1349 &exynos4_clk_sclk_mmc3,
1350 &exynos4_clk_sclk_spi0,
1351 &exynos4_clk_sclk_spi1,
1352 &exynos4_clk_sclk_spi2,
1353 &exynos4_clk_mdout_spi0,
1354 &exynos4_clk_mdout_spi1,
1355 &exynos4_clk_mdout_spi2,
1356};
1357
1358static struct clk_lookup exynos4_clk_lookup[] = {
1359 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1360 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1361 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1362 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1363 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1364 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1365 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1366 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1367 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1368 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1369 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1370 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1371 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1372 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1373 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1374};
1375
1376static int xtal_rate;
1377
1378static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1379{
1380 if (soc_is_exynos4210())
1381 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1382 pll_4508);
1383 else if (soc_is_exynos4212() || soc_is_exynos4412())
1384 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1385 else
1386 return 0;
1387}
1388
1389static struct clk_ops exynos4_fout_apll_ops = {
1390 .get_rate = exynos4_fout_apll_get_rate,
1391};
1392
1393static u32 exynos4_vpll_div[][8] = {
1394 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1395 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1396};
1397
1398static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1399{
1400 return clk->rate;
1401}
1402
1403static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1404{
1405 unsigned int vpll_con0, vpll_con1 = 0;
1406 unsigned int i;
1407
1408 /* Return if nothing changed */
1409 if (clk->rate == rate)
1410 return 0;
1411
1412 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1413 vpll_con0 &= ~(0x1 << 27 | \
1414 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1415 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1416 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1417
1418 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1419 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1420 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1421 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1422
1423 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1424 if (exynos4_vpll_div[i][0] == rate) {
1425 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1426 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1427 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1428 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1429 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1430 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1431 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1432 break;
1433 }
1434 }
1435
1436 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1437 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1438 __func__);
1439 return -EINVAL;
1440 }
1441
1442 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1443 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1444
1445 /* Wait for VPLL lock */
1446 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1447 continue;
1448
1449 clk->rate = rate;
1450 return 0;
1451}
1452
1453static struct clk_ops exynos4_vpll_ops = {
1454 .get_rate = exynos4_vpll_get_rate,
1455 .set_rate = exynos4_vpll_set_rate,
1456};
1457
1458void __init_or_cpufreq exynos4_setup_clocks(void)
1459{
1460 struct clk *xtal_clk;
1461 unsigned long apll = 0;
1462 unsigned long mpll = 0;
1463 unsigned long epll = 0;
1464 unsigned long vpll = 0;
1465 unsigned long vpllsrc;
1466 unsigned long xtal;
1467 unsigned long armclk;
1468 unsigned long sclk_dmc;
1469 unsigned long aclk_200;
1470 unsigned long aclk_100;
1471 unsigned long aclk_160;
1472 unsigned long aclk_133;
1473 unsigned int ptr;
1474
1475 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1476
1477 xtal_clk = clk_get(NULL, "xtal");
1478 BUG_ON(IS_ERR(xtal_clk));
1479
1480 xtal = clk_get_rate(xtal_clk);
1481
1482 xtal_rate = xtal;
1483
1484 clk_put(xtal_clk);
1485
1486 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1487
1488 if (soc_is_exynos4210()) {
1489 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1490 pll_4508);
1491 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1492 pll_4508);
1493 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1494 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1495
1496 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1497 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1498 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1499 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1500 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1501 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1502 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1503 __raw_readl(EXYNOS4_EPLL_CON1));
1504
1505 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1506 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1507 __raw_readl(EXYNOS4_VPLL_CON1));
1508 } else {
1509 /* nothing */
1510 }
1511
1512 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1513 clk_fout_mpll.rate = mpll;
1514 clk_fout_epll.rate = epll;
1515 clk_fout_vpll.ops = &exynos4_vpll_ops;
1516 clk_fout_vpll.rate = vpll;
1517
1518 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1519 apll, mpll, epll, vpll);
1520
1521 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1522 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1523
1524 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1525 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1526 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1527 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1528
1529 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1530 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1531 armclk, sclk_dmc, aclk_200,
1532 aclk_100, aclk_160, aclk_133);
1533
1534 clk_f.rate = armclk;
1535 clk_h.rate = sclk_dmc;
1536 clk_p.rate = aclk_100;
1537
1538 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1539 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1540}
1541
1542static struct clk *exynos4_clks[] __initdata = {
1543 &exynos4_clk_sclk_hdmi27m,
1544 &exynos4_clk_sclk_hdmiphy,
1545 &exynos4_clk_sclk_usbphy0,
1546 &exynos4_clk_sclk_usbphy1,
1547};
1548
1549#ifdef CONFIG_PM_SLEEP
1550static int exynos4_clock_suspend(void)
1551{
1552 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1553 return 0;
1554}
1555
1556static void exynos4_clock_resume(void)
1557{
1558 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1559}
1560
1561#else
1562#define exynos4_clock_suspend NULL
1563#define exynos4_clock_resume NULL
1564#endif
1565
1566static struct syscore_ops exynos4_clock_syscore_ops = {
1567 .suspend = exynos4_clock_suspend,
1568 .resume = exynos4_clock_resume,
1569};
1570
1571void __init exynos4_register_clocks(void)
1572{
1573 int ptr;
1574
1575 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1576
1577 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1578 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1579
1580 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1581 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1582
1583 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1584 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1585
1586 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1587 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1588
1589 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1590 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1591 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1592
1593 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1594 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1595 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1596
1597 register_syscore_ops(&exynos4_clock_syscore_ops);
1598 s3c24xx_register_clock(&dummy_apb_pclk);
1599
1600 s3c_pwmclk_init();
1601}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for exynos4 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_CLOCK_H
13#define __ASM_ARCH_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk exynos4_clk_aclk_133;
18extern struct clksrc_clk exynos4_clk_mout_mpll;
19
20extern struct clksrc_sources exynos4_clkset_mout_corebus;
21extern struct clksrc_sources exynos4_clkset_group;
22
23extern struct clk *exynos4_clkset_aclk_top_list[];
24extern struct clk *exynos4_clkset_group_list[];
25
26extern struct clksrc_sources exynos4_clkset_mout_g2d0;
27extern struct clksrc_sources exynos4_clkset_mout_g2d1;
28
29extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
30extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
31extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
32extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
33extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
34
35#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4210 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/hardware.h>
27#include <mach/map.h>
28#include <mach/regs-clock.h>
29
30#include "common.h"
31#include "clock-exynos4.h"
32
33#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
38 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
39 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
43};
44#endif
45
46static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */
48};
49
50static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
51 .clk = {
52 .name = "mout_g2d0",
53 },
54 .sources = &exynos4_clkset_mout_g2d0,
55 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
56};
57
58static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
59 .clk = {
60 .name = "mout_g2d1",
61 },
62 .sources = &exynos4_clkset_mout_g2d1,
63 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
64};
65
66static struct clk *exynos4210_clkset_mout_g2d_list[] = {
67 [0] = &exynos4210_clk_mout_g2d0.clk,
68 [1] = &exynos4210_clk_mout_g2d1.clk,
69};
70
71static struct clksrc_sources exynos4210_clkset_mout_g2d = {
72 .sources = exynos4210_clkset_mout_g2d_list,
73 .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
74};
75
76static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
77{
78 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
79}
80
81static struct clksrc_clk clksrcs[] = {
82 {
83 .clk = {
84 .name = "sclk_sata",
85 .id = -1,
86 .enable = exynos4_clksrc_mask_fsys_ctrl,
87 .ctrlbit = (1 << 24),
88 },
89 .sources = &exynos4_clkset_mout_corebus,
90 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
91 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
92 }, {
93 .clk = {
94 .name = "sclk_fimd",
95 .devname = "exynos4-fb.1",
96 .enable = exynos4_clksrc_mask_lcd1_ctrl,
97 .ctrlbit = (1 << 0),
98 },
99 .sources = &exynos4_clkset_group,
100 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
101 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
102 }, {
103 .clk = {
104 .name = "sclk_fimg2d",
105 },
106 .sources = &exynos4210_clkset_mout_g2d,
107 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
108 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
109 },
110};
111
112static struct clk init_clocks_off[] = {
113 {
114 .name = "sataphy",
115 .id = -1,
116 .parent = &exynos4_clk_aclk_133.clk,
117 .enable = exynos4_clk_ip_fsys_ctrl,
118 .ctrlbit = (1 << 3),
119 }, {
120 .name = "sata",
121 .id = -1,
122 .parent = &exynos4_clk_aclk_133.clk,
123 .enable = exynos4_clk_ip_fsys_ctrl,
124 .ctrlbit = (1 << 10),
125 }, {
126 .name = "fimd",
127 .devname = "exynos4-fb.1",
128 .enable = exynos4_clk_ip_lcd1_ctrl,
129 .ctrlbit = (1 << 0),
130 }, {
131 .name = "sysmmu",
132 .devname = "exynos-sysmmu.9",
133 .enable = exynos4_clk_ip_image_ctrl,
134 .ctrlbit = (1 << 3),
135 }, {
136 .name = "sysmmu",
137 .devname = "exynos-sysmmu.11",
138 .enable = exynos4_clk_ip_lcd1_ctrl,
139 .ctrlbit = (1 << 4),
140 }, {
141 .name = "fimg2d",
142 .enable = exynos4_clk_ip_image_ctrl,
143 .ctrlbit = (1 << 0),
144 },
145};
146
147#ifdef CONFIG_PM_SLEEP
148static int exynos4210_clock_suspend(void)
149{
150 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
151
152 return 0;
153}
154
155static void exynos4210_clock_resume(void)
156{
157 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
158}
159
160#else
161#define exynos4210_clock_suspend NULL
162#define exynos4210_clock_resume NULL
163#endif
164
165static struct syscore_ops exynos4210_clock_syscore_ops = {
166 .suspend = exynos4210_clock_suspend,
167 .resume = exynos4210_clock_resume,
168};
169
170void __init exynos4210_register_clocks(void)
171{
172 int ptr;
173
174 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
175 exynos4_clk_mout_mpll.reg_src.shift = 8;
176 exynos4_clk_mout_mpll.reg_src.size = 1;
177
178 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
179 s3c_register_clksrc(sysclks[ptr], 1);
180
181 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
182
183 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
184 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
185
186 register_syscore_ops(&exynos4210_clock_syscore_ops);
187}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4212 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/hardware.h>
27#include <mach/map.h>
28#include <mach/regs-clock.h>
29
30#include "common.h"
31#include "clock-exynos4.h"
32
33#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
39};
40#endif
41
42static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
43{
44 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
45}
46
47static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
48{
49 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
50}
51
52static struct clk *clk_src_mpll_user_list[] = {
53 [0] = &clk_fin_mpll,
54 [1] = &exynos4_clk_mout_mpll.clk,
55};
56
57static struct clksrc_sources clk_src_mpll_user = {
58 .sources = clk_src_mpll_user_list,
59 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
60};
61
62static struct clksrc_clk clk_mout_mpll_user = {
63 .clk = {
64 .name = "mout_mpll_user",
65 },
66 .sources = &clk_src_mpll_user,
67 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
68};
69
70static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
71 .clk = {
72 .name = "mout_g2d0",
73 },
74 .sources = &exynos4_clkset_mout_g2d0,
75 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
76};
77
78static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
79 .clk = {
80 .name = "mout_g2d1",
81 },
82 .sources = &exynos4_clkset_mout_g2d1,
83 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
84};
85
86static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
87 [0] = &exynos4x12_clk_mout_g2d0.clk,
88 [1] = &exynos4x12_clk_mout_g2d1.clk,
89};
90
91static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
92 .sources = exynos4x12_clkset_mout_g2d_list,
93 .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
94};
95
96static struct clksrc_clk *sysclks[] = {
97 &clk_mout_mpll_user,
98};
99
100static struct clksrc_clk clksrcs[] = {
101 {
102 .clk = {
103 .name = "sclk_fimg2d",
104 },
105 .sources = &exynos4x12_clkset_mout_g2d,
106 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
107 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
108 },
109};
110
111static struct clk init_clocks_off[] = {
112 {
113 .name = "sysmmu",
114 .devname = "exynos-sysmmu.9",
115 .enable = exynos4_clk_ip_dmc_ctrl,
116 .ctrlbit = (1 << 24),
117 }, {
118 .name = "sysmmu",
119 .devname = "exynos-sysmmu.12",
120 .enable = exynos4212_clk_ip_isp0_ctrl,
121 .ctrlbit = (7 << 8),
122 }, {
123 .name = "sysmmu",
124 .devname = "exynos-sysmmu.13",
125 .enable = exynos4212_clk_ip_isp1_ctrl,
126 .ctrlbit = (1 << 4),
127 }, {
128 .name = "sysmmu",
129 .devname = "exynos-sysmmu.14",
130 .enable = exynos4212_clk_ip_isp0_ctrl,
131 .ctrlbit = (1 << 11),
132 }, {
133 .name = "sysmmu",
134 .devname = "exynos-sysmmu.15",
135 .enable = exynos4212_clk_ip_isp0_ctrl,
136 .ctrlbit = (1 << 12),
137 }, {
138 .name = "flite",
139 .devname = "exynos-fimc-lite.0",
140 .enable = exynos4212_clk_ip_isp0_ctrl,
141 .ctrlbit = (1 << 4),
142 }, {
143 .name = "flite",
144 .devname = "exynos-fimc-lite.1",
145 .enable = exynos4212_clk_ip_isp0_ctrl,
146 .ctrlbit = (1 << 3),
147 }, {
148 .name = "fimg2d",
149 .enable = exynos4_clk_ip_dmc_ctrl,
150 .ctrlbit = (1 << 23),
151 },
152};
153
154#ifdef CONFIG_PM_SLEEP
155static int exynos4212_clock_suspend(void)
156{
157 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
158
159 return 0;
160}
161
162static void exynos4212_clock_resume(void)
163{
164 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
165}
166
167#else
168#define exynos4212_clock_suspend NULL
169#define exynos4212_clock_resume NULL
170#endif
171
172static struct syscore_ops exynos4212_clock_syscore_ops = {
173 .suspend = exynos4212_clock_suspend,
174 .resume = exynos4212_clock_resume,
175};
176
177void __init exynos4212_register_clocks(void)
178{
179 int ptr;
180
181 /* usbphy1 is removed */
182 exynos4_clkset_group_list[4] = NULL;
183
184 /* mout_mpll_user is used */
185 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
186 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
187
188 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
189 exynos4_clk_mout_mpll.reg_src.shift = 12;
190 exynos4_clk_mout_mpll.reg_src.size = 1;
191
192 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
193 s3c_register_clksrc(sysclks[ptr], 1);
194
195 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
196
197 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
198 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
199
200 register_syscore_ops(&exynos4212_clock_syscore_ops);
201}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27
28#include "common.h"
29
30#ifdef CONFIG_PM_SLEEP
31static struct sleep_save exynos5_clock_save[] = {
32 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
39 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
47 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
48 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
50 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
51 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
52 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
53 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
64 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
65 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
69 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
70 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
71 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
72 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
73 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
75 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
76 SAVE_ITEM(EXYNOS5_EPLL_CON0),
77 SAVE_ITEM(EXYNOS5_EPLL_CON1),
78 SAVE_ITEM(EXYNOS5_EPLL_CON2),
79 SAVE_ITEM(EXYNOS5_VPLL_CON0),
80 SAVE_ITEM(EXYNOS5_VPLL_CON1),
81 SAVE_ITEM(EXYNOS5_VPLL_CON2),
82 SAVE_ITEM(EXYNOS5_PWR_CTRL1),
83 SAVE_ITEM(EXYNOS5_PWR_CTRL2),
84};
85#endif
86
87static struct clk exynos5_clk_sclk_dptxphy = {
88 .name = "sclk_dptx",
89};
90
91static struct clk exynos5_clk_sclk_hdmi24m = {
92 .name = "sclk_hdmi24m",
93 .rate = 24000000,
94};
95
96static struct clk exynos5_clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
98 .rate = 27000000,
99};
100
101static struct clk exynos5_clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
103};
104
105static struct clk exynos5_clk_sclk_usbphy = {
106 .name = "sclk_usbphy",
107 .rate = 48000000,
108};
109
110static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
113}
114
115static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
118}
119
120static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
123}
124
125static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
128}
129
130static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
133}
134
135static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
138}
139
140static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
143}
144
145static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
148}
149
150static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
153}
154
155static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
158}
159
160static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
163}
164
165static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
168}
169
170static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
173}
174
175static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
178}
179
180static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
183}
184
185static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
188}
189
190static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
193}
194
195static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
198}
199
200static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
203}
204
205/* Core list of CMU_CPU side */
206
207static struct clksrc_clk exynos5_clk_mout_apll = {
208 .clk = {
209 .name = "mout_apll",
210 },
211 .sources = &clk_src_apll,
212 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
213};
214
215static struct clksrc_clk exynos5_clk_sclk_apll = {
216 .clk = {
217 .name = "sclk_apll",
218 .parent = &exynos5_clk_mout_apll.clk,
219 },
220 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
221};
222
223static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
224 .clk = {
225 .name = "mout_bpll_fout",
226 },
227 .sources = &clk_src_bpll_fout,
228 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
229};
230
231static struct clk *exynos5_clk_src_bpll_list[] = {
232 [0] = &clk_fin_bpll,
233 [1] = &exynos5_clk_mout_bpll_fout.clk,
234};
235
236static struct clksrc_sources exynos5_clk_src_bpll = {
237 .sources = exynos5_clk_src_bpll_list,
238 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
239};
240
241static struct clksrc_clk exynos5_clk_mout_bpll = {
242 .clk = {
243 .name = "mout_bpll",
244 },
245 .sources = &exynos5_clk_src_bpll,
246 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
247};
248
249static struct clk *exynos5_clk_src_bpll_user_list[] = {
250 [0] = &clk_fin_mpll,
251 [1] = &exynos5_clk_mout_bpll.clk,
252};
253
254static struct clksrc_sources exynos5_clk_src_bpll_user = {
255 .sources = exynos5_clk_src_bpll_user_list,
256 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
257};
258
259static struct clksrc_clk exynos5_clk_mout_bpll_user = {
260 .clk = {
261 .name = "mout_bpll_user",
262 },
263 .sources = &exynos5_clk_src_bpll_user,
264 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
265};
266
267static struct clksrc_clk exynos5_clk_mout_cpll = {
268 .clk = {
269 .name = "mout_cpll",
270 },
271 .sources = &clk_src_cpll,
272 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
273};
274
275static struct clksrc_clk exynos5_clk_mout_epll = {
276 .clk = {
277 .name = "mout_epll",
278 },
279 .sources = &clk_src_epll,
280 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
281};
282
283static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
284 .clk = {
285 .name = "mout_mpll_fout",
286 },
287 .sources = &clk_src_mpll_fout,
288 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
289};
290
291static struct clk *exynos5_clk_src_mpll_list[] = {
292 [0] = &clk_fin_mpll,
293 [1] = &exynos5_clk_mout_mpll_fout.clk,
294};
295
296static struct clksrc_sources exynos5_clk_src_mpll = {
297 .sources = exynos5_clk_src_mpll_list,
298 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
299};
300
301static struct clksrc_clk exynos5_clk_mout_mpll = {
302 .clk = {
303 .name = "mout_mpll",
304 },
305 .sources = &exynos5_clk_src_mpll,
306 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
307};
308
309static struct clk *exynos_clkset_vpllsrc_list[] = {
310 [0] = &clk_fin_vpll,
311 [1] = &exynos5_clk_sclk_hdmi27m,
312};
313
314static struct clksrc_sources exynos5_clkset_vpllsrc = {
315 .sources = exynos_clkset_vpllsrc_list,
316 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
317};
318
319static struct clksrc_clk exynos5_clk_vpllsrc = {
320 .clk = {
321 .name = "vpll_src",
322 .enable = exynos5_clksrc_mask_top_ctrl,
323 .ctrlbit = (1 << 0),
324 },
325 .sources = &exynos5_clkset_vpllsrc,
326 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
327};
328
329static struct clk *exynos5_clkset_sclk_vpll_list[] = {
330 [0] = &exynos5_clk_vpllsrc.clk,
331 [1] = &clk_fout_vpll,
332};
333
334static struct clksrc_sources exynos5_clkset_sclk_vpll = {
335 .sources = exynos5_clkset_sclk_vpll_list,
336 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
337};
338
339static struct clksrc_clk exynos5_clk_sclk_vpll = {
340 .clk = {
341 .name = "sclk_vpll",
342 },
343 .sources = &exynos5_clkset_sclk_vpll,
344 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
345};
346
347static struct clksrc_clk exynos5_clk_sclk_pixel = {
348 .clk = {
349 .name = "sclk_pixel",
350 .parent = &exynos5_clk_sclk_vpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
353};
354
355static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
356 [0] = &exynos5_clk_sclk_pixel.clk,
357 [1] = &exynos5_clk_sclk_hdmiphy,
358};
359
360static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
361 .sources = exynos5_clkset_sclk_hdmi_list,
362 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
363};
364
365static struct clksrc_clk exynos5_clk_sclk_hdmi = {
366 .clk = {
367 .name = "sclk_hdmi",
368 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
369 .ctrlbit = (1 << 20),
370 },
371 .sources = &exynos5_clkset_sclk_hdmi,
372 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
373};
374
375static struct clksrc_clk *exynos5_sclk_tv[] = {
376 &exynos5_clk_sclk_pixel,
377 &exynos5_clk_sclk_hdmi,
378};
379
380static struct clk *exynos5_clk_src_mpll_user_list[] = {
381 [0] = &clk_fin_mpll,
382 [1] = &exynos5_clk_mout_mpll.clk,
383};
384
385static struct clksrc_sources exynos5_clk_src_mpll_user = {
386 .sources = exynos5_clk_src_mpll_user_list,
387 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
388};
389
390static struct clksrc_clk exynos5_clk_mout_mpll_user = {
391 .clk = {
392 .name = "mout_mpll_user",
393 },
394 .sources = &exynos5_clk_src_mpll_user,
395 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
396};
397
398static struct clk *exynos5_clkset_mout_cpu_list[] = {
399 [0] = &exynos5_clk_mout_apll.clk,
400 [1] = &exynos5_clk_mout_mpll.clk,
401};
402
403static struct clksrc_sources exynos5_clkset_mout_cpu = {
404 .sources = exynos5_clkset_mout_cpu_list,
405 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
406};
407
408static struct clksrc_clk exynos5_clk_mout_cpu = {
409 .clk = {
410 .name = "mout_cpu",
411 },
412 .sources = &exynos5_clkset_mout_cpu,
413 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
414};
415
416static struct clksrc_clk exynos5_clk_dout_armclk = {
417 .clk = {
418 .name = "dout_armclk",
419 .parent = &exynos5_clk_mout_cpu.clk,
420 },
421 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
422};
423
424static struct clksrc_clk exynos5_clk_dout_arm2clk = {
425 .clk = {
426 .name = "dout_arm2clk",
427 .parent = &exynos5_clk_dout_armclk.clk,
428 },
429 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
430};
431
432static struct clk exynos5_clk_armclk = {
433 .name = "armclk",
434 .parent = &exynos5_clk_dout_arm2clk.clk,
435};
436
437/* Core list of CMU_CDREX side */
438
439static struct clk *exynos5_clkset_cdrex_list[] = {
440 [0] = &exynos5_clk_mout_mpll.clk,
441 [1] = &exynos5_clk_mout_bpll.clk,
442};
443
444static struct clksrc_sources exynos5_clkset_cdrex = {
445 .sources = exynos5_clkset_cdrex_list,
446 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
447};
448
449static struct clksrc_clk exynos5_clk_cdrex = {
450 .clk = {
451 .name = "clk_cdrex",
452 },
453 .sources = &exynos5_clkset_cdrex,
454 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
455 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
456};
457
458static struct clksrc_clk exynos5_clk_aclk_acp = {
459 .clk = {
460 .name = "aclk_acp",
461 .parent = &exynos5_clk_mout_mpll.clk,
462 },
463 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
464};
465
466static struct clksrc_clk exynos5_clk_pclk_acp = {
467 .clk = {
468 .name = "pclk_acp",
469 .parent = &exynos5_clk_aclk_acp.clk,
470 },
471 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
472};
473
474/* Core list of CMU_TOP side */
475
476static struct clk *exynos5_clkset_aclk_top_list[] = {
477 [0] = &exynos5_clk_mout_mpll_user.clk,
478 [1] = &exynos5_clk_mout_bpll_user.clk,
479};
480
481static struct clksrc_sources exynos5_clkset_aclk = {
482 .sources = exynos5_clkset_aclk_top_list,
483 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
484};
485
486static struct clksrc_clk exynos5_clk_aclk_400 = {
487 .clk = {
488 .name = "aclk_400",
489 },
490 .sources = &exynos5_clkset_aclk,
491 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
492 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
493};
494
495static struct clk *exynos5_clkset_aclk_333_166_list[] = {
496 [0] = &exynos5_clk_mout_cpll.clk,
497 [1] = &exynos5_clk_mout_mpll_user.clk,
498};
499
500static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
501 .sources = exynos5_clkset_aclk_333_166_list,
502 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
503};
504
505static struct clksrc_clk exynos5_clk_aclk_333 = {
506 .clk = {
507 .name = "aclk_333",
508 },
509 .sources = &exynos5_clkset_aclk_333_166,
510 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
511 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
512};
513
514static struct clksrc_clk exynos5_clk_aclk_166 = {
515 .clk = {
516 .name = "aclk_166",
517 },
518 .sources = &exynos5_clkset_aclk_333_166,
519 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
520 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
521};
522
523static struct clksrc_clk exynos5_clk_aclk_266 = {
524 .clk = {
525 .name = "aclk_266",
526 .parent = &exynos5_clk_mout_mpll_user.clk,
527 },
528 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
529};
530
531static struct clksrc_clk exynos5_clk_aclk_200 = {
532 .clk = {
533 .name = "aclk_200",
534 },
535 .sources = &exynos5_clkset_aclk,
536 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
537 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
538};
539
540static struct clksrc_clk exynos5_clk_aclk_66_pre = {
541 .clk = {
542 .name = "aclk_66_pre",
543 .parent = &exynos5_clk_mout_mpll_user.clk,
544 },
545 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
546};
547
548static struct clksrc_clk exynos5_clk_aclk_66 = {
549 .clk = {
550 .name = "aclk_66",
551 .parent = &exynos5_clk_aclk_66_pre.clk,
552 },
553 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
554};
555
556static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
557 .clk = {
558 .name = "mout_aclk_300_gscl_mid",
559 },
560 .sources = &exynos5_clkset_aclk,
561 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
562};
563
564static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
565 [0] = &exynos5_clk_sclk_vpll.clk,
566 [1] = &exynos5_clk_mout_cpll.clk,
567};
568
569static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
570 .sources = exynos5_clkset_aclk_300_mid1_list,
571 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
572};
573
574static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
575 .clk = {
576 .name = "mout_aclk_300_gscl_mid1",
577 },
578 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
579 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
580};
581
582static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
583 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
584 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
585};
586
587static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
588 .sources = exynos5_clkset_aclk_300_gscl_list,
589 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
590};
591
592static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
593 .clk = {
594 .name = "mout_aclk_300_gscl",
595 },
596 .sources = &exynos5_clkset_aclk_300_gscl,
597 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
598};
599
600static struct clk *exynos5_clk_src_gscl_300_list[] = {
601 [0] = &clk_ext_xtal_mux,
602 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
603};
604
605static struct clksrc_sources exynos5_clk_src_gscl_300 = {
606 .sources = exynos5_clk_src_gscl_300_list,
607 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
608};
609
610static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
611 .clk = {
612 .name = "aclk_300_gscl",
613 },
614 .sources = &exynos5_clk_src_gscl_300,
615 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
616};
617
618static struct clk exynos5_init_clocks_off[] = {
619 {
620 .name = "timers",
621 .parent = &exynos5_clk_aclk_66.clk,
622 .enable = exynos5_clk_ip_peric_ctrl,
623 .ctrlbit = (1 << 24),
624 }, {
625 .name = "tmu_apbif",
626 .parent = &exynos5_clk_aclk_66.clk,
627 .enable = exynos5_clk_ip_peris_ctrl,
628 .ctrlbit = (1 << 21),
629 }, {
630 .name = "rtc",
631 .parent = &exynos5_clk_aclk_66.clk,
632 .enable = exynos5_clk_ip_peris_ctrl,
633 .ctrlbit = (1 << 20),
634 }, {
635 .name = "watchdog",
636 .parent = &exynos5_clk_aclk_66.clk,
637 .enable = exynos5_clk_ip_peris_ctrl,
638 .ctrlbit = (1 << 19),
639 }, {
640 .name = "biu", /* bus interface unit clock */
641 .devname = "dw_mmc.0",
642 .parent = &exynos5_clk_aclk_200.clk,
643 .enable = exynos5_clk_ip_fsys_ctrl,
644 .ctrlbit = (1 << 12),
645 }, {
646 .name = "biu",
647 .devname = "dw_mmc.1",
648 .parent = &exynos5_clk_aclk_200.clk,
649 .enable = exynos5_clk_ip_fsys_ctrl,
650 .ctrlbit = (1 << 13),
651 }, {
652 .name = "biu",
653 .devname = "dw_mmc.2",
654 .parent = &exynos5_clk_aclk_200.clk,
655 .enable = exynos5_clk_ip_fsys_ctrl,
656 .ctrlbit = (1 << 14),
657 }, {
658 .name = "biu",
659 .devname = "dw_mmc.3",
660 .parent = &exynos5_clk_aclk_200.clk,
661 .enable = exynos5_clk_ip_fsys_ctrl,
662 .ctrlbit = (1 << 15),
663 }, {
664 .name = "sata",
665 .devname = "exynos5-sata",
666 .parent = &exynos5_clk_aclk_200.clk,
667 .enable = exynos5_clk_ip_fsys_ctrl,
668 .ctrlbit = (1 << 6),
669 }, {
670 .name = "sata-phy",
671 .devname = "exynos5-sata-phy",
672 .parent = &exynos5_clk_aclk_200.clk,
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 24),
675 }, {
676 .name = "i2c",
677 .devname = "exynos5-sata-phy-i2c",
678 .parent = &exynos5_clk_aclk_200.clk,
679 .enable = exynos5_clk_ip_fsys_ctrl,
680 .ctrlbit = (1 << 25),
681 }, {
682 .name = "mfc",
683 .devname = "s5p-mfc-v6",
684 .enable = exynos5_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 0),
686 }, {
687 .name = "hdmi",
688 .devname = "exynos5-hdmi",
689 .enable = exynos5_clk_ip_disp1_ctrl,
690 .ctrlbit = (1 << 6),
691 }, {
692 .name = "hdmiphy",
693 .devname = "exynos5-hdmi",
694 .enable = exynos5_clk_hdmiphy_ctrl,
695 .ctrlbit = (1 << 0),
696 }, {
697 .name = "mixer",
698 .devname = "exynos5-mixer",
699 .enable = exynos5_clk_ip_disp1_ctrl,
700 .ctrlbit = (1 << 5),
701 }, {
702 .name = "dp",
703 .devname = "exynos-dp",
704 .enable = exynos5_clk_ip_disp1_ctrl,
705 .ctrlbit = (1 << 4),
706 }, {
707 .name = "jpeg",
708 .enable = exynos5_clk_ip_gen_ctrl,
709 .ctrlbit = (1 << 2),
710 }, {
711 .name = "dsim0",
712 .enable = exynos5_clk_ip_disp1_ctrl,
713 .ctrlbit = (1 << 3),
714 }, {
715 .name = "iis",
716 .devname = "samsung-i2s.1",
717 .enable = exynos5_clk_ip_peric_ctrl,
718 .ctrlbit = (1 << 20),
719 }, {
720 .name = "iis",
721 .devname = "samsung-i2s.2",
722 .enable = exynos5_clk_ip_peric_ctrl,
723 .ctrlbit = (1 << 21),
724 }, {
725 .name = "pcm",
726 .devname = "samsung-pcm.1",
727 .enable = exynos5_clk_ip_peric_ctrl,
728 .ctrlbit = (1 << 22),
729 }, {
730 .name = "pcm",
731 .devname = "samsung-pcm.2",
732 .enable = exynos5_clk_ip_peric_ctrl,
733 .ctrlbit = (1 << 23),
734 }, {
735 .name = "spdif",
736 .devname = "samsung-spdif",
737 .enable = exynos5_clk_ip_peric_ctrl,
738 .ctrlbit = (1 << 26),
739 }, {
740 .name = "ac97",
741 .devname = "samsung-ac97",
742 .enable = exynos5_clk_ip_peric_ctrl,
743 .ctrlbit = (1 << 27),
744 }, {
745 .name = "usbhost",
746 .enable = exynos5_clk_ip_fsys_ctrl ,
747 .ctrlbit = (1 << 18),
748 }, {
749 .name = "usbotg",
750 .enable = exynos5_clk_ip_fsys_ctrl,
751 .ctrlbit = (1 << 7),
752 }, {
753 .name = "nfcon",
754 .enable = exynos5_clk_ip_fsys_ctrl,
755 .ctrlbit = (1 << 22),
756 }, {
757 .name = "iop",
758 .enable = exynos5_clk_ip_fsys_ctrl,
759 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
760 }, {
761 .name = "core_iop",
762 .enable = exynos5_clk_ip_core_ctrl,
763 .ctrlbit = ((1 << 21) | (1 << 3)),
764 }, {
765 .name = "mcu_iop",
766 .enable = exynos5_clk_ip_fsys_ctrl,
767 .ctrlbit = (1 << 0),
768 }, {
769 .name = "i2c",
770 .devname = "s3c2440-i2c.0",
771 .parent = &exynos5_clk_aclk_66.clk,
772 .enable = exynos5_clk_ip_peric_ctrl,
773 .ctrlbit = (1 << 6),
774 }, {
775 .name = "i2c",
776 .devname = "s3c2440-i2c.1",
777 .parent = &exynos5_clk_aclk_66.clk,
778 .enable = exynos5_clk_ip_peric_ctrl,
779 .ctrlbit = (1 << 7),
780 }, {
781 .name = "i2c",
782 .devname = "s3c2440-i2c.2",
783 .parent = &exynos5_clk_aclk_66.clk,
784 .enable = exynos5_clk_ip_peric_ctrl,
785 .ctrlbit = (1 << 8),
786 }, {
787 .name = "i2c",
788 .devname = "s3c2440-i2c.3",
789 .parent = &exynos5_clk_aclk_66.clk,
790 .enable = exynos5_clk_ip_peric_ctrl,
791 .ctrlbit = (1 << 9),
792 }, {
793 .name = "i2c",
794 .devname = "s3c2440-i2c.4",
795 .parent = &exynos5_clk_aclk_66.clk,
796 .enable = exynos5_clk_ip_peric_ctrl,
797 .ctrlbit = (1 << 10),
798 }, {
799 .name = "i2c",
800 .devname = "s3c2440-i2c.5",
801 .parent = &exynos5_clk_aclk_66.clk,
802 .enable = exynos5_clk_ip_peric_ctrl,
803 .ctrlbit = (1 << 11),
804 }, {
805 .name = "i2c",
806 .devname = "s3c2440-i2c.6",
807 .parent = &exynos5_clk_aclk_66.clk,
808 .enable = exynos5_clk_ip_peric_ctrl,
809 .ctrlbit = (1 << 12),
810 }, {
811 .name = "i2c",
812 .devname = "s3c2440-i2c.7",
813 .parent = &exynos5_clk_aclk_66.clk,
814 .enable = exynos5_clk_ip_peric_ctrl,
815 .ctrlbit = (1 << 13),
816 }, {
817 .name = "i2c",
818 .devname = "s3c2440-hdmiphy-i2c",
819 .parent = &exynos5_clk_aclk_66.clk,
820 .enable = exynos5_clk_ip_peric_ctrl,
821 .ctrlbit = (1 << 14),
822 }, {
823 .name = "spi",
824 .devname = "exynos4210-spi.0",
825 .parent = &exynos5_clk_aclk_66.clk,
826 .enable = exynos5_clk_ip_peric_ctrl,
827 .ctrlbit = (1 << 16),
828 }, {
829 .name = "spi",
830 .devname = "exynos4210-spi.1",
831 .parent = &exynos5_clk_aclk_66.clk,
832 .enable = exynos5_clk_ip_peric_ctrl,
833 .ctrlbit = (1 << 17),
834 }, {
835 .name = "spi",
836 .devname = "exynos4210-spi.2",
837 .parent = &exynos5_clk_aclk_66.clk,
838 .enable = exynos5_clk_ip_peric_ctrl,
839 .ctrlbit = (1 << 18),
840 }, {
841 .name = "gscl",
842 .devname = "exynos-gsc.0",
843 .enable = exynos5_clk_ip_gscl_ctrl,
844 .ctrlbit = (1 << 0),
845 }, {
846 .name = "gscl",
847 .devname = "exynos-gsc.1",
848 .enable = exynos5_clk_ip_gscl_ctrl,
849 .ctrlbit = (1 << 1),
850 }, {
851 .name = "gscl",
852 .devname = "exynos-gsc.2",
853 .enable = exynos5_clk_ip_gscl_ctrl,
854 .ctrlbit = (1 << 2),
855 }, {
856 .name = "gscl",
857 .devname = "exynos-gsc.3",
858 .enable = exynos5_clk_ip_gscl_ctrl,
859 .ctrlbit = (1 << 3),
860 }, {
861 .name = "sysmmu",
862 .devname = "exynos-sysmmu.1",
863 .enable = &exynos5_clk_ip_mfc_ctrl,
864 .ctrlbit = (1 << 1),
865 }, {
866 .name = "sysmmu",
867 .devname = "exynos-sysmmu.0",
868 .enable = &exynos5_clk_ip_mfc_ctrl,
869 .ctrlbit = (1 << 2),
870 }, {
871 .name = "sysmmu",
872 .devname = "exynos-sysmmu.2",
873 .enable = &exynos5_clk_ip_disp1_ctrl,
874 .ctrlbit = (1 << 9)
875 }, {
876 .name = "sysmmu",
877 .devname = "exynos-sysmmu.3",
878 .enable = &exynos5_clk_ip_gen_ctrl,
879 .ctrlbit = (1 << 7),
880 }, {
881 .name = "sysmmu",
882 .devname = "exynos-sysmmu.4",
883 .enable = &exynos5_clk_ip_gen_ctrl,
884 .ctrlbit = (1 << 6)
885 }, {
886 .name = "sysmmu",
887 .devname = "exynos-sysmmu.5",
888 .enable = &exynos5_clk_ip_gscl_ctrl,
889 .ctrlbit = (1 << 7),
890 }, {
891 .name = "sysmmu",
892 .devname = "exynos-sysmmu.6",
893 .enable = &exynos5_clk_ip_gscl_ctrl,
894 .ctrlbit = (1 << 8),
895 }, {
896 .name = "sysmmu",
897 .devname = "exynos-sysmmu.7",
898 .enable = &exynos5_clk_ip_gscl_ctrl,
899 .ctrlbit = (1 << 9),
900 }, {
901 .name = "sysmmu",
902 .devname = "exynos-sysmmu.8",
903 .enable = &exynos5_clk_ip_gscl_ctrl,
904 .ctrlbit = (1 << 10),
905 }, {
906 .name = "sysmmu",
907 .devname = "exynos-sysmmu.9",
908 .enable = &exynos5_clk_ip_isp0_ctrl,
909 .ctrlbit = (0x3F << 8),
910 }, {
911 .name = "sysmmu",
912 .devname = "exynos-sysmmu.10",
913 .enable = &exynos5_clk_ip_isp1_ctrl,
914 .ctrlbit = (0xF << 4),
915 }, {
916 .name = "sysmmu",
917 .devname = "exynos-sysmmu.11",
918 .enable = &exynos5_clk_ip_disp1_ctrl,
919 .ctrlbit = (1 << 8)
920 }, {
921 .name = "sysmmu",
922 .devname = "exynos-sysmmu.12",
923 .enable = &exynos5_clk_ip_gscl_ctrl,
924 .ctrlbit = (1 << 11),
925 }, {
926 .name = "sysmmu",
927 .devname = "exynos-sysmmu.13",
928 .enable = &exynos5_clk_ip_gscl_ctrl,
929 .ctrlbit = (1 << 12),
930 }, {
931 .name = "sysmmu",
932 .devname = "exynos-sysmmu.14",
933 .enable = &exynos5_clk_ip_acp_ctrl,
934 .ctrlbit = (1 << 7)
935 }
936};
937
938static struct clk exynos5_init_clocks_on[] = {
939 {
940 .name = "uart",
941 .devname = "s5pv210-uart.0",
942 .enable = exynos5_clk_ip_peric_ctrl,
943 .ctrlbit = (1 << 0),
944 }, {
945 .name = "uart",
946 .devname = "s5pv210-uart.1",
947 .enable = exynos5_clk_ip_peric_ctrl,
948 .ctrlbit = (1 << 1),
949 }, {
950 .name = "uart",
951 .devname = "s5pv210-uart.2",
952 .enable = exynos5_clk_ip_peric_ctrl,
953 .ctrlbit = (1 << 2),
954 }, {
955 .name = "uart",
956 .devname = "s5pv210-uart.3",
957 .enable = exynos5_clk_ip_peric_ctrl,
958 .ctrlbit = (1 << 3),
959 }, {
960 .name = "uart",
961 .devname = "s5pv210-uart.4",
962 .enable = exynos5_clk_ip_peric_ctrl,
963 .ctrlbit = (1 << 4),
964 }, {
965 .name = "uart",
966 .devname = "s5pv210-uart.5",
967 .enable = exynos5_clk_ip_peric_ctrl,
968 .ctrlbit = (1 << 5),
969 }
970};
971
972static struct clk exynos5_clk_pdma0 = {
973 .name = "dma",
974 .devname = "dma-pl330.0",
975 .enable = exynos5_clk_ip_fsys_ctrl,
976 .ctrlbit = (1 << 1),
977};
978
979static struct clk exynos5_clk_pdma1 = {
980 .name = "dma",
981 .devname = "dma-pl330.1",
982 .enable = exynos5_clk_ip_fsys_ctrl,
983 .ctrlbit = (1 << 2),
984};
985
986static struct clk exynos5_clk_mdma1 = {
987 .name = "dma",
988 .devname = "dma-pl330.2",
989 .enable = exynos5_clk_ip_gen_ctrl,
990 .ctrlbit = (1 << 4),
991};
992
993static struct clk exynos5_clk_fimd1 = {
994 .name = "fimd",
995 .devname = "exynos5-fb.1",
996 .enable = exynos5_clk_ip_disp1_ctrl,
997 .ctrlbit = (1 << 0),
998};
999
1000static struct clk *exynos5_clkset_group_list[] = {
1001 [0] = &clk_ext_xtal_mux,
1002 [1] = NULL,
1003 [2] = &exynos5_clk_sclk_hdmi24m,
1004 [3] = &exynos5_clk_sclk_dptxphy,
1005 [4] = &exynos5_clk_sclk_usbphy,
1006 [5] = &exynos5_clk_sclk_hdmiphy,
1007 [6] = &exynos5_clk_mout_mpll_user.clk,
1008 [7] = &exynos5_clk_mout_epll.clk,
1009 [8] = &exynos5_clk_sclk_vpll.clk,
1010 [9] = &exynos5_clk_mout_cpll.clk,
1011};
1012
1013static struct clksrc_sources exynos5_clkset_group = {
1014 .sources = exynos5_clkset_group_list,
1015 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
1016};
1017
1018/* Possible clock sources for aclk_266_gscl_sub Mux */
1019static struct clk *clk_src_gscl_266_list[] = {
1020 [0] = &clk_ext_xtal_mux,
1021 [1] = &exynos5_clk_aclk_266.clk,
1022};
1023
1024static struct clksrc_sources clk_src_gscl_266 = {
1025 .sources = clk_src_gscl_266_list,
1026 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
1027};
1028
1029static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1030 .clk = {
1031 .name = "dout_mmc0",
1032 },
1033 .sources = &exynos5_clkset_group,
1034 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1035 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1036};
1037
1038static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1039 .clk = {
1040 .name = "dout_mmc1",
1041 },
1042 .sources = &exynos5_clkset_group,
1043 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1044 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1045};
1046
1047static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1048 .clk = {
1049 .name = "dout_mmc2",
1050 },
1051 .sources = &exynos5_clkset_group,
1052 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1053 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1054};
1055
1056static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1057 .clk = {
1058 .name = "dout_mmc3",
1059 },
1060 .sources = &exynos5_clkset_group,
1061 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1062 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1063};
1064
1065static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1066 .clk = {
1067 .name = "dout_mmc4",
1068 },
1069 .sources = &exynos5_clkset_group,
1070 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1071 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1072};
1073
1074static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1075 .clk = {
1076 .name = "uclk1",
1077 .devname = "exynos4210-uart.0",
1078 .enable = exynos5_clksrc_mask_peric0_ctrl,
1079 .ctrlbit = (1 << 0),
1080 },
1081 .sources = &exynos5_clkset_group,
1082 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1083 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1084};
1085
1086static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1087 .clk = {
1088 .name = "uclk1",
1089 .devname = "exynos4210-uart.1",
1090 .enable = exynos5_clksrc_mask_peric0_ctrl,
1091 .ctrlbit = (1 << 4),
1092 },
1093 .sources = &exynos5_clkset_group,
1094 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1096};
1097
1098static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1099 .clk = {
1100 .name = "uclk1",
1101 .devname = "exynos4210-uart.2",
1102 .enable = exynos5_clksrc_mask_peric0_ctrl,
1103 .ctrlbit = (1 << 8),
1104 },
1105 .sources = &exynos5_clkset_group,
1106 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1107 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1108};
1109
1110static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1111 .clk = {
1112 .name = "uclk1",
1113 .devname = "exynos4210-uart.3",
1114 .enable = exynos5_clksrc_mask_peric0_ctrl,
1115 .ctrlbit = (1 << 12),
1116 },
1117 .sources = &exynos5_clkset_group,
1118 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1119 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1120};
1121
1122static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1123 .clk = {
1124 .name = "ciu", /* card interface unit clock */
1125 .devname = "dw_mmc.0",
1126 .parent = &exynos5_clk_dout_mmc0.clk,
1127 .enable = exynos5_clksrc_mask_fsys_ctrl,
1128 .ctrlbit = (1 << 0),
1129 },
1130 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1131};
1132
1133static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1134 .clk = {
1135 .name = "ciu",
1136 .devname = "dw_mmc.1",
1137 .parent = &exynos5_clk_dout_mmc1.clk,
1138 .enable = exynos5_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 4),
1140 },
1141 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1142};
1143
1144static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1145 .clk = {
1146 .name = "ciu",
1147 .devname = "dw_mmc.2",
1148 .parent = &exynos5_clk_dout_mmc2.clk,
1149 .enable = exynos5_clksrc_mask_fsys_ctrl,
1150 .ctrlbit = (1 << 8),
1151 },
1152 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1153};
1154
1155static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1156 .clk = {
1157 .name = "ciu",
1158 .devname = "dw_mmc.3",
1159 .parent = &exynos5_clk_dout_mmc3.clk,
1160 .enable = exynos5_clksrc_mask_fsys_ctrl,
1161 .ctrlbit = (1 << 12),
1162 },
1163 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1164};
1165
1166static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1167 .clk = {
1168 .name = "mdout_spi",
1169 .devname = "exynos4210-spi.0",
1170 },
1171 .sources = &exynos5_clkset_group,
1172 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1173 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1174};
1175
1176static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1177 .clk = {
1178 .name = "mdout_spi",
1179 .devname = "exynos4210-spi.1",
1180 },
1181 .sources = &exynos5_clkset_group,
1182 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1183 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1184};
1185
1186static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1187 .clk = {
1188 .name = "mdout_spi",
1189 .devname = "exynos4210-spi.2",
1190 },
1191 .sources = &exynos5_clkset_group,
1192 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1193 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1194};
1195
1196static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1197 .clk = {
1198 .name = "sclk_spi",
1199 .devname = "exynos4210-spi.0",
1200 .parent = &exynos5_clk_mdout_spi0.clk,
1201 .enable = exynos5_clksrc_mask_peric1_ctrl,
1202 .ctrlbit = (1 << 16),
1203 },
1204 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1205};
1206
1207static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1208 .clk = {
1209 .name = "sclk_spi",
1210 .devname = "exynos4210-spi.1",
1211 .parent = &exynos5_clk_mdout_spi1.clk,
1212 .enable = exynos5_clksrc_mask_peric1_ctrl,
1213 .ctrlbit = (1 << 20),
1214 },
1215 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1216};
1217
1218static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1219 .clk = {
1220 .name = "sclk_spi",
1221 .devname = "exynos4210-spi.2",
1222 .parent = &exynos5_clk_mdout_spi2.clk,
1223 .enable = exynos5_clksrc_mask_peric1_ctrl,
1224 .ctrlbit = (1 << 24),
1225 },
1226 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1227};
1228
1229static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1230 .clk = {
1231 .name = "sclk_fimd",
1232 .devname = "exynos5-fb.1",
1233 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1234 .ctrlbit = (1 << 0),
1235 },
1236 .sources = &exynos5_clkset_group,
1237 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1238 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1239};
1240
1241static struct clksrc_clk exynos5_clksrcs[] = {
1242 {
1243 .clk = {
1244 .name = "aclk_266_gscl",
1245 },
1246 .sources = &clk_src_gscl_266,
1247 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1248 }, {
1249 .clk = {
1250 .name = "sclk_g3d",
1251 .devname = "mali-t604.0",
1252 .enable = exynos5_clk_block_ctrl,
1253 .ctrlbit = (1 << 1),
1254 },
1255 .sources = &exynos5_clkset_aclk,
1256 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1257 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1258 }, {
1259 .clk = {
1260 .name = "sclk_sata",
1261 .devname = "exynos5-sata",
1262 .enable = exynos5_clksrc_mask_fsys_ctrl,
1263 .ctrlbit = (1 << 24),
1264 },
1265 .sources = &exynos5_clkset_aclk,
1266 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1267 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1268 }, {
1269 .clk = {
1270 .name = "sclk_gscl_wrap",
1271 .devname = "s5p-mipi-csis.0",
1272 .enable = exynos5_clksrc_mask_gscl_ctrl,
1273 .ctrlbit = (1 << 24),
1274 },
1275 .sources = &exynos5_clkset_group,
1276 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1277 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1278 }, {
1279 .clk = {
1280 .name = "sclk_gscl_wrap",
1281 .devname = "s5p-mipi-csis.1",
1282 .enable = exynos5_clksrc_mask_gscl_ctrl,
1283 .ctrlbit = (1 << 28),
1284 },
1285 .sources = &exynos5_clkset_group,
1286 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1287 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1288 }, {
1289 .clk = {
1290 .name = "sclk_cam0",
1291 .enable = exynos5_clksrc_mask_gscl_ctrl,
1292 .ctrlbit = (1 << 16),
1293 },
1294 .sources = &exynos5_clkset_group,
1295 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1296 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1297 }, {
1298 .clk = {
1299 .name = "sclk_cam1",
1300 .enable = exynos5_clksrc_mask_gscl_ctrl,
1301 .ctrlbit = (1 << 20),
1302 },
1303 .sources = &exynos5_clkset_group,
1304 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1305 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1306 }, {
1307 .clk = {
1308 .name = "sclk_jpeg",
1309 .parent = &exynos5_clk_mout_cpll.clk,
1310 },
1311 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1312 },
1313};
1314
1315/* Clock initialization code */
1316static struct clksrc_clk *exynos5_sysclks[] = {
1317 &exynos5_clk_mout_apll,
1318 &exynos5_clk_sclk_apll,
1319 &exynos5_clk_mout_bpll,
1320 &exynos5_clk_mout_bpll_fout,
1321 &exynos5_clk_mout_bpll_user,
1322 &exynos5_clk_mout_cpll,
1323 &exynos5_clk_mout_epll,
1324 &exynos5_clk_mout_mpll,
1325 &exynos5_clk_mout_mpll_fout,
1326 &exynos5_clk_mout_mpll_user,
1327 &exynos5_clk_vpllsrc,
1328 &exynos5_clk_sclk_vpll,
1329 &exynos5_clk_mout_cpu,
1330 &exynos5_clk_dout_armclk,
1331 &exynos5_clk_dout_arm2clk,
1332 &exynos5_clk_cdrex,
1333 &exynos5_clk_aclk_400,
1334 &exynos5_clk_aclk_333,
1335 &exynos5_clk_aclk_266,
1336 &exynos5_clk_aclk_200,
1337 &exynos5_clk_aclk_166,
1338 &exynos5_clk_aclk_300_gscl,
1339 &exynos5_clk_mout_aclk_300_gscl,
1340 &exynos5_clk_mout_aclk_300_gscl_mid,
1341 &exynos5_clk_mout_aclk_300_gscl_mid1,
1342 &exynos5_clk_aclk_66_pre,
1343 &exynos5_clk_aclk_66,
1344 &exynos5_clk_dout_mmc0,
1345 &exynos5_clk_dout_mmc1,
1346 &exynos5_clk_dout_mmc2,
1347 &exynos5_clk_dout_mmc3,
1348 &exynos5_clk_dout_mmc4,
1349 &exynos5_clk_aclk_acp,
1350 &exynos5_clk_pclk_acp,
1351 &exynos5_clk_sclk_spi0,
1352 &exynos5_clk_sclk_spi1,
1353 &exynos5_clk_sclk_spi2,
1354 &exynos5_clk_mdout_spi0,
1355 &exynos5_clk_mdout_spi1,
1356 &exynos5_clk_mdout_spi2,
1357 &exynos5_clk_sclk_fimd1,
1358};
1359
1360static struct clk *exynos5_clk_cdev[] = {
1361 &exynos5_clk_pdma0,
1362 &exynos5_clk_pdma1,
1363 &exynos5_clk_mdma1,
1364 &exynos5_clk_fimd1,
1365};
1366
1367static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1368 &exynos5_clk_sclk_uart0,
1369 &exynos5_clk_sclk_uart1,
1370 &exynos5_clk_sclk_uart2,
1371 &exynos5_clk_sclk_uart3,
1372 &exynos5_clk_sclk_mmc0,
1373 &exynos5_clk_sclk_mmc1,
1374 &exynos5_clk_sclk_mmc2,
1375 &exynos5_clk_sclk_mmc3,
1376};
1377
1378static struct clk_lookup exynos5_clk_lookup[] = {
1379 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1380 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1381 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1382 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1383 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1384 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1385 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1386 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1387 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1388 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1389 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1390 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1391 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1392 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1393 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1394};
1395
1396static unsigned long exynos5_epll_get_rate(struct clk *clk)
1397{
1398 return clk->rate;
1399}
1400
1401static struct clk *exynos5_clks[] __initdata = {
1402 &exynos5_clk_sclk_hdmi27m,
1403 &exynos5_clk_sclk_hdmiphy,
1404 &clk_fout_bpll,
1405 &clk_fout_bpll_div2,
1406 &clk_fout_cpll,
1407 &clk_fout_mpll_div2,
1408 &exynos5_clk_armclk,
1409};
1410
1411static u32 epll_div[][6] = {
1412 { 192000000, 0, 48, 3, 1, 0 },
1413 { 180000000, 0, 45, 3, 1, 0 },
1414 { 73728000, 1, 73, 3, 3, 47710 },
1415 { 67737600, 1, 90, 4, 3, 20762 },
1416 { 49152000, 0, 49, 3, 3, 9961 },
1417 { 45158400, 0, 45, 3, 3, 10381 },
1418 { 180633600, 0, 45, 3, 1, 10381 },
1419};
1420
1421static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1422{
1423 unsigned int epll_con, epll_con_k;
1424 unsigned int i;
1425 unsigned int tmp;
1426 unsigned int epll_rate;
1427 unsigned int locktime;
1428 unsigned int lockcnt;
1429
1430 /* Return if nothing changed */
1431 if (clk->rate == rate)
1432 return 0;
1433
1434 if (clk->parent)
1435 epll_rate = clk_get_rate(clk->parent);
1436 else
1437 epll_rate = clk_ext_xtal_mux.rate;
1438
1439 if (epll_rate != 24000000) {
1440 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1441 return -EINVAL;
1442 }
1443
1444 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1445 epll_con &= ~(0x1 << 27 | \
1446 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1447 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1448 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1449
1450 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1451 if (epll_div[i][0] == rate) {
1452 epll_con_k = epll_div[i][5] << 0;
1453 epll_con |= epll_div[i][1] << 27;
1454 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1455 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1456 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1457 break;
1458 }
1459 }
1460
1461 if (i == ARRAY_SIZE(epll_div)) {
1462 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1463 __func__);
1464 return -EINVAL;
1465 }
1466
1467 epll_rate /= 1000000;
1468
1469 /* 3000 max_cycls : specification data */
1470 locktime = 3000 / epll_rate * epll_div[i][3];
1471 lockcnt = locktime * 10000 / (10000 / epll_rate);
1472
1473 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1474
1475 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1476 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1477
1478 do {
1479 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1480 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1481
1482 clk->rate = rate;
1483
1484 return 0;
1485}
1486
1487static struct clk_ops exynos5_epll_ops = {
1488 .get_rate = exynos5_epll_get_rate,
1489 .set_rate = exynos5_epll_set_rate,
1490};
1491
1492static int xtal_rate;
1493
1494static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1495{
1496 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1497}
1498
1499static struct clk_ops exynos5_fout_apll_ops = {
1500 .get_rate = exynos5_fout_apll_get_rate,
1501};
1502
1503#ifdef CONFIG_PM
1504static int exynos5_clock_suspend(void)
1505{
1506 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1507
1508 return 0;
1509}
1510
1511static void exynos5_clock_resume(void)
1512{
1513 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1514}
1515#else
1516#define exynos5_clock_suspend NULL
1517#define exynos5_clock_resume NULL
1518#endif
1519
1520static struct syscore_ops exynos5_clock_syscore_ops = {
1521 .suspend = exynos5_clock_suspend,
1522 .resume = exynos5_clock_resume,
1523};
1524
1525void __init_or_cpufreq exynos5_setup_clocks(void)
1526{
1527 struct clk *xtal_clk;
1528 unsigned long apll;
1529 unsigned long bpll;
1530 unsigned long cpll;
1531 unsigned long mpll;
1532 unsigned long epll;
1533 unsigned long vpll;
1534 unsigned long vpllsrc;
1535 unsigned long xtal;
1536 unsigned long armclk;
1537 unsigned long mout_cdrex;
1538 unsigned long aclk_400;
1539 unsigned long aclk_333;
1540 unsigned long aclk_266;
1541 unsigned long aclk_200;
1542 unsigned long aclk_166;
1543 unsigned long aclk_66;
1544 unsigned int ptr;
1545
1546 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1547
1548 xtal_clk = clk_get(NULL, "xtal");
1549 BUG_ON(IS_ERR(xtal_clk));
1550
1551 xtal = clk_get_rate(xtal_clk);
1552
1553 xtal_rate = xtal;
1554
1555 clk_put(xtal_clk);
1556
1557 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1558
1559 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1560 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1561 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1562 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1563 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1564 __raw_readl(EXYNOS5_EPLL_CON1));
1565
1566 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1567 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1568 __raw_readl(EXYNOS5_VPLL_CON1));
1569
1570 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1571 clk_fout_bpll.rate = bpll;
1572 clk_fout_bpll_div2.rate = bpll >> 1;
1573 clk_fout_cpll.rate = cpll;
1574 clk_fout_mpll.rate = mpll;
1575 clk_fout_mpll_div2.rate = mpll >> 1;
1576 clk_fout_epll.rate = epll;
1577 clk_fout_vpll.rate = vpll;
1578
1579 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1580 "M=%ld, E=%ld V=%ld",
1581 apll, bpll, cpll, mpll, epll, vpll);
1582
1583 armclk = clk_get_rate(&exynos5_clk_armclk);
1584 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1585
1586 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1587 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1588 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1589 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1590 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1591 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1592
1593 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1594 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1595 "ACLK166=%ld, ACLK66=%ld\n",
1596 armclk, mout_cdrex, aclk_400,
1597 aclk_333, aclk_266, aclk_200,
1598 aclk_166, aclk_66);
1599
1600
1601 clk_fout_epll.ops = &exynos5_epll_ops;
1602
1603 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1604 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1605 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1606
1607 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1608 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1609
1610 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1611 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1612
1613 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1614 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1615}
1616
1617void __init exynos5_register_clocks(void)
1618{
1619 int ptr;
1620
1621 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1622
1623 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1624 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1625
1626 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1627 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1628
1629 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1630 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1631
1632 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1633 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1634
1635 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1636 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1637 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1638
1639 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1640 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1641 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1642
1643 register_syscore_ops(&exynos5_clock_syscore_ops);
1644 s3c_pwmclk_init();
1645}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f91dad6fe9a3..f4e8222bc3c4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -39,7 +39,6 @@
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40 40
41#include <plat/cpu.h> 41#include <plat/cpu.h>
42#include <plat/clock.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/pm.h> 43#include <plat/pm.h>
45#include <plat/sdhci.h> 44#include <plat/sdhci.h>
@@ -65,8 +64,6 @@ static const char name_exynos5440[] = "EXYNOS5440";
65static void exynos4_map_io(void); 64static void exynos4_map_io(void);
66static void exynos5_map_io(void); 65static void exynos5_map_io(void);
67static void exynos5440_map_io(void); 66static void exynos5440_map_io(void);
68static void exynos4_init_clocks(int xtal);
69static void exynos5_init_clocks(int xtal);
70static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); 67static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
71static int exynos_init(void); 68static int exynos_init(void);
72 69
@@ -75,7 +72,6 @@ static struct cpu_table cpu_ids[] __initdata = {
75 .idcode = EXYNOS4210_CPU_ID, 72 .idcode = EXYNOS4210_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK, 73 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io, 74 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts, 75 .init_uarts = exynos4_init_uarts,
80 .init = exynos_init, 76 .init = exynos_init,
81 .name = name_exynos4210, 77 .name = name_exynos4210,
@@ -83,7 +79,6 @@ static struct cpu_table cpu_ids[] __initdata = {
83 .idcode = EXYNOS4212_CPU_ID, 79 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK, 80 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io, 81 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos4_init_uarts, 82 .init_uarts = exynos4_init_uarts,
88 .init = exynos_init, 83 .init = exynos_init,
89 .name = name_exynos4212, 84 .name = name_exynos4212,
@@ -91,7 +86,6 @@ static struct cpu_table cpu_ids[] __initdata = {
91 .idcode = EXYNOS4412_CPU_ID, 86 .idcode = EXYNOS4412_CPU_ID,
92 .idmask = EXYNOS4_CPU_MASK, 87 .idmask = EXYNOS4_CPU_MASK,
93 .map_io = exynos4_map_io, 88 .map_io = exynos4_map_io,
94 .init_clocks = exynos4_init_clocks,
95 .init_uarts = exynos4_init_uarts, 89 .init_uarts = exynos4_init_uarts,
96 .init = exynos_init, 90 .init = exynos_init,
97 .name = name_exynos4412, 91 .name = name_exynos4412,
@@ -99,7 +93,6 @@ static struct cpu_table cpu_ids[] __initdata = {
99 .idcode = EXYNOS5250_SOC_ID, 93 .idcode = EXYNOS5250_SOC_ID,
100 .idmask = EXYNOS5_SOC_MASK, 94 .idmask = EXYNOS5_SOC_MASK,
101 .map_io = exynos5_map_io, 95 .map_io = exynos5_map_io,
102 .init_clocks = exynos5_init_clocks,
103 .init = exynos_init, 96 .init = exynos_init,
104 .name = name_exynos5250, 97 .name = name_exynos5250,
105 }, { 98 }, {
@@ -397,45 +390,11 @@ static void __init exynos5_map_io(void)
397 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); 390 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
398} 391}
399 392
400static void __init exynos4_init_clocks(int xtal)
401{
402 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
403
404 s3c24xx_register_baseclocks(xtal);
405 s5p_register_clocks(xtal);
406
407 if (soc_is_exynos4210())
408 exynos4210_register_clocks();
409 else if (soc_is_exynos4212() || soc_is_exynos4412())
410 exynos4212_register_clocks();
411
412 exynos4_register_clocks();
413 exynos4_setup_clocks();
414}
415
416static void __init exynos5440_map_io(void) 393static void __init exynos5440_map_io(void)
417{ 394{
418 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); 395 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
419} 396}
420 397
421static void __init exynos5_init_clocks(int xtal)
422{
423 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
424
425 /* EXYNOS5440 can support only common clock framework */
426
427 if (soc_is_exynos5440())
428 return;
429
430#ifdef CONFIG_SOC_EXYNOS5250
431 s3c24xx_register_baseclocks(xtal);
432 s5p_register_clocks(xtal);
433
434 exynos5_register_clocks();
435 exynos5_setup_clocks();
436#endif
437}
438
439void __init exynos4_init_irq(void) 398void __init exynos4_init_irq(void)
440{ 399{
441 unsigned int gic_bank_offset; 400 unsigned int gic_bank_offset;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 3b186eaaaa7b..ec4098e984b8 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,10 @@
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H 12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H 13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14 14
15#include <linux/of.h>
16
15extern void mct_init(void); 17extern void mct_init(void);
18void exynos_init_time(void);
16 19
17struct map_desc; 20struct map_desc;
18void exynos_init_io(struct map_desc *mach_desc, int size); 21void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +25,10 @@ void exynos4_restart(char mode, const char *cmd);
22void exynos5_restart(char mode, const char *cmd); 25void exynos5_restart(char mode, const char *cmd);
23void exynos_init_late(void); 26void exynos_init_late(void);
24 27
28/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
29void exynos4_clk_init(struct device_node *np);
30void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
31
25#ifdef CONFIG_PM_GENERIC_DOMAINS 32#ifdef CONFIG_PM_GENERIC_DOMAINS
26int exynos_pm_late_initcall(void); 33int exynos_pm_late_initcall(void);
27#else 34#else
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d36ad76ad6a4..20fbbdddd105 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -256,113 +256,6 @@
256#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) 256#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
257#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) 257#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
258 258
259/* For EXYNOS5250 */
260
261#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
262#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
263#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
264#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
265#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
266#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
267#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
268#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
269
270#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
271#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
272
273#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
274#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
275
276#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
277
278#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
279
280#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
281#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
282#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
283#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
284#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
285#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
286#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
287
288#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
289#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
290#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
291#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
292#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
293#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
294#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
295#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
296#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
297#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
298#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
299
300#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
301#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
302#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
303#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
304#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
305#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
306#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
307
308#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
309#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
310#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
311#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
312#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
313#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
314#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
315#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
316#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
317#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
318#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
319#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
320#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
321#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
322#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
323#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
324#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
325
326#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
327#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
328#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
329#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
330#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
331#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
332#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
333#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
334#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
335#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
336#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
337#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
338#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
339
340#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
341#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
342#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
343
344#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
345
346#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
347
348#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
349
350#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
351#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
352#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
353#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
354#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
355#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
356#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
357#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
358
359#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
360#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
361#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
362#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
363#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
364#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
365
366/* Compatibility defines and inclusion */ 259/* Compatibility defines and inclusion */
367 260
368#include <mach/regs-pmu.h> 261#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 3b1a34742679..376d6964e4aa 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
177static void __init armlex4210_map_io(void) 177static void __init armlex4210_map_io(void)
178{ 178{
179 exynos_init_io(NULL, 0); 179 exynos_init_io(NULL, 0);
180 s3c24xx_init_clocks(24000000);
181 s3c24xx_init_uarts(armlex4210_uartcfgs, 180 s3c24xx_init_uarts(armlex4210_uartcfgs,
182 ARRAY_SIZE(armlex4210_uartcfgs)); 181 ARRAY_SIZE(armlex4210_uartcfgs));
183} 182}
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index daa7b0da9a2d..e1f714647e50 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -124,7 +124,6 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
124static void __init exynos4_dt_map_io(void) 124static void __init exynos4_dt_map_io(void)
125{ 125{
126 exynos_init_io(NULL, 0); 126 exynos_init_io(NULL, 0);
127 s3c24xx_init_clocks(24000000);
128} 127}
129 128
130static void __init exynos4_dt_machine_init(void) 129static void __init exynos4_dt_machine_init(void)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 62d43dacf636..06b2e9596cdf 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -152,12 +152,7 @@ static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
152 152
153static void __init exynos5_dt_map_io(void) 153static void __init exynos5_dt_map_io(void)
154{ 154{
155 unsigned long root = of_get_flat_dt_root();
156
157 exynos_init_io(NULL, 0); 155 exynos_init_io(NULL, 0);
158
159 if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
160 s3c24xx_init_clocks(24000000);
161} 156}
162 157
163static void __init exynos5_dt_machine_init(void) 158static void __init exynos5_dt_machine_init(void)
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index da3605d15110..8ddbceb5ccc3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1330,7 +1330,6 @@ static struct platform_device *nuri_devices[] __initdata = {
1330static void __init nuri_map_io(void) 1330static void __init nuri_map_io(void)
1331{ 1331{
1332 exynos_init_io(NULL, 0); 1332 exynos_init_io(NULL, 0);
1333 s3c24xx_init_clocks(clk_xusbxti.rate);
1334 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1333 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
1335} 1334}
1336 1335
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 1772cd284f4c..620d60c8fbb5 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -754,7 +754,6 @@ static void s5p_tv_setup(void)
754static void __init origen_map_io(void) 754static void __init origen_map_io(void)
755{ 755{
756 exynos_init_io(NULL, 0); 756 exynos_init_io(NULL, 0);
757 s3c24xx_init_clocks(clk_xusbxti.rate);
758 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 757 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
759} 758}
760 759
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 34a6356364eb..63ee1b1a8263 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
322static void __init smdk4x12_map_io(void) 322static void __init smdk4x12_map_io(void)
323{ 323{
324 exynos_init_io(NULL, 0); 324 exynos_init_io(NULL, 0);
325 s3c24xx_init_clocks(clk_xusbxti.rate);
326 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 325 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
327} 326}
328 327
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 893b14e8c62a..51fa235b4dc9 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -371,7 +371,6 @@ static void s5p_tv_setup(void)
371static void __init smdkv310_map_io(void) 371static void __init smdkv310_map_io(void)
372{ 372{
373 exynos_init_io(NULL, 0); 373 exynos_init_io(NULL, 0);
374 s3c24xx_init_clocks(clk_xusbxti.rate);
375 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 374 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
376} 375}
377 376
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index c870b0aaa5e0..4e6e8cef5cbf 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1092,7 +1092,6 @@ static struct platform_device *universal_devices[] __initdata = {
1092static void __init universal_map_io(void) 1092static void __init universal_map_io(void)
1093{ 1093{
1094 exynos_init_io(NULL, 0); 1094 exynos_init_io(NULL, 0);
1095 s3c24xx_init_clocks(clk_xusbxti.rate);
1096 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 1095 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
1097 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); 1096 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
1098} 1097}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b708b3e56d27..6cb19c6aa9d6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
25 select PLAT_SAMSUNG 25 select PLAT_SAMSUNG
26 select S3C_GPIO_TRACK 26 select S3C_GPIO_TRACK
27 select S5P_GPIO_DRVSTR 27 select S5P_GPIO_DRVSTR
28 select SAMSUNG_CLKSRC 28 select SAMSUNG_CLKSRC if !COMMON_CLK
29 select SAMSUNG_GPIOLIB_4BIT 29 select SAMSUNG_GPIOLIB_4BIT
30 select SAMSUNG_IRQ_VIC_TIMER 30 select SAMSUNG_IRQ_VIC_TIMER
31 help 31 help
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
89 used by newer systems such as the S3C64XX. 89 used by newer systems such as the S3C64XX.
90 90
91config S5P_CLOCK 91config S5P_CLOCK
92 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 92 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
93 help 93 help
94 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs 94 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
95 95
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:57:10 -0500