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authorMichal Simek <monstr@monstr.eu>2012-12-27 04:40:38 -0500
committerMichal Simek <michal.simek@xilinx.com>2013-02-12 05:24:45 -0500
commit6bd55f0bbaebb79b39e147aa864401fd0c94db82 (patch)
treeeffef6e85fcbb6bd2687d881758a48c2377ef18e /arch
parent5b3084b5823339ac7bebca0701b9b89defe11c91 (diff)
microblaze: Fix coding style issues
Fix coding style issues reported by checkpatch.pl. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch')
-rw-r--r--arch/microblaze/include/asm/io.h2
-rw-r--r--arch/microblaze/kernel/cpu/cache.c148
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c21
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c13
-rw-r--r--arch/microblaze/kernel/cpu/pvr.c2
-rw-r--r--arch/microblaze/kernel/dma.c6
-rw-r--r--arch/microblaze/kernel/early_printk.c17
-rw-r--r--arch/microblaze/kernel/exceptions.c25
-rw-r--r--arch/microblaze/kernel/ftrace.c44
-rw-r--r--arch/microblaze/kernel/heartbeat.c2
-rw-r--r--arch/microblaze/kernel/intc.c4
-rw-r--r--arch/microblaze/kernel/kgdb.c2
-rw-r--r--arch/microblaze/kernel/module.c3
-rw-r--r--arch/microblaze/kernel/process.c22
-rw-r--r--arch/microblaze/kernel/ptrace.c2
-rw-r--r--arch/microblaze/kernel/setup.c28
-rw-r--r--arch/microblaze/kernel/signal.c6
-rw-r--r--arch/microblaze/kernel/sys_microblaze.c1
-rw-r--r--arch/microblaze/kernel/traps.c6
-rw-r--r--arch/microblaze/lib/ashldi3.c1
-rw-r--r--arch/microblaze/lib/ashrdi3.c1
-rw-r--r--arch/microblaze/lib/lshrdi3.c1
-rw-r--r--arch/microblaze/lib/memcpy.c10
-rw-r--r--arch/microblaze/lib/memmove.c9
-rw-r--r--arch/microblaze/mm/consistent.c5
-rw-r--r--arch/microblaze/mm/fault.c10
-rw-r--r--arch/microblaze/mm/init.c32
-rw-r--r--arch/microblaze/mm/pgtable.c15
-rw-r--r--arch/microblaze/pci/indirect_pci.c2
-rw-r--r--arch/microblaze/pci/iomap.c2
-rw-r--r--arch/microblaze/pci/pci-common.c95
-rw-r--r--arch/microblaze/pci/xilinx_pci.c16
32 files changed, 259 insertions, 294 deletions
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 4fbfdc1ac7f8..8cb8a8566ede 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -150,7 +150,7 @@ static inline void writel(unsigned int v, volatile void __iomem *addr)
150#define page_to_bus(page) (page_to_phys(page)) 150#define page_to_bus(page) (page_to_phys(page))
151#define bus_to_virt(addr) (phys_to_virt(addr)) 151#define bus_to_virt(addr) (phys_to_virt(addr))
152 152
153extern void iounmap(void *addr); 153extern void iounmap(void __iomem *addr);
154/*extern void *__ioremap(phys_addr_t address, unsigned long size, 154/*extern void *__ioremap(phys_addr_t address, unsigned long size,
155 unsigned long flags);*/ 155 unsigned long flags);*/
156extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 156extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index 4b7d8a3f4aef..4254514b4c8c 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -17,82 +17,70 @@
17 17
18static inline void __enable_icache_msr(void) 18static inline void __enable_icache_msr(void)
19{ 19{
20 __asm__ __volatile__ (" msrset r0, %0; \ 20 __asm__ __volatile__ (" msrset r0, %0;" \
21 nop; " \ 21 "nop;" \
22 : : "i" (MSR_ICE) : "memory"); 22 : : "i" (MSR_ICE) : "memory");
23} 23}
24 24
25static inline void __disable_icache_msr(void) 25static inline void __disable_icache_msr(void)
26{ 26{
27 __asm__ __volatile__ (" msrclr r0, %0; \ 27 __asm__ __volatile__ (" msrclr r0, %0;" \
28 nop; " \ 28 "nop;" \
29 : : "i" (MSR_ICE) : "memory"); 29 : : "i" (MSR_ICE) : "memory");
30} 30}
31 31
32static inline void __enable_dcache_msr(void) 32static inline void __enable_dcache_msr(void)
33{ 33{
34 __asm__ __volatile__ (" msrset r0, %0; \ 34 __asm__ __volatile__ (" msrset r0, %0;" \
35 nop; " \ 35 "nop;" \
36 : \ 36 : : "i" (MSR_DCE) : "memory");
37 : "i" (MSR_DCE) \
38 : "memory");
39} 37}
40 38
41static inline void __disable_dcache_msr(void) 39static inline void __disable_dcache_msr(void)
42{ 40{
43 __asm__ __volatile__ (" msrclr r0, %0; \ 41 __asm__ __volatile__ (" msrclr r0, %0;" \
44 nop; " \ 42 "nop; " \
45 : \ 43 : : "i" (MSR_DCE) : "memory");
46 : "i" (MSR_DCE) \
47 : "memory");
48} 44}
49 45
50static inline void __enable_icache_nomsr(void) 46static inline void __enable_icache_nomsr(void)
51{ 47{
52 __asm__ __volatile__ (" mfs r12, rmsr; \ 48 __asm__ __volatile__ (" mfs r12, rmsr;" \
53 nop; \ 49 "nop;" \
54 ori r12, r12, %0; \ 50 "ori r12, r12, %0;" \
55 mts rmsr, r12; \ 51 "mts rmsr, r12;" \
56 nop; " \ 52 "nop;" \
57 : \ 53 : : "i" (MSR_ICE) : "memory", "r12");
58 : "i" (MSR_ICE) \
59 : "memory", "r12");
60} 54}
61 55
62static inline void __disable_icache_nomsr(void) 56static inline void __disable_icache_nomsr(void)
63{ 57{
64 __asm__ __volatile__ (" mfs r12, rmsr; \ 58 __asm__ __volatile__ (" mfs r12, rmsr;" \
65 nop; \ 59 "nop;" \
66 andi r12, r12, ~%0; \ 60 "andi r12, r12, ~%0;" \
67 mts rmsr, r12; \ 61 "mts rmsr, r12;" \
68 nop; " \ 62 "nop;" \
69 : \ 63 : : "i" (MSR_ICE) : "memory", "r12");
70 : "i" (MSR_ICE) \
71 : "memory", "r12");
72} 64}
73 65
74static inline void __enable_dcache_nomsr(void) 66static inline void __enable_dcache_nomsr(void)
75{ 67{
76 __asm__ __volatile__ (" mfs r12, rmsr; \ 68 __asm__ __volatile__ (" mfs r12, rmsr;" \
77 nop; \ 69 "nop;" \
78 ori r12, r12, %0; \ 70 "ori r12, r12, %0;" \
79 mts rmsr, r12; \ 71 "mts rmsr, r12;" \
80 nop; " \ 72 "nop;" \
81 : \ 73 : : "i" (MSR_DCE) : "memory", "r12");
82 : "i" (MSR_DCE) \
83 : "memory", "r12");
84} 74}
85 75
86static inline void __disable_dcache_nomsr(void) 76static inline void __disable_dcache_nomsr(void)
87{ 77{
88 __asm__ __volatile__ (" mfs r12, rmsr; \ 78 __asm__ __volatile__ (" mfs r12, rmsr;" \
89 nop; \ 79 "nop;" \
90 andi r12, r12, ~%0; \ 80 "andi r12, r12, ~%0;" \
91 mts rmsr, r12; \ 81 "mts rmsr, r12;" \
92 nop; " \ 82 "nop;" \
93 : \ 83 : : "i" (MSR_DCE) : "memory", "r12");
94 : "i" (MSR_DCE) \
95 : "memory", "r12");
96} 84}
97 85