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authorRalf Baechle <ralf@linux-mips.org>2013-09-17 04:25:47 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-09-17 12:50:53 -0400
commit69f24d1784b631b81a54eb57c49bf46536dd2382 (patch)
tree93c05469adbeb6bd24ab06b11d5f906a879e2c11 /arch
parentff522058bd717506b2fa066fa564657f2b86477e (diff)
MIPS: Optimize current_cpu_type() for better code.
o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c1
-rw-r--r--arch/mips/dec/prom/init.c1
-rw-r--r--arch/mips/include/asm/cpu-features.h6
-rw-r--r--arch/mips/include/asm/cpu-type.h203
-rw-r--r--arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h2
-rw-r--r--arch/mips/kernel/cpu-probe.c3
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/kernel/time.c1
-rw-r--r--arch/mips/kernel/traps.c3
-rw-r--r--arch/mips/mm/c-octeon.c6
-rw-r--r--arch/mips/mm/c-r4k.c14
-rw-r--r--arch/mips/mm/dma-default.c1
-rw-r--r--arch/mips/mm/page.c1
-rw-r--r--arch/mips/mm/sc-mips.c3
-rw-r--r--arch/mips/mm/tlb-r4k.c1
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/mips/oprofile/common.c1
19 files changed, 236 insertions, 19 deletions
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 02193953eb9e..b752c4ed0b79 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -12,6 +12,7 @@
12#include <linux/smp.h> 12#include <linux/smp.h>
13 13
14#include <asm/cpu-info.h> 14#include <asm/cpu-info.h>
15#include <asm/cpu-type.h>
15#include <asm/time.h> 16#include <asm/time.h>
16 17
17#include <asm/octeon/octeon.h> 18#include <asm/octeon/octeon.h>
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index ab169046e442..468f665de7bb 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15#include <asm/cpu.h> 15#include <asm/cpu.h>
16#include <asm/cpu-type.h>
16#include <asm/processor.h> 17#include <asm/processor.h>
17 18
18#include <asm/dec/prom.h> 19#include <asm/dec/prom.h>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index fa44f3ec5302..51680d15ca8e 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -13,12 +13,6 @@
13#include <asm/cpu-info.h> 13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h> 14#include <cpu-feature-overrides.h>
15 15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
20#define boot_cpu_type() cpu_data[0].cputype
21
22/* 16/*
23 * SMP assumption: Options of CPU 0 are a superset of all processors. 17 * SMP assumption: Options of CPU 0 are a superset of all processors.
24 * This is true for all known MIPS systems. 18 * This is true for all known MIPS systems.
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
new file mode 100644
index 000000000000..4a402cc60c03
--- /dev/null
+++ b/arch/mips/include/asm/cpu-type.h
@@ -0,0 +1,203 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_TYPE_H
10#define __ASM_CPU_TYPE_H
11
12#include <linux/smp.h>
13#include <linux/compiler.h>
14
15static inline int __pure __get_cpu_type(const int cpu_type)
16{
17 switch (cpu_type) {
18#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
19 defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
20 case CPU_LOONGSON2:
21#endif
22
23#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
24 case CPU_LOONGSON1:
25#endif
26
27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28 case CPU_4KC:
29 case CPU_ALCHEMY:
30 case CPU_BMIPS3300:
31 case CPU_BMIPS4350:
32 case CPU_PR4450:
33 case CPU_BMIPS32:
34 case CPU_JZRISC:
35#endif
36
37#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
38 defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
39 case CPU_4KEC:
40#endif
41
42#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
43 case CPU_4KSC:
44 case CPU_24K:
45 case CPU_34K:
46 case CPU_1004K:
47 case CPU_74K:
48 case CPU_M14KC:
49 case CPU_M14KEC:
50#endif
51
52#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
53 case CPU_5KC:
54 case CPU_5KE:
55 case CPU_20KC:
56 case CPU_25KF:
57 case CPU_SB1:
58 case CPU_SB1A:
59#endif
60
61#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
62 /*
63 * All MIPS64 R2 processors have their own special symbols. That is,
64 * there currently is no pure R2 core
65 */
66#endif
67
68#ifdef CONFIG_SYS_HAS_CPU_R3000
69 case CPU_R2000:
70 case CPU_R3000:
71 case CPU_R3000A:
72 case CPU_R3041:
73 case CPU_R3051:
74 case CPU_R3052:
75 case CPU_R3081:
76 case CPU_R3081E:
77#endif
78
79#ifdef CONFIG_SYS_HAS_CPU_TX39XX
80 case CPU_TX3912:
81 case CPU_TX3922:
82 case CPU_TX3927:
83#endif
84
85#ifdef CONFIG_SYS_HAS_CPU_VR41XX
86 case CPU_VR41XX:
87 case CPU_VR4111:
88 case CPU_VR4121:
89 case CPU_VR4122:
90 case CPU_VR4131:
91 case CPU_VR4133:
92 case CPU_VR4181:
93 case CPU_VR4181A:
94#endif
95
96#ifdef CONFIG_SYS_HAS_CPU_R4300
97 case CPU_R4300:
98 case CPU_R4310:
99#endif
100
101#ifdef CONFIG_SYS_HAS_CPU_R4X00
102 case CPU_R4000PC:
103 case CPU_R4000SC:
104 case CPU_R4000MC:
105 case CPU_R4200:
106 case CPU_R4400PC:
107 case CPU_R4400SC:
108 case CPU_R4400MC:
109 case CPU_R4600:
110 case CPU_R4700:
111 case CPU_R4640:
112 case CPU_R4650:
113#endif
114
115#ifdef CONFIG_SYS_HAS_CPU_TX49XX
116 case CPU_TX49XX:
117#endif
118
119#ifdef CONFIG_SYS_HAS_CPU_R5000
120 case CPU_R5000:
121#endif
122
123#ifdef CONFIG_SYS_HAS_CPU_R5432
124 case CPU_R5432:
125#endif
126
127#ifdef CONFIG_SYS_HAS_CPU_R5500
128 case CPU_R5500:
129#endif
130
131#ifdef CONFIG_SYS_HAS_CPU_R6000
132 case CPU_R6000:
133 case CPU_R6000A:
134#endif
135
136#ifdef CONFIG_SYS_HAS_CPU_NEVADA
137 case CPU_NEVADA:
138#endif
139
140#ifdef CONFIG_SYS_HAS_CPU_R8000
141 case CPU_R8000:
142#endif
143
144#ifdef CONFIG_SYS_HAS_CPU_R10000
145 case CPU_R10000:
146 case CPU_R12000:
147 case CPU_R14000:
148#endif
149#ifdef CONFIG_SYS_HAS_CPU_RM7000
150 case CPU_RM7000:
151 case CPU_SR71000:
152#endif
153#ifdef CONFIG_SYS_HAS_CPU_RM9000
154 case CPU_RM9000:
155#endif
156#ifdef CONFIG_SYS_HAS_CPU_SB1
157 case CPU_SB1:
158 case CPU_SB1A:
159#endif
160#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
161 case CPU_CAVIUM_OCTEON:
162 case CPU_CAVIUM_OCTEON_PLUS:
163 case CPU_CAVIUM_OCTEON2:
164#endif
165
166#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167 case CPU_BMIPS4380:
168#endif
169
170#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
171 case CPU_BMIPS5000:
172#endif
173
174#ifdef CONFIG_SYS_HAS_CPU_XLP
175 case CPU_XLP:
176#endif
177
178#ifdef CONFIG_SYS_HAS_CPU_XLR
179 case CPU_XLR:
180#endif
181 break;
182 default:
183 unreachable();
184 }
185
186 return cpu_type;
187}
188
189static inline int __pure current_cpu_type(void)
190{
191 const int cpu_type = current_cpu_data.cputype;
192
193 return __get_cpu_type(cpu_type);
194}
195
196static inline int __pure boot_cpu_type(void)
197{
198 const int cpu_type = cpu_data[0].cputype;
199
200 return __get_cpu_type(cpu_type);
201}
202
203#endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index f4caacd25552..1bcb6421205e 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP22 with a variety of processors so we can't use defaults for everything. 14 * IP22 with a variety of processors so we can't use defaults for everything.
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 1d2b6ff60d33..d6111aa2e886 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP27 only comes with R10000 family processors all using the same config 14 * IP27 only comes with R10000 family processors all using the same config
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 65e9c856390d..4cec06d133db 100644
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -9,6 +9,8 @@
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11 11
12#include <asm/cpu.h>
13
12/* 14/*
13 * IP28 only comes with R10000 family processors all using the same config 15 * IP28 only comes with R10000 family processors all using the same config
14 */ 16 */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 37663c7862a5..9ef2b049d3c0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/bugs.h> 21#include <asm/bugs.h>
22#include <asm/cpu.h> 22#include <asm/cpu.h>
23#include <asm/cpu-type.h>
23#include <asm/fpu.h> 24#include <asm/fpu.h>
24#include <asm/mipsregs.h> 25#include <asm/mipsregs.h>
25#include <asm/watch.h> 26#include <asm/watch.h>
@@ -55,7 +56,7 @@ static inline void check_errata(void)
55{ 56{
56 struct cpuinfo_mips *c = &current_cpu_data; 57 struct cpuinfo_mips *c = &current_cpu_data;
57 58
58 switch (c->cputype) { 59 switch (current_cpu_type()) {
59 case CPU_34K: 60 case CPU_34K:
60 /* 61 /*
61 * Erratum "RPS May Cause Incorrect Instruction Execution" 62 * Erratum "RPS May Cause Incorrect Instruction Execution"
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 42f8875d2444..f7991d95bff9 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -18,6 +18,7 @@
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <asm/cpu.h> 19#include <asm/cpu.h>
20#include <asm/cpu-info.h> 20#include <asm/cpu-info.h>
21#include <asm/cpu-type.h>
21#include <asm/idle.h> 22#include <asm/idle.h>
22#include <asm/mipsregs.h> 23#include <asm/mipsregs.h>
23 24
@@ -136,7 +137,7 @@ void __init check_wait(void)
136 return; 137 return;
137 } 138 }
138 139
139 switch (c->cputype) { 140 switch (current_cpu_type()) {
140 case CPU_R3081: 141 case CPU_R3081:
141 case CPU_R3081E: 142 case CPU_R3081E:
142 cpu_wait = r3081_wait; 143 cpu_wait = r3081_wait;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 364d26ae4215..dcb8e5d3bb8a 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -24,6 +24,7 @@
24#include <linux/export.h> 24#include <linux/export.h>
25 25
26#include <asm/cpu-features.h> 26#include <asm/cpu-features.h>
27#include <asm/cpu-type.h>
27#include <asm/div64.h> 28#include <asm/div64.h>
28#include <asm/smtc_ipi.h> 29#include <asm/smtc_ipi.h>
29#include <asm/time.h> 30#include <asm/time.h>
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index aec3408edd4b..524841f02803 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -39,6 +39,7 @@
39#include <asm/break.h> 39#include <asm/break.h>
40#include <asm/cop2.h> 40#include <asm/cop2.h>
41#include <asm/cpu.h> 41#include <asm/cpu.h>
42#include <asm/cpu-type.h>
42#include <asm/dsp.h> 43#include <asm/dsp.h>
43#include <asm/fpu.h> 44#include <asm/fpu.h>
44#include <asm/fpu_emulator.h> 45#include <asm/fpu_emulator.h>
@@ -622,7 +623,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
622 regs->regs[rt] = read_c0_count(); 623 regs->regs[rt] = read_c0_count();
623 return 0; 624 return 0;
624 case 3: /* Count register resolution */ 625 case 3: /* Count register resolution */
625 switch (current_cpu_data.cputype) { 626 switch (current_cpu_type()) {
626 case CPU_20KC: 627 case CPU_20KC:
627 case CPU_25KF: 628 case CPU_25KF:
628 regs->regs[rt] = 1; 629 regs->regs[rt] = 1;
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 729e7702b1de..c8efdb5b6ee0 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -19,6 +19,7 @@
19#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
20#include <asm/cacheops.h> 20#include <asm/cacheops.h>
21#include <asm/cpu-features.h> 21#include <asm/cpu-features.h>
22#include <asm/cpu-type.h>
22#include <asm/page.h> 23#include <asm/page.h>
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/r4kcache.h> 25#include <asm/r4kcache.h>
@@ -186,9 +187,10 @@ static void probe_octeon(void)
186 unsigned long dcache_size; 187 unsigned long dcache_size;
187 unsigned int config1; 188 unsigned int config1;
188 struct cpuinfo_mips *c = &current_cpu_data; 189 struct cpuinfo_mips *c = &current_cpu_data;
190 int cputype = current_cpu_type();
189 191
190 config1 = read_c0_config1(); 192 config1 = read_c0_config1();
191 switch (c->cputype) { 193 switch (cputype) {
192 case CPU_CAVIUM_OCTEON: 194 case CPU_CAVIUM_OCTEON:
193 case CPU_CAVIUM_OCTEON_PLUS: 195 case CPU_CAVIUM_OCTEON_PLUS:
194 c->icache.linesz = 2 << ((config1 >> 19) & 7); 196 c->icache.linesz = 2 << ((config1 >> 19) & 7);
@@ -199,7 +201,7 @@ static void probe_octeon(void)
199 c->icache.sets * c->icache.ways * c->icache.linesz; 201 c->icache.sets * c->icache.ways * c->icache.linesz;
200 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; 202 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
201 c->dcache.linesz = 128; 203 c->dcache.linesz = 128;
202 if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) 204 if (cputype == CPU_CAVIUM_OCTEON_PLUS)
203 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ 205 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
204 else 206 else
205 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ 207 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 40dced23e768..73ca8c52e83f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -25,6 +25,7 @@
25#include <asm/cacheops.h> 25#include <asm/cacheops.h>
26#include <asm/cpu.h> 26#include <asm/cpu.h>
27#include <asm/cpu-features.h> 27#include <asm/cpu-features.h>
28#include <asm/cpu-type.h>
28#include <asm/io.h> 29#include <asm/io.h>
29#include <asm/page.h> 30#include <asm/page.h>
30#include <asm/pgtable.h> 31#include <asm/pgtable.h>
@@ -814,7 +815,7 @@ static void probe_pcache(void)
814 unsigned long config1; 815 unsigned long config1;
815 unsigned int lsize; 816 unsigned int lsize;
816 817
817 switch (c->cputype) { 818 switch (current_cpu_type()) {
818 case CPU_R4600: /* QED style two way caches? */ 819 case CPU_R4600: /* QED style two way caches? */
819 case CPU_R4700: 820 case CPU_R4700:
820 case CPU_R5000: 821 case CPU_R5000:
@@ -1050,7 +1051,7 @@ static void probe_pcache(void)
1050 * normally they'd suffer from aliases but magic in the hardware deals 1051 * normally they'd suffer from aliases but magic in the hardware deals
1051 * with that for us so we don't need to take care ourselves. 1052 * with that for us so we don't need to take care ourselves.
1052 */ 1053 */
1053 switch (c->cputype) { 1054 switch (current_cpu_type()) {
1054 case CPU_20KC: 1055 case CPU_20KC:
1055 case CPU_25KF: 1056 case CPU_25KF:
1056 case CPU_SB1: 1057 case CPU_SB1:
@@ -1070,7 +1071,7 @@ static void probe_pcache(void)
1070 case CPU_34K: 1071 case CPU_34K:
1071 case CPU_74K: 1072 case CPU_74K:
1072 case CPU_1004K: 1073 case CPU_1004K:
1073 if (c->cputype == CPU_74K) 1074 if (current_cpu_type() == CPU_74K)
1074 alias_74k_erratum(c); 1075 alias_74k_erratum(c);
1075 if ((read_c0_config7() & (1 << 16))) { 1076 if ((read_c0_config7() & (1 << 16))) {
1076 /* effectively physically indexed dcache, 1077 /* effectively physically indexed dcache,
@@ -1083,7 +1084,7 @@ static void probe_pcache(void)
1083 c->dcache.flags |= MIPS_CACHE_ALIASES; 1084 c->dcache.flags |= MIPS_CACHE_ALIASES;
1084 } 1085 }
1085 1086
1086 switch (c->cputype) { 1087 switch (current_cpu_type()) {
1087 case CPU_20KC: 1088 case CPU_20KC:
1088 /* 1089 /*
1089 * Some older 20Kc chips doesn't have the 'VI' bit in 1090 * Some older 20Kc chips doesn't have the 'VI' bit in
@@ -1212,7 +1213,7 @@ static void setup_scache(void)
1212 * processors don't have a S-cache that would be relevant to the 1213 * processors don't have a S-cache that would be relevant to the
1213 * Linux memory management. 1214 * Linux memory management.
1214 */ 1215 */
1215 switch (c->cputype) { 1216 switch (current_cpu_type()) {
1216 case CPU_R4000SC: 1217 case CPU_R4000SC:
1217 case CPU_R4000MC: 1218 case CPU_R4000MC:
1218 case CPU_R4400SC: 1219 case CPU_R4400SC:
@@ -1389,9 +1390,8 @@ static void r4k_cache_error_setup(void)
1389{ 1390{
1390 extern char __weak except_vec2_generic; 1391 extern char __weak except_vec2_generic;
1391 extern char __weak except_vec2_sb1; 1392 extern char __weak except_vec2_sb1;
1392 struct cpuinfo_mips *c = &current_cpu_data;
1393 1393
1394 switch (c->cputype) { 1394 switch (current_cpu_type()) {
1395 case CPU_SB1: 1395 case CPU_SB1:
1396 case CPU_SB1A: 1396 case CPU_SB1A:
1397 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1397 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 664e523653d0..f25a7e9f8cbc 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
18#include <linux/highmem.h> 18#include <linux/highmem.h>
19 19
20#include <asm/cache.h> 20#include <asm/cache.h>
21#include <asm/cpu-type.h>
21#include <asm/io.h> 22#include <asm/io.h>
22 23
23#include <dma-coherence.h> 24#include <dma-coherence.h>
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 218c2109a55d..cbd81d17793a 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -18,6 +18,7 @@
18 18
19#include <asm/bugs.h> 19#include <asm/bugs.h>
20#include <asm/cacheops.h> 20#include <asm/cacheops.h>
21#include <asm/cpu-type.h>
21#include <asm/inst.h> 22#include <asm/inst.h>
22#include <asm/io.h> 23#include <asm/io.h>
23#include <asm/page.h> 24#include <asm/page.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5d01392e3518..08d05aee8788 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -6,6 +6,7 @@
6#include <linux/sched.h> 6#include <linux/sched.h>
7#include <linux/mm.h> 7#include <linux/mm.h>
8 8
9#include <asm/cpu-type.h>
9#include <asm/mipsregs.h> 10#include <asm/mipsregs.h>
10#include <asm/bcache.h> 11#include <asm/bcache.h>
11#include <asm/cacheops.h> 12#include <asm/cacheops.h>
@@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
71 unsigned int tmp; 72 unsigned int tmp;
72 73
73 /* Check the bypass bit (L2B) */ 74 /* Check the bypass bit (L2B) */
74 switch (c->cputype) { 75 switch (current_cpu_type()) {
75 case CPU_34K: 76 case CPU_34K:
76 case CPU_74K: 77 case CPU_74K:
77 case CPU_1004K: 78 case CPU_1004K:
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 00b26a67a06d..bb3a5f643e97 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -16,6 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17 17
18#include <asm/cpu.h> 18#include <asm/cpu.h>
19#include <asm/cpu-type.h>
19#include <asm/bootinfo.h> 20#include <asm/bootinfo.h>
20#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 821b45175dc1..9bb3a9363b06 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -30,6 +30,7 @@
30#include <linux/cache.h> 30#include <linux/cache.h>
31 31
32#include <asm/cacheflush.h> 32#include <asm/cacheflush.h>
33#include <asm/cpu-type.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/war.h> 35#include <asm/war.h>
35#include <asm/uasm.h> 36#include <asm/uasm.h>
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 5e5424753b56..4d1736fc1955 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -12,6 +12,7 @@
12#include <linux/oprofile.h> 12#include <linux/oprofile.h>
13#include <linux/smp.h> 13#include <linux/smp.h>
14#include <asm/cpu-info.h> 14#include <asm/cpu-info.h>
15#include <asm/cpu-type.h>
15 16
16#include "op_impl.h" 17#include "op_impl.h"
17 18