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authorDinh Nguyen <dinguyen@altera.com>2012-07-18 18:07:18 -0400
committerArnd Bergmann <arnd@arndb.de>2012-07-19 04:39:00 -0400
commit66314223aa5e862c9d1d068cb7186b4fd58ebeaa (patch)
treec1d825523095ce89c079f7dad536d448b890838c /arch
parent31a985f5bdc7e0708fc2cf02fac06c74664a7910 (diff)
ARM: socfpga: initial support for Altera's SOCFPGA platform
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig19
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi147
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts34
-rw-r--r--arch/arm/configs/socfpga_defconfig83
-rw-r--r--arch/arm/mach-socfpga/Makefile5
-rw-r--r--arch/arm/mach-socfpga/Makefile.boot1
-rw-r--r--arch/arm/mach-socfpga/include/mach/debug-macro.S16
-rw-r--r--arch/arm/mach-socfpga/include/mach/timex.h19
-rw-r--r--arch/arm/mach-socfpga/include/mach/uncompress.h9
-rw-r--r--arch/arm/mach-socfpga/socfpga.c62
11 files changed, 396 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7e3d9317c0bf..dfeca559d700 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -250,6 +250,25 @@ choice
250 prompt "ARM system type" 250 prompt "ARM system type"
251 default ARCH_VERSATILE 251 default ARCH_VERSATILE
252 252
253config ARCH_SOCFPGA
254 bool "Altera SOCFPGA family"
255 select ARCH_WANT_OPTIONAL_GPIOLIB
256 select ARM_AMBA
257 select ARM_GIC
258 select CACHE_L2X0
259 select CLKDEV_LOOKUP
260 select COMMON_CLK
261 select CPU_V7
262 select DW_APB_TIMER
263 select DW_APB_TIMER_OF
264 select GENERIC_CLOCKEVENTS
265 select GPIO_PL061 if GPIOLIB
266 select HAVE_ARM_SCU
267 select SPARSE_IRQ
268 select USE_OF
269 help
270 This enables support for Altera SOCFPGA Cyclone V platform
271
253config ARCH_INTEGRATOR 272config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family" 273 bool "ARM Ltd. Integrator family"
255 select ARM_AMBA 274 select ARM_AMBA
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f1a1a7170103..4d6d31115cf2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
187machine-$(CONFIG_ARCH_VT8500) := vt8500 187machine-$(CONFIG_ARCH_VT8500) := vt8500
188machine-$(CONFIG_ARCH_W90X900) := w90x900 188machine-$(CONFIG_ARCH_W90X900) := w90x900
189machine-$(CONFIG_FOOTBRIDGE) := footbridge 189machine-$(CONFIG_FOOTBRIDGE) := footbridge
190machine-$(CONFIG_ARCH_SOCFPGA) := socfpga
190machine-$(CONFIG_MACH_SPEAR1310) := spear13xx 191machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
191machine-$(CONFIG_MACH_SPEAR1340) := spear13xx 192machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
192machine-$(CONFIG_MACH_SPEAR300) := spear3xx 193machine-$(CONFIG_MACH_SPEAR300) := spear3xx
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 000000000000..0772f5739f59
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "skeleton.dtsi"
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 intc: intc@fffed000 {
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
52 reg = <0xfffed000 0x1000>,
53 <0xfffec100 0x100>;
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 device_type = "soc";
61 interrupt-parent = <&intc>;
62 ranges;
63
64 amba {
65 compatible = "arm,amba-bus";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
70 pdma: pdma@ffe01000 {
71 compatible = "arm,pl330", "arm,primecell";
72 reg = <0xffe01000 0x1000>;
73 interrupts = <0 180 4>;
74 };
75 };
76
77 gmac0: stmmac@ff700000 {
78 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
79 reg = <0xff700000 0x2000>;
80 interrupts = <0 115 4>;
81 interrupt-names = "macirq";
82 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
83 phy-mode = "gmii";
84 };
85
86 L2: l2-cache@fffef000 {
87 compatible = "arm,pl310-cache";
88 reg = <0xfffef000 0x1000>;
89 interrupts = <0 38 0x04>;
90 cache-unified;
91 cache-level = <2>;
92 };
93
94 /* Local timer */
95 timer@fffec600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0xfffec600 0x100>;
98 interrupts = <1 13 0xf04>;
99 };
100
101 timer0: timer@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>;
106 };
107
108 timer1: timer@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>;
113 };
114
115 timer2: timer@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>;
120 };
121
122 timer3: timer@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>;
127 };
128
129 uart0: uart@ffc02000 {
130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>;
134 reg-shift = <2>;
135 reg-io-width = <4>;
136 };
137
138 uart1: uart@ffc03000 {
139 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>;
143 reg-shift = <2>;
144 reg-io-width = <4>;
145 };
146 };
147};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644
index 000000000000..ab7e4a94299f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
20
21/ {
22 model = "Altera SOCFPGA Cyclone V";
23 compatible = "altr,socfpga-cyclone5";
24
25 chosen {
26 bootargs = "console=ttyS0,57600";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x10000000>; /* 256MB */
33 };
34};
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644
index 000000000000..0ac1293dba10
--- /dev/null
+++ b/arch/arm/configs/socfpga_defconfig
@@ -0,0 +1,83 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_CGROUPS=y
7CONFIG_CPUSETS=y
8CONFIG_NAMESPACES=y
9CONFIG_EMBEDDED=y
10CONFIG_PROFILING=y
11CONFIG_OPROFILE=y
12CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y
14# CONFIG_LBDAF is not set
15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SOCFPGA=y
19CONFIG_MACH_SOCFPGA_CYCLONE5=y
20CONFIG_ARM_THUMBEE=y
21# CONFIG_CACHE_L2X0 is not set
22CONFIG_HIGH_RES_TIMERS=y
23CONFIG_VMSPLIT_2G=y
24CONFIG_NR_CPUS=2
25CONFIG_AEABI=y
26CONFIG_ZBOOT_ROM_TEXT=0x0
27CONFIG_ZBOOT_ROM_BSS=0x0
28CONFIG_CMDLINE=""
29CONFIG_VFP=y
30CONFIG_NEON=y
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_NET_KEY=y
35CONFIG_NET_KEY_MIGRATE=y
36CONFIG_INET=y
37CONFIG_IP_MULTICAST=y
38CONFIG_IP_PNP=y
39CONFIG_IP_PNP_DHCP=y
40CONFIG_IP_PNP_BOOTP=y
41CONFIG_IP_PNP_RARP=y
42CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
43CONFIG_DEVTMPFS=y
44CONFIG_PROC_DEVICETREE=y
45CONFIG_BLK_DEV_RAM=y
46CONFIG_BLK_DEV_RAM_COUNT=2
47CONFIG_BLK_DEV_RAM_SIZE=8192
48CONFIG_SCSI=y
49# CONFIG_SCSI_PROC_FS is not set
50CONFIG_BLK_DEV_SD=y
51# CONFIG_SCSI_LOWLEVEL is not set
52CONFIG_NETDEVICES=y
53CONFIG_STMMAC_ETH=y
54# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
55CONFIG_INPUT_EVDEV=y
56# CONFIG_SERIO_SERPORT is not set
57CONFIG_SERIO_AMBAKMI=y
58CONFIG_LEGACY_PTY_COUNT=16
59CONFIG_SERIAL_8250=y
60CONFIG_SERIAL_8250_CONSOLE=y
61CONFIG_SERIAL_8250_NR_UARTS=2
62CONFIG_SERIAL_8250_RUNTIME_UARTS=2
63CONFIG_SERIAL_8250_DW=y
64# CONFIG_RTC_HCTOSYS is not set
65CONFIG_EXT2_FS=y
66CONFIG_EXT2_FS_XATTR=y
67CONFIG_EXT2_FS_POSIX_ACL=y
68# CONFIG_DNOTIFY is not set
69# CONFIG_INOTIFY_USER is not set
70CONFIG_VFAT_FS=y
71CONFIG_NTFS_FS=y
72CONFIG_NTFS_RW=y
73CONFIG_TMPFS=y
74CONFIG_JFFS2_FS=y
75CONFIG_NLS_CODEPAGE_437=y
76CONFIG_NLS_ISO8859_1=y
77CONFIG_MAGIC_SYSRQ=y
78CONFIG_DETECT_HUNG_TASK=y
79# CONFIG_SCHED_DEBUG is not set
80CONFIG_DEBUG_INFO=y
81CONFIG_ENABLE_DEFAULT_TRACERS=y
82CONFIG_DEBUG_USER=y
83CONFIG_XZ_DEC=y
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 000000000000..4fb93240971d
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := socfpga.o
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
new file mode 100644
index 000000000000..dae9661a7689
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile.boot
@@ -0,0 +1 @@
zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d6f26d23374f
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 1994-1999 Russell King
3 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 .macro addruart, rp, rv, tmp
11 mov \rp, #DEBUG_LL_UART_OFFSET
12 orr \rp, \rp, #0x00c00000
13 orr \rv, \rp, #0xfe000000 @ virtual base
14 orr \rp, \rp, #0xff000000 @ physical base
15 .endm
16
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h
new file mode 100644
index 000000000000..43df4354e461
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/timex.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (C) 2003 ARM Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
new file mode 100644
index 000000000000..bbe20e696325
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/uncompress.h
@@ -0,0 +1,9 @@
1#ifndef __MACH_UNCOMPRESS_H
2#define __MACH_UNCOMPRESS_H
3
4#define putc(c)
5#define flush()
6#define arch_decomp_setup()
7#define arch_decomp_wdog()
8
9#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
new file mode 100644
index 000000000000..f01e1ebf5396
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2012 Altera Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/dw_apb_timer.h>
18#include <linux/of_irq.h>
19#include <linux/of_platform.h>
20
21#include <asm/hardware/cache-l2x0.h>
22#include <asm/hardware/gic.h>
23#include <asm/mach/arch.h>
24
25extern void socfpga_init_clocks(void);
26
27const static struct of_device_id irq_match[] = {
28 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
29 {}
30};
31
32static void __init gic_init_irq(void)
33{
34 of_irq_init(irq_match);
35}
36
37static void socfpga_cyclone5_restart(char mode, const char *cmd)
38{
39 /* TODO: */
40}
41
42static void __init socfpga_cyclone5_init(void)
43{
44 l2x0_of_init(0, ~0UL);
45 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
46 socfpga_init_clocks();
47}
48
49static const char *altera_dt_match[] = {
50 "altr,socfpga",
51 "altr,socfpga-cyclone5",
52 NULL
53};
54
55DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
56 .init_irq = gic_init_irq,
57 .handle_irq = gic_handle_irq,
58 .timer = &dw_apb_timer,
59 .init_machine = socfpga_cyclone5_init,
60 .restart = socfpga_cyclone5_restart,
61 .dt_compat = altera_dt_match,
62MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 04:26:51 -0400